drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Flow control default high water */
  99 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 100
 101 /* Flow control default low water */
 102 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 257 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 259 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 260 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_stats *stats);
 262 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 263                                struct rte_eth_xstat *xstats, unsigned n);
 264 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 265                                      struct rte_eth_xstat_name *xstats_names,
 266                                      unsigned limit);
 267 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 268 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id,
 270                                             uint8_t stat_idx,
 271                                             uint8_t is_rx);
 272 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 273                                 char *fw_version, size_t fw_size);
 274 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 275                               struct rte_eth_dev_info *dev_info);
 276 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 277                                 uint16_t vlan_id,
 278                                 int on);
 279 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 280                               enum rte_vlan_type vlan_type,
 281                               uint16_t tpid);
 282 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 283 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 284                                       uint16_t queue,
 285                                       int on);
 286 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 287 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 288 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 289 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 292                               struct rte_eth_fc_conf *fc_conf);
 293 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 294                                        struct rte_eth_pfc_conf *pfc_conf);
 295 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 296                             struct ether_addr *mac_addr,
 297                             uint32_t index,
 298                             uint32_t pool);
 299 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 300 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 301                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                     uint16_t reta_size);
 303 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 304                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 305                                    uint16_t reta_size);
 306
 307 static int i40e_get_cap(struct i40e_hw *hw);
 308 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 309 static int i40e_pf_setup(struct i40e_pf *pf);
 310 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 311 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 312 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 313 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 314 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 315                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 316 static void i40e_stat_update_48(struct i40e_hw *hw,
 317                                uint32_t hireg,
 318                                uint32_t loreg,
 319                                bool offset_loaded,
 320                                uint64_t *offset,
 321                                uint64_t *stat);
 322 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 323 static void i40e_dev_interrupt_handler(void *param);
 324 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 325                                 uint32_t base, uint32_t num);
 326 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 327 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 328                         uint32_t base);
 329 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 330                         uint16_t num);
 331 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 332 static int i40e_veb_release(struct i40e_veb *veb);
 333 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 334                                                 struct i40e_vsi *vsi);
 335 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 336 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 337 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 338                                              struct i40e_macvlan_filter *mv_f,
 339                                              int num,
 340                                              uint16_t vlan);
 341 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 342 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 343                                     struct rte_eth_rss_conf *rss_conf);
 344 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 345                                       struct rte_eth_rss_conf *rss_conf);
 346 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 347                                         struct rte_eth_udp_tunnel *udp_tunnel);
 348 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 349                                         struct rte_eth_udp_tunnel *udp_tunnel);
 350 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 351 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 352                                 enum rte_filter_op filter_op,
 353                                 void *arg);
 354 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 355                                 enum rte_filter_type filter_type,
 356                                 enum rte_filter_op filter_op,
 357                                 void *arg);
 358 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 359                                   struct rte_eth_dcb_info *dcb_info);
 360 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 361 static void i40e_configure_registers(struct i40e_hw *hw);
 362 static void i40e_hw_init(struct rte_eth_dev *dev);
 363 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 364 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 365                                                      uint16_t seid,
 366                                                      uint16_t rule_type,
 367                                                      uint16_t *entries,
 368                                                      uint16_t count,
 369                                                      uint16_t rule_id);
 370 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 371                         struct rte_eth_mirror_conf *mirror_conf,
 372                         uint8_t sw_id, uint8_t on);
 373 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 374
 375 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 376 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 377 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp,
 379                                            uint32_t flags);
 380 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 381                                            struct timespec *timestamp);
 382 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 383
 384 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 385
 386 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 387                                    struct timespec *timestamp);
 388 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 389                                     const struct timespec *timestamp);
 390
 391 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 392                                          uint16_t queue_id);
 393 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 394                                           uint16_t queue_id);
 395
 396 static int i40e_get_regs(struct rte_eth_dev *dev,
 397                          struct rte_dev_reg_info *regs);
 398
 399 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 400
 401 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 402                            struct rte_dev_eeprom_info *eeprom);
 403
 404 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 405                                       struct ether_addr *mac_addr);
 406
 407 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 408
 409 static int i40e_ethertype_filter_convert(
 410         const struct rte_eth_ethertype_filter *input,
 411         struct i40e_ethertype_filter *filter);
 412 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 413                                    struct i40e_ethertype_filter *filter);
 414
 415 static int i40e_tunnel_filter_convert(
 416         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 417         struct i40e_tunnel_filter *tunnel_filter);
 418 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 419                                 struct i40e_tunnel_filter *tunnel_filter);
 420 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 421
 422 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 423 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 424 static void i40e_filter_restore(struct i40e_pf *pf);
 425 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 426
 427 int i40e_logtype_init;
 428 int i40e_logtype_driver;
 429
 430 static const struct rte_pci_id pci_id_i40e_map[] = {
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 449         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 450         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 451         { .vendor_id = 0, /* sentinel */ },
 452 };
 453
 454 static const struct eth_dev_ops i40e_eth_dev_ops = {
 455         .dev_configure                = i40e_dev_configure,
 456         .dev_start                    = i40e_dev_start,
 457         .dev_stop                     = i40e_dev_stop,
 458         .dev_close                    = i40e_dev_close,
 459         .dev_reset                    = i40e_dev_reset,
 460         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 461         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 462         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 463         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 464         .dev_set_link_up              = i40e_dev_set_link_up,
 465         .dev_set_link_down            = i40e_dev_set_link_down,
 466         .link_update                  = i40e_dev_link_update,
 467         .stats_get                    = i40e_dev_stats_get,
 468         .xstats_get                   = i40e_dev_xstats_get,
 469         .xstats_get_names             = i40e_dev_xstats_get_names,
 470         .stats_reset                  = i40e_dev_stats_reset,
 471         .xstats_reset                 = i40e_dev_stats_reset,
 472         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 473         .fw_version_get               = i40e_fw_version_get,
 474         .dev_infos_get                = i40e_dev_info_get,
 475         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 476         .vlan_filter_set              = i40e_vlan_filter_set,
 477         .vlan_tpid_set                = i40e_vlan_tpid_set,
 478         .vlan_offload_set             = i40e_vlan_offload_set,
 479         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 480         .vlan_pvid_set                = i40e_vlan_pvid_set,
 481         .rx_queue_start               = i40e_dev_rx_queue_start,
 482         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 483         .tx_queue_start               = i40e_dev_tx_queue_start,
 484         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 485         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 486         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 487         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 488         .rx_queue_release             = i40e_dev_rx_queue_release,
 489         .rx_queue_count               = i40e_dev_rx_queue_count,
 490         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 491         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 492         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 493         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 494         .tx_queue_release             = i40e_dev_tx_queue_release,
 495         .dev_led_on                   = i40e_dev_led_on,
 496         .dev_led_off                  = i40e_dev_led_off,
 497         .flow_ctrl_get                = i40e_flow_ctrl_get,
 498         .flow_ctrl_set                = i40e_flow_ctrl_set,
 499         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 500         .mac_addr_add                 = i40e_macaddr_add,
 501         .mac_addr_remove              = i40e_macaddr_remove,
 502         .reta_update                  = i40e_dev_rss_reta_update,
 503         .reta_query                   = i40e_dev_rss_reta_query,
 504         .rss_hash_update              = i40e_dev_rss_hash_update,
 505         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 506         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 507         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 508         .filter_ctrl                  = i40e_dev_filter_ctrl,
 509         .rxq_info_get                 = i40e_rxq_info_get,
 510         .txq_info_get                 = i40e_txq_info_get,
 511         .mirror_rule_set              = i40e_mirror_rule_set,
 512         .mirror_rule_reset            = i40e_mirror_rule_reset,
 513         .timesync_enable              = i40e_timesync_enable,
 514         .timesync_disable             = i40e_timesync_disable,
 515         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 516         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 517         .get_dcb_info                 = i40e_dev_get_dcb_info,
 518         .timesync_adjust_time         = i40e_timesync_adjust_time,
 519         .timesync_read_time           = i40e_timesync_read_time,
 520         .timesync_write_time          = i40e_timesync_write_time,
 521         .get_reg                      = i40e_get_regs,
 522         .get_eeprom_length            = i40e_get_eeprom_length,
 523         .get_eeprom                   = i40e_get_eeprom,
 524         .mac_addr_set                 = i40e_set_default_mac_addr,
 525         .mtu_set                      = i40e_dev_mtu_set,
 526         .tm_ops_get                   = i40e_tm_ops_get,
 527 };
 528
 529 /* store statistics names and its offset in stats structure */
 530 struct rte_i40e_xstats_name_off {
 531         char name[RTE_ETH_XSTATS_NAME_SIZE];
 532         unsigned offset;
 533 };
 534
 535 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 536         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 537         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 538         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 539         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 540         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 541                 rx_unknown_protocol)},
 542         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 543         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 544         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 545         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 546 };
 547
 548 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 549                 sizeof(rte_i40e_stats_strings[0]))
 550
 551 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 552         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 553                 tx_dropped_link_down)},
 554         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 555         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 556                 illegal_bytes)},
 557         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 558         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 559                 mac_local_faults)},
 560         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 561                 mac_remote_faults)},
 562         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 563                 rx_length_errors)},
 564         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 565         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 566         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 567         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 568         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 569         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_127)},
 571         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_255)},
 573         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_511)},
 575         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_1023)},
 577         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_1522)},
 579         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 580                 rx_size_big)},
 581         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_undersize)},
 583         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_oversize)},
 585         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 586                 mac_short_packet_dropped)},
 587         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 588                 rx_fragments)},
 589         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 590         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 591         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_127)},
 593         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_255)},
 595         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_511)},
 597         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_1023)},
 599         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_1522)},
 601         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 tx_size_big)},
 603         {"rx_flow_director_atr_match_packets",
 604                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 605         {"rx_flow_director_sb_match_packets",
 606                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 607         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 608                 tx_lpi_status)},
 609         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 610                 rx_lpi_status)},
 611         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 612                 tx_lpi_count)},
 613         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 614                 rx_lpi_count)},
 615 };
 616
 617 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 618                 sizeof(rte_i40e_hw_port_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_rx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_rx)},
 625 };
 626
 627 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 628                 sizeof(rte_i40e_rxq_prio_strings[0]))
 629
 630 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 631         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xon_tx)},
 633         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 634                 priority_xoff_tx)},
 635         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 636                 priority_xon_2_xoff)},
 637 };
 638
 639 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 640                 sizeof(rte_i40e_txq_prio_strings[0]))
 641
 642 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 643         struct rte_pci_device *pci_dev)
 644 {
 645         return rte_eth_dev_pci_generic_probe(pci_dev,
 646                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 647 }
 648
 649 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 650 {
 651         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 652 }
 653
 654 static struct rte_pci_driver rte_i40e_pmd = {
 655         .id_table = pci_id_i40e_map,
 656         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 657         .probe = eth_i40e_pci_probe,
 658         .remove = eth_i40e_pci_remove,
 659 };
 660
 661 static inline int
 662 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 663                                      struct rte_eth_link *link)
 664 {
 665         struct rte_eth_link *dst = link;
 666         struct rte_eth_link *src = &(dev->data->dev_link);
 667
 668         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 669                                         *(uint64_t *)src) == 0)
 670                 return -1;
 671
 672         return 0;
 673 }
 674
 675 static inline int
 676 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 677                                       struct rte_eth_link *link)
 678 {
 679         struct rte_eth_link *dst = &(dev->data->dev_link);
 680         struct rte_eth_link *src = link;
 681
 682         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 683                                         *(uint64_t *)src) == 0)
 684                 return -1;
 685
 686         return 0;
 687 }
 688
 689 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 690 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 691 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 692
 693 #ifndef I40E_GLQF_ORT
 694 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 695 #endif
 696 #ifndef I40E_GLQF_PIT
 697 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 698 #endif
 699 #ifndef I40E_GLQF_L3_MAP
 700 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 701 #endif
 702
 703 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 704 {
 705         /*
 706          * Initialize registers for flexible payload, which should be set by NVM.
 707          * This should be removed from code once it is fixed in NVM.
 708          */
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 716         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 719         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 720         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 721
 722         /* Initialize registers for parsing packet type of QinQ */
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 724         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 725 }
 726
 727 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 728
 729 /*
 730  * Add a ethertype filter to drop all flow control frames transmitted
 731  * from VSIs.
 732 */
 733 static void
 734 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 735 {
 736         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 737         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 738                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 739                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 740         int ret;
 741
 742         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 743                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 744                                 pf->main_vsi_seid, 0,
 745                                 TRUE, NULL, NULL);
 746         if (ret)
 747                 PMD_INIT_LOG(ERR,
 748                         "Failed to add filter to drop flow control frames from VSIs.");
 749 }
 750
 751 static int
 752 floating_veb_list_handler(__rte_unused const char *key,
 753                           const char *floating_veb_value,
 754                           void *opaque)
 755 {
 756         int idx = 0;
 757         unsigned int count = 0;
 758         char *end = NULL;
 759         int min, max;
 760         bool *vf_floating_veb = opaque;
 761
 762         while (isblank(*floating_veb_value))
 763                 floating_veb_value++;
 764
 765         /* Reset floating VEB configuration for VFs */
 766         for (idx = 0; idx < I40E_MAX_VF; idx++)
 767                 vf_floating_veb[idx] = false;
 768
 769         min = I40E_MAX_VF;
 770         do {
 771                 while (isblank(*floating_veb_value))
 772                         floating_veb_value++;
 773                 if (*floating_veb_value == '\0')
 774                         return -1;
 775                 errno = 0;
 776                 idx = strtoul(floating_veb_value, &end, 10);
 777                 if (errno || end == NULL)
 778                         return -1;
 779                 while (isblank(*end))
 780                         end++;
 781                 if (*end == '-') {
 782                         min = idx;
 783                 } else if ((*end == ';') || (*end == '\0')) {
 784                         max = idx;
 785                         if (min == I40E_MAX_VF)
 786                                 min = idx;
 787                         if (max >= I40E_MAX_VF)
 788                                 max = I40E_MAX_VF - 1;
 789                         for (idx = min; idx <= max; idx++) {
 790                                 vf_floating_veb[idx] = true;
 791                                 count++;
 792                         }
 793                         min = I40E_MAX_VF;
 794                 } else {
 795                         return -1;
 796                 }
 797                 floating_veb_value = end + 1;
 798         } while (*end != '\0');
 799
 800         if (count == 0)
 801                 return -1;
 802
 803         return 0;
 804 }
 805
 806 static void
 807 config_vf_floating_veb(struct rte_devargs *devargs,
 808                        uint16_t floating_veb,
 809                        bool *vf_floating_veb)
 810 {
 811         struct rte_kvargs *kvlist;
 812         int i;
 813         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 814
 815         if (!floating_veb)
 816                 return;
 817         /* All the VFs attach to the floating VEB by default
 818          * when the floating VEB is enabled.
 819          */
 820         for (i = 0; i < I40E_MAX_VF; i++)
 821                 vf_floating_veb[i] = true;
 822
 823         if (devargs == NULL)
 824                 return;
 825
 826         kvlist = rte_kvargs_parse(devargs->args, NULL);
 827         if (kvlist == NULL)
 828                 return;
 829
 830         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 831                 rte_kvargs_free(kvlist);
 832                 return;
 833         }
 834         /* When the floating_veb_list parameter exists, all the VFs
 835          * will attach to the legacy VEB firstly, then configure VFs
 836          * to the floating VEB according to the floating_veb_list.
 837          */
 838         if (rte_kvargs_process(kvlist, floating_veb_list,
 839                                floating_veb_list_handler,
 840                                vf_floating_veb) < 0) {
 841                 rte_kvargs_free(kvlist);
 842                 return;
 843         }
 844         rte_kvargs_free(kvlist);
 845 }
 846
 847 static int
 848 i40e_check_floating_handler(__rte_unused const char *key,
 849                             const char *value,
 850                             __rte_unused void *opaque)
 851 {
 852         if (strcmp(value, "1"))
 853                 return -1;
 854
 855         return 0;
 856 }
 857
 858 static int
 859 is_floating_veb_supported(struct rte_devargs *devargs)
 860 {
 861         struct rte_kvargs *kvlist;
 862         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 863
 864         if (devargs == NULL)
 865                 return 0;
 866
 867         kvlist = rte_kvargs_parse(devargs->args, NULL);
 868         if (kvlist == NULL)
 869                 return 0;
 870
 871         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 872                 rte_kvargs_free(kvlist);
 873                 return 0;
 874         }
 875         /* Floating VEB is enabled when there's key-value:
 876          * enable_floating_veb=1
 877          */
 878         if (rte_kvargs_process(kvlist, floating_veb_key,
 879                                i40e_check_floating_handler, NULL) < 0) {
 880                 rte_kvargs_free(kvlist);
 881                 return 0;
 882         }
 883         rte_kvargs_free(kvlist);
 884
 885         return 1;
 886 }
 887
 888 static void
 889 config_floating_veb(struct rte_eth_dev *dev)
 890 {
 891         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 892         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 894
 895         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 896
 897         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 898                 pf->floating_veb =
 899                         is_floating_veb_supported(pci_dev->device.devargs);
 900                 config_vf_floating_veb(pci_dev->device.devargs,
 901                                        pf->floating_veb,
 902                                        pf->floating_veb_list);
 903         } else {
 904                 pf->floating_veb = false;
 905         }
 906 }
 907
 908 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 909 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 910
 911 static int
 912 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 913 {
 914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 915         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 916         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 917         int ret;
 918
 919         struct rte_hash_parameters ethertype_hash_params = {
 920                 .name = ethertype_hash_name,
 921                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 922                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 923                 .hash_func = rte_hash_crc,
 924                 .hash_func_init_val = 0,
 925                 .socket_id = rte_socket_id(),
 926         };
 927
 928         /* Initialize ethertype filter rule list and hash */
 929         TAILQ_INIT(&ethertype_rule->ethertype_list);
 930         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 931                  "ethertype_%s", dev->device->name);
 932         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 933         if (!ethertype_rule->hash_table) {
 934                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 935                 return -EINVAL;
 936         }
 937         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 938                                        sizeof(struct i40e_ethertype_filter *) *
 939                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 940                                        0);
 941         if (!ethertype_rule->hash_map) {
 942                 PMD_INIT_LOG(ERR,
 943                              "Failed to allocate memory for ethertype hash map!");
 944                 ret = -ENOMEM;
 945                 goto err_ethertype_hash_map_alloc;
 946         }
 947
 948         return 0;
 949
 950 err_ethertype_hash_map_alloc:
 951         rte_hash_free(ethertype_rule->hash_table);
 952
 953         return ret;
 954 }
 955
 956 static int
 957 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 958 {
 959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 960         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 961         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 962         int ret;
 963
 964         struct rte_hash_parameters tunnel_hash_params = {
 965                 .name = tunnel_hash_name,
 966                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 967                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 968                 .hash_func = rte_hash_crc,
 969                 .hash_func_init_val = 0,
 970                 .socket_id = rte_socket_id(),
 971         };
 972
 973         /* Initialize tunnel filter rule list and hash */
 974         TAILQ_INIT(&tunnel_rule->tunnel_list);
 975         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 976                  "tunnel_%s", dev->device->name);
 977         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 978         if (!tunnel_rule->hash_table) {
 979                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 980                 return -EINVAL;
 981         }
 982         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 983                                     sizeof(struct i40e_tunnel_filter *) *
 984                                     I40E_MAX_TUNNEL_FILTER_NUM,
 985                                     0);
 986         if (!tunnel_rule->hash_map) {
 987                 PMD_INIT_LOG(ERR,
 988                              "Failed to allocate memory for tunnel hash map!");
 989                 ret = -ENOMEM;
 990                 goto err_tunnel_hash_map_alloc;
 991         }
 992
 993         return 0;
 994
 995 err_tunnel_hash_map_alloc:
 996         rte_hash_free(tunnel_rule->hash_table);
 997
 998         return ret;
 999 }
1000
1001 static int
1002 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1003 {
1004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1005         struct i40e_fdir_info *fdir_info = &pf->fdir;
1006         char fdir_hash_name[RTE_HASH_NAMESIZE];
1007         int ret;
1008
1009         struct rte_hash_parameters fdir_hash_params = {
1010                 .name = fdir_hash_name,
1011                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1012                 .key_len = sizeof(struct rte_eth_fdir_input),
1013                 .hash_func = rte_hash_crc,
1014                 .hash_func_init_val = 0,
1015                 .socket_id = rte_socket_id(),
1016         };
1017
1018         /* Initialize flow director filter rule list and hash */
1019         TAILQ_INIT(&fdir_info->fdir_list);
1020         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1021                  "fdir_%s", dev->device->name);
1022         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1023         if (!fdir_info->hash_table) {
1024                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1025                 return -EINVAL;
1026         }
1027         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1028                                           sizeof(struct i40e_fdir_filter *) *
1029                                           I40E_MAX_FDIR_FILTER_NUM,
1030                                           0);
1031         if (!fdir_info->hash_map) {
1032                 PMD_INIT_LOG(ERR,
1033                              "Failed to allocate memory for fdir hash map!");
1034                 ret = -ENOMEM;
1035                 goto err_fdir_hash_map_alloc;
1036         }
1037         return 0;
1038
1039 err_fdir_hash_map_alloc:
1040         rte_hash_free(fdir_info->hash_table);
1041
1042         return ret;
1043 }
1044
1045 static int
1046 eth_i40e_dev_init(struct rte_eth_dev *dev)
1047 {
1048         struct rte_pci_device *pci_dev;
1049         struct rte_intr_handle *intr_handle;
1050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1051         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052         struct i40e_vsi *vsi;
1053         int ret;
1054         uint32_t len;
1055         uint8_t aq_fail = 0;
1056
1057         PMD_INIT_FUNC_TRACE();
1058
1059         dev->dev_ops = &i40e_eth_dev_ops;
1060         dev->rx_pkt_burst = i40e_recv_pkts;
1061         dev->tx_pkt_burst = i40e_xmit_pkts;
1062         dev->tx_pkt_prepare = i40e_prep_pkts;
1063
1064         /* for secondary processes, we don't initialise any further as primary
1065          * has already done this work. Only check we don't need a different
1066          * RX function */
1067         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1068                 i40e_set_rx_function(dev);
1069                 i40e_set_tx_function(dev);
1070                 return 0;
1071         }
1072         i40e_set_default_ptype_table(dev);
1073         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1074         intr_handle = &pci_dev->intr_handle;
1075
1076         rte_eth_copy_pci_info(dev, pci_dev);
1077         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1078
1079         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1080         pf->adapter->eth_dev = dev;
1081         pf->dev_data = dev->data;
1082
1083         hw->back = I40E_PF_TO_ADAPTER(pf);
1084         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1085         if (!hw->hw_addr) {
1086                 PMD_INIT_LOG(ERR,
1087                         "Hardware is not available, as address is NULL");
1088                 return -ENODEV;
1089         }
1090
1091         hw->vendor_id = pci_dev->id.vendor_id;
1092         hw->device_id = pci_dev->id.device_id;
1093         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1094         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1095         hw->bus.device = pci_dev->addr.devid;
1096         hw->bus.func = pci_dev->addr.function;
1097         hw->adapter_stopped = 0;
1098
1099         /* Make sure all is clean before doing PF reset */
1100         i40e_clear_hw(hw);
1101
1102         /* Initialize the hardware */
1103         i40e_hw_init(dev);
1104
1105         /* Reset here to make sure all is clean for each PF */
1106         ret = i40e_pf_reset(hw);
1107         if (ret) {
1108                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1109                 return ret;
1110         }
1111
1112         /* Initialize the shared code (base driver) */
1113         ret = i40e_init_shared_code(hw);
1114         if (ret) {
1115                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1116                 return ret;
1117         }
1118
1119         /*
1120          * To work around the NVM issue, initialize registers
1121          * for flexible payload and packet type of QinQ by
1122          * software. It should be removed once issues are fixed
1123          * in NVM.
1124          */
1125         i40e_GLQF_reg_init(hw);
1126
1127         /* Initialize the input set for filters (hash and fd) to default value */
1128         i40e_filter_input_set_init(pf);
1129
1130         /* Initialize the parameters for adminq */
1131         i40e_init_adminq_parameter(hw);
1132         ret = i40e_init_adminq(hw);
1133         if (ret != I40E_SUCCESS) {
1134                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1135                 return -EIO;
1136         }
1137         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1138                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1139                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1140                      ((hw->nvm.version >> 12) & 0xf),
1141                      ((hw->nvm.version >> 4) & 0xff),
1142                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1143
1144         /* initialise the L3_MAP register */
1145         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1146                                    0x00000028,  NULL);
1147         if (ret)
1148                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1149
1150         /* Need the special FW version to support floating VEB */
1151         config_floating_veb(dev);
1152         /* Clear PXE mode */
1153         i40e_clear_pxe_mode(hw);
1154         i40e_dev_sync_phy_type(hw);
1155
1156         /*
1157          * On X710, performance number is far from the expectation on recent
1158          * firmware versions. The fix for this issue may not be integrated in
1159          * the following firmware version. So the workaround in software driver
1160          * is needed. It needs to modify the initial values of 3 internal only
1161          * registers. Note that the workaround can be removed when it is fixed
1162          * in firmware in the future.
1163          */
1164         i40e_configure_registers(hw);
1165
1166         /* Get hw capabilities */
1167         ret = i40e_get_cap(hw);
1168         if (ret != I40E_SUCCESS) {
1169                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1170                 goto err_get_capabilities;
1171         }
1172
1173         /* Initialize parameters for PF */
1174         ret = i40e_pf_parameter_init(dev);
1175         if (ret != 0) {
1176                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1177                 goto err_parameter_init;
1178         }
1179
1180         /* Initialize the queue management */
1181         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1182         if (ret < 0) {
1183                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1184                 goto err_qp_pool_init;
1185         }
1186         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1187                                 hw->func_caps.num_msix_vectors - 1);
1188         if (ret < 0) {
1189                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1190                 goto err_msix_pool_init;
1191         }
1192
1193         /* Initialize lan hmc */
1194         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1195                                 hw->func_caps.num_rx_qp, 0, 0);
1196         if (ret != I40E_SUCCESS) {
1197                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1198                 goto err_init_lan_hmc;
1199         }
1200
1201         /* Configure lan hmc */
1202         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1203         if (ret != I40E_SUCCESS) {
1204                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1205                 goto err_configure_lan_hmc;
1206         }
1207
1208         /* Get and check the mac address */
1209         i40e_get_mac_addr(hw, hw->mac.addr);
1210         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1211                 PMD_INIT_LOG(ERR, "mac address is not valid");
1212                 ret = -EIO;
1213                 goto err_get_mac_addr;
1214         }
1215         /* Copy the permanent MAC address */
1216         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1217                         (struct ether_addr *) hw->mac.perm_addr);
1218
1219         /* Disable flow control */
1220         hw->fc.requested_mode = I40E_FC_NONE;
1221         i40e_set_fc(hw, &aq_fail, TRUE);
1222
1223         /* Set the global registers with default ether type value */
1224         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1225         if (ret != I40E_SUCCESS) {
1226                 PMD_INIT_LOG(ERR,
1227                         "Failed to set the default outer VLAN ether type");
1228                 goto err_setup_pf_switch;
1229         }
1230
1231         /* PF setup, which includes VSI setup */
1232         ret = i40e_pf_setup(pf);
1233         if (ret) {
1234                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1235                 goto err_setup_pf_switch;
1236         }
1237
1238         /* reset all stats of the device, including pf and main vsi */
1239         i40e_dev_stats_reset(dev);
1240
1241         vsi = pf->main_vsi;
1242
1243         /* Disable double vlan by default */
1244         i40e_vsi_config_double_vlan(vsi, FALSE);
1245
1246         /* Disable S-TAG identification when floating_veb is disabled */
1247         if (!pf->floating_veb) {
1248                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1249                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1250                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1251                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1252                 }
1253         }
1254
1255         if (!vsi->max_macaddrs)
1256                 len = ETHER_ADDR_LEN;
1257         else
1258                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1259
1260         /* Should be after VSI initialized */
1261         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1262         if (!dev->data->mac_addrs) {
1263                 PMD_INIT_LOG(ERR,
1264                         "Failed to allocated memory for storing mac address");
1265                 goto err_mac_alloc;
1266         }
1267         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1268                                         &dev->data->mac_addrs[0]);
1269
1270         /* Init dcb to sw mode by default */
1271         ret = i40e_dcb_init_configure(dev, TRUE);
1272         if (ret != I40E_SUCCESS) {
1273                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1274                 pf->flags &= ~I40E_FLAG_DCB;
1275         }
1276         /* Update HW struct after DCB configuration */
1277         i40e_get_cap(hw);
1278
1279         /* initialize pf host driver to setup SRIOV resource if applicable */
1280         i40e_pf_host_init(dev);
1281
1282         /* register callback func to eal lib */
1283         rte_intr_callback_register(intr_handle,
1284                                    i40e_dev_interrupt_handler, dev);
1285
1286         /* configure and enable device interrupt */
1287         i40e_pf_config_irq0(hw, TRUE);
1288         i40e_pf_enable_irq0(hw);
1289
1290         /* enable uio intr after callback register */
1291         rte_intr_enable(intr_handle);
1292         /*
1293          * Add an ethertype filter to drop all flow control frames transmitted
1294          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1295          * frames to wire.
1296          */
1297         i40e_add_tx_flow_control_drop_filter(pf);
1298
1299         /* Set the max frame size to 0x2600 by default,
1300          * in case other drivers changed the default value.
1301          */
1302         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1303
1304         /* initialize mirror rule list */
1305         TAILQ_INIT(&pf->mirror_list);
1306
1307         /* initialize Traffic Manager configuration */
1308         i40e_tm_conf_init(dev);
1309
1310         ret = i40e_init_ethtype_filter_list(dev);
1311         if (ret < 0)
1312                 goto err_init_ethtype_filter_list;
1313         ret = i40e_init_tunnel_filter_list(dev);
1314         if (ret < 0)
1315                 goto err_init_tunnel_filter_list;
1316         ret = i40e_init_fdir_filter_list(dev);
1317         if (ret < 0)
1318                 goto err_init_fdir_filter_list;
1319
1320         return 0;
1321
1322 err_init_fdir_filter_list:
1323         rte_free(pf->tunnel.hash_table);
1324         rte_free(pf->tunnel.hash_map);
1325 err_init_tunnel_filter_list:
1326         rte_free(pf->ethertype.hash_table);
1327         rte_free(pf->ethertype.hash_map);
1328 err_init_ethtype_filter_list:
1329         rte_free(dev->data->mac_addrs);
1330 err_mac_alloc:
1331         i40e_vsi_release(pf->main_vsi);
1332 err_setup_pf_switch:
1333 err_get_mac_addr:
1334 err_configure_lan_hmc:
1335         (void)i40e_shutdown_lan_hmc(hw);
1336 err_init_lan_hmc:
1337         i40e_res_pool_destroy(&pf->msix_pool);
1338 err_msix_pool_init:
1339         i40e_res_pool_destroy(&pf->qp_pool);
1340 err_qp_pool_init:
1341 err_parameter_init:
1342 err_get_capabilities:
1343         (void)i40e_shutdown_adminq(hw);
1344
1345         return ret;
1346 }
1347
1348 static void
1349 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1350 {
1351         struct i40e_ethertype_filter *p_ethertype;
1352         struct i40e_ethertype_rule *ethertype_rule;
1353
1354         ethertype_rule = &pf->ethertype;
1355         /* Remove all ethertype filter rules and hash */
1356         if (ethertype_rule->hash_map)
1357                 rte_free(ethertype_rule->hash_map);
1358         if (ethertype_rule->hash_table)
1359                 rte_hash_free(ethertype_rule->hash_table);
1360
1361         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1362                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1363                              p_ethertype, rules);
1364                 rte_free(p_ethertype);
1365         }
1366 }
1367
1368 static void
1369 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1370 {
1371         struct i40e_tunnel_filter *p_tunnel;
1372         struct i40e_tunnel_rule *tunnel_rule;
1373
1374         tunnel_rule = &pf->tunnel;
1375         /* Remove all tunnel director rules and hash */
1376         if (tunnel_rule->hash_map)
1377                 rte_free(tunnel_rule->hash_map);
1378         if (tunnel_rule->hash_table)
1379                 rte_hash_free(tunnel_rule->hash_table);
1380
1381         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1382                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1383                 rte_free(p_tunnel);
1384         }
1385 }
1386
1387 static void
1388 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1389 {
1390         struct i40e_fdir_filter *p_fdir;
1391         struct i40e_fdir_info *fdir_info;
1392
1393         fdir_info = &pf->fdir;
1394         /* Remove all flow director rules and hash */
1395         if (fdir_info->hash_map)
1396                 rte_free(fdir_info->hash_map);
1397         if (fdir_info->hash_table)
1398                 rte_hash_free(fdir_info->hash_table);
1399
1400         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1401                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1402                 rte_free(p_fdir);
1403         }
1404 }
1405
1406 static int
1407 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1408 {
1409         struct i40e_pf *pf;
1410         struct rte_pci_device *pci_dev;
1411         struct rte_intr_handle *intr_handle;
1412         struct i40e_hw *hw;
1413         struct i40e_filter_control_settings settings;
1414         struct rte_flow *p_flow;
1415         int ret;
1416         uint8_t aq_fail = 0;
1417
1418         PMD_INIT_FUNC_TRACE();
1419
1420         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1421                 return 0;
1422
1423         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1424         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1425         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1426         intr_handle = &pci_dev->intr_handle;
1427
1428         if (hw->adapter_stopped == 0)
1429                 i40e_dev_close(dev);
1430
1431         dev->dev_ops = NULL;
1432         dev->rx_pkt_burst = NULL;
1433         dev->tx_pkt_burst = NULL;
1434
1435         /* Clear PXE mode */
1436         i40e_clear_pxe_mode(hw);
1437
1438         /* Unconfigure filter control */
1439         memset(&settings, 0, sizeof(settings));
1440         ret = i40e_set_filter_control(hw, &settings);
1441         if (ret)
1442                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1443                                         ret);
1444
1445         /* Disable flow control */
1446         hw->fc.requested_mode = I40E_FC_NONE;
1447         i40e_set_fc(hw, &aq_fail, TRUE);
1448
1449         /* uninitialize pf host driver */
1450         i40e_pf_host_uninit(dev);
1451
1452         rte_free(dev->data->mac_addrs);
1453         dev->data->mac_addrs = NULL;
1454
1455         /* disable uio intr before callback unregister */
1456         rte_intr_disable(intr_handle);
1457
1458         /* register callback func to eal lib */
1459         rte_intr_callback_unregister(intr_handle,
1460                                      i40e_dev_interrupt_handler, dev);
1461
1462         i40e_rm_ethtype_filter_list(pf);
1463         i40e_rm_tunnel_filter_list(pf);
1464         i40e_rm_fdir_filter_list(pf);
1465
1466         /* Remove all flows */
1467         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1468                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1469                 rte_free(p_flow);
1470         }
1471
1472         /* Remove all Traffic Manager configuration */
1473         i40e_tm_conf_uninit(dev);
1474
1475         return 0;
1476 }
1477
1478 static int
1479 i40e_dev_configure(struct rte_eth_dev *dev)
1480 {
1481         struct i40e_adapter *ad =
1482                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1483         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1484         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1486         int i, ret;
1487
1488         ret = i40e_dev_sync_phy_type(hw);
1489         if (ret)
1490                 return ret;
1491
1492         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1493          * bulk allocation or vector Rx preconditions we will reset it.
1494          */
1495         ad->rx_bulk_alloc_allowed = true;
1496         ad->rx_vec_allowed = true;
1497         ad->tx_simple_allowed = true;
1498         ad->tx_vec_allowed = true;
1499
1500         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1501                 ret = i40e_fdir_setup(pf);
1502                 if (ret != I40E_SUCCESS) {
1503                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1504                         return -ENOTSUP;
1505                 }
1506                 ret = i40e_fdir_configure(dev);
1507                 if (ret < 0) {
1508                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1509                         goto err;
1510                 }
1511         } else
1512                 i40e_fdir_teardown(pf);
1513
1514         ret = i40e_dev_init_vlan(dev);
1515         if (ret < 0)
1516                 goto err;
1517
1518         /* VMDQ setup.
1519          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1520          *  RSS setting have different requirements.
1521          *  General PMD driver call sequence are NIC init, configure,
1522          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1523          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1524          *  applicable. So, VMDQ setting has to be done before
1525          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1526          *  For RSS setting, it will try to calculate actual configured RX queue
1527          *  number, which will be available after rx_queue_setup(). dev_start()
1528          *  function is good to place RSS setup.
1529          */
1530         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1531                 ret = i40e_vmdq_setup(dev);
1532                 if (ret)
1533                         goto err;
1534         }
1535
1536         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1537                 ret = i40e_dcb_setup(dev);
1538                 if (ret) {
1539                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1540                         goto err_dcb;
1541                 }
1542         }
1543
1544         TAILQ_INIT(&pf->flow_list);
1545
1546         return 0;
1547
1548 err_dcb:
1549         /* need to release vmdq resource if exists */
1550         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1551                 i40e_vsi_release(pf->vmdq[i].vsi);
1552                 pf->vmdq[i].vsi = NULL;
1553         }
1554         rte_free(pf->vmdq);
1555         pf->vmdq = NULL;
1556 err:
1557         /* need to release fdir resource if exists */
1558         i40e_fdir_teardown(pf);
1559         return ret;
1560 }
1561
1562 void
1563 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1564 {
1565         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1566         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1567         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1568         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1569         uint16_t msix_vect = vsi->msix_intr;
1570         uint16_t i;
1571
1572         for (i = 0; i < vsi->nb_qps; i++) {
1573                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1574                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1575                 rte_wmb();
1576         }
1577
1578         if (vsi->type != I40E_VSI_SRIOV) {
1579                 if (!rte_intr_allow_others(intr_handle)) {
1580                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1581                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1582                         I40E_WRITE_REG(hw,
1583                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1584                                        0);
1585                 } else {
1586                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1587                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1588                         I40E_WRITE_REG(hw,
1589                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1590                                                        msix_vect - 1), 0);
1591                 }
1592         } else {
1593                 uint32_t reg;
1594                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1595                         vsi->user_param + (msix_vect - 1);
1596
1597                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1598                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1599         }
1600         I40E_WRITE_FLUSH(hw);
1601 }
1602
1603 static void
1604 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1605                        int base_queue, int nb_queue,
1606                        uint16_t itr_idx)
1607 {
1608         int i;
1609         uint32_t val;
1610         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1611
1612         /* Bind all RX queues to allocated MSIX interrupt */
1613         for (i = 0; i < nb_queue; i++) {
1614                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1615                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1616                         ((base_queue + i + 1) <<
1617                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1618                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1619                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1620
1621                 if (i == nb_queue - 1)
1622                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1623                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1624         }
1625
1626         /* Write first RX queue to Link list register as the head element */
1627         if (vsi->type != I40E_VSI_SRIOV) {
1628                 uint16_t interval =
1629                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1630
1631                 if (msix_vect == I40E_MISC_VEC_ID) {
1632                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1633                                        (base_queue <<
1634                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1635                                        (0x0 <<
1636                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1637                         I40E_WRITE_REG(hw,
1638                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1639                                        interval);
1640                 } else {
1641                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1642                                        (base_queue <<
1643                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1644                                        (0x0 <<
1645                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1646                         I40E_WRITE_REG(hw,
1647                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1648                                                        msix_vect - 1),
1649                                        interval);
1650                 }
1651         } else {
1652                 uint32_t reg;
1653
1654                 if (msix_vect == I40E_MISC_VEC_ID) {
1655                         I40E_WRITE_REG(hw,
1656                                        I40E_VPINT_LNKLST0(vsi->user_param),
1657                                        (base_queue <<
1658                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1659                                        (0x0 <<
1660                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1661                 } else {
1662                         /* num_msix_vectors_vf needs to minus irq0 */
1663                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1664                                 vsi->user_param + (msix_vect - 1);
1665
1666                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1667                                        (base_queue <<
1668                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1669                                        (0x0 <<
1670                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1671                 }
1672         }
1673
1674         I40E_WRITE_FLUSH(hw);
1675 }
1676
1677 void
1678 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1679 {
1680         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1681         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1682         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1683         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1684         uint16_t msix_vect = vsi->msix_intr;
1685         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1686         uint16_t queue_idx = 0;
1687         int record = 0;
1688         uint32_t val;
1689         int i;
1690
1691         for (i = 0; i < vsi->nb_qps; i++) {
1692                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1693                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1694         }
1695
1696         /* INTENA flag is not auto-cleared for interrupt */
1697         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1698         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1699                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1700                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1701         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1702
1703         /* VF bind interrupt */
1704         if (vsi->type == I40E_VSI_SRIOV) {
1705                 __vsi_queues_bind_intr(vsi, msix_vect,
1706                                        vsi->base_queue, vsi->nb_qps,
1707                                        itr_idx);
1708                 return;
1709         }
1710
1711         /* PF & VMDq bind interrupt */
1712         if (rte_intr_dp_is_en(intr_handle)) {
1713                 if (vsi->type == I40E_VSI_MAIN) {
1714                         queue_idx = 0;
1715                         record = 1;
1716                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1717                         struct i40e_vsi *main_vsi =
1718                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1719                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1720                         record = 1;
1721                 }
1722         }
1723
1724         for (i = 0; i < vsi->nb_used_qps; i++) {
1725                 if (nb_msix <= 1) {
1726                         if (!rte_intr_allow_others(intr_handle))
1727                                 /* allow to share MISC_VEC_ID */
1728                                 msix_vect = I40E_MISC_VEC_ID;
1729
1730                         /* no enough msix_vect, map all to one */
1731                         __vsi_queues_bind_intr(vsi, msix_vect,
1732                                                vsi->base_queue + i,
1733                                                vsi->nb_used_qps - i,
1734                                                itr_idx);
1735                         for (; !!record && i < vsi->nb_used_qps; i++)
1736                                 intr_handle->intr_vec[queue_idx + i] =
1737                                         msix_vect;
1738                         break;
1739                 }
1740                 /* 1:1 queue/msix_vect mapping */
1741                 __vsi_queues_bind_intr(vsi, msix_vect,
1742                                        vsi->base_queue + i, 1,
1743                                        itr_idx);
1744                 if (!!record)
1745                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1746
1747                 msix_vect++;
1748                 nb_msix--;
1749         }
1750 }
1751
1752 static void
1753 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1754 {
1755         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1756         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1757         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1758         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1759         uint16_t interval = i40e_calc_itr_interval(\
1760                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1761         uint16_t msix_intr, i;
1762
1763         if (rte_intr_allow_others(intr_handle))
1764                 for (i = 0; i < vsi->nb_msix; i++) {
1765                         msix_intr = vsi->msix_intr + i;
1766                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1767                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1768                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1769                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1770                                 (interval <<
1771                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1772                 }
1773         else
1774                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1775                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1776                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1777                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1778                                (interval <<
1779                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1780
1781         I40E_WRITE_FLUSH(hw);
1782 }
1783
1784 static void
1785 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1786 {
1787         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1788         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1789         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1790         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1791         uint16_t msix_intr, i;
1792
1793         if (rte_intr_allow_others(intr_handle))
1794                 for (i = 0; i < vsi->nb_msix; i++) {
1795                         msix_intr = vsi->msix_intr + i;
1796                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1797                                        0);
1798                 }
1799         else
1800                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1801
1802         I40E_WRITE_FLUSH(hw);
1803 }
1804
1805 static inline uint8_t
1806 i40e_parse_link_speeds(uint16_t link_speeds)
1807 {
1808         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1809
1810         if (link_speeds & ETH_LINK_SPEED_40G)
1811                 link_speed |= I40E_LINK_SPEED_40GB;
1812         if (link_speeds & ETH_LINK_SPEED_25G)
1813                 link_speed |= I40E_LINK_SPEED_25GB;
1814         if (link_speeds & ETH_LINK_SPEED_20G)
1815                 link_speed |= I40E_LINK_SPEED_20GB;
1816         if (link_speeds & ETH_LINK_SPEED_10G)
1817                 link_speed |= I40E_LINK_SPEED_10GB;
1818         if (link_speeds & ETH_LINK_SPEED_1G)
1819                 link_speed |= I40E_LINK_SPEED_1GB;
1820         if (link_speeds & ETH_LINK_SPEED_100M)
1821                 link_speed |= I40E_LINK_SPEED_100MB;
1822
1823         return link_speed;
1824 }
1825
1826 static int
1827 i40e_phy_conf_link(struct i40e_hw *hw,
1828                    uint8_t abilities,
1829                    uint8_t force_speed,
1830                    bool is_up)
1831 {
1832         enum i40e_status_code status;
1833         struct i40e_aq_get_phy_abilities_resp phy_ab;
1834         struct i40e_aq_set_phy_config phy_conf;
1835         enum i40e_aq_phy_type cnt;
1836         uint32_t phy_type_mask = 0;
1837
1838         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1839                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1840                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1841                         I40E_AQ_PHY_FLAG_LOW_POWER;
1842         const uint8_t advt = I40E_LINK_SPEED_40GB |
1843                         I40E_LINK_SPEED_25GB |
1844                         I40E_LINK_SPEED_10GB |
1845                         I40E_LINK_SPEED_1GB |
1846                         I40E_LINK_SPEED_100MB;
1847         int ret = -ENOTSUP;
1848
1849
1850         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1851                                               NULL);
1852         if (status)
1853                 return ret;
1854
1855         /* If link already up, no need to set up again */
1856         if (is_up && phy_ab.phy_type != 0)
1857                 return I40E_SUCCESS;
1858
1859         memset(&phy_conf, 0, sizeof(phy_conf));
1860
1861         /* bits 0-2 use the values from get_phy_abilities_resp */
1862         abilities &= ~mask;
1863         abilities |= phy_ab.abilities & mask;
1864
1865         /* update ablities and speed */
1866         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1867                 phy_conf.link_speed = advt;
1868         else
1869                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1870
1871         phy_conf.abilities = abilities;
1872
1873
1874
1875         /* To enable link, phy_type mask needs to include each type */
1876         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1877                 phy_type_mask |= 1 << cnt;
1878
1879         /* use get_phy_abilities_resp value for the rest */
1880         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1881         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1882                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1883                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1884         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1885         phy_conf.eee_capability = phy_ab.eee_capability;
1886         phy_conf.eeer = phy_ab.eeer_val;
1887         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1888
1889         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1890                     phy_ab.abilities, phy_ab.link_speed);
1891         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1892                     phy_conf.abilities, phy_conf.link_speed);
1893
1894         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1895         if (status)
1896                 return ret;
1897
1898         return I40E_SUCCESS;
1899 }
1900
1901 static int
1902 i40e_apply_link_speed(struct rte_eth_dev *dev)
1903 {
1904         uint8_t speed;
1905         uint8_t abilities = 0;
1906         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1907         struct rte_eth_conf *conf = &dev->data->dev_conf;
1908
1909         speed = i40e_parse_link_speeds(conf->link_speeds);
1910         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1911         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1912                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1913         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1914
1915         return i40e_phy_conf_link(hw, abilities, speed, true);
1916 }
1917
1918 static int
1919 i40e_dev_start(struct rte_eth_dev *dev)
1920 {
1921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923         struct i40e_vsi *main_vsi = pf->main_vsi;
1924         int ret, i;
1925         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1926         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1927         uint32_t intr_vector = 0;
1928         struct i40e_vsi *vsi;
1929
1930         hw->adapter_stopped = 0;
1931
1932         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1933                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1934                              dev->data->port_id);
1935                 return -EINVAL;
1936         }
1937
1938         rte_intr_disable(intr_handle);
1939
1940         if ((rte_intr_cap_multiple(intr_handle) ||
1941              !RTE_ETH_DEV_SRIOV(dev).active) &&
1942             dev->data->dev_conf.intr_conf.rxq != 0) {
1943                 intr_vector = dev->data->nb_rx_queues;
1944                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1945                 if (ret)
1946                         return ret;
1947         }
1948
1949         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1950                 intr_handle->intr_vec =
1951                         rte_zmalloc("intr_vec",
1952                                     dev->data->nb_rx_queues * sizeof(int),
1953                                     0);
1954                 if (!intr_handle->intr_vec) {
1955                         PMD_INIT_LOG(ERR,
1956                                 "Failed to allocate %d rx_queues intr_vec",
1957                                 dev->data->nb_rx_queues);
1958                         return -ENOMEM;
1959                 }
1960         }
1961
1962         /* Initialize VSI */
1963         ret = i40e_dev_rxtx_init(pf);
1964         if (ret != I40E_SUCCESS) {
1965                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1966                 goto err_up;
1967         }
1968
1969         /* Map queues with MSIX interrupt */
1970         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1971                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1972         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1973         i40e_vsi_enable_queues_intr(main_vsi);
1974
1975         /* Map VMDQ VSI queues with MSIX interrupt */
1976         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1977                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1978                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1979                                           I40E_ITR_INDEX_DEFAULT);
1980                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1981         }
1982
1983         /* enable FDIR MSIX interrupt */
1984         if (pf->fdir.fdir_vsi) {
1985                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1986                                           I40E_ITR_INDEX_NONE);
1987                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1988         }
1989
1990         /* Enable all queues which have been configured */
1991         ret = i40e_dev_switch_queues(pf, TRUE);
1992         if (ret != I40E_SUCCESS) {
1993                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1994                 goto err_up;
1995         }
1996
1997         /* Enable receiving broadcast packets */
1998         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1999         if (ret != I40E_SUCCESS)
2000                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2001
2002         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2003                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2004                                                 true, NULL);
2005                 if (ret != I40E_SUCCESS)
2006                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2007         }
2008
2009         /* Enable the VLAN promiscuous mode. */
2010         if (pf->vfs) {
2011                 for (i = 0; i < pf->vf_num; i++) {
2012                         vsi = pf->vfs[i].vsi;
2013                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2014                                                      true, NULL);
2015                 }
2016         }
2017
2018         /* Apply link configure */
2019         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2020                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2021                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2022                                 ETH_LINK_SPEED_40G)) {
2023                 PMD_DRV_LOG(ERR, "Invalid link setting");
2024                 goto err_up;
2025         }
2026         ret = i40e_apply_link_speed(dev);
2027         if (I40E_SUCCESS != ret) {
2028                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2029                 goto err_up;
2030         }
2031
2032         if (!rte_intr_allow_others(intr_handle)) {
2033                 rte_intr_callback_unregister(intr_handle,
2034                                              i40e_dev_interrupt_handler,
2035                                              (void *)dev);
2036                 /* configure and enable device interrupt */
2037                 i40e_pf_config_irq0(hw, FALSE);
2038                 i40e_pf_enable_irq0(hw);
2039
2040                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2041                         PMD_INIT_LOG(INFO,
2042                                 "lsc won't enable because of no intr multiplex");
2043         } else {
2044                 ret = i40e_aq_set_phy_int_mask(hw,
2045                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2046                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2047                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2048                 if (ret != I40E_SUCCESS)
2049                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2050
2051                 /* Call get_link_info aq commond to enable/disable LSE */
2052                 i40e_dev_link_update(dev, 0);
2053         }
2054
2055         /* enable uio intr after callback register */
2056         rte_intr_enable(intr_handle);
2057
2058         i40e_filter_restore(pf);
2059
2060         if (pf->tm_conf.root && !pf->tm_conf.committed)
2061                 PMD_DRV_LOG(WARNING,
2062                             "please call hierarchy_commit() "
2063                             "before starting the port");
2064
2065         return I40E_SUCCESS;
2066
2067 err_up:
2068         i40e_dev_switch_queues(pf, FALSE);
2069         i40e_dev_clear_queues(dev);
2070
2071         return ret;
2072 }
2073
2074 static void
2075 i40e_dev_stop(struct rte_eth_dev *dev)
2076 {
2077         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         struct i40e_vsi *main_vsi = pf->main_vsi;
2080         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082         int i;
2083
2084         if (hw->adapter_stopped == 1)
2085                 return;
2086         /* Disable all queues */
2087         i40e_dev_switch_queues(pf, FALSE);
2088
2089         /* un-map queues with interrupt registers */
2090         i40e_vsi_disable_queues_intr(main_vsi);
2091         i40e_vsi_queues_unbind_intr(main_vsi);
2092
2093         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2094                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2095                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2096         }
2097
2098         if (pf->fdir.fdir_vsi) {
2099                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2100                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2101         }
2102         /* Clear all queues and release memory */
2103         i40e_dev_clear_queues(dev);
2104
2105         /* Set link down */
2106         i40e_dev_set_link_down(dev);
2107
2108         if (!rte_intr_allow_others(intr_handle))
2109                 /* resume to the default handler */
2110                 rte_intr_callback_register(intr_handle,
2111                                            i40e_dev_interrupt_handler,
2112                                            (void *)dev);
2113
2114         /* Clean datapath event and queue/vec mapping */
2115         rte_intr_efd_disable(intr_handle);
2116         if (intr_handle->intr_vec) {
2117                 rte_free(intr_handle->intr_vec);
2118                 intr_handle->intr_vec = NULL;
2119         }
2120
2121         /* reset hierarchy commit */
2122         pf->tm_conf.committed = false;
2123
2124         hw->adapter_stopped = 1;
2125 }
2126
2127 static void
2128 i40e_dev_close(struct rte_eth_dev *dev)
2129 {
2130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2133         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2134         struct i40e_mirror_rule *p_mirror;
2135         uint32_t reg;
2136         int i;
2137         int ret;
2138
2139         PMD_INIT_FUNC_TRACE();
2140
2141         i40e_dev_stop(dev);
2142
2143         /* Remove all mirror rules */
2144         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2145                 ret = i40e_aq_del_mirror_rule(hw,
2146                                               pf->main_vsi->veb->seid,
2147                                               p_mirror->rule_type,
2148                                               p_mirror->entries,
2149                                               p_mirror->num_entries,
2150                                               p_mirror->id);
2151                 if (ret < 0)
2152                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2153                                     "status = %d, aq_err = %d.", ret,
2154                                     hw->aq.asq_last_status);
2155
2156                 /* remove mirror software resource anyway */
2157                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2158                 rte_free(p_mirror);
2159                 pf->nb_mirror_rule--;
2160         }
2161
2162         i40e_dev_free_queues(dev);
2163
2164         /* Disable interrupt */
2165         i40e_pf_disable_irq0(hw);
2166         rte_intr_disable(intr_handle);
2167
2168         /* shutdown and destroy the HMC */
2169         i40e_shutdown_lan_hmc(hw);
2170
2171         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2172                 i40e_vsi_release(pf->vmdq[i].vsi);
2173                 pf->vmdq[i].vsi = NULL;
2174         }
2175         rte_free(pf->vmdq);
2176         pf->vmdq = NULL;
2177
2178         /* release all the existing VSIs and VEBs */
2179         i40e_fdir_teardown(pf);
2180         i40e_vsi_release(pf->main_vsi);
2181
2182         /* shutdown the adminq */
2183         i40e_aq_queue_shutdown(hw, true);
2184         i40e_shutdown_adminq(hw);
2185
2186         i40e_res_pool_destroy(&pf->qp_pool);
2187         i40e_res_pool_destroy(&pf->msix_pool);
2188
2189         /* force a PF reset to clean anything leftover */
2190         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2191         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2192                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2193         I40E_WRITE_FLUSH(hw);
2194 }
2195
2196 /*
2197  * Reset PF device only to re-initialize resources in PMD layer
2198  */
2199 static int
2200 i40e_dev_reset(struct rte_eth_dev *dev)
2201 {
2202         int ret;
2203
2204         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2205          * its VF to make them align with it. The detailed notification
2206          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2207          * To avoid unexpected behavior in VF, currently reset of PF with
2208          * SR-IOV activation is not supported. It might be supported later.
2209          */
2210         if (dev->data->sriov.active)
2211                 return -ENOTSUP;
2212
2213         ret = eth_i40e_dev_uninit(dev);
2214         if (ret)
2215                 return ret;
2216
2217         ret = eth_i40e_dev_init(dev);
2218
2219         return ret;
2220 }
2221
2222 static void
2223 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2224 {
2225         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2226         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         struct i40e_vsi *vsi = pf->main_vsi;
2228         int status;
2229
2230         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2231                                                      true, NULL, true);
2232         if (status != I40E_SUCCESS)
2233                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2234
2235         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2236                                                         TRUE, NULL);
2237         if (status != I40E_SUCCESS)
2238                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2239
2240 }
2241
2242 static void
2243 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2244 {
2245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247         struct i40e_vsi *vsi = pf->main_vsi;
2248         int status;
2249
2250         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2251                                                      false, NULL, true);
2252         if (status != I40E_SUCCESS)
2253                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2254
2255         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2256                                                         false, NULL);
2257         if (status != I40E_SUCCESS)
2258                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2259 }
2260
2261 static void
2262 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2263 {
2264         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2265         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2266         struct i40e_vsi *vsi = pf->main_vsi;
2267         int ret;
2268
2269         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2270         if (ret != I40E_SUCCESS)
2271                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2272 }
2273
2274 static void
2275 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2276 {
2277         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2278         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279         struct i40e_vsi *vsi = pf->main_vsi;
2280         int ret;
2281
2282         if (dev->data->promiscuous == 1)
2283                 return; /* must remain in all_multicast mode */
2284
2285         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2286                                 vsi->seid, FALSE, NULL);
2287         if (ret != I40E_SUCCESS)
2288                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2289 }
2290
2291 /*
2292  * Set device link up.
2293  */
2294 static int
2295 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2296 {
2297         /* re-apply link speed setting */
2298         return i40e_apply_link_speed(dev);
2299 }
2300
2301 /*
2302  * Set device link down.
2303  */
2304 static int
2305 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2306 {
2307         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2308         uint8_t abilities = 0;
2309         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2310
2311         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2312         return i40e_phy_conf_link(hw, abilities, speed, false);
2313 }
2314
2315 int
2316 i40e_dev_link_update(struct rte_eth_dev *dev,
2317                      int wait_to_complete)
2318 {
2319 #define CHECK_INTERVAL 100  /* 100ms */
2320 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2321         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2322         struct i40e_link_status link_status;
2323         struct rte_eth_link link, old;
2324         int status;
2325         unsigned rep_cnt = MAX_REPEAT_TIME;
2326         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2327
2328         memset(&link, 0, sizeof(link));
2329         memset(&old, 0, sizeof(old));
2330         memset(&link_status, 0, sizeof(link_status));
2331         rte_i40e_dev_atomic_read_link_status(dev, &old);
2332
2333         do {
2334                 /* Get link status information from hardware */
2335                 status = i40e_aq_get_link_info(hw, enable_lse,
2336                                                 &link_status, NULL);
2337                 if (status != I40E_SUCCESS) {
2338                         link.link_speed = ETH_SPEED_NUM_100M;
2339                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2340                         PMD_DRV_LOG(ERR, "Failed to get link info");
2341                         goto out;
2342                 }
2343
2344                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2345                 if (!wait_to_complete || link.link_status)
2346                         break;
2347
2348                 rte_delay_ms(CHECK_INTERVAL);
2349         } while (--rep_cnt);
2350
2351         if (!link.link_status)
2352                 goto out;
2353
2354         /* i40e uses full duplex only */
2355         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2356
2357         /* Parse the link status */
2358         switch (link_status.link_speed) {
2359         case I40E_LINK_SPEED_100MB:
2360                 link.link_speed = ETH_SPEED_NUM_100M;
2361                 break;
2362         case I40E_LINK_SPEED_1GB:
2363                 link.link_speed = ETH_SPEED_NUM_1G;
2364                 break;
2365         case I40E_LINK_SPEED_10GB:
2366                 link.link_speed = ETH_SPEED_NUM_10G;
2367                 break;
2368         case I40E_LINK_SPEED_20GB:
2369                 link.link_speed = ETH_SPEED_NUM_20G;
2370                 break;
2371         case I40E_LINK_SPEED_25GB:
2372                 link.link_speed = ETH_SPEED_NUM_25G;
2373                 break;
2374         case I40E_LINK_SPEED_40GB:
2375                 link.link_speed = ETH_SPEED_NUM_40G;
2376                 break;
2377         default:
2378                 link.link_speed = ETH_SPEED_NUM_100M;
2379                 break;
2380         }
2381
2382         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2383                         ETH_LINK_SPEED_FIXED);
2384
2385 out:
2386         rte_i40e_dev_atomic_write_link_status(dev, &link);
2387         if (link.link_status == old.link_status)
2388                 return -1;
2389
2390         i40e_notify_all_vfs_link_status(dev);
2391
2392         return 0;
2393 }
2394
2395 /* Get all the statistics of a VSI */
2396 void
2397 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2398 {
2399         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2400         struct i40e_eth_stats *nes = &vsi->eth_stats;
2401         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2402         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2403
2404         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2405                             vsi->offset_loaded, &oes->rx_bytes,
2406                             &nes->rx_bytes);
2407         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2408                             vsi->offset_loaded, &oes->rx_unicast,
2409                             &nes->rx_unicast);
2410         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2411                             vsi->offset_loaded, &oes->rx_multicast,
2412                             &nes->rx_multicast);
2413         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2414                             vsi->offset_loaded, &oes->rx_broadcast,
2415                             &nes->rx_broadcast);
2416         /* exclude CRC bytes */
2417         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2418                 nes->rx_broadcast) * ETHER_CRC_LEN;
2419
2420         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2421                             &oes->rx_discards, &nes->rx_discards);
2422         /* GLV_REPC not supported */
2423         /* GLV_RMPC not supported */
2424         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2425                             &oes->rx_unknown_protocol,
2426                             &nes->rx_unknown_protocol);
2427         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2428                             vsi->offset_loaded, &oes->tx_bytes,
2429                             &nes->tx_bytes);
2430         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2431                             vsi->offset_loaded, &oes->tx_unicast,
2432                             &nes->tx_unicast);
2433         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2434                             vsi->offset_loaded, &oes->tx_multicast,
2435                             &nes->tx_multicast);
2436         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2437                             vsi->offset_loaded,  &oes->tx_broadcast,
2438                             &nes->tx_broadcast);
2439         /* GLV_TDPC not supported */
2440         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2441                             &oes->tx_errors, &nes->tx_errors);
2442         vsi->offset_loaded = true;
2443
2444         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2445                     vsi->vsi_id);
2446         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2447         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2448         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2449         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2450         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2451         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2452                     nes->rx_unknown_protocol);
2453         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2454         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2455         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2456         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2457         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2458         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2459         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2460                     vsi->vsi_id);
2461 }
2462
2463 static void
2464 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2465 {
2466         unsigned int i;
2467         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2468         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2469
2470         /* Get rx/tx bytes of internal transfer packets */
2471         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2472                         I40E_GLV_GORCL(hw->port),
2473                         pf->offset_loaded,
2474                         &pf->internal_stats_offset.rx_bytes,
2475                         &pf->internal_stats.rx_bytes);
2476
2477         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2478                         I40E_GLV_GOTCL(hw->port),
2479                         pf->offset_loaded,
2480                         &pf->internal_stats_offset.tx_bytes,
2481                         &pf->internal_stats.tx_bytes);
2482         /* Get total internal rx packet count */
2483         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2484                             I40E_GLV_UPRCL(hw->port),
2485                             pf->offset_loaded,
2486                             &pf->internal_stats_offset.rx_unicast,
2487                             &pf->internal_stats.rx_unicast);
2488         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2489                             I40E_GLV_MPRCL(hw->port),
2490                             pf->offset_loaded,
2491                             &pf->internal_stats_offset.rx_multicast,
2492                             &pf->internal_stats.rx_multicast);
2493         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2494                             I40E_GLV_BPRCL(hw->port),
2495                             pf->offset_loaded,
2496                             &pf->internal_stats_offset.rx_broadcast,
2497                             &pf->internal_stats.rx_broadcast);
2498
2499         /* exclude CRC size */
2500         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2501                 pf->internal_stats.rx_multicast +
2502                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2503
2504         /* Get statistics of struct i40e_eth_stats */
2505         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2506                             I40E_GLPRT_GORCL(hw->port),
2507                             pf->offset_loaded, &os->eth.rx_bytes,
2508                             &ns->eth.rx_bytes);
2509         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2510                             I40E_GLPRT_UPRCL(hw->port),
2511                             pf->offset_loaded, &os->eth.rx_unicast,
2512                             &ns->eth.rx_unicast);
2513         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2514                             I40E_GLPRT_MPRCL(hw->port),
2515                             pf->offset_loaded, &os->eth.rx_multicast,
2516                             &ns->eth.rx_multicast);
2517         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2518                             I40E_GLPRT_BPRCL(hw->port),
2519                             pf->offset_loaded, &os->eth.rx_broadcast,
2520                             &ns->eth.rx_broadcast);
2521         /* Workaround: CRC size should not be included in byte statistics,
2522          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2523          */
2524         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2525                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2526
2527         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2528          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2529          * value.
2530          */
2531         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2532                 ns->eth.rx_bytes = 0;
2533         /* exlude internal rx bytes */
2534         else
2535                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2536
2537         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2538                             pf->offset_loaded, &os->eth.rx_discards,
2539                             &ns->eth.rx_discards);
2540         /* GLPRT_REPC not supported */
2541         /* GLPRT_RMPC not supported */
2542         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2543                             pf->offset_loaded,
2544                             &os->eth.rx_unknown_protocol,
2545                             &ns->eth.rx_unknown_protocol);
2546         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2547                             I40E_GLPRT_GOTCL(hw->port),
2548                             pf->offset_loaded, &os->eth.tx_bytes,
2549                             &ns->eth.tx_bytes);
2550         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2551                             I40E_GLPRT_UPTCL(hw->port),
2552                             pf->offset_loaded, &os->eth.tx_unicast,
2553                             &ns->eth.tx_unicast);
2554         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2555                             I40E_GLPRT_MPTCL(hw->port),
2556                             pf->offset_loaded, &os->eth.tx_multicast,
2557                             &ns->eth.tx_multicast);
2558         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2559                             I40E_GLPRT_BPTCL(hw->port),
2560                             pf->offset_loaded, &os->eth.tx_broadcast,
2561                             &ns->eth.tx_broadcast);
2562         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2563                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2564
2565         /* exclude internal tx bytes */
2566         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2567                 ns->eth.tx_bytes = 0;
2568         else
2569                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2570
2571         /* GLPRT_TEPC not supported */
2572
2573         /* additional port specific stats */
2574         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2575                             pf->offset_loaded, &os->tx_dropped_link_down,
2576                             &ns->tx_dropped_link_down);
2577         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2578                             pf->offset_loaded, &os->crc_errors,
2579                             &ns->crc_errors);
2580         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2581                             pf->offset_loaded, &os->illegal_bytes,
2582                             &ns->illegal_bytes);
2583         /* GLPRT_ERRBC not supported */
2584         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2585                             pf->offset_loaded, &os->mac_local_faults,
2586                             &ns->mac_local_faults);
2587         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2588                             pf->offset_loaded, &os->mac_remote_faults,
2589                             &ns->mac_remote_faults);
2590         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2591                             pf->offset_loaded, &os->rx_length_errors,
2592                             &ns->rx_length_errors);
2593         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2594                             pf->offset_loaded, &os->link_xon_rx,
2595                             &ns->link_xon_rx);
2596         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2597                             pf->offset_loaded, &os->link_xoff_rx,
2598                             &ns->link_xoff_rx);
2599         for (i = 0; i < 8; i++) {
2600                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2601                                     pf->offset_loaded,
2602                                     &os->priority_xon_rx[i],
2603                                     &ns->priority_xon_rx[i]);
2604                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2605                                     pf->offset_loaded,
2606                                     &os->priority_xoff_rx[i],
2607                                     &ns->priority_xoff_rx[i]);
2608         }
2609         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2610                             pf->offset_loaded, &os->link_xon_tx,
2611                             &ns->link_xon_tx);
2612         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2613                             pf->offset_loaded, &os->link_xoff_tx,
2614                             &ns->link_xoff_tx);
2615         for (i = 0; i < 8; i++) {
2616                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2617                                     pf->offset_loaded,
2618                                     &os->priority_xon_tx[i],
2619                                     &ns->priority_xon_tx[i]);
2620                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2621                                     pf->offset_loaded,
2622                                     &os->priority_xoff_tx[i],
2623                                     &ns->priority_xoff_tx[i]);
2624                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2625                                     pf->offset_loaded,
2626                                     &os->priority_xon_2_xoff[i],
2627                                     &ns->priority_xon_2_xoff[i]);
2628         }
2629         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2630                             I40E_GLPRT_PRC64L(hw->port),
2631                             pf->offset_loaded, &os->rx_size_64,
2632                             &ns->rx_size_64);
2633         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2634                             I40E_GLPRT_PRC127L(hw->port),
2635                             pf->offset_loaded, &os->rx_size_127,
2636                             &ns->rx_size_127);
2637         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2638                             I40E_GLPRT_PRC255L(hw->port),
2639                             pf->offset_loaded, &os->rx_size_255,
2640                             &ns->rx_size_255);
2641         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2642                             I40E_GLPRT_PRC511L(hw->port),
2643                             pf->offset_loaded, &os->rx_size_511,
2644                             &ns->rx_size_511);
2645         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2646                             I40E_GLPRT_PRC1023L(hw->port),
2647                             pf->offset_loaded, &os->rx_size_1023,
2648                             &ns->rx_size_1023);
2649         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2650                             I40E_GLPRT_PRC1522L(hw->port),
2651                             pf->offset_loaded, &os->rx_size_1522,
2652                             &ns->rx_size_1522);
2653         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2654                             I40E_GLPRT_PRC9522L(hw->port),
2655                             pf->offset_loaded, &os->rx_size_big,
2656                             &ns->rx_size_big);
2657         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2658                             pf->offset_loaded, &os->rx_undersize,
2659                             &ns->rx_undersize);
2660         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2661                             pf->offset_loaded, &os->rx_fragments,
2662                             &ns->rx_fragments);
2663         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2664                             pf->offset_loaded, &os->rx_oversize,
2665                             &ns->rx_oversize);
2666         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2667                             pf->offset_loaded, &os->rx_jabber,
2668                             &ns->rx_jabber);
2669         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2670                             I40E_GLPRT_PTC64L(hw->port),
2671                             pf->offset_loaded, &os->tx_size_64,
2672                             &ns->tx_size_64);
2673         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2674                             I40E_GLPRT_PTC127L(hw->port),
2675                             pf->offset_loaded, &os->tx_size_127,
2676                             &ns->tx_size_127);
2677         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2678                             I40E_GLPRT_PTC255L(hw->port),
2679                             pf->offset_loaded, &os->tx_size_255,
2680                             &ns->tx_size_255);
2681         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2682                             I40E_GLPRT_PTC511L(hw->port),
2683                             pf->offset_loaded, &os->tx_size_511,
2684                             &ns->tx_size_511);
2685         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2686                             I40E_GLPRT_PTC1023L(hw->port),
2687                             pf->offset_loaded, &os->tx_size_1023,
2688                             &ns->tx_size_1023);
2689         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2690                             I40E_GLPRT_PTC1522L(hw->port),
2691                             pf->offset_loaded, &os->tx_size_1522,
2692                             &ns->tx_size_1522);
2693         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2694                             I40E_GLPRT_PTC9522L(hw->port),
2695                             pf->offset_loaded, &os->tx_size_big,
2696                             &ns->tx_size_big);
2697         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2698                            pf->offset_loaded,
2699                            &os->fd_sb_match, &ns->fd_sb_match);
2700         /* GLPRT_MSPDC not supported */
2701         /* GLPRT_XEC not supported */
2702
2703         pf->offset_loaded = true;
2704
2705         if (pf->main_vsi)
2706                 i40e_update_vsi_stats(pf->main_vsi);
2707 }
2708
2709 /* Get all statistics of a port */
2710 static void
2711 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2712 {
2713         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2715         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2716         unsigned i;
2717
2718         /* call read registers - updates values, now write them to struct */
2719         i40e_read_stats_registers(pf, hw);
2720
2721         stats->ipackets = ns->eth.rx_unicast +
2722                         ns->eth.rx_multicast +
2723                         ns->eth.rx_broadcast -
2724                         ns->eth.rx_discards -
2725                         pf->main_vsi->eth_stats.rx_discards;
2726         stats->opackets = ns->eth.tx_unicast +
2727                         ns->eth.tx_multicast +
2728                         ns->eth.tx_broadcast;
2729         stats->ibytes   = ns->eth.rx_bytes;
2730         stats->obytes   = ns->eth.tx_bytes;
2731         stats->oerrors  = ns->eth.tx_errors +
2732                         pf->main_vsi->eth_stats.tx_errors;
2733
2734         /* Rx Errors */
2735         stats->imissed  = ns->eth.rx_discards +
2736                         pf->main_vsi->eth_stats.rx_discards;
2737         stats->ierrors  = ns->crc_errors +
2738                         ns->rx_length_errors + ns->rx_undersize +
2739                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2740
2741         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2742         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2743         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2744         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2745         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2746         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2747         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2748                     ns->eth.rx_unknown_protocol);
2749         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2750         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2751         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2752         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2753         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2754         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2755
2756         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2757                     ns->tx_dropped_link_down);
2758         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2759         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2760                     ns->illegal_bytes);
2761         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2762         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2763                     ns->mac_local_faults);
2764         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2765                     ns->mac_remote_faults);
2766         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2767                     ns->rx_length_errors);
2768         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2769         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2770         for (i = 0; i < 8; i++) {
2771                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2772                                 i, ns->priority_xon_rx[i]);
2773                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2774                                 i, ns->priority_xoff_rx[i]);
2775         }
2776         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2777         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2778         for (i = 0; i < 8; i++) {
2779                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2780                                 i, ns->priority_xon_tx[i]);
2781                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2782                                 i, ns->priority_xoff_tx[i]);
2783                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2784                                 i, ns->priority_xon_2_xoff[i]);
2785         }
2786         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2787         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2788         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2789         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2790         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2791         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2792         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2793         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2794         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2795         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2796         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2797         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2798         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2799         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2800         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2801         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2802         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2803         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2804         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2805                         ns->mac_short_packet_dropped);
2806         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2807                     ns->checksum_error);
2808         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2809         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2810 }
2811
2812 /* Reset the statistics */
2813 static void
2814 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2815 {
2816         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818
2819         /* Mark PF and VSI stats to update the offset, aka "reset" */
2820         pf->offset_loaded = false;
2821         if (pf->main_vsi)
2822                 pf->main_vsi->offset_loaded = false;
2823
2824         /* read the stats, reading current register values into offset */
2825         i40e_read_stats_registers(pf, hw);
2826 }
2827
2828 static uint32_t
2829 i40e_xstats_calc_num(void)
2830 {
2831         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2832                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2833                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2834 }
2835
2836 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2837                                      struct rte_eth_xstat_name *xstats_names,
2838                                      __rte_unused unsigned limit)
2839 {
2840         unsigned count = 0;
2841         unsigned i, prio;
2842
2843         if (xstats_names == NULL)
2844                 return i40e_xstats_calc_num();
2845
2846         /* Note: limit checked in rte_eth_xstats_names() */
2847
2848         /* Get stats from i40e_eth_stats struct */
2849         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2850                 snprintf(xstats_names[count].name,
2851                          sizeof(xstats_names[count].name),
2852                          "%s", rte_i40e_stats_strings[i].name);
2853                 count++;
2854         }
2855
2856         /* Get individiual stats from i40e_hw_port struct */
2857         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2858                 snprintf(xstats_names[count].name,
2859                         sizeof(xstats_names[count].name),
2860                          "%s", rte_i40e_hw_port_strings[i].name);
2861                 count++;
2862         }
2863
2864         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2865                 for (prio = 0; prio < 8; prio++) {
2866                         snprintf(xstats_names[count].name,
2867                                  sizeof(xstats_names[count].name),
2868                                  "rx_priority%u_%s", prio,
2869                                  rte_i40e_rxq_prio_strings[i].name);
2870                         count++;
2871                 }
2872         }
2873
2874         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2875                 for (prio = 0; prio < 8; prio++) {
2876                         snprintf(xstats_names[count].name,
2877                                  sizeof(xstats_names[count].name),
2878                                  "tx_priority%u_%s", prio,
2879                                  rte_i40e_txq_prio_strings[i].name);
2880                         count++;
2881                 }
2882         }
2883         return count;
2884 }
2885
2886 static int
2887 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2888                     unsigned n)
2889 {
2890         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2892         unsigned i, count, prio;
2893         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2894
2895         count = i40e_xstats_calc_num();
2896         if (n < count)
2897                 return count;
2898
2899         i40e_read_stats_registers(pf, hw);
2900
2901         if (xstats == NULL)
2902                 return 0;
2903
2904         count = 0;
2905
2906         /* Get stats from i40e_eth_stats struct */
2907         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2908                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2909                         rte_i40e_stats_strings[i].offset);
2910                 xstats[count].id = count;
2911                 count++;
2912         }
2913
2914         /* Get individiual stats from i40e_hw_port struct */
2915         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2916                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2917                         rte_i40e_hw_port_strings[i].offset);
2918                 xstats[count].id = count;
2919                 count++;
2920         }
2921
2922         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2923                 for (prio = 0; prio < 8; prio++) {
2924                         xstats[count].value =
2925                                 *(uint64_t *)(((char *)hw_stats) +
2926                                 rte_i40e_rxq_prio_strings[i].offset +
2927                                 (sizeof(uint64_t) * prio));
2928                         xstats[count].id = count;
2929                         count++;
2930                 }
2931         }
2932
2933         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2934                 for (prio = 0; prio < 8; prio++) {
2935                         xstats[count].value =
2936                                 *(uint64_t *)(((char *)hw_stats) +
2937                                 rte_i40e_txq_prio_strings[i].offset +
2938                                 (sizeof(uint64_t) * prio));
2939                         xstats[count].id = count;
2940                         count++;
2941                 }
2942         }
2943
2944         return count;
2945 }
2946
2947 static int
2948 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2949                                  __rte_unused uint16_t queue_id,
2950                                  __rte_unused uint8_t stat_idx,
2951                                  __rte_unused uint8_t is_rx)
2952 {
2953         PMD_INIT_FUNC_TRACE();
2954
2955         return -ENOSYS;
2956 }
2957
2958 static int
2959 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2960 {
2961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962         u32 full_ver;
2963         u8 ver, patch;
2964         u16 build;
2965         int ret;
2966
2967         full_ver = hw->nvm.oem_ver;
2968         ver = (u8)(full_ver >> 24);
2969         build = (u16)((full_ver >> 8) & 0xffff);
2970         patch = (u8)(full_ver & 0xff);
2971
2972         ret = snprintf(fw_version, fw_size,
2973                  "%d.%d%d 0x%08x %d.%d.%d",
2974                  ((hw->nvm.version >> 12) & 0xf),
2975                  ((hw->nvm.version >> 4) & 0xff),
2976                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2977                  ver, build, patch);
2978
2979         ret += 1; /* add the size of '\0' */
2980         if (fw_size < (u32)ret)
2981                 return ret;
2982         else
2983                 return 0;
2984 }
2985
2986 static void
2987 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2988 {
2989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2991         struct i40e_vsi *vsi = pf->main_vsi;
2992         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2993
2994         dev_info->pci_dev = pci_dev;
2995         dev_info->max_rx_queues = vsi->nb_qps;
2996         dev_info->max_tx_queues = vsi->nb_qps;
2997         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2998         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2999         dev_info->max_mac_addrs = vsi->max_macaddrs;
3000         dev_info->max_vfs = pci_dev->max_vfs;
3001         dev_info->rx_offload_capa =
3002                 DEV_RX_OFFLOAD_VLAN_STRIP |
3003                 DEV_RX_OFFLOAD_QINQ_STRIP |
3004                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3005                 DEV_RX_OFFLOAD_UDP_CKSUM |
3006                 DEV_RX_OFFLOAD_TCP_CKSUM;
3007         dev_info->tx_offload_capa =
3008                 DEV_TX_OFFLOAD_VLAN_INSERT |
3009                 DEV_TX_OFFLOAD_QINQ_INSERT |
3010                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3011                 DEV_TX_OFFLOAD_UDP_CKSUM |
3012                 DEV_TX_OFFLOAD_TCP_CKSUM |
3013                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3014                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3015                 DEV_TX_OFFLOAD_TCP_TSO |
3016                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3017                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3018                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3019                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3020         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3021                                                 sizeof(uint32_t);
3022         dev_info->reta_size = pf->hash_lut_size;
3023         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
3024
3025         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3026                 .rx_thresh = {
3027                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3028                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3029                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3030                 },
3031                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3032                 .rx_drop_en = 0,
3033         };
3034
3035         dev_info->default_txconf = (struct rte_eth_txconf) {
3036                 .tx_thresh = {
3037                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3038                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3039                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3040                 },
3041                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3042                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3043                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3044                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3045         };
3046
3047         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3048                 .nb_max = I40E_MAX_RING_DESC,
3049                 .nb_min = I40E_MIN_RING_DESC,
3050                 .nb_align = I40E_ALIGN_RING_DESC,
3051         };
3052
3053         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3054                 .nb_max = I40E_MAX_RING_DESC,
3055                 .nb_min = I40E_MIN_RING_DESC,
3056                 .nb_align = I40E_ALIGN_RING_DESC,
3057                 .nb_seg_max = I40E_TX_MAX_SEG,
3058                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3059         };
3060
3061         if (pf->flags & I40E_FLAG_VMDQ) {
3062                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3063                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3064                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3065                                                 pf->max_nb_vmdq_vsi;
3066                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3067                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3068                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3069         }
3070
3071         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3072                 /* For XL710 */
3073                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3074         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3075                 /* For XXV710 */
3076                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3077         else
3078                 /* For X710 */
3079                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3080 }
3081
3082 static int
3083 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3084 {
3085         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3086         struct i40e_vsi *vsi = pf->main_vsi;
3087         PMD_INIT_FUNC_TRACE();
3088
3089         if (on)
3090                 return i40e_vsi_add_vlan(vsi, vlan_id);
3091         else
3092                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3093 }
3094
3095 static int
3096 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3097                                 enum rte_vlan_type vlan_type,
3098                                 uint16_t tpid, int qinq)
3099 {
3100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3101         uint64_t reg_r = 0;
3102         uint64_t reg_w = 0;
3103         uint16_t reg_id = 3;
3104         int ret;
3105
3106         if (qinq) {
3107                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3108                         reg_id = 2;
3109         }
3110
3111         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3112                                           &reg_r, NULL);
3113         if (ret != I40E_SUCCESS) {
3114                 PMD_DRV_LOG(ERR,
3115                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3116                            reg_id);
3117                 return -EIO;
3118         }
3119         PMD_DRV_LOG(DEBUG,
3120                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3121                     reg_id, reg_r);
3122
3123         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3124         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3125         if (reg_r == reg_w) {
3126                 PMD_DRV_LOG(DEBUG, "No need to write");
3127                 return 0;
3128         }
3129
3130         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3131                                            reg_w, NULL);
3132         if (ret != I40E_SUCCESS) {
3133                 PMD_DRV_LOG(ERR,
3134                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3135                             reg_id);
3136                 return -EIO;
3137         }
3138         PMD_DRV_LOG(DEBUG,
3139                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3140                     reg_w, reg_id);
3141
3142         return 0;
3143 }
3144
3145 static int
3146 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3147                    enum rte_vlan_type vlan_type,
3148                    uint16_t tpid)
3149 {
3150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3151         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3152         int ret = 0;
3153
3154         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3155              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3156             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3157                 PMD_DRV_LOG(ERR,
3158                             "Unsupported vlan type.");
3159                 return -EINVAL;
3160         }
3161         /* 802.1ad frames ability is added in NVM API 1.7*/
3162         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3163                 if (qinq) {
3164                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3165                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3166                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3167                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3168                 } else {
3169                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3170                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3171                 }
3172                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3173                 if (ret != I40E_SUCCESS) {
3174                         PMD_DRV_LOG(ERR,
3175                                     "Set switch config failed aq_err: %d",
3176                                     hw->aq.asq_last_status);
3177                         ret = -EIO;
3178                 }
3179         } else
3180                 /* If NVM API < 1.7, keep the register setting */
3181                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3182                                                       tpid, qinq);
3183
3184         return ret;
3185 }
3186
3187 static void
3188 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3189 {
3190         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3191         struct i40e_vsi *vsi = pf->main_vsi;
3192
3193         if (mask & ETH_VLAN_FILTER_MASK) {
3194                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3195                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3196                 else
3197                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3198         }
3199
3200         if (mask & ETH_VLAN_STRIP_MASK) {
3201                 /* Enable or disable VLAN stripping */
3202                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3203                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3204                 else
3205                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3206         }
3207
3208         if (mask & ETH_VLAN_EXTEND_MASK) {
3209                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3210                         i40e_vsi_config_double_vlan(vsi, TRUE);
3211                         /* Set global registers with default ethertype. */
3212                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3213                                            ETHER_TYPE_VLAN);
3214                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3215                                            ETHER_TYPE_VLAN);
3216                 }
3217                 else
3218                         i40e_vsi_config_double_vlan(vsi, FALSE);
3219         }
3220 }
3221
3222 static void
3223 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3224                           __rte_unused uint16_t queue,
3225                           __rte_unused int on)
3226 {
3227         PMD_INIT_FUNC_TRACE();
3228 }
3229
3230 static int
3231 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3232 {
3233         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3234         struct i40e_vsi *vsi = pf->main_vsi;
3235         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3236         struct i40e_vsi_vlan_pvid_info info;
3237
3238         memset(&info, 0, sizeof(info));
3239         info.on = on;
3240         if (info.on)
3241                 info.config.pvid = pvid;
3242         else {
3243                 info.config.reject.tagged =
3244                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3245                 info.config.reject.untagged =
3246                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3247         }
3248
3249         return i40e_vsi_vlan_pvid_set(vsi, &info);
3250 }
3251
3252 static int
3253 i40e_dev_led_on(struct rte_eth_dev *dev)
3254 {
3255         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3256         uint32_t mode = i40e_led_get(hw);
3257
3258         if (mode == 0)
3259                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3260
3261         return 0;
3262 }
3263
3264 static int
3265 i40e_dev_led_off(struct rte_eth_dev *dev)
3266 {
3267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268         uint32_t mode = i40e_led_get(hw);
3269
3270         if (mode != 0)
3271                 i40e_led_set(hw, 0, false);
3272
3273         return 0;
3274 }
3275
3276 static int
3277 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3278 {
3279         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3280         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3281
3282         fc_conf->pause_time = pf->fc_conf.pause_time;
3283
3284         /* read out from register, in case they are modified by other port */
3285         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3286                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3287         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3288                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3289
3290         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3291         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3292
3293          /* Return current mode according to actual setting*/
3294         switch (hw->fc.current_mode) {
3295         case I40E_FC_FULL:
3296                 fc_conf->mode = RTE_FC_FULL;
3297                 break;
3298         case I40E_FC_TX_PAUSE:
3299                 fc_conf->mode = RTE_FC_TX_PAUSE;
3300                 break;
3301         case I40E_FC_RX_PAUSE:
3302                 fc_conf->mode = RTE_FC_RX_PAUSE;
3303                 break;
3304         case I40E_FC_NONE:
3305         default:
3306                 fc_conf->mode = RTE_FC_NONE;
3307         };
3308
3309         return 0;
3310 }
3311
3312 static int
3313 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3314 {
3315         uint32_t mflcn_reg, fctrl_reg, reg;
3316         uint32_t max_high_water;
3317         uint8_t i, aq_failure;
3318         int err;
3319         struct i40e_hw *hw;
3320         struct i40e_pf *pf;
3321         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3322                 [RTE_FC_NONE] = I40E_FC_NONE,
3323                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3324                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3325                 [RTE_FC_FULL] = I40E_FC_FULL
3326         };
3327
3328         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3329
3330         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3331         if ((fc_conf->high_water > max_high_water) ||
3332                         (fc_conf->high_water < fc_conf->low_water)) {
3333                 PMD_INIT_LOG(ERR,
3334                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3335                         max_high_water);
3336                 return -EINVAL;
3337         }
3338
3339         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3341         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3342
3343         pf->fc_conf.pause_time = fc_conf->pause_time;
3344         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3345         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3346
3347         PMD_INIT_FUNC_TRACE();
3348
3349         /* All the link flow control related enable/disable register
3350          * configuration is handle by the F/W
3351          */
3352         err = i40e_set_fc(hw, &aq_failure, true);
3353         if (err < 0)
3354                 return -ENOSYS;
3355
3356         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3357                 /* Configure flow control refresh threshold,
3358                  * the value for stat_tx_pause_refresh_timer[8]
3359                  * is used for global pause operation.
3360                  */
3361
3362                 I40E_WRITE_REG(hw,
3363                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3364                                pf->fc_conf.pause_time);
3365
3366                 /* configure the timer value included in transmitted pause
3367                  * frame,
3368                  * the value for stat_tx_pause_quanta[8] is used for global
3369                  * pause operation
3370                  */
3371                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3372                                pf->fc_conf.pause_time);
3373
3374                 fctrl_reg = I40E_READ_REG(hw,
3375                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3376
3377                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3378                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3379                 else
3380                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3381
3382                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3383                                fctrl_reg);
3384         } else {
3385                 /* Configure pause time (2 TCs per register) */
3386                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3387                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3388                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3389
3390                 /* Configure flow control refresh threshold value */
3391                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3392                                pf->fc_conf.pause_time / 2);
3393
3394                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3395
3396                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3397                  *depending on configuration
3398                  */
3399                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3400                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3401                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3402                 } else {
3403                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3404                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3405                 }
3406
3407                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3408         }
3409
3410         /* config the water marker both based on the packets and bytes */
3411         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3412                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3413                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3414         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3415                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3416                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3417         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3418                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3419                        << I40E_KILOSHIFT);
3420         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3421                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3422                        << I40E_KILOSHIFT);
3423
3424         I40E_WRITE_FLUSH(hw);
3425
3426         return 0;
3427 }
3428
3429 static int
3430 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3431                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3432 {
3433         PMD_INIT_FUNC_TRACE();
3434
3435         return -ENOSYS;
3436 }
3437
3438 /* Add a MAC address, and update filters */
3439 static int
3440 i40e_macaddr_add(struct rte_eth_dev *dev,
3441                  struct ether_addr *mac_addr,
3442                  __rte_unused uint32_t index,
3443                  uint32_t pool)
3444 {
3445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3446         struct i40e_mac_filter_info mac_filter;
3447         struct i40e_vsi *vsi;
3448         int ret;
3449
3450         /* If VMDQ not enabled or configured, return */
3451         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3452                           !pf->nb_cfg_vmdq_vsi)) {
3453                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3454                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3455                         pool);
3456                 return -ENOTSUP;
3457         }
3458
3459         if (pool > pf->nb_cfg_vmdq_vsi) {
3460                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3461                                 pool, pf->nb_cfg_vmdq_vsi);
3462                 return -EINVAL;
3463         }
3464
3465         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3466         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3467                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3468         else
3469                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3470
3471         if (pool == 0)
3472                 vsi = pf->main_vsi;
3473         else
3474                 vsi = pf->vmdq[pool - 1].vsi;
3475
3476         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3477         if (ret != I40E_SUCCESS) {
3478                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3479                 return -ENODEV;
3480         }
3481         return 0;
3482 }
3483
3484 /* Remove a MAC address, and update filters */
3485 static void
3486 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3487 {
3488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3489         struct i40e_vsi *vsi;
3490         struct rte_eth_dev_data *data = dev->data;
3491         struct ether_addr *macaddr;
3492         int ret;
3493         uint32_t i;
3494         uint64_t pool_sel;
3495
3496         macaddr = &(data->mac_addrs[index]);
3497
3498         pool_sel = dev->data->mac_pool_sel[index];
3499
3500         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3501                 if (pool_sel & (1ULL << i)) {
3502                         if (i == 0)
3503                                 vsi = pf->main_vsi;
3504                         else {
3505                                 /* No VMDQ pool enabled or configured */
3506                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3507                                         (i > pf->nb_cfg_vmdq_vsi)) {
3508                                         PMD_DRV_LOG(ERR,
3509                                                 "No VMDQ pool enabled/configured");
3510                                         return;
3511                                 }
3512                                 vsi = pf->vmdq[i - 1].vsi;
3513                         }
3514                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3515
3516                         if (ret) {
3517                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3518                                 return;
3519                         }
3520                 }
3521         }
3522 }
3523
3524 /* Set perfect match or hash match of MAC and VLAN for a VF */
3525 static int
3526 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3527                  struct rte_eth_mac_filter *filter,
3528                  bool add)
3529 {
3530         struct i40e_hw *hw;
3531         struct i40e_mac_filter_info mac_filter;
3532         struct ether_addr old_mac;
3533         struct ether_addr *new_mac;
3534         struct i40e_pf_vf *vf = NULL;
3535         uint16_t vf_id;
3536         int ret;
3537
3538         if (pf == NULL) {
3539                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3540                 return -EINVAL;
3541         }
3542         hw = I40E_PF_TO_HW(pf);
3543
3544         if (filter == NULL) {
3545                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3546                 return -EINVAL;
3547         }
3548
3549         new_mac = &filter->mac_addr;
3550
3551         if (is_zero_ether_addr(new_mac)) {
3552                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3553                 return -EINVAL;
3554         }
3555
3556         vf_id = filter->dst_id;
3557
3558         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3559                 PMD_DRV_LOG(ERR, "Invalid argument.");
3560                 return -EINVAL;
3561         }
3562         vf = &pf->vfs[vf_id];
3563
3564         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3565                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3566                 return -EINVAL;
3567         }
3568
3569         if (add) {
3570                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3571                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3572                                 ETHER_ADDR_LEN);
3573                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3574                                  ETHER_ADDR_LEN);
3575
3576                 mac_filter.filter_type = filter->filter_type;
3577                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3578                 if (ret != I40E_SUCCESS) {
3579                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3580                         return -1;
3581                 }
3582                 ether_addr_copy(new_mac, &pf->dev_addr);
3583         } else {
3584                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3585                                 ETHER_ADDR_LEN);
3586                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3587                 if (ret != I40E_SUCCESS) {
3588                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3589                         return -1;
3590                 }
3591
3592                 /* Clear device address as it has been removed */
3593                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3594                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3595         }
3596
3597         return 0;
3598 }
3599
3600 /* MAC filter handle */
3601 static int
3602 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3603                 void *arg)
3604 {
3605         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3606         struct rte_eth_mac_filter *filter;
3607         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3608         int ret = I40E_NOT_SUPPORTED;
3609
3610         filter = (struct rte_eth_mac_filter *)(arg);
3611
3612         switch (filter_op) {
3613         case RTE_ETH_FILTER_NOP:
3614                 ret = I40E_SUCCESS;
3615                 break;
3616         case RTE_ETH_FILTER_ADD:
3617                 i40e_pf_disable_irq0(hw);
3618                 if (filter->is_vf)
3619                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3620                 i40e_pf_enable_irq0(hw);
3621                 break;
3622         case RTE_ETH_FILTER_DELETE:
3623                 i40e_pf_disable_irq0(hw);
3624                 if (filter->is_vf)
3625                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3626                 i40e_pf_enable_irq0(hw);
3627                 break;
3628         default:
3629                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3630                 ret = I40E_ERR_PARAM;
3631                 break;
3632         }
3633
3634         return ret;
3635 }
3636
3637 static int
3638 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3639 {
3640         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3641         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3642         int ret;
3643
3644         if (!lut)
3645                 return -EINVAL;
3646
3647         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3648                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3649                                           lut, lut_size);
3650                 if (ret) {
3651                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3652                         return ret;
3653                 }
3654         } else {
3655                 uint32_t *lut_dw = (uint32_t *)lut;
3656                 uint16_t i, lut_size_dw = lut_size / 4;
3657
3658                 for (i = 0; i < lut_size_dw; i++)
3659                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3660         }
3661
3662         return 0;
3663 }
3664
3665 static int
3666 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3667 {
3668         struct i40e_pf *pf;
3669         struct i40e_hw *hw;
3670         int ret;
3671
3672         if (!vsi || !lut)
3673                 return -EINVAL;
3674
3675         pf = I40E_VSI_TO_PF(vsi);
3676         hw = I40E_VSI_TO_HW(vsi);
3677
3678         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3679                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3680                                           lut, lut_size);
3681                 if (ret) {
3682                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3683                         return ret;
3684                 }
3685         } else {
3686                 uint32_t *lut_dw = (uint32_t *)lut;
3687                 uint16_t i, lut_size_dw = lut_size / 4;
3688
3689                 for (i = 0; i < lut_size_dw; i++)
3690                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3691                 I40E_WRITE_FLUSH(hw);
3692         }
3693
3694         return 0;
3695 }
3696
3697 static int
3698 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3699                          struct rte_eth_rss_reta_entry64 *reta_conf,
3700                          uint16_t reta_size)
3701 {
3702         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3703         uint16_t i, lut_size = pf->hash_lut_size;
3704         uint16_t idx, shift;
3705         uint8_t *lut;
3706         int ret;
3707
3708         if (reta_size != lut_size ||
3709                 reta_size > ETH_RSS_RETA_SIZE_512) {
3710                 PMD_DRV_LOG(ERR,
3711                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3712                         reta_size, lut_size);
3713                 return -EINVAL;
3714         }
3715
3716         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3717         if (!lut) {
3718                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3719                 return -ENOMEM;
3720         }
3721         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3722         if (ret)
3723                 goto out;
3724         for (i = 0; i < reta_size; i++) {
3725                 idx = i / RTE_RETA_GROUP_SIZE;
3726                 shift = i % RTE_RETA_GROUP_SIZE;
3727                 if (reta_conf[idx].mask & (1ULL << shift))
3728                         lut[i] = reta_conf[idx].reta[shift];
3729         }
3730         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3731
3732 out:
3733         rte_free(lut);
3734
3735         return ret;
3736 }
3737
3738 static int
3739 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3740                         struct rte_eth_rss_reta_entry64 *reta_conf,
3741                         uint16_t reta_size)
3742 {
3743         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3744         uint16_t i, lut_size = pf->hash_lut_size;
3745         uint16_t idx, shift;
3746         uint8_t *lut;
3747         int ret;
3748
3749         if (reta_size != lut_size ||
3750                 reta_size > ETH_RSS_RETA_SIZE_512) {
3751                 PMD_DRV_LOG(ERR,
3752                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3753                         reta_size, lut_size);
3754                 return -EINVAL;
3755         }
3756
3757         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3758         if (!lut) {
3759                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3760                 return -ENOMEM;
3761         }
3762
3763         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3764         if (ret)
3765                 goto out;
3766         for (i = 0; i < reta_size; i++) {
3767                 idx = i / RTE_RETA_GROUP_SIZE;
3768                 shift = i % RTE_RETA_GROUP_SIZE;
3769                 if (reta_conf[idx].mask & (1ULL << shift))
3770                         reta_conf[idx].reta[shift] = lut[i];
3771         }
3772
3773 out:
3774         rte_free(lut);
3775
3776         return ret;
3777 }
3778
3779 /**
3780  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3781  * @hw:   pointer to the HW structure
3782  * @mem:  pointer to mem struct to fill out
3783  * @size: size of memory requested
3784  * @alignment: what to align the allocation to
3785  **/
3786 enum i40e_status_code
3787 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3788                         struct i40e_dma_mem *mem,
3789                         u64 size,
3790                         u32 alignment)
3791 {
3792         const struct rte_memzone *mz = NULL;
3793         char z_name[RTE_MEMZONE_NAMESIZE];
3794
3795         if (!mem)
3796                 return I40E_ERR_PARAM;
3797
3798         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3799         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3800                                          alignment, RTE_PGSIZE_2M);
3801         if (!mz)
3802                 return I40E_ERR_NO_MEMORY;
3803
3804         mem->size = size;
3805         mem->va = mz->addr;
3806         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3807         mem->zone = (const void *)mz;
3808         PMD_DRV_LOG(DEBUG,
3809                 "memzone %s allocated with physical address: %"PRIu64,
3810                 mz->name, mem->pa);
3811
3812         return I40E_SUCCESS;
3813 }
3814
3815 /**
3816  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3817  * @hw:   pointer to the HW structure
3818  * @mem:  ptr to mem struct to free
3819  **/
3820 enum i40e_status_code
3821 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3822                     struct i40e_dma_mem *mem)
3823 {
3824         if (!mem)
3825                 return I40E_ERR_PARAM;
3826
3827         PMD_DRV_LOG(DEBUG,
3828                 "memzone %s to be freed with physical address: %"PRIu64,
3829                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3830         rte_memzone_free((const struct rte_memzone *)mem->zone);
3831         mem->zone = NULL;
3832         mem->va = NULL;
3833         mem->pa = (u64)0;
3834
3835         return I40E_SUCCESS;
3836 }
3837
3838 /**
3839  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3840  * @hw:   pointer to the HW structure
3841  * @mem:  pointer to mem struct to fill out
3842  * @size: size of memory requested
3843  **/
3844 enum i40e_status_code
3845 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3846                          struct i40e_virt_mem *mem,
3847                          u32 size)
3848 {
3849         if (!mem)
3850                 return I40E_ERR_PARAM;
3851
3852         mem->size = size;
3853         mem->va = rte_zmalloc("i40e", size, 0);
3854
3855         if (mem->va)
3856                 return I40E_SUCCESS;
3857         else
3858                 return I40E_ERR_NO_MEMORY;
3859 }
3860
3861 /**
3862  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3863  * @hw:   pointer to the HW structure
3864  * @mem:  pointer to mem struct to free
3865  **/
3866 enum i40e_status_code
3867 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3868                      struct i40e_virt_mem *mem)
3869 {
3870         if (!mem)
3871                 return I40E_ERR_PARAM;
3872
3873         rte_free(mem->va);
3874         mem->va = NULL;
3875
3876         return I40E_SUCCESS;
3877 }
3878
3879 void
3880 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3881 {
3882         rte_spinlock_init(&sp->spinlock);
3883 }
3884
3885 void
3886 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3887 {
3888         rte_spinlock_lock(&sp->spinlock);
3889 }
3890
3891 void
3892 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3893 {
3894         rte_spinlock_unlock(&sp->spinlock);
3895 }
3896
3897 void
3898 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3899 {
3900         return;
3901 }
3902
3903 /**
3904  * Get the hardware capabilities, which will be parsed
3905  * and saved into struct i40e_hw.
3906  */
3907 static int
3908 i40e_get_cap(struct i40e_hw *hw)
3909 {
3910         struct i40e_aqc_list_capabilities_element_resp *buf;
3911         uint16_t len, size = 0;
3912         int ret;
3913
3914         /* Calculate a huge enough buff for saving response data temporarily */
3915         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3916                                                 I40E_MAX_CAP_ELE_NUM;
3917         buf = rte_zmalloc("i40e", len, 0);
3918         if (!buf) {
3919                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3920                 return I40E_ERR_NO_MEMORY;
3921         }
3922
3923         /* Get, parse the capabilities and save it to hw */
3924         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3925                         i40e_aqc_opc_list_func_capabilities, NULL);
3926         if (ret != I40E_SUCCESS)
3927                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3928
3929         /* Free the temporary buffer after being used */
3930         rte_free(buf);
3931
3932         return ret;
3933 }
3934
3935 static int
3936 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3937 {
3938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3939         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3940         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3941         uint16_t qp_count = 0, vsi_count = 0;
3942
3943         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3944                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3945                 return -EINVAL;
3946         }
3947         /* Add the parameter init for LFC */
3948         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3949         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3950         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3951
3952         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3953         pf->max_num_vsi = hw->func_caps.num_vsis;
3954         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3955         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3956         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3957
3958         /* FDir queue/VSI allocation */
3959         pf->fdir_qp_offset = 0;
3960         if (hw->func_caps.fd) {
3961                 pf->flags |= I40E_FLAG_FDIR;
3962                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3963         } else {
3964                 pf->fdir_nb_qps = 0;
3965         }
3966         qp_count += pf->fdir_nb_qps;
3967         vsi_count += 1;
3968
3969         /* LAN queue/VSI allocation */
3970         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3971         if (!hw->func_caps.rss) {
3972                 pf->lan_nb_qps = 1;
3973         } else {
3974                 pf->flags |= I40E_FLAG_RSS;
3975                 if (hw->mac.type == I40E_MAC_X722)
3976                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3977                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3978         }
3979         qp_count += pf->lan_nb_qps;
3980         vsi_count += 1;
3981
3982         /* VF queue/VSI allocation */
3983         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3984         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3985                 pf->flags |= I40E_FLAG_SRIOV;
3986                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3987                 pf->vf_num = pci_dev->max_vfs;
3988                 PMD_DRV_LOG(DEBUG,
3989                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3990                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3991         } else {
3992                 pf->vf_nb_qps = 0;
3993                 pf->vf_num = 0;
3994         }
3995         qp_count += pf->vf_nb_qps * pf->vf_num;
3996         vsi_count += pf->vf_num;
3997
3998         /* VMDq queue/VSI allocation */
3999         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4000         pf->vmdq_nb_qps = 0;
4001         pf->max_nb_vmdq_vsi = 0;
4002         if (hw->func_caps.vmdq) {
4003                 if (qp_count < hw->func_caps.num_tx_qp &&
4004                         vsi_count < hw->func_caps.num_vsis) {
4005                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4006                                 qp_count) / pf->vmdq_nb_qp_max;
4007
4008                         /* Limit the maximum number of VMDq vsi to the maximum
4009                          * ethdev can support
4010                          */
4011                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4012                                 hw->func_caps.num_vsis - vsi_count);
4013                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4014                                 ETH_64_POOLS);
4015                         if (pf->max_nb_vmdq_vsi) {
4016                                 pf->flags |= I40E_FLAG_VMDQ;
4017                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4018                                 PMD_DRV_LOG(DEBUG,
4019                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4020                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4021                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4022                         } else {
4023                                 PMD_DRV_LOG(INFO,
4024                                         "No enough queues left for VMDq");
4025                         }
4026                 } else {
4027                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4028                 }
4029         }
4030         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4031         vsi_count += pf->max_nb_vmdq_vsi;
4032
4033         if (hw->func_caps.dcb)
4034                 pf->flags |= I40E_FLAG_DCB;
4035
4036         if (qp_count > hw->func_caps.num_tx_qp) {
4037                 PMD_DRV_LOG(ERR,
4038                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4039                         qp_count, hw->func_caps.num_tx_qp);
4040                 return -EINVAL;
4041         }
4042         if (vsi_count > hw->func_caps.num_vsis) {
4043                 PMD_DRV_LOG(ERR,
4044                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4045                         vsi_count, hw->func_caps.num_vsis);
4046                 return -EINVAL;
4047         }
4048
4049         return 0;
4050 }
4051
4052 static int
4053 i40e_pf_get_switch_config(struct i40e_pf *pf)
4054 {
4055         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4056         struct i40e_aqc_get_switch_config_resp *switch_config;
4057         struct i40e_aqc_switch_config_element_resp *element;
4058         uint16_t start_seid = 0, num_reported;
4059         int ret;
4060
4061         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4062                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4063         if (!switch_config) {
4064                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4065                 return -ENOMEM;
4066         }
4067
4068         /* Get the switch configurations */
4069         ret = i40e_aq_get_switch_config(hw, switch_config,
4070                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4071         if (ret != I40E_SUCCESS) {
4072                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4073                 goto fail;
4074         }
4075         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4076         if (num_reported != 1) { /* The number should be 1 */
4077                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4078                 goto fail;
4079         }
4080
4081         /* Parse the switch configuration elements */
4082         element = &(switch_config->element[0]);
4083         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4084                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4085                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4086         } else
4087                 PMD_DRV_LOG(INFO, "Unknown element type");
4088
4089 fail:
4090         rte_free(switch_config);
4091
4092         return ret;
4093 }
4094
4095 static int
4096 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4097                         uint32_t num)
4098 {
4099         struct pool_entry *entry;
4100
4101         if (pool == NULL || num == 0)
4102                 return -EINVAL;
4103
4104         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4105         if (entry == NULL) {
4106                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4107                 return -ENOMEM;
4108         }
4109
4110         /* queue heap initialize */
4111         pool->num_free = num;
4112         pool->num_alloc = 0;
4113         pool->base = base;
4114         LIST_INIT(&pool->alloc_list);
4115         LIST_INIT(&pool->free_list);
4116
4117         /* Initialize element  */
4118         entry->base = 0;
4119         entry->len = num;
4120
4121         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4122         return 0;
4123 }
4124
4125 static void
4126 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4127 {
4128         struct pool_entry *entry, *next_entry;
4129
4130         if (pool == NULL)
4131                 return;
4132
4133         for (entry = LIST_FIRST(&pool->alloc_list);
4134                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4135                         entry = next_entry) {
4136                 LIST_REMOVE(entry, next);
4137                 rte_free(entry);
4138         }
4139
4140         for (entry = LIST_FIRST(&pool->free_list);
4141                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4142                         entry = next_entry) {
4143                 LIST_REMOVE(entry, next);
4144                 rte_free(entry);
4145         }
4146
4147         pool->num_free = 0;
4148         pool->num_alloc = 0;
4149         pool->base = 0;
4150         LIST_INIT(&pool->alloc_list);
4151         LIST_INIT(&pool->free_list);
4152 }
4153
4154 static int
4155 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4156                        uint32_t base)
4157 {
4158         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4159         uint32_t pool_offset;
4160         int insert;
4161
4162         if (pool == NULL) {
4163                 PMD_DRV_LOG(ERR, "Invalid parameter");
4164                 return -EINVAL;
4165         }
4166
4167         pool_offset = base - pool->base;
4168         /* Lookup in alloc list */
4169         LIST_FOREACH(entry, &pool->alloc_list, next) {
4170                 if (entry->base == pool_offset) {
4171                         valid_entry = entry;
4172                         LIST_REMOVE(entry, next);
4173                         break;
4174                 }
4175         }
4176
4177         /* Not find, return */
4178         if (valid_entry == NULL) {
4179                 PMD_DRV_LOG(ERR, "Failed to find entry");
4180                 return -EINVAL;
4181         }
4182
4183         /**
4184          * Found it, move it to free list  and try to merge.
4185          * In order to make merge easier, always sort it by qbase.
4186          * Find adjacent prev and last entries.
4187          */
4188         prev = next = NULL;
4189         LIST_FOREACH(entry, &pool->free_list, next) {
4190                 if (entry->base > valid_entry->base) {
4191                         next = entry;
4192                         break;
4193                 }
4194                 prev = entry;
4195         }
4196
4197         insert = 0;
4198         /* Try to merge with next one*/
4199         if (next != NULL) {
4200                 /* Merge with next one */
4201                 if (valid_entry->base + valid_entry->len == next->base) {
4202                         next->base = valid_entry->base;
4203                         next->len += valid_entry->len;
4204                         rte_free(valid_entry);
4205                         valid_entry = next;
4206                         insert = 1;
4207                 }
4208         }
4209
4210         if (prev != NULL) {
4211                 /* Merge with previous one */
4212                 if (prev->base + prev->len == valid_entry->base) {
4213                         prev->len += valid_entry->len;
4214                         /* If it merge with next one, remove next node */
4215                         if (insert == 1) {
4216                                 LIST_REMOVE(valid_entry, next);
4217                                 rte_free(valid_entry);
4218                         } else {
4219                                 rte_free(valid_entry);
4220                                 insert = 1;
4221                         }
4222                 }
4223         }
4224
4225         /* Not find any entry to merge, insert */
4226         if (insert == 0) {
4227                 if (prev != NULL)
4228                         LIST_INSERT_AFTER(prev, valid_entry, next);
4229                 else if (next != NULL)
4230                         LIST_INSERT_BEFORE(next, valid_entry, next);
4231                 else /* It's empty list, insert to head */
4232                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4233         }
4234
4235         pool->num_free += valid_entry->len;
4236         pool->num_alloc -= valid_entry->len;
4237
4238         return 0;
4239 }
4240
4241 static int
4242 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4243                        uint16_t num)
4244 {
4245         struct pool_entry *entry, *valid_entry;
4246
4247         if (pool == NULL || num == 0) {
4248                 PMD_DRV_LOG(ERR, "Invalid parameter");
4249                 return -EINVAL;
4250         }
4251
4252         if (pool->num_free < num) {
4253                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4254                             num, pool->num_free);
4255                 return -ENOMEM;
4256         }
4257
4258         valid_entry = NULL;
4259         /* Lookup  in free list and find most fit one */
4260         LIST_FOREACH(entry, &pool->free_list, next) {
4261                 if (entry->len >= num) {
4262                         /* Find best one */
4263                         if (entry->len == num) {
4264                                 valid_entry = entry;
4265                                 break;
4266                         }
4267                         if (valid_entry == NULL || valid_entry->len > entry->len)
4268                                 valid_entry = entry;
4269                 }
4270         }
4271
4272         /* Not find one to satisfy the request, return */
4273         if (valid_entry == NULL) {
4274                 PMD_DRV_LOG(ERR, "No valid entry found");
4275                 return -ENOMEM;
4276         }
4277         /**
4278          * The entry have equal queue number as requested,
4279          * remove it from alloc_list.
4280          */
4281         if (valid_entry->len == num) {
4282                 LIST_REMOVE(valid_entry, next);
4283         } else {
4284                 /**
4285                  * The entry have more numbers than requested,
4286                  * create a new entry for alloc_list and minus its
4287                  * queue base and number in free_list.
4288                  */
4289                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4290                 if (entry == NULL) {
4291                         PMD_DRV_LOG(ERR,
4292                                 "Failed to allocate memory for resource pool");
4293                         return -ENOMEM;
4294                 }
4295                 entry->base = valid_entry->base;
4296                 entry->len = num;
4297                 valid_entry->base += num;
4298                 valid_entry->len -= num;
4299                 valid_entry = entry;
4300         }
4301
4302         /* Insert it into alloc list, not sorted */
4303         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4304
4305         pool->num_free -= valid_entry->len;
4306         pool->num_alloc += valid_entry->len;
4307
4308         return valid_entry->base + pool->base;
4309 }
4310
4311 /**
4312  * bitmap_is_subset - Check whether src2 is subset of src1
4313  **/
4314 static inline int
4315 bitmap_is_subset(uint8_t src1, uint8_t src2)
4316 {
4317         return !((src1 ^ src2) & src2);
4318 }
4319
4320 static enum i40e_status_code
4321 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4322 {
4323         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4324
4325         /* If DCB is not supported, only default TC is supported */
4326         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4327                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4328                 return I40E_NOT_SUPPORTED;
4329         }
4330
4331         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4332                 PMD_DRV_LOG(ERR,
4333                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4334                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4335                 return I40E_NOT_SUPPORTED;
4336         }
4337         return I40E_SUCCESS;
4338 }
4339
4340 int
4341 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4342                                 struct i40e_vsi_vlan_pvid_info *info)
4343 {
4344         struct i40e_hw *hw;
4345         struct i40e_vsi_context ctxt;
4346         uint8_t vlan_flags = 0;
4347         int ret;
4348
4349         if (vsi == NULL || info == NULL) {
4350                 PMD_DRV_LOG(ERR, "invalid parameters");
4351                 return I40E_ERR_PARAM;
4352         }
4353
4354         if (info->on) {
4355                 vsi->info.pvid = info->config.pvid;
4356                 /**
4357                  * If insert pvid is enabled, only tagged pkts are
4358                  * allowed to be sent out.
4359                  */
4360                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4361                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4362         } else {
4363                 vsi->info.pvid = 0;
4364                 if (info->config.reject.tagged == 0)
4365                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4366
4367                 if (info->config.reject.untagged == 0)
4368                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4369         }
4370         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4371                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4372         vsi->info.port_vlan_flags |= vlan_flags;
4373         vsi->info.valid_sections =
4374                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4375         memset(&ctxt, 0, sizeof(ctxt));
4376         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4377         ctxt.seid = vsi->seid;
4378
4379         hw = I40E_VSI_TO_HW(vsi);
4380         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4381         if (ret != I40E_SUCCESS)
4382                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4383
4384         return ret;
4385 }
4386
4387 static int
4388 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4389 {
4390         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4391         int i, ret;
4392         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4393
4394         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4395         if (ret != I40E_SUCCESS)
4396                 return ret;
4397
4398         if (!vsi->seid) {
4399                 PMD_DRV_LOG(ERR, "seid not valid");
4400                 return -EINVAL;
4401         }
4402
4403         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4404         tc_bw_data.tc_valid_bits = enabled_tcmap;
4405         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4406                 tc_bw_data.tc_bw_credits[i] =
4407                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4408
4409         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4410         if (ret != I40E_SUCCESS) {
4411                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4412                 return ret;
4413         }
4414
4415         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4416                                         sizeof(vsi->info.qs_handle));
4417         return I40E_SUCCESS;
4418 }
4419
4420 static enum i40e_status_code
4421 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4422                                  struct i40e_aqc_vsi_properties_data *info,
4423                                  uint8_t enabled_tcmap)
4424 {
4425         enum i40e_status_code ret;
4426         int i, total_tc = 0;
4427         uint16_t qpnum_per_tc, bsf, qp_idx;
4428
4429         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4430         if (ret != I40E_SUCCESS)
4431                 return ret;
4432
4433         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4434                 if (enabled_tcmap & (1 << i))
4435                         total_tc++;
4436         if (total_tc == 0)
4437                 total_tc = 1;
4438         vsi->enabled_tc = enabled_tcmap;
4439
4440         /* Number of queues per enabled TC */
4441         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4442         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4443         bsf = rte_bsf32(qpnum_per_tc);
4444
4445         /* Adjust the queue number to actual queues that can be applied */
4446         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4447                 vsi->nb_qps = qpnum_per_tc * total_tc;
4448
4449         /**
4450          * Configure TC and queue mapping parameters, for enabled TC,
4451          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4452          * default queue will serve it.
4453          */
4454         qp_idx = 0;
4455         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4456                 if (vsi->enabled_tc & (1 << i)) {
4457                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4458                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4459                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4460                         qp_idx += qpnum_per_tc;
4461                 } else
4462                         info->tc_mapping[i] = 0;
4463         }
4464
4465         /* Associate queue number with VSI */
4466         if (vsi->type == I40E_VSI_SRIOV) {
4467                 info->mapping_flags |=
4468                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4469                 for (i = 0; i < vsi->nb_qps; i++)
4470                         info->queue_mapping[i] =
4471                                 rte_cpu_to_le_16(vsi->base_queue + i);
4472         } else {
4473                 info->mapping_flags |=
4474                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4475                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4476         }
4477         info->valid_sections |=
4478                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4479
4480         return I40E_SUCCESS;
4481 }
4482
4483 static int
4484 i40e_veb_release(struct i40e_veb *veb)
4485 {
4486         struct i40e_vsi *vsi;
4487         struct i40e_hw *hw;
4488
4489         if (veb == NULL)
4490                 return -EINVAL;
4491
4492         if (!TAILQ_EMPTY(&veb->head)) {
4493                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4494                 return -EACCES;
4495         }
4496         /* associate_vsi field is NULL for floating VEB */
4497         if (veb->associate_vsi != NULL) {
4498                 vsi = veb->associate_vsi;
4499                 hw = I40E_VSI_TO_HW(vsi);
4500
4501                 vsi->uplink_seid = veb->uplink_seid;
4502                 vsi->veb = NULL;
4503         } else {
4504                 veb->associate_pf->main_vsi->floating_veb = NULL;
4505                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4506         }
4507
4508         i40e_aq_delete_element(hw, veb->seid, NULL);
4509         rte_free(veb);
4510         return I40E_SUCCESS;
4511 }
4512
4513 /* Setup a veb */
4514 static struct i40e_veb *
4515 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4516 {
4517         struct i40e_veb *veb;
4518         int ret;
4519         struct i40e_hw *hw;
4520
4521         if (pf == NULL) {
4522                 PMD_DRV_LOG(ERR,
4523                             "veb setup failed, associated PF shouldn't null");
4524                 return NULL;
4525         }
4526         hw = I40E_PF_TO_HW(pf);
4527
4528         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4529         if (!veb) {
4530                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4531                 goto fail;
4532         }
4533
4534         veb->associate_vsi = vsi;
4535         veb->associate_pf = pf;
4536         TAILQ_INIT(&veb->head);
4537         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4538
4539         /* create floating veb if vsi is NULL */
4540         if (vsi != NULL) {
4541                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4542                                       I40E_DEFAULT_TCMAP, false,
4543                                       &veb->seid, false, NULL);
4544         } else {
4545                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4546                                       true, &veb->seid, false, NULL);
4547         }
4548
4549         if (ret != I40E_SUCCESS) {
4550                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4551                             hw->aq.asq_last_status);
4552                 goto fail;
4553         }
4554         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4555
4556         /* get statistics index */
4557         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4558                                 &veb->stats_idx, NULL, NULL, NULL);
4559         if (ret != I40E_SUCCESS) {
4560                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4561                             hw->aq.asq_last_status);
4562                 goto fail;
4563         }
4564         /* Get VEB bandwidth, to be implemented */
4565         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4566         if (vsi)
4567                 vsi->uplink_seid = veb->seid;
4568
4569         return veb;
4570 fail:
4571         rte_free(veb);
4572         return NULL;
4573 }
4574
4575 int
4576 i40e_vsi_release(struct i40e_vsi *vsi)
4577 {
4578         struct i40e_pf *pf;
4579         struct i40e_hw *hw;
4580         struct i40e_vsi_list *vsi_list;
4581         void *temp;
4582         int ret;
4583         struct i40e_mac_filter *f;
4584         uint16_t user_param;
4585
4586         if (!vsi)
4587                 return I40E_SUCCESS;
4588
4589         if (!vsi->adapter)
4590                 return -EFAULT;
4591
4592         user_param = vsi->user_param;
4593
4594         pf = I40E_VSI_TO_PF(vsi);
4595         hw = I40E_VSI_TO_HW(vsi);
4596
4597         /* VSI has child to attach, release child first */
4598         if (vsi->veb) {
4599                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4600                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4601                                 return -1;
4602                 }
4603                 i40e_veb_release(vsi->veb);
4604         }
4605
4606         if (vsi->floating_veb) {
4607                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4608                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4609                                 return -1;
4610                 }
4611         }
4612
4613         /* Remove all macvlan filters of the VSI */
4614         i40e_vsi_remove_all_macvlan_filter(vsi);
4615         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4616                 rte_free(f);
4617
4618         if (vsi->type != I40E_VSI_MAIN &&
4619             ((vsi->type != I40E_VSI_SRIOV) ||
4620             !pf->floating_veb_list[user_param])) {
4621                 /* Remove vsi from parent's sibling list */
4622                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4623                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4624                         return I40E_ERR_PARAM;
4625                 }
4626                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4627                                 &vsi->sib_vsi_list, list);
4628
4629                 /* Remove all switch element of the VSI */
4630                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4631                 if (ret != I40E_SUCCESS)
4632                         PMD_DRV_LOG(ERR, "Failed to delete element");
4633         }
4634
4635         if ((vsi->type == I40E_VSI_SRIOV) &&
4636             pf->floating_veb_list[user_param]) {
4637                 /* Remove vsi from parent's sibling list */
4638                 if (vsi->parent_vsi == NULL ||
4639                     vsi->parent_vsi->floating_veb == NULL) {
4640                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4641                         return I40E_ERR_PARAM;
4642                 }
4643                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4644                              &vsi->sib_vsi_list, list);
4645
4646                 /* Remove all switch element of the VSI */
4647                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4648                 if (ret != I40E_SUCCESS)
4649                         PMD_DRV_LOG(ERR, "Failed to delete element");
4650         }
4651
4652         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4653
4654         if (vsi->type != I40E_VSI_SRIOV)
4655                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4656         rte_free(vsi);
4657
4658         return I40E_SUCCESS;
4659 }
4660
4661 static int
4662 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4663 {
4664         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4665         struct i40e_aqc_remove_macvlan_element_data def_filter;
4666         struct i40e_mac_filter_info filter;
4667         int ret;
4668
4669         if (vsi->type != I40E_VSI_MAIN)
4670                 return I40E_ERR_CONFIG;
4671         memset(&def_filter, 0, sizeof(def_filter));
4672         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4673                                         ETH_ADDR_LEN);
4674         def_filter.vlan_tag = 0;
4675         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4676                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4677         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4678         if (ret != I40E_SUCCESS) {
4679                 struct i40e_mac_filter *f;
4680                 struct ether_addr *mac;
4681
4682                 PMD_DRV_LOG(DEBUG,
4683                             "Cannot remove the default macvlan filter");
4684                 /* It needs to add the permanent mac into mac list */
4685                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4686                 if (f == NULL) {
4687                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4688                         return I40E_ERR_NO_MEMORY;
4689                 }
4690                 mac = &f->mac_info.mac_addr;
4691                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4692                                 ETH_ADDR_LEN);
4693                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4694                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4695                 vsi->mac_num++;
4696
4697                 return ret;
4698         }
4699         rte_memcpy(&filter.mac_addr,
4700                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4701         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4702         return i40e_vsi_add_mac(vsi, &filter);
4703 }
4704
4705 /*
4706  * i40e_vsi_get_bw_config - Query VSI BW Information
4707  * @vsi: the VSI to be queried
4708  *
4709  * Returns 0 on success, negative value on failure
4710  */
4711 static enum i40e_status_code
4712 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4713 {
4714         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4715         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4716         struct i40e_hw *hw = &vsi->adapter->hw;
4717         i40e_status ret;
4718         int i;
4719         uint32_t bw_max;
4720
4721         memset(&bw_config, 0, sizeof(bw_config));
4722         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4723         if (ret != I40E_SUCCESS) {
4724                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4725                             hw->aq.asq_last_status);
4726                 return ret;
4727         }
4728
4729         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4730         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4731                                         &ets_sla_config, NULL);
4732         if (ret != I40E_SUCCESS) {
4733                 PMD_DRV_LOG(ERR,
4734                         "VSI failed to get TC bandwdith configuration %u",
4735                         hw->aq.asq_last_status);
4736                 return ret;
4737         }
4738
4739         /* store and print out BW info */
4740         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4741         vsi->bw_info.bw_max = bw_config.max_bw;
4742         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4743         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4744         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4745                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4746                      I40E_16_BIT_WIDTH);
4747         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4748                 vsi->bw_info.bw_ets_share_credits[i] =
4749                                 ets_sla_config.share_credits[i];
4750                 vsi->bw_info.bw_ets_credits[i] =
4751                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4752                 /* 4 bits per TC, 4th bit is reserved */
4753                 vsi->bw_info.bw_ets_max[i] =
4754                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4755                                   RTE_LEN2MASK(3, uint8_t));
4756                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4757                             vsi->bw_info.bw_ets_share_credits[i]);
4758                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4759                             vsi->bw_info.bw_ets_credits[i]);
4760                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4761                             vsi->bw_info.bw_ets_max[i]);
4762         }
4763
4764         return I40E_SUCCESS;
4765 }
4766
4767 /* i40e_enable_pf_lb
4768  * @pf: pointer to the pf structure
4769  *
4770  * allow loopback on pf
4771  */
4772 static inline void
4773 i40e_enable_pf_lb(struct i40e_pf *pf)
4774 {
4775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4776         struct i40e_vsi_context ctxt;
4777         int ret;
4778
4779         /* Use the FW API if FW >= v5.0 */
4780         if (hw->aq.fw_maj_ver < 5) {
4781                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4782                 return;
4783         }
4784
4785         memset(&ctxt, 0, sizeof(ctxt));
4786         ctxt.seid = pf->main_vsi_seid;
4787         ctxt.pf_num = hw->pf_id;
4788         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4789         if (ret) {
4790                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4791                             ret, hw->aq.asq_last_status);
4792                 return;
4793         }
4794         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4795         ctxt.info.valid_sections =
4796                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4797         ctxt.info.switch_id |=
4798                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4799
4800         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4801         if (ret)
4802                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4803                             hw->aq.asq_last_status);
4804 }
4805
4806 /* Setup a VSI */
4807 struct i40e_vsi *
4808 i40e_vsi_setup(struct i40e_pf *pf,
4809                enum i40e_vsi_type type,
4810                struct i40e_vsi *uplink_vsi,
4811                uint16_t user_param)
4812 {
4813         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4814         struct i40e_vsi *vsi;
4815         struct i40e_mac_filter_info filter;
4816         int ret;
4817         struct i40e_vsi_context ctxt;
4818         struct ether_addr broadcast =
4819                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4820
4821         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4822             uplink_vsi == NULL) {
4823                 PMD_DRV_LOG(ERR,
4824                         "VSI setup failed, VSI link shouldn't be NULL");
4825                 return NULL;
4826         }
4827
4828         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4829                 PMD_DRV_LOG(ERR,
4830                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4831                 return NULL;
4832         }
4833
4834         /* two situations
4835          * 1.type is not MAIN and uplink vsi is not NULL
4836          * If uplink vsi didn't setup VEB, create one first under veb field
4837          * 2.type is SRIOV and the uplink is NULL
4838          * If floating VEB is NULL, create one veb under floating veb field
4839          */
4840
4841         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4842             uplink_vsi->veb == NULL) {
4843                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4844
4845                 if (uplink_vsi->veb == NULL) {
4846                         PMD_DRV_LOG(ERR, "VEB setup failed");
4847                         return NULL;
4848                 }
4849                 /* set ALLOWLOOPBACk on pf, when veb is created */
4850                 i40e_enable_pf_lb(pf);
4851         }
4852
4853         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4854             pf->main_vsi->floating_veb == NULL) {
4855                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4856
4857                 if (pf->main_vsi->floating_veb == NULL) {
4858                         PMD_DRV_LOG(ERR, "VEB setup failed");
4859                         return NULL;
4860                 }
4861         }
4862
4863         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4864         if (!vsi) {
4865                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4866                 return NULL;
4867         }
4868         TAILQ_INIT(&vsi->mac_list);
4869         vsi->type = type;
4870         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4871         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4872         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4873         vsi->user_param = user_param;
4874         vsi->vlan_anti_spoof_on = 0;
4875         vsi->vlan_filter_on = 0;
4876         /* Allocate queues */
4877         switch (vsi->type) {
4878         case I40E_VSI_MAIN  :
4879                 vsi->nb_qps = pf->lan_nb_qps;
4880                 break;
4881         case I40E_VSI_SRIOV :
4882                 vsi->nb_qps = pf->vf_nb_qps;
4883                 break;
4884         case I40E_VSI_VMDQ2:
4885                 vsi->nb_qps = pf->vmdq_nb_qps;
4886                 break;
4887         case I40E_VSI_FDIR:
4888                 vsi->nb_qps = pf->fdir_nb_qps;
4889                 break;
4890         default:
4891                 goto fail_mem;
4892         }
4893         /*
4894          * The filter status descriptor is reported in rx queue 0,
4895          * while the tx queue for fdir filter programming has no
4896          * such constraints, can be non-zero queues.
4897          * To simplify it, choose FDIR vsi use queue 0 pair.
4898          * To make sure it will use queue 0 pair, queue allocation
4899          * need be done before this function is called
4900          */
4901         if (type != I40E_VSI_FDIR) {
4902                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4903                         if (ret < 0) {
4904                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4905                                                 vsi->seid, ret);
4906                                 goto fail_mem;
4907                         }
4908                         vsi->base_queue = ret;
4909         } else
4910                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4911
4912         /* VF has MSIX interrupt in VF range, don't allocate here */
4913         if (type == I40E_VSI_MAIN) {
4914                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4915                                           RTE_MIN(vsi->nb_qps,
4916                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4917                 if (ret < 0) {
4918                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4919                                     vsi->seid, ret);
4920                         goto fail_queue_alloc;
4921                 }
4922                 vsi->msix_intr = ret;
4923                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4924         } else if (type != I40E_VSI_SRIOV) {
4925                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4926                 if (ret < 0) {
4927                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4928                         goto fail_queue_alloc;
4929                 }
4930                 vsi->msix_intr = ret;
4931                 vsi->nb_msix = 1;
4932         } else {
4933                 vsi->msix_intr = 0;
4934                 vsi->nb_msix = 0;
4935         }
4936
4937         /* Add VSI */
4938         if (type == I40E_VSI_MAIN) {
4939                 /* For main VSI, no need to add since it's default one */
4940                 vsi->uplink_seid = pf->mac_seid;
4941                 vsi->seid = pf->main_vsi_seid;
4942                 /* Bind queues with specific MSIX interrupt */
4943                 /**
4944                  * Needs 2 interrupt at least, one for misc cause which will
4945                  * enabled from OS side, Another for queues binding the
4946                  * interrupt from device side only.
4947                  */
4948
4949                 /* Get default VSI parameters from hardware */
4950                 memset(&ctxt, 0, sizeof(ctxt));
4951                 ctxt.seid = vsi->seid;
4952                 ctxt.pf_num = hw->pf_id;
4953                 ctxt.uplink_seid = vsi->uplink_seid;
4954                 ctxt.vf_num = 0;
4955                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4956                 if (ret != I40E_SUCCESS) {
4957                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4958                         goto fail_msix_alloc;
4959                 }
4960                 rte_memcpy(&vsi->info, &ctxt.info,
4961                         sizeof(struct i40e_aqc_vsi_properties_data));
4962                 vsi->vsi_id = ctxt.vsi_number;
4963                 vsi->info.valid_sections = 0;
4964
4965                 /* Configure tc, enabled TC0 only */
4966                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4967                         I40E_SUCCESS) {
4968                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4969                         goto fail_msix_alloc;
4970                 }
4971
4972                 /* TC, queue mapping */
4973                 memset(&ctxt, 0, sizeof(ctxt));
4974                 vsi->info.valid_sections |=
4975                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4976                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4977                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4978                 rte_memcpy(&ctxt.info, &vsi->info,
4979                         sizeof(struct i40e_aqc_vsi_properties_data));
4980                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4981                                                 I40E_DEFAULT_TCMAP);
4982                 if (ret != I40E_SUCCESS) {
4983                         PMD_DRV_LOG(ERR,
4984                                 "Failed to configure TC queue mapping");
4985                         goto fail_msix_alloc;
4986                 }
4987                 ctxt.seid = vsi->seid;
4988                 ctxt.pf_num = hw->pf_id;
4989                 ctxt.uplink_seid = vsi->uplink_seid;
4990                 ctxt.vf_num = 0;
4991
4992                 /* Update VSI parameters */
4993                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4994                 if (ret != I40E_SUCCESS) {
4995                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4996                         goto fail_msix_alloc;
4997                 }
4998
4999                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5000                                                 sizeof(vsi->info.tc_mapping));
5001                 rte_memcpy(&vsi->info.queue_mapping,
5002                                 &ctxt.info.queue_mapping,
5003                         sizeof(vsi->info.queue_mapping));
5004                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5005                 vsi->info.valid_sections = 0;
5006
5007                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5008                                 ETH_ADDR_LEN);
5009
5010                 /**
5011                  * Updating default filter settings are necessary to prevent
5012                  * reception of tagged packets.
5013                  * Some old firmware configurations load a default macvlan
5014                  * filter which accepts both tagged and untagged packets.
5015                  * The updating is to use a normal filter instead if needed.
5016                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5017                  * The firmware with correct configurations load the default
5018                  * macvlan filter which is expected and cannot be removed.
5019                  */
5020                 i40e_update_default_filter_setting(vsi);
5021                 i40e_config_qinq(hw, vsi);
5022         } else if (type == I40E_VSI_SRIOV) {
5023                 memset(&ctxt, 0, sizeof(ctxt));
5024                 /**
5025                  * For other VSI, the uplink_seid equals to uplink VSI's
5026                  * uplink_seid since they share same VEB
5027                  */
5028                 if (uplink_vsi == NULL)
5029                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5030                 else
5031                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5032                 ctxt.pf_num = hw->pf_id;
5033                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5034                 ctxt.uplink_seid = vsi->uplink_seid;
5035                 ctxt.connection_type = 0x1;
5036                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5037
5038                 /* Use the VEB configuration if FW >= v5.0 */
5039                 if (hw->aq.fw_maj_ver >= 5) {
5040                         /* Configure switch ID */
5041                         ctxt.info.valid_sections |=
5042                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5043                         ctxt.info.switch_id =
5044                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5045                 }
5046
5047                 /* Configure port/vlan */
5048                 ctxt.info.valid_sections |=
5049                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5050                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5051                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5052                                                 hw->func_caps.enabled_tcmap);
5053                 if (ret != I40E_SUCCESS) {
5054                         PMD_DRV_LOG(ERR,
5055                                 "Failed to configure TC queue mapping");
5056                         goto fail_msix_alloc;
5057                 }
5058
5059                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5060                 ctxt.info.valid_sections |=
5061                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5062                 /**
5063                  * Since VSI is not created yet, only configure parameter,
5064                  * will add vsi below.
5065                  */
5066
5067                 i40e_config_qinq(hw, vsi);
5068         } else if (type == I40E_VSI_VMDQ2) {
5069                 memset(&ctxt, 0, sizeof(ctxt));
5070                 /*
5071                  * For other VSI, the uplink_seid equals to uplink VSI's
5072                  * uplink_seid since they share same VEB
5073                  */
5074                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5075                 ctxt.pf_num = hw->pf_id;
5076                 ctxt.vf_num = 0;
5077                 ctxt.uplink_seid = vsi->uplink_seid;
5078                 ctxt.connection_type = 0x1;
5079                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5080
5081                 ctxt.info.valid_sections |=
5082                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5083                 /* user_param carries flag to enable loop back */
5084                 if (user_param) {
5085                         ctxt.info.switch_id =
5086                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5087                         ctxt.info.switch_id |=
5088                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5089                 }
5090
5091                 /* Configure port/vlan */
5092                 ctxt.info.valid_sections |=
5093                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5094                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5095                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5096                                                 I40E_DEFAULT_TCMAP);
5097                 if (ret != I40E_SUCCESS) {
5098                         PMD_DRV_LOG(ERR,
5099                                 "Failed to configure TC queue mapping");
5100                         goto fail_msix_alloc;
5101                 }
5102                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5103                 ctxt.info.valid_sections |=
5104                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5105         } else if (type == I40E_VSI_FDIR) {
5106                 memset(&ctxt, 0, sizeof(ctxt));
5107                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5108                 ctxt.pf_num = hw->pf_id;
5109                 ctxt.vf_num = 0;
5110                 ctxt.uplink_seid = vsi->uplink_seid;
5111                 ctxt.connection_type = 0x1;     /* regular data port */
5112                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5113                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5114                                                 I40E_DEFAULT_TCMAP);
5115                 if (ret != I40E_SUCCESS) {
5116                         PMD_DRV_LOG(ERR,
5117                                 "Failed to configure TC queue mapping.");
5118                         goto fail_msix_alloc;
5119                 }
5120                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5121                 ctxt.info.valid_sections |=
5122                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5123         } else {
5124                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5125                 goto fail_msix_alloc;
5126         }
5127
5128         if (vsi->type != I40E_VSI_MAIN) {
5129                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5130                 if (ret != I40E_SUCCESS) {
5131                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5132                                     hw->aq.asq_last_status);
5133                         goto fail_msix_alloc;
5134                 }
5135                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5136                 vsi->info.valid_sections = 0;
5137                 vsi->seid = ctxt.seid;
5138                 vsi->vsi_id = ctxt.vsi_number;
5139                 vsi->sib_vsi_list.vsi = vsi;
5140                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5141                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5142                                           &vsi->sib_vsi_list, list);
5143                 } else {
5144                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5145                                           &vsi->sib_vsi_list, list);
5146                 }
5147         }
5148
5149         /* MAC/VLAN configuration */
5150         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5151         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5152
5153         ret = i40e_vsi_add_mac(vsi, &filter);
5154         if (ret != I40E_SUCCESS) {
5155                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5156                 goto fail_msix_alloc;
5157         }
5158
5159         /* Get VSI BW information */
5160         i40e_vsi_get_bw_config(vsi);
5161         return vsi;
5162 fail_msix_alloc:
5163         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5164 fail_queue_alloc:
5165         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5166 fail_mem:
5167         rte_free(vsi);
5168         return NULL;
5169 }
5170
5171 /* Configure vlan filter on or off */
5172 int
5173 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5174 {
5175         int i, num;
5176         struct i40e_mac_filter *f;
5177         void *temp;
5178         struct i40e_mac_filter_info *mac_filter;
5179         enum rte_mac_filter_type desired_filter;
5180         int ret = I40E_SUCCESS;
5181
5182         if (on) {
5183                 /* Filter to match MAC and VLAN */
5184                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5185         } else {
5186                 /* Filter to match only MAC */
5187                 desired_filter = RTE_MAC_PERFECT_MATCH;
5188         }
5189
5190         num = vsi->mac_num;
5191
5192         mac_filter = rte_zmalloc("mac_filter_info_data",
5193                                  num * sizeof(*mac_filter), 0);
5194         if (mac_filter == NULL) {
5195                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5196                 return I40E_ERR_NO_MEMORY;
5197         }
5198
5199         i = 0;
5200
5201         /* Remove all existing mac */
5202         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5203                 mac_filter[i] = f->mac_info;
5204                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5205                 if (ret) {
5206                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5207                                     on ? "enable" : "disable");
5208                         goto DONE;
5209                 }
5210                 i++;
5211         }
5212
5213         /* Override with new filter */
5214         for (i = 0; i < num; i++) {
5215                 mac_filter[i].filter_type = desired_filter;
5216                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5217                 if (ret) {
5218                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5219                                     on ? "enable" : "disable");
5220                         goto DONE;
5221                 }
5222         }
5223
5224 DONE:
5225         rte_free(mac_filter);
5226         return ret;
5227 }
5228
5229 /* Configure vlan stripping on or off */
5230 int
5231 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5232 {
5233         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5234         struct i40e_vsi_context ctxt;
5235         uint8_t vlan_flags;
5236         int ret = I40E_SUCCESS;
5237
5238         /* Check if it has been already on or off */
5239         if (vsi->info.valid_sections &
5240                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5241                 if (on) {
5242                         if ((vsi->info.port_vlan_flags &
5243                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5244                                 return 0; /* already on */
5245                 } else {
5246                         if ((vsi->info.port_vlan_flags &
5247                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5248                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5249                                 return 0; /* already off */
5250                 }
5251         }
5252
5253         if (on)
5254                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5255         else
5256                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5257         vsi->info.valid_sections =
5258                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5259         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5260         vsi->info.port_vlan_flags |= vlan_flags;
5261         ctxt.seid = vsi->seid;
5262         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5263         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5264         if (ret)
5265                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5266                             on ? "enable" : "disable");
5267
5268         return ret;
5269 }
5270
5271 static int
5272 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5273 {
5274         struct rte_eth_dev_data *data = dev->data;
5275         int ret;
5276         int mask = 0;
5277
5278         /* Apply vlan offload setting */
5279         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5280         i40e_vlan_offload_set(dev, mask);
5281
5282         /* Apply double-vlan setting, not implemented yet */
5283
5284         /* Apply pvid setting */
5285         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5286                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5287         if (ret)
5288                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5289
5290         return ret;
5291 }
5292
5293 static int
5294 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5295 {
5296         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5297
5298         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5299 }
5300
5301 static int
5302 i40e_update_flow_control(struct i40e_hw *hw)
5303 {
5304 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5305         struct i40e_link_status link_status;
5306         uint32_t rxfc = 0, txfc = 0, reg;
5307         uint8_t an_info;
5308         int ret;
5309
5310         memset(&link_status, 0, sizeof(link_status));
5311         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5312         if (ret != I40E_SUCCESS) {
5313                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5314                 goto write_reg; /* Disable flow control */
5315         }
5316
5317         an_info = hw->phy.link_info.an_info;
5318         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5319                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5320                 ret = I40E_ERR_NOT_READY;
5321                 goto write_reg; /* Disable flow control */
5322         }
5323         /**
5324          * If link auto negotiation is enabled, flow control needs to
5325          * be configured according to it
5326          */
5327         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5328         case I40E_LINK_PAUSE_RXTX:
5329                 rxfc = 1;
5330                 txfc = 1;
5331                 hw->fc.current_mode = I40E_FC_FULL;
5332                 break;
5333         case I40E_AQ_LINK_PAUSE_RX:
5334                 rxfc = 1;
5335                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5336                 break;
5337         case I40E_AQ_LINK_PAUSE_TX:
5338                 txfc = 1;
5339                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5340                 break;
5341         default:
5342                 hw->fc.current_mode = I40E_FC_NONE;
5343                 break;
5344         }
5345
5346 write_reg:
5347         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5348                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5349         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5350         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5351         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5352         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5353
5354         return ret;
5355 }
5356
5357 /* PF setup */
5358 static int
5359 i40e_pf_setup(struct i40e_pf *pf)
5360 {
5361         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5362         struct i40e_filter_control_settings settings;
5363         struct i40e_vsi *vsi;
5364         int ret;
5365
5366         /* Clear all stats counters */
5367         pf->offset_loaded = FALSE;
5368         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5369         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5370         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5371         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5372
5373         ret = i40e_pf_get_switch_config(pf);
5374         if (ret != I40E_SUCCESS) {
5375                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5376                 return ret;
5377         }
5378         if (pf->flags & I40E_FLAG_FDIR) {
5379                 /* make queue allocated first, let FDIR use queue pair 0*/
5380                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5381                 if (ret != I40E_FDIR_QUEUE_ID) {
5382                         PMD_DRV_LOG(ERR,
5383                                 "queue allocation fails for FDIR: ret =%d",
5384                                 ret);
5385                         pf->flags &= ~I40E_FLAG_FDIR;
5386                 }
5387         }
5388         /*  main VSI setup */
5389         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5390         if (!vsi) {
5391                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5392                 return I40E_ERR_NOT_READY;
5393         }
5394         pf->main_vsi = vsi;
5395
5396         /* Configure filter control */
5397         memset(&settings, 0, sizeof(settings));
5398         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5399                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5400         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5401                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5402         else {
5403                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5404                         hw->func_caps.rss_table_size);
5405                 return I40E_ERR_PARAM;
5406         }
5407         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5408                 hw->func_caps.rss_table_size);
5409         pf->hash_lut_size = hw->func_caps.rss_table_size;
5410
5411         /* Enable ethtype and macvlan filters */
5412         settings.enable_ethtype = TRUE;
5413         settings.enable_macvlan = TRUE;
5414         ret = i40e_set_filter_control(hw, &settings);
5415         if (ret)
5416                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5417                                                                 ret);
5418
5419         /* Update flow control according to the auto negotiation */
5420         i40e_update_flow_control(hw);
5421
5422         return I40E_SUCCESS;
5423 }
5424
5425 int
5426 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5427 {
5428         uint32_t reg;
5429         uint16_t j;
5430
5431         /**
5432          * Set or clear TX Queue Disable flags,
5433          * which is required by hardware.
5434          */
5435         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5436         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5437
5438         /* Wait until the request is finished */
5439         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5440                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5441                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5442                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5443                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5444                                                         & 0x1))) {
5445                         break;
5446                 }
5447         }
5448         if (on) {
5449                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5450                         return I40E_SUCCESS; /* already on, skip next steps */
5451
5452                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5453                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5454         } else {
5455                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5456                         return I40E_SUCCESS; /* already off, skip next steps */
5457                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5458         }
5459         /* Write the register */
5460         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5461         /* Check the result */
5462         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5463                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5464                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5465                 if (on) {
5466                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5467                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5468                                 break;
5469                 } else {
5470                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5471                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5472                                 break;
5473                 }
5474         }
5475         /* Check if it is timeout */
5476         if (j >= I40E_CHK_Q_ENA_COUNT) {
5477                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5478                             (on ? "enable" : "disable"), q_idx);
5479                 return I40E_ERR_TIMEOUT;
5480         }
5481
5482         return I40E_SUCCESS;
5483 }
5484
5485 /* Swith on or off the tx queues */
5486 static int
5487 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5488 {
5489         struct rte_eth_dev_data *dev_data = pf->dev_data;
5490         struct i40e_tx_queue *txq;
5491         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5492         uint16_t i;
5493         int ret;
5494
5495         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5496                 txq = dev_data->tx_queues[i];
5497                 /* Don't operate the queue if not configured or
5498                  * if starting only per queue */
5499                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5500                         continue;
5501                 if (on)
5502                         ret = i40e_dev_tx_queue_start(dev, i);
5503                 else
5504                         ret = i40e_dev_tx_queue_stop(dev, i);
5505                 if ( ret != I40E_SUCCESS)
5506                         return ret;
5507         }
5508
5509         return I40E_SUCCESS;
5510 }
5511
5512 int
5513 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5514 {
5515         uint32_t reg;
5516         uint16_t j;
5517
5518         /* Wait until the request is finished */
5519         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5520                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5521                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5522                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5523                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5524                         break;
5525         }
5526
5527         if (on) {
5528                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5529                         return I40E_SUCCESS; /* Already on, skip next steps */
5530                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5531         } else {
5532                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5533                         return I40E_SUCCESS; /* Already off, skip next steps */
5534                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5535         }
5536
5537         /* Write the register */
5538         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5539         /* Check the result */
5540         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5541                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5542                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5543                 if (on) {
5544                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5545                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5546                                 break;
5547                 } else {
5548                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5549                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5550                                 break;
5551                 }
5552         }
5553
5554         /* Check if it is timeout */
5555         if (j >= I40E_CHK_Q_ENA_COUNT) {
5556                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5557                             (on ? "enable" : "disable"), q_idx);
5558                 return I40E_ERR_TIMEOUT;
5559         }
5560
5561         return I40E_SUCCESS;
5562 }
5563 /* Switch on or off the rx queues */
5564 static int
5565 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5566 {
5567         struct rte_eth_dev_data *dev_data = pf->dev_data;
5568         struct i40e_rx_queue *rxq;
5569         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5570         uint16_t i;
5571         int ret;
5572
5573         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5574                 rxq = dev_data->rx_queues[i];
5575                 /* Don't operate the queue if not configured or
5576                  * if starting only per queue */
5577                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5578                         continue;
5579                 if (on)
5580                         ret = i40e_dev_rx_queue_start(dev, i);
5581                 else
5582                         ret = i40e_dev_rx_queue_stop(dev, i);
5583                 if (ret != I40E_SUCCESS)
5584                         return ret;
5585         }
5586
5587         return I40E_SUCCESS;
5588 }
5589
5590 /* Switch on or off all the rx/tx queues */
5591 int
5592 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5593 {
5594         int ret;
5595
5596         if (on) {
5597                 /* enable rx queues before enabling tx queues */
5598                 ret = i40e_dev_switch_rx_queues(pf, on);
5599                 if (ret) {
5600                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5601                         return ret;
5602                 }
5603                 ret = i40e_dev_switch_tx_queues(pf, on);
5604         } else {
5605                 /* Stop tx queues before stopping rx queues */
5606                 ret = i40e_dev_switch_tx_queues(pf, on);
5607                 if (ret) {
5608                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5609                         return ret;
5610                 }
5611                 ret = i40e_dev_switch_rx_queues(pf, on);
5612         }
5613
5614         return ret;
5615 }
5616
5617 /* Initialize VSI for TX */
5618 static int
5619 i40e_dev_tx_init(struct i40e_pf *pf)
5620 {
5621         struct rte_eth_dev_data *data = pf->dev_data;
5622         uint16_t i;
5623         uint32_t ret = I40E_SUCCESS;
5624         struct i40e_tx_queue *txq;
5625
5626         for (i = 0; i < data->nb_tx_queues; i++) {
5627                 txq = data->tx_queues[i];
5628                 if (!txq || !txq->q_set)
5629                         continue;
5630                 ret = i40e_tx_queue_init(txq);
5631                 if (ret != I40E_SUCCESS)
5632                         break;
5633         }
5634         if (ret == I40E_SUCCESS)
5635                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5636                                      ->eth_dev);
5637
5638         return ret;
5639 }
5640
5641 /* Initialize VSI for RX */
5642 static int
5643 i40e_dev_rx_init(struct i40e_pf *pf)
5644 {
5645         struct rte_eth_dev_data *data = pf->dev_data;
5646         int ret = I40E_SUCCESS;
5647         uint16_t i;
5648         struct i40e_rx_queue *rxq;
5649
5650         i40e_pf_config_mq_rx(pf);
5651         for (i = 0; i < data->nb_rx_queues; i++) {
5652                 rxq = data->rx_queues[i];
5653                 if (!rxq || !rxq->q_set)
5654                         continue;
5655
5656                 ret = i40e_rx_queue_init(rxq);
5657                 if (ret != I40E_SUCCESS) {
5658                         PMD_DRV_LOG(ERR,
5659                                 "Failed to do RX queue initialization");
5660                         break;
5661                 }
5662         }
5663         if (ret == I40E_SUCCESS)
5664                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5665                                      ->eth_dev);
5666
5667         return ret;
5668 }
5669
5670 static int
5671 i40e_dev_rxtx_init(struct i40e_pf *pf)
5672 {
5673         int err;
5674
5675         err = i40e_dev_tx_init(pf);
5676         if (err) {
5677                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5678                 return err;
5679         }
5680         err = i40e_dev_rx_init(pf);
5681         if (err) {
5682                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5683                 return err;
5684         }
5685
5686         return err;
5687 }
5688
5689 static int
5690 i40e_vmdq_setup(struct rte_eth_dev *dev)
5691 {
5692         struct rte_eth_conf *conf = &dev->data->dev_conf;
5693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5694         int i, err, conf_vsis, j, loop;
5695         struct i40e_vsi *vsi;
5696         struct i40e_vmdq_info *vmdq_info;
5697         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5698         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5699
5700         /*
5701          * Disable interrupt to avoid message from VF. Furthermore, it will
5702          * avoid race condition in VSI creation/destroy.
5703          */
5704         i40e_pf_disable_irq0(hw);
5705
5706         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5707                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5708                 return -ENOTSUP;
5709         }
5710
5711         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5712         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5713                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5714                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5715                         pf->max_nb_vmdq_vsi);
5716                 return -ENOTSUP;
5717         }
5718
5719         if (pf->vmdq != NULL) {
5720                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5721                 return 0;
5722         }
5723
5724         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5725                                 sizeof(*vmdq_info) * conf_vsis, 0);
5726
5727         if (pf->vmdq == NULL) {
5728                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5729                 return -ENOMEM;
5730         }
5731
5732         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5733
5734         /* Create VMDQ VSI */
5735         for (i = 0; i < conf_vsis; i++) {
5736                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5737                                 vmdq_conf->enable_loop_back);
5738                 if (vsi == NULL) {
5739                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5740                         err = -1;
5741                         goto err_vsi_setup;
5742                 }
5743                 vmdq_info = &pf->vmdq[i];
5744                 vmdq_info->pf = pf;
5745                 vmdq_info->vsi = vsi;
5746         }
5747         pf->nb_cfg_vmdq_vsi = conf_vsis;
5748
5749         /* Configure Vlan */
5750         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5751         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5752                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5753                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5754                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5755                                         vmdq_conf->pool_map[i].vlan_id, j);
5756
5757                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5758                                                 vmdq_conf->pool_map[i].vlan_id);
5759                                 if (err) {
5760                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5761                                         err = -1;
5762                                         goto err_vsi_setup;
5763                                 }
5764                         }
5765                 }
5766         }
5767
5768         i40e_pf_enable_irq0(hw);
5769
5770         return 0;
5771
5772 err_vsi_setup:
5773         for (i = 0; i < conf_vsis; i++)
5774                 if (pf->vmdq[i].vsi == NULL)
5775                         break;
5776                 else
5777                         i40e_vsi_release(pf->vmdq[i].vsi);
5778
5779         rte_free(pf->vmdq);
5780         pf->vmdq = NULL;
5781         i40e_pf_enable_irq0(hw);
5782         return err;
5783 }
5784
5785 static void
5786 i40e_stat_update_32(struct i40e_hw *hw,
5787                    uint32_t reg,
5788                    bool offset_loaded,
5789                    uint64_t *offset,
5790                    uint64_t *stat)
5791 {
5792         uint64_t new_data;
5793
5794         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5795         if (!offset_loaded)
5796                 *offset = new_data;
5797
5798         if (new_data >= *offset)
5799                 *stat = (uint64_t)(new_data - *offset);
5800         else
5801                 *stat = (uint64_t)((new_data +
5802                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5803 }
5804
5805 static void
5806 i40e_stat_update_48(struct i40e_hw *hw,
5807                    uint32_t hireg,
5808                    uint32_t loreg,
5809                    bool offset_loaded,
5810                    uint64_t *offset,
5811                    uint64_t *stat)
5812 {
5813         uint64_t new_data;
5814
5815         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5816         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5817                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5818
5819         if (!offset_loaded)
5820                 *offset = new_data;
5821
5822         if (new_data >= *offset)
5823                 *stat = new_data - *offset;
5824         else
5825                 *stat = (uint64_t)((new_data +
5826                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5827
5828         *stat &= I40E_48_BIT_MASK;
5829 }
5830
5831 /* Disable IRQ0 */
5832 void
5833 i40e_pf_disable_irq0(struct i40e_hw *hw)
5834 {
5835         /* Disable all interrupt types */
5836         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5837         I40E_WRITE_FLUSH(hw);
5838 }
5839
5840 /* Enable IRQ0 */
5841 void
5842 i40e_pf_enable_irq0(struct i40e_hw *hw)
5843 {
5844         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5845                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5846                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5847                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5848         I40E_WRITE_FLUSH(hw);
5849 }
5850
5851 static void
5852 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5853 {
5854         /* read pending request and disable first */
5855         i40e_pf_disable_irq0(hw);
5856         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5857         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5858                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5859
5860         if (no_queue)
5861                 /* Link no queues with irq0 */
5862                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5863                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5864 }
5865
5866 static void
5867 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5868 {
5869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5871         int i;
5872         uint16_t abs_vf_id;
5873         uint32_t index, offset, val;
5874
5875         if (!pf->vfs)
5876                 return;
5877         /**
5878          * Try to find which VF trigger a reset, use absolute VF id to access
5879          * since the reg is global register.
5880          */
5881         for (i = 0; i < pf->vf_num; i++) {
5882                 abs_vf_id = hw->func_caps.vf_base_id + i;
5883                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5884                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5885                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5886                 /* VFR event occurred */
5887                 if (val & (0x1 << offset)) {
5888                         int ret;
5889
5890                         /* Clear the event first */
5891                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5892                                                         (0x1 << offset));
5893                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5894                         /**
5895                          * Only notify a VF reset event occurred,
5896                          * don't trigger another SW reset
5897                          */
5898                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5899                         if (ret != I40E_SUCCESS)
5900                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5901                 }
5902         }
5903 }
5904
5905 static void
5906 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5907 {
5908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5909         int i;
5910
5911         for (i = 0; i < pf->vf_num; i++)
5912                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5913 }
5914
5915 static void
5916 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5917 {
5918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5919         struct i40e_arq_event_info info;
5920         uint16_t pending, opcode;
5921         int ret;
5922
5923         info.buf_len = I40E_AQ_BUF_SZ;
5924         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5925         if (!info.msg_buf) {
5926                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5927                 return;
5928         }
5929
5930         pending = 1;
5931         while (pending) {
5932                 ret = i40e_clean_arq_element(hw, &info, &pending);
5933
5934                 if (ret != I40E_SUCCESS) {
5935                         PMD_DRV_LOG(INFO,
5936                                 "Failed to read msg from AdminQ, aq_err: %u",
5937                                 hw->aq.asq_last_status);
5938                         break;
5939                 }
5940                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5941
5942                 switch (opcode) {
5943                 case i40e_aqc_opc_send_msg_to_pf:
5944                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5945                         i40e_pf_host_handle_vf_msg(dev,
5946                                         rte_le_to_cpu_16(info.desc.retval),
5947                                         rte_le_to_cpu_32(info.desc.cookie_high),
5948                                         rte_le_to_cpu_32(info.desc.cookie_low),
5949                                         info.msg_buf,
5950                                         info.msg_len);
5951                         break;
5952                 case i40e_aqc_opc_get_link_status:
5953                         ret = i40e_dev_link_update(dev, 0);
5954                         if (!ret)
5955                                 _rte_eth_dev_callback_process(dev,
5956                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5957                         break;
5958                 default:
5959                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5960                                     opcode);
5961                         break;
5962                 }
5963         }
5964         rte_free(info.msg_buf);
5965 }
5966
5967 /**
5968  * Interrupt handler triggered by NIC  for handling
5969  * specific interrupt.
5970  *
5971  * @param handle
5972  *  Pointer to interrupt handle.
5973  * @param param
5974  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5975  *
5976  * @return
5977  *  void
5978  */
5979 static void
5980 i40e_dev_interrupt_handler(void *param)
5981 {
5982         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5984         uint32_t icr0;
5985
5986         /* Disable interrupt */
5987         i40e_pf_disable_irq0(hw);
5988
5989         /* read out interrupt causes */
5990         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5991
5992         /* No interrupt event indicated */
5993         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5994                 PMD_DRV_LOG(INFO, "No interrupt event");
5995                 goto done;
5996         }
5997         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5998                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5999         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6000                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6001         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6002                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6003         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6004                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6005         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6006                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6007         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6008                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6009         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6010                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6011
6012         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6013                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6014                 i40e_dev_handle_vfr_event(dev);
6015         }
6016         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6017                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6018                 i40e_dev_handle_aq_msg(dev);
6019         }
6020
6021 done:
6022         /* Enable interrupt */
6023         i40e_pf_enable_irq0(hw);
6024         rte_intr_enable(dev->intr_handle);
6025 }
6026
6027 int
6028 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6029                          struct i40e_macvlan_filter *filter,
6030                          int total)
6031 {
6032         int ele_num, ele_buff_size;
6033         int num, actual_num, i;
6034         uint16_t flags;
6035         int ret = I40E_SUCCESS;
6036         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6037         struct i40e_aqc_add_macvlan_element_data *req_list;
6038
6039         if (filter == NULL  || total == 0)
6040                 return I40E_ERR_PARAM;
6041         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6042         ele_buff_size = hw->aq.asq_buf_size;
6043
6044         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6045         if (req_list == NULL) {
6046                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6047                 return I40E_ERR_NO_MEMORY;
6048         }
6049
6050         num = 0;
6051         do {
6052                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6053                 memset(req_list, 0, ele_buff_size);
6054
6055                 for (i = 0; i < actual_num; i++) {
6056                         rte_memcpy(req_list[i].mac_addr,
6057                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6058                         req_list[i].vlan_tag =
6059                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6060
6061                         switch (filter[num + i].filter_type) {
6062                         case RTE_MAC_PERFECT_MATCH:
6063                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6064                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6065                                 break;
6066                         case RTE_MACVLAN_PERFECT_MATCH:
6067                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6068                                 break;
6069                         case RTE_MAC_HASH_MATCH:
6070                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6071                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6072                                 break;
6073                         case RTE_MACVLAN_HASH_MATCH:
6074                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6075                                 break;
6076                         default:
6077                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6078                                 ret = I40E_ERR_PARAM;
6079                                 goto DONE;
6080                         }
6081
6082                         req_list[i].queue_number = 0;
6083
6084                         req_list[i].flags = rte_cpu_to_le_16(flags);
6085                 }
6086
6087                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6088                                                 actual_num, NULL);
6089                 if (ret != I40E_SUCCESS) {
6090                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6091                         goto DONE;
6092                 }
6093                 num += actual_num;
6094         } while (num < total);
6095
6096 DONE:
6097         rte_free(req_list);
6098         return ret;
6099 }
6100
6101 int
6102 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6103                             struct i40e_macvlan_filter *filter,
6104                             int total)
6105 {
6106         int ele_num, ele_buff_size;
6107         int num, actual_num, i;
6108         uint16_t flags;
6109         int ret = I40E_SUCCESS;
6110         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6111         struct i40e_aqc_remove_macvlan_element_data *req_list;
6112
6113         if (filter == NULL  || total == 0)
6114                 return I40E_ERR_PARAM;
6115
6116         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6117         ele_buff_size = hw->aq.asq_buf_size;
6118
6119         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6120         if (req_list == NULL) {
6121                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6122                 return I40E_ERR_NO_MEMORY;
6123         }
6124
6125         num = 0;
6126         do {
6127                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6128                 memset(req_list, 0, ele_buff_size);
6129
6130                 for (i = 0; i < actual_num; i++) {
6131                         rte_memcpy(req_list[i].mac_addr,
6132                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6133                         req_list[i].vlan_tag =
6134                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6135
6136                         switch (filter[num + i].filter_type) {
6137                         case RTE_MAC_PERFECT_MATCH:
6138                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6139                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6140                                 break;
6141                         case RTE_MACVLAN_PERFECT_MATCH:
6142                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6143                                 break;
6144                         case RTE_MAC_HASH_MATCH:
6145                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6146                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6147                                 break;
6148                         case RTE_MACVLAN_HASH_MATCH:
6149                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6150                                 break;
6151                         default:
6152                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6153                                 ret = I40E_ERR_PARAM;
6154                                 goto DONE;
6155                         }
6156                         req_list[i].flags = rte_cpu_to_le_16(flags);
6157                 }
6158
6159                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6160                                                 actual_num, NULL);
6161                 if (ret != I40E_SUCCESS) {
6162                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6163                         goto DONE;
6164                 }
6165                 num += actual_num;
6166         } while (num < total);
6167
6168 DONE:
6169         rte_free(req_list);
6170         return ret;
6171 }
6172
6173 /* Find out specific MAC filter */
6174 static struct i40e_mac_filter *
6175 i40e_find_mac_filter(struct i40e_vsi *vsi,
6176                          struct ether_addr *macaddr)
6177 {
6178         struct i40e_mac_filter *f;
6179
6180         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6181                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6182                         return f;
6183         }
6184
6185         return NULL;
6186 }
6187
6188 static bool
6189 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6190                          uint16_t vlan_id)
6191 {
6192         uint32_t vid_idx, vid_bit;
6193
6194         if (vlan_id > ETH_VLAN_ID_MAX)
6195                 return 0;
6196
6197         vid_idx = I40E_VFTA_IDX(vlan_id);
6198         vid_bit = I40E_VFTA_BIT(vlan_id);
6199
6200         if (vsi->vfta[vid_idx] & vid_bit)
6201                 return 1;
6202         else
6203                 return 0;
6204 }
6205
6206 static void
6207 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6208                        uint16_t vlan_id, bool on)
6209 {
6210         uint32_t vid_idx, vid_bit;
6211
6212         vid_idx = I40E_VFTA_IDX(vlan_id);
6213         vid_bit = I40E_VFTA_BIT(vlan_id);
6214
6215         if (on)
6216                 vsi->vfta[vid_idx] |= vid_bit;
6217         else
6218                 vsi->vfta[vid_idx] &= ~vid_bit;
6219 }
6220
6221 void
6222 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6223                      uint16_t vlan_id, bool on)
6224 {
6225         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6226         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6227         int ret;
6228
6229         if (vlan_id > ETH_VLAN_ID_MAX)
6230                 return;
6231
6232         i40e_store_vlan_filter(vsi, vlan_id, on);
6233
6234         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6235                 return;
6236
6237         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6238
6239         if (on) {
6240                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6241                                        &vlan_data, 1, NULL);
6242                 if (ret != I40E_SUCCESS)
6243                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6244         } else {
6245                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6246                                           &vlan_data, 1, NULL);
6247                 if (ret != I40E_SUCCESS)
6248                         PMD_DRV_LOG(ERR,
6249                                     "Failed to remove vlan filter");
6250         }
6251 }
6252
6253 /**
6254  * Find all vlan options for specific mac addr,
6255  * return with actual vlan found.
6256  */
6257 int
6258 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6259                            struct i40e_macvlan_filter *mv_f,
6260                            int num, struct ether_addr *addr)
6261 {
6262         int i;
6263         uint32_t j, k;
6264
6265         /**
6266          * Not to use i40e_find_vlan_filter to decrease the loop time,
6267          * although the code looks complex.
6268           */
6269         if (num < vsi->vlan_num)
6270                 return I40E_ERR_PARAM;
6271
6272         i = 0;
6273         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6274                 if (vsi->vfta[j]) {
6275                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6276                                 if (vsi->vfta[j] & (1 << k)) {
6277                                         if (i > num - 1) {
6278                                                 PMD_DRV_LOG(ERR,
6279                                                         "vlan number doesn't match");
6280                                                 return I40E_ERR_PARAM;
6281                                         }
6282                                         rte_memcpy(&mv_f[i].macaddr,
6283                                                         addr, ETH_ADDR_LEN);
6284                                         mv_f[i].vlan_id =
6285                                                 j * I40E_UINT32_BIT_SIZE + k;
6286                                         i++;
6287                                 }
6288                         }
6289                 }
6290         }
6291         return I40E_SUCCESS;
6292 }
6293
6294 static inline int
6295 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6296                            struct i40e_macvlan_filter *mv_f,
6297                            int num,
6298                            uint16_t vlan)
6299 {
6300         int i = 0;
6301         struct i40e_mac_filter *f;
6302
6303         if (num < vsi->mac_num)
6304                 return I40E_ERR_PARAM;
6305
6306         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6307                 if (i > num - 1) {
6308                         PMD_DRV_LOG(ERR, "buffer number not match");
6309                         return I40E_ERR_PARAM;
6310                 }
6311                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6312                                 ETH_ADDR_LEN);
6313                 mv_f[i].vlan_id = vlan;
6314                 mv_f[i].filter_type = f->mac_info.filter_type;
6315                 i++;
6316         }
6317
6318         return I40E_SUCCESS;
6319 }
6320
6321 static int
6322 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6323 {
6324         int i, j, num;
6325         struct i40e_mac_filter *f;
6326         struct i40e_macvlan_filter *mv_f;
6327         int ret = I40E_SUCCESS;
6328
6329         if (vsi == NULL || vsi->mac_num == 0)
6330                 return I40E_ERR_PARAM;
6331
6332         /* Case that no vlan is set */
6333         if (vsi->vlan_num == 0)
6334                 num = vsi->mac_num;
6335         else
6336                 num = vsi->mac_num * vsi->vlan_num;
6337
6338         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6339         if (mv_f == NULL) {
6340                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6341                 return I40E_ERR_NO_MEMORY;
6342         }
6343
6344         i = 0;
6345         if (vsi->vlan_num == 0) {
6346                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6347                         rte_memcpy(&mv_f[i].macaddr,
6348                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6349                         mv_f[i].filter_type = f->mac_info.filter_type;
6350                         mv_f[i].vlan_id = 0;
6351                         i++;
6352                 }
6353         } else {
6354                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6355                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6356                                         vsi->vlan_num, &f->mac_info.mac_addr);
6357                         if (ret != I40E_SUCCESS)
6358                                 goto DONE;
6359                         for (j = i; j < i + vsi->vlan_num; j++)
6360                                 mv_f[j].filter_type = f->mac_info.filter_type;
6361                         i += vsi->vlan_num;
6362                 }
6363         }
6364
6365         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6366 DONE:
6367         rte_free(mv_f);
6368
6369         return ret;
6370 }
6371
6372 int
6373 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6374 {
6375         struct i40e_macvlan_filter *mv_f;
6376         int mac_num;
6377         int ret = I40E_SUCCESS;
6378
6379         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6380                 return I40E_ERR_PARAM;
6381
6382         /* If it's already set, just return */
6383         if (i40e_find_vlan_filter(vsi,vlan))
6384                 return I40E_SUCCESS;
6385
6386         mac_num = vsi->mac_num;
6387
6388         if (mac_num == 0) {
6389                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6390                 return I40E_ERR_PARAM;
6391         }
6392
6393         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6394
6395         if (mv_f == NULL) {
6396                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6397                 return I40E_ERR_NO_MEMORY;
6398         }
6399
6400         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6401
6402         if (ret != I40E_SUCCESS)
6403                 goto DONE;
6404
6405         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6406
6407         if (ret != I40E_SUCCESS)
6408                 goto DONE;
6409
6410         i40e_set_vlan_filter(vsi, vlan, 1);
6411
6412         vsi->vlan_num++;
6413         ret = I40E_SUCCESS;
6414 DONE:
6415         rte_free(mv_f);
6416         return ret;
6417 }
6418
6419 int
6420 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6421 {
6422         struct i40e_macvlan_filter *mv_f;
6423         int mac_num;
6424         int ret = I40E_SUCCESS;
6425
6426         /**
6427          * Vlan 0 is the generic filter for untagged packets
6428          * and can't be removed.
6429          */
6430         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6431                 return I40E_ERR_PARAM;
6432
6433         /* If can't find it, just return */
6434         if (!i40e_find_vlan_filter(vsi, vlan))
6435                 return I40E_ERR_PARAM;
6436
6437         mac_num = vsi->mac_num;
6438
6439         if (mac_num == 0) {
6440                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6441                 return I40E_ERR_PARAM;
6442         }
6443
6444         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6445
6446         if (mv_f == NULL) {
6447                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6448                 return I40E_ERR_NO_MEMORY;
6449         }
6450
6451         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6452
6453         if (ret != I40E_SUCCESS)
6454                 goto DONE;
6455
6456         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6457
6458         if (ret != I40E_SUCCESS)
6459                 goto DONE;
6460
6461         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6462         if (vsi->vlan_num == 1) {
6463                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6464                 if (ret != I40E_SUCCESS)
6465                         goto DONE;
6466
6467                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6468                 if (ret != I40E_SUCCESS)
6469                         goto DONE;
6470         }
6471
6472         i40e_set_vlan_filter(vsi, vlan, 0);
6473
6474         vsi->vlan_num--;
6475         ret = I40E_SUCCESS;
6476 DONE:
6477         rte_free(mv_f);
6478         return ret;
6479 }
6480
6481 int
6482 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6483 {
6484         struct i40e_mac_filter *f;
6485         struct i40e_macvlan_filter *mv_f;
6486         int i, vlan_num = 0;
6487         int ret = I40E_SUCCESS;
6488
6489         /* If it's add and we've config it, return */
6490         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6491         if (f != NULL)
6492                 return I40E_SUCCESS;
6493         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6494                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6495
6496                 /**
6497                  * If vlan_num is 0, that's the first time to add mac,
6498                  * set mask for vlan_id 0.
6499                  */
6500                 if (vsi->vlan_num == 0) {
6501                         i40e_set_vlan_filter(vsi, 0, 1);
6502                         vsi->vlan_num = 1;
6503                 }
6504                 vlan_num = vsi->vlan_num;
6505         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6506                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6507                 vlan_num = 1;
6508
6509         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6510         if (mv_f == NULL) {
6511                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6512                 return I40E_ERR_NO_MEMORY;
6513         }
6514
6515         for (i = 0; i < vlan_num; i++) {
6516                 mv_f[i].filter_type = mac_filter->filter_type;
6517                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6518                                 ETH_ADDR_LEN);
6519         }
6520
6521         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6522                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6523                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6524                                         &mac_filter->mac_addr);
6525                 if (ret != I40E_SUCCESS)
6526                         goto DONE;
6527         }
6528
6529         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6530         if (ret != I40E_SUCCESS)
6531                 goto DONE;
6532
6533         /* Add the mac addr into mac list */
6534         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6535         if (f == NULL) {
6536                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6537                 ret = I40E_ERR_NO_MEMORY;
6538                 goto DONE;
6539         }
6540         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6541                         ETH_ADDR_LEN);
6542         f->mac_info.filter_type = mac_filter->filter_type;
6543         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6544         vsi->mac_num++;
6545
6546         ret = I40E_SUCCESS;
6547 DONE:
6548         rte_free(mv_f);
6549
6550         return ret;
6551 }
6552
6553 int
6554 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6555 {
6556         struct i40e_mac_filter *f;
6557         struct i40e_macvlan_filter *mv_f;
6558         int i, vlan_num;
6559         enum rte_mac_filter_type filter_type;
6560         int ret = I40E_SUCCESS;
6561
6562         /* Can't find it, return an error */
6563         f = i40e_find_mac_filter(vsi, addr);
6564         if (f == NULL)
6565                 return I40E_ERR_PARAM;
6566
6567         vlan_num = vsi->vlan_num;
6568         filter_type = f->mac_info.filter_type;
6569         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6570                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6571                 if (vlan_num == 0) {
6572                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6573                         return I40E_ERR_PARAM;
6574                 }
6575         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6576                         filter_type == RTE_MAC_HASH_MATCH)
6577                 vlan_num = 1;
6578
6579         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6580         if (mv_f == NULL) {
6581                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6582                 return I40E_ERR_NO_MEMORY;
6583         }
6584
6585         for (i = 0; i < vlan_num; i++) {
6586                 mv_f[i].filter_type = filter_type;
6587                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6588                                 ETH_ADDR_LEN);
6589         }
6590         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6591                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6592                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6593                 if (ret != I40E_SUCCESS)
6594                         goto DONE;
6595         }
6596
6597         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6598         if (ret != I40E_SUCCESS)
6599                 goto DONE;
6600
6601         /* Remove the mac addr into mac list */
6602         TAILQ_REMOVE(&vsi->mac_list, f, next);
6603         rte_free(f);
6604         vsi->mac_num--;
6605
6606         ret = I40E_SUCCESS;
6607 DONE:
6608         rte_free(mv_f);
6609         return ret;
6610 }
6611
6612 /* Configure hash enable flags for RSS */
6613 uint64_t
6614 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6615 {
6616         uint64_t hena = 0;
6617
6618         if (!flags)
6619                 return hena;
6620
6621         if (flags & ETH_RSS_FRAG_IPV4)
6622                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6623         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6624                 if (type == I40E_MAC_X722) {
6625                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6626                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6627                 } else
6628                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6629         }
6630         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6631                 if (type == I40E_MAC_X722) {
6632                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6633                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6634                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6635                 } else
6636                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6637         }
6638         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6639                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6640         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6641                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6642         if (flags & ETH_RSS_FRAG_IPV6)
6643                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6644         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6645                 if (type == I40E_MAC_X722) {
6646                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6647                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6648                 } else
6649                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6650         }
6651         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6652                 if (type == I40E_MAC_X722) {
6653                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6654                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6655                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6656                 } else
6657                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6658         }
6659         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6660                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6661         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6662                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6663         if (flags & ETH_RSS_L2_PAYLOAD)
6664                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6665
6666         return hena;
6667 }
6668
6669 /* Parse the hash enable flags */
6670 uint64_t
6671 i40e_parse_hena(uint64_t flags)
6672 {
6673         uint64_t rss_hf = 0;
6674
6675         if (!flags)
6676                 return rss_hf;
6677         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6678                 rss_hf |= ETH_RSS_FRAG_IPV4;
6679         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6680                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6681         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6682                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6683         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6684                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6685         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6686                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6687         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6688                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6689         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6690                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6691         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6692                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6693         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6694                 rss_hf |= ETH_RSS_FRAG_IPV6;
6695         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6696                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6697         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6698                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6699         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6700                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6701         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6702                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6703         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6704                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6705         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6706                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6707         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6708                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6709         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6710                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6711
6712         return rss_hf;
6713 }
6714
6715 /* Disable RSS */
6716 static void
6717 i40e_pf_disable_rss(struct i40e_pf *pf)
6718 {
6719         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6720         uint64_t hena;
6721
6722         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6723         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6724         if (hw->mac.type == I40E_MAC_X722)
6725                 hena &= ~I40E_RSS_HENA_ALL_X722;
6726         else
6727                 hena &= ~I40E_RSS_HENA_ALL;
6728         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6729         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6730         I40E_WRITE_FLUSH(hw);
6731 }
6732
6733 static int
6734 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6735 {
6736         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6737         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6738         int ret = 0;
6739
6740         if (!key || key_len == 0) {
6741                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6742                 return 0;
6743         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6744                 sizeof(uint32_t)) {
6745                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6746                 return -EINVAL;
6747         }
6748
6749         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6750                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6751                         (struct i40e_aqc_get_set_rss_key_data *)key;
6752
6753                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6754                 if (ret)
6755                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6756         } else {
6757                 uint32_t *hash_key = (uint32_t *)key;
6758                 uint16_t i;
6759
6760                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6761                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6762                 I40E_WRITE_FLUSH(hw);
6763         }
6764
6765         return ret;
6766 }
6767
6768 static int
6769 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6770 {
6771         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6772         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6773         int ret;
6774
6775         if (!key || !key_len)
6776                 return -EINVAL;
6777
6778         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6779                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6780                         (struct i40e_aqc_get_set_rss_key_data *)key);
6781                 if (ret) {
6782                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6783                         return ret;
6784                 }
6785         } else {
6786                 uint32_t *key_dw = (uint32_t *)key;
6787                 uint16_t i;
6788
6789                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6790                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6791         }
6792         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6793
6794         return 0;
6795 }
6796
6797 static int
6798 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6799 {
6800         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6801         uint64_t rss_hf;
6802         uint64_t hena;
6803         int ret;
6804
6805         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6806                                rss_conf->rss_key_len);
6807         if (ret)
6808                 return ret;
6809
6810         rss_hf = rss_conf->rss_hf;
6811         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6812         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6813         if (hw->mac.type == I40E_MAC_X722)
6814                 hena &= ~I40E_RSS_HENA_ALL_X722;
6815         else
6816                 hena &= ~I40E_RSS_HENA_ALL;
6817         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6818         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6819         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6820         I40E_WRITE_FLUSH(hw);
6821
6822         return 0;
6823 }
6824
6825 static int
6826 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6827                          struct rte_eth_rss_conf *rss_conf)
6828 {
6829         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6831         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6832         uint64_t hena;
6833
6834         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6835         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6836         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6837                  ? I40E_RSS_HENA_ALL_X722
6838                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6839                 if (rss_hf != 0) /* Enable RSS */
6840                         return -EINVAL;
6841                 return 0; /* Nothing to do */
6842         }
6843         /* RSS enabled */
6844         if (rss_hf == 0) /* Disable RSS */
6845                 return -EINVAL;
6846
6847         return i40e_hw_rss_hash_set(pf, rss_conf);
6848 }
6849
6850 static int
6851 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6852                            struct rte_eth_rss_conf *rss_conf)
6853 {
6854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6856         uint64_t hena;
6857
6858         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6859                          &rss_conf->rss_key_len);
6860
6861         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6862         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6863         rss_conf->rss_hf = i40e_parse_hena(hena);
6864
6865         return 0;
6866 }
6867
6868 static int
6869 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6870 {
6871         switch (filter_type) {
6872         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6873                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6874                 break;
6875         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6876                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6877                 break;
6878         case RTE_TUNNEL_FILTER_IMAC_TENID:
6879                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6880                 break;
6881         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6882                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6883                 break;
6884         case ETH_TUNNEL_FILTER_IMAC:
6885                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6886                 break;
6887         case ETH_TUNNEL_FILTER_OIP:
6888                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6889                 break;
6890         case ETH_TUNNEL_FILTER_IIP:
6891                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6892                 break;
6893         default:
6894                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6895                 return -EINVAL;
6896         }
6897
6898         return 0;
6899 }
6900
6901 /* Convert tunnel filter structure */
6902 static int
6903 i40e_tunnel_filter_convert(
6904         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6905         struct i40e_tunnel_filter *tunnel_filter)
6906 {
6907         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6908                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6909         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6910                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6911         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6912         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6913              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6914             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6915                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6916         else
6917                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6918         tunnel_filter->input.flags = cld_filter->element.flags;
6919         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6920         tunnel_filter->queue = cld_filter->element.queue_number;
6921         rte_memcpy(tunnel_filter->input.general_fields,
6922                    cld_filter->general_fields,
6923                    sizeof(cld_filter->general_fields));
6924
6925         return 0;
6926 }
6927
6928 /* Check if there exists the tunnel filter */
6929 struct i40e_tunnel_filter *
6930 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6931                              const struct i40e_tunnel_filter_input *input)
6932 {
6933         int ret;
6934
6935         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6936         if (ret < 0)
6937                 return NULL;
6938
6939         return tunnel_rule->hash_map[ret];
6940 }
6941
6942 /* Add a tunnel filter into the SW list */
6943 static int
6944 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6945                              struct i40e_tunnel_filter *tunnel_filter)
6946 {
6947         struct i40e_tunnel_rule *rule = &pf->tunnel;
6948         int ret;
6949
6950         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6951         if (ret < 0) {
6952                 PMD_DRV_LOG(ERR,
6953                             "Failed to insert tunnel filter to hash table %d!",
6954                             ret);
6955                 return ret;
6956         }
6957         rule->hash_map[ret] = tunnel_filter;
6958
6959         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6960
6961         return 0;
6962 }
6963
6964 /* Delete a tunnel filter from the SW list */
6965 int
6966 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6967                           struct i40e_tunnel_filter_input *input)
6968 {
6969         struct i40e_tunnel_rule *rule = &pf->tunnel;
6970         struct i40e_tunnel_filter *tunnel_filter;
6971         int ret;
6972
6973         ret = rte_hash_del_key(rule->hash_table, input);
6974         if (ret < 0) {
6975                 PMD_DRV_LOG(ERR,
6976                             "Failed to delete tunnel filter to hash table %d!",
6977                             ret);
6978                 return ret;
6979         }
6980         tunnel_filter = rule->hash_map[ret];
6981         rule->hash_map[ret] = NULL;
6982
6983         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6984         rte_free(tunnel_filter);
6985
6986         return 0;
6987 }
6988
6989 int
6990 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6991                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6992                         uint8_t add)
6993 {
6994         uint16_t ip_type;
6995         uint32_t ipv4_addr;
6996         uint8_t i, tun_type = 0;
6997         /* internal varialbe to convert ipv6 byte order */
6998         uint32_t convert_ipv6[4];
6999         int val, ret = 0;
7000         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7001         struct i40e_vsi *vsi = pf->main_vsi;
7002         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7003         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7004         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7005         struct i40e_tunnel_filter *tunnel, *node;
7006         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7007
7008         cld_filter = rte_zmalloc("tunnel_filter",
7009                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7010         0);
7011
7012         if (NULL == cld_filter) {
7013                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7014                 return -ENOMEM;
7015         }
7016         pfilter = cld_filter;
7017
7018         ether_addr_copy(&tunnel_filter->outer_mac,
7019                         (struct ether_addr *)&pfilter->element.outer_mac);
7020         ether_addr_copy(&tunnel_filter->inner_mac,
7021                         (struct ether_addr *)&pfilter->element.inner_mac);
7022
7023         pfilter->element.inner_vlan =
7024                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7025         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7026                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7027                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7028                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7029                                 &rte_cpu_to_le_32(ipv4_addr),
7030                                 sizeof(pfilter->element.ipaddr.v4.data));
7031         } else {
7032                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7033                 for (i = 0; i < 4; i++) {
7034                         convert_ipv6[i] =
7035                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7036                 }
7037                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7038                            &convert_ipv6,
7039                            sizeof(pfilter->element.ipaddr.v6.data));
7040         }
7041
7042         /* check tunneled type */
7043         switch (tunnel_filter->tunnel_type) {
7044         case RTE_TUNNEL_TYPE_VXLAN:
7045                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7046                 break;
7047         case RTE_TUNNEL_TYPE_NVGRE:
7048                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7049                 break;
7050         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7051                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7052                 break;
7053         default:
7054                 /* Other tunnel types is not supported. */
7055                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7056                 rte_free(cld_filter);
7057                 return -EINVAL;
7058         }
7059
7060         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7061                                        &pfilter->element.flags);
7062         if (val < 0) {
7063                 rte_free(cld_filter);
7064                 return -EINVAL;
7065         }
7066
7067         pfilter->element.flags |= rte_cpu_to_le_16(
7068                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7069                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7070         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7071         pfilter->element.queue_number =
7072                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7073
7074         /* Check if there is the filter in SW list */
7075         memset(&check_filter, 0, sizeof(check_filter));
7076         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7077         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7078         if (add && node) {
7079                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7080                 return -EINVAL;
7081         }
7082
7083         if (!add && !node) {
7084                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7085                 return -EINVAL;
7086         }
7087
7088         if (add) {
7089                 ret = i40e_aq_add_cloud_filters(hw,
7090                                         vsi->seid, &cld_filter->element, 1);
7091                 if (ret < 0) {
7092                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7093                         return -ENOTSUP;
7094                 }
7095                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7096                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7097                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7098         } else {
7099                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7100                                                    &cld_filter->element, 1);
7101                 if (ret < 0) {
7102                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7103                         return -ENOTSUP;
7104                 }
7105                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7106         }
7107
7108         rte_free(cld_filter);
7109         return ret;
7110 }
7111
7112 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7113 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7114 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7115 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7116 #define I40E_TR_GRE_KEY_MASK                    0x400
7117 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7118 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7119
7120 static enum
7121 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7122 {
7123         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7124         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7125         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7126         enum i40e_status_code status = I40E_SUCCESS;
7127
7128         memset(&filter_replace, 0,
7129                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7130         memset(&filter_replace_buf, 0,
7131                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7132
7133         /* create L1 filter */
7134         filter_replace.old_filter_type =
7135                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7136         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7137         filter_replace.tr_bit = 0;
7138
7139         /* Prepare the buffer, 3 entries */
7140         filter_replace_buf.data[0] =
7141                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7142         filter_replace_buf.data[0] |=
7143                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7144         filter_replace_buf.data[2] = 0xFF;
7145         filter_replace_buf.data[3] = 0xFF;
7146         filter_replace_buf.data[4] =
7147                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7148         filter_replace_buf.data[4] |=
7149                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7150         filter_replace_buf.data[7] = 0xF0;
7151         filter_replace_buf.data[8]
7152                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7153         filter_replace_buf.data[8] |=
7154                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7155         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7156                 I40E_TR_GENEVE_KEY_MASK |
7157                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7158         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7159                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7160                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7161
7162         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7163                                                &filter_replace_buf);
7164         return status;
7165 }
7166
7167 static enum
7168 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7169 {
7170         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7171         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7172         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7173         enum i40e_status_code status = I40E_SUCCESS;
7174
7175         /* For MPLSoUDP */
7176         memset(&filter_replace, 0,
7177                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7178         memset(&filter_replace_buf, 0,
7179                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7180         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7181                 I40E_AQC_MIRROR_CLOUD_FILTER;
7182         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7183         filter_replace.new_filter_type =
7184                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7185         /* Prepare the buffer, 2 entries */
7186         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7187         filter_replace_buf.data[0] |=
7188                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7189         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7190         filter_replace_buf.data[4] |=
7191                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7192         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7193                                                &filter_replace_buf);
7194         if (status < 0)
7195                 return status;
7196
7197         /* For MPLSoGRE */
7198         memset(&filter_replace, 0,
7199                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7200         memset(&filter_replace_buf, 0,
7201                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7202
7203         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7204                 I40E_AQC_MIRROR_CLOUD_FILTER;
7205         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7206         filter_replace.new_filter_type =
7207                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7208         /* Prepare the buffer, 2 entries */
7209         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7210         filter_replace_buf.data[0] |=
7211                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7212         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7213         filter_replace_buf.data[4] |=
7214                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7215
7216         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7217                                                &filter_replace_buf);
7218         return status;
7219 }
7220
7221 int
7222 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7223                       struct i40e_tunnel_filter_conf *tunnel_filter,
7224                       uint8_t add)
7225 {
7226         uint16_t ip_type;
7227         uint32_t ipv4_addr;
7228         uint8_t i, tun_type = 0;
7229         /* internal variable to convert ipv6 byte order */
7230         uint32_t convert_ipv6[4];
7231         int val, ret = 0;
7232         struct i40e_pf_vf *vf = NULL;
7233         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7234         struct i40e_vsi *vsi;
7235         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7236         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7237         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7238         struct i40e_tunnel_filter *tunnel, *node;
7239         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7240         uint32_t teid_le;
7241         bool big_buffer = 0;
7242
7243         cld_filter = rte_zmalloc("tunnel_filter",
7244                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7245                          0);
7246
7247         if (cld_filter == NULL) {
7248                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7249                 return -ENOMEM;
7250         }
7251         pfilter = cld_filter;
7252
7253         ether_addr_copy(&tunnel_filter->outer_mac,
7254                         (struct ether_addr *)&pfilter->element.outer_mac);
7255         ether_addr_copy(&tunnel_filter->inner_mac,
7256                         (struct ether_addr *)&pfilter->element.inner_mac);
7257
7258         pfilter->element.inner_vlan =
7259                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7260         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7261                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7262                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7263                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7264                                 &rte_cpu_to_le_32(ipv4_addr),
7265                                 sizeof(pfilter->element.ipaddr.v4.data));
7266         } else {
7267                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7268                 for (i = 0; i < 4; i++) {
7269                         convert_ipv6[i] =
7270                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7271                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7272                 }
7273                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7274                            &convert_ipv6,
7275                            sizeof(pfilter->element.ipaddr.v6.data));
7276         }
7277
7278         /* check tunneled type */
7279         switch (tunnel_filter->tunnel_type) {
7280         case I40E_TUNNEL_TYPE_VXLAN:
7281                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7282                 break;
7283         case I40E_TUNNEL_TYPE_NVGRE:
7284                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7285                 break;
7286         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7287                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7288                 break;
7289         case I40E_TUNNEL_TYPE_MPLSoUDP:
7290                 if (!pf->mpls_replace_flag) {
7291                         i40e_replace_mpls_l1_filter(pf);
7292                         i40e_replace_mpls_cloud_filter(pf);
7293                         pf->mpls_replace_flag = 1;
7294                 }
7295                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7296                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7297                         teid_le >> 4;
7298                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7299                         (teid_le & 0xF) << 12;
7300                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7301                         0x40;
7302                 big_buffer = 1;
7303                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7304                 break;
7305         case I40E_TUNNEL_TYPE_MPLSoGRE:
7306                 if (!pf->mpls_replace_flag) {
7307                         i40e_replace_mpls_l1_filter(pf);
7308                         i40e_replace_mpls_cloud_filter(pf);
7309                         pf->mpls_replace_flag = 1;
7310                 }
7311                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7312                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7313                         teid_le >> 4;
7314                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7315                         (teid_le & 0xF) << 12;
7316                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7317                         0x0;
7318                 big_buffer = 1;
7319                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7320                 break;
7321         case I40E_TUNNEL_TYPE_QINQ:
7322                 if (!pf->qinq_replace_flag) {
7323                         ret = i40e_cloud_filter_qinq_create(pf);
7324                         if (ret < 0)
7325                                 PMD_DRV_LOG(DEBUG,
7326                                             "QinQ tunnel filter already created.");
7327                         pf->qinq_replace_flag = 1;
7328                 }
7329                 /*      Add in the General fields the values of
7330                  *      the Outer and Inner VLAN
7331                  *      Big Buffer should be set, see changes in
7332                  *      i40e_aq_add_cloud_filters
7333                  */
7334                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7335                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7336                 big_buffer = 1;
7337                 break;
7338         default:
7339                 /* Other tunnel types is not supported. */
7340                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7341                 rte_free(cld_filter);
7342                 return -EINVAL;
7343         }
7344
7345         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7346                 pfilter->element.flags =
7347                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7348         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7349                 pfilter->element.flags =
7350                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7351         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7352                 pfilter->element.flags |=
7353                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7354         else {
7355                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7356                                                 &pfilter->element.flags);
7357                 if (val < 0) {
7358                         rte_free(cld_filter);
7359                         return -EINVAL;
7360                 }
7361         }
7362
7363         pfilter->element.flags |= rte_cpu_to_le_16(
7364                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7365                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7366         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7367         pfilter->element.queue_number =
7368                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7369
7370         if (!tunnel_filter->is_to_vf)
7371                 vsi = pf->main_vsi;
7372         else {
7373                 if (tunnel_filter->vf_id >= pf->vf_num) {
7374                         PMD_DRV_LOG(ERR, "Invalid argument.");
7375                         return -EINVAL;
7376                 }
7377                 vf = &pf->vfs[tunnel_filter->vf_id];
7378                 vsi = vf->vsi;
7379         }
7380
7381         /* Check if there is the filter in SW list */
7382         memset(&check_filter, 0, sizeof(check_filter));
7383         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7384         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7385         check_filter.vf_id = tunnel_filter->vf_id;
7386         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7387         if (add && node) {
7388                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7389                 return -EINVAL;
7390         }
7391
7392         if (!add && !node) {
7393                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7394                 return -EINVAL;
7395         }
7396
7397         if (add) {
7398                 if (big_buffer)
7399                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7400                                                    vsi->seid, cld_filter, 1);
7401                 else
7402                         ret = i40e_aq_add_cloud_filters(hw,
7403                                         vsi->seid, &cld_filter->element, 1);
7404                 if (ret < 0) {
7405                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7406                         return -ENOTSUP;
7407                 }
7408                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7409                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7410                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7411         } else {
7412                 if (big_buffer)
7413                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7414                                 hw, vsi->seid, cld_filter, 1);
7415                 else
7416                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7417                                                    &cld_filter->element, 1);
7418                 if (ret < 0) {
7419                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7420                         return -ENOTSUP;
7421                 }
7422                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7423         }
7424
7425         rte_free(cld_filter);
7426         return ret;
7427 }
7428
7429 static int
7430 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7431 {
7432         uint8_t i;
7433
7434         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7435                 if (pf->vxlan_ports[i] == port)
7436                         return i;
7437         }
7438
7439         return -1;
7440 }
7441
7442 static int
7443 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7444 {
7445         int  idx, ret;
7446         uint8_t filter_idx;
7447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7448
7449         idx = i40e_get_vxlan_port_idx(pf, port);
7450
7451         /* Check if port already exists */
7452         if (idx >= 0) {
7453                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7454                 return -EINVAL;
7455         }
7456
7457         /* Now check if there is space to add the new port */
7458         idx = i40e_get_vxlan_port_idx(pf, 0);
7459         if (idx < 0) {
7460                 PMD_DRV_LOG(ERR,
7461                         "Maximum number of UDP ports reached, not adding port %d",
7462                         port);
7463                 return -ENOSPC;
7464         }
7465
7466         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7467                                         &filter_idx, NULL);
7468         if (ret < 0) {
7469                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7470                 return -1;
7471         }
7472
7473         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7474                          port,  filter_idx);
7475
7476         /* New port: add it and mark its index in the bitmap */
7477         pf->vxlan_ports[idx] = port;
7478         pf->vxlan_bitmap |= (1 << idx);
7479
7480         if (!(pf->flags & I40E_FLAG_VXLAN))
7481                 pf->flags |= I40E_FLAG_VXLAN;
7482
7483         return 0;
7484 }
7485
7486 static int
7487 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7488 {
7489         int idx;
7490         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7491
7492         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7493                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7494                 return -EINVAL;
7495         }
7496
7497         idx = i40e_get_vxlan_port_idx(pf, port);
7498
7499         if (idx < 0) {
7500                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7501                 return -EINVAL;
7502         }
7503
7504         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7505                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7506                 return -1;
7507         }
7508
7509         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7510                         port, idx);
7511
7512         pf->vxlan_ports[idx] = 0;
7513         pf->vxlan_bitmap &= ~(1 << idx);
7514
7515         if (!pf->vxlan_bitmap)
7516                 pf->flags &= ~I40E_FLAG_VXLAN;
7517
7518         return 0;
7519 }
7520
7521 /* Add UDP tunneling port */
7522 static int
7523 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7524                              struct rte_eth_udp_tunnel *udp_tunnel)
7525 {
7526         int ret = 0;
7527         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7528
7529         if (udp_tunnel == NULL)
7530                 return -EINVAL;
7531
7532         switch (udp_tunnel->prot_type) {
7533         case RTE_TUNNEL_TYPE_VXLAN:
7534                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7535                 break;
7536
7537         case RTE_TUNNEL_TYPE_GENEVE:
7538         case RTE_TUNNEL_TYPE_TEREDO:
7539                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7540                 ret = -1;
7541                 break;
7542
7543         default:
7544                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7545                 ret = -1;
7546                 break;
7547         }
7548
7549         return ret;
7550 }
7551
7552 /* Remove UDP tunneling port */
7553 static int
7554 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7555                              struct rte_eth_udp_tunnel *udp_tunnel)
7556 {
7557         int ret = 0;
7558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7559
7560         if (udp_tunnel == NULL)
7561                 return -EINVAL;
7562
7563         switch (udp_tunnel->prot_type) {
7564         case RTE_TUNNEL_TYPE_VXLAN:
7565                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7566                 break;
7567         case RTE_TUNNEL_TYPE_GENEVE:
7568         case RTE_TUNNEL_TYPE_TEREDO:
7569                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7570                 ret = -1;
7571                 break;
7572         default:
7573                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7574                 ret = -1;
7575                 break;
7576         }
7577
7578         return ret;
7579 }
7580
7581 /* Calculate the maximum number of contiguous PF queues that are configured */
7582 static int
7583 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7584 {
7585         struct rte_eth_dev_data *data = pf->dev_data;
7586         int i, num;
7587         struct i40e_rx_queue *rxq;
7588
7589         num = 0;
7590         for (i = 0; i < pf->lan_nb_qps; i++) {
7591                 rxq = data->rx_queues[i];
7592                 if (rxq && rxq->q_set)
7593                         num++;
7594                 else
7595                         break;
7596         }
7597
7598         return num;
7599 }
7600
7601 /* Configure RSS */
7602 static int
7603 i40e_pf_config_rss(struct i40e_pf *pf)
7604 {
7605         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7606         struct rte_eth_rss_conf rss_conf;
7607         uint32_t i, lut = 0;
7608         uint16_t j, num;
7609
7610         /*
7611          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7612          * It's necessary to calculate the actual PF queues that are configured.
7613          */
7614         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7615                 num = i40e_pf_calc_configured_queues_num(pf);
7616         else
7617                 num = pf->dev_data->nb_rx_queues;
7618
7619         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7620         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7621                         num);
7622
7623         if (num == 0) {
7624                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7625                 return -ENOTSUP;
7626         }
7627
7628         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7629                 if (j == num)
7630                         j = 0;
7631                 lut = (lut << 8) | (j & ((0x1 <<
7632                         hw->func_caps.rss_table_entry_width) - 1));
7633                 if ((i & 3) == 3)
7634                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7635         }
7636
7637         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7638         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7639                 i40e_pf_disable_rss(pf);
7640                 return 0;
7641         }
7642         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7643                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7644                 /* Random default keys */
7645                 static uint32_t rss_key_default[] = {0x6b793944,
7646                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7647                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7648                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7649
7650                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7651                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7652                                                         sizeof(uint32_t);
7653         }
7654
7655         return i40e_hw_rss_hash_set(pf, &rss_conf);
7656 }
7657
7658 static int
7659 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7660                                struct rte_eth_tunnel_filter_conf *filter)
7661 {
7662         if (pf == NULL || filter == NULL) {
7663                 PMD_DRV_LOG(ERR, "Invalid parameter");
7664                 return -EINVAL;
7665         }
7666
7667         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7668                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7669                 return -EINVAL;
7670         }
7671
7672         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7673                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7674                 return -EINVAL;
7675         }
7676
7677         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7678                 (is_zero_ether_addr(&filter->outer_mac))) {
7679                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7680                 return -EINVAL;
7681         }
7682
7683         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7684                 (is_zero_ether_addr(&filter->inner_mac))) {
7685                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7686                 return -EINVAL;
7687         }
7688
7689         return 0;
7690 }
7691
7692 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7693 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7694 static int
7695 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7696 {
7697         uint32_t val, reg;
7698         int ret = -EINVAL;
7699
7700         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7701         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7702
7703         if (len == 3) {
7704                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7705         } else if (len == 4) {
7706                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7707         } else {
7708                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7709                 return ret;
7710         }
7711
7712         if (reg != val) {
7713                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7714                                                    reg, NULL);
7715                 if (ret != 0)
7716                         return ret;
7717         } else {
7718                 ret = 0;
7719         }
7720         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7721                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7722
7723         return ret;
7724 }
7725
7726 static int
7727 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7728 {
7729         int ret = -EINVAL;
7730
7731         if (!hw || !cfg)
7732                 return -EINVAL;
7733
7734         switch (cfg->cfg_type) {
7735         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7736                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7737                 break;
7738         default:
7739                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7740                 break;
7741         }
7742
7743         return ret;
7744 }
7745
7746 static int
7747 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7748                                enum rte_filter_op filter_op,
7749                                void *arg)
7750 {
7751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7752         int ret = I40E_ERR_PARAM;
7753
7754         switch (filter_op) {
7755         case RTE_ETH_FILTER_SET:
7756                 ret = i40e_dev_global_config_set(hw,
7757                         (struct rte_eth_global_cfg *)arg);
7758                 break;
7759         default:
7760                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7761                 break;
7762         }
7763
7764         return ret;
7765 }
7766
7767 static int
7768 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7769                           enum rte_filter_op filter_op,
7770                           void *arg)
7771 {
7772         struct rte_eth_tunnel_filter_conf *filter;
7773         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7774         int ret = I40E_SUCCESS;
7775
7776         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7777
7778         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7779                 return I40E_ERR_PARAM;
7780
7781         switch (filter_op) {
7782         case RTE_ETH_FILTER_NOP:
7783                 if (!(pf->flags & I40E_FLAG_VXLAN))
7784                         ret = I40E_NOT_SUPPORTED;
7785                 break;
7786         case RTE_ETH_FILTER_ADD:
7787                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7788                 break;
7789         case RTE_ETH_FILTER_DELETE:
7790                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7791                 break;
7792         default:
7793                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7794                 ret = I40E_ERR_PARAM;
7795                 break;
7796         }
7797
7798         return ret;
7799 }
7800
7801 static int
7802 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7803 {
7804         int ret = 0;
7805         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7806
7807         /* RSS setup */
7808         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7809                 ret = i40e_pf_config_rss(pf);
7810         else
7811                 i40e_pf_disable_rss(pf);
7812
7813         return ret;
7814 }
7815
7816 /* Get the symmetric hash enable configurations per port */
7817 static void
7818 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7819 {
7820         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7821
7822         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7823 }
7824
7825 /* Set the symmetric hash enable configurations per port */
7826 static void
7827 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7828 {
7829         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7830
7831         if (enable > 0) {
7832                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7833                         PMD_DRV_LOG(INFO,
7834                                 "Symmetric hash has already been enabled");
7835                         return;
7836                 }
7837                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7838         } else {
7839                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7840                         PMD_DRV_LOG(INFO,
7841                                 "Symmetric hash has already been disabled");
7842                         return;
7843                 }
7844                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7845         }
7846         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7847         I40E_WRITE_FLUSH(hw);
7848 }
7849
7850 /*
7851  * Get global configurations of hash function type and symmetric hash enable
7852  * per flow type (pctype). Note that global configuration means it affects all
7853  * the ports on the same NIC.
7854  */
7855 static int
7856 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7857                                    struct rte_eth_hash_global_conf *g_cfg)
7858 {
7859         uint32_t reg, mask = I40E_FLOW_TYPES;
7860         uint16_t i;
7861         enum i40e_filter_pctype pctype;
7862
7863         memset(g_cfg, 0, sizeof(*g_cfg));
7864         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7865         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7866                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7867         else
7868                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7869         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7870                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7871
7872         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7873                 if (!(mask & (1UL << i)))
7874                         continue;
7875                 mask &= ~(1UL << i);
7876                 /* Bit set indicats the coresponding flow type is supported */
7877                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7878                 /* if flowtype is invalid, continue */
7879                 if (!I40E_VALID_FLOW(i))
7880                         continue;
7881                 pctype = i40e_flowtype_to_pctype(i);
7882                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7883                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7884                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7885         }
7886
7887         return 0;
7888 }
7889
7890 static int
7891 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7892 {
7893         uint32_t i;
7894         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7895
7896         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7897                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7898                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7899                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7900                                                 g_cfg->hash_func);
7901                 return -EINVAL;
7902         }
7903
7904         /*
7905          * As i40e supports less than 32 flow types, only first 32 bits need to
7906          * be checked.
7907          */
7908         mask0 = g_cfg->valid_bit_mask[0];
7909         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7910                 if (i == 0) {
7911                         /* Check if any unsupported flow type configured */
7912                         if ((mask0 | i40e_mask) ^ i40e_mask)
7913                                 goto mask_err;
7914                 } else {
7915                         if (g_cfg->valid_bit_mask[i])
7916                                 goto mask_err;
7917                 }
7918         }
7919
7920         return 0;
7921
7922 mask_err:
7923         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7924
7925         return -EINVAL;
7926 }
7927
7928 /*
7929  * Set global configurations of hash function type and symmetric hash enable
7930  * per flow type (pctype). Note any modifying global configuration will affect
7931  * all the ports on the same NIC.
7932  */
7933 static int
7934 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7935                                    struct rte_eth_hash_global_conf *g_cfg)
7936 {
7937         int ret;
7938         uint16_t i;
7939         uint32_t reg;
7940         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7941         enum i40e_filter_pctype pctype;
7942
7943         /* Check the input parameters */
7944         ret = i40e_hash_global_config_check(g_cfg);
7945         if (ret < 0)
7946                 return ret;
7947
7948         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7949                 if (!(mask0 & (1UL << i)))
7950                         continue;
7951                 mask0 &= ~(1UL << i);
7952                 /* if flowtype is invalid, continue */
7953                 if (!I40E_VALID_FLOW(i))
7954                         continue;
7955                 pctype = i40e_flowtype_to_pctype(i);
7956                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7957                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7958                 if (hw->mac.type == I40E_MAC_X722) {
7959                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7960                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7961                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7962                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7963                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7964                                   reg);
7965                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7966                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7967                                   reg);
7968                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7969                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7970                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7971                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7972                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7973                                   reg);
7974                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7975                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7976                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7977                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7978                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7979                                   reg);
7980                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7981                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7982                                   reg);
7983                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7984                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7985                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7986                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7987                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7988                                   reg);
7989                         } else {
7990                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7991                                   reg);
7992                         }
7993                 } else {
7994                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7995                 }
7996         }
7997
7998         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7999         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8000                 /* Toeplitz */
8001                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8002                         PMD_DRV_LOG(DEBUG,
8003                                 "Hash function already set to Toeplitz");
8004                         goto out;
8005                 }
8006                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8007         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8008                 /* Simple XOR */
8009                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8010                         PMD_DRV_LOG(DEBUG,
8011                                 "Hash function already set to Simple XOR");
8012                         goto out;
8013                 }
8014                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8015         } else
8016                 /* Use the default, and keep it as it is */
8017                 goto out;
8018
8019         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8020
8021 out:
8022         I40E_WRITE_FLUSH(hw);
8023
8024         return 0;
8025 }
8026
8027 /**
8028  * Valid input sets for hash and flow director filters per PCTYPE
8029  */
8030 static uint64_t
8031 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8032                 enum rte_filter_type filter)
8033 {
8034         uint64_t valid;
8035
8036         static const uint64_t valid_hash_inset_table[] = {
8037                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8038                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8039                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8040                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8041                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8042                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8043                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8044                         I40E_INSET_FLEX_PAYLOAD,
8045                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8046                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8047                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8048                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8049                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8050                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8051                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8052                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8053                         I40E_INSET_FLEX_PAYLOAD,
8054                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8055                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8056                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8057                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8058                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8059                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8060                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8061                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8062                         I40E_INSET_FLEX_PAYLOAD,
8063                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8064                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8065                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8066                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8067                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8068                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8069                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8070                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8071                         I40E_INSET_FLEX_PAYLOAD,
8072                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8076                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8077                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8078                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8079                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8080                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8081                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8082                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8083                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8084                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8085                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8086                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8087                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8088                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8089                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8090                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8091                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8092                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8093                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8094                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8095                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8096                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8097                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8098                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8099                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8100                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8101                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8102                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8103                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8104                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8105                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8106                         I40E_INSET_FLEX_PAYLOAD,
8107                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8108                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8109                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8110                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8111                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8112                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8113                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8114                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8115                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8116                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8117                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8118                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8119                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8120                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8121                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8122                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8123                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8124                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8125                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8126                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8127                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8128                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8129                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8130                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8131                         I40E_INSET_FLEX_PAYLOAD,
8132                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8133                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8134                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8135                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8136                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8137                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8138                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8139                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8140                         I40E_INSET_FLEX_PAYLOAD,
8141                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8142                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8143                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8144                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8145                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8146                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8147                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8148                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8149                         I40E_INSET_FLEX_PAYLOAD,
8150                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8151                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8152                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8153                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8154                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8155                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8156                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8157                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8158                         I40E_INSET_FLEX_PAYLOAD,
8159                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8160                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8161                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8162                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8163                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8164                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8165                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8166                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8167                         I40E_INSET_FLEX_PAYLOAD,
8168                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8169                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8170                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8171                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8172                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8173                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8174                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8175                         I40E_INSET_FLEX_PAYLOAD,
8176                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8177                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8178                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8179                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8180                         I40E_INSET_FLEX_PAYLOAD,
8181         };
8182
8183         /**
8184          * Flow director supports only fields defined in
8185          * union rte_eth_fdir_flow.
8186          */
8187         static const uint64_t valid_fdir_inset_table[] = {
8188                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8189                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8190                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8191                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8192                 I40E_INSET_IPV4_TTL,
8193                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8194                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8195                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8196                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8197                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8198                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8199                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8200                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8201                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8202                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8203                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8204                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8205                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8206                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8207                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8208                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8209                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8210                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8211                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8212                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8213                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8214                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8215                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8216                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8217                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8218                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8219                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8220                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8221                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8222                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8223                 I40E_INSET_SCTP_VT,
8224                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8225                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8226                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8227                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8228                 I40E_INSET_IPV4_TTL,
8229                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8230                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8231                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8232                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8233                 I40E_INSET_IPV6_HOP_LIMIT,
8234                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8235                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8236                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8237                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8238                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8239                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8240                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8241                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8242                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8243                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8244                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8245                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8246                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8247                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8248                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8249                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8250                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8251                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8252                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8253                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8254                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8255                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8256                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8257                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8258                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8259                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8260                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8261                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8262                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8263                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8264                 I40E_INSET_SCTP_VT,
8265                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8266                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8267                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8268                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8269                 I40E_INSET_IPV6_HOP_LIMIT,
8270                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8271                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8272                 I40E_INSET_LAST_ETHER_TYPE,
8273         };
8274
8275         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8276                 return 0;
8277         if (filter == RTE_ETH_FILTER_HASH)
8278                 valid = valid_hash_inset_table[pctype];
8279         else
8280                 valid = valid_fdir_inset_table[pctype];
8281
8282         return valid;
8283 }
8284
8285 /**
8286  * Validate if the input set is allowed for a specific PCTYPE
8287  */
8288 int
8289 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8290                 enum rte_filter_type filter, uint64_t inset)
8291 {
8292         uint64_t valid;
8293
8294         valid = i40e_get_valid_input_set(pctype, filter);
8295         if (inset & (~valid))
8296                 return -EINVAL;
8297
8298         return 0;
8299 }
8300
8301 /* default input set fields combination per pctype */
8302 uint64_t
8303 i40e_get_default_input_set(uint16_t pctype)
8304 {
8305         static const uint64_t default_inset_table[] = {
8306                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8307                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8308                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8309                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8310                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8311                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8312                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8313                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8314                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8315                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8316                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8317                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8318                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8319                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8320                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8321                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8322                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8323                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8324                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8325                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8326                         I40E_INSET_SCTP_VT,
8327                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8328                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8329                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8330                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8331                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8332                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8333                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8334                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8335                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8336                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8337                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8338                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8339                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8340                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8341                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8342                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8343                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8344                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8345                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8346                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8347                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8348                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8349                         I40E_INSET_SCTP_VT,
8350                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8351                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8352                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8353                         I40E_INSET_LAST_ETHER_TYPE,
8354         };
8355
8356         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8357                 return 0;
8358
8359         return default_inset_table[pctype];
8360 }
8361
8362 /**
8363  * Parse the input set from index to logical bit masks
8364  */
8365 static int
8366 i40e_parse_input_set(uint64_t *inset,
8367                      enum i40e_filter_pctype pctype,
8368                      enum rte_eth_input_set_field *field,
8369                      uint16_t size)
8370 {
8371         uint16_t i, j;
8372         int ret = -EINVAL;
8373
8374         static const struct {
8375                 enum rte_eth_input_set_field field;
8376                 uint64_t inset;
8377         } inset_convert_table[] = {
8378                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8379                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8380                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8381                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8382                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8383                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8384                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8385                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8386                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8387                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8388                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8389                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8390                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8391                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8392                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8393                         I40E_INSET_IPV6_NEXT_HDR},
8394                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8395                         I40E_INSET_IPV6_HOP_LIMIT},
8396                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8397                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8398                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8399                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8400                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8401                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8402                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8403                         I40E_INSET_SCTP_VT},
8404                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8405                         I40E_INSET_TUNNEL_DMAC},
8406                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8407                         I40E_INSET_VLAN_TUNNEL},
8408                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8409                         I40E_INSET_TUNNEL_ID},
8410                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8411                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8412                         I40E_INSET_FLEX_PAYLOAD_W1},
8413                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8414                         I40E_INSET_FLEX_PAYLOAD_W2},
8415                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8416                         I40E_INSET_FLEX_PAYLOAD_W3},
8417                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8418                         I40E_INSET_FLEX_PAYLOAD_W4},
8419                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8420                         I40E_INSET_FLEX_PAYLOAD_W5},
8421                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8422                         I40E_INSET_FLEX_PAYLOAD_W6},
8423                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8424                         I40E_INSET_FLEX_PAYLOAD_W7},
8425                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8426                         I40E_INSET_FLEX_PAYLOAD_W8},
8427         };
8428
8429         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8430                 return ret;
8431
8432         /* Only one item allowed for default or all */
8433         if (size == 1) {
8434                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8435                         *inset = i40e_get_default_input_set(pctype);
8436                         return 0;
8437                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8438                         *inset = I40E_INSET_NONE;
8439                         return 0;
8440                 }
8441         }
8442
8443         for (i = 0, *inset = 0; i < size; i++) {
8444                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8445                         if (field[i] == inset_convert_table[j].field) {
8446                                 *inset |= inset_convert_table[j].inset;
8447                                 break;
8448                         }
8449                 }
8450
8451                 /* It contains unsupported input set, return immediately */
8452                 if (j == RTE_DIM(inset_convert_table))
8453                         return ret;
8454         }
8455
8456         return 0;
8457 }
8458
8459 /**
8460  * Translate the input set from bit masks to register aware bit masks
8461  * and vice versa
8462  */
8463 uint64_t
8464 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8465 {
8466         uint64_t val = 0;
8467         uint16_t i;
8468
8469         struct inset_map {
8470                 uint64_t inset;
8471                 uint64_t inset_reg;
8472         };
8473
8474         static const struct inset_map inset_map_common[] = {
8475                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8476                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8477                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8478                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8479                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8480                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8481                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8482                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8483                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8484                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8485                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8486                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8487                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8488                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8489                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8490                 {I40E_INSET_TUNNEL_DMAC,
8491                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8492                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8493                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8494                 {I40E_INSET_TUNNEL_SRC_PORT,
8495                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8496                 {I40E_INSET_TUNNEL_DST_PORT,
8497                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8498                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8499                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8500                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8501                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8502                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8503                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8504                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8505                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8506                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8507         };
8508
8509     /* some different registers map in x722*/
8510         static const struct inset_map inset_map_diff_x722[] = {
8511                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8512                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8513                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8514                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8515         };
8516
8517         static const struct inset_map inset_map_diff_not_x722[] = {
8518                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8519                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8520                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8521                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8522         };
8523
8524         if (input == 0)
8525                 return val;
8526
8527         /* Translate input set to register aware inset */
8528         if (type == I40E_MAC_X722) {
8529                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8530                         if (input & inset_map_diff_x722[i].inset)
8531                                 val |= inset_map_diff_x722[i].inset_reg;
8532                 }
8533         } else {
8534                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8535                         if (input & inset_map_diff_not_x722[i].inset)
8536                                 val |= inset_map_diff_not_x722[i].inset_reg;
8537                 }
8538         }
8539
8540         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8541                 if (input & inset_map_common[i].inset)
8542                         val |= inset_map_common[i].inset_reg;
8543         }
8544
8545         return val;
8546 }
8547
8548 int
8549 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8550 {
8551         uint8_t i, idx = 0;
8552         uint64_t inset_need_mask = inset;
8553
8554         static const struct {
8555                 uint64_t inset;
8556                 uint32_t mask;
8557         } inset_mask_map[] = {
8558                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8559                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8560                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8561                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8562                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8563                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8564                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8565                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8566         };
8567
8568         if (!inset || !mask || !nb_elem)
8569                 return 0;
8570
8571         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8572                 /* Clear the inset bit, if no MASK is required,
8573                  * for example proto + ttl
8574                  */
8575                 if ((inset & inset_mask_map[i].inset) ==
8576                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8577                         inset_need_mask &= ~inset_mask_map[i].inset;
8578                 if (!inset_need_mask)
8579                         return 0;
8580         }
8581         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8582                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8583                     inset_mask_map[i].inset) {
8584                         if (idx >= nb_elem) {
8585                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8586                                 return -EINVAL;
8587                         }
8588                         mask[idx] = inset_mask_map[i].mask;
8589                         idx++;
8590                 }
8591         }
8592
8593         return idx;
8594 }
8595
8596 void
8597 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8598 {
8599         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8600
8601         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8602         if (reg != val)
8603                 i40e_write_rx_ctl(hw, addr, val);
8604         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8605                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8606 }
8607
8608 static void
8609 i40e_filter_input_set_init(struct i40e_pf *pf)
8610 {
8611         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8612         enum i40e_filter_pctype pctype;
8613         uint64_t input_set, inset_reg;
8614         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8615         int num, i;
8616
8617         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8618              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8619                 if (hw->mac.type == I40E_MAC_X722) {
8620                         if (!I40E_VALID_PCTYPE_X722(pctype))
8621                                 continue;
8622                 } else {
8623                         if (!I40E_VALID_PCTYPE(pctype))
8624                                 continue;
8625                 }
8626
8627                 input_set = i40e_get_default_input_set(pctype);
8628
8629                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8630                                                    I40E_INSET_MASK_NUM_REG);
8631                 if (num < 0)
8632                         return;
8633                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8634                                         input_set);
8635
8636                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8637                                       (uint32_t)(inset_reg & UINT32_MAX));
8638                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8639                                      (uint32_t)((inset_reg >>
8640                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8641                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8642                                       (uint32_t)(inset_reg & UINT32_MAX));
8643                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8644                                      (uint32_t)((inset_reg >>
8645                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8646
8647                 for (i = 0; i < num; i++) {
8648                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8649                                              mask_reg[i]);
8650                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8651                                              mask_reg[i]);
8652                 }
8653                 /*clear unused mask registers of the pctype */
8654                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8655                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8656                                              0);
8657                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8658                                              0);
8659                 }
8660                 I40E_WRITE_FLUSH(hw);
8661
8662                 /* store the default input set */
8663                 pf->hash_input_set[pctype] = input_set;
8664                 pf->fdir.input_set[pctype] = input_set;
8665         }
8666 }
8667
8668 int
8669 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8670                          struct rte_eth_input_set_conf *conf)
8671 {
8672         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8673         enum i40e_filter_pctype pctype;
8674         uint64_t input_set, inset_reg = 0;
8675         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8676         int ret, i, num;
8677
8678         if (!conf) {
8679                 PMD_DRV_LOG(ERR, "Invalid pointer");
8680                 return -EFAULT;
8681         }
8682         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8683             conf->op != RTE_ETH_INPUT_SET_ADD) {
8684                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8685                 return -EINVAL;
8686         }
8687
8688         if (!I40E_VALID_FLOW(conf->flow_type)) {
8689                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8690                 return -EINVAL;
8691         }
8692
8693         if (hw->mac.type == I40E_MAC_X722) {
8694                 /* get translated pctype value in fd pctype register */
8695                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8696                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8697                         conf->flow_type)));
8698         } else
8699                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8700
8701         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8702                                    conf->inset_size);
8703         if (ret) {
8704                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8705                 return -EINVAL;
8706         }
8707         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8708                                     input_set) != 0) {
8709                 PMD_DRV_LOG(ERR, "Invalid input set");
8710                 return -EINVAL;
8711         }
8712         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8713                 /* get inset value in register */
8714                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8715                 inset_reg <<= I40E_32_BIT_WIDTH;
8716                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8717                 input_set |= pf->hash_input_set[pctype];
8718         }
8719         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8720                                            I40E_INSET_MASK_NUM_REG);
8721         if (num < 0)
8722                 return -EINVAL;
8723
8724         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8725
8726         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8727                               (uint32_t)(inset_reg & UINT32_MAX));
8728         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8729                              (uint32_t)((inset_reg >>
8730                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8731
8732         for (i = 0; i < num; i++)
8733                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8734                                      mask_reg[i]);
8735         /*clear unused mask registers of the pctype */
8736         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8737                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8738                                      0);
8739         I40E_WRITE_FLUSH(hw);
8740
8741         pf->hash_input_set[pctype] = input_set;
8742         return 0;
8743 }
8744
8745 int
8746 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8747                          struct rte_eth_input_set_conf *conf)
8748 {
8749         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8750         enum i40e_filter_pctype pctype;
8751         uint64_t input_set, inset_reg = 0;
8752         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8753         int ret, i, num;
8754
8755         if (!hw || !conf) {
8756                 PMD_DRV_LOG(ERR, "Invalid pointer");
8757                 return -EFAULT;
8758         }
8759         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8760             conf->op != RTE_ETH_INPUT_SET_ADD) {
8761                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8762                 return -EINVAL;
8763         }
8764
8765         if (!I40E_VALID_FLOW(conf->flow_type)) {
8766                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8767                 return -EINVAL;
8768         }
8769
8770         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8771
8772         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8773                                    conf->inset_size);
8774         if (ret) {
8775                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8776                 return -EINVAL;
8777         }
8778         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8779                                     input_set) != 0) {
8780                 PMD_DRV_LOG(ERR, "Invalid input set");
8781                 return -EINVAL;
8782         }
8783
8784         /* get inset value in register */
8785         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8786         inset_reg <<= I40E_32_BIT_WIDTH;
8787         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8788
8789         /* Can not change the inset reg for flex payload for fdir,
8790          * it is done by writing I40E_PRTQF_FD_FLXINSET
8791          * in i40e_set_flex_mask_on_pctype.
8792          */
8793         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8794                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8795         else
8796                 input_set |= pf->fdir.input_set[pctype];
8797         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8798                                            I40E_INSET_MASK_NUM_REG);
8799         if (num < 0)
8800                 return -EINVAL;
8801
8802         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8803
8804         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8805                               (uint32_t)(inset_reg & UINT32_MAX));
8806         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8807                              (uint32_t)((inset_reg >>
8808                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8809
8810         for (i = 0; i < num; i++)
8811                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8812                                      mask_reg[i]);
8813         /*clear unused mask registers of the pctype */
8814         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8815                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8816                                      0);
8817         I40E_WRITE_FLUSH(hw);
8818
8819         pf->fdir.input_set[pctype] = input_set;
8820         return 0;
8821 }
8822
8823 static int
8824 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8825 {
8826         int ret = 0;
8827
8828         if (!hw || !info) {
8829                 PMD_DRV_LOG(ERR, "Invalid pointer");
8830                 return -EFAULT;
8831         }
8832
8833         switch (info->info_type) {
8834         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8835                 i40e_get_symmetric_hash_enable_per_port(hw,
8836                                         &(info->info.enable));
8837                 break;
8838         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8839                 ret = i40e_get_hash_filter_global_config(hw,
8840                                 &(info->info.global_conf));
8841                 break;
8842         default:
8843                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8844                                                         info->info_type);
8845                 ret = -EINVAL;
8846                 break;
8847         }
8848
8849         return ret;
8850 }
8851
8852 static int
8853 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8854 {
8855         int ret = 0;
8856
8857         if (!hw || !info) {
8858                 PMD_DRV_LOG(ERR, "Invalid pointer");
8859                 return -EFAULT;
8860         }
8861
8862         switch (info->info_type) {
8863         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8864                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8865                 break;
8866         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8867                 ret = i40e_set_hash_filter_global_config(hw,
8868                                 &(info->info.global_conf));
8869                 break;
8870         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8871                 ret = i40e_hash_filter_inset_select(hw,
8872                                                &(info->info.input_set_conf));
8873                 break;
8874
8875         default:
8876                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8877                                                         info->info_type);
8878                 ret = -EINVAL;
8879                 break;
8880         }
8881
8882         return ret;
8883 }
8884
8885 /* Operations for hash function */
8886 static int
8887 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8888                       enum rte_filter_op filter_op,
8889                       void *arg)
8890 {
8891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8892         int ret = 0;
8893
8894         switch (filter_op) {
8895         case RTE_ETH_FILTER_NOP:
8896                 break;
8897         case RTE_ETH_FILTER_GET:
8898                 ret = i40e_hash_filter_get(hw,
8899                         (struct rte_eth_hash_filter_info *)arg);
8900                 break;
8901         case RTE_ETH_FILTER_SET:
8902                 ret = i40e_hash_filter_set(hw,
8903                         (struct rte_eth_hash_filter_info *)arg);
8904                 break;
8905         default:
8906                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8907                                                                 filter_op);
8908                 ret = -ENOTSUP;
8909                 break;
8910         }
8911
8912         return ret;
8913 }
8914
8915 /* Convert ethertype filter structure */
8916 static int
8917 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8918                               struct i40e_ethertype_filter *filter)
8919 {
8920         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8921         filter->input.ether_type = input->ether_type;
8922         filter->flags = input->flags;
8923         filter->queue = input->queue;
8924
8925         return 0;
8926 }
8927
8928 /* Check if there exists the ehtertype filter */
8929 struct i40e_ethertype_filter *
8930 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8931                                 const struct i40e_ethertype_filter_input *input)
8932 {
8933         int ret;
8934
8935         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8936         if (ret < 0)
8937                 return NULL;
8938
8939         return ethertype_rule->hash_map[ret];
8940 }
8941
8942 /* Add ethertype filter in SW list */
8943 static int
8944 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8945                                 struct i40e_ethertype_filter *filter)
8946 {
8947         struct i40e_ethertype_rule *rule = &pf->ethertype;
8948         int ret;
8949
8950         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8951         if (ret < 0) {
8952                 PMD_DRV_LOG(ERR,
8953                             "Failed to insert ethertype filter"
8954                             " to hash table %d!",
8955                             ret);
8956                 return ret;
8957         }
8958         rule->hash_map[ret] = filter;
8959
8960         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8961
8962         return 0;
8963 }
8964
8965 /* Delete ethertype filter in SW list */
8966 int
8967 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8968                              struct i40e_ethertype_filter_input *input)
8969 {
8970         struct i40e_ethertype_rule *rule = &pf->ethertype;
8971         struct i40e_ethertype_filter *filter;
8972         int ret;
8973
8974         ret = rte_hash_del_key(rule->hash_table, input);
8975         if (ret < 0) {
8976                 PMD_DRV_LOG(ERR,
8977                             "Failed to delete ethertype filter"
8978                             " to hash table %d!",
8979                             ret);
8980                 return ret;
8981         }
8982         filter = rule->hash_map[ret];
8983         rule->hash_map[ret] = NULL;
8984
8985         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8986         rte_free(filter);
8987
8988         return 0;
8989 }
8990
8991 /*
8992  * Configure ethertype filter, which can director packet by filtering
8993  * with mac address and ether_type or only ether_type
8994  */
8995 int
8996 i40e_ethertype_filter_set(struct i40e_pf *pf,
8997                         struct rte_eth_ethertype_filter *filter,
8998                         bool add)
8999 {
9000         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9001         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9002         struct i40e_ethertype_filter *ethertype_filter, *node;
9003         struct i40e_ethertype_filter check_filter;
9004         struct i40e_control_filter_stats stats;
9005         uint16_t flags = 0;
9006         int ret;
9007
9008         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9009                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9010                 return -EINVAL;
9011         }
9012         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9013                 filter->ether_type == ETHER_TYPE_IPv6) {
9014                 PMD_DRV_LOG(ERR,
9015                         "unsupported ether_type(0x%04x) in control packet filter.",
9016                         filter->ether_type);
9017                 return -EINVAL;
9018         }
9019         if (filter->ether_type == ETHER_TYPE_VLAN)
9020                 PMD_DRV_LOG(WARNING,
9021                         "filter vlan ether_type in first tag is not supported.");
9022
9023         /* Check if there is the filter in SW list */
9024         memset(&check_filter, 0, sizeof(check_filter));
9025         i40e_ethertype_filter_convert(filter, &check_filter);
9026         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9027                                                &check_filter.input);
9028         if (add && node) {
9029                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9030                 return -EINVAL;
9031         }
9032
9033         if (!add && !node) {
9034                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9035                 return -EINVAL;
9036         }
9037
9038         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9039                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9040         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9041                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9042         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9043
9044         memset(&stats, 0, sizeof(stats));
9045         ret = i40e_aq_add_rem_control_packet_filter(hw,
9046                         filter->mac_addr.addr_bytes,
9047                         filter->ether_type, flags,
9048                         pf->main_vsi->seid,
9049                         filter->queue, add, &stats, NULL);
9050
9051         PMD_DRV_LOG(INFO,
9052                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9053                 ret, stats.mac_etype_used, stats.etype_used,
9054                 stats.mac_etype_free, stats.etype_free);
9055         if (ret < 0)
9056                 return -ENOSYS;
9057
9058         /* Add or delete a filter in SW list */
9059         if (add) {
9060                 ethertype_filter = rte_zmalloc("ethertype_filter",
9061                                        sizeof(*ethertype_filter), 0);
9062                 rte_memcpy(ethertype_filter, &check_filter,
9063                            sizeof(check_filter));
9064                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9065         } else {
9066                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9067         }
9068
9069         return ret;
9070 }
9071
9072 /*
9073  * Handle operations for ethertype filter.
9074  */
9075 static int
9076 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9077                                 enum rte_filter_op filter_op,
9078                                 void *arg)
9079 {
9080         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9081         int ret = 0;
9082
9083         if (filter_op == RTE_ETH_FILTER_NOP)
9084                 return ret;
9085
9086         if (arg == NULL) {
9087                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9088                             filter_op);
9089                 return -EINVAL;
9090         }
9091
9092         switch (filter_op) {
9093         case RTE_ETH_FILTER_ADD:
9094                 ret = i40e_ethertype_filter_set(pf,
9095                         (struct rte_eth_ethertype_filter *)arg,
9096                         TRUE);
9097                 break;
9098         case RTE_ETH_FILTER_DELETE:
9099                 ret = i40e_ethertype_filter_set(pf,
9100                         (struct rte_eth_ethertype_filter *)arg,
9101                         FALSE);
9102                 break;
9103         default:
9104                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9105                 ret = -ENOSYS;
9106                 break;
9107         }
9108         return ret;
9109 }
9110
9111 static int
9112 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9113                      enum rte_filter_type filter_type,
9114                      enum rte_filter_op filter_op,
9115                      void *arg)
9116 {
9117         int ret = 0;
9118
9119         if (dev == NULL)
9120                 return -EINVAL;
9121
9122         switch (filter_type) {
9123         case RTE_ETH_FILTER_NONE:
9124                 /* For global configuration */
9125                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9126                 break;
9127         case RTE_ETH_FILTER_HASH:
9128                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9129                 break;
9130         case RTE_ETH_FILTER_MACVLAN:
9131                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9132                 break;
9133         case RTE_ETH_FILTER_ETHERTYPE:
9134                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9135                 break;
9136         case RTE_ETH_FILTER_TUNNEL:
9137                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9138                 break;
9139         case RTE_ETH_FILTER_FDIR:
9140                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9141                 break;
9142         case RTE_ETH_FILTER_GENERIC:
9143                 if (filter_op != RTE_ETH_FILTER_GET)
9144                         return -EINVAL;
9145                 *(const void **)arg = &i40e_flow_ops;
9146                 break;
9147         default:
9148                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9149                                                         filter_type);
9150                 ret = -EINVAL;
9151                 break;
9152         }
9153
9154         return ret;
9155 }
9156
9157 /*
9158  * Check and enable Extended Tag.
9159  * Enabling Extended Tag is important for 40G performance.
9160  */
9161 static void
9162 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9163 {
9164         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9165         uint32_t buf = 0;
9166         int ret;
9167
9168         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9169                                       PCI_DEV_CAP_REG);
9170         if (ret < 0) {
9171                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9172                             PCI_DEV_CAP_REG);
9173                 return;
9174         }
9175         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9176                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9177                 return;
9178         }
9179
9180         buf = 0;
9181         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9182                                       PCI_DEV_CTRL_REG);
9183         if (ret < 0) {
9184                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9185                             PCI_DEV_CTRL_REG);
9186                 return;
9187         }
9188         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9189                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9190                 return;
9191         }
9192         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9193         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9194                                        PCI_DEV_CTRL_REG);
9195         if (ret < 0) {
9196                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9197                             PCI_DEV_CTRL_REG);
9198                 return;
9199         }
9200 }
9201
9202 /*
9203  * As some registers wouldn't be reset unless a global hardware reset,
9204  * hardware initialization is needed to put those registers into an
9205  * expected initial state.
9206  */
9207 static void
9208 i40e_hw_init(struct rte_eth_dev *dev)
9209 {
9210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9211
9212         i40e_enable_extended_tag(dev);
9213
9214         /* clear the PF Queue Filter control register */
9215         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9216
9217         /* Disable symmetric hash per port */
9218         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9219 }
9220
9221 enum i40e_filter_pctype
9222 i40e_flowtype_to_pctype(uint16_t flow_type)
9223 {
9224         static const enum i40e_filter_pctype pctype_table[] = {
9225                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9226                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9227                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9228                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9229                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9230                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9231                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9232                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9233                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9234                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9235                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9236                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9237                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9238                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9239                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9240                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9241                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9242                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9243                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9244         };
9245
9246         return pctype_table[flow_type];
9247 }
9248
9249 uint16_t
9250 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9251 {
9252         static const uint16_t flowtype_table[] = {
9253                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9254                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9255                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9256                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9257                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9258                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9259                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9260                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9261                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9262                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9263                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9264                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9265                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9266                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9267                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9268                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9269                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9270                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9271                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9272                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9273                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9274                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9275                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9276                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9277                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9278                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9279                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9280                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9281                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9282                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9283                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9284         };
9285
9286         return flowtype_table[pctype];
9287 }
9288
9289 /*
9290  * On X710, performance number is far from the expectation on recent firmware
9291  * versions; on XL710, performance number is also far from the expectation on
9292  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9293  * mode is enabled and port MAC address is equal to the packet destination MAC
9294  * address. The fix for this issue may not be integrated in the following
9295  * firmware version. So the workaround in software driver is needed. It needs
9296  * to modify the initial values of 3 internal only registers for both X710 and
9297  * XL710. Note that the values for X710 or XL710 could be different, and the
9298  * workaround can be removed when it is fixed in firmware in the future.
9299  */
9300
9301 /* For both X710 and XL710 */
9302 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9303 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9304 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9305
9306 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9307 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9308
9309 /* For X722 */
9310 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9311 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9312
9313 /* For X710 */
9314 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9315 /* For XL710 */
9316 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9317 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9318
9319 static int
9320 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9321 {
9322         enum i40e_status_code status;
9323         struct i40e_aq_get_phy_abilities_resp phy_ab;
9324         int ret = -ENOTSUP;
9325         int retries = 0;
9326
9327         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9328                                               NULL);
9329
9330         while (status) {
9331                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9332                         status);
9333                 retries++;
9334                 rte_delay_us(100000);
9335                 if  (retries < 5)
9336                         status = i40e_aq_get_phy_capabilities(hw, false,
9337                                         true, &phy_ab, NULL);
9338                 else
9339                         return ret;
9340         }
9341         return 0;
9342 }
9343
9344 static void
9345 i40e_configure_registers(struct i40e_hw *hw)
9346 {
9347         static struct {
9348                 uint32_t addr;
9349                 uint64_t val;
9350         } reg_table[] = {
9351                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9352                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9353                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9354         };
9355         uint64_t reg;
9356         uint32_t i;
9357         int ret;
9358
9359         for (i = 0; i < RTE_DIM(reg_table); i++) {
9360                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9361                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9362                                 reg_table[i].val =
9363                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9364                         else /* For X710/XL710/XXV710 */
9365                                 if (hw->aq.fw_maj_ver < 6)
9366                                         reg_table[i].val =
9367                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9368                                 else
9369                                         reg_table[i].val =
9370                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9371                 }
9372
9373                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9374                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9375                                 reg_table[i].val =
9376                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9377                         else /* For X710/XL710/XXV710 */
9378                                 reg_table[i].val =
9379                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9380                 }
9381
9382                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9383                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9384                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9385                                 reg_table[i].val =
9386                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9387                         else /* For X710 */
9388                                 reg_table[i].val =
9389                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9390                 }
9391
9392                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9393                                                         &reg, NULL);
9394                 if (ret < 0) {
9395                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9396                                                         reg_table[i].addr);
9397                         break;
9398                 }
9399                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9400                                                 reg_table[i].addr, reg);
9401                 if (reg == reg_table[i].val)
9402                         continue;
9403
9404                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9405                                                 reg_table[i].val, NULL);
9406                 if (ret < 0) {
9407                         PMD_DRV_LOG(ERR,
9408                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9409                                 reg_table[i].val, reg_table[i].addr);
9410                         break;
9411                 }
9412                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9413                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9414         }
9415 }
9416
9417 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9418 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9419 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9420 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9421 static int
9422 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9423 {
9424         uint32_t reg;
9425         int ret;
9426
9427         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9428                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9429                 return -EINVAL;
9430         }
9431
9432         /* Configure for double VLAN RX stripping */
9433         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9434         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9435                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9436                 ret = i40e_aq_debug_write_register(hw,
9437                                                    I40E_VSI_TSR(vsi->vsi_id),
9438                                                    reg, NULL);
9439                 if (ret < 0) {
9440                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9441                                     vsi->vsi_id);
9442                         return I40E_ERR_CONFIG;
9443                 }
9444         }
9445
9446         /* Configure for double VLAN TX insertion */
9447         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9448         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9449                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9450                 ret = i40e_aq_debug_write_register(hw,
9451                                                    I40E_VSI_L2TAGSTXVALID(
9452                                                    vsi->vsi_id), reg, NULL);
9453                 if (ret < 0) {
9454                         PMD_DRV_LOG(ERR,
9455                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9456                                 vsi->vsi_id);
9457                         return I40E_ERR_CONFIG;
9458                 }
9459         }
9460
9461         return 0;
9462 }
9463
9464 /**
9465  * i40e_aq_add_mirror_rule
9466  * @hw: pointer to the hardware structure
9467  * @seid: VEB seid to add mirror rule to
9468  * @dst_id: destination vsi seid
9469  * @entries: Buffer which contains the entities to be mirrored
9470  * @count: number of entities contained in the buffer
9471  * @rule_id:the rule_id of the rule to be added
9472  *
9473  * Add a mirror rule for a given veb.
9474  *
9475  **/
9476 static enum i40e_status_code
9477 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9478                         uint16_t seid, uint16_t dst_id,
9479                         uint16_t rule_type, uint16_t *entries,
9480                         uint16_t count, uint16_t *rule_id)
9481 {
9482         struct i40e_aq_desc desc;
9483         struct i40e_aqc_add_delete_mirror_rule cmd;
9484         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9485                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9486                 &desc.params.raw;
9487         uint16_t buff_len;
9488         enum i40e_status_code status;
9489
9490         i40e_fill_default_direct_cmd_desc(&desc,
9491                                           i40e_aqc_opc_add_mirror_rule);
9492         memset(&cmd, 0, sizeof(cmd));
9493
9494         buff_len = sizeof(uint16_t) * count;
9495         desc.datalen = rte_cpu_to_le_16(buff_len);
9496         if (buff_len > 0)
9497                 desc.flags |= rte_cpu_to_le_16(
9498                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9499         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9500                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9501         cmd.num_entries = rte_cpu_to_le_16(count);
9502         cmd.seid = rte_cpu_to_le_16(seid);
9503         cmd.destination = rte_cpu_to_le_16(dst_id);
9504
9505         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9506         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9507         PMD_DRV_LOG(INFO,
9508                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9509                 hw->aq.asq_last_status, resp->rule_id,
9510                 resp->mirror_rules_used, resp->mirror_rules_free);
9511         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9512
9513         return status;
9514 }
9515
9516 /**
9517  * i40e_aq_del_mirror_rule
9518  * @hw: pointer to the hardware structure
9519  * @seid: VEB seid to add mirror rule to
9520  * @entries: Buffer which contains the entities to be mirrored
9521  * @count: number of entities contained in the buffer
9522  * @rule_id:the rule_id of the rule to be delete
9523  *
9524  * Delete a mirror rule for a given veb.
9525  *
9526  **/
9527 static enum i40e_status_code
9528 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9529                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9530                 uint16_t count, uint16_t rule_id)
9531 {
9532         struct i40e_aq_desc desc;
9533         struct i40e_aqc_add_delete_mirror_rule cmd;
9534         uint16_t buff_len = 0;
9535         enum i40e_status_code status;
9536         void *buff = NULL;
9537
9538         i40e_fill_default_direct_cmd_desc(&desc,
9539                                           i40e_aqc_opc_delete_mirror_rule);
9540         memset(&cmd, 0, sizeof(cmd));
9541         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9542                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9543                                                           I40E_AQ_FLAG_RD));
9544                 cmd.num_entries = count;
9545                 buff_len = sizeof(uint16_t) * count;
9546                 desc.datalen = rte_cpu_to_le_16(buff_len);
9547                 buff = (void *)entries;
9548         } else
9549                 /* rule id is filled in destination field for deleting mirror rule */
9550                 cmd.destination = rte_cpu_to_le_16(rule_id);
9551
9552         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9553                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9554         cmd.seid = rte_cpu_to_le_16(seid);
9555
9556         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9557         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9558
9559         return status;
9560 }
9561
9562 /**
9563  * i40e_mirror_rule_set
9564  * @dev: pointer to the hardware structure
9565  * @mirror_conf: mirror rule info
9566  * @sw_id: mirror rule's sw_id
9567  * @on: enable/disable
9568  *
9569  * set a mirror rule.
9570  *
9571  **/
9572 static int
9573 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9574                         struct rte_eth_mirror_conf *mirror_conf,
9575                         uint8_t sw_id, uint8_t on)
9576 {
9577         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9578         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9579         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9580         struct i40e_mirror_rule *parent = NULL;
9581         uint16_t seid, dst_seid, rule_id;
9582         uint16_t i, j = 0;
9583         int ret;
9584
9585         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9586
9587         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9588                 PMD_DRV_LOG(ERR,
9589                         "mirror rule can not be configured without veb or vfs.");
9590                 return -ENOSYS;
9591         }
9592         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9593                 PMD_DRV_LOG(ERR, "mirror table is full.");
9594                 return -ENOSPC;
9595         }
9596         if (mirror_conf->dst_pool > pf->vf_num) {
9597                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9598                                  mirror_conf->dst_pool);
9599                 return -EINVAL;
9600         }
9601
9602         seid = pf->main_vsi->veb->seid;
9603
9604         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9605                 if (sw_id <= it->index) {
9606                         mirr_rule = it;
9607                         break;
9608                 }
9609                 parent = it;
9610         }
9611         if (mirr_rule && sw_id == mirr_rule->index) {
9612                 if (on) {
9613                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9614                         return -EEXIST;
9615                 } else {
9616                         ret = i40e_aq_del_mirror_rule(hw, seid,
9617                                         mirr_rule->rule_type,
9618                                         mirr_rule->entries,
9619                                         mirr_rule->num_entries, mirr_rule->id);
9620                         if (ret < 0) {
9621                                 PMD_DRV_LOG(ERR,
9622                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9623                                         ret, hw->aq.asq_last_status);
9624                                 return -ENOSYS;
9625                         }
9626                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9627                         rte_free(mirr_rule);
9628                         pf->nb_mirror_rule--;
9629                         return 0;
9630                 }
9631         } else if (!on) {
9632                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9633                 return -ENOENT;
9634         }
9635
9636         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9637                                 sizeof(struct i40e_mirror_rule) , 0);
9638         if (!mirr_rule) {
9639                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9640                 return I40E_ERR_NO_MEMORY;
9641         }
9642         switch (mirror_conf->rule_type) {
9643         case ETH_MIRROR_VLAN:
9644                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9645                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9646                                 mirr_rule->entries[j] =
9647                                         mirror_conf->vlan.vlan_id[i];
9648                                 j++;
9649                         }
9650                 }
9651                 if (j == 0) {
9652                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9653                         rte_free(mirr_rule);
9654                         return -EINVAL;
9655                 }
9656                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9657                 break;
9658         case ETH_MIRROR_VIRTUAL_POOL_UP:
9659         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9660                 /* check if the specified pool bit is out of range */
9661                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9662                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9663                         rte_free(mirr_rule);
9664                         return -EINVAL;
9665                 }
9666                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9667                         if (mirror_conf->pool_mask & (1ULL << i)) {
9668                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9669                                 j++;
9670                         }
9671                 }
9672                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9673                         /* add pf vsi to entries */
9674                         mirr_rule->entries[j] = pf->main_vsi_seid;
9675                         j++;
9676                 }
9677                 if (j == 0) {
9678                         PMD_DRV_LOG(ERR, "pool is not specified.");
9679                         rte_free(mirr_rule);
9680                         return -EINVAL;
9681                 }
9682                 /* egress and ingress in aq commands means from switch but not port */
9683                 mirr_rule->rule_type =
9684                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9685                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9686                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9687                 break;
9688         case ETH_MIRROR_UPLINK_PORT:
9689                 /* egress and ingress in aq commands means from switch but not port*/
9690                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9691                 break;
9692         case ETH_MIRROR_DOWNLINK_PORT:
9693                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9694                 break;
9695         default:
9696                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9697                         mirror_conf->rule_type);
9698                 rte_free(mirr_rule);
9699                 return -EINVAL;
9700         }
9701
9702         /* If the dst_pool is equal to vf_num, consider it as PF */
9703         if (mirror_conf->dst_pool == pf->vf_num)
9704                 dst_seid = pf->main_vsi_seid;
9705         else
9706                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9707
9708         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9709                                       mirr_rule->rule_type, mirr_rule->entries,
9710                                       j, &rule_id);
9711         if (ret < 0) {
9712                 PMD_DRV_LOG(ERR,
9713                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9714                         ret, hw->aq.asq_last_status);
9715                 rte_free(mirr_rule);
9716                 return -ENOSYS;
9717         }
9718
9719         mirr_rule->index = sw_id;
9720         mirr_rule->num_entries = j;
9721         mirr_rule->id = rule_id;
9722         mirr_rule->dst_vsi_seid = dst_seid;
9723
9724         if (parent)
9725                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9726         else
9727                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9728
9729         pf->nb_mirror_rule++;
9730         return 0;
9731 }
9732
9733 /**
9734  * i40e_mirror_rule_reset
9735  * @dev: pointer to the device
9736  * @sw_id: mirror rule's sw_id
9737  *
9738  * reset a mirror rule.
9739  *
9740  **/
9741 static int
9742 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9743 {
9744         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9746         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9747         uint16_t seid;
9748         int ret;
9749
9750         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9751
9752         seid = pf->main_vsi->veb->seid;
9753
9754         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9755                 if (sw_id == it->index) {
9756                         mirr_rule = it;
9757                         break;
9758                 }
9759         }
9760         if (mirr_rule) {
9761                 ret = i40e_aq_del_mirror_rule(hw, seid,
9762                                 mirr_rule->rule_type,
9763                                 mirr_rule->entries,
9764                                 mirr_rule->num_entries, mirr_rule->id);
9765                 if (ret < 0) {
9766                         PMD_DRV_LOG(ERR,
9767                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9768                                 ret, hw->aq.asq_last_status);
9769                         return -ENOSYS;
9770                 }
9771                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9772                 rte_free(mirr_rule);
9773                 pf->nb_mirror_rule--;
9774         } else {
9775                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9776                 return -ENOENT;
9777         }
9778         return 0;
9779 }
9780
9781 static uint64_t
9782 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9783 {
9784         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9785         uint64_t systim_cycles;
9786
9787         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9788         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9789                         << 32;
9790
9791         return systim_cycles;
9792 }
9793
9794 static uint64_t
9795 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9796 {
9797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9798         uint64_t rx_tstamp;
9799
9800         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9801         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9802                         << 32;
9803
9804         return rx_tstamp;
9805 }
9806
9807 static uint64_t
9808 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9809 {
9810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9811         uint64_t tx_tstamp;
9812
9813         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9814         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9815                         << 32;
9816
9817         return tx_tstamp;
9818 }
9819
9820 static void
9821 i40e_start_timecounters(struct rte_eth_dev *dev)
9822 {
9823         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9824         struct i40e_adapter *adapter =
9825                         (struct i40e_adapter *)dev->data->dev_private;
9826         struct rte_eth_link link;
9827         uint32_t tsync_inc_l;
9828         uint32_t tsync_inc_h;
9829
9830         /* Get current link speed. */
9831         memset(&link, 0, sizeof(link));
9832         i40e_dev_link_update(dev, 1);
9833         rte_i40e_dev_atomic_read_link_status(dev, &link);
9834
9835         switch (link.link_speed) {
9836         case ETH_SPEED_NUM_40G:
9837                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9838                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9839                 break;
9840         case ETH_SPEED_NUM_10G:
9841                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9842                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9843                 break;
9844         case ETH_SPEED_NUM_1G:
9845                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9846                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9847                 break;
9848         default:
9849                 tsync_inc_l = 0x0;
9850                 tsync_inc_h = 0x0;
9851         }
9852
9853         /* Set the timesync increment value. */
9854         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9855         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9856
9857         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9858         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9859         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9860
9861         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9862         adapter->systime_tc.cc_shift = 0;
9863         adapter->systime_tc.nsec_mask = 0;
9864
9865         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9866         adapter->rx_tstamp_tc.cc_shift = 0;
9867         adapter->rx_tstamp_tc.nsec_mask = 0;
9868
9869         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9870         adapter->tx_tstamp_tc.cc_shift = 0;
9871         adapter->tx_tstamp_tc.nsec_mask = 0;
9872 }
9873
9874 static int
9875 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9876 {
9877         struct i40e_adapter *adapter =
9878                         (struct i40e_adapter *)dev->data->dev_private;
9879
9880         adapter->systime_tc.nsec += delta;
9881         adapter->rx_tstamp_tc.nsec += delta;
9882         adapter->tx_tstamp_tc.nsec += delta;
9883
9884         return 0;
9885 }
9886
9887 static int
9888 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9889 {
9890         uint64_t ns;
9891         struct i40e_adapter *adapter =
9892                         (struct i40e_adapter *)dev->data->dev_private;
9893
9894         ns = rte_timespec_to_ns(ts);
9895
9896         /* Set the timecounters to a new value. */
9897         adapter->systime_tc.nsec = ns;
9898         adapter->rx_tstamp_tc.nsec = ns;
9899         adapter->tx_tstamp_tc.nsec = ns;
9900
9901         return 0;
9902 }
9903
9904 static int
9905 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9906 {
9907         uint64_t ns, systime_cycles;
9908         struct i40e_adapter *adapter =
9909                         (struct i40e_adapter *)dev->data->dev_private;
9910
9911         systime_cycles = i40e_read_systime_cyclecounter(dev);
9912         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9913         *ts = rte_ns_to_timespec(ns);
9914
9915         return 0;
9916 }
9917
9918 static int
9919 i40e_timesync_enable(struct rte_eth_dev *dev)
9920 {
9921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9922         uint32_t tsync_ctl_l;
9923         uint32_t tsync_ctl_h;
9924
9925         /* Stop the timesync system time. */
9926         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9927         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9928         /* Reset the timesync system time value. */
9929         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9930         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9931
9932         i40e_start_timecounters(dev);
9933
9934         /* Clear timesync registers. */
9935         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9936         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9937         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9938         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9939         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9940         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9941
9942         /* Enable timestamping of PTP packets. */
9943         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9944         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9945
9946         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9947         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9948         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9949
9950         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9951         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9952
9953         return 0;
9954 }
9955
9956 static int
9957 i40e_timesync_disable(struct rte_eth_dev *dev)
9958 {
9959         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9960         uint32_t tsync_ctl_l;
9961         uint32_t tsync_ctl_h;
9962
9963         /* Disable timestamping of transmitted PTP packets. */
9964         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9965         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9966
9967         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9968         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9969
9970         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9971         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9972
9973         /* Reset the timesync increment value. */
9974         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9975         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9976
9977         return 0;
9978 }
9979
9980 static int
9981 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9982                                 struct timespec *timestamp, uint32_t flags)
9983 {
9984         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9985         struct i40e_adapter *adapter =
9986                 (struct i40e_adapter *)dev->data->dev_private;
9987
9988         uint32_t sync_status;
9989         uint32_t index = flags & 0x03;
9990         uint64_t rx_tstamp_cycles;
9991         uint64_t ns;
9992
9993         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9994         if ((sync_status & (1 << index)) == 0)
9995                 return -EINVAL;
9996
9997         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9998         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9999         *timestamp = rte_ns_to_timespec(ns);
10000
10001         return 0;
10002 }
10003
10004 static int
10005 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10006                                 struct timespec *timestamp)
10007 {
10008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10009         struct i40e_adapter *adapter =
10010                 (struct i40e_adapter *)dev->data->dev_private;
10011
10012         uint32_t sync_status;
10013         uint64_t tx_tstamp_cycles;
10014         uint64_t ns;
10015
10016         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10017         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10018                 return -EINVAL;
10019
10020         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10021         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10022         *timestamp = rte_ns_to_timespec(ns);
10023
10024         return 0;
10025 }
10026
10027 /*
10028  * i40e_parse_dcb_configure - parse dcb configure from user
10029  * @dev: the device being configured
10030  * @dcb_cfg: pointer of the result of parse
10031  * @*tc_map: bit map of enabled traffic classes
10032  *
10033  * Returns 0 on success, negative value on failure
10034  */
10035 static int
10036 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10037                          struct i40e_dcbx_config *dcb_cfg,
10038                          uint8_t *tc_map)
10039 {
10040         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10041         uint8_t i, tc_bw, bw_lf;
10042
10043         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10044
10045         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10046         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10047                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10048                 return -EINVAL;
10049         }
10050
10051         /* assume each tc has the same bw */
10052         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10053         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10054                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10055         /* to ensure the sum of tcbw is equal to 100 */
10056         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10057         for (i = 0; i < bw_lf; i++)
10058                 dcb_cfg->etscfg.tcbwtable[i]++;
10059
10060         /* assume each tc has the same Transmission Selection Algorithm */
10061         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10062                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10063
10064         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10065                 dcb_cfg->etscfg.prioritytable[i] =
10066                                 dcb_rx_conf->dcb_tc[i];
10067
10068         /* FW needs one App to configure HW */
10069         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10070         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10071         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10072         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10073
10074         if (dcb_rx_conf->nb_tcs == 0)
10075                 *tc_map = 1; /* tc0 only */
10076         else
10077                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10078
10079         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10080                 dcb_cfg->pfc.willing = 0;
10081                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10082                 dcb_cfg->pfc.pfcenable = *tc_map;
10083         }
10084         return 0;
10085 }
10086
10087
10088 static enum i40e_status_code
10089 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10090                               struct i40e_aqc_vsi_properties_data *info,
10091                               uint8_t enabled_tcmap)
10092 {
10093         enum i40e_status_code ret;
10094         int i, total_tc = 0;
10095         uint16_t qpnum_per_tc, bsf, qp_idx;
10096         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10097         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10098         uint16_t used_queues;
10099
10100         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10101         if (ret != I40E_SUCCESS)
10102                 return ret;
10103
10104         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10105                 if (enabled_tcmap & (1 << i))
10106                         total_tc++;
10107         }
10108         if (total_tc == 0)
10109                 total_tc = 1;
10110         vsi->enabled_tc = enabled_tcmap;
10111
10112         /* different VSI has different queues assigned */
10113         if (vsi->type == I40E_VSI_MAIN)
10114                 used_queues = dev_data->nb_rx_queues -
10115                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10116         else if (vsi->type == I40E_VSI_VMDQ2)
10117                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10118         else {
10119                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10120                 return I40E_ERR_NO_AVAILABLE_VSI;
10121         }
10122
10123         qpnum_per_tc = used_queues / total_tc;
10124         /* Number of queues per enabled TC */
10125         if (qpnum_per_tc == 0) {
10126                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10127                 return I40E_ERR_INVALID_QP_ID;
10128         }
10129         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10130                                 I40E_MAX_Q_PER_TC);
10131         bsf = rte_bsf32(qpnum_per_tc);
10132
10133         /**
10134          * Configure TC and queue mapping parameters, for enabled TC,
10135          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10136          * default queue will serve it.
10137          */
10138         qp_idx = 0;
10139         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10140                 if (vsi->enabled_tc & (1 << i)) {
10141                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10142                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10143                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10144                         qp_idx += qpnum_per_tc;
10145                 } else
10146                         info->tc_mapping[i] = 0;
10147         }
10148
10149         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10150         if (vsi->type == I40E_VSI_SRIOV) {
10151                 info->mapping_flags |=
10152                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10153                 for (i = 0; i < vsi->nb_qps; i++)
10154                         info->queue_mapping[i] =
10155                                 rte_cpu_to_le_16(vsi->base_queue + i);
10156         } else {
10157                 info->mapping_flags |=
10158                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10159                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10160         }
10161         info->valid_sections |=
10162                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10163
10164         return I40E_SUCCESS;
10165 }
10166
10167 /*
10168  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10169  * @veb: VEB to be configured
10170  * @tc_map: enabled TC bitmap
10171  *
10172  * Returns 0 on success, negative value on failure
10173  */
10174 static enum i40e_status_code
10175 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10176 {
10177         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10178         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10179         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10180         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10181         enum i40e_status_code ret = I40E_SUCCESS;
10182         int i;
10183         uint32_t bw_max;
10184
10185         /* Check if enabled_tc is same as existing or new TCs */
10186         if (veb->enabled_tc == tc_map)
10187                 return ret;
10188
10189         /* configure tc bandwidth */
10190         memset(&veb_bw, 0, sizeof(veb_bw));
10191         veb_bw.tc_valid_bits = tc_map;
10192         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10193         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10194                 if (tc_map & BIT_ULL(i))
10195                         veb_bw.tc_bw_share_credits[i] = 1;
10196         }
10197         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10198                                                    &veb_bw, NULL);
10199         if (ret) {
10200                 PMD_INIT_LOG(ERR,
10201                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10202                         hw->aq.asq_last_status);
10203                 return ret;
10204         }
10205
10206         memset(&ets_query, 0, sizeof(ets_query));
10207         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10208                                                    &ets_query, NULL);
10209         if (ret != I40E_SUCCESS) {
10210                 PMD_DRV_LOG(ERR,
10211                         "Failed to get switch_comp ETS configuration %u",
10212                         hw->aq.asq_last_status);
10213                 return ret;
10214         }
10215         memset(&bw_query, 0, sizeof(bw_query));
10216         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10217                                                   &bw_query, NULL);
10218         if (ret != I40E_SUCCESS) {
10219                 PMD_DRV_LOG(ERR,
10220                         "Failed to get switch_comp bandwidth configuration %u",
10221                         hw->aq.asq_last_status);
10222                 return ret;
10223         }
10224
10225         /* store and print out BW info */
10226         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10227         veb->bw_info.bw_max = ets_query.tc_bw_max;
10228         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10229         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10230         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10231                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10232                      I40E_16_BIT_WIDTH);
10233         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10234                 veb->bw_info.bw_ets_share_credits[i] =
10235                                 bw_query.tc_bw_share_credits[i];
10236                 veb->bw_info.bw_ets_credits[i] =
10237                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10238                 /* 4 bits per TC, 4th bit is reserved */
10239                 veb->bw_info.bw_ets_max[i] =
10240                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10241                                   RTE_LEN2MASK(3, uint8_t));
10242                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10243                             veb->bw_info.bw_ets_share_credits[i]);
10244                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10245                             veb->bw_info.bw_ets_credits[i]);
10246                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10247                             veb->bw_info.bw_ets_max[i]);
10248         }
10249
10250         veb->enabled_tc = tc_map;
10251
10252         return ret;
10253 }
10254
10255
10256 /*
10257  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10258  * @vsi: VSI to be configured
10259  * @tc_map: enabled TC bitmap
10260  *
10261  * Returns 0 on success, negative value on failure
10262  */
10263 static enum i40e_status_code
10264 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10265 {
10266         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10267         struct i40e_vsi_context ctxt;
10268         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10269         enum i40e_status_code ret = I40E_SUCCESS;
10270         int i;
10271
10272         /* Check if enabled_tc is same as existing or new TCs */
10273         if (vsi->enabled_tc == tc_map)
10274                 return ret;
10275
10276         /* configure tc bandwidth */
10277         memset(&bw_data, 0, sizeof(bw_data));
10278         bw_data.tc_valid_bits = tc_map;
10279         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10280         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10281                 if (tc_map & BIT_ULL(i))
10282                         bw_data.tc_bw_credits[i] = 1;
10283         }
10284         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10285         if (ret) {
10286                 PMD_INIT_LOG(ERR,
10287                         "AQ command Config VSI BW allocation per TC failed = %d",
10288                         hw->aq.asq_last_status);
10289                 goto out;
10290         }
10291         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10292                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10293
10294         /* Update Queue Pairs Mapping for currently enabled UPs */
10295         ctxt.seid = vsi->seid;
10296         ctxt.pf_num = hw->pf_id;
10297         ctxt.vf_num = 0;
10298         ctxt.uplink_seid = vsi->uplink_seid;
10299         ctxt.info = vsi->info;
10300         i40e_get_cap(hw);
10301         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10302         if (ret)
10303                 goto out;
10304
10305         /* Update the VSI after updating the VSI queue-mapping information */
10306         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10307         if (ret) {
10308                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10309                         hw->aq.asq_last_status);
10310                 goto out;
10311         }
10312         /* update the local VSI info with updated queue map */
10313         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10314                                         sizeof(vsi->info.tc_mapping));
10315         rte_memcpy(&vsi->info.queue_mapping,
10316                         &ctxt.info.queue_mapping,
10317                 sizeof(vsi->info.queue_mapping));
10318         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10319         vsi->info.valid_sections = 0;
10320
10321         /* query and update current VSI BW information */
10322         ret = i40e_vsi_get_bw_config(vsi);
10323         if (ret) {
10324                 PMD_INIT_LOG(ERR,
10325                          "Failed updating vsi bw info, err %s aq_err %s",
10326                          i40e_stat_str(hw, ret),
10327                          i40e_aq_str(hw, hw->aq.asq_last_status));
10328                 goto out;
10329         }
10330
10331         vsi->enabled_tc = tc_map;
10332
10333 out:
10334         return ret;
10335 }
10336
10337 /*
10338  * i40e_dcb_hw_configure - program the dcb setting to hw
10339  * @pf: pf the configuration is taken on
10340  * @new_cfg: new configuration
10341  * @tc_map: enabled TC bitmap
10342  *
10343  * Returns 0 on success, negative value on failure
10344  */
10345 static enum i40e_status_code
10346 i40e_dcb_hw_configure(struct i40e_pf *pf,
10347                       struct i40e_dcbx_config *new_cfg,
10348                       uint8_t tc_map)
10349 {
10350         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10351         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10352         struct i40e_vsi *main_vsi = pf->main_vsi;
10353         struct i40e_vsi_list *vsi_list;
10354         enum i40e_status_code ret;
10355         int i;
10356         uint32_t val;
10357
10358         /* Use the FW API if FW > v4.4*/
10359         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10360               (hw->aq.fw_maj_ver >= 5))) {
10361                 PMD_INIT_LOG(ERR,
10362                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10363                 return I40E_ERR_FIRMWARE_API_VERSION;
10364         }
10365
10366         /* Check if need reconfiguration */
10367         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10368                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10369                 return I40E_SUCCESS;
10370         }
10371
10372         /* Copy the new config to the current config */
10373         *old_cfg = *new_cfg;
10374         old_cfg->etsrec = old_cfg->etscfg;
10375         ret = i40e_set_dcb_config(hw);
10376         if (ret) {
10377                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10378                          i40e_stat_str(hw, ret),
10379                          i40e_aq_str(hw, hw->aq.asq_last_status));
10380                 return ret;
10381         }
10382         /* set receive Arbiter to RR mode and ETS scheme by default */
10383         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10384                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10385                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10386                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10387                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10388                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10389                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10390                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10391                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10392                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10393                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10394                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10395                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10396         }
10397         /* get local mib to check whether it is configured correctly */
10398         /* IEEE mode */
10399         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10400         /* Get Local DCB Config */
10401         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10402                                      &hw->local_dcbx_config);
10403
10404         /* if Veb is created, need to update TC of it at first */
10405         if (main_vsi->veb) {
10406                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10407                 if (ret)
10408                         PMD_INIT_LOG(WARNING,
10409                                  "Failed configuring TC for VEB seid=%d",
10410                                  main_vsi->veb->seid);
10411         }
10412         /* Update each VSI */
10413         i40e_vsi_config_tc(main_vsi, tc_map);
10414         if (main_vsi->veb) {
10415                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10416                         /* Beside main VSI and VMDQ VSIs, only enable default
10417                          * TC for other VSIs
10418                          */
10419                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10420                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10421                                                          tc_map);
10422                         else
10423                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10424                                                          I40E_DEFAULT_TCMAP);
10425                         if (ret)
10426                                 PMD_INIT_LOG(WARNING,
10427                                         "Failed configuring TC for VSI seid=%d",
10428                                         vsi_list->vsi->seid);
10429                         /* continue */
10430                 }
10431         }
10432         return I40E_SUCCESS;
10433 }
10434
10435 /*
10436  * i40e_dcb_init_configure - initial dcb config
10437  * @dev: device being configured
10438  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10439  *
10440  * Returns 0 on success, negative value on failure
10441  */
10442 static int
10443 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10444 {
10445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10446         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10447         int i, ret = 0;
10448
10449         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10450                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10451                 return -ENOTSUP;
10452         }
10453
10454         /* DCB initialization:
10455          * Update DCB configuration from the Firmware and configure
10456          * LLDP MIB change event.
10457          */
10458         if (sw_dcb == TRUE) {
10459                 ret = i40e_init_dcb(hw);
10460                 /* If lldp agent is stopped, the return value from
10461                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10462                  * adminq status. Otherwise, it should return success.
10463                  */
10464                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10465                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10466                         memset(&hw->local_dcbx_config, 0,
10467                                 sizeof(struct i40e_dcbx_config));
10468                         /* set dcb default configuration */
10469                         hw->local_dcbx_config.etscfg.willing = 0;
10470                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10471                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10472                         hw->local_dcbx_config.etscfg.tsatable[0] =
10473                                                 I40E_IEEE_TSA_ETS;
10474                         /* all UPs mapping to TC0 */
10475                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10476                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10477                         hw->local_dcbx_config.etsrec =
10478                                 hw->local_dcbx_config.etscfg;
10479                         hw->local_dcbx_config.pfc.willing = 0;
10480                         hw->local_dcbx_config.pfc.pfccap =
10481                                                 I40E_MAX_TRAFFIC_CLASS;
10482                         /* FW needs one App to configure HW */
10483                         hw->local_dcbx_config.numapps = 1;
10484                         hw->local_dcbx_config.app[0].selector =
10485                                                 I40E_APP_SEL_ETHTYPE;
10486                         hw->local_dcbx_config.app[0].priority = 3;
10487                         hw->local_dcbx_config.app[0].protocolid =
10488                                                 I40E_APP_PROTOID_FCOE;
10489                         ret = i40e_set_dcb_config(hw);
10490                         if (ret) {
10491                                 PMD_INIT_LOG(ERR,
10492                                         "default dcb config fails. err = %d, aq_err = %d.",
10493                                         ret, hw->aq.asq_last_status);
10494                                 return -ENOSYS;
10495                         }
10496                 } else {
10497                         PMD_INIT_LOG(ERR,
10498                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10499                                 ret, hw->aq.asq_last_status);
10500                         return -ENOTSUP;
10501                 }
10502         } else {
10503                 ret = i40e_aq_start_lldp(hw, NULL);
10504                 if (ret != I40E_SUCCESS)
10505                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10506
10507                 ret = i40e_init_dcb(hw);
10508                 if (!ret) {
10509                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10510                                 PMD_INIT_LOG(ERR,
10511                                         "HW doesn't support DCBX offload.");
10512                                 return -ENOTSUP;
10513                         }
10514                 } else {
10515                         PMD_INIT_LOG(ERR,
10516                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10517                                 ret, hw->aq.asq_last_status);
10518                         return -ENOTSUP;
10519                 }
10520         }
10521         return 0;
10522 }
10523
10524 /*
10525  * i40e_dcb_setup - setup dcb related config
10526  * @dev: device being configured
10527  *
10528  * Returns 0 on success, negative value on failure
10529  */
10530 static int
10531 i40e_dcb_setup(struct rte_eth_dev *dev)
10532 {
10533         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10534         struct i40e_dcbx_config dcb_cfg;
10535         uint8_t tc_map = 0;
10536         int ret = 0;
10537
10538         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10539                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10540                 return -ENOTSUP;
10541         }
10542
10543         if (pf->vf_num != 0)
10544                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10545
10546         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10547         if (ret) {
10548                 PMD_INIT_LOG(ERR, "invalid dcb config");
10549                 return -EINVAL;
10550         }
10551         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10552         if (ret) {
10553                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10554                 return -ENOSYS;
10555         }
10556
10557         return 0;
10558 }
10559
10560 static int
10561 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10562                       struct rte_eth_dcb_info *dcb_info)
10563 {
10564         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10565         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10566         struct i40e_vsi *vsi = pf->main_vsi;
10567         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10568         uint16_t bsf, tc_mapping;
10569         int i, j = 0;
10570
10571         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10572                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10573         else
10574                 dcb_info->nb_tcs = 1;
10575         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10576                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10577         for (i = 0; i < dcb_info->nb_tcs; i++)
10578                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10579
10580         /* get queue mapping if vmdq is disabled */
10581         if (!pf->nb_cfg_vmdq_vsi) {
10582                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10583                         if (!(vsi->enabled_tc & (1 << i)))
10584                                 continue;
10585                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10586                         dcb_info->tc_queue.tc_rxq[j][i].base =
10587                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10588                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10589                         dcb_info->tc_queue.tc_txq[j][i].base =
10590                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10591                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10592                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10593                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10594                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10595                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10596                 }
10597                 return 0;
10598         }
10599
10600         /* get queue mapping if vmdq is enabled */
10601         do {
10602                 vsi = pf->vmdq[j].vsi;
10603                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10604                         if (!(vsi->enabled_tc & (1 << i)))
10605                                 continue;
10606                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10607                         dcb_info->tc_queue.tc_rxq[j][i].base =
10608                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10609                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10610                         dcb_info->tc_queue.tc_txq[j][i].base =
10611                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10612                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10613                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10614                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10615                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10616                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10617                 }
10618                 j++;
10619         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10620         return 0;
10621 }
10622
10623 static int
10624 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10625 {
10626         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10627         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10629         uint16_t interval =
10630                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10631         uint16_t msix_intr;
10632
10633         msix_intr = intr_handle->intr_vec[queue_id];
10634         if (msix_intr == I40E_MISC_VEC_ID)
10635                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10636                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10637                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10638                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10639                                (interval <<
10640                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10641         else
10642                 I40E_WRITE_REG(hw,
10643                                I40E_PFINT_DYN_CTLN(msix_intr -
10644                                                    I40E_RX_VEC_START),
10645                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10646                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10647                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10648                                (interval <<
10649                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10650
10651         I40E_WRITE_FLUSH(hw);
10652         rte_intr_enable(&pci_dev->intr_handle);
10653
10654         return 0;
10655 }
10656
10657 static int
10658 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10659 {
10660         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10661         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10663         uint16_t msix_intr;
10664
10665         msix_intr = intr_handle->intr_vec[queue_id];
10666         if (msix_intr == I40E_MISC_VEC_ID)
10667                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10668         else
10669                 I40E_WRITE_REG(hw,
10670                                I40E_PFINT_DYN_CTLN(msix_intr -
10671                                                    I40E_RX_VEC_START),
10672                                0);
10673         I40E_WRITE_FLUSH(hw);
10674
10675         return 0;
10676 }
10677
10678 static int i40e_get_regs(struct rte_eth_dev *dev,
10679                          struct rte_dev_reg_info *regs)
10680 {
10681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10682         uint32_t *ptr_data = regs->data;
10683         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10684         const struct i40e_reg_info *reg_info;
10685
10686         if (ptr_data == NULL) {
10687                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10688                 regs->width = sizeof(uint32_t);
10689                 return 0;
10690         }
10691
10692         /* The first few registers have to be read using AQ operations */
10693         reg_idx = 0;
10694         while (i40e_regs_adminq[reg_idx].name) {
10695                 reg_info = &i40e_regs_adminq[reg_idx++];
10696                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10697                         for (arr_idx2 = 0;
10698                                         arr_idx2 <= reg_info->count2;
10699                                         arr_idx2++) {
10700                                 reg_offset = arr_idx * reg_info->stride1 +
10701                                         arr_idx2 * reg_info->stride2;
10702                                 reg_offset += reg_info->base_addr;
10703                                 ptr_data[reg_offset >> 2] =
10704                                         i40e_read_rx_ctl(hw, reg_offset);
10705                         }
10706         }
10707
10708         /* The remaining registers can be read using primitives */
10709         reg_idx = 0;
10710         while (i40e_regs_others[reg_idx].name) {
10711                 reg_info = &i40e_regs_others[reg_idx++];
10712                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10713                         for (arr_idx2 = 0;
10714                                         arr_idx2 <= reg_info->count2;
10715                                         arr_idx2++) {
10716                                 reg_offset = arr_idx * reg_info->stride1 +
10717                                         arr_idx2 * reg_info->stride2;
10718                                 reg_offset += reg_info->base_addr;
10719                                 ptr_data[reg_offset >> 2] =
10720                                         I40E_READ_REG(hw, reg_offset);
10721                         }
10722         }
10723
10724         return 0;
10725 }
10726
10727 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10728 {
10729         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10730
10731         /* Convert word count to byte count */
10732         return hw->nvm.sr_size << 1;
10733 }
10734
10735 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10736                            struct rte_dev_eeprom_info *eeprom)
10737 {
10738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10739         uint16_t *data = eeprom->data;
10740         uint16_t offset, length, cnt_words;
10741         int ret_code;
10742
10743         offset = eeprom->offset >> 1;
10744         length = eeprom->length >> 1;
10745         cnt_words = length;
10746
10747         if (offset > hw->nvm.sr_size ||
10748                 offset + length > hw->nvm.sr_size) {
10749                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10750                 return -EINVAL;
10751         }
10752
10753         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10754
10755         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10756         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10757                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10758                 return -EIO;
10759         }
10760
10761         return 0;
10762 }
10763
10764 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10765                                       struct ether_addr *mac_addr)
10766 {
10767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10768
10769         if (!is_valid_assigned_ether_addr(mac_addr)) {
10770                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10771                 return;
10772         }
10773
10774         /* Flags: 0x3 updates port address */
10775         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10776 }
10777
10778 static int
10779 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10780 {
10781         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10782         struct rte_eth_dev_data *dev_data = pf->dev_data;
10783         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10784         int ret = 0;
10785
10786         /* check if mtu is within the allowed range */
10787         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10788                 return -EINVAL;
10789
10790         /* mtu setting is forbidden if port is start */
10791         if (dev_data->dev_started) {
10792                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10793                             dev_data->port_id);
10794                 return -EBUSY;
10795         }
10796
10797         if (frame_size > ETHER_MAX_LEN)
10798                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10799         else
10800                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10801
10802         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10803
10804         return ret;
10805 }
10806
10807 /* Restore ethertype filter */
10808 static void
10809 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10810 {
10811         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10812         struct i40e_ethertype_filter_list
10813                 *ethertype_list = &pf->ethertype.ethertype_list;
10814         struct i40e_ethertype_filter *f;
10815         struct i40e_control_filter_stats stats;
10816         uint16_t flags;
10817
10818         TAILQ_FOREACH(f, ethertype_list, rules) {
10819                 flags = 0;
10820                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10821                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10822                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10823                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10824                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10825
10826                 memset(&stats, 0, sizeof(stats));
10827                 i40e_aq_add_rem_control_packet_filter(hw,
10828                                             f->input.mac_addr.addr_bytes,
10829                                             f->input.ether_type,
10830                                             flags, pf->main_vsi->seid,
10831                                             f->queue, 1, &stats, NULL);
10832         }
10833         PMD_DRV_LOG(INFO, "Ethertype filter:"
10834                     " mac_etype_used = %u, etype_used = %u,"
10835                     " mac_etype_free = %u, etype_free = %u",
10836                     stats.mac_etype_used, stats.etype_used,
10837                     stats.mac_etype_free, stats.etype_free);
10838 }
10839
10840 /* Restore tunnel filter */
10841 static void
10842 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10843 {
10844         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10845         struct i40e_vsi *vsi;
10846         struct i40e_pf_vf *vf;
10847         struct i40e_tunnel_filter_list
10848                 *tunnel_list = &pf->tunnel.tunnel_list;
10849         struct i40e_tunnel_filter *f;
10850         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10851         bool big_buffer = 0;
10852
10853         TAILQ_FOREACH(f, tunnel_list, rules) {
10854                 if (!f->is_to_vf)
10855                         vsi = pf->main_vsi;
10856                 else {
10857                         vf = &pf->vfs[f->vf_id];
10858                         vsi = vf->vsi;
10859                 }
10860                 memset(&cld_filter, 0, sizeof(cld_filter));
10861                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10862                         (struct ether_addr *)&cld_filter.element.outer_mac);
10863                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10864                         (struct ether_addr *)&cld_filter.element.inner_mac);
10865                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10866                 cld_filter.element.flags = f->input.flags;
10867                 cld_filter.element.tenant_id = f->input.tenant_id;
10868                 cld_filter.element.queue_number = f->queue;
10869                 rte_memcpy(cld_filter.general_fields,
10870                            f->input.general_fields,
10871                            sizeof(f->input.general_fields));
10872
10873                 if (((f->input.flags &
10874                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10875                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10876                     ((f->input.flags &
10877                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10878                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10879                     ((f->input.flags &
10880                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10881                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10882                         big_buffer = 1;
10883
10884                 if (big_buffer)
10885                         i40e_aq_add_cloud_filters_big_buffer(hw,
10886                                              vsi->seid, &cld_filter, 1);
10887                 else
10888                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10889                                                   &cld_filter.element, 1);
10890         }
10891 }
10892
10893 static void
10894 i40e_filter_restore(struct i40e_pf *pf)
10895 {
10896         i40e_ethertype_filter_restore(pf);
10897         i40e_tunnel_filter_restore(pf);
10898         i40e_fdir_filter_restore(pf);
10899 }
10900
10901 static bool
10902 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10903 {
10904         if (strcmp(dev->device->driver->name, drv->driver.name))
10905                 return false;
10906
10907         return true;
10908 }
10909
10910 bool
10911 is_i40e_supported(struct rte_eth_dev *dev)
10912 {
10913         return is_device_supported(dev, &rte_i40e_pmd);
10914 }
10915
10916 /* Create a QinQ cloud filter
10917  *
10918  * The Fortville NIC has limited resources for tunnel filters,
10919  * so we can only reuse existing filters.
10920  *
10921  * In step 1 we define which Field Vector fields can be used for
10922  * filter types.
10923  * As we do not have the inner tag defined as a field,
10924  * we have to define it first, by reusing one of L1 entries.
10925  *
10926  * In step 2 we are replacing one of existing filter types with
10927  * a new one for QinQ.
10928  * As we reusing L1 and replacing L2, some of the default filter
10929  * types will disappear,which depends on L1 and L2 entries we reuse.
10930  *
10931  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10932  *
10933  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10934  *              later when we define the cloud filter.
10935  *      a.      Valid_flags.replace_cloud = 0
10936  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10937  *      c.      New_filter = 0x10
10938  *      d.      TR bit = 0xff (optional, not used here)
10939  *      e.      Buffer – 2 entries:
10940  *              i.      Byte 0 = 8 (outer vlan FV index).
10941  *                      Byte 1 = 0 (rsv)
10942  *                      Byte 2-3 = 0x0fff
10943  *              ii.     Byte 0 = 37 (inner vlan FV index).
10944  *                      Byte 1 =0 (rsv)
10945  *                      Byte 2-3 = 0x0fff
10946  *
10947  * Step 2:
10948  * 2.   Create cloud filter using two L1 filters entries: stag and
10949  *              new filter(outer vlan+ inner vlan)
10950  *      a.      Valid_flags.replace_cloud = 1
10951  *      b.      Old_filter = 1 (instead of outer IP)
10952  *      c.      New_filter = 0x10
10953  *      d.      Buffer – 2 entries:
10954  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10955  *                      Byte 1-3 = 0 (rsv)
10956  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10957  *                      Byte 9-11 = 0 (rsv)
10958  */
10959 static int
10960 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10961 {
10962         int ret = -ENOTSUP;
10963         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10964         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10965         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10966
10967         /* Init */
10968         memset(&filter_replace, 0,
10969                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10970         memset(&filter_replace_buf, 0,
10971                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10972
10973         /* create L1 filter */
10974         filter_replace.old_filter_type =
10975                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10976         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10977         filter_replace.tr_bit = 0;
10978
10979         /* Prepare the buffer, 2 entries */
10980         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10981         filter_replace_buf.data[0] |=
10982                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10983         /* Field Vector 12b mask */
10984         filter_replace_buf.data[2] = 0xff;
10985         filter_replace_buf.data[3] = 0x0f;
10986         filter_replace_buf.data[4] =
10987                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10988         filter_replace_buf.data[4] |=
10989                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10990         /* Field Vector 12b mask */
10991         filter_replace_buf.data[6] = 0xff;
10992         filter_replace_buf.data[7] = 0x0f;
10993         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10994                         &filter_replace_buf);
10995         if (ret != I40E_SUCCESS)
10996                 return ret;
10997
10998         /* Apply the second L2 cloud filter */
10999         memset(&filter_replace, 0,
11000                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11001         memset(&filter_replace_buf, 0,
11002                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11003
11004         /* create L2 filter, input for L2 filter will be L1 filter  */
11005         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11006         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11007         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
11008
11009         /* Prepare the buffer, 2 entries */
11010         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11011         filter_replace_buf.data[0] |=
11012                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11013         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
11014         filter_replace_buf.data[4] |=
11015                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11016         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11017                         &filter_replace_buf);
11018         return ret;
11019 }
11020
11021 RTE_INIT(i40e_init_log);
11022 static void
11023 i40e_init_log(void)
11024 {
11025         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11026         if (i40e_logtype_init >= 0)
11027                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11028         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11029         if (i40e_logtype_driver >= 0)
11030                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11031 }