4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
80 /* Flow control default timer */
81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
83 /* Flow control default high water */
84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
86 /* Flow control default low water */
87 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Receive Average Packet Size in Byte*/
99 #define I40E_PACKET_AVERAGE_SIZE 128
101 /* Mask of PF interrupt causes */
102 #define I40E_PFINT_ICR0_ENA_MASK ( \
103 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
104 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
105 I40E_PFINT_ICR0_ENA_GRST_MASK | \
106 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
107 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
109 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
111 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
112 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
114 #define I40E_FLOW_TYPES ( \
115 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
116 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
125 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
127 /* Additional timesync values. */
128 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
129 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
130 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
131 #define I40E_PRTTSYN_TSYNENA 0x80000000
132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
133 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
135 #define I40E_MAX_PERCENT 100
136 #define I40E_DEFAULT_DCB_APP_NUM 1
137 #define I40E_DEFAULT_DCB_APP_PRIO 3
139 #define I40E_INSET_NONE 0x00000000000000000ULL
142 #define I40E_INSET_DMAC 0x0000000000000001ULL
143 #define I40E_INSET_SMAC 0x0000000000000002ULL
144 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
145 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
146 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
149 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
150 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
151 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
152 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
153 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
154 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
155 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
157 /* bit 16 ~ bit 31 */
158 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
159 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
160 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
161 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
162 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
163 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
164 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
165 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
167 /* bit 32 ~ bit 47, tunnel fields */
168 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
169 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
170 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
171 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
172 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
173 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
175 /* bit 48 ~ bit 55 */
176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
178 /* bit 56 ~ bit 63, Flex Payload */
179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD \
188 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
189 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
190 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
191 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
194 * Below are values for writing un-exposed registers suggested
197 /* Destination MAC address */
198 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
199 /* Source MAC address */
200 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
202 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
205 /* Single VLAN tag in the inner L2 header */
206 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
207 /* Source IPv4 address */
208 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
209 /* Destination IPv4 address */
210 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
211 /* IPv4 Type of Service (TOS) */
212 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
214 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
215 /* IPv4 Time to Live */
216 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
217 /* Source IPv6 address */
218 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
219 /* Destination IPv6 address */
220 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
221 /* IPv6 Traffic Class (TC) */
222 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
223 /* IPv6 Next Header */
224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
228 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
229 /* Destination L4 port */
230 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
231 /* SCTP verification tag */
232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
235 /* Source port of tunneling UDP */
236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
237 /* Destination port of tunneling UDP */
238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
239 /* UDP Tunneling ID, NVGRE/GRE key */
240 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
241 /* Last ether type */
242 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
243 /* Tunneling outer destination IPv4 address */
244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
245 /* Tunneling outer destination IPv6 address */
246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
247 /* 1st word of flex payload */
248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
249 /* 2nd word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
251 /* 3rd word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
253 /* 4th word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
255 /* 5th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
257 /* 6th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
259 /* 7th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
261 /* 8th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
263 /* all 8 words flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
265 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
267 #define I40E_TRANSLATE_INSET 0
268 #define I40E_TRANSLATE_REG 1
270 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
271 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
272 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
273 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
275 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
277 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
280 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
282 /* PCI offset for querying capability */
283 #define PCI_DEV_CAP_REG 0xA4
284 /* PCI offset for enabling/disabling Extended Tag */
285 #define PCI_DEV_CTRL_REG 0xA8
286 /* Bit mask of Extended Tag capability */
287 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
288 /* Bit shift of Extended Tag enable/disable */
289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
290 /* Bit mask of Extended Tag enable/disable */
291 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
295 static int i40e_dev_configure(struct rte_eth_dev *dev);
296 static int i40e_dev_start(struct rte_eth_dev *dev);
297 static void i40e_dev_stop(struct rte_eth_dev *dev);
298 static void i40e_dev_close(struct rte_eth_dev *dev);
299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
306 struct rte_eth_stats *stats);
307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
308 struct rte_eth_xstats *xstats, unsigned n);
309 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
310 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
314 static void i40e_dev_info_get(struct rte_eth_dev *dev,
315 struct rte_eth_dev_info *dev_info);
316 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
319 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
320 enum rte_vlan_type vlan_type,
322 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
323 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
326 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
327 static int i40e_dev_led_on(struct rte_eth_dev *dev);
328 static int i40e_dev_led_off(struct rte_eth_dev *dev);
329 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
330 struct rte_eth_fc_conf *fc_conf);
331 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
332 struct rte_eth_fc_conf *fc_conf);
333 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
334 struct rte_eth_pfc_conf *pfc_conf);
335 static void i40e_macaddr_add(struct rte_eth_dev *dev,
336 struct ether_addr *mac_addr,
339 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
340 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
341 struct rte_eth_rss_reta_entry64 *reta_conf,
343 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
344 struct rte_eth_rss_reta_entry64 *reta_conf,
347 static int i40e_get_cap(struct i40e_hw *hw);
348 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
349 static int i40e_pf_setup(struct i40e_pf *pf);
350 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
351 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
352 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
353 static int i40e_dcb_setup(struct rte_eth_dev *dev);
354 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
355 bool offset_loaded, uint64_t *offset, uint64_t *stat);
356 static void i40e_stat_update_48(struct i40e_hw *hw,
362 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
363 static void i40e_dev_interrupt_handler(
364 __rte_unused struct rte_intr_handle *handle, void *param);
365 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
366 uint32_t base, uint32_t num);
367 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
368 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
370 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
372 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
373 static int i40e_veb_release(struct i40e_veb *veb);
374 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
375 struct i40e_vsi *vsi);
376 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
377 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
378 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
379 struct i40e_macvlan_filter *mv_f,
381 struct ether_addr *addr);
382 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
383 struct i40e_macvlan_filter *mv_f,
386 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
387 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
388 struct rte_eth_rss_conf *rss_conf);
389 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
390 struct rte_eth_rss_conf *rss_conf);
391 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
392 struct rte_eth_udp_tunnel *udp_tunnel);
393 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
394 struct rte_eth_udp_tunnel *udp_tunnel);
395 static void i40e_filter_input_set_init(struct i40e_pf *pf);
396 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
397 struct rte_eth_ethertype_filter *filter,
399 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
400 enum rte_filter_op filter_op,
402 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
403 enum rte_filter_type filter_type,
404 enum rte_filter_op filter_op,
406 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
407 struct rte_eth_dcb_info *dcb_info);
408 static void i40e_configure_registers(struct i40e_hw *hw);
409 static void i40e_hw_init(struct rte_eth_dev *dev);
410 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
411 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
412 struct rte_eth_mirror_conf *mirror_conf,
413 uint8_t sw_id, uint8_t on);
414 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
416 static int i40e_timesync_enable(struct rte_eth_dev *dev);
417 static int i40e_timesync_disable(struct rte_eth_dev *dev);
418 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
419 struct timespec *timestamp,
421 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
422 struct timespec *timestamp);
423 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
425 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
427 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
428 struct timespec *timestamp);
429 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
430 const struct timespec *timestamp);
432 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
434 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
437 static int i40e_get_reg_length(struct rte_eth_dev *dev);
439 static int i40e_get_regs(struct rte_eth_dev *dev,
440 struct rte_dev_reg_info *regs);
442 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
444 static int i40e_get_eeprom(struct rte_eth_dev *dev,
445 struct rte_dev_eeprom_info *eeprom);
447 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
448 struct ether_addr *mac_addr);
450 static const struct rte_pci_id pci_id_i40e_map[] = {
451 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
452 #include "rte_pci_dev_ids.h"
453 { .vendor_id = 0, /* sentinel */ },
456 static const struct eth_dev_ops i40e_eth_dev_ops = {
457 .dev_configure = i40e_dev_configure,
458 .dev_start = i40e_dev_start,
459 .dev_stop = i40e_dev_stop,
460 .dev_close = i40e_dev_close,
461 .promiscuous_enable = i40e_dev_promiscuous_enable,
462 .promiscuous_disable = i40e_dev_promiscuous_disable,
463 .allmulticast_enable = i40e_dev_allmulticast_enable,
464 .allmulticast_disable = i40e_dev_allmulticast_disable,
465 .dev_set_link_up = i40e_dev_set_link_up,
466 .dev_set_link_down = i40e_dev_set_link_down,
467 .link_update = i40e_dev_link_update,
468 .stats_get = i40e_dev_stats_get,
469 .xstats_get = i40e_dev_xstats_get,
470 .stats_reset = i40e_dev_stats_reset,
471 .xstats_reset = i40e_dev_stats_reset,
472 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
473 .dev_infos_get = i40e_dev_info_get,
474 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
475 .vlan_filter_set = i40e_vlan_filter_set,
476 .vlan_tpid_set = i40e_vlan_tpid_set,
477 .vlan_offload_set = i40e_vlan_offload_set,
478 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
479 .vlan_pvid_set = i40e_vlan_pvid_set,
480 .rx_queue_start = i40e_dev_rx_queue_start,
481 .rx_queue_stop = i40e_dev_rx_queue_stop,
482 .tx_queue_start = i40e_dev_tx_queue_start,
483 .tx_queue_stop = i40e_dev_tx_queue_stop,
484 .rx_queue_setup = i40e_dev_rx_queue_setup,
485 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
486 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
487 .rx_queue_release = i40e_dev_rx_queue_release,
488 .rx_queue_count = i40e_dev_rx_queue_count,
489 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .filter_ctrl = i40e_dev_filter_ctrl,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .mirror_rule_set = i40e_mirror_rule_set,
509 .mirror_rule_reset = i40e_mirror_rule_reset,
510 .timesync_enable = i40e_timesync_enable,
511 .timesync_disable = i40e_timesync_disable,
512 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
513 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
514 .get_dcb_info = i40e_dev_get_dcb_info,
515 .timesync_adjust_time = i40e_timesync_adjust_time,
516 .timesync_read_time = i40e_timesync_read_time,
517 .timesync_write_time = i40e_timesync_write_time,
518 .get_reg_length = i40e_get_reg_length,
519 .get_reg = i40e_get_regs,
520 .get_eeprom_length = i40e_get_eeprom_length,
521 .get_eeprom = i40e_get_eeprom,
522 .mac_addr_set = i40e_set_default_mac_addr,
525 /* store statistics names and its offset in stats structure */
526 struct rte_i40e_xstats_name_off {
527 char name[RTE_ETH_XSTATS_NAME_SIZE];
531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
532 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
533 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
534 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
535 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
536 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
537 rx_unknown_protocol)},
538 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
539 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
540 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
541 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
545 sizeof(rte_i40e_stats_strings[0]))
547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
548 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
549 tx_dropped_link_down)},
550 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
551 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
554 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
556 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
560 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
561 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
562 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
563 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
564 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
565 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
581 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
582 mac_short_packet_dropped)},
583 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
586 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
587 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
599 {"rx_flow_director_atr_match_packets",
600 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
601 {"rx_flow_director_sb_match_packets",
602 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
603 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
605 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
607 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
614 sizeof(rte_i40e_hw_port_strings[0]))
616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
617 {"xon_packets", offsetof(struct i40e_hw_port_stats,
619 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
624 sizeof(rte_i40e_rxq_prio_strings[0]))
626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
627 {"xon_packets", offsetof(struct i40e_hw_port_stats,
629 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
631 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
632 priority_xon_2_xoff)},
635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
636 sizeof(rte_i40e_txq_prio_strings[0]))
638 static struct eth_driver rte_i40e_pmd = {
640 .name = "rte_i40e_pmd",
641 .id_table = pci_id_i40e_map,
642 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
643 RTE_PCI_DRV_DETACHABLE,
645 .eth_dev_init = eth_i40e_dev_init,
646 .eth_dev_uninit = eth_i40e_dev_uninit,
647 .dev_private_size = sizeof(struct i40e_adapter),
651 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
652 struct rte_eth_link *link)
654 struct rte_eth_link *dst = link;
655 struct rte_eth_link *src = &(dev->data->dev_link);
657 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
658 *(uint64_t *)src) == 0)
665 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
666 struct rte_eth_link *link)
668 struct rte_eth_link *dst = &(dev->data->dev_link);
669 struct rte_eth_link *src = link;
671 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
672 *(uint64_t *)src) == 0)
679 * Driver initialization routine.
680 * Invoked once at EAL init time.
681 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
684 rte_i40e_pmd_init(const char *name __rte_unused,
685 const char *params __rte_unused)
687 PMD_INIT_FUNC_TRACE();
688 rte_eth_driver_register(&rte_i40e_pmd);
693 static struct rte_driver rte_i40e_driver = {
695 .init = rte_i40e_pmd_init,
698 PMD_REGISTER_DRIVER(rte_i40e_driver);
701 * Initialize registers for flexible payload, which should be set by NVM.
702 * This should be removed from code once it is fixed in NVM.
704 #ifndef I40E_GLQF_ORT
705 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
707 #ifndef I40E_GLQF_PIT
708 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
711 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
721 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
724 /* GLQF_PIT Registers */
725 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
726 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
729 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
732 * Add a ethertype filter to drop all flow control frames transmitted
736 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
739 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
740 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
741 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
744 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
745 I40E_FLOW_CONTROL_ETHERTYPE, flags,
746 pf->main_vsi_seid, 0,
749 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
750 " frames from VSIs.");
754 eth_i40e_dev_init(struct rte_eth_dev *dev)
756 struct rte_pci_device *pci_dev;
757 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
758 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
759 struct i40e_vsi *vsi;
764 PMD_INIT_FUNC_TRACE();
766 dev->dev_ops = &i40e_eth_dev_ops;
767 dev->rx_pkt_burst = i40e_recv_pkts;
768 dev->tx_pkt_burst = i40e_xmit_pkts;
770 /* for secondary processes, we don't initialise any further as primary
771 * has already done this work. Only check we don't need a different
773 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
774 i40e_set_rx_function(dev);
775 i40e_set_tx_function(dev);
778 pci_dev = dev->pci_dev;
780 rte_eth_copy_pci_info(dev, pci_dev);
782 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
783 pf->adapter->eth_dev = dev;
784 pf->dev_data = dev->data;
786 hw->back = I40E_PF_TO_ADAPTER(pf);
787 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
789 PMD_INIT_LOG(ERR, "Hardware is not available, "
790 "as address is NULL");
794 hw->vendor_id = pci_dev->id.vendor_id;
795 hw->device_id = pci_dev->id.device_id;
796 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
797 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
798 hw->bus.device = pci_dev->addr.devid;
799 hw->bus.func = pci_dev->addr.function;
800 hw->adapter_stopped = 0;
802 /* Make sure all is clean before doing PF reset */
805 /* Initialize the hardware */
808 /* Reset here to make sure all is clean for each PF */
809 ret = i40e_pf_reset(hw);
811 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
815 /* Initialize the shared code (base driver) */
816 ret = i40e_init_shared_code(hw);
818 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
823 * To work around the NVM issue,initialize registers
824 * for flexible payload by software.
825 * It should be removed once issues are fixed in NVM.
827 i40e_flex_payload_reg_init(hw);
829 /* Initialize the input set for filters (hash and fd) to default value */
830 i40e_filter_input_set_init(pf);
832 /* Initialize the parameters for adminq */
833 i40e_init_adminq_parameter(hw);
834 ret = i40e_init_adminq(hw);
835 if (ret != I40E_SUCCESS) {
836 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
839 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
840 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
841 hw->aq.api_maj_ver, hw->aq.api_min_ver,
842 ((hw->nvm.version >> 12) & 0xf),
843 ((hw->nvm.version >> 4) & 0xff),
844 (hw->nvm.version & 0xf), hw->nvm.eetrack);
847 i40e_clear_pxe_mode(hw);
850 * On X710, performance number is far from the expectation on recent
851 * firmware versions. The fix for this issue may not be integrated in
852 * the following firmware version. So the workaround in software driver
853 * is needed. It needs to modify the initial values of 3 internal only
854 * registers. Note that the workaround can be removed when it is fixed
855 * in firmware in the future.
857 i40e_configure_registers(hw);
859 /* Get hw capabilities */
860 ret = i40e_get_cap(hw);
861 if (ret != I40E_SUCCESS) {
862 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
863 goto err_get_capabilities;
866 /* Initialize parameters for PF */
867 ret = i40e_pf_parameter_init(dev);
869 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
870 goto err_parameter_init;
873 /* Initialize the queue management */
874 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
876 PMD_INIT_LOG(ERR, "Failed to init queue pool");
877 goto err_qp_pool_init;
879 ret = i40e_res_pool_init(&pf->msix_pool, 1,
880 hw->func_caps.num_msix_vectors - 1);
882 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
883 goto err_msix_pool_init;
886 /* Initialize lan hmc */
887 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
888 hw->func_caps.num_rx_qp, 0, 0);
889 if (ret != I40E_SUCCESS) {
890 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
891 goto err_init_lan_hmc;
894 /* Configure lan hmc */
895 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
896 if (ret != I40E_SUCCESS) {
897 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
898 goto err_configure_lan_hmc;
901 /* Get and check the mac address */
902 i40e_get_mac_addr(hw, hw->mac.addr);
903 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
904 PMD_INIT_LOG(ERR, "mac address is not valid");
906 goto err_get_mac_addr;
908 /* Copy the permanent MAC address */
909 ether_addr_copy((struct ether_addr *) hw->mac.addr,
910 (struct ether_addr *) hw->mac.perm_addr);
912 /* Disable flow control */
913 hw->fc.requested_mode = I40E_FC_NONE;
914 i40e_set_fc(hw, &aq_fail, TRUE);
916 /* Set the global registers with default ether type value */
917 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
918 if (ret != I40E_SUCCESS) {
919 PMD_INIT_LOG(ERR, "Failed to set the default outer "
921 goto err_setup_pf_switch;
923 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
924 if (ret != I40E_SUCCESS) {
925 PMD_INIT_LOG(ERR, "Failed to set the default outer "
927 goto err_setup_pf_switch;
930 /* PF setup, which includes VSI setup */
931 ret = i40e_pf_setup(pf);
933 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
934 goto err_setup_pf_switch;
939 /* Disable double vlan by default */
940 i40e_vsi_config_double_vlan(vsi, FALSE);
942 if (!vsi->max_macaddrs)
943 len = ETHER_ADDR_LEN;
945 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
947 /* Should be after VSI initialized */
948 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
949 if (!dev->data->mac_addrs) {
950 PMD_INIT_LOG(ERR, "Failed to allocated memory "
951 "for storing mac address");
954 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
955 &dev->data->mac_addrs[0]);
957 /* initialize pf host driver to setup SRIOV resource if applicable */
958 i40e_pf_host_init(dev);
960 /* register callback func to eal lib */
961 rte_intr_callback_register(&(pci_dev->intr_handle),
962 i40e_dev_interrupt_handler, (void *)dev);
964 /* configure and enable device interrupt */
965 i40e_pf_config_irq0(hw, TRUE);
966 i40e_pf_enable_irq0(hw);
968 /* enable uio intr after callback register */
969 rte_intr_enable(&(pci_dev->intr_handle));
971 * Add an ethertype filter to drop all flow control frames transmitted
972 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
975 i40e_add_tx_flow_control_drop_filter(pf);
977 /* Set the max frame size to 0x2600 by default,
978 * in case other drivers changed the default value.
980 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
982 /* initialize mirror rule list */
983 TAILQ_INIT(&pf->mirror_list);
985 /* Init dcb to sw mode by default */
986 ret = i40e_dcb_init_configure(dev, TRUE);
987 if (ret != I40E_SUCCESS) {
988 PMD_INIT_LOG(INFO, "Failed to init dcb.");
989 pf->flags &= ~I40E_FLAG_DCB;
995 i40e_vsi_release(pf->main_vsi);
998 err_configure_lan_hmc:
999 (void)i40e_shutdown_lan_hmc(hw);
1001 i40e_res_pool_destroy(&pf->msix_pool);
1003 i40e_res_pool_destroy(&pf->qp_pool);
1006 err_get_capabilities:
1007 (void)i40e_shutdown_adminq(hw);
1013 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1015 struct rte_pci_device *pci_dev;
1017 struct i40e_filter_control_settings settings;
1019 uint8_t aq_fail = 0;
1021 PMD_INIT_FUNC_TRACE();
1023 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1026 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027 pci_dev = dev->pci_dev;
1029 if (hw->adapter_stopped == 0)
1030 i40e_dev_close(dev);
1032 dev->dev_ops = NULL;
1033 dev->rx_pkt_burst = NULL;
1034 dev->tx_pkt_burst = NULL;
1037 ret = i40e_aq_stop_lldp(hw, true, NULL);
1038 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1039 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1041 /* Clear PXE mode */
1042 i40e_clear_pxe_mode(hw);
1044 /* Unconfigure filter control */
1045 memset(&settings, 0, sizeof(settings));
1046 ret = i40e_set_filter_control(hw, &settings);
1048 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1051 /* Disable flow control */
1052 hw->fc.requested_mode = I40E_FC_NONE;
1053 i40e_set_fc(hw, &aq_fail, TRUE);
1055 /* uninitialize pf host driver */
1056 i40e_pf_host_uninit(dev);
1058 rte_free(dev->data->mac_addrs);
1059 dev->data->mac_addrs = NULL;
1061 /* disable uio intr before callback unregister */
1062 rte_intr_disable(&(pci_dev->intr_handle));
1064 /* register callback func to eal lib */
1065 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1066 i40e_dev_interrupt_handler, (void *)dev);
1072 i40e_dev_configure(struct rte_eth_dev *dev)
1074 struct i40e_adapter *ad =
1075 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1076 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1077 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1080 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1081 * bulk allocation or vector Rx preconditions we will reset it.
1083 ad->rx_bulk_alloc_allowed = true;
1084 ad->rx_vec_allowed = true;
1085 ad->tx_simple_allowed = true;
1086 ad->tx_vec_allowed = true;
1088 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1089 ret = i40e_fdir_setup(pf);
1090 if (ret != I40E_SUCCESS) {
1091 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1094 ret = i40e_fdir_configure(dev);
1096 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1100 i40e_fdir_teardown(pf);
1102 ret = i40e_dev_init_vlan(dev);
1107 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1108 * RSS setting have different requirements.
1109 * General PMD driver call sequence are NIC init, configure,
1110 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1111 * will try to lookup the VSI that specific queue belongs to if VMDQ
1112 * applicable. So, VMDQ setting has to be done before
1113 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1114 * For RSS setting, it will try to calculate actual configured RX queue
1115 * number, which will be available after rx_queue_setup(). dev_start()
1116 * function is good to place RSS setup.
1118 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1119 ret = i40e_vmdq_setup(dev);
1124 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1125 ret = i40e_dcb_setup(dev);
1127 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1135 /* need to release vmdq resource if exists */
1136 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1137 i40e_vsi_release(pf->vmdq[i].vsi);
1138 pf->vmdq[i].vsi = NULL;
1143 /* need to release fdir resource if exists */
1144 i40e_fdir_teardown(pf);
1149 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1151 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1152 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1153 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1154 uint16_t msix_vect = vsi->msix_intr;
1157 for (i = 0; i < vsi->nb_qps; i++) {
1158 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1159 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1163 if (vsi->type != I40E_VSI_SRIOV) {
1164 if (!rte_intr_allow_others(intr_handle)) {
1165 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1166 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1168 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1171 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1172 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1174 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1179 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1180 vsi->user_param + (msix_vect - 1);
1182 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1183 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1185 I40E_WRITE_FLUSH(hw);
1189 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1190 int base_queue, int nb_queue)
1194 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1196 /* Bind all RX queues to allocated MSIX interrupt */
1197 for (i = 0; i < nb_queue; i++) {
1198 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1199 I40E_QINT_RQCTL_ITR_INDX_MASK |
1200 ((base_queue + i + 1) <<
1201 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1202 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1203 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1205 if (i == nb_queue - 1)
1206 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1207 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1210 /* Write first RX queue to Link list register as the head element */
1211 if (vsi->type != I40E_VSI_SRIOV) {
1213 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1215 if (msix_vect == I40E_MISC_VEC_ID) {
1216 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1218 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1220 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1222 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1225 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1227 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1229 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1231 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1238 if (msix_vect == I40E_MISC_VEC_ID) {
1240 I40E_VPINT_LNKLST0(vsi->user_param),
1242 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1244 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1246 /* num_msix_vectors_vf needs to minus irq0 */
1247 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1248 vsi->user_param + (msix_vect - 1);
1250 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1252 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1254 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1258 I40E_WRITE_FLUSH(hw);
1262 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1264 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1265 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1266 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1267 uint16_t msix_vect = vsi->msix_intr;
1268 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1269 uint16_t queue_idx = 0;
1274 for (i = 0; i < vsi->nb_qps; i++) {
1275 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1276 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1279 /* INTENA flag is not auto-cleared for interrupt */
1280 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1281 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1282 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1283 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1284 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1286 /* VF bind interrupt */
1287 if (vsi->type == I40E_VSI_SRIOV) {
1288 __vsi_queues_bind_intr(vsi, msix_vect,
1289 vsi->base_queue, vsi->nb_qps);
1293 /* PF & VMDq bind interrupt */
1294 if (rte_intr_dp_is_en(intr_handle)) {
1295 if (vsi->type == I40E_VSI_MAIN) {
1298 } else if (vsi->type == I40E_VSI_VMDQ2) {
1299 struct i40e_vsi *main_vsi =
1300 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1301 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1306 for (i = 0; i < vsi->nb_used_qps; i++) {
1308 if (!rte_intr_allow_others(intr_handle))
1309 /* allow to share MISC_VEC_ID */
1310 msix_vect = I40E_MISC_VEC_ID;
1312 /* no enough msix_vect, map all to one */
1313 __vsi_queues_bind_intr(vsi, msix_vect,
1314 vsi->base_queue + i,
1315 vsi->nb_used_qps - i);
1316 for (; !!record && i < vsi->nb_used_qps; i++)
1317 intr_handle->intr_vec[queue_idx + i] =
1321 /* 1:1 queue/msix_vect mapping */
1322 __vsi_queues_bind_intr(vsi, msix_vect,
1323 vsi->base_queue + i, 1);
1325 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1333 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1335 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1336 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1337 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1338 uint16_t interval = i40e_calc_itr_interval(\
1339 RTE_LIBRTE_I40E_ITR_INTERVAL);
1340 uint16_t msix_intr, i;
1342 if (rte_intr_allow_others(intr_handle))
1343 for (i = 0; i < vsi->nb_msix; i++) {
1344 msix_intr = vsi->msix_intr + i;
1345 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1346 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1347 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1348 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1350 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1353 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1354 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1355 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1356 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1358 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1360 I40E_WRITE_FLUSH(hw);
1364 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1366 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1367 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1368 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1369 uint16_t msix_intr, i;
1371 if (rte_intr_allow_others(intr_handle))
1372 for (i = 0; i < vsi->nb_msix; i++) {
1373 msix_intr = vsi->msix_intr + i;
1374 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1378 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1380 I40E_WRITE_FLUSH(hw);
1383 static inline uint8_t
1384 i40e_parse_link_speed(uint16_t eth_link_speed)
1386 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1388 switch (eth_link_speed) {
1389 case ETH_SPEED_NUM_40G:
1390 link_speed = I40E_LINK_SPEED_40GB;
1392 case ETH_SPEED_NUM_20G:
1393 link_speed = I40E_LINK_SPEED_20GB;
1395 case ETH_SPEED_NUM_10G:
1396 link_speed = I40E_LINK_SPEED_10GB;
1398 case ETH_SPEED_NUM_1G:
1399 link_speed = I40E_LINK_SPEED_1GB;
1401 case ETH_SPEED_NUM_100M:
1402 link_speed = I40E_LINK_SPEED_100MB;
1410 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1411 __rte_unused uint8_t abilities,
1412 __rte_unused uint8_t force_speed)
1414 /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1415 * for the link control limitation of that all link control should be
1416 * handled by firmware. It should follow up if link control will be
1417 * opened to software driver in future firmware versions.
1419 return I40E_SUCCESS;
1423 i40e_apply_link_speed(struct rte_eth_dev *dev)
1426 uint8_t abilities = 0;
1427 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 struct rte_eth_conf *conf = &dev->data->dev_conf;
1430 speed = i40e_parse_link_speed(conf->link_speed);
1431 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1432 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1433 abilities |= I40E_AQ_PHY_AN_ENABLED;
1435 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1437 return i40e_phy_conf_link(hw, abilities, speed);
1441 i40e_dev_start(struct rte_eth_dev *dev)
1443 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445 struct i40e_vsi *main_vsi = pf->main_vsi;
1447 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1448 uint32_t intr_vector = 0;
1450 hw->adapter_stopped = 0;
1452 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1453 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1454 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1455 dev->data->dev_conf.link_duplex,
1456 dev->data->port_id);
1460 rte_intr_disable(intr_handle);
1462 if ((rte_intr_cap_multiple(intr_handle) ||
1463 !RTE_ETH_DEV_SRIOV(dev).active) &&
1464 dev->data->dev_conf.intr_conf.rxq != 0) {
1465 intr_vector = dev->data->nb_rx_queues;
1466 if (rte_intr_efd_enable(intr_handle, intr_vector))
1470 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1471 intr_handle->intr_vec =
1472 rte_zmalloc("intr_vec",
1473 dev->data->nb_rx_queues * sizeof(int),
1475 if (!intr_handle->intr_vec) {
1476 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1477 " intr_vec\n", dev->data->nb_rx_queues);
1482 /* Initialize VSI */
1483 ret = i40e_dev_rxtx_init(pf);
1484 if (ret != I40E_SUCCESS) {
1485 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1489 /* Map queues with MSIX interrupt */
1490 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1491 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1492 i40e_vsi_queues_bind_intr(main_vsi);
1493 i40e_vsi_enable_queues_intr(main_vsi);
1495 /* Map VMDQ VSI queues with MSIX interrupt */
1496 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1497 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1498 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1499 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1502 /* enable FDIR MSIX interrupt */
1503 if (pf->fdir.fdir_vsi) {
1504 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1505 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1508 /* Enable all queues which have been configured */
1509 ret = i40e_dev_switch_queues(pf, TRUE);
1510 if (ret != I40E_SUCCESS) {
1511 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1515 /* Enable receiving broadcast packets */
1516 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1517 if (ret != I40E_SUCCESS)
1518 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1520 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1521 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1523 if (ret != I40E_SUCCESS)
1524 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1527 /* Apply link configure */
1528 ret = i40e_apply_link_speed(dev);
1529 if (I40E_SUCCESS != ret) {
1530 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1534 if (!rte_intr_allow_others(intr_handle)) {
1535 rte_intr_callback_unregister(intr_handle,
1536 i40e_dev_interrupt_handler,
1538 /* configure and enable device interrupt */
1539 i40e_pf_config_irq0(hw, FALSE);
1540 i40e_pf_enable_irq0(hw);
1542 if (dev->data->dev_conf.intr_conf.lsc != 0)
1543 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1544 " no intr multiplex\n");
1547 /* enable uio intr after callback register */
1548 rte_intr_enable(intr_handle);
1550 return I40E_SUCCESS;
1553 i40e_dev_switch_queues(pf, FALSE);
1554 i40e_dev_clear_queues(dev);
1560 i40e_dev_stop(struct rte_eth_dev *dev)
1562 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1563 struct i40e_vsi *main_vsi = pf->main_vsi;
1564 struct i40e_mirror_rule *p_mirror;
1565 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1568 /* Disable all queues */
1569 i40e_dev_switch_queues(pf, FALSE);
1571 /* un-map queues with interrupt registers */
1572 i40e_vsi_disable_queues_intr(main_vsi);
1573 i40e_vsi_queues_unbind_intr(main_vsi);
1575 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1576 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1577 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1580 if (pf->fdir.fdir_vsi) {
1581 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1582 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1584 /* Clear all queues and release memory */
1585 i40e_dev_clear_queues(dev);
1588 i40e_dev_set_link_down(dev);
1590 /* Remove all mirror rules */
1591 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1592 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1595 pf->nb_mirror_rule = 0;
1597 if (!rte_intr_allow_others(intr_handle))
1598 /* resume to the default handler */
1599 rte_intr_callback_register(intr_handle,
1600 i40e_dev_interrupt_handler,
1603 /* Clean datapath event and queue/vec mapping */
1604 rte_intr_efd_disable(intr_handle);
1605 if (intr_handle->intr_vec) {
1606 rte_free(intr_handle->intr_vec);
1607 intr_handle->intr_vec = NULL;
1612 i40e_dev_close(struct rte_eth_dev *dev)
1614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1619 PMD_INIT_FUNC_TRACE();
1622 hw->adapter_stopped = 1;
1623 i40e_dev_free_queues(dev);
1625 /* Disable interrupt */
1626 i40e_pf_disable_irq0(hw);
1627 rte_intr_disable(&(dev->pci_dev->intr_handle));
1629 /* shutdown and destroy the HMC */
1630 i40e_shutdown_lan_hmc(hw);
1632 /* release all the existing VSIs and VEBs */
1633 i40e_fdir_teardown(pf);
1634 i40e_vsi_release(pf->main_vsi);
1636 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1637 i40e_vsi_release(pf->vmdq[i].vsi);
1638 pf->vmdq[i].vsi = NULL;
1644 /* shutdown the adminq */
1645 i40e_aq_queue_shutdown(hw, true);
1646 i40e_shutdown_adminq(hw);
1648 i40e_res_pool_destroy(&pf->qp_pool);
1649 i40e_res_pool_destroy(&pf->msix_pool);
1651 /* force a PF reset to clean anything leftover */
1652 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1653 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1654 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1655 I40E_WRITE_FLUSH(hw);
1659 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1661 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1662 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663 struct i40e_vsi *vsi = pf->main_vsi;
1666 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1668 if (status != I40E_SUCCESS)
1669 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1671 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1673 if (status != I40E_SUCCESS)
1674 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1679 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1681 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1682 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683 struct i40e_vsi *vsi = pf->main_vsi;
1686 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1688 if (status != I40E_SUCCESS)
1689 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1691 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1693 if (status != I40E_SUCCESS)
1694 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1698 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1700 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1701 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1702 struct i40e_vsi *vsi = pf->main_vsi;
1705 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1706 if (ret != I40E_SUCCESS)
1707 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1711 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1713 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1714 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715 struct i40e_vsi *vsi = pf->main_vsi;
1718 if (dev->data->promiscuous == 1)
1719 return; /* must remain in all_multicast mode */
1721 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1722 vsi->seid, FALSE, NULL);
1723 if (ret != I40E_SUCCESS)
1724 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1728 * Set device link up.
1731 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1733 /* re-apply link speed setting */
1734 return i40e_apply_link_speed(dev);
1738 * Set device link down.
1741 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1743 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1744 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747 return i40e_phy_conf_link(hw, abilities, speed);
1751 i40e_dev_link_update(struct rte_eth_dev *dev,
1752 int wait_to_complete)
1754 #define CHECK_INTERVAL 100 /* 100ms */
1755 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757 struct i40e_link_status link_status;
1758 struct rte_eth_link link, old;
1760 unsigned rep_cnt = MAX_REPEAT_TIME;
1762 memset(&link, 0, sizeof(link));
1763 memset(&old, 0, sizeof(old));
1764 memset(&link_status, 0, sizeof(link_status));
1765 rte_i40e_dev_atomic_read_link_status(dev, &old);
1768 /* Get link status information from hardware */
1769 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1770 if (status != I40E_SUCCESS) {
1771 link.link_speed = ETH_SPEED_NUM_100M;
1772 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1773 PMD_DRV_LOG(ERR, "Failed to get link info");
1777 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1778 if (!wait_to_complete)
1781 rte_delay_ms(CHECK_INTERVAL);
1782 } while (!link.link_status && rep_cnt--);
1784 if (!link.link_status)
1787 /* i40e uses full duplex only */
1788 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1790 /* Parse the link status */
1791 switch (link_status.link_speed) {
1792 case I40E_LINK_SPEED_100MB:
1793 link.link_speed = ETH_SPEED_NUM_100M;
1795 case I40E_LINK_SPEED_1GB:
1796 link.link_speed = ETH_SPEED_NUM_1G;
1798 case I40E_LINK_SPEED_10GB:
1799 link.link_speed = ETH_SPEED_NUM_10G;
1801 case I40E_LINK_SPEED_20GB:
1802 link.link_speed = ETH_SPEED_NUM_20G;
1804 case I40E_LINK_SPEED_40GB:
1805 link.link_speed = ETH_SPEED_NUM_40G;
1808 link.link_speed = ETH_SPEED_NUM_100M;
1813 rte_i40e_dev_atomic_write_link_status(dev, &link);
1814 if (link.link_status == old.link_status)
1820 /* Get all the statistics of a VSI */
1822 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1824 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1825 struct i40e_eth_stats *nes = &vsi->eth_stats;
1826 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1827 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1829 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1830 vsi->offset_loaded, &oes->rx_bytes,
1832 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1833 vsi->offset_loaded, &oes->rx_unicast,
1835 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1836 vsi->offset_loaded, &oes->rx_multicast,
1837 &nes->rx_multicast);
1838 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1839 vsi->offset_loaded, &oes->rx_broadcast,
1840 &nes->rx_broadcast);
1841 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1842 &oes->rx_discards, &nes->rx_discards);
1843 /* GLV_REPC not supported */
1844 /* GLV_RMPC not supported */
1845 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1846 &oes->rx_unknown_protocol,
1847 &nes->rx_unknown_protocol);
1848 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1849 vsi->offset_loaded, &oes->tx_bytes,
1851 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1852 vsi->offset_loaded, &oes->tx_unicast,
1854 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1855 vsi->offset_loaded, &oes->tx_multicast,
1856 &nes->tx_multicast);
1857 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1858 vsi->offset_loaded, &oes->tx_broadcast,
1859 &nes->tx_broadcast);
1860 /* GLV_TDPC not supported */
1861 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1862 &oes->tx_errors, &nes->tx_errors);
1863 vsi->offset_loaded = true;
1865 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1867 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1868 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1869 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1870 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1871 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1872 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1873 nes->rx_unknown_protocol);
1874 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1875 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1876 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1877 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1878 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1879 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1880 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1885 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1888 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1889 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1891 /* Get statistics of struct i40e_eth_stats */
1892 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1893 I40E_GLPRT_GORCL(hw->port),
1894 pf->offset_loaded, &os->eth.rx_bytes,
1896 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1897 I40E_GLPRT_UPRCL(hw->port),
1898 pf->offset_loaded, &os->eth.rx_unicast,
1899 &ns->eth.rx_unicast);
1900 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1901 I40E_GLPRT_MPRCL(hw->port),
1902 pf->offset_loaded, &os->eth.rx_multicast,
1903 &ns->eth.rx_multicast);
1904 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1905 I40E_GLPRT_BPRCL(hw->port),
1906 pf->offset_loaded, &os->eth.rx_broadcast,
1907 &ns->eth.rx_broadcast);
1908 /* Workaround: CRC size should not be included in byte statistics,
1909 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1911 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1912 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1914 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1915 pf->offset_loaded, &os->eth.rx_discards,
1916 &ns->eth.rx_discards);
1917 /* GLPRT_REPC not supported */
1918 /* GLPRT_RMPC not supported */
1919 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1921 &os->eth.rx_unknown_protocol,
1922 &ns->eth.rx_unknown_protocol);
1923 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1924 I40E_GLPRT_GOTCL(hw->port),
1925 pf->offset_loaded, &os->eth.tx_bytes,
1927 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1928 I40E_GLPRT_UPTCL(hw->port),
1929 pf->offset_loaded, &os->eth.tx_unicast,
1930 &ns->eth.tx_unicast);
1931 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1932 I40E_GLPRT_MPTCL(hw->port),
1933 pf->offset_loaded, &os->eth.tx_multicast,
1934 &ns->eth.tx_multicast);
1935 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1936 I40E_GLPRT_BPTCL(hw->port),
1937 pf->offset_loaded, &os->eth.tx_broadcast,
1938 &ns->eth.tx_broadcast);
1939 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1940 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1941 /* GLPRT_TEPC not supported */
1943 /* additional port specific stats */
1944 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1945 pf->offset_loaded, &os->tx_dropped_link_down,
1946 &ns->tx_dropped_link_down);
1947 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1948 pf->offset_loaded, &os->crc_errors,
1950 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1951 pf->offset_loaded, &os->illegal_bytes,
1952 &ns->illegal_bytes);
1953 /* GLPRT_ERRBC not supported */
1954 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1955 pf->offset_loaded, &os->mac_local_faults,
1956 &ns->mac_local_faults);
1957 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1958 pf->offset_loaded, &os->mac_remote_faults,
1959 &ns->mac_remote_faults);
1960 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1961 pf->offset_loaded, &os->rx_length_errors,
1962 &ns->rx_length_errors);
1963 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1964 pf->offset_loaded, &os->link_xon_rx,
1966 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1967 pf->offset_loaded, &os->link_xoff_rx,
1969 for (i = 0; i < 8; i++) {
1970 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1972 &os->priority_xon_rx[i],
1973 &ns->priority_xon_rx[i]);
1974 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1976 &os->priority_xoff_rx[i],
1977 &ns->priority_xoff_rx[i]);
1979 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1980 pf->offset_loaded, &os->link_xon_tx,
1982 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1983 pf->offset_loaded, &os->link_xoff_tx,
1985 for (i = 0; i < 8; i++) {
1986 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1988 &os->priority_xon_tx[i],
1989 &ns->priority_xon_tx[i]);
1990 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1992 &os->priority_xoff_tx[i],
1993 &ns->priority_xoff_tx[i]);
1994 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1996 &os->priority_xon_2_xoff[i],
1997 &ns->priority_xon_2_xoff[i]);
1999 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2000 I40E_GLPRT_PRC64L(hw->port),
2001 pf->offset_loaded, &os->rx_size_64,
2003 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2004 I40E_GLPRT_PRC127L(hw->port),
2005 pf->offset_loaded, &os->rx_size_127,
2007 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2008 I40E_GLPRT_PRC255L(hw->port),
2009 pf->offset_loaded, &os->rx_size_255,
2011 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2012 I40E_GLPRT_PRC511L(hw->port),
2013 pf->offset_loaded, &os->rx_size_511,
2015 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2016 I40E_GLPRT_PRC1023L(hw->port),
2017 pf->offset_loaded, &os->rx_size_1023,
2019 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2020 I40E_GLPRT_PRC1522L(hw->port),
2021 pf->offset_loaded, &os->rx_size_1522,
2023 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2024 I40E_GLPRT_PRC9522L(hw->port),
2025 pf->offset_loaded, &os->rx_size_big,
2027 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2028 pf->offset_loaded, &os->rx_undersize,
2030 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2031 pf->offset_loaded, &os->rx_fragments,
2033 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2034 pf->offset_loaded, &os->rx_oversize,
2036 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2037 pf->offset_loaded, &os->rx_jabber,
2039 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2040 I40E_GLPRT_PTC64L(hw->port),
2041 pf->offset_loaded, &os->tx_size_64,
2043 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2044 I40E_GLPRT_PTC127L(hw->port),
2045 pf->offset_loaded, &os->tx_size_127,
2047 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2048 I40E_GLPRT_PTC255L(hw->port),
2049 pf->offset_loaded, &os->tx_size_255,
2051 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2052 I40E_GLPRT_PTC511L(hw->port),
2053 pf->offset_loaded, &os->tx_size_511,
2055 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2056 I40E_GLPRT_PTC1023L(hw->port),
2057 pf->offset_loaded, &os->tx_size_1023,
2059 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2060 I40E_GLPRT_PTC1522L(hw->port),
2061 pf->offset_loaded, &os->tx_size_1522,
2063 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2064 I40E_GLPRT_PTC9522L(hw->port),
2065 pf->offset_loaded, &os->tx_size_big,
2067 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2069 &os->fd_sb_match, &ns->fd_sb_match);
2070 /* GLPRT_MSPDC not supported */
2071 /* GLPRT_XEC not supported */
2073 pf->offset_loaded = true;
2076 i40e_update_vsi_stats(pf->main_vsi);
2079 /* Get all statistics of a port */
2081 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2083 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2084 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2088 /* call read registers - updates values, now write them to struct */
2089 i40e_read_stats_registers(pf, hw);
2091 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2092 pf->main_vsi->eth_stats.rx_multicast +
2093 pf->main_vsi->eth_stats.rx_broadcast -
2094 pf->main_vsi->eth_stats.rx_discards;
2095 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2096 pf->main_vsi->eth_stats.tx_multicast +
2097 pf->main_vsi->eth_stats.tx_broadcast;
2098 stats->ibytes = ns->eth.rx_bytes;
2099 stats->obytes = ns->eth.tx_bytes;
2100 stats->oerrors = ns->eth.tx_errors +
2101 pf->main_vsi->eth_stats.tx_errors;
2102 stats->imcasts = pf->main_vsi->eth_stats.rx_multicast;
2105 stats->imissed = ns->eth.rx_discards +
2106 pf->main_vsi->eth_stats.rx_discards;
2107 stats->ierrors = ns->crc_errors +
2108 ns->rx_length_errors + ns->rx_undersize +
2109 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2111 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2112 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2113 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2114 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2115 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2116 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2117 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2118 ns->eth.rx_unknown_protocol);
2119 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2120 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2121 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2122 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2123 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2124 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2126 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2127 ns->tx_dropped_link_down);
2128 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2129 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2131 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2132 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2133 ns->mac_local_faults);
2134 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2135 ns->mac_remote_faults);
2136 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2137 ns->rx_length_errors);
2138 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2139 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2140 for (i = 0; i < 8; i++) {
2141 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2142 i, ns->priority_xon_rx[i]);
2143 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2144 i, ns->priority_xoff_rx[i]);
2146 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2147 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2148 for (i = 0; i < 8; i++) {
2149 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2150 i, ns->priority_xon_tx[i]);
2151 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2152 i, ns->priority_xoff_tx[i]);
2153 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2154 i, ns->priority_xon_2_xoff[i]);
2156 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2157 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2158 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2159 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2160 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2161 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2162 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2163 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2164 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2165 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2166 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2167 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2168 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2169 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2170 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2171 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2172 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2173 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2174 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2175 ns->mac_short_packet_dropped);
2176 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2177 ns->checksum_error);
2178 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2179 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2182 /* Reset the statistics */
2184 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2186 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189 /* Mark PF and VSI stats to update the offset, aka "reset" */
2190 pf->offset_loaded = false;
2192 pf->main_vsi->offset_loaded = false;
2194 /* read the stats, reading current register values into offset */
2195 i40e_read_stats_registers(pf, hw);
2199 i40e_xstats_calc_num(void)
2201 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2202 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2203 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2207 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2210 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2211 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212 unsigned i, count, prio;
2213 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2215 count = i40e_xstats_calc_num();
2219 i40e_read_stats_registers(pf, hw);
2226 /* Get stats from i40e_eth_stats struct */
2227 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2228 snprintf(xstats[count].name, sizeof(xstats[count].name),
2229 "%s", rte_i40e_stats_strings[i].name);
2230 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2231 rte_i40e_stats_strings[i].offset);
2235 /* Get individiual stats from i40e_hw_port struct */
2236 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2237 snprintf(xstats[count].name, sizeof(xstats[count].name),
2238 "%s", rte_i40e_hw_port_strings[i].name);
2239 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2240 rte_i40e_hw_port_strings[i].offset);
2244 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2245 for (prio = 0; prio < 8; prio++) {
2246 snprintf(xstats[count].name,
2247 sizeof(xstats[count].name),
2248 "rx_priority%u_%s", prio,
2249 rte_i40e_rxq_prio_strings[i].name);
2250 xstats[count].value =
2251 *(uint64_t *)(((char *)hw_stats) +
2252 rte_i40e_rxq_prio_strings[i].offset +
2253 (sizeof(uint64_t) * prio));
2258 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2259 for (prio = 0; prio < 8; prio++) {
2260 snprintf(xstats[count].name,
2261 sizeof(xstats[count].name),
2262 "tx_priority%u_%s", prio,
2263 rte_i40e_txq_prio_strings[i].name);
2264 xstats[count].value =
2265 *(uint64_t *)(((char *)hw_stats) +
2266 rte_i40e_txq_prio_strings[i].offset +
2267 (sizeof(uint64_t) * prio));
2276 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2277 __rte_unused uint16_t queue_id,
2278 __rte_unused uint8_t stat_idx,
2279 __rte_unused uint8_t is_rx)
2281 PMD_INIT_FUNC_TRACE();
2287 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2289 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2290 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291 struct i40e_vsi *vsi = pf->main_vsi;
2293 dev_info->max_rx_queues = vsi->nb_qps;
2294 dev_info->max_tx_queues = vsi->nb_qps;
2295 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2296 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2297 dev_info->max_mac_addrs = vsi->max_macaddrs;
2298 dev_info->max_vfs = dev->pci_dev->max_vfs;
2299 dev_info->rx_offload_capa =
2300 DEV_RX_OFFLOAD_VLAN_STRIP |
2301 DEV_RX_OFFLOAD_QINQ_STRIP |
2302 DEV_RX_OFFLOAD_IPV4_CKSUM |
2303 DEV_RX_OFFLOAD_UDP_CKSUM |
2304 DEV_RX_OFFLOAD_TCP_CKSUM;
2305 dev_info->tx_offload_capa =
2306 DEV_TX_OFFLOAD_VLAN_INSERT |
2307 DEV_TX_OFFLOAD_QINQ_INSERT |
2308 DEV_TX_OFFLOAD_IPV4_CKSUM |
2309 DEV_TX_OFFLOAD_UDP_CKSUM |
2310 DEV_TX_OFFLOAD_TCP_CKSUM |
2311 DEV_TX_OFFLOAD_SCTP_CKSUM |
2312 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2313 DEV_TX_OFFLOAD_TCP_TSO;
2314 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2316 dev_info->reta_size = pf->hash_lut_size;
2317 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2319 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2321 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2322 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2323 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2325 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2329 dev_info->default_txconf = (struct rte_eth_txconf) {
2331 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2332 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2333 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2335 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2336 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2337 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2338 ETH_TXQ_FLAGS_NOOFFLOADS,
2341 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2342 .nb_max = I40E_MAX_RING_DESC,
2343 .nb_min = I40E_MIN_RING_DESC,
2344 .nb_align = I40E_ALIGN_RING_DESC,
2347 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2348 .nb_max = I40E_MAX_RING_DESC,
2349 .nb_min = I40E_MIN_RING_DESC,
2350 .nb_align = I40E_ALIGN_RING_DESC,
2353 if (pf->flags & I40E_FLAG_VMDQ) {
2354 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2355 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2356 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2357 pf->max_nb_vmdq_vsi;
2358 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2359 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2360 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2363 if (i40e_is_40G_device(hw->device_id))
2365 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2368 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2372 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2374 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2375 struct i40e_vsi *vsi = pf->main_vsi;
2376 PMD_INIT_FUNC_TRACE();
2379 return i40e_vsi_add_vlan(vsi, vlan_id);
2381 return i40e_vsi_delete_vlan(vsi, vlan_id);
2385 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2386 enum rte_vlan_type vlan_type,
2389 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390 uint64_t reg_r = 0, reg_w = 0;
2391 uint16_t reg_id = 0;
2394 switch (vlan_type) {
2395 case ETH_VLAN_TYPE_OUTER:
2398 case ETH_VLAN_TYPE_INNER:
2403 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2406 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2408 if (ret != I40E_SUCCESS) {
2409 PMD_DRV_LOG(ERR, "Fail to debug read from "
2410 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2414 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2415 "0x%08"PRIx64"", reg_id, reg_r);
2417 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2418 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2419 if (reg_r == reg_w) {
2421 PMD_DRV_LOG(DEBUG, "No need to write");
2425 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2427 if (ret != I40E_SUCCESS) {
2429 PMD_DRV_LOG(ERR, "Fail to debug write to "
2430 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2433 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2434 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2440 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2442 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2443 struct i40e_vsi *vsi = pf->main_vsi;
2445 if (mask & ETH_VLAN_FILTER_MASK) {
2446 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2447 i40e_vsi_config_vlan_filter(vsi, TRUE);
2449 i40e_vsi_config_vlan_filter(vsi, FALSE);
2452 if (mask & ETH_VLAN_STRIP_MASK) {
2453 /* Enable or disable VLAN stripping */
2454 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2455 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2457 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2460 if (mask & ETH_VLAN_EXTEND_MASK) {
2461 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2462 i40e_vsi_config_double_vlan(vsi, TRUE);
2464 i40e_vsi_config_double_vlan(vsi, FALSE);
2469 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2470 __rte_unused uint16_t queue,
2471 __rte_unused int on)
2473 PMD_INIT_FUNC_TRACE();
2477 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2479 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2480 struct i40e_vsi *vsi = pf->main_vsi;
2481 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2482 struct i40e_vsi_vlan_pvid_info info;
2484 memset(&info, 0, sizeof(info));
2487 info.config.pvid = pvid;
2489 info.config.reject.tagged =
2490 data->dev_conf.txmode.hw_vlan_reject_tagged;
2491 info.config.reject.untagged =
2492 data->dev_conf.txmode.hw_vlan_reject_untagged;
2495 return i40e_vsi_vlan_pvid_set(vsi, &info);
2499 i40e_dev_led_on(struct rte_eth_dev *dev)
2501 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2502 uint32_t mode = i40e_led_get(hw);
2505 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2511 i40e_dev_led_off(struct rte_eth_dev *dev)
2513 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514 uint32_t mode = i40e_led_get(hw);
2517 i40e_led_set(hw, 0, false);
2523 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2525 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2526 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2528 fc_conf->pause_time = pf->fc_conf.pause_time;
2529 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2530 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2532 /* Return current mode according to actual setting*/
2533 switch (hw->fc.current_mode) {
2535 fc_conf->mode = RTE_FC_FULL;
2537 case I40E_FC_TX_PAUSE:
2538 fc_conf->mode = RTE_FC_TX_PAUSE;
2540 case I40E_FC_RX_PAUSE:
2541 fc_conf->mode = RTE_FC_RX_PAUSE;
2545 fc_conf->mode = RTE_FC_NONE;
2552 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2554 uint32_t mflcn_reg, fctrl_reg, reg;
2555 uint32_t max_high_water;
2556 uint8_t i, aq_failure;
2560 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2561 [RTE_FC_NONE] = I40E_FC_NONE,
2562 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2563 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2564 [RTE_FC_FULL] = I40E_FC_FULL
2567 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2569 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2570 if ((fc_conf->high_water > max_high_water) ||
2571 (fc_conf->high_water < fc_conf->low_water)) {
2572 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2573 "High_water must <= %d.", max_high_water);
2577 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2579 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2581 pf->fc_conf.pause_time = fc_conf->pause_time;
2582 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2583 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2585 PMD_INIT_FUNC_TRACE();
2587 /* All the link flow control related enable/disable register
2588 * configuration is handle by the F/W
2590 err = i40e_set_fc(hw, &aq_failure, true);
2594 if (i40e_is_40G_device(hw->device_id)) {
2595 /* Configure flow control refresh threshold,
2596 * the value for stat_tx_pause_refresh_timer[8]
2597 * is used for global pause operation.
2601 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2602 pf->fc_conf.pause_time);
2604 /* configure the timer value included in transmitted pause
2606 * the value for stat_tx_pause_quanta[8] is used for global
2609 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2610 pf->fc_conf.pause_time);
2612 fctrl_reg = I40E_READ_REG(hw,
2613 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2615 if (fc_conf->mac_ctrl_frame_fwd != 0)
2616 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2618 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2620 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2623 /* Configure pause time (2 TCs per register) */
2624 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2625 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2626 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2628 /* Configure flow control refresh threshold value */
2629 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2630 pf->fc_conf.pause_time / 2);
2632 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2634 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2635 *depending on configuration
2637 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2638 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2639 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2641 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2642 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2645 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2648 /* config the water marker both based on the packets and bytes */
2649 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2650 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2651 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2652 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2653 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2654 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2655 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2656 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2658 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2659 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2662 I40E_WRITE_FLUSH(hw);
2668 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2669 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2671 PMD_INIT_FUNC_TRACE();
2676 /* Add a MAC address, and update filters */
2678 i40e_macaddr_add(struct rte_eth_dev *dev,
2679 struct ether_addr *mac_addr,
2680 __rte_unused uint32_t index,
2683 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2684 struct i40e_mac_filter_info mac_filter;
2685 struct i40e_vsi *vsi;
2688 /* If VMDQ not enabled or configured, return */
2689 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2690 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2691 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2696 if (pool > pf->nb_cfg_vmdq_vsi) {
2697 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2698 pool, pf->nb_cfg_vmdq_vsi);
2702 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2703 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2704 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2706 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2711 vsi = pf->vmdq[pool - 1].vsi;
2713 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2714 if (ret != I40E_SUCCESS) {
2715 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2720 /* Remove a MAC address, and update filters */
2722 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2724 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2725 struct i40e_vsi *vsi;
2726 struct rte_eth_dev_data *data = dev->data;
2727 struct ether_addr *macaddr;
2732 macaddr = &(data->mac_addrs[index]);
2734 pool_sel = dev->data->mac_pool_sel[index];
2736 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2737 if (pool_sel & (1ULL << i)) {
2741 /* No VMDQ pool enabled or configured */
2742 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2743 (i > pf->nb_cfg_vmdq_vsi)) {
2744 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2748 vsi = pf->vmdq[i - 1].vsi;
2750 ret = i40e_vsi_delete_mac(vsi, macaddr);
2753 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2760 /* Set perfect match or hash match of MAC and VLAN for a VF */
2762 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2763 struct rte_eth_mac_filter *filter,
2767 struct i40e_mac_filter_info mac_filter;
2768 struct ether_addr old_mac;
2769 struct ether_addr *new_mac;
2770 struct i40e_pf_vf *vf = NULL;
2775 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2778 hw = I40E_PF_TO_HW(pf);
2780 if (filter == NULL) {
2781 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2785 new_mac = &filter->mac_addr;
2787 if (is_zero_ether_addr(new_mac)) {
2788 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2792 vf_id = filter->dst_id;
2794 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2795 PMD_DRV_LOG(ERR, "Invalid argument.");
2798 vf = &pf->vfs[vf_id];
2800 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2801 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2806 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2807 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2809 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2812 mac_filter.filter_type = filter->filter_type;
2813 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2814 if (ret != I40E_SUCCESS) {
2815 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2818 ether_addr_copy(new_mac, &pf->dev_addr);
2820 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2822 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2823 if (ret != I40E_SUCCESS) {
2824 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2828 /* Clear device address as it has been removed */
2829 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2830 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2836 /* MAC filter handle */
2838 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2841 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2842 struct rte_eth_mac_filter *filter;
2843 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2844 int ret = I40E_NOT_SUPPORTED;
2846 filter = (struct rte_eth_mac_filter *)(arg);
2848 switch (filter_op) {
2849 case RTE_ETH_FILTER_NOP:
2852 case RTE_ETH_FILTER_ADD:
2853 i40e_pf_disable_irq0(hw);
2855 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2856 i40e_pf_enable_irq0(hw);
2858 case RTE_ETH_FILTER_DELETE:
2859 i40e_pf_disable_irq0(hw);
2861 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2862 i40e_pf_enable_irq0(hw);
2865 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2866 ret = I40E_ERR_PARAM;
2874 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2876 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2877 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2883 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2884 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2887 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2891 uint32_t *lut_dw = (uint32_t *)lut;
2892 uint16_t i, lut_size_dw = lut_size / 4;
2894 for (i = 0; i < lut_size_dw; i++)
2895 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2902 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2904 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2905 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2911 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2912 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2915 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2919 uint32_t *lut_dw = (uint32_t *)lut;
2920 uint16_t i, lut_size_dw = lut_size / 4;
2922 for (i = 0; i < lut_size_dw; i++)
2923 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2924 I40E_WRITE_FLUSH(hw);
2931 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2932 struct rte_eth_rss_reta_entry64 *reta_conf,
2935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2936 uint16_t i, lut_size = pf->hash_lut_size;
2937 uint16_t idx, shift;
2941 if (reta_size != lut_size ||
2942 reta_size > ETH_RSS_RETA_SIZE_512) {
2943 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2944 "(%d) doesn't match the number hardware can supported "
2945 "(%d)\n", reta_size, lut_size);
2949 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2951 PMD_DRV_LOG(ERR, "No memory can be allocated");
2954 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2957 for (i = 0; i < reta_size; i++) {
2958 idx = i / RTE_RETA_GROUP_SIZE;
2959 shift = i % RTE_RETA_GROUP_SIZE;
2960 if (reta_conf[idx].mask & (1ULL << shift))
2961 lut[i] = reta_conf[idx].reta[shift];
2963 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2972 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2973 struct rte_eth_rss_reta_entry64 *reta_conf,
2976 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2977 uint16_t i, lut_size = pf->hash_lut_size;
2978 uint16_t idx, shift;
2982 if (reta_size != lut_size ||
2983 reta_size > ETH_RSS_RETA_SIZE_512) {
2984 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2985 "(%d) doesn't match the number hardware can supported "
2986 "(%d)\n", reta_size, lut_size);
2990 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2992 PMD_DRV_LOG(ERR, "No memory can be allocated");
2996 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2999 for (i = 0; i < reta_size; i++) {
3000 idx = i / RTE_RETA_GROUP_SIZE;
3001 shift = i % RTE_RETA_GROUP_SIZE;
3002 if (reta_conf[idx].mask & (1ULL << shift))
3003 reta_conf[idx].reta[shift] = lut[i];
3013 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3014 * @hw: pointer to the HW structure
3015 * @mem: pointer to mem struct to fill out
3016 * @size: size of memory requested
3017 * @alignment: what to align the allocation to
3019 enum i40e_status_code
3020 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3021 struct i40e_dma_mem *mem,
3025 const struct rte_memzone *mz = NULL;
3026 char z_name[RTE_MEMZONE_NAMESIZE];
3029 return I40E_ERR_PARAM;
3031 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3032 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3033 alignment, RTE_PGSIZE_2M);
3035 return I40E_ERR_NO_MEMORY;
3039 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3040 mem->zone = (const void *)mz;
3041 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3042 "%"PRIu64, mz->name, mem->pa);
3044 return I40E_SUCCESS;
3048 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3049 * @hw: pointer to the HW structure
3050 * @mem: ptr to mem struct to free
3052 enum i40e_status_code
3053 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3054 struct i40e_dma_mem *mem)
3057 return I40E_ERR_PARAM;
3059 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3060 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3062 rte_memzone_free((const struct rte_memzone *)mem->zone);
3067 return I40E_SUCCESS;
3071 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3072 * @hw: pointer to the HW structure
3073 * @mem: pointer to mem struct to fill out
3074 * @size: size of memory requested
3076 enum i40e_status_code
3077 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3078 struct i40e_virt_mem *mem,
3082 return I40E_ERR_PARAM;
3085 mem->va = rte_zmalloc("i40e", size, 0);
3088 return I40E_SUCCESS;
3090 return I40E_ERR_NO_MEMORY;
3094 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3095 * @hw: pointer to the HW structure
3096 * @mem: pointer to mem struct to free
3098 enum i40e_status_code
3099 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3100 struct i40e_virt_mem *mem)
3103 return I40E_ERR_PARAM;
3108 return I40E_SUCCESS;
3112 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3114 rte_spinlock_init(&sp->spinlock);
3118 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3120 rte_spinlock_lock(&sp->spinlock);
3124 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3126 rte_spinlock_unlock(&sp->spinlock);
3130 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3136 * Get the hardware capabilities, which will be parsed
3137 * and saved into struct i40e_hw.
3140 i40e_get_cap(struct i40e_hw *hw)
3142 struct i40e_aqc_list_capabilities_element_resp *buf;
3143 uint16_t len, size = 0;
3146 /* Calculate a huge enough buff for saving response data temporarily */
3147 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3148 I40E_MAX_CAP_ELE_NUM;
3149 buf = rte_zmalloc("i40e", len, 0);
3151 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3152 return I40E_ERR_NO_MEMORY;
3155 /* Get, parse the capabilities and save it to hw */
3156 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3157 i40e_aqc_opc_list_func_capabilities, NULL);
3158 if (ret != I40E_SUCCESS)
3159 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3161 /* Free the temporary buffer after being used */
3168 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3170 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3172 uint16_t qp_count = 0, vsi_count = 0;
3174 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3175 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3178 /* Add the parameter init for LFC */
3179 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3180 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3181 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3183 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3184 pf->max_num_vsi = hw->func_caps.num_vsis;
3185 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3186 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3187 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3189 /* FDir queue/VSI allocation */
3190 pf->fdir_qp_offset = 0;
3191 if (hw->func_caps.fd) {
3192 pf->flags |= I40E_FLAG_FDIR;
3193 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3195 pf->fdir_nb_qps = 0;
3197 qp_count += pf->fdir_nb_qps;
3200 /* LAN queue/VSI allocation */
3201 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3202 if (!hw->func_caps.rss) {
3205 pf->flags |= I40E_FLAG_RSS;
3206 if (hw->mac.type == I40E_MAC_X722)
3207 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3208 pf->lan_nb_qps = pf->lan_nb_qp_max;
3210 qp_count += pf->lan_nb_qps;
3213 /* VF queue/VSI allocation */
3214 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3215 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3216 pf->flags |= I40E_FLAG_SRIOV;
3217 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3218 pf->vf_num = dev->pci_dev->max_vfs;
3219 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3220 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3221 pf->vf_nb_qps * pf->vf_num);
3226 qp_count += pf->vf_nb_qps * pf->vf_num;
3227 vsi_count += pf->vf_num;
3229 /* VMDq queue/VSI allocation */
3230 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3231 pf->vmdq_nb_qps = 0;
3232 pf->max_nb_vmdq_vsi = 0;
3233 if (hw->func_caps.vmdq) {
3234 if (qp_count < hw->func_caps.num_tx_qp &&
3235 vsi_count < hw->func_caps.num_vsis) {
3236 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3237 qp_count) / pf->vmdq_nb_qp_max;
3239 /* Limit the maximum number of VMDq vsi to the maximum
3240 * ethdev can support
3242 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3243 hw->func_caps.num_vsis - vsi_count);
3244 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3246 if (pf->max_nb_vmdq_vsi) {
3247 pf->flags |= I40E_FLAG_VMDQ;
3248 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3249 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3250 "per VMDQ VSI, in total %u queues",
3251 pf->max_nb_vmdq_vsi,
3252 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3253 pf->max_nb_vmdq_vsi);
3255 PMD_DRV_LOG(INFO, "No enough queues left for "
3259 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3262 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3263 vsi_count += pf->max_nb_vmdq_vsi;
3265 if (hw->func_caps.dcb)
3266 pf->flags |= I40E_FLAG_DCB;
3268 if (qp_count > hw->func_caps.num_tx_qp) {
3269 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3270 "the hardware maximum %u", qp_count,
3271 hw->func_caps.num_tx_qp);
3274 if (vsi_count > hw->func_caps.num_vsis) {
3275 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3276 "the hardware maximum %u", vsi_count,
3277 hw->func_caps.num_vsis);
3285 i40e_pf_get_switch_config(struct i40e_pf *pf)
3287 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3288 struct i40e_aqc_get_switch_config_resp *switch_config;
3289 struct i40e_aqc_switch_config_element_resp *element;
3290 uint16_t start_seid = 0, num_reported;
3293 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3294 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3295 if (!switch_config) {
3296 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3300 /* Get the switch configurations */
3301 ret = i40e_aq_get_switch_config(hw, switch_config,
3302 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3303 if (ret != I40E_SUCCESS) {
3304 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3307 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3308 if (num_reported != 1) { /* The number should be 1 */
3309 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3313 /* Parse the switch configuration elements */
3314 element = &(switch_config->element[0]);
3315 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3316 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3317 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3319 PMD_DRV_LOG(INFO, "Unknown element type");
3322 rte_free(switch_config);
3328 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3331 struct pool_entry *entry;
3333 if (pool == NULL || num == 0)
3336 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3337 if (entry == NULL) {
3338 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3342 /* queue heap initialize */
3343 pool->num_free = num;
3344 pool->num_alloc = 0;
3346 LIST_INIT(&pool->alloc_list);
3347 LIST_INIT(&pool->free_list);
3349 /* Initialize element */
3353 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3358 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3360 struct pool_entry *entry, *next_entry;
3365 for (entry = LIST_FIRST(&pool->alloc_list);
3366 entry && (next_entry = LIST_NEXT(entry, next), 1);
3367 entry = next_entry) {
3368 LIST_REMOVE(entry, next);
3372 for (entry = LIST_FIRST(&pool->free_list);
3373 entry && (next_entry = LIST_NEXT(entry, next), 1);
3374 entry = next_entry) {
3375 LIST_REMOVE(entry, next);
3380 pool->num_alloc = 0;
3382 LIST_INIT(&pool->alloc_list);
3383 LIST_INIT(&pool->free_list);
3387 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3390 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3391 uint32_t pool_offset;
3395 PMD_DRV_LOG(ERR, "Invalid parameter");
3399 pool_offset = base - pool->base;
3400 /* Lookup in alloc list */
3401 LIST_FOREACH(entry, &pool->alloc_list, next) {
3402 if (entry->base == pool_offset) {
3403 valid_entry = entry;
3404 LIST_REMOVE(entry, next);
3409 /* Not find, return */
3410 if (valid_entry == NULL) {
3411 PMD_DRV_LOG(ERR, "Failed to find entry");
3416 * Found it, move it to free list and try to merge.
3417 * In order to make merge easier, always sort it by qbase.
3418 * Find adjacent prev and last entries.
3421 LIST_FOREACH(entry, &pool->free_list, next) {
3422 if (entry->base > valid_entry->base) {
3430 /* Try to merge with next one*/
3432 /* Merge with next one */
3433 if (valid_entry->base + valid_entry->len == next->base) {
3434 next->base = valid_entry->base;
3435 next->len += valid_entry->len;
3436 rte_free(valid_entry);
3443 /* Merge with previous one */
3444 if (prev->base + prev->len == valid_entry->base) {
3445 prev->len += valid_entry->len;
3446 /* If it merge with next one, remove next node */
3448 LIST_REMOVE(valid_entry, next);
3449 rte_free(valid_entry);
3451 rte_free(valid_entry);
3457 /* Not find any entry to merge, insert */
3460 LIST_INSERT_AFTER(prev, valid_entry, next);
3461 else if (next != NULL)
3462 LIST_INSERT_BEFORE(next, valid_entry, next);
3463 else /* It's empty list, insert to head */
3464 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3467 pool->num_free += valid_entry->len;
3468 pool->num_alloc -= valid_entry->len;
3474 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3477 struct pool_entry *entry, *valid_entry;
3479 if (pool == NULL || num == 0) {
3480 PMD_DRV_LOG(ERR, "Invalid parameter");
3484 if (pool->num_free < num) {
3485 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3486 num, pool->num_free);
3491 /* Lookup in free list and find most fit one */
3492 LIST_FOREACH(entry, &pool->free_list, next) {
3493 if (entry->len >= num) {
3495 if (entry->len == num) {
3496 valid_entry = entry;
3499 if (valid_entry == NULL || valid_entry->len > entry->len)
3500 valid_entry = entry;
3504 /* Not find one to satisfy the request, return */
3505 if (valid_entry == NULL) {
3506 PMD_DRV_LOG(ERR, "No valid entry found");
3510 * The entry have equal queue number as requested,
3511 * remove it from alloc_list.
3513 if (valid_entry->len == num) {
3514 LIST_REMOVE(valid_entry, next);
3517 * The entry have more numbers than requested,
3518 * create a new entry for alloc_list and minus its
3519 * queue base and number in free_list.
3521 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3522 if (entry == NULL) {
3523 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3527 entry->base = valid_entry->base;
3529 valid_entry->base += num;
3530 valid_entry->len -= num;
3531 valid_entry = entry;
3534 /* Insert it into alloc list, not sorted */
3535 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3537 pool->num_free -= valid_entry->len;
3538 pool->num_alloc += valid_entry->len;
3540 return valid_entry->base + pool->base;
3544 * bitmap_is_subset - Check whether src2 is subset of src1
3547 bitmap_is_subset(uint8_t src1, uint8_t src2)
3549 return !((src1 ^ src2) & src2);
3552 static enum i40e_status_code
3553 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3555 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3557 /* If DCB is not supported, only default TC is supported */
3558 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3559 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3560 return I40E_NOT_SUPPORTED;
3563 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3564 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3565 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3567 return I40E_NOT_SUPPORTED;
3569 return I40E_SUCCESS;
3573 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3574 struct i40e_vsi_vlan_pvid_info *info)
3577 struct i40e_vsi_context ctxt;
3578 uint8_t vlan_flags = 0;
3581 if (vsi == NULL || info == NULL) {
3582 PMD_DRV_LOG(ERR, "invalid parameters");
3583 return I40E_ERR_PARAM;
3587 vsi->info.pvid = info->config.pvid;
3589 * If insert pvid is enabled, only tagged pkts are
3590 * allowed to be sent out.
3592 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3593 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3596 if (info->config.reject.tagged == 0)
3597 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3599 if (info->config.reject.untagged == 0)
3600 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3602 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3603 I40E_AQ_VSI_PVLAN_MODE_MASK);
3604 vsi->info.port_vlan_flags |= vlan_flags;
3605 vsi->info.valid_sections =
3606 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3607 memset(&ctxt, 0, sizeof(ctxt));
3608 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3609 ctxt.seid = vsi->seid;
3611 hw = I40E_VSI_TO_HW(vsi);
3612 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3613 if (ret != I40E_SUCCESS)
3614 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3620 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3622 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3624 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3626 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3627 if (ret != I40E_SUCCESS)
3631 PMD_DRV_LOG(ERR, "seid not valid");
3635 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3636 tc_bw_data.tc_valid_bits = enabled_tcmap;
3637 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3638 tc_bw_data.tc_bw_credits[i] =
3639 (enabled_tcmap & (1 << i)) ? 1 : 0;
3641 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3642 if (ret != I40E_SUCCESS) {
3643 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3647 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3648 sizeof(vsi->info.qs_handle));
3649 return I40E_SUCCESS;
3652 static enum i40e_status_code
3653 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3654 struct i40e_aqc_vsi_properties_data *info,
3655 uint8_t enabled_tcmap)
3657 enum i40e_status_code ret;
3658 int i, total_tc = 0;
3659 uint16_t qpnum_per_tc, bsf, qp_idx;
3661 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3662 if (ret != I40E_SUCCESS)
3665 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3666 if (enabled_tcmap & (1 << i))
3668 vsi->enabled_tc = enabled_tcmap;
3670 /* Number of queues per enabled TC */
3671 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3672 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3673 bsf = rte_bsf32(qpnum_per_tc);
3675 /* Adjust the queue number to actual queues that can be applied */
3676 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3677 vsi->nb_qps = qpnum_per_tc * total_tc;
3680 * Configure TC and queue mapping parameters, for enabled TC,
3681 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3682 * default queue will serve it.
3685 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3686 if (vsi->enabled_tc & (1 << i)) {
3687 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3688 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3689 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3690 qp_idx += qpnum_per_tc;
3692 info->tc_mapping[i] = 0;
3695 /* Associate queue number with VSI */
3696 if (vsi->type == I40E_VSI_SRIOV) {
3697 info->mapping_flags |=
3698 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3699 for (i = 0; i < vsi->nb_qps; i++)
3700 info->queue_mapping[i] =
3701 rte_cpu_to_le_16(vsi->base_queue + i);
3703 info->mapping_flags |=
3704 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3705 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3707 info->valid_sections |=
3708 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3710 return I40E_SUCCESS;
3714 i40e_veb_release(struct i40e_veb *veb)
3716 struct i40e_vsi *vsi;
3719 if (veb == NULL || veb->associate_vsi == NULL)
3722 if (!TAILQ_EMPTY(&veb->head)) {
3723 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3727 vsi = veb->associate_vsi;
3728 hw = I40E_VSI_TO_HW(vsi);
3730 vsi->uplink_seid = veb->uplink_seid;
3731 i40e_aq_delete_element(hw, veb->seid, NULL);
3734 return I40E_SUCCESS;
3738 static struct i40e_veb *
3739 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3741 struct i40e_veb *veb;
3745 if (NULL == pf || vsi == NULL) {
3746 PMD_DRV_LOG(ERR, "veb setup failed, "
3747 "associated VSI shouldn't null");
3750 hw = I40E_PF_TO_HW(pf);
3752 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3754 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3758 veb->associate_vsi = vsi;
3759 TAILQ_INIT(&veb->head);
3760 veb->uplink_seid = vsi->uplink_seid;
3762 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3763 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3765 if (ret != I40E_SUCCESS) {
3766 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3767 hw->aq.asq_last_status);
3771 /* get statistics index */
3772 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3773 &veb->stats_idx, NULL, NULL, NULL);
3774 if (ret != I40E_SUCCESS) {
3775 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3776 hw->aq.asq_last_status);
3780 /* Get VEB bandwidth, to be implemented */
3781 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3782 vsi->uplink_seid = veb->seid;
3791 i40e_vsi_release(struct i40e_vsi *vsi)
3795 struct i40e_vsi_list *vsi_list;
3797 struct i40e_mac_filter *f;
3800 return I40E_SUCCESS;
3802 pf = I40E_VSI_TO_PF(vsi);
3803 hw = I40E_VSI_TO_HW(vsi);
3805 /* VSI has child to attach, release child first */
3807 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3808 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3810 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3812 i40e_veb_release(vsi->veb);
3815 /* Remove all macvlan filters of the VSI */
3816 i40e_vsi_remove_all_macvlan_filter(vsi);
3817 TAILQ_FOREACH(f, &vsi->mac_list, next)
3820 if (vsi->type != I40E_VSI_MAIN) {
3821 /* Remove vsi from parent's sibling list */
3822 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3823 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3824 return I40E_ERR_PARAM;
3826 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3827 &vsi->sib_vsi_list, list);
3829 /* Remove all switch element of the VSI */
3830 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3831 if (ret != I40E_SUCCESS)
3832 PMD_DRV_LOG(ERR, "Failed to delete element");
3834 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3836 if (vsi->type != I40E_VSI_SRIOV)
3837 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3840 return I40E_SUCCESS;
3844 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3846 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3847 struct i40e_aqc_remove_macvlan_element_data def_filter;
3848 struct i40e_mac_filter_info filter;
3851 if (vsi->type != I40E_VSI_MAIN)
3852 return I40E_ERR_CONFIG;
3853 memset(&def_filter, 0, sizeof(def_filter));
3854 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3856 def_filter.vlan_tag = 0;
3857 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3858 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3859 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3860 if (ret != I40E_SUCCESS) {
3861 struct i40e_mac_filter *f;
3862 struct ether_addr *mac;
3864 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3866 /* It needs to add the permanent mac into mac list */
3867 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3869 PMD_DRV_LOG(ERR, "failed to allocate memory");
3870 return I40E_ERR_NO_MEMORY;
3872 mac = &f->mac_info.mac_addr;
3873 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3875 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3876 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3881 (void)rte_memcpy(&filter.mac_addr,
3882 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3883 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3884 return i40e_vsi_add_mac(vsi, &filter);
3888 * i40e_vsi_get_bw_config - Query VSI BW Information
3889 * @vsi: the VSI to be queried
3891 * Returns 0 on success, negative value on failure
3893 static enum i40e_status_code
3894 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3896 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3897 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3898 struct i40e_hw *hw = &vsi->adapter->hw;
3903 memset(&bw_config, 0, sizeof(bw_config));
3904 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3905 if (ret != I40E_SUCCESS) {
3906 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3907 hw->aq.asq_last_status);
3911 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3912 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3913 &ets_sla_config, NULL);
3914 if (ret != I40E_SUCCESS) {
3915 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3916 "configuration %u", hw->aq.asq_last_status);
3920 /* store and print out BW info */
3921 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3922 vsi->bw_info.bw_max = bw_config.max_bw;
3923 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3924 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3925 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3926 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3928 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3929 vsi->bw_info.bw_ets_share_credits[i] =
3930 ets_sla_config.share_credits[i];
3931 vsi->bw_info.bw_ets_credits[i] =
3932 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3933 /* 4 bits per TC, 4th bit is reserved */
3934 vsi->bw_info.bw_ets_max[i] =
3935 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3936 RTE_LEN2MASK(3, uint8_t));
3937 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3938 vsi->bw_info.bw_ets_share_credits[i]);
3939 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3940 vsi->bw_info.bw_ets_credits[i]);
3941 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3942 vsi->bw_info.bw_ets_max[i]);
3945 return I40E_SUCCESS;
3948 /* i40e_enable_pf_lb
3949 * @pf: pointer to the pf structure
3951 * allow loopback on pf
3954 i40e_enable_pf_lb(struct i40e_pf *pf)
3956 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3957 struct i40e_vsi_context ctxt;
3960 /* Use the FW API if FW >= v5.0 */
3961 if (hw->aq.fw_maj_ver < 5) {
3962 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3966 memset(&ctxt, 0, sizeof(ctxt));
3967 ctxt.seid = pf->main_vsi_seid;
3968 ctxt.pf_num = hw->pf_id;
3969 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3971 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3972 ret, hw->aq.asq_last_status);
3975 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3976 ctxt.info.valid_sections =
3977 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3978 ctxt.info.switch_id |=
3979 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3981 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3983 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3984 hw->aq.asq_last_status);
3989 i40e_vsi_setup(struct i40e_pf *pf,
3990 enum i40e_vsi_type type,
3991 struct i40e_vsi *uplink_vsi,
3992 uint16_t user_param)
3994 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3995 struct i40e_vsi *vsi;
3996 struct i40e_mac_filter_info filter;
3998 struct i40e_vsi_context ctxt;
3999 struct ether_addr broadcast =
4000 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4002 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
4003 PMD_DRV_LOG(ERR, "VSI setup failed, "
4004 "VSI link shouldn't be NULL");
4008 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4009 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4010 "uplink VSI should be NULL");
4014 /* If uplink vsi didn't setup VEB, create one first */
4015 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4016 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4018 if (NULL == uplink_vsi->veb) {
4019 PMD_DRV_LOG(ERR, "VEB setup failed");
4022 /* set ALLOWLOOPBACk on pf, when veb is created */
4023 i40e_enable_pf_lb(pf);
4026 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4028 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4031 TAILQ_INIT(&vsi->mac_list);
4033 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4034 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4035 vsi->parent_vsi = uplink_vsi;
4036 vsi->user_param = user_param;
4037 /* Allocate queues */
4038 switch (vsi->type) {
4039 case I40E_VSI_MAIN :
4040 vsi->nb_qps = pf->lan_nb_qps;
4042 case I40E_VSI_SRIOV :
4043 vsi->nb_qps = pf->vf_nb_qps;
4045 case I40E_VSI_VMDQ2:
4046 vsi->nb_qps = pf->vmdq_nb_qps;
4049 vsi->nb_qps = pf->fdir_nb_qps;
4055 * The filter status descriptor is reported in rx queue 0,
4056 * while the tx queue for fdir filter programming has no
4057 * such constraints, can be non-zero queues.
4058 * To simplify it, choose FDIR vsi use queue 0 pair.
4059 * To make sure it will use queue 0 pair, queue allocation
4060 * need be done before this function is called
4062 if (type != I40E_VSI_FDIR) {
4063 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4065 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4069 vsi->base_queue = ret;
4071 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4073 /* VF has MSIX interrupt in VF range, don't allocate here */
4074 if (type == I40E_VSI_MAIN) {
4075 ret = i40e_res_pool_alloc(&pf->msix_pool,
4076 RTE_MIN(vsi->nb_qps,
4077 RTE_MAX_RXTX_INTR_VEC_ID));
4079 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4081 goto fail_queue_alloc;
4083 vsi->msix_intr = ret;
4084 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4085 } else if (type != I40E_VSI_SRIOV) {
4086 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4088 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4089 goto fail_queue_alloc;
4091 vsi->msix_intr = ret;
4099 if (type == I40E_VSI_MAIN) {
4100 /* For main VSI, no need to add since it's default one */
4101 vsi->uplink_seid = pf->mac_seid;
4102 vsi->seid = pf->main_vsi_seid;
4103 /* Bind queues with specific MSIX interrupt */
4105 * Needs 2 interrupt at least, one for misc cause which will
4106 * enabled from OS side, Another for queues binding the
4107 * interrupt from device side only.
4110 /* Get default VSI parameters from hardware */
4111 memset(&ctxt, 0, sizeof(ctxt));
4112 ctxt.seid = vsi->seid;
4113 ctxt.pf_num = hw->pf_id;
4114 ctxt.uplink_seid = vsi->uplink_seid;
4116 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4117 if (ret != I40E_SUCCESS) {
4118 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4119 goto fail_msix_alloc;
4121 (void)rte_memcpy(&vsi->info, &ctxt.info,
4122 sizeof(struct i40e_aqc_vsi_properties_data));
4123 vsi->vsi_id = ctxt.vsi_number;
4124 vsi->info.valid_sections = 0;
4126 /* Configure tc, enabled TC0 only */
4127 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4129 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4130 goto fail_msix_alloc;
4133 /* TC, queue mapping */
4134 memset(&ctxt, 0, sizeof(ctxt));
4135 vsi->info.valid_sections |=
4136 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4137 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4138 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4139 (void)rte_memcpy(&ctxt.info, &vsi->info,
4140 sizeof(struct i40e_aqc_vsi_properties_data));
4141 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4142 I40E_DEFAULT_TCMAP);
4143 if (ret != I40E_SUCCESS) {
4144 PMD_DRV_LOG(ERR, "Failed to configure "
4145 "TC queue mapping");
4146 goto fail_msix_alloc;
4148 ctxt.seid = vsi->seid;
4149 ctxt.pf_num = hw->pf_id;
4150 ctxt.uplink_seid = vsi->uplink_seid;
4153 /* Update VSI parameters */
4154 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4155 if (ret != I40E_SUCCESS) {
4156 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4157 goto fail_msix_alloc;
4160 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4161 sizeof(vsi->info.tc_mapping));
4162 (void)rte_memcpy(&vsi->info.queue_mapping,
4163 &ctxt.info.queue_mapping,
4164 sizeof(vsi->info.queue_mapping));
4165 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4166 vsi->info.valid_sections = 0;
4168 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4172 * Updating default filter settings are necessary to prevent
4173 * reception of tagged packets.
4174 * Some old firmware configurations load a default macvlan
4175 * filter which accepts both tagged and untagged packets.
4176 * The updating is to use a normal filter instead if needed.
4177 * For NVM 4.2.2 or after, the updating is not needed anymore.
4178 * The firmware with correct configurations load the default
4179 * macvlan filter which is expected and cannot be removed.
4181 i40e_update_default_filter_setting(vsi);
4182 i40e_config_qinq(hw, vsi);
4183 } else if (type == I40E_VSI_SRIOV) {
4184 memset(&ctxt, 0, sizeof(ctxt));
4186 * For other VSI, the uplink_seid equals to uplink VSI's
4187 * uplink_seid since they share same VEB
4189 vsi->uplink_seid = uplink_vsi->uplink_seid;
4190 ctxt.pf_num = hw->pf_id;
4191 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4192 ctxt.uplink_seid = vsi->uplink_seid;
4193 ctxt.connection_type = 0x1;
4194 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4196 /* Use the VEB configuration if FW >= v5.0 */
4197 if (hw->aq.fw_maj_ver >= 5) {
4198 /* Configure switch ID */
4199 ctxt.info.valid_sections |=
4200 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4201 ctxt.info.switch_id =
4202 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4205 /* Configure port/vlan */
4206 ctxt.info.valid_sections |=
4207 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4208 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4209 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4210 I40E_DEFAULT_TCMAP);
4211 if (ret != I40E_SUCCESS) {
4212 PMD_DRV_LOG(ERR, "Failed to configure "
4213 "TC queue mapping");
4214 goto fail_msix_alloc;
4216 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4217 ctxt.info.valid_sections |=
4218 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4220 * Since VSI is not created yet, only configure parameter,
4221 * will add vsi below.
4224 i40e_config_qinq(hw, vsi);
4225 } else if (type == I40E_VSI_VMDQ2) {
4226 memset(&ctxt, 0, sizeof(ctxt));
4228 * For other VSI, the uplink_seid equals to uplink VSI's
4229 * uplink_seid since they share same VEB
4231 vsi->uplink_seid = uplink_vsi->uplink_seid;
4232 ctxt.pf_num = hw->pf_id;
4234 ctxt.uplink_seid = vsi->uplink_seid;
4235 ctxt.connection_type = 0x1;
4236 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4238 ctxt.info.valid_sections |=
4239 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4240 /* user_param carries flag to enable loop back */
4242 ctxt.info.switch_id =
4243 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4244 ctxt.info.switch_id |=
4245 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4248 /* Configure port/vlan */
4249 ctxt.info.valid_sections |=
4250 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4251 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4252 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4253 I40E_DEFAULT_TCMAP);
4254 if (ret != I40E_SUCCESS) {
4255 PMD_DRV_LOG(ERR, "Failed to configure "
4256 "TC queue mapping");
4257 goto fail_msix_alloc;
4259 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4260 ctxt.info.valid_sections |=
4261 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4262 } else if (type == I40E_VSI_FDIR) {
4263 memset(&ctxt, 0, sizeof(ctxt));
4264 vsi->uplink_seid = uplink_vsi->uplink_seid;
4265 ctxt.pf_num = hw->pf_id;
4267 ctxt.uplink_seid = vsi->uplink_seid;
4268 ctxt.connection_type = 0x1; /* regular data port */
4269 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4270 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4271 I40E_DEFAULT_TCMAP);
4272 if (ret != I40E_SUCCESS) {
4273 PMD_DRV_LOG(ERR, "Failed to configure "
4274 "TC queue mapping.");
4275 goto fail_msix_alloc;
4277 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4278 ctxt.info.valid_sections |=
4279 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4281 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4282 goto fail_msix_alloc;
4285 if (vsi->type != I40E_VSI_MAIN) {
4286 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4287 if (ret != I40E_SUCCESS) {
4288 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4289 hw->aq.asq_last_status);
4290 goto fail_msix_alloc;
4292 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4293 vsi->info.valid_sections = 0;
4294 vsi->seid = ctxt.seid;
4295 vsi->vsi_id = ctxt.vsi_number;
4296 vsi->sib_vsi_list.vsi = vsi;
4297 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4298 &vsi->sib_vsi_list, list);
4301 /* MAC/VLAN configuration */
4302 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4303 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4305 ret = i40e_vsi_add_mac(vsi, &filter);
4306 if (ret != I40E_SUCCESS) {
4307 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4308 goto fail_msix_alloc;
4311 /* Get VSI BW information */
4312 i40e_vsi_get_bw_config(vsi);
4315 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4317 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4323 /* Configure vlan filter on or off */
4325 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4328 struct i40e_mac_filter *f;
4329 struct i40e_mac_filter_info *mac_filter;
4330 enum rte_mac_filter_type desired_filter;
4331 int ret = I40E_SUCCESS;
4334 /* Filter to match MAC and VLAN */
4335 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4337 /* Filter to match only MAC */
4338 desired_filter = RTE_MAC_PERFECT_MATCH;
4343 mac_filter = rte_zmalloc("mac_filter_info_data",
4344 num * sizeof(*mac_filter), 0);
4345 if (mac_filter == NULL) {
4346 PMD_DRV_LOG(ERR, "failed to allocate memory");
4347 return I40E_ERR_NO_MEMORY;
4352 /* Remove all existing mac */
4353 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4354 mac_filter[i] = f->mac_info;
4355 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4357 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4358 on ? "enable" : "disable");
4364 /* Override with new filter */
4365 for (i = 0; i < num; i++) {
4366 mac_filter[i].filter_type = desired_filter;
4367 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4369 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4370 on ? "enable" : "disable");
4376 rte_free(mac_filter);
4380 /* Configure vlan stripping on or off */
4382 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4384 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4385 struct i40e_vsi_context ctxt;
4387 int ret = I40E_SUCCESS;
4389 /* Check if it has been already on or off */
4390 if (vsi->info.valid_sections &
4391 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4393 if ((vsi->info.port_vlan_flags &
4394 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4395 return 0; /* already on */
4397 if ((vsi->info.port_vlan_flags &
4398 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4399 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4400 return 0; /* already off */
4405 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4407 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4408 vsi->info.valid_sections =
4409 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4410 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4411 vsi->info.port_vlan_flags |= vlan_flags;
4412 ctxt.seid = vsi->seid;
4413 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4414 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4416 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4417 on ? "enable" : "disable");
4423 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4425 struct rte_eth_dev_data *data = dev->data;
4429 /* Apply vlan offload setting */
4430 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4431 i40e_vlan_offload_set(dev, mask);
4433 /* Apply double-vlan setting, not implemented yet */
4435 /* Apply pvid setting */
4436 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4437 data->dev_conf.txmode.hw_vlan_insert_pvid);
4439 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4445 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4447 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4449 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4453 i40e_update_flow_control(struct i40e_hw *hw)
4455 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4456 struct i40e_link_status link_status;
4457 uint32_t rxfc = 0, txfc = 0, reg;
4461 memset(&link_status, 0, sizeof(link_status));
4462 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4463 if (ret != I40E_SUCCESS) {
4464 PMD_DRV_LOG(ERR, "Failed to get link status information");
4465 goto write_reg; /* Disable flow control */
4468 an_info = hw->phy.link_info.an_info;
4469 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4470 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4471 ret = I40E_ERR_NOT_READY;
4472 goto write_reg; /* Disable flow control */
4475 * If link auto negotiation is enabled, flow control needs to
4476 * be configured according to it
4478 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4479 case I40E_LINK_PAUSE_RXTX:
4482 hw->fc.current_mode = I40E_FC_FULL;
4484 case I40E_AQ_LINK_PAUSE_RX:
4486 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4488 case I40E_AQ_LINK_PAUSE_TX:
4490 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4493 hw->fc.current_mode = I40E_FC_NONE;
4498 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4499 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4500 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4501 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4502 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4503 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4510 i40e_pf_setup(struct i40e_pf *pf)
4512 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4513 struct i40e_filter_control_settings settings;
4514 struct i40e_vsi *vsi;
4517 /* Clear all stats counters */
4518 pf->offset_loaded = FALSE;
4519 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4520 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4522 ret = i40e_pf_get_switch_config(pf);
4523 if (ret != I40E_SUCCESS) {
4524 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4527 if (pf->flags & I40E_FLAG_FDIR) {
4528 /* make queue allocated first, let FDIR use queue pair 0*/
4529 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4530 if (ret != I40E_FDIR_QUEUE_ID) {
4531 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4533 pf->flags &= ~I40E_FLAG_FDIR;
4536 /* main VSI setup */
4537 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4539 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4540 return I40E_ERR_NOT_READY;
4544 /* Configure filter control */
4545 memset(&settings, 0, sizeof(settings));
4546 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4547 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4548 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4549 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4551 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4552 hw->func_caps.rss_table_size);
4553 return I40E_ERR_PARAM;
4555 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4556 "size: %u\n", hw->func_caps.rss_table_size);
4557 pf->hash_lut_size = hw->func_caps.rss_table_size;
4559 /* Enable ethtype and macvlan filters */
4560 settings.enable_ethtype = TRUE;
4561 settings.enable_macvlan = TRUE;
4562 ret = i40e_set_filter_control(hw, &settings);
4564 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4567 /* Update flow control according to the auto negotiation */
4568 i40e_update_flow_control(hw);
4570 return I40E_SUCCESS;
4574 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4580 * Set or clear TX Queue Disable flags,
4581 * which is required by hardware.
4583 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4584 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4586 /* Wait until the request is finished */
4587 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4588 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4589 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4590 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4591 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4597 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4598 return I40E_SUCCESS; /* already on, skip next steps */
4600 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4601 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4603 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4604 return I40E_SUCCESS; /* already off, skip next steps */
4605 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4607 /* Write the register */
4608 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4609 /* Check the result */
4610 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4611 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4612 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4614 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4615 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4618 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4619 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4623 /* Check if it is timeout */
4624 if (j >= I40E_CHK_Q_ENA_COUNT) {
4625 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4626 (on ? "enable" : "disable"), q_idx);
4627 return I40E_ERR_TIMEOUT;
4630 return I40E_SUCCESS;
4633 /* Swith on or off the tx queues */
4635 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4637 struct rte_eth_dev_data *dev_data = pf->dev_data;
4638 struct i40e_tx_queue *txq;
4639 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4643 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4644 txq = dev_data->tx_queues[i];
4645 /* Don't operate the queue if not configured or
4646 * if starting only per queue */
4647 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4650 ret = i40e_dev_tx_queue_start(dev, i);
4652 ret = i40e_dev_tx_queue_stop(dev, i);
4653 if ( ret != I40E_SUCCESS)
4657 return I40E_SUCCESS;
4661 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4666 /* Wait until the request is finished */
4667 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4668 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4669 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4670 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4671 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4676 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4677 return I40E_SUCCESS; /* Already on, skip next steps */
4678 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4680 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4681 return I40E_SUCCESS; /* Already off, skip next steps */
4682 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4685 /* Write the register */
4686 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4687 /* Check the result */
4688 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4689 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4690 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4692 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4693 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4696 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4697 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4702 /* Check if it is timeout */
4703 if (j >= I40E_CHK_Q_ENA_COUNT) {
4704 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4705 (on ? "enable" : "disable"), q_idx);
4706 return I40E_ERR_TIMEOUT;
4709 return I40E_SUCCESS;
4711 /* Switch on or off the rx queues */
4713 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4715 struct rte_eth_dev_data *dev_data = pf->dev_data;
4716 struct i40e_rx_queue *rxq;
4717 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4721 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4722 rxq = dev_data->rx_queues[i];
4723 /* Don't operate the queue if not configured or
4724 * if starting only per queue */
4725 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4728 ret = i40e_dev_rx_queue_start(dev, i);
4730 ret = i40e_dev_rx_queue_stop(dev, i);
4731 if (ret != I40E_SUCCESS)
4735 return I40E_SUCCESS;
4738 /* Switch on or off all the rx/tx queues */
4740 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4745 /* enable rx queues before enabling tx queues */
4746 ret = i40e_dev_switch_rx_queues(pf, on);
4748 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4751 ret = i40e_dev_switch_tx_queues(pf, on);
4753 /* Stop tx queues before stopping rx queues */
4754 ret = i40e_dev_switch_tx_queues(pf, on);
4756 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4759 ret = i40e_dev_switch_rx_queues(pf, on);
4765 /* Initialize VSI for TX */
4767 i40e_dev_tx_init(struct i40e_pf *pf)
4769 struct rte_eth_dev_data *data = pf->dev_data;
4771 uint32_t ret = I40E_SUCCESS;
4772 struct i40e_tx_queue *txq;
4774 for (i = 0; i < data->nb_tx_queues; i++) {
4775 txq = data->tx_queues[i];
4776 if (!txq || !txq->q_set)
4778 ret = i40e_tx_queue_init(txq);
4779 if (ret != I40E_SUCCESS)
4782 if (ret == I40E_SUCCESS)
4783 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4789 /* Initialize VSI for RX */
4791 i40e_dev_rx_init(struct i40e_pf *pf)
4793 struct rte_eth_dev_data *data = pf->dev_data;
4794 int ret = I40E_SUCCESS;
4796 struct i40e_rx_queue *rxq;
4798 i40e_pf_config_mq_rx(pf);
4799 for (i = 0; i < data->nb_rx_queues; i++) {
4800 rxq = data->rx_queues[i];
4801 if (!rxq || !rxq->q_set)
4804 ret = i40e_rx_queue_init(rxq);
4805 if (ret != I40E_SUCCESS) {
4806 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4811 if (ret == I40E_SUCCESS)
4812 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4819 i40e_dev_rxtx_init(struct i40e_pf *pf)
4823 err = i40e_dev_tx_init(pf);
4825 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4828 err = i40e_dev_rx_init(pf);
4830 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4838 i40e_vmdq_setup(struct rte_eth_dev *dev)
4840 struct rte_eth_conf *conf = &dev->data->dev_conf;
4841 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4842 int i, err, conf_vsis, j, loop;
4843 struct i40e_vsi *vsi;
4844 struct i40e_vmdq_info *vmdq_info;
4845 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4846 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4849 * Disable interrupt to avoid message from VF. Furthermore, it will
4850 * avoid race condition in VSI creation/destroy.
4852 i40e_pf_disable_irq0(hw);
4854 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4855 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4859 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4860 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4861 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4862 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4863 pf->max_nb_vmdq_vsi);
4867 if (pf->vmdq != NULL) {
4868 PMD_INIT_LOG(INFO, "VMDQ already configured");
4872 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4873 sizeof(*vmdq_info) * conf_vsis, 0);
4875 if (pf->vmdq == NULL) {
4876 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4880 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4882 /* Create VMDQ VSI */
4883 for (i = 0; i < conf_vsis; i++) {
4884 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4885 vmdq_conf->enable_loop_back);
4887 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4891 vmdq_info = &pf->vmdq[i];
4893 vmdq_info->vsi = vsi;
4895 pf->nb_cfg_vmdq_vsi = conf_vsis;
4897 /* Configure Vlan */
4898 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4899 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4900 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4901 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4902 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4903 vmdq_conf->pool_map[i].vlan_id, j);
4905 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4906 vmdq_conf->pool_map[i].vlan_id);
4908 PMD_INIT_LOG(ERR, "Failed to add vlan");
4916 i40e_pf_enable_irq0(hw);
4921 for (i = 0; i < conf_vsis; i++)
4922 if (pf->vmdq[i].vsi == NULL)
4925 i40e_vsi_release(pf->vmdq[i].vsi);
4929 i40e_pf_enable_irq0(hw);
4934 i40e_stat_update_32(struct i40e_hw *hw,
4942 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4946 if (new_data >= *offset)
4947 *stat = (uint64_t)(new_data - *offset);
4949 *stat = (uint64_t)((new_data +
4950 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4954 i40e_stat_update_48(struct i40e_hw *hw,
4963 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4964 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4965 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4970 if (new_data >= *offset)
4971 *stat = new_data - *offset;
4973 *stat = (uint64_t)((new_data +
4974 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4976 *stat &= I40E_48_BIT_MASK;
4981 i40e_pf_disable_irq0(struct i40e_hw *hw)
4983 /* Disable all interrupt types */
4984 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4985 I40E_WRITE_FLUSH(hw);
4990 i40e_pf_enable_irq0(struct i40e_hw *hw)
4992 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4993 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4994 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4995 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4996 I40E_WRITE_FLUSH(hw);
5000 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5002 /* read pending request and disable first */
5003 i40e_pf_disable_irq0(hw);
5004 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5005 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5006 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5009 /* Link no queues with irq0 */
5010 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5011 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5015 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5017 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5021 uint32_t index, offset, val;
5026 * Try to find which VF trigger a reset, use absolute VF id to access
5027 * since the reg is global register.
5029 for (i = 0; i < pf->vf_num; i++) {
5030 abs_vf_id = hw->func_caps.vf_base_id + i;
5031 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5032 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5033 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5034 /* VFR event occured */
5035 if (val & (0x1 << offset)) {
5038 /* Clear the event first */
5039 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5041 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5043 * Only notify a VF reset event occured,
5044 * don't trigger another SW reset
5046 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5047 if (ret != I40E_SUCCESS)
5048 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5054 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5056 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5057 struct i40e_arq_event_info info;
5058 uint16_t pending, opcode;
5061 info.buf_len = I40E_AQ_BUF_SZ;
5062 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5063 if (!info.msg_buf) {
5064 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5070 ret = i40e_clean_arq_element(hw, &info, &pending);
5072 if (ret != I40E_SUCCESS) {
5073 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5074 "aq_err: %u", hw->aq.asq_last_status);
5077 opcode = rte_le_to_cpu_16(info.desc.opcode);
5080 case i40e_aqc_opc_send_msg_to_pf:
5081 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5082 i40e_pf_host_handle_vf_msg(dev,
5083 rte_le_to_cpu_16(info.desc.retval),
5084 rte_le_to_cpu_32(info.desc.cookie_high),
5085 rte_le_to_cpu_32(info.desc.cookie_low),
5090 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5095 rte_free(info.msg_buf);
5099 * Interrupt handler is registered as the alarm callback for handling LSC
5100 * interrupt in a definite of time, in order to wait the NIC into a stable
5101 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5102 * no need for link down interrupt.
5105 i40e_dev_interrupt_delayed_handler(void *param)
5107 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5108 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5111 /* read interrupt causes again */
5112 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5114 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5115 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5116 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5117 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5118 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5119 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5120 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5121 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5122 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5123 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5124 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5126 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5127 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5128 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5129 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5130 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5132 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5133 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5134 i40e_dev_handle_vfr_event(dev);
5136 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5137 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5138 i40e_dev_handle_aq_msg(dev);
5141 /* handle the link up interrupt in an alarm callback */
5142 i40e_dev_link_update(dev, 0);
5143 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5145 i40e_pf_enable_irq0(hw);
5146 rte_intr_enable(&(dev->pci_dev->intr_handle));
5150 * Interrupt handler triggered by NIC for handling
5151 * specific interrupt.
5154 * Pointer to interrupt handle.
5156 * The address of parameter (struct rte_eth_dev *) regsitered before.
5162 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5165 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5166 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5169 /* Disable interrupt */
5170 i40e_pf_disable_irq0(hw);
5172 /* read out interrupt causes */
5173 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5175 /* No interrupt event indicated */
5176 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5177 PMD_DRV_LOG(INFO, "No interrupt event");
5180 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5181 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5182 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5183 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5184 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5185 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5186 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5187 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5188 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5189 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5190 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5191 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5192 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5193 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5194 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5195 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5197 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5198 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5199 i40e_dev_handle_vfr_event(dev);
5201 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5202 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5203 i40e_dev_handle_aq_msg(dev);
5206 /* Link Status Change interrupt */
5207 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5208 #define I40E_US_PER_SECOND 1000000
5209 struct rte_eth_link link;
5211 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5212 memset(&link, 0, sizeof(link));
5213 rte_i40e_dev_atomic_read_link_status(dev, &link);
5214 i40e_dev_link_update(dev, 0);
5217 * For link up interrupt, it needs to wait 1 second to let the
5218 * hardware be a stable state. Otherwise several consecutive
5219 * interrupts can be observed.
5220 * For link down interrupt, no need to wait.
5222 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5223 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5226 _rte_eth_dev_callback_process(dev,
5227 RTE_ETH_EVENT_INTR_LSC);
5231 /* Enable interrupt */
5232 i40e_pf_enable_irq0(hw);
5233 rte_intr_enable(&(dev->pci_dev->intr_handle));
5237 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5238 struct i40e_macvlan_filter *filter,
5241 int ele_num, ele_buff_size;
5242 int num, actual_num, i;
5244 int ret = I40E_SUCCESS;
5245 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5246 struct i40e_aqc_add_macvlan_element_data *req_list;
5248 if (filter == NULL || total == 0)
5249 return I40E_ERR_PARAM;
5250 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5251 ele_buff_size = hw->aq.asq_buf_size;
5253 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5254 if (req_list == NULL) {
5255 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5256 return I40E_ERR_NO_MEMORY;
5261 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5262 memset(req_list, 0, ele_buff_size);
5264 for (i = 0; i < actual_num; i++) {
5265 (void)rte_memcpy(req_list[i].mac_addr,
5266 &filter[num + i].macaddr, ETH_ADDR_LEN);
5267 req_list[i].vlan_tag =
5268 rte_cpu_to_le_16(filter[num + i].vlan_id);
5270 switch (filter[num + i].filter_type) {
5271 case RTE_MAC_PERFECT_MATCH:
5272 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5273 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5275 case RTE_MACVLAN_PERFECT_MATCH:
5276 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5278 case RTE_MAC_HASH_MATCH:
5279 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5280 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5282 case RTE_MACVLAN_HASH_MATCH:
5283 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5286 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5287 ret = I40E_ERR_PARAM;
5291 req_list[i].queue_number = 0;
5293 req_list[i].flags = rte_cpu_to_le_16(flags);
5296 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5298 if (ret != I40E_SUCCESS) {
5299 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5303 } while (num < total);
5311 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5312 struct i40e_macvlan_filter *filter,
5315 int ele_num, ele_buff_size;
5316 int num, actual_num, i;
5318 int ret = I40E_SUCCESS;
5319 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5320 struct i40e_aqc_remove_macvlan_element_data *req_list;
5322 if (filter == NULL || total == 0)
5323 return I40E_ERR_PARAM;
5325 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5326 ele_buff_size = hw->aq.asq_buf_size;
5328 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5329 if (req_list == NULL) {
5330 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5331 return I40E_ERR_NO_MEMORY;
5336 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5337 memset(req_list, 0, ele_buff_size);
5339 for (i = 0; i < actual_num; i++) {
5340 (void)rte_memcpy(req_list[i].mac_addr,
5341 &filter[num + i].macaddr, ETH_ADDR_LEN);
5342 req_list[i].vlan_tag =
5343 rte_cpu_to_le_16(filter[num + i].vlan_id);
5345 switch (filter[num + i].filter_type) {
5346 case RTE_MAC_PERFECT_MATCH:
5347 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5348 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5350 case RTE_MACVLAN_PERFECT_MATCH:
5351 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5353 case RTE_MAC_HASH_MATCH:
5354 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5355 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5357 case RTE_MACVLAN_HASH_MATCH:
5358 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5361 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5362 ret = I40E_ERR_PARAM;
5365 req_list[i].flags = rte_cpu_to_le_16(flags);
5368 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5370 if (ret != I40E_SUCCESS) {
5371 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5375 } while (num < total);
5382 /* Find out specific MAC filter */
5383 static struct i40e_mac_filter *
5384 i40e_find_mac_filter(struct i40e_vsi *vsi,
5385 struct ether_addr *macaddr)
5387 struct i40e_mac_filter *f;
5389 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5390 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5398 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5401 uint32_t vid_idx, vid_bit;
5403 if (vlan_id > ETH_VLAN_ID_MAX)
5406 vid_idx = I40E_VFTA_IDX(vlan_id);
5407 vid_bit = I40E_VFTA_BIT(vlan_id);
5409 if (vsi->vfta[vid_idx] & vid_bit)
5416 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5417 uint16_t vlan_id, bool on)
5419 uint32_t vid_idx, vid_bit;
5421 if (vlan_id > ETH_VLAN_ID_MAX)
5424 vid_idx = I40E_VFTA_IDX(vlan_id);
5425 vid_bit = I40E_VFTA_BIT(vlan_id);
5428 vsi->vfta[vid_idx] |= vid_bit;
5430 vsi->vfta[vid_idx] &= ~vid_bit;
5434 * Find all vlan options for specific mac addr,
5435 * return with actual vlan found.
5438 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5439 struct i40e_macvlan_filter *mv_f,
5440 int num, struct ether_addr *addr)
5446 * Not to use i40e_find_vlan_filter to decrease the loop time,
5447 * although the code looks complex.
5449 if (num < vsi->vlan_num)
5450 return I40E_ERR_PARAM;
5453 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5455 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5456 if (vsi->vfta[j] & (1 << k)) {
5458 PMD_DRV_LOG(ERR, "vlan number "
5460 return I40E_ERR_PARAM;
5462 (void)rte_memcpy(&mv_f[i].macaddr,
5463 addr, ETH_ADDR_LEN);
5465 j * I40E_UINT32_BIT_SIZE + k;
5471 return I40E_SUCCESS;
5475 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5476 struct i40e_macvlan_filter *mv_f,
5481 struct i40e_mac_filter *f;
5483 if (num < vsi->mac_num)
5484 return I40E_ERR_PARAM;
5486 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5488 PMD_DRV_LOG(ERR, "buffer number not match");
5489 return I40E_ERR_PARAM;
5491 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5493 mv_f[i].vlan_id = vlan;
5494 mv_f[i].filter_type = f->mac_info.filter_type;
5498 return I40E_SUCCESS;
5502 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5505 struct i40e_mac_filter *f;
5506 struct i40e_macvlan_filter *mv_f;
5507 int ret = I40E_SUCCESS;
5509 if (vsi == NULL || vsi->mac_num == 0)
5510 return I40E_ERR_PARAM;
5512 /* Case that no vlan is set */
5513 if (vsi->vlan_num == 0)
5516 num = vsi->mac_num * vsi->vlan_num;
5518 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5520 PMD_DRV_LOG(ERR, "failed to allocate memory");
5521 return I40E_ERR_NO_MEMORY;
5525 if (vsi->vlan_num == 0) {
5526 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5527 (void)rte_memcpy(&mv_f[i].macaddr,
5528 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5529 mv_f[i].vlan_id = 0;
5533 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5534 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5535 vsi->vlan_num, &f->mac_info.mac_addr);
5536 if (ret != I40E_SUCCESS)
5542 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5550 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5552 struct i40e_macvlan_filter *mv_f;
5554 int ret = I40E_SUCCESS;
5556 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5557 return I40E_ERR_PARAM;
5559 /* If it's already set, just return */
5560 if (i40e_find_vlan_filter(vsi,vlan))
5561 return I40E_SUCCESS;
5563 mac_num = vsi->mac_num;
5566 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5567 return I40E_ERR_PARAM;
5570 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5573 PMD_DRV_LOG(ERR, "failed to allocate memory");
5574 return I40E_ERR_NO_MEMORY;
5577 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5579 if (ret != I40E_SUCCESS)
5582 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5584 if (ret != I40E_SUCCESS)
5587 i40e_set_vlan_filter(vsi, vlan, 1);
5597 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5599 struct i40e_macvlan_filter *mv_f;
5601 int ret = I40E_SUCCESS;
5604 * Vlan 0 is the generic filter for untagged packets
5605 * and can't be removed.
5607 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5608 return I40E_ERR_PARAM;
5610 /* If can't find it, just return */
5611 if (!i40e_find_vlan_filter(vsi, vlan))
5612 return I40E_ERR_PARAM;
5614 mac_num = vsi->mac_num;
5617 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5618 return I40E_ERR_PARAM;
5621 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5624 PMD_DRV_LOG(ERR, "failed to allocate memory");
5625 return I40E_ERR_NO_MEMORY;
5628 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5630 if (ret != I40E_SUCCESS)
5633 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5635 if (ret != I40E_SUCCESS)
5638 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5639 if (vsi->vlan_num == 1) {
5640 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5641 if (ret != I40E_SUCCESS)
5644 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5645 if (ret != I40E_SUCCESS)
5649 i40e_set_vlan_filter(vsi, vlan, 0);
5659 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5661 struct i40e_mac_filter *f;
5662 struct i40e_macvlan_filter *mv_f;
5663 int i, vlan_num = 0;
5664 int ret = I40E_SUCCESS;
5666 /* If it's add and we've config it, return */
5667 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5669 return I40E_SUCCESS;
5670 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5671 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5674 * If vlan_num is 0, that's the first time to add mac,
5675 * set mask for vlan_id 0.
5677 if (vsi->vlan_num == 0) {
5678 i40e_set_vlan_filter(vsi, 0, 1);
5681 vlan_num = vsi->vlan_num;
5682 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5683 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5686 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5688 PMD_DRV_LOG(ERR, "failed to allocate memory");
5689 return I40E_ERR_NO_MEMORY;
5692 for (i = 0; i < vlan_num; i++) {
5693 mv_f[i].filter_type = mac_filter->filter_type;
5694 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5698 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5699 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5700 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5701 &mac_filter->mac_addr);
5702 if (ret != I40E_SUCCESS)
5706 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5707 if (ret != I40E_SUCCESS)
5710 /* Add the mac addr into mac list */
5711 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5713 PMD_DRV_LOG(ERR, "failed to allocate memory");
5714 ret = I40E_ERR_NO_MEMORY;
5717 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5719 f->mac_info.filter_type = mac_filter->filter_type;
5720 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5731 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5733 struct i40e_mac_filter *f;
5734 struct i40e_macvlan_filter *mv_f;
5736 enum rte_mac_filter_type filter_type;
5737 int ret = I40E_SUCCESS;
5739 /* Can't find it, return an error */
5740 f = i40e_find_mac_filter(vsi, addr);
5742 return I40E_ERR_PARAM;
5744 vlan_num = vsi->vlan_num;
5745 filter_type = f->mac_info.filter_type;
5746 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5747 filter_type == RTE_MACVLAN_HASH_MATCH) {
5748 if (vlan_num == 0) {
5749 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5750 return I40E_ERR_PARAM;
5752 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5753 filter_type == RTE_MAC_HASH_MATCH)
5756 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5758 PMD_DRV_LOG(ERR, "failed to allocate memory");
5759 return I40E_ERR_NO_MEMORY;
5762 for (i = 0; i < vlan_num; i++) {
5763 mv_f[i].filter_type = filter_type;
5764 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5767 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5768 filter_type == RTE_MACVLAN_HASH_MATCH) {
5769 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5770 if (ret != I40E_SUCCESS)
5774 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5775 if (ret != I40E_SUCCESS)
5778 /* Remove the mac addr into mac list */
5779 TAILQ_REMOVE(&vsi->mac_list, f, next);
5789 /* Configure hash enable flags for RSS */
5791 i40e_config_hena(uint64_t flags)
5798 if (flags & ETH_RSS_FRAG_IPV4)
5799 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5800 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5801 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5802 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5803 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5804 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5805 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5806 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5807 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5808 if (flags & ETH_RSS_FRAG_IPV6)
5809 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5810 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5811 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5812 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5813 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5814 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5815 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5816 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5817 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5818 if (flags & ETH_RSS_L2_PAYLOAD)
5819 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5824 /* Parse the hash enable flags */
5826 i40e_parse_hena(uint64_t flags)
5828 uint64_t rss_hf = 0;
5832 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5833 rss_hf |= ETH_RSS_FRAG_IPV4;
5834 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5835 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5836 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5837 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5838 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5839 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5840 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5841 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5842 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5843 rss_hf |= ETH_RSS_FRAG_IPV6;
5844 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5845 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5846 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5847 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5848 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5849 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5850 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5851 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5852 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5853 rss_hf |= ETH_RSS_L2_PAYLOAD;
5860 i40e_pf_disable_rss(struct i40e_pf *pf)
5862 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5865 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5866 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5867 hena &= ~I40E_RSS_HENA_ALL;
5868 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5869 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5870 I40E_WRITE_FLUSH(hw);
5874 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5876 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5877 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5880 if (!key || key_len == 0) {
5881 PMD_DRV_LOG(DEBUG, "No key to be configured");
5883 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5885 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5889 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5890 struct i40e_aqc_get_set_rss_key_data *key_dw =
5891 (struct i40e_aqc_get_set_rss_key_data *)key;
5893 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5895 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5898 uint32_t *hash_key = (uint32_t *)key;
5901 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5902 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5903 I40E_WRITE_FLUSH(hw);
5910 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5912 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5913 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5916 if (!key || !key_len)
5919 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5920 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5921 (struct i40e_aqc_get_set_rss_key_data *)key);
5923 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5927 uint32_t *key_dw = (uint32_t *)key;
5930 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5931 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5933 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5939 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5941 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5946 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5947 rss_conf->rss_key_len);
5951 rss_hf = rss_conf->rss_hf;
5952 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5953 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5954 hena &= ~I40E_RSS_HENA_ALL;
5955 hena |= i40e_config_hena(rss_hf);
5956 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5957 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5958 I40E_WRITE_FLUSH(hw);
5964 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5965 struct rte_eth_rss_conf *rss_conf)
5967 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5968 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5969 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5972 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5973 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5974 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5975 if (rss_hf != 0) /* Enable RSS */
5977 return 0; /* Nothing to do */
5980 if (rss_hf == 0) /* Disable RSS */
5983 return i40e_hw_rss_hash_set(pf, rss_conf);
5987 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5988 struct rte_eth_rss_conf *rss_conf)
5990 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5991 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5994 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5995 &rss_conf->rss_key_len);
5997 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5998 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5999 rss_conf->rss_hf = i40e_parse_hena(hena);
6005 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6007 switch (filter_type) {
6008 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6009 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6011 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6012 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6014 case RTE_TUNNEL_FILTER_IMAC_TENID:
6015 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6017 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6018 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6020 case ETH_TUNNEL_FILTER_IMAC:
6021 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6023 case ETH_TUNNEL_FILTER_OIP:
6024 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6026 case ETH_TUNNEL_FILTER_IIP:
6027 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6030 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6038 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6039 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6044 uint8_t i, tun_type = 0;
6045 /* internal varialbe to convert ipv6 byte order */
6046 uint32_t convert_ipv6[4];
6048 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6049 struct i40e_vsi *vsi = pf->main_vsi;
6050 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6051 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6053 cld_filter = rte_zmalloc("tunnel_filter",
6054 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6057 if (NULL == cld_filter) {
6058 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6061 pfilter = cld_filter;
6063 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6064 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6066 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6067 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6068 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6069 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6070 rte_memcpy(&pfilter->ipaddr.v4.data,
6071 &rte_cpu_to_le_32(ipv4_addr),
6072 sizeof(pfilter->ipaddr.v4.data));
6074 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6075 for (i = 0; i < 4; i++) {
6077 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6079 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6080 sizeof(pfilter->ipaddr.v6.data));
6083 /* check tunneled type */
6084 switch (tunnel_filter->tunnel_type) {
6085 case RTE_TUNNEL_TYPE_VXLAN:
6086 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6088 case RTE_TUNNEL_TYPE_NVGRE:
6089 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6091 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6092 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6095 /* Other tunnel types is not supported. */
6096 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6097 rte_free(cld_filter);
6101 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6104 rte_free(cld_filter);
6108 pfilter->flags |= rte_cpu_to_le_16(
6109 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6110 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6111 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6112 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6115 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6117 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6120 rte_free(cld_filter);
6125 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6129 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6130 if (pf->vxlan_ports[i] == port)
6138 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6142 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6144 idx = i40e_get_vxlan_port_idx(pf, port);
6146 /* Check if port already exists */
6148 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6152 /* Now check if there is space to add the new port */
6153 idx = i40e_get_vxlan_port_idx(pf, 0);
6155 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6156 "not adding port %d", port);
6160 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6163 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6167 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6170 /* New port: add it and mark its index in the bitmap */
6171 pf->vxlan_ports[idx] = port;
6172 pf->vxlan_bitmap |= (1 << idx);
6174 if (!(pf->flags & I40E_FLAG_VXLAN))
6175 pf->flags |= I40E_FLAG_VXLAN;
6181 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6184 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6186 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6187 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6191 idx = i40e_get_vxlan_port_idx(pf, port);
6194 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6198 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6199 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6203 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6206 pf->vxlan_ports[idx] = 0;
6207 pf->vxlan_bitmap &= ~(1 << idx);
6209 if (!pf->vxlan_bitmap)
6210 pf->flags &= ~I40E_FLAG_VXLAN;
6215 /* Add UDP tunneling port */
6217 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6218 struct rte_eth_udp_tunnel *udp_tunnel)
6221 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6223 if (udp_tunnel == NULL)
6226 switch (udp_tunnel->prot_type) {
6227 case RTE_TUNNEL_TYPE_VXLAN:
6228 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6231 case RTE_TUNNEL_TYPE_GENEVE:
6232 case RTE_TUNNEL_TYPE_TEREDO:
6233 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6238 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6246 /* Remove UDP tunneling port */
6248 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6249 struct rte_eth_udp_tunnel *udp_tunnel)
6252 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6254 if (udp_tunnel == NULL)
6257 switch (udp_tunnel->prot_type) {
6258 case RTE_TUNNEL_TYPE_VXLAN:
6259 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6261 case RTE_TUNNEL_TYPE_GENEVE:
6262 case RTE_TUNNEL_TYPE_TEREDO:
6263 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6267 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6275 /* Calculate the maximum number of contiguous PF queues that are configured */
6277 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6279 struct rte_eth_dev_data *data = pf->dev_data;
6281 struct i40e_rx_queue *rxq;
6284 for (i = 0; i < pf->lan_nb_qps; i++) {
6285 rxq = data->rx_queues[i];
6286 if (rxq && rxq->q_set)
6297 i40e_pf_config_rss(struct i40e_pf *pf)
6299 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6300 struct rte_eth_rss_conf rss_conf;
6301 uint32_t i, lut = 0;
6305 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6306 * It's necessary to calulate the actual PF queues that are configured.
6308 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6309 num = i40e_pf_calc_configured_queues_num(pf);
6311 num = pf->dev_data->nb_rx_queues;
6313 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6314 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6318 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6322 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6325 lut = (lut << 8) | (j & ((0x1 <<
6326 hw->func_caps.rss_table_entry_width) - 1));
6328 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6331 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6332 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6333 i40e_pf_disable_rss(pf);
6336 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6337 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6338 /* Random default keys */
6339 static uint32_t rss_key_default[] = {0x6b793944,
6340 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6341 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6342 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6344 rss_conf.rss_key = (uint8_t *)rss_key_default;
6345 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6349 return i40e_hw_rss_hash_set(pf, &rss_conf);
6353 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6354 struct rte_eth_tunnel_filter_conf *filter)
6356 if (pf == NULL || filter == NULL) {
6357 PMD_DRV_LOG(ERR, "Invalid parameter");
6361 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6362 PMD_DRV_LOG(ERR, "Invalid queue ID");
6366 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6367 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6371 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6372 (is_zero_ether_addr(&filter->outer_mac))) {
6373 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6377 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6378 (is_zero_ether_addr(&filter->inner_mac))) {
6379 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6386 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6387 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6389 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6394 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6395 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6398 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6399 } else if (len == 4) {
6400 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6402 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6407 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6414 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6415 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6421 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6428 switch (cfg->cfg_type) {
6429 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6430 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6433 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6441 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6442 enum rte_filter_op filter_op,
6445 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6446 int ret = I40E_ERR_PARAM;
6448 switch (filter_op) {
6449 case RTE_ETH_FILTER_SET:
6450 ret = i40e_dev_global_config_set(hw,
6451 (struct rte_eth_global_cfg *)arg);
6454 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6462 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6463 enum rte_filter_op filter_op,
6466 struct rte_eth_tunnel_filter_conf *filter;
6467 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6468 int ret = I40E_SUCCESS;
6470 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6472 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6473 return I40E_ERR_PARAM;
6475 switch (filter_op) {
6476 case RTE_ETH_FILTER_NOP:
6477 if (!(pf->flags & I40E_FLAG_VXLAN))
6478 ret = I40E_NOT_SUPPORTED;
6480 case RTE_ETH_FILTER_ADD:
6481 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6483 case RTE_ETH_FILTER_DELETE:
6484 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6487 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6488 ret = I40E_ERR_PARAM;
6496 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6499 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6502 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6503 ret = i40e_pf_config_rss(pf);
6505 i40e_pf_disable_rss(pf);
6510 /* Get the symmetric hash enable configurations per port */
6512 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6514 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6516 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6519 /* Set the symmetric hash enable configurations per port */
6521 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6523 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6526 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6527 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6531 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6533 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6534 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6538 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6540 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6541 I40E_WRITE_FLUSH(hw);
6545 * Get global configurations of hash function type and symmetric hash enable
6546 * per flow type (pctype). Note that global configuration means it affects all
6547 * the ports on the same NIC.
6550 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6551 struct rte_eth_hash_global_conf *g_cfg)
6553 uint32_t reg, mask = I40E_FLOW_TYPES;
6555 enum i40e_filter_pctype pctype;
6557 memset(g_cfg, 0, sizeof(*g_cfg));
6558 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6559 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6560 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6562 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6563 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6564 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6566 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6567 if (!(mask & (1UL << i)))
6569 mask &= ~(1UL << i);
6570 /* Bit set indicats the coresponding flow type is supported */
6571 g_cfg->valid_bit_mask[0] |= (1UL << i);
6572 pctype = i40e_flowtype_to_pctype(i);
6573 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6574 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6575 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6582 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6585 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6587 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6588 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6589 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6590 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6596 * As i40e supports less than 32 flow types, only first 32 bits need to
6599 mask0 = g_cfg->valid_bit_mask[0];
6600 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6602 /* Check if any unsupported flow type configured */
6603 if ((mask0 | i40e_mask) ^ i40e_mask)
6606 if (g_cfg->valid_bit_mask[i])
6614 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6620 * Set global configurations of hash function type and symmetric hash enable
6621 * per flow type (pctype). Note any modifying global configuration will affect
6622 * all the ports on the same NIC.
6625 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6626 struct rte_eth_hash_global_conf *g_cfg)
6631 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6632 enum i40e_filter_pctype pctype;
6634 /* Check the input parameters */
6635 ret = i40e_hash_global_config_check(g_cfg);
6639 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6640 if (!(mask0 & (1UL << i)))
6642 mask0 &= ~(1UL << i);
6643 pctype = i40e_flowtype_to_pctype(i);
6644 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6645 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6646 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6649 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6650 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6652 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6653 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6657 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6658 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6660 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6661 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6665 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6667 /* Use the default, and keep it as it is */
6670 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6673 I40E_WRITE_FLUSH(hw);
6679 * Valid input sets for hash and flow director filters per PCTYPE
6682 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6683 enum rte_filter_type filter)
6687 static const uint64_t valid_hash_inset_table[] = {
6688 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6689 I40E_INSET_DMAC | I40E_INSET_SMAC |
6690 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6691 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6692 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6693 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6694 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6695 I40E_INSET_FLEX_PAYLOAD,
6696 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6697 I40E_INSET_DMAC | I40E_INSET_SMAC |
6698 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6699 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6700 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6701 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6702 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6703 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6704 I40E_INSET_FLEX_PAYLOAD,
6705 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6706 I40E_INSET_DMAC | I40E_INSET_SMAC |
6707 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6708 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6709 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6710 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6711 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6712 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6713 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6714 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6715 I40E_INSET_DMAC | I40E_INSET_SMAC |
6716 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6717 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6718 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6719 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6720 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6721 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6722 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6723 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6724 I40E_INSET_DMAC | I40E_INSET_SMAC |
6725 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6726 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6727 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6728 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6729 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6730 I40E_INSET_FLEX_PAYLOAD,
6731 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6732 I40E_INSET_DMAC | I40E_INSET_SMAC |
6733 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6734 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6735 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6736 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6737 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6738 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6739 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6740 I40E_INSET_DMAC | I40E_INSET_SMAC |
6741 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6742 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6743 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6744 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6745 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6746 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6747 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6748 I40E_INSET_DMAC | I40E_INSET_SMAC |
6749 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6750 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6751 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6752 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6753 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6754 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6755 I40E_INSET_FLEX_PAYLOAD,
6756 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6757 I40E_INSET_DMAC | I40E_INSET_SMAC |
6758 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6759 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6760 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6761 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6762 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6763 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6764 I40E_INSET_FLEX_PAYLOAD,
6765 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6766 I40E_INSET_DMAC | I40E_INSET_SMAC |
6767 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6768 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6769 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6770 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6771 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6772 I40E_INSET_FLEX_PAYLOAD,
6773 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6774 I40E_INSET_DMAC | I40E_INSET_SMAC |
6775 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6776 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6777 I40E_INSET_FLEX_PAYLOAD,
6781 * Flow director supports only fields defined in
6782 * union rte_eth_fdir_flow.
6784 static const uint64_t valid_fdir_inset_table[] = {
6785 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6786 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6787 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6788 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6789 I40E_INSET_IPV4_TTL,
6790 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6791 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6792 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6793 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6794 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6795 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6796 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6797 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6798 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6799 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6800 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6801 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6802 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6803 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6804 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6806 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6807 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6808 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6809 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6810 I40E_INSET_IPV4_TTL,
6811 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6812 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6813 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6814 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6815 I40E_INSET_IPV6_HOP_LIMIT,
6816 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6817 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6818 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6819 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6820 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6821 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6822 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6823 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6824 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6825 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6826 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6827 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6828 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6829 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6830 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6832 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6833 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6834 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6835 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6836 I40E_INSET_IPV6_HOP_LIMIT,
6837 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6838 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6839 I40E_INSET_LAST_ETHER_TYPE,
6842 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6844 if (filter == RTE_ETH_FILTER_HASH)
6845 valid = valid_hash_inset_table[pctype];
6847 valid = valid_fdir_inset_table[pctype];
6853 * Validate if the input set is allowed for a specific PCTYPE
6856 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6857 enum rte_filter_type filter, uint64_t inset)
6861 valid = i40e_get_valid_input_set(pctype, filter);
6862 if (inset & (~valid))
6868 /* default input set fields combination per pctype */
6870 i40e_get_default_input_set(uint16_t pctype)
6872 static const uint64_t default_inset_table[] = {
6873 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6874 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6875 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6876 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6877 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6878 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6879 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6880 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6881 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6882 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6883 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6885 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6886 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6887 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6888 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6889 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6890 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6891 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6892 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6893 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6894 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6895 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6896 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6897 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6899 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6900 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6901 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6902 I40E_INSET_LAST_ETHER_TYPE,
6905 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6908 return default_inset_table[pctype];
6912 * Parse the input set from index to logical bit masks
6915 i40e_parse_input_set(uint64_t *inset,
6916 enum i40e_filter_pctype pctype,
6917 enum rte_eth_input_set_field *field,
6923 static const struct {
6924 enum rte_eth_input_set_field field;
6926 } inset_convert_table[] = {
6927 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6928 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6929 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6930 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6931 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6932 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6933 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6934 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6935 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6936 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6937 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
6938 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6939 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6940 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6941 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6942 I40E_INSET_IPV6_NEXT_HDR},
6943 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
6944 I40E_INSET_IPV6_HOP_LIMIT},
6945 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6946 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6947 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6948 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6949 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6950 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6951 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6952 I40E_INSET_SCTP_VT},
6953 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6954 I40E_INSET_TUNNEL_DMAC},
6955 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6956 I40E_INSET_VLAN_TUNNEL},
6957 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6958 I40E_INSET_TUNNEL_ID},
6959 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6960 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6961 I40E_INSET_FLEX_PAYLOAD_W1},
6962 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6963 I40E_INSET_FLEX_PAYLOAD_W2},
6964 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6965 I40E_INSET_FLEX_PAYLOAD_W3},
6966 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6967 I40E_INSET_FLEX_PAYLOAD_W4},
6968 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6969 I40E_INSET_FLEX_PAYLOAD_W5},
6970 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6971 I40E_INSET_FLEX_PAYLOAD_W6},
6972 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6973 I40E_INSET_FLEX_PAYLOAD_W7},
6974 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6975 I40E_INSET_FLEX_PAYLOAD_W8},
6978 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6981 /* Only one item allowed for default or all */
6983 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6984 *inset = i40e_get_default_input_set(pctype);
6986 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6987 *inset = I40E_INSET_NONE;
6992 for (i = 0, *inset = 0; i < size; i++) {
6993 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6994 if (field[i] == inset_convert_table[j].field) {
6995 *inset |= inset_convert_table[j].inset;
7000 /* It contains unsupported input set, return immediately */
7001 if (j == RTE_DIM(inset_convert_table))
7009 * Translate the input set from bit masks to register aware bit masks
7013 i40e_translate_input_set_reg(uint64_t input)
7018 static const struct {
7022 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7023 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7024 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7025 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7026 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7027 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7028 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7029 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7030 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7031 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7032 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7033 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7034 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7035 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7036 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7037 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7038 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7039 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7040 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7041 {I40E_INSET_TUNNEL_DMAC,
7042 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7043 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7044 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7045 {I40E_INSET_TUNNEL_SRC_PORT,
7046 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7047 {I40E_INSET_TUNNEL_DST_PORT,
7048 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7049 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7050 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7051 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7052 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7053 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7054 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7055 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7056 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7057 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7063 /* Translate input set to register aware inset */
7064 for (i = 0; i < RTE_DIM(inset_map); i++) {
7065 if (input & inset_map[i].inset)
7066 val |= inset_map[i].inset_reg;
7073 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7076 uint64_t inset_need_mask = inset;
7078 static const struct {
7081 } inset_mask_map[] = {
7082 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7083 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7084 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7085 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7086 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7087 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7088 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7089 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7092 if (!inset || !mask || !nb_elem)
7095 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7096 /* Clear the inset bit, if no MASK is required,
7097 * for example proto + ttl
7099 if ((inset & inset_mask_map[i].inset) ==
7100 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7101 inset_need_mask &= ~inset_mask_map[i].inset;
7102 if (!inset_need_mask)
7105 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7106 if ((inset_need_mask & inset_mask_map[i].inset) ==
7107 inset_mask_map[i].inset) {
7108 if (idx >= nb_elem) {
7109 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7112 mask[idx] = inset_mask_map[i].mask;
7121 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7123 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7125 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7127 i40e_write_rx_ctl(hw, addr, val);
7128 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7129 (uint32_t)i40e_read_rx_ctl(hw, addr));
7133 i40e_filter_input_set_init(struct i40e_pf *pf)
7135 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7136 enum i40e_filter_pctype pctype;
7137 uint64_t input_set, inset_reg;
7138 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7141 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7142 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7143 if (!I40E_VALID_PCTYPE(pctype))
7145 input_set = i40e_get_default_input_set(pctype);
7147 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7148 I40E_INSET_MASK_NUM_REG);
7151 inset_reg = i40e_translate_input_set_reg(input_set);
7153 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7154 (uint32_t)(inset_reg & UINT32_MAX));
7155 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7156 (uint32_t)((inset_reg >>
7157 I40E_32_BIT_WIDTH) & UINT32_MAX));
7158 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7159 (uint32_t)(inset_reg & UINT32_MAX));
7160 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7161 (uint32_t)((inset_reg >>
7162 I40E_32_BIT_WIDTH) & UINT32_MAX));
7164 for (i = 0; i < num; i++) {
7165 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7167 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7170 /*clear unused mask registers of the pctype */
7171 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7172 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7174 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7177 I40E_WRITE_FLUSH(hw);
7179 /* store the default input set */
7180 pf->hash_input_set[pctype] = input_set;
7181 pf->fdir.input_set[pctype] = input_set;
7186 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7187 struct rte_eth_input_set_conf *conf)
7189 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7190 enum i40e_filter_pctype pctype;
7191 uint64_t input_set, inset_reg = 0;
7192 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7196 PMD_DRV_LOG(ERR, "Invalid pointer");
7199 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7200 conf->op != RTE_ETH_INPUT_SET_ADD) {
7201 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7205 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7206 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7207 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7212 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7215 PMD_DRV_LOG(ERR, "Failed to parse input set");
7218 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7220 PMD_DRV_LOG(ERR, "Invalid input set");
7223 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7224 /* get inset value in register */
7225 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7226 inset_reg <<= I40E_32_BIT_WIDTH;
7227 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7228 input_set |= pf->hash_input_set[pctype];
7230 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7231 I40E_INSET_MASK_NUM_REG);
7235 inset_reg |= i40e_translate_input_set_reg(input_set);
7237 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7238 (uint32_t)(inset_reg & UINT32_MAX));
7239 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7240 (uint32_t)((inset_reg >>
7241 I40E_32_BIT_WIDTH) & UINT32_MAX));
7243 for (i = 0; i < num; i++)
7244 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7246 /*clear unused mask registers of the pctype */
7247 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7248 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7250 I40E_WRITE_FLUSH(hw);
7252 pf->hash_input_set[pctype] = input_set;
7257 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7258 struct rte_eth_input_set_conf *conf)
7260 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7261 enum i40e_filter_pctype pctype;
7262 uint64_t input_set, inset_reg = 0;
7263 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7267 PMD_DRV_LOG(ERR, "Invalid pointer");
7270 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7271 conf->op != RTE_ETH_INPUT_SET_ADD) {
7272 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7276 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7277 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7278 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7282 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7285 PMD_DRV_LOG(ERR, "Failed to parse input set");
7288 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7290 PMD_DRV_LOG(ERR, "Invalid input set");
7294 /* get inset value in register */
7295 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7296 inset_reg <<= I40E_32_BIT_WIDTH;
7297 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7299 /* Can not change the inset reg for flex payload for fdir,
7300 * it is done by writing I40E_PRTQF_FD_FLXINSET
7301 * in i40e_set_flex_mask_on_pctype.
7303 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7304 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7306 input_set |= pf->fdir.input_set[pctype];
7307 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7308 I40E_INSET_MASK_NUM_REG);
7312 inset_reg |= i40e_translate_input_set_reg(input_set);
7314 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7315 (uint32_t)(inset_reg & UINT32_MAX));
7316 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7317 (uint32_t)((inset_reg >>
7318 I40E_32_BIT_WIDTH) & UINT32_MAX));
7320 for (i = 0; i < num; i++)
7321 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7323 /*clear unused mask registers of the pctype */
7324 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7325 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7327 I40E_WRITE_FLUSH(hw);
7329 pf->fdir.input_set[pctype] = input_set;
7334 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7339 PMD_DRV_LOG(ERR, "Invalid pointer");
7343 switch (info->info_type) {
7344 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7345 i40e_get_symmetric_hash_enable_per_port(hw,
7346 &(info->info.enable));
7348 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7349 ret = i40e_get_hash_filter_global_config(hw,
7350 &(info->info.global_conf));
7353 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7363 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7368 PMD_DRV_LOG(ERR, "Invalid pointer");
7372 switch (info->info_type) {
7373 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7374 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7376 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7377 ret = i40e_set_hash_filter_global_config(hw,
7378 &(info->info.global_conf));
7380 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7381 ret = i40e_hash_filter_inset_select(hw,
7382 &(info->info.input_set_conf));
7386 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7395 /* Operations for hash function */
7397 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7398 enum rte_filter_op filter_op,
7401 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7404 switch (filter_op) {
7405 case RTE_ETH_FILTER_NOP:
7407 case RTE_ETH_FILTER_GET:
7408 ret = i40e_hash_filter_get(hw,
7409 (struct rte_eth_hash_filter_info *)arg);
7411 case RTE_ETH_FILTER_SET:
7412 ret = i40e_hash_filter_set(hw,
7413 (struct rte_eth_hash_filter_info *)arg);
7416 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7426 * Configure ethertype filter, which can director packet by filtering
7427 * with mac address and ether_type or only ether_type
7430 i40e_ethertype_filter_set(struct i40e_pf *pf,
7431 struct rte_eth_ethertype_filter *filter,
7434 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7435 struct i40e_control_filter_stats stats;
7439 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7440 PMD_DRV_LOG(ERR, "Invalid queue ID");
7443 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7444 filter->ether_type == ETHER_TYPE_IPv6) {
7445 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7446 " control packet filter.", filter->ether_type);
7449 if (filter->ether_type == ETHER_TYPE_VLAN)
7450 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7453 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7454 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7455 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7456 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7457 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7459 memset(&stats, 0, sizeof(stats));
7460 ret = i40e_aq_add_rem_control_packet_filter(hw,
7461 filter->mac_addr.addr_bytes,
7462 filter->ether_type, flags,
7464 filter->queue, add, &stats, NULL);
7466 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7467 " mac_etype_used = %u, etype_used = %u,"
7468 " mac_etype_free = %u, etype_free = %u\n",
7469 ret, stats.mac_etype_used, stats.etype_used,
7470 stats.mac_etype_free, stats.etype_free);
7477 * Handle operations for ethertype filter.
7480 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7481 enum rte_filter_op filter_op,
7484 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7487 if (filter_op == RTE_ETH_FILTER_NOP)
7491 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7496 switch (filter_op) {
7497 case RTE_ETH_FILTER_ADD:
7498 ret = i40e_ethertype_filter_set(pf,
7499 (struct rte_eth_ethertype_filter *)arg,
7502 case RTE_ETH_FILTER_DELETE:
7503 ret = i40e_ethertype_filter_set(pf,
7504 (struct rte_eth_ethertype_filter *)arg,
7508 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7516 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7517 enum rte_filter_type filter_type,
7518 enum rte_filter_op filter_op,
7526 switch (filter_type) {
7527 case RTE_ETH_FILTER_NONE:
7528 /* For global configuration */
7529 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7531 case RTE_ETH_FILTER_HASH:
7532 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7534 case RTE_ETH_FILTER_MACVLAN:
7535 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7537 case RTE_ETH_FILTER_ETHERTYPE:
7538 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7540 case RTE_ETH_FILTER_TUNNEL:
7541 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7543 case RTE_ETH_FILTER_FDIR:
7544 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7547 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7557 * Check and enable Extended Tag.
7558 * Enabling Extended Tag is important for 40G performance.
7561 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7566 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7569 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7573 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7574 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7579 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7582 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7586 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7587 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7590 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7591 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7594 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7601 * As some registers wouldn't be reset unless a global hardware reset,
7602 * hardware initialization is needed to put those registers into an
7603 * expected initial state.
7606 i40e_hw_init(struct rte_eth_dev *dev)
7608 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7610 i40e_enable_extended_tag(dev);
7612 /* clear the PF Queue Filter control register */
7613 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7615 /* Disable symmetric hash per port */
7616 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7619 enum i40e_filter_pctype
7620 i40e_flowtype_to_pctype(uint16_t flow_type)
7622 static const enum i40e_filter_pctype pctype_table[] = {
7623 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7624 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7625 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7626 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7627 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7628 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7629 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7630 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7631 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7632 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7633 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7634 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7635 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7636 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7637 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7638 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7639 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7640 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7641 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7644 return pctype_table[flow_type];
7648 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7650 static const uint16_t flowtype_table[] = {
7651 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7652 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7653 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7654 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7655 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7656 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7657 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7658 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7659 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7660 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7661 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7662 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7663 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7664 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7665 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7666 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7667 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7668 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7669 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7672 return flowtype_table[pctype];
7676 * On X710, performance number is far from the expectation on recent firmware
7677 * versions; on XL710, performance number is also far from the expectation on
7678 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7679 * mode is enabled and port MAC address is equal to the packet destination MAC
7680 * address. The fix for this issue may not be integrated in the following
7681 * firmware version. So the workaround in software driver is needed. It needs
7682 * to modify the initial values of 3 internal only registers for both X710 and
7683 * XL710. Note that the values for X710 or XL710 could be different, and the
7684 * workaround can be removed when it is fixed in firmware in the future.
7687 /* For both X710 and XL710 */
7688 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7689 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7691 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7692 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7695 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7697 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7698 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7701 i40e_configure_registers(struct i40e_hw *hw)
7707 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7708 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7709 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7715 for (i = 0; i < RTE_DIM(reg_table); i++) {
7716 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7717 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7719 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7722 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7725 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7728 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7732 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7733 reg_table[i].addr, reg);
7734 if (reg == reg_table[i].val)
7737 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7738 reg_table[i].val, NULL);
7740 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7741 "address of 0x%"PRIx32, reg_table[i].val,
7745 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7746 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7750 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7751 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7752 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7753 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7755 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7760 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7761 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7765 /* Configure for double VLAN RX stripping */
7766 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7767 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7768 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7769 ret = i40e_aq_debug_write_register(hw,
7770 I40E_VSI_TSR(vsi->vsi_id),
7773 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7775 return I40E_ERR_CONFIG;
7779 /* Configure for double VLAN TX insertion */
7780 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7781 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7782 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7783 ret = i40e_aq_debug_write_register(hw,
7784 I40E_VSI_L2TAGSTXVALID(
7785 vsi->vsi_id), reg, NULL);
7787 PMD_DRV_LOG(ERR, "Failed to update "
7788 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7789 return I40E_ERR_CONFIG;
7797 * i40e_aq_add_mirror_rule
7798 * @hw: pointer to the hardware structure
7799 * @seid: VEB seid to add mirror rule to
7800 * @dst_id: destination vsi seid
7801 * @entries: Buffer which contains the entities to be mirrored
7802 * @count: number of entities contained in the buffer
7803 * @rule_id:the rule_id of the rule to be added
7805 * Add a mirror rule for a given veb.
7808 static enum i40e_status_code
7809 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7810 uint16_t seid, uint16_t dst_id,
7811 uint16_t rule_type, uint16_t *entries,
7812 uint16_t count, uint16_t *rule_id)
7814 struct i40e_aq_desc desc;
7815 struct i40e_aqc_add_delete_mirror_rule cmd;
7816 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7817 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7820 enum i40e_status_code status;
7822 i40e_fill_default_direct_cmd_desc(&desc,
7823 i40e_aqc_opc_add_mirror_rule);
7824 memset(&cmd, 0, sizeof(cmd));
7826 buff_len = sizeof(uint16_t) * count;
7827 desc.datalen = rte_cpu_to_le_16(buff_len);
7829 desc.flags |= rte_cpu_to_le_16(
7830 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7831 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7832 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7833 cmd.num_entries = rte_cpu_to_le_16(count);
7834 cmd.seid = rte_cpu_to_le_16(seid);
7835 cmd.destination = rte_cpu_to_le_16(dst_id);
7837 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7838 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7839 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7841 " mirror_rules_used = %u, mirror_rules_free = %u,",
7842 hw->aq.asq_last_status, resp->rule_id,
7843 resp->mirror_rules_used, resp->mirror_rules_free);
7844 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7850 * i40e_aq_del_mirror_rule
7851 * @hw: pointer to the hardware structure
7852 * @seid: VEB seid to add mirror rule to
7853 * @entries: Buffer which contains the entities to be mirrored
7854 * @count: number of entities contained in the buffer
7855 * @rule_id:the rule_id of the rule to be delete
7857 * Delete a mirror rule for a given veb.
7860 static enum i40e_status_code
7861 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7862 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7863 uint16_t count, uint16_t rule_id)
7865 struct i40e_aq_desc desc;
7866 struct i40e_aqc_add_delete_mirror_rule cmd;
7867 uint16_t buff_len = 0;
7868 enum i40e_status_code status;
7871 i40e_fill_default_direct_cmd_desc(&desc,
7872 i40e_aqc_opc_delete_mirror_rule);
7873 memset(&cmd, 0, sizeof(cmd));
7874 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7875 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7877 cmd.num_entries = count;
7878 buff_len = sizeof(uint16_t) * count;
7879 desc.datalen = rte_cpu_to_le_16(buff_len);
7880 buff = (void *)entries;
7882 /* rule id is filled in destination field for deleting mirror rule */
7883 cmd.destination = rte_cpu_to_le_16(rule_id);
7885 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7886 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7887 cmd.seid = rte_cpu_to_le_16(seid);
7889 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7890 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7896 * i40e_mirror_rule_set
7897 * @dev: pointer to the hardware structure
7898 * @mirror_conf: mirror rule info
7899 * @sw_id: mirror rule's sw_id
7900 * @on: enable/disable
7902 * set a mirror rule.
7906 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7907 struct rte_eth_mirror_conf *mirror_conf,
7908 uint8_t sw_id, uint8_t on)
7910 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7911 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7912 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7913 struct i40e_mirror_rule *parent = NULL;
7914 uint16_t seid, dst_seid, rule_id;
7918 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7920 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7921 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7922 " without veb or vfs.");
7925 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7926 PMD_DRV_LOG(ERR, "mirror table is full.");
7929 if (mirror_conf->dst_pool > pf->vf_num) {
7930 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7931 mirror_conf->dst_pool);
7935 seid = pf->main_vsi->veb->seid;
7937 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7938 if (sw_id <= it->index) {
7944 if (mirr_rule && sw_id == mirr_rule->index) {
7946 PMD_DRV_LOG(ERR, "mirror rule exists.");
7949 ret = i40e_aq_del_mirror_rule(hw, seid,
7950 mirr_rule->rule_type,
7952 mirr_rule->num_entries, mirr_rule->id);
7954 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7955 " ret = %d, aq_err = %d.",
7956 ret, hw->aq.asq_last_status);
7959 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7960 rte_free(mirr_rule);
7961 pf->nb_mirror_rule--;
7965 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7969 mirr_rule = rte_zmalloc("i40e_mirror_rule",
7970 sizeof(struct i40e_mirror_rule) , 0);
7972 PMD_DRV_LOG(ERR, "failed to allocate memory");
7973 return I40E_ERR_NO_MEMORY;
7975 switch (mirror_conf->rule_type) {
7976 case ETH_MIRROR_VLAN:
7977 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7978 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7979 mirr_rule->entries[j] =
7980 mirror_conf->vlan.vlan_id[i];
7985 PMD_DRV_LOG(ERR, "vlan is not specified.");
7986 rte_free(mirr_rule);
7989 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7991 case ETH_MIRROR_VIRTUAL_POOL_UP:
7992 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7993 /* check if the specified pool bit is out of range */
7994 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7995 PMD_DRV_LOG(ERR, "pool mask is out of range.");
7996 rte_free(mirr_rule);
7999 for (i = 0, j = 0; i < pf->vf_num; i++) {
8000 if (mirror_conf->pool_mask & (1ULL << i)) {
8001 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8005 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8006 /* add pf vsi to entries */
8007 mirr_rule->entries[j] = pf->main_vsi_seid;
8011 PMD_DRV_LOG(ERR, "pool is not specified.");
8012 rte_free(mirr_rule);
8015 /* egress and ingress in aq commands means from switch but not port */
8016 mirr_rule->rule_type =
8017 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8018 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8019 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8021 case ETH_MIRROR_UPLINK_PORT:
8022 /* egress and ingress in aq commands means from switch but not port*/
8023 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8025 case ETH_MIRROR_DOWNLINK_PORT:
8026 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8029 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8030 mirror_conf->rule_type);
8031 rte_free(mirr_rule);
8035 /* If the dst_pool is equal to vf_num, consider it as PF */
8036 if (mirror_conf->dst_pool == pf->vf_num)
8037 dst_seid = pf->main_vsi_seid;
8039 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8041 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8042 mirr_rule->rule_type, mirr_rule->entries,
8045 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8046 " ret = %d, aq_err = %d.",
8047 ret, hw->aq.asq_last_status);
8048 rte_free(mirr_rule);
8052 mirr_rule->index = sw_id;
8053 mirr_rule->num_entries = j;
8054 mirr_rule->id = rule_id;
8055 mirr_rule->dst_vsi_seid = dst_seid;
8058 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8060 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8062 pf->nb_mirror_rule++;
8067 * i40e_mirror_rule_reset
8068 * @dev: pointer to the device
8069 * @sw_id: mirror rule's sw_id
8071 * reset a mirror rule.
8075 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8077 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8078 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8079 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8083 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8085 seid = pf->main_vsi->veb->seid;
8087 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8088 if (sw_id == it->index) {
8094 ret = i40e_aq_del_mirror_rule(hw, seid,
8095 mirr_rule->rule_type,
8097 mirr_rule->num_entries, mirr_rule->id);
8099 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8100 " status = %d, aq_err = %d.",
8101 ret, hw->aq.asq_last_status);
8104 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8105 rte_free(mirr_rule);
8106 pf->nb_mirror_rule--;
8108 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8115 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8117 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8118 uint64_t systim_cycles;
8120 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8121 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8124 return systim_cycles;
8128 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8130 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8133 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8134 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8141 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8143 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8146 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8147 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8154 i40e_start_timecounters(struct rte_eth_dev *dev)
8156 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8157 struct i40e_adapter *adapter =
8158 (struct i40e_adapter *)dev->data->dev_private;
8159 struct rte_eth_link link;
8160 uint32_t tsync_inc_l;
8161 uint32_t tsync_inc_h;
8163 /* Get current link speed. */
8164 memset(&link, 0, sizeof(link));
8165 i40e_dev_link_update(dev, 1);
8166 rte_i40e_dev_atomic_read_link_status(dev, &link);
8168 switch (link.link_speed) {
8169 case ETH_SPEED_NUM_40G:
8170 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8171 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8173 case ETH_SPEED_NUM_10G:
8174 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8175 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8177 case ETH_SPEED_NUM_1G:
8178 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8179 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8186 /* Set the timesync increment value. */
8187 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8188 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8190 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8191 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8192 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8194 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8195 adapter->systime_tc.cc_shift = 0;
8196 adapter->systime_tc.nsec_mask = 0;
8198 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8199 adapter->rx_tstamp_tc.cc_shift = 0;
8200 adapter->rx_tstamp_tc.nsec_mask = 0;
8202 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8203 adapter->tx_tstamp_tc.cc_shift = 0;
8204 adapter->tx_tstamp_tc.nsec_mask = 0;
8208 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8210 struct i40e_adapter *adapter =
8211 (struct i40e_adapter *)dev->data->dev_private;
8213 adapter->systime_tc.nsec += delta;
8214 adapter->rx_tstamp_tc.nsec += delta;
8215 adapter->tx_tstamp_tc.nsec += delta;
8221 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8224 struct i40e_adapter *adapter =
8225 (struct i40e_adapter *)dev->data->dev_private;
8227 ns = rte_timespec_to_ns(ts);
8229 /* Set the timecounters to a new value. */
8230 adapter->systime_tc.nsec = ns;
8231 adapter->rx_tstamp_tc.nsec = ns;
8232 adapter->tx_tstamp_tc.nsec = ns;
8238 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8240 uint64_t ns, systime_cycles;
8241 struct i40e_adapter *adapter =
8242 (struct i40e_adapter *)dev->data->dev_private;
8244 systime_cycles = i40e_read_systime_cyclecounter(dev);
8245 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8246 *ts = rte_ns_to_timespec(ns);
8252 i40e_timesync_enable(struct rte_eth_dev *dev)
8254 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8255 uint32_t tsync_ctl_l;
8256 uint32_t tsync_ctl_h;
8258 /* Stop the timesync system time. */
8259 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8260 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8261 /* Reset the timesync system time value. */
8262 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8263 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8265 i40e_start_timecounters(dev);
8267 /* Clear timesync registers. */
8268 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8269 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8270 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8271 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8272 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8273 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8275 /* Enable timestamping of PTP packets. */
8276 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8277 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8279 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8280 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8281 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8283 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8284 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8290 i40e_timesync_disable(struct rte_eth_dev *dev)
8292 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8293 uint32_t tsync_ctl_l;
8294 uint32_t tsync_ctl_h;
8296 /* Disable timestamping of transmitted PTP packets. */
8297 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8298 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8300 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8301 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8303 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8304 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8306 /* Reset the timesync increment value. */
8307 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8308 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8314 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8315 struct timespec *timestamp, uint32_t flags)
8317 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8318 struct i40e_adapter *adapter =
8319 (struct i40e_adapter *)dev->data->dev_private;
8321 uint32_t sync_status;
8322 uint32_t index = flags & 0x03;
8323 uint64_t rx_tstamp_cycles;
8326 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8327 if ((sync_status & (1 << index)) == 0)
8330 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8331 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8332 *timestamp = rte_ns_to_timespec(ns);
8338 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8339 struct timespec *timestamp)
8341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8342 struct i40e_adapter *adapter =
8343 (struct i40e_adapter *)dev->data->dev_private;
8345 uint32_t sync_status;
8346 uint64_t tx_tstamp_cycles;
8349 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8350 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8353 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8354 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8355 *timestamp = rte_ns_to_timespec(ns);
8361 * i40e_parse_dcb_configure - parse dcb configure from user
8362 * @dev: the device being configured
8363 * @dcb_cfg: pointer of the result of parse
8364 * @*tc_map: bit map of enabled traffic classes
8366 * Returns 0 on success, negative value on failure
8369 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8370 struct i40e_dcbx_config *dcb_cfg,
8373 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8374 uint8_t i, tc_bw, bw_lf;
8376 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8378 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8379 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8380 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8384 /* assume each tc has the same bw */
8385 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8386 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8387 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8388 /* to ensure the sum of tcbw is equal to 100 */
8389 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8390 for (i = 0; i < bw_lf; i++)
8391 dcb_cfg->etscfg.tcbwtable[i]++;
8393 /* assume each tc has the same Transmission Selection Algorithm */
8394 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8395 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8397 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8398 dcb_cfg->etscfg.prioritytable[i] =
8399 dcb_rx_conf->dcb_tc[i];
8401 /* FW needs one App to configure HW */
8402 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8403 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8404 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8405 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8407 if (dcb_rx_conf->nb_tcs == 0)
8408 *tc_map = 1; /* tc0 only */
8410 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8412 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8413 dcb_cfg->pfc.willing = 0;
8414 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8415 dcb_cfg->pfc.pfcenable = *tc_map;
8421 static enum i40e_status_code
8422 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8423 struct i40e_aqc_vsi_properties_data *info,
8424 uint8_t enabled_tcmap)
8426 enum i40e_status_code ret;
8427 int i, total_tc = 0;
8428 uint16_t qpnum_per_tc, bsf, qp_idx;
8429 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8430 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8431 uint16_t used_queues;
8433 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8434 if (ret != I40E_SUCCESS)
8437 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8438 if (enabled_tcmap & (1 << i))
8443 vsi->enabled_tc = enabled_tcmap;
8445 /* different VSI has different queues assigned */
8446 if (vsi->type == I40E_VSI_MAIN)
8447 used_queues = dev_data->nb_rx_queues -
8448 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8449 else if (vsi->type == I40E_VSI_VMDQ2)
8450 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8452 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8453 return I40E_ERR_NO_AVAILABLE_VSI;
8456 qpnum_per_tc = used_queues / total_tc;
8457 /* Number of queues per enabled TC */
8458 if (qpnum_per_tc == 0) {
8459 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8460 return I40E_ERR_INVALID_QP_ID;
8462 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8464 bsf = rte_bsf32(qpnum_per_tc);
8467 * Configure TC and queue mapping parameters, for enabled TC,
8468 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8469 * default queue will serve it.
8472 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8473 if (vsi->enabled_tc & (1 << i)) {
8474 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8475 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8476 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8477 qp_idx += qpnum_per_tc;
8479 info->tc_mapping[i] = 0;
8482 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8483 if (vsi->type == I40E_VSI_SRIOV) {
8484 info->mapping_flags |=
8485 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8486 for (i = 0; i < vsi->nb_qps; i++)
8487 info->queue_mapping[i] =
8488 rte_cpu_to_le_16(vsi->base_queue + i);
8490 info->mapping_flags |=
8491 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8492 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8494 info->valid_sections |=
8495 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8497 return I40E_SUCCESS;
8501 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8502 * @veb: VEB to be configured
8503 * @tc_map: enabled TC bitmap
8505 * Returns 0 on success, negative value on failure
8507 static enum i40e_status_code
8508 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8510 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8511 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8512 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8513 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8514 enum i40e_status_code ret = I40E_SUCCESS;
8518 /* Check if enabled_tc is same as existing or new TCs */
8519 if (veb->enabled_tc == tc_map)
8522 /* configure tc bandwidth */
8523 memset(&veb_bw, 0, sizeof(veb_bw));
8524 veb_bw.tc_valid_bits = tc_map;
8525 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8526 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8527 if (tc_map & BIT_ULL(i))
8528 veb_bw.tc_bw_share_credits[i] = 1;
8530 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8533 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8534 " per TC failed = %d",
8535 hw->aq.asq_last_status);
8539 memset(&ets_query, 0, sizeof(ets_query));
8540 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8542 if (ret != I40E_SUCCESS) {
8543 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8544 " configuration %u", hw->aq.asq_last_status);
8547 memset(&bw_query, 0, sizeof(bw_query));
8548 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8550 if (ret != I40E_SUCCESS) {
8551 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8552 " configuration %u", hw->aq.asq_last_status);
8556 /* store and print out BW info */
8557 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8558 veb->bw_info.bw_max = ets_query.tc_bw_max;
8559 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8560 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8561 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8562 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8564 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8565 veb->bw_info.bw_ets_share_credits[i] =
8566 bw_query.tc_bw_share_credits[i];
8567 veb->bw_info.bw_ets_credits[i] =
8568 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8569 /* 4 bits per TC, 4th bit is reserved */
8570 veb->bw_info.bw_ets_max[i] =
8571 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8572 RTE_LEN2MASK(3, uint8_t));
8573 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8574 veb->bw_info.bw_ets_share_credits[i]);
8575 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8576 veb->bw_info.bw_ets_credits[i]);
8577 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8578 veb->bw_info.bw_ets_max[i]);
8581 veb->enabled_tc = tc_map;
8588 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8589 * @vsi: VSI to be configured
8590 * @tc_map: enabled TC bitmap
8592 * Returns 0 on success, negative value on failure
8594 static enum i40e_status_code
8595 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8597 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8598 struct i40e_vsi_context ctxt;
8599 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8600 enum i40e_status_code ret = I40E_SUCCESS;
8603 /* Check if enabled_tc is same as existing or new TCs */
8604 if (vsi->enabled_tc == tc_map)
8607 /* configure tc bandwidth */
8608 memset(&bw_data, 0, sizeof(bw_data));
8609 bw_data.tc_valid_bits = tc_map;
8610 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8611 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8612 if (tc_map & BIT_ULL(i))
8613 bw_data.tc_bw_credits[i] = 1;
8615 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8617 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8618 " per TC failed = %d",
8619 hw->aq.asq_last_status);
8622 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8623 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8625 /* Update Queue Pairs Mapping for currently enabled UPs */
8626 ctxt.seid = vsi->seid;
8627 ctxt.pf_num = hw->pf_id;
8629 ctxt.uplink_seid = vsi->uplink_seid;
8630 ctxt.info = vsi->info;
8632 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8636 /* Update the VSI after updating the VSI queue-mapping information */
8637 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8639 PMD_INIT_LOG(ERR, "Failed to configure "
8640 "TC queue mapping = %d",
8641 hw->aq.asq_last_status);
8644 /* update the local VSI info with updated queue map */
8645 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8646 sizeof(vsi->info.tc_mapping));
8647 (void)rte_memcpy(&vsi->info.queue_mapping,
8648 &ctxt.info.queue_mapping,
8649 sizeof(vsi->info.queue_mapping));
8650 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8651 vsi->info.valid_sections = 0;
8653 /* query and update current VSI BW information */
8654 ret = i40e_vsi_get_bw_config(vsi);
8657 "Failed updating vsi bw info, err %s aq_err %s",
8658 i40e_stat_str(hw, ret),
8659 i40e_aq_str(hw, hw->aq.asq_last_status));
8663 vsi->enabled_tc = tc_map;
8670 * i40e_dcb_hw_configure - program the dcb setting to hw
8671 * @pf: pf the configuration is taken on
8672 * @new_cfg: new configuration
8673 * @tc_map: enabled TC bitmap
8675 * Returns 0 on success, negative value on failure
8677 static enum i40e_status_code
8678 i40e_dcb_hw_configure(struct i40e_pf *pf,
8679 struct i40e_dcbx_config *new_cfg,
8682 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8683 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8684 struct i40e_vsi *main_vsi = pf->main_vsi;
8685 struct i40e_vsi_list *vsi_list;
8686 enum i40e_status_code ret;
8690 /* Use the FW API if FW > v4.4*/
8691 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8692 (hw->aq.fw_maj_ver >= 5))) {
8693 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8694 " to configure DCB");
8695 return I40E_ERR_FIRMWARE_API_VERSION;
8698 /* Check if need reconfiguration */
8699 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8700 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8701 return I40E_SUCCESS;
8704 /* Copy the new config to the current config */
8705 *old_cfg = *new_cfg;
8706 old_cfg->etsrec = old_cfg->etscfg;
8707 ret = i40e_set_dcb_config(hw);
8710 "Set DCB Config failed, err %s aq_err %s\n",
8711 i40e_stat_str(hw, ret),
8712 i40e_aq_str(hw, hw->aq.asq_last_status));
8715 /* set receive Arbiter to RR mode and ETS scheme by default */
8716 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8717 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8718 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8719 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8720 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8721 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8722 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8723 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8724 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8725 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8726 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8727 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8728 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8730 /* get local mib to check whether it is configured correctly */
8732 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8733 /* Get Local DCB Config */
8734 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8735 &hw->local_dcbx_config);
8737 /* if Veb is created, need to update TC of it at first */
8738 if (main_vsi->veb) {
8739 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8741 PMD_INIT_LOG(WARNING,
8742 "Failed configuring TC for VEB seid=%d\n",
8743 main_vsi->veb->seid);
8745 /* Update each VSI */
8746 i40e_vsi_config_tc(main_vsi, tc_map);
8747 if (main_vsi->veb) {
8748 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8749 /* Beside main VSI and VMDQ VSIs, only enable default
8752 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8753 ret = i40e_vsi_config_tc(vsi_list->vsi,
8756 ret = i40e_vsi_config_tc(vsi_list->vsi,
8757 I40E_DEFAULT_TCMAP);
8759 PMD_INIT_LOG(WARNING,
8760 "Failed configuring TC for VSI seid=%d\n",
8761 vsi_list->vsi->seid);
8765 return I40E_SUCCESS;
8769 * i40e_dcb_init_configure - initial dcb config
8770 * @dev: device being configured
8771 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8773 * Returns 0 on success, negative value on failure
8776 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8778 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8779 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8782 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8783 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8787 /* DCB initialization:
8788 * Update DCB configuration from the Firmware and configure
8789 * LLDP MIB change event.
8791 if (sw_dcb == TRUE) {
8792 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8793 if (ret != I40E_SUCCESS)
8794 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8796 ret = i40e_init_dcb(hw);
8797 /* if sw_dcb, lldp agent is stopped, the return from
8798 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8801 if (ret != I40E_SUCCESS &&
8802 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8803 memset(&hw->local_dcbx_config, 0,
8804 sizeof(struct i40e_dcbx_config));
8805 /* set dcb default configuration */
8806 hw->local_dcbx_config.etscfg.willing = 0;
8807 hw->local_dcbx_config.etscfg.maxtcs = 0;
8808 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8809 hw->local_dcbx_config.etscfg.tsatable[0] =
8811 hw->local_dcbx_config.etsrec =
8812 hw->local_dcbx_config.etscfg;
8813 hw->local_dcbx_config.pfc.willing = 0;
8814 hw->local_dcbx_config.pfc.pfccap =
8815 I40E_MAX_TRAFFIC_CLASS;
8816 /* FW needs one App to configure HW */
8817 hw->local_dcbx_config.numapps = 1;
8818 hw->local_dcbx_config.app[0].selector =
8819 I40E_APP_SEL_ETHTYPE;
8820 hw->local_dcbx_config.app[0].priority = 3;
8821 hw->local_dcbx_config.app[0].protocolid =
8822 I40E_APP_PROTOID_FCOE;
8823 ret = i40e_set_dcb_config(hw);
8825 PMD_INIT_LOG(ERR, "default dcb config fails."
8826 " err = %d, aq_err = %d.", ret,
8827 hw->aq.asq_last_status);
8831 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8832 " aq_err = %d.", ret,
8833 hw->aq.asq_last_status);
8837 ret = i40e_aq_start_lldp(hw, NULL);
8838 if (ret != I40E_SUCCESS)
8839 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8841 ret = i40e_init_dcb(hw);
8843 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8844 PMD_INIT_LOG(ERR, "HW doesn't support"
8849 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8850 " aq_err = %d.", ret,
8851 hw->aq.asq_last_status);
8859 * i40e_dcb_setup - setup dcb related config
8860 * @dev: device being configured
8862 * Returns 0 on success, negative value on failure
8865 i40e_dcb_setup(struct rte_eth_dev *dev)
8867 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8868 struct i40e_dcbx_config dcb_cfg;
8872 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8873 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8877 if (pf->vf_num != 0)
8878 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8880 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8882 PMD_INIT_LOG(ERR, "invalid dcb config");
8885 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8887 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8895 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8896 struct rte_eth_dcb_info *dcb_info)
8898 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8899 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8900 struct i40e_vsi *vsi = pf->main_vsi;
8901 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8902 uint16_t bsf, tc_mapping;
8905 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8906 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8908 dcb_info->nb_tcs = 1;
8909 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8910 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8911 for (i = 0; i < dcb_info->nb_tcs; i++)
8912 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8914 /* get queue mapping if vmdq is disabled */
8915 if (!pf->nb_cfg_vmdq_vsi) {
8916 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8917 if (!(vsi->enabled_tc & (1 << i)))
8919 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8920 dcb_info->tc_queue.tc_rxq[j][i].base =
8921 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8922 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8923 dcb_info->tc_queue.tc_txq[j][i].base =
8924 dcb_info->tc_queue.tc_rxq[j][i].base;
8925 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8926 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8927 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8928 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8929 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8934 /* get queue mapping if vmdq is enabled */
8936 vsi = pf->vmdq[j].vsi;
8937 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8938 if (!(vsi->enabled_tc & (1 << i)))
8940 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8941 dcb_info->tc_queue.tc_rxq[j][i].base =
8942 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8943 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8944 dcb_info->tc_queue.tc_txq[j][i].base =
8945 dcb_info->tc_queue.tc_rxq[j][i].base;
8946 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8947 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8948 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8949 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8950 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8953 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8958 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8960 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8961 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8963 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8966 msix_intr = intr_handle->intr_vec[queue_id];
8967 if (msix_intr == I40E_MISC_VEC_ID)
8968 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8969 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8970 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8971 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8973 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8976 I40E_PFINT_DYN_CTLN(msix_intr -
8978 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8979 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8980 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8982 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8984 I40E_WRITE_FLUSH(hw);
8985 rte_intr_enable(&dev->pci_dev->intr_handle);
8991 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8993 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8994 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8997 msix_intr = intr_handle->intr_vec[queue_id];
8998 if (msix_intr == I40E_MISC_VEC_ID)
8999 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9002 I40E_PFINT_DYN_CTLN(msix_intr -
9005 I40E_WRITE_FLUSH(hw);
9010 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9012 /* Highest base addr + 32-bit word */
9013 return I40E_GLGEN_STAT_CLEAR + 4;
9016 static int i40e_get_regs(struct rte_eth_dev *dev,
9017 struct rte_dev_reg_info *regs)
9019 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9020 uint32_t *ptr_data = regs->data;
9021 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9022 const struct i40e_reg_info *reg_info;
9024 /* The first few registers have to be read using AQ operations */
9026 while (i40e_regs_adminq[reg_idx].name) {
9027 reg_info = &i40e_regs_adminq[reg_idx++];
9028 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9030 arr_idx2 <= reg_info->count2;
9032 reg_offset = arr_idx * reg_info->stride1 +
9033 arr_idx2 * reg_info->stride2;
9034 ptr_data[reg_offset >> 2] =
9035 i40e_read_rx_ctl(hw, reg_offset);
9039 /* The remaining registers can be read using primitives */
9041 while (i40e_regs_others[reg_idx].name) {
9042 reg_info = &i40e_regs_others[reg_idx++];
9043 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9045 arr_idx2 <= reg_info->count2;
9047 reg_offset = arr_idx * reg_info->stride1 +
9048 arr_idx2 * reg_info->stride2;
9049 ptr_data[reg_offset >> 2] =
9050 I40E_READ_REG(hw, reg_offset);
9057 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9059 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9061 /* Convert word count to byte count */
9062 return hw->nvm.sr_size << 1;
9065 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9066 struct rte_dev_eeprom_info *eeprom)
9068 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9069 uint16_t *data = eeprom->data;
9070 uint16_t offset, length, cnt_words;
9073 offset = eeprom->offset >> 1;
9074 length = eeprom->length >> 1;
9077 if (offset > hw->nvm.sr_size ||
9078 offset + length > hw->nvm.sr_size) {
9079 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9083 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9085 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9086 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9087 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9094 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9095 struct ether_addr *mac_addr)
9097 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9099 if (!is_valid_assigned_ether_addr(mac_addr)) {
9100 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9104 /* Flags: 0x3 updates port address */
9105 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);