drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  79
  80 /* Flow control default timer */
  81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  82
  83 /* Flow control default high water */
  84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  85
  86 /* Flow control default low water */
  87 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Receive Average Packet Size in Byte*/
  99 #define I40E_PACKET_AVERAGE_SIZE 128
 100
 101 /* Mask of PF interrupt causes */
 102 #define I40E_PFINT_ICR0_ENA_MASK ( \
 103                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 104                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 105                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 106                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 107                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 109                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 113
 114 #define I40E_FLOW_TYPES ( \
 115         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 116         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 126
 127 /* Additional timesync values. */
 128 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA     0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 133 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 134
 135 #define I40E_MAX_PERCENT            100
 136 #define I40E_DEFAULT_DCB_APP_NUM    1
 137 #define I40E_DEFAULT_DCB_APP_PRIO   3
 138
 139 #define I40E_INSET_NONE            0x00000000000000000ULL
 140
 141 /* bit0 ~ bit 7 */
 142 #define I40E_INSET_DMAC            0x0000000000000001ULL
 143 #define I40E_INSET_SMAC            0x0000000000000002ULL
 144 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 145 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 146 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 147
 148 /* bit 8 ~ bit 15 */
 149 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 150 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 151 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 152 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 153 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 154 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 155 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 156
 157 /* bit 16 ~ bit 31 */
 158 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 159 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 160 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 161 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 162 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 163 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 164 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 165 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 166
 167 /* bit 32 ~ bit 47, tunnel fields */
 168 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 169 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 170 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 171 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 172 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 173 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 174
 175 /* bit 48 ~ bit 55 */
 176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 177
 178 /* bit 56 ~ bit 63, Flex Payload */
 179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD \
 188         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 189         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 190         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 191         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 192
 193 /**
 194  * Below are values for writing un-exposed registers suggested
 195  * by silicon experts
 196  */
 197 /* Destination MAC address */
 198 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 199 /* Source MAC address */
 200 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 201 /* VLAN tag in the outer L2 header */
 202 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0080000000000000ULL
 203 /* VLAN tag in the inner L2 header */
 204 #define I40E_REG_INSET_L2_INNER_VLAN             0x0100000000000000ULL
 205 /* Source IPv4 address */
 206 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 207 /* Destination IPv4 address */
 208 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 209 /* IPv4 Type of Service (TOS) */
 210 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 211 /* IPv4 Protocol */
 212 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 213 /* Source IPv6 address */
 214 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 215 /* Destination IPv6 address */
 216 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 217 /* IPv6 Traffic Class (TC) */
 218 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 219 /* IPv6 Next Header */
 220 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 221 /* Source L4 port */
 222 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 223 /* Destination L4 port */
 224 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 225 /* SCTP verification tag */
 226 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 227 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 228 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 229 /* Source port of tunneling UDP */
 230 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 231 /* Destination port of tunneling UDP */
 232 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 233 /* UDP Tunneling ID, NVGRE/GRE key */
 234 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 235 /* Last ether type */
 236 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 237 /* Tunneling outer destination IPv4 address */
 238 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 239 /* Tunneling outer destination IPv6 address */
 240 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 241 /* 1st word of flex payload */
 242 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 243 /* 2nd word of flex payload */
 244 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 245 /* 3rd word of flex payload */
 246 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 247 /* 4th word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 249 /* 5th word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 251 /* 6th word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 253 /* 7th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 255 /* 8th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 257 /* all 8 words flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 259 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 260
 261 #define I40E_TRANSLATE_INSET 0
 262 #define I40E_TRANSLATE_REG   1
 263
 264 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 265 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 266 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 267 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 268
 269 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 270 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 271 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 272         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 273
 274 /* PCI offset for querying capability */
 275 #define PCI_DEV_CAP_REG            0xA4
 276 /* PCI offset for enabling/disabling Extended Tag */
 277 #define PCI_DEV_CTRL_REG           0xA8
 278 /* Bit mask of Extended Tag capability */
 279 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 280 /* Bit shift of Extended Tag enable/disable */
 281 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 282 /* Bit mask of Extended Tag enable/disable */
 283 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 284
 285 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 286 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 287 static int i40e_dev_configure(struct rte_eth_dev *dev);
 288 static int i40e_dev_start(struct rte_eth_dev *dev);
 289 static void i40e_dev_stop(struct rte_eth_dev *dev);
 290 static void i40e_dev_close(struct rte_eth_dev *dev);
 291 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 292 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 293 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 294 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 295 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 296 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 297 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 298                                struct rte_eth_stats *stats);
 299 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 300                                struct rte_eth_xstats *xstats, unsigned n);
 301 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 302 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 303                                             uint16_t queue_id,
 304                                             uint8_t stat_idx,
 305                                             uint8_t is_rx);
 306 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 307                               struct rte_eth_dev_info *dev_info);
 308 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 309                                 uint16_t vlan_id,
 310                                 int on);
 311 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 312                               enum rte_vlan_type vlan_type,
 313                               uint16_t tpid);
 314 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 315 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 316                                       uint16_t queue,
 317                                       int on);
 318 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 319 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 320 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 321 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 322                               struct rte_eth_fc_conf *fc_conf);
 323 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 324                               struct rte_eth_fc_conf *fc_conf);
 325 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 326                                        struct rte_eth_pfc_conf *pfc_conf);
 327 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 328                           struct ether_addr *mac_addr,
 329                           uint32_t index,
 330                           uint32_t pool);
 331 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 332 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 333                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 334                                     uint16_t reta_size);
 335 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 336                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 337                                    uint16_t reta_size);
 338
 339 static int i40e_get_cap(struct i40e_hw *hw);
 340 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 341 static int i40e_pf_setup(struct i40e_pf *pf);
 342 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 343 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 344 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 345 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 346 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 347                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 348 static void i40e_stat_update_48(struct i40e_hw *hw,
 349                                uint32_t hireg,
 350                                uint32_t loreg,
 351                                bool offset_loaded,
 352                                uint64_t *offset,
 353                                uint64_t *stat);
 354 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 355 static void i40e_dev_interrupt_handler(
 356                 __rte_unused struct rte_intr_handle *handle, void *param);
 357 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 358                                 uint32_t base, uint32_t num);
 359 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 360 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 361                         uint32_t base);
 362 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 363                         uint16_t num);
 364 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 365 static int i40e_veb_release(struct i40e_veb *veb);
 366 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 367                                                 struct i40e_vsi *vsi);
 368 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 369 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 370 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 371                                              struct i40e_macvlan_filter *mv_f,
 372                                              int num,
 373                                              struct ether_addr *addr);
 374 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 375                                              struct i40e_macvlan_filter *mv_f,
 376                                              int num,
 377                                              uint16_t vlan);
 378 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 379 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 380                                     struct rte_eth_rss_conf *rss_conf);
 381 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 382                                       struct rte_eth_rss_conf *rss_conf);
 383 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 384                                         struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 386                                         struct rte_eth_udp_tunnel *udp_tunnel);
 387 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 388 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 389                         struct rte_eth_ethertype_filter *filter,
 390                         bool add);
 391 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 392                                 enum rte_filter_op filter_op,
 393                                 void *arg);
 394 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 395                                 enum rte_filter_type filter_type,
 396                                 enum rte_filter_op filter_op,
 397                                 void *arg);
 398 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 399                                   struct rte_eth_dcb_info *dcb_info);
 400 static void i40e_configure_registers(struct i40e_hw *hw);
 401 static void i40e_hw_init(struct rte_eth_dev *dev);
 402 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 403 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 404                         struct rte_eth_mirror_conf *mirror_conf,
 405                         uint8_t sw_id, uint8_t on);
 406 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 407
 408 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 409 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 410 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 411                                            struct timespec *timestamp,
 412                                            uint32_t flags);
 413 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 414                                            struct timespec *timestamp);
 415 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 416
 417 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 418
 419 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 420                                    struct timespec *timestamp);
 421 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 422                                     const struct timespec *timestamp);
 423
 424 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 425                                          uint16_t queue_id);
 426 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 427                                           uint16_t queue_id);
 428
 429 static int i40e_get_reg_length(struct rte_eth_dev *dev);
 430
 431 static int i40e_get_regs(struct rte_eth_dev *dev,
 432                          struct rte_dev_reg_info *regs);
 433
 434 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 435
 436 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 437                            struct rte_dev_eeprom_info *eeprom);
 438
 439 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 440                                       struct ether_addr *mac_addr);
 441
 442 static const struct rte_pci_id pci_id_i40e_map[] = {
 443 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 444 #include "rte_pci_dev_ids.h"
 445 { .vendor_id = 0, /* sentinel */ },
 446 };
 447
 448 static const struct eth_dev_ops i40e_eth_dev_ops = {
 449         .dev_configure                = i40e_dev_configure,
 450         .dev_start                    = i40e_dev_start,
 451         .dev_stop                     = i40e_dev_stop,
 452         .dev_close                    = i40e_dev_close,
 453         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 454         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 455         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 456         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 457         .dev_set_link_up              = i40e_dev_set_link_up,
 458         .dev_set_link_down            = i40e_dev_set_link_down,
 459         .link_update                  = i40e_dev_link_update,
 460         .stats_get                    = i40e_dev_stats_get,
 461         .xstats_get                   = i40e_dev_xstats_get,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 483         .tx_queue_release             = i40e_dev_tx_queue_release,
 484         .dev_led_on                   = i40e_dev_led_on,
 485         .dev_led_off                  = i40e_dev_led_off,
 486         .flow_ctrl_get                = i40e_flow_ctrl_get,
 487         .flow_ctrl_set                = i40e_flow_ctrl_set,
 488         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 489         .mac_addr_add                 = i40e_macaddr_add,
 490         .mac_addr_remove              = i40e_macaddr_remove,
 491         .reta_update                  = i40e_dev_rss_reta_update,
 492         .reta_query                   = i40e_dev_rss_reta_query,
 493         .rss_hash_update              = i40e_dev_rss_hash_update,
 494         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 495         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 496         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 497         .filter_ctrl                  = i40e_dev_filter_ctrl,
 498         .rxq_info_get                 = i40e_rxq_info_get,
 499         .txq_info_get                 = i40e_txq_info_get,
 500         .mirror_rule_set              = i40e_mirror_rule_set,
 501         .mirror_rule_reset            = i40e_mirror_rule_reset,
 502         .timesync_enable              = i40e_timesync_enable,
 503         .timesync_disable             = i40e_timesync_disable,
 504         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 505         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 506         .get_dcb_info                 = i40e_dev_get_dcb_info,
 507         .timesync_adjust_time         = i40e_timesync_adjust_time,
 508         .timesync_read_time           = i40e_timesync_read_time,
 509         .timesync_write_time          = i40e_timesync_write_time,
 510         .get_reg_length               = i40e_get_reg_length,
 511         .get_reg                      = i40e_get_regs,
 512         .get_eeprom_length            = i40e_get_eeprom_length,
 513         .get_eeprom                   = i40e_get_eeprom,
 514         .mac_addr_set                 = i40e_set_default_mac_addr,
 515 };
 516
 517 /* store statistics names and its offset in stats structure */
 518 struct rte_i40e_xstats_name_off {
 519         char name[RTE_ETH_XSTATS_NAME_SIZE];
 520         unsigned offset;
 521 };
 522
 523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 524         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 525         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 526         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 527         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 528         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 529                 rx_unknown_protocol)},
 530         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 531         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 532         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 533         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 534 };
 535
 536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 537                 sizeof(rte_i40e_stats_strings[0]))
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 540         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 541                 tx_dropped_link_down)},
 542         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 543         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 544                 illegal_bytes)},
 545         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 546         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_local_faults)},
 548         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_remote_faults)},
 550         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_length_errors)},
 552         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 553         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 554         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 555         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 556         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 557         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_255)},
 561         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_511)},
 563         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1023)},
 565         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1522)},
 567         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_big)},
 569         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_undersize)},
 571         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_oversize)},
 573         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 574                 mac_short_packet_dropped)},
 575         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_fragments)},
 577         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 578         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 579         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_127)},
 581         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_255)},
 583         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_511)},
 585         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1023)},
 587         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1522)},
 589         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_big)},
 591         {"rx_flow_director_atr_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 593         {"rx_flow_director_sb_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 595         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 tx_lpi_status)},
 597         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 rx_lpi_status)},
 599         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_count)},
 601         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_count)},
 603 };
 604
 605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 606                 sizeof(rte_i40e_hw_port_strings[0]))
 607
 608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 609         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xon_rx)},
 611         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xoff_rx)},
 613 };
 614
 615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 616                 sizeof(rte_i40e_rxq_prio_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_tx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_tx)},
 623         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_2_xoff)},
 625 };
 626
 627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 628                 sizeof(rte_i40e_txq_prio_strings[0]))
 629
 630 static struct eth_driver rte_i40e_pmd = {
 631         .pci_drv = {
 632                 .name = "rte_i40e_pmd",
 633                 .id_table = pci_id_i40e_map,
 634                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 635                         RTE_PCI_DRV_DETACHABLE,
 636         },
 637         .eth_dev_init = eth_i40e_dev_init,
 638         .eth_dev_uninit = eth_i40e_dev_uninit,
 639         .dev_private_size = sizeof(struct i40e_adapter),
 640 };
 641
 642 static inline int
 643 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 644                                      struct rte_eth_link *link)
 645 {
 646         struct rte_eth_link *dst = link;
 647         struct rte_eth_link *src = &(dev->data->dev_link);
 648
 649         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 650                                         *(uint64_t *)src) == 0)
 651                 return -1;
 652
 653         return 0;
 654 }
 655
 656 static inline int
 657 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 658                                       struct rte_eth_link *link)
 659 {
 660         struct rte_eth_link *dst = &(dev->data->dev_link);
 661         struct rte_eth_link *src = link;
 662
 663         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 664                                         *(uint64_t *)src) == 0)
 665                 return -1;
 666
 667         return 0;
 668 }
 669
 670 /*
 671  * Driver initialization routine.
 672  * Invoked once at EAL init time.
 673  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 674  */
 675 static int
 676 rte_i40e_pmd_init(const char *name __rte_unused,
 677                   const char *params __rte_unused)
 678 {
 679         PMD_INIT_FUNC_TRACE();
 680         rte_eth_driver_register(&rte_i40e_pmd);
 681
 682         return 0;
 683 }
 684
 685 static struct rte_driver rte_i40e_driver = {
 686         .type = PMD_PDEV,
 687         .init = rte_i40e_pmd_init,
 688 };
 689
 690 PMD_REGISTER_DRIVER(rte_i40e_driver);
 691
 692 /*
 693  * Initialize registers for flexible payload, which should be set by NVM.
 694  * This should be removed from code once it is fixed in NVM.
 695  */
 696 #ifndef I40E_GLQF_ORT
 697 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 698 #endif
 699 #ifndef I40E_GLQF_PIT
 700 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 701 #endif
 702
 703 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 704 {
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 715
 716         /* GLQF_PIT Registers */
 717         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 718         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 719 }
 720
 721 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 722
 723 /*
 724  * Add a ethertype filter to drop all flow control frames transmitted
 725  * from VSIs.
 726 */
 727 static void
 728 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 729 {
 730         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 731         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 732                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 733                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 734         int ret;
 735
 736         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 737                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 738                                 pf->main_vsi_seid, 0,
 739                                 TRUE, NULL, NULL);
 740         if (ret)
 741                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 742                                   " frames from VSIs.");
 743 }
 744
 745 static int
 746 eth_i40e_dev_init(struct rte_eth_dev *dev)
 747 {
 748         struct rte_pci_device *pci_dev;
 749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 751         struct i40e_vsi *vsi;
 752         int ret;
 753         uint32_t len;
 754         uint8_t aq_fail = 0;
 755
 756         PMD_INIT_FUNC_TRACE();
 757
 758         dev->dev_ops = &i40e_eth_dev_ops;
 759         dev->rx_pkt_burst = i40e_recv_pkts;
 760         dev->tx_pkt_burst = i40e_xmit_pkts;
 761
 762         /* for secondary processes, we don't initialise any further as primary
 763          * has already done this work. Only check we don't need a different
 764          * RX function */
 765         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 766                 i40e_set_rx_function(dev);
 767                 i40e_set_tx_function(dev);
 768                 return 0;
 769         }
 770         pci_dev = dev->pci_dev;
 771
 772         rte_eth_copy_pci_info(dev, pci_dev);
 773
 774         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 775         pf->adapter->eth_dev = dev;
 776         pf->dev_data = dev->data;
 777
 778         hw->back = I40E_PF_TO_ADAPTER(pf);
 779         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 780         if (!hw->hw_addr) {
 781                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 782                              "as address is NULL");
 783                 return -ENODEV;
 784         }
 785
 786         hw->vendor_id = pci_dev->id.vendor_id;
 787         hw->device_id = pci_dev->id.device_id;
 788         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 789         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 790         hw->bus.device = pci_dev->addr.devid;
 791         hw->bus.func = pci_dev->addr.function;
 792         hw->adapter_stopped = 0;
 793
 794         /* Make sure all is clean before doing PF reset */
 795         i40e_clear_hw(hw);
 796
 797         /* Initialize the hardware */
 798         i40e_hw_init(dev);
 799
 800         /* Reset here to make sure all is clean for each PF */
 801         ret = i40e_pf_reset(hw);
 802         if (ret) {
 803                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 804                 return ret;
 805         }
 806
 807         /* Initialize the shared code (base driver) */
 808         ret = i40e_init_shared_code(hw);
 809         if (ret) {
 810                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 811                 return ret;
 812         }
 813
 814         /*
 815          * To work around the NVM issue,initialize registers
 816          * for flexible payload by software.
 817          * It should be removed once issues are fixed in NVM.
 818          */
 819         i40e_flex_payload_reg_init(hw);
 820
 821         /* Initialize the input set for filters (hash and fd) to default value */
 822         i40e_filter_input_set_init(pf);
 823
 824         /* Initialize the parameters for adminq */
 825         i40e_init_adminq_parameter(hw);
 826         ret = i40e_init_adminq(hw);
 827         if (ret != I40E_SUCCESS) {
 828                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 829                 return -EIO;
 830         }
 831         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 832                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 833                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 834                      ((hw->nvm.version >> 12) & 0xf),
 835                      ((hw->nvm.version >> 4) & 0xff),
 836                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 837
 838         /* Clear PXE mode */
 839         i40e_clear_pxe_mode(hw);
 840
 841         /*
 842          * On X710, performance number is far from the expectation on recent
 843          * firmware versions. The fix for this issue may not be integrated in
 844          * the following firmware version. So the workaround in software driver
 845          * is needed. It needs to modify the initial values of 3 internal only
 846          * registers. Note that the workaround can be removed when it is fixed
 847          * in firmware in the future.
 848          */
 849         i40e_configure_registers(hw);
 850
 851         /* Get hw capabilities */
 852         ret = i40e_get_cap(hw);
 853         if (ret != I40E_SUCCESS) {
 854                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 855                 goto err_get_capabilities;
 856         }
 857
 858         /* Initialize parameters for PF */
 859         ret = i40e_pf_parameter_init(dev);
 860         if (ret != 0) {
 861                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 862                 goto err_parameter_init;
 863         }
 864
 865         /* Initialize the queue management */
 866         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 867         if (ret < 0) {
 868                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 869                 goto err_qp_pool_init;
 870         }
 871         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 872                                 hw->func_caps.num_msix_vectors - 1);
 873         if (ret < 0) {
 874                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 875                 goto err_msix_pool_init;
 876         }
 877
 878         /* Initialize lan hmc */
 879         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 880                                 hw->func_caps.num_rx_qp, 0, 0);
 881         if (ret != I40E_SUCCESS) {
 882                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 883                 goto err_init_lan_hmc;
 884         }
 885
 886         /* Configure lan hmc */
 887         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 888         if (ret != I40E_SUCCESS) {
 889                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 890                 goto err_configure_lan_hmc;
 891         }
 892
 893         /* Get and check the mac address */
 894         i40e_get_mac_addr(hw, hw->mac.addr);
 895         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 896                 PMD_INIT_LOG(ERR, "mac address is not valid");
 897                 ret = -EIO;
 898                 goto err_get_mac_addr;
 899         }
 900         /* Copy the permanent MAC address */
 901         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 902                         (struct ether_addr *) hw->mac.perm_addr);
 903
 904         /* Disable flow control */
 905         hw->fc.requested_mode = I40E_FC_NONE;
 906         i40e_set_fc(hw, &aq_fail, TRUE);
 907
 908         /* Set the global registers with default ether type value */
 909         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 910         if (ret != I40E_SUCCESS) {
 911                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 912                              "VLAN ether type");
 913                 goto err_setup_pf_switch;
 914         }
 915         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 916         if (ret != I40E_SUCCESS) {
 917                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 918                              "VLAN ether type");
 919                 goto err_setup_pf_switch;
 920         }
 921
 922         /* PF setup, which includes VSI setup */
 923         ret = i40e_pf_setup(pf);
 924         if (ret) {
 925                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 926                 goto err_setup_pf_switch;
 927         }
 928
 929         vsi = pf->main_vsi;
 930
 931         /* Disable double vlan by default */
 932         i40e_vsi_config_double_vlan(vsi, FALSE);
 933
 934         if (!vsi->max_macaddrs)
 935                 len = ETHER_ADDR_LEN;
 936         else
 937                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 938
 939         /* Should be after VSI initialized */
 940         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 941         if (!dev->data->mac_addrs) {
 942                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 943                                         "for storing mac address");
 944                 goto err_mac_alloc;
 945         }
 946         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 947                                         &dev->data->mac_addrs[0]);
 948
 949         /* initialize pf host driver to setup SRIOV resource if applicable */
 950         i40e_pf_host_init(dev);
 951
 952         /* register callback func to eal lib */
 953         rte_intr_callback_register(&(pci_dev->intr_handle),
 954                 i40e_dev_interrupt_handler, (void *)dev);
 955
 956         /* configure and enable device interrupt */
 957         i40e_pf_config_irq0(hw, TRUE);
 958         i40e_pf_enable_irq0(hw);
 959
 960         /* enable uio intr after callback register */
 961         rte_intr_enable(&(pci_dev->intr_handle));
 962         /*
 963          * Add an ethertype filter to drop all flow control frames transmitted
 964          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 965          * frames to wire.
 966          */
 967         i40e_add_tx_flow_control_drop_filter(pf);
 968
 969         /* Set the max frame size to 0x2600 by default,
 970          * in case other drivers changed the default value.
 971          */
 972         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 973
 974         /* initialize mirror rule list */
 975         TAILQ_INIT(&pf->mirror_list);
 976
 977         /* Init dcb to sw mode by default */
 978         ret = i40e_dcb_init_configure(dev, TRUE);
 979         if (ret != I40E_SUCCESS) {
 980                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 981                 pf->flags &= ~I40E_FLAG_DCB;
 982         }
 983
 984         return 0;
 985
 986 err_mac_alloc:
 987         i40e_vsi_release(pf->main_vsi);
 988 err_setup_pf_switch:
 989 err_get_mac_addr:
 990 err_configure_lan_hmc:
 991         (void)i40e_shutdown_lan_hmc(hw);
 992 err_init_lan_hmc:
 993         i40e_res_pool_destroy(&pf->msix_pool);
 994 err_msix_pool_init:
 995         i40e_res_pool_destroy(&pf->qp_pool);
 996 err_qp_pool_init:
 997 err_parameter_init:
 998 err_get_capabilities:
 999         (void)i40e_shutdown_adminq(hw);
1000
1001         return ret;
1002 }
1003
1004 static int
1005 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1006 {
1007         struct rte_pci_device *pci_dev;
1008         struct i40e_hw *hw;
1009         struct i40e_filter_control_settings settings;
1010         int ret;
1011         uint8_t aq_fail = 0;
1012
1013         PMD_INIT_FUNC_TRACE();
1014
1015         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1016                 return 0;
1017
1018         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1019         pci_dev = dev->pci_dev;
1020
1021         if (hw->adapter_stopped == 0)
1022                 i40e_dev_close(dev);
1023
1024         dev->dev_ops = NULL;
1025         dev->rx_pkt_burst = NULL;
1026         dev->tx_pkt_burst = NULL;
1027
1028         /* Disable LLDP */
1029         ret = i40e_aq_stop_lldp(hw, true, NULL);
1030         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1031                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1032
1033         /* Clear PXE mode */
1034         i40e_clear_pxe_mode(hw);
1035
1036         /* Unconfigure filter control */
1037         memset(&settings, 0, sizeof(settings));
1038         ret = i40e_set_filter_control(hw, &settings);
1039         if (ret)
1040                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1041                                         ret);
1042
1043         /* Disable flow control */
1044         hw->fc.requested_mode = I40E_FC_NONE;
1045         i40e_set_fc(hw, &aq_fail, TRUE);
1046
1047         /* uninitialize pf host driver */
1048         i40e_pf_host_uninit(dev);
1049
1050         rte_free(dev->data->mac_addrs);
1051         dev->data->mac_addrs = NULL;
1052
1053         /* disable uio intr before callback unregister */
1054         rte_intr_disable(&(pci_dev->intr_handle));
1055
1056         /* register callback func to eal lib */
1057         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1058                 i40e_dev_interrupt_handler, (void *)dev);
1059
1060         return 0;
1061 }
1062
1063 static int
1064 i40e_dev_configure(struct rte_eth_dev *dev)
1065 {
1066         struct i40e_adapter *ad =
1067                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1068         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1069         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1070         int i, ret;
1071
1072         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1073          * bulk allocation or vector Rx preconditions we will reset it.
1074          */
1075         ad->rx_bulk_alloc_allowed = true;
1076         ad->rx_vec_allowed = true;
1077         ad->tx_simple_allowed = true;
1078         ad->tx_vec_allowed = true;
1079
1080         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1081                 ret = i40e_fdir_setup(pf);
1082                 if (ret != I40E_SUCCESS) {
1083                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1084                         return -ENOTSUP;
1085                 }
1086                 ret = i40e_fdir_configure(dev);
1087                 if (ret < 0) {
1088                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1089                         goto err;
1090                 }
1091         } else
1092                 i40e_fdir_teardown(pf);
1093
1094         ret = i40e_dev_init_vlan(dev);
1095         if (ret < 0)
1096                 goto err;
1097
1098         /* VMDQ setup.
1099          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1100          *  RSS setting have different requirements.
1101          *  General PMD driver call sequence are NIC init, configure,
1102          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1103          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1104          *  applicable. So, VMDQ setting has to be done before
1105          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1106          *  For RSS setting, it will try to calculate actual configured RX queue
1107          *  number, which will be available after rx_queue_setup(). dev_start()
1108          *  function is good to place RSS setup.
1109          */
1110         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1111                 ret = i40e_vmdq_setup(dev);
1112                 if (ret)
1113                         goto err;
1114         }
1115
1116         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1117                 ret = i40e_dcb_setup(dev);
1118                 if (ret) {
1119                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1120                         goto err_dcb;
1121                 }
1122         }
1123
1124         return 0;
1125
1126 err_dcb:
1127         /* need to release vmdq resource if exists */
1128         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1129                 i40e_vsi_release(pf->vmdq[i].vsi);
1130                 pf->vmdq[i].vsi = NULL;
1131         }
1132         rte_free(pf->vmdq);
1133         pf->vmdq = NULL;
1134 err:
1135         /* need to release fdir resource if exists */
1136         i40e_fdir_teardown(pf);
1137         return ret;
1138 }
1139
1140 void
1141 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1142 {
1143         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1144         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1145         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1146         uint16_t msix_vect = vsi->msix_intr;
1147         uint16_t i;
1148
1149         for (i = 0; i < vsi->nb_qps; i++) {
1150                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1151                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1152                 rte_wmb();
1153         }
1154
1155         if (vsi->type != I40E_VSI_SRIOV) {
1156                 if (!rte_intr_allow_others(intr_handle)) {
1157                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1158                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1159                         I40E_WRITE_REG(hw,
1160                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1161                                        0);
1162                 } else {
1163                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1164                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1165                         I40E_WRITE_REG(hw,
1166                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1167                                                        msix_vect - 1), 0);
1168                 }
1169         } else {
1170                 uint32_t reg;
1171                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1172                         vsi->user_param + (msix_vect - 1);
1173
1174                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1175                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1176         }
1177         I40E_WRITE_FLUSH(hw);
1178 }
1179
1180 static void
1181 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1182                        int base_queue, int nb_queue)
1183 {
1184         int i;
1185         uint32_t val;
1186         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1187
1188         /* Bind all RX queues to allocated MSIX interrupt */
1189         for (i = 0; i < nb_queue; i++) {
1190                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1191                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1192                         ((base_queue + i + 1) <<
1193                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1194                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1195                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1196
1197                 if (i == nb_queue - 1)
1198                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1199                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1200         }
1201
1202         /* Write first RX queue to Link list register as the head element */
1203         if (vsi->type != I40E_VSI_SRIOV) {
1204                 uint16_t interval =
1205                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1206
1207                 if (msix_vect == I40E_MISC_VEC_ID) {
1208                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1209                                        (base_queue <<
1210                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1211                                        (0x0 <<
1212                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1213                         I40E_WRITE_REG(hw,
1214                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1215                                        interval);
1216                 } else {
1217                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1218                                        (base_queue <<
1219                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1220                                        (0x0 <<
1221                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1222                         I40E_WRITE_REG(hw,
1223                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1224                                                        msix_vect - 1),
1225                                        interval);
1226                 }
1227         } else {
1228                 uint32_t reg;
1229
1230                 if (msix_vect == I40E_MISC_VEC_ID) {
1231                         I40E_WRITE_REG(hw,
1232                                        I40E_VPINT_LNKLST0(vsi->user_param),
1233                                        (base_queue <<
1234                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1235                                        (0x0 <<
1236                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1237                 } else {
1238                         /* num_msix_vectors_vf needs to minus irq0 */
1239                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1240                                 vsi->user_param + (msix_vect - 1);
1241
1242                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1243                                        (base_queue <<
1244                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1245                                        (0x0 <<
1246                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1247                 }
1248         }
1249
1250         I40E_WRITE_FLUSH(hw);
1251 }
1252
1253 void
1254 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1255 {
1256         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1257         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1258         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1259         uint16_t msix_vect = vsi->msix_intr;
1260         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1261         uint16_t queue_idx = 0;
1262         int record = 0;
1263         uint32_t val;
1264         int i;
1265
1266         for (i = 0; i < vsi->nb_qps; i++) {
1267                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1268                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1269         }
1270
1271         /* INTENA flag is not auto-cleared for interrupt */
1272         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1273         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1274                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1275                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1276         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1277
1278         /* VF bind interrupt */
1279         if (vsi->type == I40E_VSI_SRIOV) {
1280                 __vsi_queues_bind_intr(vsi, msix_vect,
1281                                        vsi->base_queue, vsi->nb_qps);
1282                 return;
1283         }
1284
1285         /* PF & VMDq bind interrupt */
1286         if (rte_intr_dp_is_en(intr_handle)) {
1287                 if (vsi->type == I40E_VSI_MAIN) {
1288                         queue_idx = 0;
1289                         record = 1;
1290                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1291                         struct i40e_vsi *main_vsi =
1292                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1293                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1294                         record = 1;
1295                 }
1296         }
1297
1298         for (i = 0; i < vsi->nb_used_qps; i++) {
1299                 if (nb_msix <= 1) {
1300                         if (!rte_intr_allow_others(intr_handle))
1301                                 /* allow to share MISC_VEC_ID */
1302                                 msix_vect = I40E_MISC_VEC_ID;
1303
1304                         /* no enough msix_vect, map all to one */
1305                         __vsi_queues_bind_intr(vsi, msix_vect,
1306                                                vsi->base_queue + i,
1307                                                vsi->nb_used_qps - i);
1308                         for (; !!record && i < vsi->nb_used_qps; i++)
1309                                 intr_handle->intr_vec[queue_idx + i] =
1310                                         msix_vect;
1311                         break;
1312                 }
1313                 /* 1:1 queue/msix_vect mapping */
1314                 __vsi_queues_bind_intr(vsi, msix_vect,
1315                                        vsi->base_queue + i, 1);
1316                 if (!!record)
1317                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1318
1319                 msix_vect++;
1320                 nb_msix--;
1321         }
1322 }
1323
1324 static void
1325 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1326 {
1327         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1328         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1329         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1330         uint16_t interval = i40e_calc_itr_interval(\
1331                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1332         uint16_t msix_intr, i;
1333
1334         if (rte_intr_allow_others(intr_handle))
1335                 for (i = 0; i < vsi->nb_msix; i++) {
1336                         msix_intr = vsi->msix_intr + i;
1337                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1338                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1339                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1340                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1341                                 (interval <<
1342                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1343                 }
1344         else
1345                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1346                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1347                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1348                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1349                                (interval <<
1350                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1351
1352         I40E_WRITE_FLUSH(hw);
1353 }
1354
1355 static void
1356 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1357 {
1358         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1359         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1360         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1361         uint16_t msix_intr, i;
1362
1363         if (rte_intr_allow_others(intr_handle))
1364                 for (i = 0; i < vsi->nb_msix; i++) {
1365                         msix_intr = vsi->msix_intr + i;
1366                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1367                                        0);
1368                 }
1369         else
1370                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1371
1372         I40E_WRITE_FLUSH(hw);
1373 }
1374
1375 static inline uint8_t
1376 i40e_parse_link_speed(uint16_t eth_link_speed)
1377 {
1378         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1379
1380         switch (eth_link_speed) {
1381         case ETH_LINK_SPEED_40G:
1382                 link_speed = I40E_LINK_SPEED_40GB;
1383                 break;
1384         case ETH_LINK_SPEED_20G:
1385                 link_speed = I40E_LINK_SPEED_20GB;
1386                 break;
1387         case ETH_LINK_SPEED_10G:
1388                 link_speed = I40E_LINK_SPEED_10GB;
1389                 break;
1390         case ETH_LINK_SPEED_1000:
1391                 link_speed = I40E_LINK_SPEED_1GB;
1392                 break;
1393         case ETH_LINK_SPEED_100:
1394                 link_speed = I40E_LINK_SPEED_100MB;
1395                 break;
1396         }
1397
1398         return link_speed;
1399 }
1400
1401 static int
1402 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1403                    __rte_unused uint8_t abilities,
1404                    __rte_unused uint8_t force_speed)
1405 {
1406         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1407          * for the link control limitation of that all link control should be
1408          * handled by firmware. It should follow up if link control will be
1409          * opened to software driver in future firmware versions.
1410          */
1411         return I40E_SUCCESS;
1412 }
1413
1414 static int
1415 i40e_apply_link_speed(struct rte_eth_dev *dev)
1416 {
1417         uint8_t speed;
1418         uint8_t abilities = 0;
1419         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1420         struct rte_eth_conf *conf = &dev->data->dev_conf;
1421
1422         speed = i40e_parse_link_speed(conf->link_speed);
1423         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1424         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1425                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1426         else
1427                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1428
1429         return i40e_phy_conf_link(hw, abilities, speed);
1430 }
1431
1432 static int
1433 i40e_dev_start(struct rte_eth_dev *dev)
1434 {
1435         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1436         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437         struct i40e_vsi *main_vsi = pf->main_vsi;
1438         int ret, i;
1439         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1440         uint32_t intr_vector = 0;
1441
1442         hw->adapter_stopped = 0;
1443
1444         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1445                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1446                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1447                              dev->data->dev_conf.link_duplex,
1448                              dev->data->port_id);
1449                 return -EINVAL;
1450         }
1451
1452         rte_intr_disable(intr_handle);
1453
1454         if ((rte_intr_cap_multiple(intr_handle) ||
1455              !RTE_ETH_DEV_SRIOV(dev).active) &&
1456             dev->data->dev_conf.intr_conf.rxq != 0) {
1457                 intr_vector = dev->data->nb_rx_queues;
1458                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1459                         return -1;
1460         }
1461
1462         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1463                 intr_handle->intr_vec =
1464                         rte_zmalloc("intr_vec",
1465                                     dev->data->nb_rx_queues * sizeof(int),
1466                                     0);
1467                 if (!intr_handle->intr_vec) {
1468                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1469                                      " intr_vec\n", dev->data->nb_rx_queues);
1470                         return -ENOMEM;
1471                 }
1472         }
1473
1474         /* Initialize VSI */
1475         ret = i40e_dev_rxtx_init(pf);
1476         if (ret != I40E_SUCCESS) {
1477                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1478                 goto err_up;
1479         }
1480
1481         /* Map queues with MSIX interrupt */
1482         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1483                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1484         i40e_vsi_queues_bind_intr(main_vsi);
1485         i40e_vsi_enable_queues_intr(main_vsi);
1486
1487         /* Map VMDQ VSI queues with MSIX interrupt */
1488         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1489                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1490                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1491                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1492         }
1493
1494         /* enable FDIR MSIX interrupt */
1495         if (pf->fdir.fdir_vsi) {
1496                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1497                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1498         }
1499
1500         /* Enable all queues which have been configured */
1501         ret = i40e_dev_switch_queues(pf, TRUE);
1502         if (ret != I40E_SUCCESS) {
1503                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1504                 goto err_up;
1505         }
1506
1507         /* Enable receiving broadcast packets */
1508         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1509         if (ret != I40E_SUCCESS)
1510                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1511
1512         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1513                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1514                                                 true, NULL);
1515                 if (ret != I40E_SUCCESS)
1516                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1517         }
1518
1519         /* Apply link configure */
1520         ret = i40e_apply_link_speed(dev);
1521         if (I40E_SUCCESS != ret) {
1522                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1523                 goto err_up;
1524         }
1525
1526         if (!rte_intr_allow_others(intr_handle)) {
1527                 rte_intr_callback_unregister(intr_handle,
1528                                              i40e_dev_interrupt_handler,
1529                                              (void *)dev);
1530                 /* configure and enable device interrupt */
1531                 i40e_pf_config_irq0(hw, FALSE);
1532                 i40e_pf_enable_irq0(hw);
1533
1534                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1535                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1536                                      " no intr multiplex\n");
1537         }
1538
1539         /* enable uio intr after callback register */
1540         rte_intr_enable(intr_handle);
1541
1542         return I40E_SUCCESS;
1543
1544 err_up:
1545         i40e_dev_switch_queues(pf, FALSE);
1546         i40e_dev_clear_queues(dev);
1547
1548         return ret;
1549 }
1550
1551 static void
1552 i40e_dev_stop(struct rte_eth_dev *dev)
1553 {
1554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1555         struct i40e_vsi *main_vsi = pf->main_vsi;
1556         struct i40e_mirror_rule *p_mirror;
1557         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1558         int i;
1559
1560         /* Disable all queues */
1561         i40e_dev_switch_queues(pf, FALSE);
1562
1563         /* un-map queues with interrupt registers */
1564         i40e_vsi_disable_queues_intr(main_vsi);
1565         i40e_vsi_queues_unbind_intr(main_vsi);
1566
1567         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1568                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1569                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1570         }
1571
1572         if (pf->fdir.fdir_vsi) {
1573                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1574                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1575         }
1576         /* Clear all queues and release memory */
1577         i40e_dev_clear_queues(dev);
1578
1579         /* Set link down */
1580         i40e_dev_set_link_down(dev);
1581
1582         /* Remove all mirror rules */
1583         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1584                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1585                 rte_free(p_mirror);
1586         }
1587         pf->nb_mirror_rule = 0;
1588
1589         if (!rte_intr_allow_others(intr_handle))
1590                 /* resume to the default handler */
1591                 rte_intr_callback_register(intr_handle,
1592                                            i40e_dev_interrupt_handler,
1593                                            (void *)dev);
1594
1595         /* Clean datapath event and queue/vec mapping */
1596         rte_intr_efd_disable(intr_handle);
1597         if (intr_handle->intr_vec) {
1598                 rte_free(intr_handle->intr_vec);
1599                 intr_handle->intr_vec = NULL;
1600         }
1601 }
1602
1603 static void
1604 i40e_dev_close(struct rte_eth_dev *dev)
1605 {
1606         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608         uint32_t reg;
1609         int i;
1610
1611         PMD_INIT_FUNC_TRACE();
1612
1613         i40e_dev_stop(dev);
1614         hw->adapter_stopped = 1;
1615         i40e_dev_free_queues(dev);
1616
1617         /* Disable interrupt */
1618         i40e_pf_disable_irq0(hw);
1619         rte_intr_disable(&(dev->pci_dev->intr_handle));
1620
1621         /* shutdown and destroy the HMC */
1622         i40e_shutdown_lan_hmc(hw);
1623
1624         /* release all the existing VSIs and VEBs */
1625         i40e_fdir_teardown(pf);
1626         i40e_vsi_release(pf->main_vsi);
1627
1628         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1629                 i40e_vsi_release(pf->vmdq[i].vsi);
1630                 pf->vmdq[i].vsi = NULL;
1631         }
1632
1633         rte_free(pf->vmdq);
1634         pf->vmdq = NULL;
1635
1636         /* shutdown the adminq */
1637         i40e_aq_queue_shutdown(hw, true);
1638         i40e_shutdown_adminq(hw);
1639
1640         i40e_res_pool_destroy(&pf->qp_pool);
1641         i40e_res_pool_destroy(&pf->msix_pool);
1642
1643         /* force a PF reset to clean anything leftover */
1644         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1645         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1646                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1647         I40E_WRITE_FLUSH(hw);
1648 }
1649
1650 static void
1651 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1652 {
1653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         struct i40e_vsi *vsi = pf->main_vsi;
1656         int status;
1657
1658         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1659                                                         true, NULL);
1660         if (status != I40E_SUCCESS)
1661                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1662
1663         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1664                                                         TRUE, NULL);
1665         if (status != I40E_SUCCESS)
1666                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1667
1668 }
1669
1670 static void
1671 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1672 {
1673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675         struct i40e_vsi *vsi = pf->main_vsi;
1676         int status;
1677
1678         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1679                                                         false, NULL);
1680         if (status != I40E_SUCCESS)
1681                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1682
1683         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1684                                                         false, NULL);
1685         if (status != I40E_SUCCESS)
1686                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1687 }
1688
1689 static void
1690 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1691 {
1692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1693         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1694         struct i40e_vsi *vsi = pf->main_vsi;
1695         int ret;
1696
1697         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1698         if (ret != I40E_SUCCESS)
1699                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1700 }
1701
1702 static void
1703 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1704 {
1705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707         struct i40e_vsi *vsi = pf->main_vsi;
1708         int ret;
1709
1710         if (dev->data->promiscuous == 1)
1711                 return; /* must remain in all_multicast mode */
1712
1713         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1714                                 vsi->seid, FALSE, NULL);
1715         if (ret != I40E_SUCCESS)
1716                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1717 }
1718
1719 /*
1720  * Set device link up.
1721  */
1722 static int
1723 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1724 {
1725         /* re-apply link speed setting */
1726         return i40e_apply_link_speed(dev);
1727 }
1728
1729 /*
1730  * Set device link down.
1731  */
1732 static int
1733 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1734 {
1735         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1736         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1738
1739         return i40e_phy_conf_link(hw, abilities, speed);
1740 }
1741
1742 int
1743 i40e_dev_link_update(struct rte_eth_dev *dev,
1744                      int wait_to_complete)
1745 {
1746 #define CHECK_INTERVAL 100  /* 100ms */
1747 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749         struct i40e_link_status link_status;
1750         struct rte_eth_link link, old;
1751         int status;
1752         unsigned rep_cnt = MAX_REPEAT_TIME;
1753
1754         memset(&link, 0, sizeof(link));
1755         memset(&old, 0, sizeof(old));
1756         memset(&link_status, 0, sizeof(link_status));
1757         rte_i40e_dev_atomic_read_link_status(dev, &old);
1758
1759         do {
1760                 /* Get link status information from hardware */
1761                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1762                 if (status != I40E_SUCCESS) {
1763                         link.link_speed = ETH_LINK_SPEED_100;
1764                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1765                         PMD_DRV_LOG(ERR, "Failed to get link info");
1766                         goto out;
1767                 }
1768
1769                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1770                 if (!wait_to_complete)
1771                         break;
1772
1773                 rte_delay_ms(CHECK_INTERVAL);
1774         } while (!link.link_status && rep_cnt--);
1775
1776         if (!link.link_status)
1777                 goto out;
1778
1779         /* i40e uses full duplex only */
1780         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1781
1782         /* Parse the link status */
1783         switch (link_status.link_speed) {
1784         case I40E_LINK_SPEED_100MB:
1785                 link.link_speed = ETH_LINK_SPEED_100;
1786                 break;
1787         case I40E_LINK_SPEED_1GB:
1788                 link.link_speed = ETH_LINK_SPEED_1000;
1789                 break;
1790         case I40E_LINK_SPEED_10GB:
1791                 link.link_speed = ETH_LINK_SPEED_10G;
1792                 break;
1793         case I40E_LINK_SPEED_20GB:
1794                 link.link_speed = ETH_LINK_SPEED_20G;
1795                 break;
1796         case I40E_LINK_SPEED_40GB:
1797                 link.link_speed = ETH_LINK_SPEED_40G;
1798                 break;
1799         default:
1800                 link.link_speed = ETH_LINK_SPEED_100;
1801                 break;
1802         }
1803
1804 out:
1805         rte_i40e_dev_atomic_write_link_status(dev, &link);
1806         if (link.link_status == old.link_status)
1807                 return -1;
1808
1809         return 0;
1810 }
1811
1812 /* Get all the statistics of a VSI */
1813 void
1814 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1815 {
1816         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1817         struct i40e_eth_stats *nes = &vsi->eth_stats;
1818         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1819         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1820
1821         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1822                             vsi->offset_loaded, &oes->rx_bytes,
1823                             &nes->rx_bytes);
1824         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1825                             vsi->offset_loaded, &oes->rx_unicast,
1826                             &nes->rx_unicast);
1827         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1828                             vsi->offset_loaded, &oes->rx_multicast,
1829                             &nes->rx_multicast);
1830         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1831                             vsi->offset_loaded, &oes->rx_broadcast,
1832                             &nes->rx_broadcast);
1833         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1834                             &oes->rx_discards, &nes->rx_discards);
1835         /* GLV_REPC not supported */
1836         /* GLV_RMPC not supported */
1837         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1838                             &oes->rx_unknown_protocol,
1839                             &nes->rx_unknown_protocol);
1840         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1841                             vsi->offset_loaded, &oes->tx_bytes,
1842                             &nes->tx_bytes);
1843         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1844                             vsi->offset_loaded, &oes->tx_unicast,
1845                             &nes->tx_unicast);
1846         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1847                             vsi->offset_loaded, &oes->tx_multicast,
1848                             &nes->tx_multicast);
1849         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1850                             vsi->offset_loaded,  &oes->tx_broadcast,
1851                             &nes->tx_broadcast);
1852         /* GLV_TDPC not supported */
1853         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1854                             &oes->tx_errors, &nes->tx_errors);
1855         vsi->offset_loaded = true;
1856
1857         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1858                     vsi->vsi_id);
1859         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1860         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1861         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1862         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1863         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1864         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1865                     nes->rx_unknown_protocol);
1866         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1867         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1868         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1869         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1870         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1871         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1872         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1873                     vsi->vsi_id);
1874 }
1875
1876 static void
1877 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1878 {
1879         unsigned int i;
1880         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1881         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1882
1883         /* Get statistics of struct i40e_eth_stats */
1884         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1885                             I40E_GLPRT_GORCL(hw->port),
1886                             pf->offset_loaded, &os->eth.rx_bytes,
1887                             &ns->eth.rx_bytes);
1888         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1889                             I40E_GLPRT_UPRCL(hw->port),
1890                             pf->offset_loaded, &os->eth.rx_unicast,
1891                             &ns->eth.rx_unicast);
1892         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1893                             I40E_GLPRT_MPRCL(hw->port),
1894                             pf->offset_loaded, &os->eth.rx_multicast,
1895                             &ns->eth.rx_multicast);
1896         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1897                             I40E_GLPRT_BPRCL(hw->port),
1898                             pf->offset_loaded, &os->eth.rx_broadcast,
1899                             &ns->eth.rx_broadcast);
1900         /* Workaround: CRC size should not be included in byte statistics,
1901          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1902          */
1903         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1904                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1905
1906         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1907                             pf->offset_loaded, &os->eth.rx_discards,
1908                             &ns->eth.rx_discards);
1909         /* GLPRT_REPC not supported */
1910         /* GLPRT_RMPC not supported */
1911         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1912                             pf->offset_loaded,
1913                             &os->eth.rx_unknown_protocol,
1914                             &ns->eth.rx_unknown_protocol);
1915         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1916                             I40E_GLPRT_GOTCL(hw->port),
1917                             pf->offset_loaded, &os->eth.tx_bytes,
1918                             &ns->eth.tx_bytes);
1919         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1920                             I40E_GLPRT_UPTCL(hw->port),
1921                             pf->offset_loaded, &os->eth.tx_unicast,
1922                             &ns->eth.tx_unicast);
1923         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1924                             I40E_GLPRT_MPTCL(hw->port),
1925                             pf->offset_loaded, &os->eth.tx_multicast,
1926                             &ns->eth.tx_multicast);
1927         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1928                             I40E_GLPRT_BPTCL(hw->port),
1929                             pf->offset_loaded, &os->eth.tx_broadcast,
1930                             &ns->eth.tx_broadcast);
1931         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1932                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1933         /* GLPRT_TEPC not supported */
1934
1935         /* additional port specific stats */
1936         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1937                             pf->offset_loaded, &os->tx_dropped_link_down,
1938                             &ns->tx_dropped_link_down);
1939         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1940                             pf->offset_loaded, &os->crc_errors,
1941                             &ns->crc_errors);
1942         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1943                             pf->offset_loaded, &os->illegal_bytes,
1944                             &ns->illegal_bytes);
1945         /* GLPRT_ERRBC not supported */
1946         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1947                             pf->offset_loaded, &os->mac_local_faults,
1948                             &ns->mac_local_faults);
1949         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1950                             pf->offset_loaded, &os->mac_remote_faults,
1951                             &ns->mac_remote_faults);
1952         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1953                             pf->offset_loaded, &os->rx_length_errors,
1954                             &ns->rx_length_errors);
1955         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1956                             pf->offset_loaded, &os->link_xon_rx,
1957                             &ns->link_xon_rx);
1958         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1959                             pf->offset_loaded, &os->link_xoff_rx,
1960                             &ns->link_xoff_rx);
1961         for (i = 0; i < 8; i++) {
1962                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1963                                     pf->offset_loaded,
1964                                     &os->priority_xon_rx[i],
1965                                     &ns->priority_xon_rx[i]);
1966                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1967                                     pf->offset_loaded,
1968                                     &os->priority_xoff_rx[i],
1969                                     &ns->priority_xoff_rx[i]);
1970         }
1971         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1972                             pf->offset_loaded, &os->link_xon_tx,
1973                             &ns->link_xon_tx);
1974         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1975                             pf->offset_loaded, &os->link_xoff_tx,
1976                             &ns->link_xoff_tx);
1977         for (i = 0; i < 8; i++) {
1978                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1979                                     pf->offset_loaded,
1980                                     &os->priority_xon_tx[i],
1981                                     &ns->priority_xon_tx[i]);
1982                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1983                                     pf->offset_loaded,
1984                                     &os->priority_xoff_tx[i],
1985                                     &ns->priority_xoff_tx[i]);
1986                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1987                                     pf->offset_loaded,
1988                                     &os->priority_xon_2_xoff[i],
1989                                     &ns->priority_xon_2_xoff[i]);
1990         }
1991         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1992                             I40E_GLPRT_PRC64L(hw->port),
1993                             pf->offset_loaded, &os->rx_size_64,
1994                             &ns->rx_size_64);
1995         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1996                             I40E_GLPRT_PRC127L(hw->port),
1997                             pf->offset_loaded, &os->rx_size_127,
1998                             &ns->rx_size_127);
1999         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2000                             I40E_GLPRT_PRC255L(hw->port),
2001                             pf->offset_loaded, &os->rx_size_255,
2002                             &ns->rx_size_255);
2003         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2004                             I40E_GLPRT_PRC511L(hw->port),
2005                             pf->offset_loaded, &os->rx_size_511,
2006                             &ns->rx_size_511);
2007         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2008                             I40E_GLPRT_PRC1023L(hw->port),
2009                             pf->offset_loaded, &os->rx_size_1023,
2010                             &ns->rx_size_1023);
2011         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2012                             I40E_GLPRT_PRC1522L(hw->port),
2013                             pf->offset_loaded, &os->rx_size_1522,
2014                             &ns->rx_size_1522);
2015         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2016                             I40E_GLPRT_PRC9522L(hw->port),
2017                             pf->offset_loaded, &os->rx_size_big,
2018                             &ns->rx_size_big);
2019         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2020                             pf->offset_loaded, &os->rx_undersize,
2021                             &ns->rx_undersize);
2022         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2023                             pf->offset_loaded, &os->rx_fragments,
2024                             &ns->rx_fragments);
2025         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2026                             pf->offset_loaded, &os->rx_oversize,
2027                             &ns->rx_oversize);
2028         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2029                             pf->offset_loaded, &os->rx_jabber,
2030                             &ns->rx_jabber);
2031         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2032                             I40E_GLPRT_PTC64L(hw->port),
2033                             pf->offset_loaded, &os->tx_size_64,
2034                             &ns->tx_size_64);
2035         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2036                             I40E_GLPRT_PTC127L(hw->port),
2037                             pf->offset_loaded, &os->tx_size_127,
2038                             &ns->tx_size_127);
2039         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2040                             I40E_GLPRT_PTC255L(hw->port),
2041                             pf->offset_loaded, &os->tx_size_255,
2042                             &ns->tx_size_255);
2043         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2044                             I40E_GLPRT_PTC511L(hw->port),
2045                             pf->offset_loaded, &os->tx_size_511,
2046                             &ns->tx_size_511);
2047         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2048                             I40E_GLPRT_PTC1023L(hw->port),
2049                             pf->offset_loaded, &os->tx_size_1023,
2050                             &ns->tx_size_1023);
2051         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2052                             I40E_GLPRT_PTC1522L(hw->port),
2053                             pf->offset_loaded, &os->tx_size_1522,
2054                             &ns->tx_size_1522);
2055         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2056                             I40E_GLPRT_PTC9522L(hw->port),
2057                             pf->offset_loaded, &os->tx_size_big,
2058                             &ns->tx_size_big);
2059         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2060                            pf->offset_loaded,
2061                            &os->fd_sb_match, &ns->fd_sb_match);
2062         /* GLPRT_MSPDC not supported */
2063         /* GLPRT_XEC not supported */
2064
2065         pf->offset_loaded = true;
2066
2067         if (pf->main_vsi)
2068                 i40e_update_vsi_stats(pf->main_vsi);
2069 }
2070
2071 /* Get all statistics of a port */
2072 static void
2073 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2074 {
2075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2078         unsigned i;
2079
2080         /* call read registers - updates values, now write them to struct */
2081         i40e_read_stats_registers(pf, hw);
2082
2083         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2084                         pf->main_vsi->eth_stats.rx_multicast +
2085                         pf->main_vsi->eth_stats.rx_broadcast -
2086                         pf->main_vsi->eth_stats.rx_discards;
2087         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2088                         pf->main_vsi->eth_stats.tx_multicast +
2089                         pf->main_vsi->eth_stats.tx_broadcast;
2090         stats->ibytes   = ns->eth.rx_bytes;
2091         stats->obytes   = ns->eth.tx_bytes;
2092         stats->oerrors  = ns->eth.tx_errors +
2093                         pf->main_vsi->eth_stats.tx_errors;
2094         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2095
2096         /* Rx Errors */
2097         stats->imissed  = ns->eth.rx_discards +
2098                         pf->main_vsi->eth_stats.rx_discards;
2099         stats->ierrors  = ns->crc_errors +
2100                         ns->rx_length_errors + ns->rx_undersize +
2101                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2102
2103         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2104         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2105         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2106         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2107         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2108         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2109         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2110                     ns->eth.rx_unknown_protocol);
2111         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2112         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2113         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2114         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2115         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2116         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2117
2118         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2119                     ns->tx_dropped_link_down);
2120         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2121         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2122                     ns->illegal_bytes);
2123         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2124         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2125                     ns->mac_local_faults);
2126         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2127                     ns->mac_remote_faults);
2128         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2129                     ns->rx_length_errors);
2130         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2131         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2132         for (i = 0; i < 8; i++) {
2133                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2134                                 i, ns->priority_xon_rx[i]);
2135                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2136                                 i, ns->priority_xoff_rx[i]);
2137         }
2138         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2139         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2140         for (i = 0; i < 8; i++) {
2141                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2142                                 i, ns->priority_xon_tx[i]);
2143                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2144                                 i, ns->priority_xoff_tx[i]);
2145                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2146                                 i, ns->priority_xon_2_xoff[i]);
2147         }
2148         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2149         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2150         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2151         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2152         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2153         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2154         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2155         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2156         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2157         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2158         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2159         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2160         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2161         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2162         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2163         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2164         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2165         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2166         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2167                         ns->mac_short_packet_dropped);
2168         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2169                     ns->checksum_error);
2170         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2171         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2172 }
2173
2174 /* Reset the statistics */
2175 static void
2176 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2177 {
2178         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2179         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2180
2181         /* Mark PF and VSI stats to update the offset, aka "reset" */
2182         pf->offset_loaded = false;
2183         if (pf->main_vsi)
2184                 pf->main_vsi->offset_loaded = false;
2185
2186         /* read the stats, reading current register values into offset */
2187         i40e_read_stats_registers(pf, hw);
2188 }
2189
2190 static uint32_t
2191 i40e_xstats_calc_num(void)
2192 {
2193         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2194                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2195                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2196 }
2197
2198 static int
2199 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2200                     unsigned n)
2201 {
2202         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2203         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         unsigned i, count, prio;
2205         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2206
2207         count = i40e_xstats_calc_num();
2208         if (n < count)
2209                 return count;
2210
2211         i40e_read_stats_registers(pf, hw);
2212
2213         if (xstats == NULL)
2214                 return 0;
2215
2216         count = 0;
2217
2218         /* Get stats from i40e_eth_stats struct */
2219         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2220                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2221                          "%s", rte_i40e_stats_strings[i].name);
2222                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2223                         rte_i40e_stats_strings[i].offset);
2224                 count++;
2225         }
2226
2227         /* Get individiual stats from i40e_hw_port struct */
2228         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2229                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2230                          "%s", rte_i40e_hw_port_strings[i].name);
2231                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2232                                 rte_i40e_hw_port_strings[i].offset);
2233                 count++;
2234         }
2235
2236         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2237                 for (prio = 0; prio < 8; prio++) {
2238                         snprintf(xstats[count].name,
2239                                  sizeof(xstats[count].name),
2240                                  "rx_priority%u_%s", prio,
2241                                  rte_i40e_rxq_prio_strings[i].name);
2242                         xstats[count].value =
2243                                 *(uint64_t *)(((char *)hw_stats) +
2244                                 rte_i40e_rxq_prio_strings[i].offset +
2245                                 (sizeof(uint64_t) * prio));
2246                         count++;
2247                 }
2248         }
2249
2250         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2251                 for (prio = 0; prio < 8; prio++) {
2252                         snprintf(xstats[count].name,
2253                                  sizeof(xstats[count].name),
2254                                  "tx_priority%u_%s", prio,
2255                                  rte_i40e_txq_prio_strings[i].name);
2256                         xstats[count].value =
2257                                 *(uint64_t *)(((char *)hw_stats) +
2258                                 rte_i40e_txq_prio_strings[i].offset +
2259                                 (sizeof(uint64_t) * prio));
2260                         count++;
2261                 }
2262         }
2263
2264         return count;
2265 }
2266
2267 static int
2268 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2269                                  __rte_unused uint16_t queue_id,
2270                                  __rte_unused uint8_t stat_idx,
2271                                  __rte_unused uint8_t is_rx)
2272 {
2273         PMD_INIT_FUNC_TRACE();
2274
2275         return -ENOSYS;
2276 }
2277
2278 static void
2279 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2280 {
2281         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282         struct i40e_vsi *vsi = pf->main_vsi;
2283
2284         dev_info->max_rx_queues = vsi->nb_qps;
2285         dev_info->max_tx_queues = vsi->nb_qps;
2286         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2287         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2288         dev_info->max_mac_addrs = vsi->max_macaddrs;
2289         dev_info->max_vfs = dev->pci_dev->max_vfs;
2290         dev_info->rx_offload_capa =
2291                 DEV_RX_OFFLOAD_VLAN_STRIP |
2292                 DEV_RX_OFFLOAD_QINQ_STRIP |
2293                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2294                 DEV_RX_OFFLOAD_UDP_CKSUM |
2295                 DEV_RX_OFFLOAD_TCP_CKSUM;
2296         dev_info->tx_offload_capa =
2297                 DEV_TX_OFFLOAD_VLAN_INSERT |
2298                 DEV_TX_OFFLOAD_QINQ_INSERT |
2299                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2300                 DEV_TX_OFFLOAD_UDP_CKSUM |
2301                 DEV_TX_OFFLOAD_TCP_CKSUM |
2302                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2303                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2304                 DEV_TX_OFFLOAD_TCP_TSO;
2305         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2306                                                 sizeof(uint32_t);
2307         dev_info->reta_size = pf->hash_lut_size;
2308         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2309
2310         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2311                 .rx_thresh = {
2312                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2313                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2314                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2315                 },
2316                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2317                 .rx_drop_en = 0,
2318         };
2319
2320         dev_info->default_txconf = (struct rte_eth_txconf) {
2321                 .tx_thresh = {
2322                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2323                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2324                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2325                 },
2326                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2327                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2328                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2329                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2330         };
2331
2332         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2333                 .nb_max = I40E_MAX_RING_DESC,
2334                 .nb_min = I40E_MIN_RING_DESC,
2335                 .nb_align = I40E_ALIGN_RING_DESC,
2336         };
2337
2338         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2339                 .nb_max = I40E_MAX_RING_DESC,
2340                 .nb_min = I40E_MIN_RING_DESC,
2341                 .nb_align = I40E_ALIGN_RING_DESC,
2342         };
2343
2344         if (pf->flags & I40E_FLAG_VMDQ) {
2345                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2346                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2347                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2348                                                 pf->max_nb_vmdq_vsi;
2349                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2350                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2351                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2352         }
2353 }
2354
2355 static int
2356 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2357 {
2358         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2359         struct i40e_vsi *vsi = pf->main_vsi;
2360         PMD_INIT_FUNC_TRACE();
2361
2362         if (on)
2363                 return i40e_vsi_add_vlan(vsi, vlan_id);
2364         else
2365                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2366 }
2367
2368 static int
2369 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2370                    enum rte_vlan_type vlan_type,
2371                    uint16_t tpid)
2372 {
2373         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2374         uint64_t reg_r = 0, reg_w = 0;
2375         uint16_t reg_id = 0;
2376         int ret = 0;
2377
2378         switch (vlan_type) {
2379         case ETH_VLAN_TYPE_OUTER:
2380                 reg_id = 2;
2381                 break;
2382         case ETH_VLAN_TYPE_INNER:
2383                 reg_id = 3;
2384                 break;
2385         default:
2386                 ret = -EINVAL;
2387                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2388                 return ret;
2389         }
2390         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2391                                           &reg_r, NULL);
2392         if (ret != I40E_SUCCESS) {
2393                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2394                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2395                 ret = -EIO;
2396                 return ret;
2397         }
2398         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2399                     "0x%08"PRIx64"", reg_id, reg_r);
2400
2401         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2402         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2403         if (reg_r == reg_w) {
2404                 ret = 0;
2405                 PMD_DRV_LOG(DEBUG, "No need to write");
2406                 return ret;
2407         }
2408
2409         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2410                                            reg_w, NULL);
2411         if (ret != I40E_SUCCESS) {
2412                 ret = -EIO;
2413                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2414                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2415                 return ret;
2416         }
2417         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2418                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2419
2420         return ret;
2421 }
2422
2423 static void
2424 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2425 {
2426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2427         struct i40e_vsi *vsi = pf->main_vsi;
2428
2429         if (mask & ETH_VLAN_FILTER_MASK) {
2430                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2431                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2432                 else
2433                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2434         }
2435
2436         if (mask & ETH_VLAN_STRIP_MASK) {
2437                 /* Enable or disable VLAN stripping */
2438                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2439                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2440                 else
2441                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2442         }
2443
2444         if (mask & ETH_VLAN_EXTEND_MASK) {
2445                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2446                         i40e_vsi_config_double_vlan(vsi, TRUE);
2447                 else
2448                         i40e_vsi_config_double_vlan(vsi, FALSE);
2449         }
2450 }
2451
2452 static void
2453 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2454                           __rte_unused uint16_t queue,
2455                           __rte_unused int on)
2456 {
2457         PMD_INIT_FUNC_TRACE();
2458 }
2459
2460 static int
2461 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2462 {
2463         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2464         struct i40e_vsi *vsi = pf->main_vsi;
2465         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2466         struct i40e_vsi_vlan_pvid_info info;
2467
2468         memset(&info, 0, sizeof(info));
2469         info.on = on;
2470         if (info.on)
2471                 info.config.pvid = pvid;
2472         else {
2473                 info.config.reject.tagged =
2474                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2475                 info.config.reject.untagged =
2476                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2477         }
2478
2479         return i40e_vsi_vlan_pvid_set(vsi, &info);
2480 }
2481
2482 static int
2483 i40e_dev_led_on(struct rte_eth_dev *dev)
2484 {
2485         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486         uint32_t mode = i40e_led_get(hw);
2487
2488         if (mode == 0)
2489                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2490
2491         return 0;
2492 }
2493
2494 static int
2495 i40e_dev_led_off(struct rte_eth_dev *dev)
2496 {
2497         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498         uint32_t mode = i40e_led_get(hw);
2499
2500         if (mode != 0)
2501                 i40e_led_set(hw, 0, false);
2502
2503         return 0;
2504 }
2505
2506 static int
2507 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2508 {
2509         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2511
2512         fc_conf->pause_time = pf->fc_conf.pause_time;
2513         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2514         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2515
2516          /* Return current mode according to actual setting*/
2517         switch (hw->fc.current_mode) {
2518         case I40E_FC_FULL:
2519                 fc_conf->mode = RTE_FC_FULL;
2520                 break;
2521         case I40E_FC_TX_PAUSE:
2522                 fc_conf->mode = RTE_FC_TX_PAUSE;
2523                 break;
2524         case I40E_FC_RX_PAUSE:
2525                 fc_conf->mode = RTE_FC_RX_PAUSE;
2526                 break;
2527         case I40E_FC_NONE:
2528         default:
2529                 fc_conf->mode = RTE_FC_NONE;
2530         };
2531
2532         return 0;
2533 }
2534
2535 static int
2536 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2537 {
2538         uint32_t mflcn_reg, fctrl_reg, reg;
2539         uint32_t max_high_water;
2540         uint8_t i, aq_failure;
2541         int err;
2542         struct i40e_hw *hw;
2543         struct i40e_pf *pf;
2544         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2545                 [RTE_FC_NONE] = I40E_FC_NONE,
2546                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2547                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2548                 [RTE_FC_FULL] = I40E_FC_FULL
2549         };
2550
2551         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2552
2553         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2554         if ((fc_conf->high_water > max_high_water) ||
2555                         (fc_conf->high_water < fc_conf->low_water)) {
2556                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2557                         "High_water must <= %d.", max_high_water);
2558                 return -EINVAL;
2559         }
2560
2561         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2562         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2563         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2564
2565         pf->fc_conf.pause_time = fc_conf->pause_time;
2566         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2567         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2568
2569         PMD_INIT_FUNC_TRACE();
2570
2571         /* All the link flow control related enable/disable register
2572          * configuration is handle by the F/W
2573          */
2574         err = i40e_set_fc(hw, &aq_failure, true);
2575         if (err < 0)
2576                 return -ENOSYS;
2577
2578         if (i40e_is_40G_device(hw->device_id)) {
2579                 /* Configure flow control refresh threshold,
2580                  * the value for stat_tx_pause_refresh_timer[8]
2581                  * is used for global pause operation.
2582                  */
2583
2584                 I40E_WRITE_REG(hw,
2585                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2586                                pf->fc_conf.pause_time);
2587
2588                 /* configure the timer value included in transmitted pause
2589                  * frame,
2590                  * the value for stat_tx_pause_quanta[8] is used for global
2591                  * pause operation
2592                  */
2593                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2594                                pf->fc_conf.pause_time);
2595
2596                 fctrl_reg = I40E_READ_REG(hw,
2597                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2598
2599                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2600                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2601                 else
2602                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2603
2604                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2605                                fctrl_reg);
2606         } else {
2607                 /* Configure pause time (2 TCs per register) */
2608                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2609                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2610                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2611
2612                 /* Configure flow control refresh threshold value */
2613                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2614                                pf->fc_conf.pause_time / 2);
2615
2616                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2617
2618                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2619                  *depending on configuration
2620                  */
2621                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2622                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2623                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2624                 } else {
2625                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2626                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2627                 }
2628
2629                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2630         }
2631
2632         /* config the water marker both based on the packets and bytes */
2633         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2634                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2635                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2636         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2637                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2638                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2639         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2640                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2641                        << I40E_KILOSHIFT);
2642         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2643                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2644                        << I40E_KILOSHIFT);
2645
2646         I40E_WRITE_FLUSH(hw);
2647
2648         return 0;
2649 }
2650
2651 static int
2652 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2653                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2654 {
2655         PMD_INIT_FUNC_TRACE();
2656
2657         return -ENOSYS;
2658 }
2659
2660 /* Add a MAC address, and update filters */
2661 static void
2662 i40e_macaddr_add(struct rte_eth_dev *dev,
2663                  struct ether_addr *mac_addr,
2664                  __rte_unused uint32_t index,
2665                  uint32_t pool)
2666 {
2667         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2668         struct i40e_mac_filter_info mac_filter;
2669         struct i40e_vsi *vsi;
2670         int ret;
2671
2672         /* If VMDQ not enabled or configured, return */
2673         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2674                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2675                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2676                         pool);
2677                 return;
2678         }
2679
2680         if (pool > pf->nb_cfg_vmdq_vsi) {
2681                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2682                                 pool, pf->nb_cfg_vmdq_vsi);
2683                 return;
2684         }
2685
2686         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2687         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2688                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2689         else
2690                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2691
2692         if (pool == 0)
2693                 vsi = pf->main_vsi;
2694         else
2695                 vsi = pf->vmdq[pool - 1].vsi;
2696
2697         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2698         if (ret != I40E_SUCCESS) {
2699                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2700                 return;
2701         }
2702 }
2703
2704 /* Remove a MAC address, and update filters */
2705 static void
2706 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2707 {
2708         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2709         struct i40e_vsi *vsi;
2710         struct rte_eth_dev_data *data = dev->data;
2711         struct ether_addr *macaddr;
2712         int ret;
2713         uint32_t i;
2714         uint64_t pool_sel;
2715
2716         macaddr = &(data->mac_addrs[index]);
2717
2718         pool_sel = dev->data->mac_pool_sel[index];
2719
2720         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2721                 if (pool_sel & (1ULL << i)) {
2722                         if (i == 0)
2723                                 vsi = pf->main_vsi;
2724                         else {
2725                                 /* No VMDQ pool enabled or configured */
2726                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2727                                         (i > pf->nb_cfg_vmdq_vsi)) {
2728                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2729                                                         "/configured");
2730                                         return;
2731                                 }
2732                                 vsi = pf->vmdq[i - 1].vsi;
2733                         }
2734                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2735
2736                         if (ret) {
2737                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2738                                 return;
2739                         }
2740                 }
2741         }
2742 }
2743
2744 /* Set perfect match or hash match of MAC and VLAN for a VF */
2745 static int
2746 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2747                  struct rte_eth_mac_filter *filter,
2748                  bool add)
2749 {
2750         struct i40e_hw *hw;
2751         struct i40e_mac_filter_info mac_filter;
2752         struct ether_addr old_mac;
2753         struct ether_addr *new_mac;
2754         struct i40e_pf_vf *vf = NULL;
2755         uint16_t vf_id;
2756         int ret;
2757
2758         if (pf == NULL) {
2759                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2760                 return -EINVAL;
2761         }
2762         hw = I40E_PF_TO_HW(pf);
2763
2764         if (filter == NULL) {
2765                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2766                 return -EINVAL;
2767         }
2768
2769         new_mac = &filter->mac_addr;
2770
2771         if (is_zero_ether_addr(new_mac)) {
2772                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2773                 return -EINVAL;
2774         }
2775
2776         vf_id = filter->dst_id;
2777
2778         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2779                 PMD_DRV_LOG(ERR, "Invalid argument.");
2780                 return -EINVAL;
2781         }
2782         vf = &pf->vfs[vf_id];
2783
2784         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2785                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2786                 return -EINVAL;
2787         }
2788
2789         if (add) {
2790                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2791                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2792                                 ETHER_ADDR_LEN);
2793                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2794                                  ETHER_ADDR_LEN);
2795
2796                 mac_filter.filter_type = filter->filter_type;
2797                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2798                 if (ret != I40E_SUCCESS) {
2799                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2800                         return -1;
2801                 }
2802                 ether_addr_copy(new_mac, &pf->dev_addr);
2803         } else {
2804                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2805                                 ETHER_ADDR_LEN);
2806                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2807                 if (ret != I40E_SUCCESS) {
2808                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2809                         return -1;
2810                 }
2811
2812                 /* Clear device address as it has been removed */
2813                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2814                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2815         }
2816
2817         return 0;
2818 }
2819
2820 /* MAC filter handle */
2821 static int
2822 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2823                 void *arg)
2824 {
2825         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2826         struct rte_eth_mac_filter *filter;
2827         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2828         int ret = I40E_NOT_SUPPORTED;
2829
2830         filter = (struct rte_eth_mac_filter *)(arg);
2831
2832         switch (filter_op) {
2833         case RTE_ETH_FILTER_NOP:
2834                 ret = I40E_SUCCESS;
2835                 break;
2836         case RTE_ETH_FILTER_ADD:
2837                 i40e_pf_disable_irq0(hw);
2838                 if (filter->is_vf)
2839                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2840                 i40e_pf_enable_irq0(hw);
2841                 break;
2842         case RTE_ETH_FILTER_DELETE:
2843                 i40e_pf_disable_irq0(hw);
2844                 if (filter->is_vf)
2845                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2846                 i40e_pf_enable_irq0(hw);
2847                 break;
2848         default:
2849                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2850                 ret = I40E_ERR_PARAM;
2851                 break;
2852         }
2853
2854         return ret;
2855 }
2856
2857 static int
2858 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2859 {
2860         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2861         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2862         int ret;
2863
2864         if (!lut)
2865                 return -EINVAL;
2866
2867         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2868                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2869                                           lut, lut_size);
2870                 if (ret) {
2871                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2872                         return ret;
2873                 }
2874         } else {
2875                 uint32_t *lut_dw = (uint32_t *)lut;
2876                 uint16_t i, lut_size_dw = lut_size / 4;
2877
2878                 for (i = 0; i < lut_size_dw; i++)
2879                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2880         }
2881
2882         return 0;
2883 }
2884
2885 static int
2886 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2887 {
2888         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2889         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2890         int ret;
2891
2892         if (!vsi || !lut)
2893                 return -EINVAL;
2894
2895         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2896                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2897                                           lut, lut_size);
2898                 if (ret) {
2899                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2900                         return ret;
2901                 }
2902         } else {
2903                 uint32_t *lut_dw = (uint32_t *)lut;
2904                 uint16_t i, lut_size_dw = lut_size / 4;
2905
2906                 for (i = 0; i < lut_size_dw; i++)
2907                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2908                 I40E_WRITE_FLUSH(hw);
2909         }
2910
2911         return 0;
2912 }
2913
2914 static int
2915 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2916                          struct rte_eth_rss_reta_entry64 *reta_conf,
2917                          uint16_t reta_size)
2918 {
2919         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2920         uint16_t i, lut_size = pf->hash_lut_size;
2921         uint16_t idx, shift;
2922         uint8_t *lut;
2923         int ret;
2924
2925         if (reta_size != lut_size ||
2926                 reta_size > ETH_RSS_RETA_SIZE_512) {
2927                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2928                         "(%d) doesn't match the number hardware can supported "
2929                                         "(%d)\n", reta_size, lut_size);
2930                 return -EINVAL;
2931         }
2932
2933         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2934         if (!lut) {
2935                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2936                 return -ENOMEM;
2937         }
2938         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2939         if (ret)
2940                 goto out;
2941         for (i = 0; i < reta_size; i++) {
2942                 idx = i / RTE_RETA_GROUP_SIZE;
2943                 shift = i % RTE_RETA_GROUP_SIZE;
2944                 if (reta_conf[idx].mask & (1ULL << shift))
2945                         lut[i] = reta_conf[idx].reta[shift];
2946         }
2947         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2948
2949 out:
2950         rte_free(lut);
2951
2952         return ret;
2953 }
2954
2955 static int
2956 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2957                         struct rte_eth_rss_reta_entry64 *reta_conf,
2958                         uint16_t reta_size)
2959 {
2960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2961         uint16_t i, lut_size = pf->hash_lut_size;
2962         uint16_t idx, shift;
2963         uint8_t *lut;
2964         int ret;
2965
2966         if (reta_size != lut_size ||
2967                 reta_size > ETH_RSS_RETA_SIZE_512) {
2968                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2969                         "(%d) doesn't match the number hardware can supported "
2970                                         "(%d)\n", reta_size, lut_size);
2971                 return -EINVAL;
2972         }
2973
2974         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2975         if (!lut) {
2976                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2977                 return -ENOMEM;
2978         }
2979
2980         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2981         if (ret)
2982                 goto out;
2983         for (i = 0; i < reta_size; i++) {
2984                 idx = i / RTE_RETA_GROUP_SIZE;
2985                 shift = i % RTE_RETA_GROUP_SIZE;
2986                 if (reta_conf[idx].mask & (1ULL << shift))
2987                         reta_conf[idx].reta[shift] = lut[i];
2988         }
2989
2990 out:
2991         rte_free(lut);
2992
2993         return ret;
2994 }
2995
2996 /**
2997  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2998  * @hw:   pointer to the HW structure
2999  * @mem:  pointer to mem struct to fill out
3000  * @size: size of memory requested
3001  * @alignment: what to align the allocation to
3002  **/
3003 enum i40e_status_code
3004 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3005                         struct i40e_dma_mem *mem,
3006                         u64 size,
3007                         u32 alignment)
3008 {
3009         const struct rte_memzone *mz = NULL;
3010         char z_name[RTE_MEMZONE_NAMESIZE];
3011
3012         if (!mem)
3013                 return I40E_ERR_PARAM;
3014
3015         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3016         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3017                                          alignment, RTE_PGSIZE_2M);
3018         if (!mz)
3019                 return I40E_ERR_NO_MEMORY;
3020
3021         mem->size = size;
3022         mem->va = mz->addr;
3023         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3024         mem->zone = (const void *)mz;
3025         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3026                     "%"PRIu64, mz->name, mem->pa);
3027
3028         return I40E_SUCCESS;
3029 }
3030
3031 /**
3032  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3033  * @hw:   pointer to the HW structure
3034  * @mem:  ptr to mem struct to free
3035  **/
3036 enum i40e_status_code
3037 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3038                     struct i40e_dma_mem *mem)
3039 {
3040         if (!mem)
3041                 return I40E_ERR_PARAM;
3042
3043         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3044                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3045                     mem->pa);
3046         rte_memzone_free((const struct rte_memzone *)mem->zone);
3047         mem->zone = NULL;
3048         mem->va = NULL;
3049         mem->pa = (u64)0;
3050
3051         return I40E_SUCCESS;
3052 }
3053
3054 /**
3055  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3056  * @hw:   pointer to the HW structure
3057  * @mem:  pointer to mem struct to fill out
3058  * @size: size of memory requested
3059  **/
3060 enum i40e_status_code
3061 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3062                          struct i40e_virt_mem *mem,
3063                          u32 size)
3064 {
3065         if (!mem)
3066                 return I40E_ERR_PARAM;
3067
3068         mem->size = size;
3069         mem->va = rte_zmalloc("i40e", size, 0);
3070
3071         if (mem->va)
3072                 return I40E_SUCCESS;
3073         else
3074                 return I40E_ERR_NO_MEMORY;
3075 }
3076
3077 /**
3078  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3079  * @hw:   pointer to the HW structure
3080  * @mem:  pointer to mem struct to free
3081  **/
3082 enum i40e_status_code
3083 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3084                      struct i40e_virt_mem *mem)
3085 {
3086         if (!mem)
3087                 return I40E_ERR_PARAM;
3088
3089         rte_free(mem->va);
3090         mem->va = NULL;
3091
3092         return I40E_SUCCESS;
3093 }
3094
3095 void
3096 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3097 {
3098         rte_spinlock_init(&sp->spinlock);
3099 }
3100
3101 void
3102 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3103 {
3104         rte_spinlock_lock(&sp->spinlock);
3105 }
3106
3107 void
3108 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3109 {
3110         rte_spinlock_unlock(&sp->spinlock);
3111 }
3112
3113 void
3114 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3115 {
3116         return;
3117 }
3118
3119 /**
3120  * Get the hardware capabilities, which will be parsed
3121  * and saved into struct i40e_hw.
3122  */
3123 static int
3124 i40e_get_cap(struct i40e_hw *hw)
3125 {
3126         struct i40e_aqc_list_capabilities_element_resp *buf;
3127         uint16_t len, size = 0;
3128         int ret;
3129
3130         /* Calculate a huge enough buff for saving response data temporarily */
3131         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3132                                                 I40E_MAX_CAP_ELE_NUM;
3133         buf = rte_zmalloc("i40e", len, 0);
3134         if (!buf) {
3135                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3136                 return I40E_ERR_NO_MEMORY;
3137         }
3138
3139         /* Get, parse the capabilities and save it to hw */
3140         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3141                         i40e_aqc_opc_list_func_capabilities, NULL);
3142         if (ret != I40E_SUCCESS)
3143                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3144
3145         /* Free the temporary buffer after being used */
3146         rte_free(buf);
3147
3148         return ret;
3149 }
3150
3151 static int
3152 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3153 {
3154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3155         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3156         uint16_t qp_count = 0, vsi_count = 0;
3157
3158         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3159                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3160                 return -EINVAL;
3161         }
3162         /* Add the parameter init for LFC */
3163         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3164         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3165         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3166
3167         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3168         pf->max_num_vsi = hw->func_caps.num_vsis;
3169         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3170         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3171         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3172
3173         /* FDir queue/VSI allocation */
3174         pf->fdir_qp_offset = 0;
3175         if (hw->func_caps.fd) {
3176                 pf->flags |= I40E_FLAG_FDIR;
3177                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3178         } else {
3179                 pf->fdir_nb_qps = 0;
3180         }
3181         qp_count += pf->fdir_nb_qps;
3182         vsi_count += 1;
3183
3184         /* LAN queue/VSI allocation */
3185         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3186         if (!hw->func_caps.rss) {
3187                 pf->lan_nb_qps = 1;
3188         } else {
3189                 pf->flags |= I40E_FLAG_RSS;
3190                 if (hw->mac.type == I40E_MAC_X722)
3191                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3192                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3193         }
3194         qp_count += pf->lan_nb_qps;
3195         vsi_count += 1;
3196
3197         /* VF queue/VSI allocation */
3198         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3199         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3200                 pf->flags |= I40E_FLAG_SRIOV;
3201                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3202                 pf->vf_num = dev->pci_dev->max_vfs;
3203                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3204                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3205                             pf->vf_nb_qps * pf->vf_num);
3206         } else {
3207                 pf->vf_nb_qps = 0;
3208                 pf->vf_num = 0;
3209         }
3210         qp_count += pf->vf_nb_qps * pf->vf_num;
3211         vsi_count += pf->vf_num;
3212
3213         /* VMDq queue/VSI allocation */
3214         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3215         pf->vmdq_nb_qps = 0;
3216         pf->max_nb_vmdq_vsi = 0;
3217         if (hw->func_caps.vmdq) {
3218                 if (qp_count < hw->func_caps.num_tx_qp &&
3219                         vsi_count < hw->func_caps.num_vsis) {
3220                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3221                                 qp_count) / pf->vmdq_nb_qp_max;
3222
3223                         /* Limit the maximum number of VMDq vsi to the maximum
3224                          * ethdev can support
3225                          */
3226                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3227                                 hw->func_caps.num_vsis - vsi_count);
3228                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3229                                 ETH_64_POOLS);
3230                         if (pf->max_nb_vmdq_vsi) {
3231                                 pf->flags |= I40E_FLAG_VMDQ;
3232                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3233                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3234                                             "per VMDQ VSI, in total %u queues",
3235                                             pf->max_nb_vmdq_vsi,
3236                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3237                                             pf->max_nb_vmdq_vsi);
3238                         } else {
3239                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3240                                             "VMDq");
3241                         }
3242                 } else {
3243                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3244                 }
3245         }
3246         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3247         vsi_count += pf->max_nb_vmdq_vsi;
3248
3249         if (hw->func_caps.dcb)
3250                 pf->flags |= I40E_FLAG_DCB;
3251
3252         if (qp_count > hw->func_caps.num_tx_qp) {
3253                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3254                             "the hardware maximum %u", qp_count,
3255                             hw->func_caps.num_tx_qp);
3256                 return -EINVAL;
3257         }
3258         if (vsi_count > hw->func_caps.num_vsis) {
3259                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3260                             "the hardware maximum %u", vsi_count,
3261                             hw->func_caps.num_vsis);
3262                 return -EINVAL;
3263         }
3264
3265         return 0;
3266 }
3267
3268 static int
3269 i40e_pf_get_switch_config(struct i40e_pf *pf)
3270 {
3271         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3272         struct i40e_aqc_get_switch_config_resp *switch_config;
3273         struct i40e_aqc_switch_config_element_resp *element;
3274         uint16_t start_seid = 0, num_reported;
3275         int ret;
3276
3277         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3278                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3279         if (!switch_config) {
3280                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3281                 return -ENOMEM;
3282         }
3283
3284         /* Get the switch configurations */
3285         ret = i40e_aq_get_switch_config(hw, switch_config,
3286                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3287         if (ret != I40E_SUCCESS) {
3288                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3289                 goto fail;
3290         }
3291         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3292         if (num_reported != 1) { /* The number should be 1 */
3293                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3294                 goto fail;
3295         }
3296
3297         /* Parse the switch configuration elements */
3298         element = &(switch_config->element[0]);
3299         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3300                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3301                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3302         } else
3303                 PMD_DRV_LOG(INFO, "Unknown element type");
3304
3305 fail:
3306         rte_free(switch_config);
3307
3308         return ret;
3309 }
3310
3311 static int
3312 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3313                         uint32_t num)
3314 {
3315         struct pool_entry *entry;
3316
3317         if (pool == NULL || num == 0)
3318                 return -EINVAL;
3319
3320         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3321         if (entry == NULL) {
3322                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3323                 return -ENOMEM;
3324         }
3325
3326         /* queue heap initialize */
3327         pool->num_free = num;
3328         pool->num_alloc = 0;
3329         pool->base = base;
3330         LIST_INIT(&pool->alloc_list);
3331         LIST_INIT(&pool->free_list);
3332
3333         /* Initialize element  */
3334         entry->base = 0;
3335         entry->len = num;
3336
3337         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3338         return 0;
3339 }
3340
3341 static void
3342 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3343 {
3344         struct pool_entry *entry;
3345
3346         if (pool == NULL)
3347                 return;
3348
3349         LIST_FOREACH(entry, &pool->alloc_list, next) {
3350                 LIST_REMOVE(entry, next);
3351                 rte_free(entry);
3352         }
3353
3354         LIST_FOREACH(entry, &pool->free_list, next) {
3355                 LIST_REMOVE(entry, next);
3356                 rte_free(entry);
3357         }
3358
3359         pool->num_free = 0;
3360         pool->num_alloc = 0;
3361         pool->base = 0;
3362         LIST_INIT(&pool->alloc_list);
3363         LIST_INIT(&pool->free_list);
3364 }
3365
3366 static int
3367 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3368                        uint32_t base)
3369 {
3370         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3371         uint32_t pool_offset;
3372         int insert;
3373
3374         if (pool == NULL) {
3375                 PMD_DRV_LOG(ERR, "Invalid parameter");
3376                 return -EINVAL;
3377         }
3378
3379         pool_offset = base - pool->base;
3380         /* Lookup in alloc list */
3381         LIST_FOREACH(entry, &pool->alloc_list, next) {
3382                 if (entry->base == pool_offset) {
3383                         valid_entry = entry;
3384                         LIST_REMOVE(entry, next);
3385                         break;
3386                 }
3387         }
3388
3389         /* Not find, return */
3390         if (valid_entry == NULL) {
3391                 PMD_DRV_LOG(ERR, "Failed to find entry");
3392                 return -EINVAL;
3393         }
3394
3395         /**
3396          * Found it, move it to free list  and try to merge.
3397          * In order to make merge easier, always sort it by qbase.
3398          * Find adjacent prev and last entries.
3399          */
3400         prev = next = NULL;
3401         LIST_FOREACH(entry, &pool->free_list, next) {
3402                 if (entry->base > valid_entry->base) {
3403                         next = entry;
3404                         break;
3405                 }
3406                 prev = entry;
3407         }
3408
3409         insert = 0;
3410         /* Try to merge with next one*/
3411         if (next != NULL) {
3412                 /* Merge with next one */
3413                 if (valid_entry->base + valid_entry->len == next->base) {
3414                         next->base = valid_entry->base;
3415                         next->len += valid_entry->len;
3416                         rte_free(valid_entry);
3417                         valid_entry = next;
3418                         insert = 1;
3419                 }
3420         }
3421
3422         if (prev != NULL) {
3423                 /* Merge with previous one */
3424                 if (prev->base + prev->len == valid_entry->base) {
3425                         prev->len += valid_entry->len;
3426                         /* If it merge with next one, remove next node */
3427                         if (insert == 1) {
3428                                 LIST_REMOVE(valid_entry, next);
3429                                 rte_free(valid_entry);
3430                         } else {
3431                                 rte_free(valid_entry);
3432                                 insert = 1;
3433                         }
3434                 }
3435         }
3436
3437         /* Not find any entry to merge, insert */
3438         if (insert == 0) {
3439                 if (prev != NULL)
3440                         LIST_INSERT_AFTER(prev, valid_entry, next);
3441                 else if (next != NULL)
3442                         LIST_INSERT_BEFORE(next, valid_entry, next);
3443                 else /* It's empty list, insert to head */
3444                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3445         }
3446
3447         pool->num_free += valid_entry->len;
3448         pool->num_alloc -= valid_entry->len;
3449
3450         return 0;
3451 }
3452
3453 static int
3454 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3455                        uint16_t num)
3456 {
3457         struct pool_entry *entry, *valid_entry;
3458
3459         if (pool == NULL || num == 0) {
3460                 PMD_DRV_LOG(ERR, "Invalid parameter");
3461                 return -EINVAL;
3462         }
3463
3464         if (pool->num_free < num) {
3465                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3466                             num, pool->num_free);
3467                 return -ENOMEM;
3468         }
3469
3470         valid_entry = NULL;
3471         /* Lookup  in free list and find most fit one */
3472         LIST_FOREACH(entry, &pool->free_list, next) {
3473                 if (entry->len >= num) {
3474                         /* Find best one */
3475                         if (entry->len == num) {
3476                                 valid_entry = entry;
3477                                 break;
3478                         }
3479                         if (valid_entry == NULL || valid_entry->len > entry->len)
3480                                 valid_entry = entry;
3481                 }
3482         }
3483
3484         /* Not find one to satisfy the request, return */
3485         if (valid_entry == NULL) {
3486                 PMD_DRV_LOG(ERR, "No valid entry found");
3487                 return -ENOMEM;
3488         }
3489         /**
3490          * The entry have equal queue number as requested,
3491          * remove it from alloc_list.
3492          */
3493         if (valid_entry->len == num) {
3494                 LIST_REMOVE(valid_entry, next);
3495         } else {
3496                 /**
3497                  * The entry have more numbers than requested,
3498                  * create a new entry for alloc_list and minus its
3499                  * queue base and number in free_list.
3500                  */
3501                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3502                 if (entry == NULL) {
3503                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3504                                     "resource pool");
3505                         return -ENOMEM;
3506                 }
3507                 entry->base = valid_entry->base;
3508                 entry->len = num;
3509                 valid_entry->base += num;
3510                 valid_entry->len -= num;
3511                 valid_entry = entry;
3512         }
3513
3514         /* Insert it into alloc list, not sorted */
3515         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3516
3517         pool->num_free -= valid_entry->len;
3518         pool->num_alloc += valid_entry->len;
3519
3520         return valid_entry->base + pool->base;
3521 }
3522
3523 /**
3524  * bitmap_is_subset - Check whether src2 is subset of src1
3525  **/
3526 static inline int
3527 bitmap_is_subset(uint8_t src1, uint8_t src2)
3528 {
3529         return !((src1 ^ src2) & src2);
3530 }
3531
3532 static enum i40e_status_code
3533 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3534 {
3535         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3536
3537         /* If DCB is not supported, only default TC is supported */
3538         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3539                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3540                 return I40E_NOT_SUPPORTED;
3541         }
3542
3543         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3544                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3545                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3546                             enabled_tcmap);
3547                 return I40E_NOT_SUPPORTED;
3548         }
3549         return I40E_SUCCESS;
3550 }
3551
3552 int
3553 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3554                                 struct i40e_vsi_vlan_pvid_info *info)
3555 {
3556         struct i40e_hw *hw;
3557         struct i40e_vsi_context ctxt;
3558         uint8_t vlan_flags = 0;
3559         int ret;
3560
3561         if (vsi == NULL || info == NULL) {
3562                 PMD_DRV_LOG(ERR, "invalid parameters");
3563                 return I40E_ERR_PARAM;
3564         }
3565
3566         if (info->on) {
3567                 vsi->info.pvid = info->config.pvid;
3568                 /**
3569                  * If insert pvid is enabled, only tagged pkts are
3570                  * allowed to be sent out.
3571                  */
3572                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3573                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3574         } else {
3575                 vsi->info.pvid = 0;
3576                 if (info->config.reject.tagged == 0)
3577                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3578
3579                 if (info->config.reject.untagged == 0)
3580                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3581         }
3582         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3583                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3584         vsi->info.port_vlan_flags |= vlan_flags;
3585         vsi->info.valid_sections =
3586                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3587         memset(&ctxt, 0, sizeof(ctxt));
3588         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3589         ctxt.seid = vsi->seid;
3590
3591         hw = I40E_VSI_TO_HW(vsi);
3592         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3593         if (ret != I40E_SUCCESS)
3594                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3595
3596         return ret;
3597 }
3598
3599 static int
3600 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3601 {
3602         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3603         int i, ret;
3604         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3605
3606         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3607         if (ret != I40E_SUCCESS)
3608                 return ret;
3609
3610         if (!vsi->seid) {
3611                 PMD_DRV_LOG(ERR, "seid not valid");
3612                 return -EINVAL;
3613         }
3614
3615         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3616         tc_bw_data.tc_valid_bits = enabled_tcmap;
3617         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3618                 tc_bw_data.tc_bw_credits[i] =
3619                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3620
3621         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3622         if (ret != I40E_SUCCESS) {
3623                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3624                 return ret;
3625         }
3626
3627         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3628                                         sizeof(vsi->info.qs_handle));
3629         return I40E_SUCCESS;
3630 }
3631
3632 static enum i40e_status_code
3633 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3634                                  struct i40e_aqc_vsi_properties_data *info,
3635                                  uint8_t enabled_tcmap)
3636 {
3637         enum i40e_status_code ret;
3638         int i, total_tc = 0;
3639         uint16_t qpnum_per_tc, bsf, qp_idx;
3640
3641         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3642         if (ret != I40E_SUCCESS)
3643                 return ret;
3644
3645         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3646                 if (enabled_tcmap & (1 << i))
3647                         total_tc++;
3648         vsi->enabled_tc = enabled_tcmap;
3649
3650         /* Number of queues per enabled TC */
3651         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3652         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3653         bsf = rte_bsf32(qpnum_per_tc);
3654
3655         /* Adjust the queue number to actual queues that can be applied */
3656         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3657                 vsi->nb_qps = qpnum_per_tc * total_tc;
3658
3659         /**
3660          * Configure TC and queue mapping parameters, for enabled TC,
3661          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3662          * default queue will serve it.
3663          */
3664         qp_idx = 0;
3665         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3666                 if (vsi->enabled_tc & (1 << i)) {
3667                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3668                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3669                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3670                         qp_idx += qpnum_per_tc;
3671                 } else
3672                         info->tc_mapping[i] = 0;
3673         }
3674
3675         /* Associate queue number with VSI */
3676         if (vsi->type == I40E_VSI_SRIOV) {
3677                 info->mapping_flags |=
3678                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3679                 for (i = 0; i < vsi->nb_qps; i++)
3680                         info->queue_mapping[i] =
3681                                 rte_cpu_to_le_16(vsi->base_queue + i);
3682         } else {
3683                 info->mapping_flags |=
3684                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3685                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3686         }
3687         info->valid_sections |=
3688                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3689
3690         return I40E_SUCCESS;
3691 }
3692
3693 static int
3694 i40e_veb_release(struct i40e_veb *veb)
3695 {
3696         struct i40e_vsi *vsi;
3697         struct i40e_hw *hw;
3698
3699         if (veb == NULL || veb->associate_vsi == NULL)
3700                 return -EINVAL;
3701
3702         if (!TAILQ_EMPTY(&veb->head)) {
3703                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3704                 return -EACCES;
3705         }
3706
3707         vsi = veb->associate_vsi;
3708         hw = I40E_VSI_TO_HW(vsi);
3709
3710         vsi->uplink_seid = veb->uplink_seid;
3711         i40e_aq_delete_element(hw, veb->seid, NULL);
3712         rte_free(veb);
3713         vsi->veb = NULL;
3714         return I40E_SUCCESS;
3715 }
3716
3717 /* Setup a veb */
3718 static struct i40e_veb *
3719 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3720 {
3721         struct i40e_veb *veb;
3722         int ret;
3723         struct i40e_hw *hw;
3724
3725         if (NULL == pf || vsi == NULL) {
3726                 PMD_DRV_LOG(ERR, "veb setup failed, "
3727                             "associated VSI shouldn't null");
3728                 return NULL;
3729         }
3730         hw = I40E_PF_TO_HW(pf);
3731
3732         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3733         if (!veb) {
3734                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3735                 goto fail;
3736         }
3737
3738         veb->associate_vsi = vsi;
3739         TAILQ_INIT(&veb->head);
3740         veb->uplink_seid = vsi->uplink_seid;
3741
3742         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3743                 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3744
3745         if (ret != I40E_SUCCESS) {
3746                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3747                             hw->aq.asq_last_status);
3748                 goto fail;
3749         }
3750
3751         /* get statistics index */
3752         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3753                                 &veb->stats_idx, NULL, NULL, NULL);
3754         if (ret != I40E_SUCCESS) {
3755                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3756                             hw->aq.asq_last_status);
3757                 goto fail;
3758         }
3759
3760         /* Get VEB bandwidth, to be implemented */
3761         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3762         vsi->uplink_seid = veb->seid;
3763
3764         return veb;
3765 fail:
3766         rte_free(veb);
3767         return NULL;
3768 }
3769
3770 int
3771 i40e_vsi_release(struct i40e_vsi *vsi)
3772 {
3773         struct i40e_pf *pf;
3774         struct i40e_hw *hw;
3775         struct i40e_vsi_list *vsi_list;
3776         int ret;
3777         struct i40e_mac_filter *f;
3778
3779         if (!vsi)
3780                 return I40E_SUCCESS;
3781
3782         pf = I40E_VSI_TO_PF(vsi);
3783         hw = I40E_VSI_TO_HW(vsi);
3784
3785         /* VSI has child to attach, release child first */
3786         if (vsi->veb) {
3787                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3788                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3789                                 return -1;
3790                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3791                 }
3792                 i40e_veb_release(vsi->veb);
3793         }
3794
3795         /* Remove all macvlan filters of the VSI */
3796         i40e_vsi_remove_all_macvlan_filter(vsi);
3797         TAILQ_FOREACH(f, &vsi->mac_list, next)
3798                 rte_free(f);
3799
3800         if (vsi->type != I40E_VSI_MAIN) {
3801                 /* Remove vsi from parent's sibling list */
3802                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3803                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3804                         return I40E_ERR_PARAM;
3805                 }
3806                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3807                                 &vsi->sib_vsi_list, list);
3808
3809                 /* Remove all switch element of the VSI */
3810                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3811                 if (ret != I40E_SUCCESS)
3812                         PMD_DRV_LOG(ERR, "Failed to delete element");
3813         }
3814         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3815
3816         if (vsi->type != I40E_VSI_SRIOV)
3817                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3818         rte_free(vsi);
3819
3820         return I40E_SUCCESS;
3821 }
3822
3823 static int
3824 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3825 {
3826         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3827         struct i40e_aqc_remove_macvlan_element_data def_filter;
3828         struct i40e_mac_filter_info filter;
3829         int ret;
3830
3831         if (vsi->type != I40E_VSI_MAIN)
3832                 return I40E_ERR_CONFIG;
3833         memset(&def_filter, 0, sizeof(def_filter));
3834         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3835                                         ETH_ADDR_LEN);
3836         def_filter.vlan_tag = 0;
3837         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3838                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3839         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3840         if (ret != I40E_SUCCESS) {
3841                 struct i40e_mac_filter *f;
3842                 struct ether_addr *mac;
3843
3844                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3845                             "macvlan filter");
3846                 /* It needs to add the permanent mac into mac list */
3847                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3848                 if (f == NULL) {
3849                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3850                         return I40E_ERR_NO_MEMORY;
3851                 }
3852                 mac = &f->mac_info.mac_addr;
3853                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3854                                 ETH_ADDR_LEN);
3855                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3856                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3857                 vsi->mac_num++;
3858
3859                 return ret;
3860         }
3861         (void)rte_memcpy(&filter.mac_addr,
3862                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3863         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3864         return i40e_vsi_add_mac(vsi, &filter);
3865 }
3866
3867 /*
3868  * i40e_vsi_get_bw_config - Query VSI BW Information
3869  * @vsi: the VSI to be queried
3870  *
3871  * Returns 0 on success, negative value on failure
3872  */
3873 static enum i40e_status_code
3874 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3875 {
3876         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3877         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3878         struct i40e_hw *hw = &vsi->adapter->hw;
3879         i40e_status ret;
3880         int i;
3881         uint32_t bw_max;
3882
3883         memset(&bw_config, 0, sizeof(bw_config));
3884         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3885         if (ret != I40E_SUCCESS) {
3886                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3887                             hw->aq.asq_last_status);
3888                 return ret;
3889         }
3890
3891         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3892         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3893                                         &ets_sla_config, NULL);
3894         if (ret != I40E_SUCCESS) {
3895                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3896                             "configuration %u", hw->aq.asq_last_status);
3897                 return ret;
3898         }
3899
3900         /* store and print out BW info */
3901         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3902         vsi->bw_info.bw_max = bw_config.max_bw;
3903         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3904         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3905         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3906                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3907                      I40E_16_BIT_WIDTH);
3908         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3909                 vsi->bw_info.bw_ets_share_credits[i] =
3910                                 ets_sla_config.share_credits[i];
3911                 vsi->bw_info.bw_ets_credits[i] =
3912                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3913                 /* 4 bits per TC, 4th bit is reserved */
3914                 vsi->bw_info.bw_ets_max[i] =
3915                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3916                                   RTE_LEN2MASK(3, uint8_t));
3917                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3918                             vsi->bw_info.bw_ets_share_credits[i]);
3919                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3920                             vsi->bw_info.bw_ets_credits[i]);
3921                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3922                             vsi->bw_info.bw_ets_max[i]);
3923         }
3924
3925         return I40E_SUCCESS;
3926 }
3927
3928 /* i40e_enable_pf_lb
3929  * @pf: pointer to the pf structure
3930  *
3931  * allow loopback on pf
3932  */
3933 static inline void
3934 i40e_enable_pf_lb(struct i40e_pf *pf)
3935 {
3936         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3937         struct i40e_vsi_context ctxt;
3938         int ret;
3939
3940         /* Use the FW API if FW >= v5.0 */
3941         if (hw->aq.fw_maj_ver < 5) {
3942                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3943                 return;
3944         }
3945
3946         memset(&ctxt, 0, sizeof(ctxt));
3947         ctxt.seid = pf->main_vsi_seid;
3948         ctxt.pf_num = hw->pf_id;
3949         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3950         if (ret) {
3951                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3952                             ret, hw->aq.asq_last_status);
3953                 return;
3954         }
3955         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3956         ctxt.info.valid_sections =
3957                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3958         ctxt.info.switch_id |=
3959                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3960
3961         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3962         if (ret)
3963                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3964                             hw->aq.asq_last_status);
3965 }
3966
3967 /* Setup a VSI */
3968 struct i40e_vsi *
3969 i40e_vsi_setup(struct i40e_pf *pf,
3970                enum i40e_vsi_type type,
3971                struct i40e_vsi *uplink_vsi,
3972                uint16_t user_param)
3973 {
3974         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3975         struct i40e_vsi *vsi;
3976         struct i40e_mac_filter_info filter;
3977         int ret;
3978         struct i40e_vsi_context ctxt;
3979         struct ether_addr broadcast =
3980                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3981
3982         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3983                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3984                             "VSI link shouldn't be NULL");
3985                 return NULL;
3986         }
3987
3988         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3989                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3990                             "uplink VSI should be NULL");
3991                 return NULL;
3992         }
3993
3994         /* If uplink vsi didn't setup VEB, create one first */
3995         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3996                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3997
3998                 if (NULL == uplink_vsi->veb) {
3999                         PMD_DRV_LOG(ERR, "VEB setup failed");
4000                         return NULL;
4001                 }
4002                 /* set ALLOWLOOPBACk on pf, when veb is created */
4003                 i40e_enable_pf_lb(pf);
4004         }
4005
4006         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4007         if (!vsi) {
4008                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4009                 return NULL;
4010         }
4011         TAILQ_INIT(&vsi->mac_list);
4012         vsi->type = type;
4013         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4014         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4015         vsi->parent_vsi = uplink_vsi;
4016         vsi->user_param = user_param;
4017         /* Allocate queues */
4018         switch (vsi->type) {
4019         case I40E_VSI_MAIN  :
4020                 vsi->nb_qps = pf->lan_nb_qps;
4021                 break;
4022         case I40E_VSI_SRIOV :
4023                 vsi->nb_qps = pf->vf_nb_qps;
4024                 break;
4025         case I40E_VSI_VMDQ2:
4026                 vsi->nb_qps = pf->vmdq_nb_qps;
4027                 break;
4028         case I40E_VSI_FDIR:
4029                 vsi->nb_qps = pf->fdir_nb_qps;
4030                 break;
4031         default:
4032                 goto fail_mem;
4033         }
4034         /*
4035          * The filter status descriptor is reported in rx queue 0,
4036          * while the tx queue for fdir filter programming has no
4037          * such constraints, can be non-zero queues.
4038          * To simplify it, choose FDIR vsi use queue 0 pair.
4039          * To make sure it will use queue 0 pair, queue allocation
4040          * need be done before this function is called
4041          */
4042         if (type != I40E_VSI_FDIR) {
4043                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4044                         if (ret < 0) {
4045                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4046                                                 vsi->seid, ret);
4047                                 goto fail_mem;
4048                         }
4049                         vsi->base_queue = ret;
4050         } else
4051                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4052
4053         /* VF has MSIX interrupt in VF range, don't allocate here */
4054         if (type == I40E_VSI_MAIN) {
4055                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4056                                           RTE_MIN(vsi->nb_qps,
4057                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4058                 if (ret < 0) {
4059                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4060                                     vsi->seid, ret);
4061                         goto fail_queue_alloc;
4062                 }
4063                 vsi->msix_intr = ret;
4064                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4065         } else if (type != I40E_VSI_SRIOV) {
4066                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4067                 if (ret < 0) {
4068                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4069                         goto fail_queue_alloc;
4070                 }
4071                 vsi->msix_intr = ret;
4072                 vsi->nb_msix = 1;
4073         } else {
4074                 vsi->msix_intr = 0;
4075                 vsi->nb_msix = 0;
4076         }
4077
4078         /* Add VSI */
4079         if (type == I40E_VSI_MAIN) {
4080                 /* For main VSI, no need to add since it's default one */
4081                 vsi->uplink_seid = pf->mac_seid;
4082                 vsi->seid = pf->main_vsi_seid;
4083                 /* Bind queues with specific MSIX interrupt */
4084                 /**
4085                  * Needs 2 interrupt at least, one for misc cause which will
4086                  * enabled from OS side, Another for queues binding the
4087                  * interrupt from device side only.
4088                  */
4089
4090                 /* Get default VSI parameters from hardware */
4091                 memset(&ctxt, 0, sizeof(ctxt));
4092                 ctxt.seid = vsi->seid;
4093                 ctxt.pf_num = hw->pf_id;
4094                 ctxt.uplink_seid = vsi->uplink_seid;
4095                 ctxt.vf_num = 0;
4096                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4097                 if (ret != I40E_SUCCESS) {
4098                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4099                         goto fail_msix_alloc;
4100                 }
4101                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4102                         sizeof(struct i40e_aqc_vsi_properties_data));
4103                 vsi->vsi_id = ctxt.vsi_number;
4104                 vsi->info.valid_sections = 0;
4105
4106                 /* Configure tc, enabled TC0 only */
4107                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4108                         I40E_SUCCESS) {
4109                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4110                         goto fail_msix_alloc;
4111                 }
4112
4113                 /* TC, queue mapping */
4114                 memset(&ctxt, 0, sizeof(ctxt));
4115                 vsi->info.valid_sections |=
4116                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4117                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4118                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4119                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4120                         sizeof(struct i40e_aqc_vsi_properties_data));
4121                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4122                                                 I40E_DEFAULT_TCMAP);
4123                 if (ret != I40E_SUCCESS) {
4124                         PMD_DRV_LOG(ERR, "Failed to configure "
4125                                     "TC queue mapping");
4126                         goto fail_msix_alloc;
4127                 }
4128                 ctxt.seid = vsi->seid;
4129                 ctxt.pf_num = hw->pf_id;
4130                 ctxt.uplink_seid = vsi->uplink_seid;
4131                 ctxt.vf_num = 0;
4132
4133                 /* Update VSI parameters */
4134                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4135                 if (ret != I40E_SUCCESS) {
4136                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4137                         goto fail_msix_alloc;
4138                 }
4139
4140                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4141                                                 sizeof(vsi->info.tc_mapping));
4142                 (void)rte_memcpy(&vsi->info.queue_mapping,
4143                                 &ctxt.info.queue_mapping,
4144                         sizeof(vsi->info.queue_mapping));
4145                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4146                 vsi->info.valid_sections = 0;
4147
4148                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4149                                 ETH_ADDR_LEN);
4150
4151                 /**
4152                  * Updating default filter settings are necessary to prevent
4153                  * reception of tagged packets.
4154                  * Some old firmware configurations load a default macvlan
4155                  * filter which accepts both tagged and untagged packets.
4156                  * The updating is to use a normal filter instead if needed.
4157                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4158                  * The firmware with correct configurations load the default
4159                  * macvlan filter which is expected and cannot be removed.
4160                  */
4161                 i40e_update_default_filter_setting(vsi);
4162                 i40e_config_qinq(hw, vsi);
4163         } else if (type == I40E_VSI_SRIOV) {
4164                 memset(&ctxt, 0, sizeof(ctxt));
4165                 /**
4166                  * For other VSI, the uplink_seid equals to uplink VSI's
4167                  * uplink_seid since they share same VEB
4168                  */
4169                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4170                 ctxt.pf_num = hw->pf_id;
4171                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4172                 ctxt.uplink_seid = vsi->uplink_seid;
4173                 ctxt.connection_type = 0x1;
4174                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4175
4176                 /* Use the VEB configuration if FW >= v5.0 */
4177                 if (hw->aq.fw_maj_ver >= 5) {
4178                         /* Configure switch ID */
4179                         ctxt.info.valid_sections |=
4180                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4181                         ctxt.info.switch_id =
4182                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4183                 }
4184
4185                 /* Configure port/vlan */
4186                 ctxt.info.valid_sections |=
4187                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4188                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4189                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4190                                                 I40E_DEFAULT_TCMAP);
4191                 if (ret != I40E_SUCCESS) {
4192                         PMD_DRV_LOG(ERR, "Failed to configure "
4193                                     "TC queue mapping");
4194                         goto fail_msix_alloc;
4195                 }
4196                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4197                 ctxt.info.valid_sections |=
4198                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4199                 /**
4200                  * Since VSI is not created yet, only configure parameter,
4201                  * will add vsi below.
4202                  */
4203
4204                 i40e_config_qinq(hw, vsi);
4205         } else if (type == I40E_VSI_VMDQ2) {
4206                 memset(&ctxt, 0, sizeof(ctxt));
4207                 /*
4208                  * For other VSI, the uplink_seid equals to uplink VSI's
4209                  * uplink_seid since they share same VEB
4210                  */
4211                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4212                 ctxt.pf_num = hw->pf_id;
4213                 ctxt.vf_num = 0;
4214                 ctxt.uplink_seid = vsi->uplink_seid;
4215                 ctxt.connection_type = 0x1;
4216                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4217
4218                 ctxt.info.valid_sections |=
4219                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4220                 /* user_param carries flag to enable loop back */
4221                 if (user_param) {
4222                         ctxt.info.switch_id =
4223                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4224                         ctxt.info.switch_id |=
4225                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4226                 }
4227
4228                 /* Configure port/vlan */
4229                 ctxt.info.valid_sections |=
4230                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4231                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4232                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4233                                                 I40E_DEFAULT_TCMAP);
4234                 if (ret != I40E_SUCCESS) {
4235                         PMD_DRV_LOG(ERR, "Failed to configure "
4236                                         "TC queue mapping");
4237                         goto fail_msix_alloc;
4238                 }
4239                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4240                 ctxt.info.valid_sections |=
4241                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4242         } else if (type == I40E_VSI_FDIR) {
4243                 memset(&ctxt, 0, sizeof(ctxt));
4244                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4245                 ctxt.pf_num = hw->pf_id;
4246                 ctxt.vf_num = 0;
4247                 ctxt.uplink_seid = vsi->uplink_seid;
4248                 ctxt.connection_type = 0x1;     /* regular data port */
4249                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4250                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4251                                                 I40E_DEFAULT_TCMAP);
4252                 if (ret != I40E_SUCCESS) {
4253                         PMD_DRV_LOG(ERR, "Failed to configure "
4254                                         "TC queue mapping.");
4255                         goto fail_msix_alloc;
4256                 }
4257                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4258                 ctxt.info.valid_sections |=
4259                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4260         } else {
4261                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4262                 goto fail_msix_alloc;
4263         }
4264
4265         if (vsi->type != I40E_VSI_MAIN) {
4266                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4267                 if (ret != I40E_SUCCESS) {
4268                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4269                                     hw->aq.asq_last_status);
4270                         goto fail_msix_alloc;
4271                 }
4272                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4273                 vsi->info.valid_sections = 0;
4274                 vsi->seid = ctxt.seid;
4275                 vsi->vsi_id = ctxt.vsi_number;
4276                 vsi->sib_vsi_list.vsi = vsi;
4277                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4278                                 &vsi->sib_vsi_list, list);
4279         }
4280
4281         /* MAC/VLAN configuration */
4282         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4283         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4284
4285         ret = i40e_vsi_add_mac(vsi, &filter);
4286         if (ret != I40E_SUCCESS) {
4287                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4288                 goto fail_msix_alloc;
4289         }
4290
4291         /* Get VSI BW information */
4292         i40e_vsi_get_bw_config(vsi);
4293         return vsi;
4294 fail_msix_alloc:
4295         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4296 fail_queue_alloc:
4297         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4298 fail_mem:
4299         rte_free(vsi);
4300         return NULL;
4301 }
4302
4303 /* Configure vlan filter on or off */
4304 int
4305 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4306 {
4307         int i, num;
4308         struct i40e_mac_filter *f;
4309         struct i40e_mac_filter_info *mac_filter;
4310         enum rte_mac_filter_type desired_filter;
4311         int ret = I40E_SUCCESS;
4312
4313         if (on) {
4314                 /* Filter to match MAC and VLAN */
4315                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4316         } else {
4317                 /* Filter to match only MAC */
4318                 desired_filter = RTE_MAC_PERFECT_MATCH;
4319         }
4320
4321         num = vsi->mac_num;
4322
4323         mac_filter = rte_zmalloc("mac_filter_info_data",
4324                                  num * sizeof(*mac_filter), 0);
4325         if (mac_filter == NULL) {
4326                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4327                 return I40E_ERR_NO_MEMORY;
4328         }
4329
4330         i = 0;
4331
4332         /* Remove all existing mac */
4333         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4334                 mac_filter[i] = f->mac_info;
4335                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4336                 if (ret) {
4337                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4338                                     on ? "enable" : "disable");
4339                         goto DONE;
4340                 }
4341                 i++;
4342         }
4343
4344         /* Override with new filter */
4345         for (i = 0; i < num; i++) {
4346                 mac_filter[i].filter_type = desired_filter;
4347                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4348                 if (ret) {
4349                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4350                                     on ? "enable" : "disable");
4351                         goto DONE;
4352                 }
4353         }
4354
4355 DONE:
4356         rte_free(mac_filter);
4357         return ret;
4358 }
4359
4360 /* Configure vlan stripping on or off */
4361 int
4362 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4363 {
4364         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4365         struct i40e_vsi_context ctxt;
4366         uint8_t vlan_flags;
4367         int ret = I40E_SUCCESS;
4368
4369         /* Check if it has been already on or off */
4370         if (vsi->info.valid_sections &
4371                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4372                 if (on) {
4373                         if ((vsi->info.port_vlan_flags &
4374                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4375                                 return 0; /* already on */
4376                 } else {
4377                         if ((vsi->info.port_vlan_flags &
4378                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4379                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4380                                 return 0; /* already off */
4381                 }
4382         }
4383
4384         if (on)
4385                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4386         else
4387                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4388         vsi->info.valid_sections =
4389                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4390         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4391         vsi->info.port_vlan_flags |= vlan_flags;
4392         ctxt.seid = vsi->seid;
4393         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4394         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4395         if (ret)
4396                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4397                             on ? "enable" : "disable");
4398
4399         return ret;
4400 }
4401
4402 static int
4403 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4404 {
4405         struct rte_eth_dev_data *data = dev->data;
4406         int ret;
4407         int mask = 0;
4408
4409         /* Apply vlan offload setting */
4410         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4411         i40e_vlan_offload_set(dev, mask);
4412
4413         /* Apply double-vlan setting, not implemented yet */
4414
4415         /* Apply pvid setting */
4416         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4417                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4418         if (ret)
4419                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4420
4421         return ret;
4422 }
4423
4424 static int
4425 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4426 {
4427         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4428
4429         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4430 }
4431
4432 static int
4433 i40e_update_flow_control(struct i40e_hw *hw)
4434 {
4435 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4436         struct i40e_link_status link_status;
4437         uint32_t rxfc = 0, txfc = 0, reg;
4438         uint8_t an_info;
4439         int ret;
4440
4441         memset(&link_status, 0, sizeof(link_status));
4442         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4443         if (ret != I40E_SUCCESS) {
4444                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4445                 goto write_reg; /* Disable flow control */
4446         }
4447
4448         an_info = hw->phy.link_info.an_info;
4449         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4450                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4451                 ret = I40E_ERR_NOT_READY;
4452                 goto write_reg; /* Disable flow control */
4453         }
4454         /**
4455          * If link auto negotiation is enabled, flow control needs to
4456          * be configured according to it
4457          */
4458         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4459         case I40E_LINK_PAUSE_RXTX:
4460                 rxfc = 1;
4461                 txfc = 1;
4462                 hw->fc.current_mode = I40E_FC_FULL;
4463                 break;
4464         case I40E_AQ_LINK_PAUSE_RX:
4465                 rxfc = 1;
4466                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4467                 break;
4468         case I40E_AQ_LINK_PAUSE_TX:
4469                 txfc = 1;
4470                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4471                 break;
4472         default:
4473                 hw->fc.current_mode = I40E_FC_NONE;
4474                 break;
4475         }
4476
4477 write_reg:
4478         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4479                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4480         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4481         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4482         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4483         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4484
4485         return ret;
4486 }
4487
4488 /* PF setup */
4489 static int
4490 i40e_pf_setup(struct i40e_pf *pf)
4491 {
4492         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4493         struct i40e_filter_control_settings settings;
4494         struct i40e_vsi *vsi;
4495         int ret;
4496
4497         /* Clear all stats counters */
4498         pf->offset_loaded = FALSE;
4499         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4500         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4501
4502         ret = i40e_pf_get_switch_config(pf);
4503         if (ret != I40E_SUCCESS) {
4504                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4505                 return ret;
4506         }
4507         if (pf->flags & I40E_FLAG_FDIR) {
4508                 /* make queue allocated first, let FDIR use queue pair 0*/
4509                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4510                 if (ret != I40E_FDIR_QUEUE_ID) {
4511                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4512                                     " ret =%d", ret);
4513                         pf->flags &= ~I40E_FLAG_FDIR;
4514                 }
4515         }
4516         /*  main VSI setup */
4517         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4518         if (!vsi) {
4519                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4520                 return I40E_ERR_NOT_READY;
4521         }
4522         pf->main_vsi = vsi;
4523
4524         /* Configure filter control */
4525         memset(&settings, 0, sizeof(settings));
4526         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4527                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4528         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4529                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4530         else {
4531                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4532                                                 hw->func_caps.rss_table_size);
4533                 return I40E_ERR_PARAM;
4534         }
4535         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4536                         "size: %u\n", hw->func_caps.rss_table_size);
4537         pf->hash_lut_size = hw->func_caps.rss_table_size;
4538
4539         /* Enable ethtype and macvlan filters */
4540         settings.enable_ethtype = TRUE;
4541         settings.enable_macvlan = TRUE;
4542         ret = i40e_set_filter_control(hw, &settings);
4543         if (ret)
4544                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4545                                                                 ret);
4546
4547         /* Update flow control according to the auto negotiation */
4548         i40e_update_flow_control(hw);
4549
4550         return I40E_SUCCESS;
4551 }
4552
4553 int
4554 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4555 {
4556         uint32_t reg;
4557         uint16_t j;
4558
4559         /**
4560          * Set or clear TX Queue Disable flags,
4561          * which is required by hardware.
4562          */
4563         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4564         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4565
4566         /* Wait until the request is finished */
4567         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4568                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4569                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4570                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4571                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4572                                                         & 0x1))) {
4573                         break;
4574                 }
4575         }
4576         if (on) {
4577                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4578                         return I40E_SUCCESS; /* already on, skip next steps */
4579
4580                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4581                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4582         } else {
4583                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4584                         return I40E_SUCCESS; /* already off, skip next steps */
4585                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4586         }
4587         /* Write the register */
4588         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4589         /* Check the result */
4590         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4591                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4592                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4593                 if (on) {
4594                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4595                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4596                                 break;
4597                 } else {
4598                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4599                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4600                                 break;
4601                 }
4602         }
4603         /* Check if it is timeout */
4604         if (j >= I40E_CHK_Q_ENA_COUNT) {
4605                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4606                             (on ? "enable" : "disable"), q_idx);
4607                 return I40E_ERR_TIMEOUT;
4608         }
4609
4610         return I40E_SUCCESS;
4611 }
4612
4613 /* Swith on or off the tx queues */
4614 static int
4615 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4616 {
4617         struct rte_eth_dev_data *dev_data = pf->dev_data;
4618         struct i40e_tx_queue *txq;
4619         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4620         uint16_t i;
4621         int ret;
4622
4623         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4624                 txq = dev_data->tx_queues[i];
4625                 /* Don't operate the queue if not configured or
4626                  * if starting only per queue */
4627                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4628                         continue;
4629                 if (on)
4630                         ret = i40e_dev_tx_queue_start(dev, i);
4631                 else
4632                         ret = i40e_dev_tx_queue_stop(dev, i);
4633                 if ( ret != I40E_SUCCESS)
4634                         return ret;
4635         }
4636
4637         return I40E_SUCCESS;
4638 }
4639
4640 int
4641 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4642 {
4643         uint32_t reg;
4644         uint16_t j;
4645
4646         /* Wait until the request is finished */
4647         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4648                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4649                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4650                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4651                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4652                         break;
4653         }
4654
4655         if (on) {
4656                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4657                         return I40E_SUCCESS; /* Already on, skip next steps */
4658                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4659         } else {
4660                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4661                         return I40E_SUCCESS; /* Already off, skip next steps */
4662                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4663         }
4664
4665         /* Write the register */
4666         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4667         /* Check the result */
4668         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4669                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4670                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4671                 if (on) {
4672                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4673                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4674                                 break;
4675                 } else {
4676                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4677                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4678                                 break;
4679                 }
4680         }
4681
4682         /* Check if it is timeout */
4683         if (j >= I40E_CHK_Q_ENA_COUNT) {
4684                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4685                             (on ? "enable" : "disable"), q_idx);
4686                 return I40E_ERR_TIMEOUT;
4687         }
4688
4689         return I40E_SUCCESS;
4690 }
4691 /* Switch on or off the rx queues */
4692 static int
4693 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4694 {
4695         struct rte_eth_dev_data *dev_data = pf->dev_data;
4696         struct i40e_rx_queue *rxq;
4697         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4698         uint16_t i;
4699         int ret;
4700
4701         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4702                 rxq = dev_data->rx_queues[i];
4703                 /* Don't operate the queue if not configured or
4704                  * if starting only per queue */
4705                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4706                         continue;
4707                 if (on)
4708                         ret = i40e_dev_rx_queue_start(dev, i);
4709                 else
4710                         ret = i40e_dev_rx_queue_stop(dev, i);
4711                 if (ret != I40E_SUCCESS)
4712                         return ret;
4713         }
4714
4715         return I40E_SUCCESS;
4716 }
4717
4718 /* Switch on or off all the rx/tx queues */
4719 int
4720 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4721 {
4722         int ret;
4723
4724         if (on) {
4725                 /* enable rx queues before enabling tx queues */
4726                 ret = i40e_dev_switch_rx_queues(pf, on);
4727                 if (ret) {
4728                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4729                         return ret;
4730                 }
4731                 ret = i40e_dev_switch_tx_queues(pf, on);
4732         } else {
4733                 /* Stop tx queues before stopping rx queues */
4734                 ret = i40e_dev_switch_tx_queues(pf, on);
4735                 if (ret) {
4736                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4737                         return ret;
4738                 }
4739                 ret = i40e_dev_switch_rx_queues(pf, on);
4740         }
4741
4742         return ret;
4743 }
4744
4745 /* Initialize VSI for TX */
4746 static int
4747 i40e_dev_tx_init(struct i40e_pf *pf)
4748 {
4749         struct rte_eth_dev_data *data = pf->dev_data;
4750         uint16_t i;
4751         uint32_t ret = I40E_SUCCESS;
4752         struct i40e_tx_queue *txq;
4753
4754         for (i = 0; i < data->nb_tx_queues; i++) {
4755                 txq = data->tx_queues[i];
4756                 if (!txq || !txq->q_set)
4757                         continue;
4758                 ret = i40e_tx_queue_init(txq);
4759                 if (ret != I40E_SUCCESS)
4760                         break;
4761         }
4762         if (ret == I40E_SUCCESS)
4763                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4764                                      ->eth_dev);
4765
4766         return ret;
4767 }
4768
4769 /* Initialize VSI for RX */
4770 static int
4771 i40e_dev_rx_init(struct i40e_pf *pf)
4772 {
4773         struct rte_eth_dev_data *data = pf->dev_data;
4774         int ret = I40E_SUCCESS;
4775         uint16_t i;
4776         struct i40e_rx_queue *rxq;
4777
4778         i40e_pf_config_mq_rx(pf);
4779         for (i = 0; i < data->nb_rx_queues; i++) {
4780                 rxq = data->rx_queues[i];
4781                 if (!rxq || !rxq->q_set)
4782                         continue;
4783
4784                 ret = i40e_rx_queue_init(rxq);
4785                 if (ret != I40E_SUCCESS) {
4786                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4787                                     "initialization");
4788                         break;
4789                 }
4790         }
4791         if (ret == I40E_SUCCESS)
4792                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4793                                      ->eth_dev);
4794
4795         return ret;
4796 }
4797
4798 static int
4799 i40e_dev_rxtx_init(struct i40e_pf *pf)
4800 {
4801         int err;
4802
4803         err = i40e_dev_tx_init(pf);
4804         if (err) {
4805                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4806                 return err;
4807         }
4808         err = i40e_dev_rx_init(pf);
4809         if (err) {
4810                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4811                 return err;
4812         }
4813
4814         return err;
4815 }
4816
4817 static int
4818 i40e_vmdq_setup(struct rte_eth_dev *dev)
4819 {
4820         struct rte_eth_conf *conf = &dev->data->dev_conf;
4821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4822         int i, err, conf_vsis, j, loop;
4823         struct i40e_vsi *vsi;
4824         struct i40e_vmdq_info *vmdq_info;
4825         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4826         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4827
4828         /*
4829          * Disable interrupt to avoid message from VF. Furthermore, it will
4830          * avoid race condition in VSI creation/destroy.
4831          */
4832         i40e_pf_disable_irq0(hw);
4833
4834         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4835                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4836                 return -ENOTSUP;
4837         }
4838
4839         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4840         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4841                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4842                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4843                         pf->max_nb_vmdq_vsi);
4844                 return -ENOTSUP;
4845         }
4846
4847         if (pf->vmdq != NULL) {
4848                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4849                 return 0;
4850         }
4851
4852         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4853                                 sizeof(*vmdq_info) * conf_vsis, 0);
4854
4855         if (pf->vmdq == NULL) {
4856                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4857                 return -ENOMEM;
4858         }
4859
4860         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4861
4862         /* Create VMDQ VSI */
4863         for (i = 0; i < conf_vsis; i++) {
4864                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4865                                 vmdq_conf->enable_loop_back);
4866                 if (vsi == NULL) {
4867                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4868                         err = -1;
4869                         goto err_vsi_setup;
4870                 }
4871                 vmdq_info = &pf->vmdq[i];
4872                 vmdq_info->pf = pf;
4873                 vmdq_info->vsi = vsi;
4874         }
4875         pf->nb_cfg_vmdq_vsi = conf_vsis;
4876
4877         /* Configure Vlan */
4878         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4879         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4880                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4881                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4882                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4883                                         vmdq_conf->pool_map[i].vlan_id, j);
4884
4885                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4886                                                 vmdq_conf->pool_map[i].vlan_id);
4887                                 if (err) {
4888                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4889                                         err = -1;
4890                                         goto err_vsi_setup;
4891                                 }
4892                         }
4893                 }
4894         }
4895
4896         i40e_pf_enable_irq0(hw);
4897
4898         return 0;
4899
4900 err_vsi_setup:
4901         for (i = 0; i < conf_vsis; i++)
4902                 if (pf->vmdq[i].vsi == NULL)
4903                         break;
4904                 else
4905                         i40e_vsi_release(pf->vmdq[i].vsi);
4906
4907         rte_free(pf->vmdq);
4908         pf->vmdq = NULL;
4909         i40e_pf_enable_irq0(hw);
4910         return err;
4911 }
4912
4913 static void
4914 i40e_stat_update_32(struct i40e_hw *hw,
4915                    uint32_t reg,
4916                    bool offset_loaded,
4917                    uint64_t *offset,
4918                    uint64_t *stat)
4919 {
4920         uint64_t new_data;
4921
4922         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4923         if (!offset_loaded)
4924                 *offset = new_data;
4925
4926         if (new_data >= *offset)
4927                 *stat = (uint64_t)(new_data - *offset);
4928         else
4929                 *stat = (uint64_t)((new_data +
4930                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4931 }
4932
4933 static void
4934 i40e_stat_update_48(struct i40e_hw *hw,
4935                    uint32_t hireg,
4936                    uint32_t loreg,
4937                    bool offset_loaded,
4938                    uint64_t *offset,
4939                    uint64_t *stat)
4940 {
4941         uint64_t new_data;
4942
4943         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4944         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4945                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4946
4947         if (!offset_loaded)
4948                 *offset = new_data;
4949
4950         if (new_data >= *offset)
4951                 *stat = new_data - *offset;
4952         else
4953                 *stat = (uint64_t)((new_data +
4954                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4955
4956         *stat &= I40E_48_BIT_MASK;
4957 }
4958
4959 /* Disable IRQ0 */
4960 void
4961 i40e_pf_disable_irq0(struct i40e_hw *hw)
4962 {
4963         /* Disable all interrupt types */
4964         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4965         I40E_WRITE_FLUSH(hw);
4966 }
4967
4968 /* Enable IRQ0 */
4969 void
4970 i40e_pf_enable_irq0(struct i40e_hw *hw)
4971 {
4972         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4973                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4974                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4975                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4976         I40E_WRITE_FLUSH(hw);
4977 }
4978
4979 static void
4980 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4981 {
4982         /* read pending request and disable first */
4983         i40e_pf_disable_irq0(hw);
4984         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4985         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4986                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4987
4988         if (no_queue)
4989                 /* Link no queues with irq0 */
4990                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4991                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4992 }
4993
4994 static void
4995 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4996 {
4997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4999         int i;
5000         uint16_t abs_vf_id;
5001         uint32_t index, offset, val;
5002
5003         if (!pf->vfs)
5004                 return;
5005         /**
5006          * Try to find which VF trigger a reset, use absolute VF id to access
5007          * since the reg is global register.
5008          */
5009         for (i = 0; i < pf->vf_num; i++) {
5010                 abs_vf_id = hw->func_caps.vf_base_id + i;
5011                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5012                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5013                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5014                 /* VFR event occured */
5015                 if (val & (0x1 << offset)) {
5016                         int ret;
5017
5018                         /* Clear the event first */
5019                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5020                                                         (0x1 << offset));
5021                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5022                         /**
5023                          * Only notify a VF reset event occured,
5024                          * don't trigger another SW reset
5025                          */
5026                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5027                         if (ret != I40E_SUCCESS)
5028                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5029                 }
5030         }
5031 }
5032
5033 static void
5034 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5035 {
5036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5037         struct i40e_arq_event_info info;
5038         uint16_t pending, opcode;
5039         int ret;
5040
5041         info.buf_len = I40E_AQ_BUF_SZ;
5042         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5043         if (!info.msg_buf) {
5044                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5045                 return;
5046         }
5047
5048         pending = 1;
5049         while (pending) {
5050                 ret = i40e_clean_arq_element(hw, &info, &pending);
5051
5052                 if (ret != I40E_SUCCESS) {
5053                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5054                                     "aq_err: %u", hw->aq.asq_last_status);
5055                         break;
5056                 }
5057                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5058
5059                 switch (opcode) {
5060                 case i40e_aqc_opc_send_msg_to_pf:
5061                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5062                         i40e_pf_host_handle_vf_msg(dev,
5063                                         rte_le_to_cpu_16(info.desc.retval),
5064                                         rte_le_to_cpu_32(info.desc.cookie_high),
5065                                         rte_le_to_cpu_32(info.desc.cookie_low),
5066                                         info.msg_buf,
5067                                         info.msg_len);
5068                         break;
5069                 default:
5070                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5071                                     opcode);
5072                         break;
5073                 }
5074         }
5075         rte_free(info.msg_buf);
5076 }
5077
5078 /*
5079  * Interrupt handler is registered as the alarm callback for handling LSC
5080  * interrupt in a definite of time, in order to wait the NIC into a stable
5081  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5082  * no need for link down interrupt.
5083  */
5084 static void
5085 i40e_dev_interrupt_delayed_handler(void *param)
5086 {
5087         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5089         uint32_t icr0;
5090
5091         /* read interrupt causes again */
5092         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5093
5094 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5095         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5096                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5097         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5098                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5099         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5100                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5101         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5102                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5103         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5104                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5105                                                                 "state\n");
5106         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5107                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5108         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5109                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5110 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5111
5112         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5113                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5114                 i40e_dev_handle_vfr_event(dev);
5115         }
5116         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5117                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5118                 i40e_dev_handle_aq_msg(dev);
5119         }
5120
5121         /* handle the link up interrupt in an alarm callback */
5122         i40e_dev_link_update(dev, 0);
5123         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5124
5125         i40e_pf_enable_irq0(hw);
5126         rte_intr_enable(&(dev->pci_dev->intr_handle));
5127 }
5128
5129 /**
5130  * Interrupt handler triggered by NIC  for handling
5131  * specific interrupt.
5132  *
5133  * @param handle
5134  *  Pointer to interrupt handle.
5135  * @param param
5136  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5137  *
5138  * @return
5139  *  void
5140  */
5141 static void
5142 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5143                            void *param)
5144 {
5145         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5146         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147         uint32_t icr0;
5148
5149         /* Disable interrupt */
5150         i40e_pf_disable_irq0(hw);
5151
5152         /* read out interrupt causes */
5153         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5154
5155         /* No interrupt event indicated */
5156         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5157                 PMD_DRV_LOG(INFO, "No interrupt event");
5158                 goto done;
5159         }
5160 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5161         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5162                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5163         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5164                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5165         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5166                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5167         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5168                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5169         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5170                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5171         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5172                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5173         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5174                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5175 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5176
5177         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5178                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5179                 i40e_dev_handle_vfr_event(dev);
5180         }
5181         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5182                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5183                 i40e_dev_handle_aq_msg(dev);
5184         }
5185
5186         /* Link Status Change interrupt */
5187         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5188 #define I40E_US_PER_SECOND 1000000
5189                 struct rte_eth_link link;
5190
5191                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5192                 memset(&link, 0, sizeof(link));
5193                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5194                 i40e_dev_link_update(dev, 0);
5195
5196                 /*
5197                  * For link up interrupt, it needs to wait 1 second to let the
5198                  * hardware be a stable state. Otherwise several consecutive
5199                  * interrupts can be observed.
5200                  * For link down interrupt, no need to wait.
5201                  */
5202                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5203                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5204                         return;
5205                 else
5206                         _rte_eth_dev_callback_process(dev,
5207                                 RTE_ETH_EVENT_INTR_LSC);
5208         }
5209
5210 done:
5211         /* Enable interrupt */
5212         i40e_pf_enable_irq0(hw);
5213         rte_intr_enable(&(dev->pci_dev->intr_handle));
5214 }
5215
5216 static int
5217 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5218                          struct i40e_macvlan_filter *filter,
5219                          int total)
5220 {
5221         int ele_num, ele_buff_size;
5222         int num, actual_num, i;
5223         uint16_t flags;
5224         int ret = I40E_SUCCESS;
5225         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5226         struct i40e_aqc_add_macvlan_element_data *req_list;
5227
5228         if (filter == NULL  || total == 0)
5229                 return I40E_ERR_PARAM;
5230         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5231         ele_buff_size = hw->aq.asq_buf_size;
5232
5233         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5234         if (req_list == NULL) {
5235                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5236                 return I40E_ERR_NO_MEMORY;
5237         }
5238
5239         num = 0;
5240         do {
5241                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5242                 memset(req_list, 0, ele_buff_size);
5243
5244                 for (i = 0; i < actual_num; i++) {
5245                         (void)rte_memcpy(req_list[i].mac_addr,
5246                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5247                         req_list[i].vlan_tag =
5248                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5249
5250                         switch (filter[num + i].filter_type) {
5251                         case RTE_MAC_PERFECT_MATCH:
5252                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5253                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5254                                 break;
5255                         case RTE_MACVLAN_PERFECT_MATCH:
5256                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5257                                 break;
5258                         case RTE_MAC_HASH_MATCH:
5259                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5260                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5261                                 break;
5262                         case RTE_MACVLAN_HASH_MATCH:
5263                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5264                                 break;
5265                         default:
5266                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5267                                 ret = I40E_ERR_PARAM;
5268                                 goto DONE;
5269                         }
5270
5271                         req_list[i].queue_number = 0;
5272
5273                         req_list[i].flags = rte_cpu_to_le_16(flags);
5274                 }
5275
5276                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5277                                                 actual_num, NULL);
5278                 if (ret != I40E_SUCCESS) {
5279                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5280                         goto DONE;
5281                 }
5282                 num += actual_num;
5283         } while (num < total);
5284
5285 DONE:
5286         rte_free(req_list);
5287         return ret;
5288 }
5289
5290 static int
5291 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5292                             struct i40e_macvlan_filter *filter,
5293                             int total)
5294 {
5295         int ele_num, ele_buff_size;
5296         int num, actual_num, i;
5297         uint16_t flags;
5298         int ret = I40E_SUCCESS;
5299         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5300         struct i40e_aqc_remove_macvlan_element_data *req_list;
5301
5302         if (filter == NULL  || total == 0)
5303                 return I40E_ERR_PARAM;
5304
5305         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5306         ele_buff_size = hw->aq.asq_buf_size;
5307
5308         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5309         if (req_list == NULL) {
5310                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5311                 return I40E_ERR_NO_MEMORY;
5312         }
5313
5314         num = 0;
5315         do {
5316                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5317                 memset(req_list, 0, ele_buff_size);
5318
5319                 for (i = 0; i < actual_num; i++) {
5320                         (void)rte_memcpy(req_list[i].mac_addr,
5321                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5322                         req_list[i].vlan_tag =
5323                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5324
5325                         switch (filter[num + i].filter_type) {
5326                         case RTE_MAC_PERFECT_MATCH:
5327                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5328                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5329                                 break;
5330                         case RTE_MACVLAN_PERFECT_MATCH:
5331                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5332                                 break;
5333                         case RTE_MAC_HASH_MATCH:
5334                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5335                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5336                                 break;
5337                         case RTE_MACVLAN_HASH_MATCH:
5338                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5339                                 break;
5340                         default:
5341                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5342                                 ret = I40E_ERR_PARAM;
5343                                 goto DONE;
5344                         }
5345                         req_list[i].flags = rte_cpu_to_le_16(flags);
5346                 }
5347
5348                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5349                                                 actual_num, NULL);
5350                 if (ret != I40E_SUCCESS) {
5351                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5352                         goto DONE;
5353                 }
5354                 num += actual_num;
5355         } while (num < total);
5356
5357 DONE:
5358         rte_free(req_list);
5359         return ret;
5360 }
5361
5362 /* Find out specific MAC filter */
5363 static struct i40e_mac_filter *
5364 i40e_find_mac_filter(struct i40e_vsi *vsi,
5365                          struct ether_addr *macaddr)
5366 {
5367         struct i40e_mac_filter *f;
5368
5369         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5370                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5371                         return f;
5372         }
5373
5374         return NULL;
5375 }
5376
5377 static bool
5378 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5379                          uint16_t vlan_id)
5380 {
5381         uint32_t vid_idx, vid_bit;
5382
5383         if (vlan_id > ETH_VLAN_ID_MAX)
5384                 return 0;
5385
5386         vid_idx = I40E_VFTA_IDX(vlan_id);
5387         vid_bit = I40E_VFTA_BIT(vlan_id);
5388
5389         if (vsi->vfta[vid_idx] & vid_bit)
5390                 return 1;
5391         else
5392                 return 0;
5393 }
5394
5395 static void
5396 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5397                          uint16_t vlan_id, bool on)
5398 {
5399         uint32_t vid_idx, vid_bit;
5400
5401         if (vlan_id > ETH_VLAN_ID_MAX)
5402                 return;
5403
5404         vid_idx = I40E_VFTA_IDX(vlan_id);
5405         vid_bit = I40E_VFTA_BIT(vlan_id);
5406
5407         if (on)
5408                 vsi->vfta[vid_idx] |= vid_bit;
5409         else
5410                 vsi->vfta[vid_idx] &= ~vid_bit;
5411 }
5412
5413 /**
5414  * Find all vlan options for specific mac addr,
5415  * return with actual vlan found.
5416  */
5417 static inline int
5418 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5419                            struct i40e_macvlan_filter *mv_f,
5420                            int num, struct ether_addr *addr)
5421 {
5422         int i;
5423         uint32_t j, k;
5424
5425         /**
5426          * Not to use i40e_find_vlan_filter to decrease the loop time,
5427          * although the code looks complex.
5428           */
5429         if (num < vsi->vlan_num)
5430                 return I40E_ERR_PARAM;
5431
5432         i = 0;
5433         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5434                 if (vsi->vfta[j]) {
5435                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5436                                 if (vsi->vfta[j] & (1 << k)) {
5437                                         if (i > num - 1) {
5438                                                 PMD_DRV_LOG(ERR, "vlan number "
5439                                                             "not match");
5440                                                 return I40E_ERR_PARAM;
5441                                         }
5442                                         (void)rte_memcpy(&mv_f[i].macaddr,
5443                                                         addr, ETH_ADDR_LEN);
5444                                         mv_f[i].vlan_id =
5445                                                 j * I40E_UINT32_BIT_SIZE + k;
5446                                         i++;
5447                                 }
5448                         }
5449                 }
5450         }
5451         return I40E_SUCCESS;
5452 }
5453
5454 static inline int
5455 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5456                            struct i40e_macvlan_filter *mv_f,
5457                            int num,
5458                            uint16_t vlan)
5459 {
5460         int i = 0;
5461         struct i40e_mac_filter *f;
5462
5463         if (num < vsi->mac_num)
5464                 return I40E_ERR_PARAM;
5465
5466         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5467                 if (i > num - 1) {
5468                         PMD_DRV_LOG(ERR, "buffer number not match");
5469                         return I40E_ERR_PARAM;
5470                 }
5471                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5472                                 ETH_ADDR_LEN);
5473                 mv_f[i].vlan_id = vlan;
5474                 mv_f[i].filter_type = f->mac_info.filter_type;
5475                 i++;
5476         }
5477
5478         return I40E_SUCCESS;
5479 }
5480
5481 static int
5482 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5483 {
5484         int i, num;
5485         struct i40e_mac_filter *f;
5486         struct i40e_macvlan_filter *mv_f;
5487         int ret = I40E_SUCCESS;
5488
5489         if (vsi == NULL || vsi->mac_num == 0)
5490                 return I40E_ERR_PARAM;
5491
5492         /* Case that no vlan is set */
5493         if (vsi->vlan_num == 0)
5494                 num = vsi->mac_num;
5495         else
5496                 num = vsi->mac_num * vsi->vlan_num;
5497
5498         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5499         if (mv_f == NULL) {
5500                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5501                 return I40E_ERR_NO_MEMORY;
5502         }
5503
5504         i = 0;
5505         if (vsi->vlan_num == 0) {
5506                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5507                         (void)rte_memcpy(&mv_f[i].macaddr,
5508                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5509                         mv_f[i].vlan_id = 0;
5510                         i++;
5511                 }
5512         } else {
5513                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5514                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5515                                         vsi->vlan_num, &f->mac_info.mac_addr);
5516                         if (ret != I40E_SUCCESS)
5517                                 goto DONE;
5518                         i += vsi->vlan_num;
5519                 }
5520         }
5521
5522         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5523 DONE:
5524         rte_free(mv_f);
5525
5526         return ret;
5527 }
5528
5529 int
5530 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5531 {
5532         struct i40e_macvlan_filter *mv_f;
5533         int mac_num;
5534         int ret = I40E_SUCCESS;
5535
5536         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5537                 return I40E_ERR_PARAM;
5538
5539         /* If it's already set, just return */
5540         if (i40e_find_vlan_filter(vsi,vlan))
5541                 return I40E_SUCCESS;
5542
5543         mac_num = vsi->mac_num;
5544
5545         if (mac_num == 0) {
5546                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5547                 return I40E_ERR_PARAM;
5548         }
5549
5550         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5551
5552         if (mv_f == NULL) {
5553                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5554                 return I40E_ERR_NO_MEMORY;
5555         }
5556
5557         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5558
5559         if (ret != I40E_SUCCESS)
5560                 goto DONE;
5561
5562         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5563
5564         if (ret != I40E_SUCCESS)
5565                 goto DONE;
5566
5567         i40e_set_vlan_filter(vsi, vlan, 1);
5568
5569         vsi->vlan_num++;
5570         ret = I40E_SUCCESS;
5571 DONE:
5572         rte_free(mv_f);
5573         return ret;
5574 }
5575
5576 int
5577 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5578 {
5579         struct i40e_macvlan_filter *mv_f;
5580         int mac_num;
5581         int ret = I40E_SUCCESS;
5582
5583         /**
5584          * Vlan 0 is the generic filter for untagged packets
5585          * and can't be removed.
5586          */
5587         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5588                 return I40E_ERR_PARAM;
5589
5590         /* If can't find it, just return */
5591         if (!i40e_find_vlan_filter(vsi, vlan))
5592                 return I40E_ERR_PARAM;
5593
5594         mac_num = vsi->mac_num;
5595
5596         if (mac_num == 0) {
5597                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5598                 return I40E_ERR_PARAM;
5599         }
5600
5601         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5602
5603         if (mv_f == NULL) {
5604                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5605                 return I40E_ERR_NO_MEMORY;
5606         }
5607
5608         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5609
5610         if (ret != I40E_SUCCESS)
5611                 goto DONE;
5612
5613         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5614
5615         if (ret != I40E_SUCCESS)
5616                 goto DONE;
5617
5618         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5619         if (vsi->vlan_num == 1) {
5620                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5621                 if (ret != I40E_SUCCESS)
5622                         goto DONE;
5623
5624                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5625                 if (ret != I40E_SUCCESS)
5626                         goto DONE;
5627         }
5628
5629         i40e_set_vlan_filter(vsi, vlan, 0);
5630
5631         vsi->vlan_num--;
5632         ret = I40E_SUCCESS;
5633 DONE:
5634         rte_free(mv_f);
5635         return ret;
5636 }
5637
5638 int
5639 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5640 {
5641         struct i40e_mac_filter *f;
5642         struct i40e_macvlan_filter *mv_f;
5643         int i, vlan_num = 0;
5644         int ret = I40E_SUCCESS;
5645
5646         /* If it's add and we've config it, return */
5647         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5648         if (f != NULL)
5649                 return I40E_SUCCESS;
5650         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5651                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5652
5653                 /**
5654                  * If vlan_num is 0, that's the first time to add mac,
5655                  * set mask for vlan_id 0.
5656                  */
5657                 if (vsi->vlan_num == 0) {
5658                         i40e_set_vlan_filter(vsi, 0, 1);
5659                         vsi->vlan_num = 1;
5660                 }
5661                 vlan_num = vsi->vlan_num;
5662         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5663                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5664                 vlan_num = 1;
5665
5666         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5667         if (mv_f == NULL) {
5668                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5669                 return I40E_ERR_NO_MEMORY;
5670         }
5671
5672         for (i = 0; i < vlan_num; i++) {
5673                 mv_f[i].filter_type = mac_filter->filter_type;
5674                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5675                                 ETH_ADDR_LEN);
5676         }
5677
5678         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5679                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5680                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5681                                         &mac_filter->mac_addr);
5682                 if (ret != I40E_SUCCESS)
5683                         goto DONE;
5684         }
5685
5686         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5687         if (ret != I40E_SUCCESS)
5688                 goto DONE;
5689
5690         /* Add the mac addr into mac list */
5691         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5692         if (f == NULL) {
5693                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5694                 ret = I40E_ERR_NO_MEMORY;
5695                 goto DONE;
5696         }
5697         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5698                         ETH_ADDR_LEN);
5699         f->mac_info.filter_type = mac_filter->filter_type;
5700         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5701         vsi->mac_num++;
5702
5703         ret = I40E_SUCCESS;
5704 DONE:
5705         rte_free(mv_f);
5706
5707         return ret;
5708 }
5709
5710 int
5711 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5712 {
5713         struct i40e_mac_filter *f;
5714         struct i40e_macvlan_filter *mv_f;
5715         int i, vlan_num;
5716         enum rte_mac_filter_type filter_type;
5717         int ret = I40E_SUCCESS;
5718
5719         /* Can't find it, return an error */
5720         f = i40e_find_mac_filter(vsi, addr);
5721         if (f == NULL)
5722                 return I40E_ERR_PARAM;
5723
5724         vlan_num = vsi->vlan_num;
5725         filter_type = f->mac_info.filter_type;
5726         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5727                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5728                 if (vlan_num == 0) {
5729                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5730                         return I40E_ERR_PARAM;
5731                 }
5732         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5733                         filter_type == RTE_MAC_HASH_MATCH)
5734                 vlan_num = 1;
5735
5736         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5737         if (mv_f == NULL) {
5738                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5739                 return I40E_ERR_NO_MEMORY;
5740         }
5741
5742         for (i = 0; i < vlan_num; i++) {
5743                 mv_f[i].filter_type = filter_type;
5744                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5745                                 ETH_ADDR_LEN);
5746         }
5747         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5748                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5749                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5750                 if (ret != I40E_SUCCESS)
5751                         goto DONE;
5752         }
5753
5754         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5755         if (ret != I40E_SUCCESS)
5756                 goto DONE;
5757
5758         /* Remove the mac addr into mac list */
5759         TAILQ_REMOVE(&vsi->mac_list, f, next);
5760         rte_free(f);
5761         vsi->mac_num--;
5762
5763         ret = I40E_SUCCESS;
5764 DONE:
5765         rte_free(mv_f);
5766         return ret;
5767 }
5768
5769 /* Configure hash enable flags for RSS */
5770 uint64_t
5771 i40e_config_hena(uint64_t flags)
5772 {
5773         uint64_t hena = 0;
5774
5775         if (!flags)
5776                 return hena;
5777
5778         if (flags & ETH_RSS_FRAG_IPV4)
5779                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5780         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5781                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5782         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5783                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5784         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5785                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5786         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5787                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5788         if (flags & ETH_RSS_FRAG_IPV6)
5789                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5790         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5791                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5792         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5793                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5794         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5795                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5796         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5797                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5798         if (flags & ETH_RSS_L2_PAYLOAD)
5799                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5800
5801         return hena;
5802 }
5803
5804 /* Parse the hash enable flags */
5805 uint64_t
5806 i40e_parse_hena(uint64_t flags)
5807 {
5808         uint64_t rss_hf = 0;
5809
5810         if (!flags)
5811                 return rss_hf;
5812         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5813                 rss_hf |= ETH_RSS_FRAG_IPV4;
5814         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5815                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5816         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5817                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5818         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5819                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5820         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5821                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5822         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5823                 rss_hf |= ETH_RSS_FRAG_IPV6;
5824         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5825                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5826         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5827                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5828         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5829                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5830         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5831                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5832         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5833                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5834
5835         return rss_hf;
5836 }
5837
5838 /* Disable RSS */
5839 static void
5840 i40e_pf_disable_rss(struct i40e_pf *pf)
5841 {
5842         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5843         uint64_t hena;
5844
5845         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5846         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5847         hena &= ~I40E_RSS_HENA_ALL;
5848         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5849         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5850         I40E_WRITE_FLUSH(hw);
5851 }
5852
5853 static int
5854 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5855 {
5856         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5857         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5858         int ret = 0;
5859
5860         if (!key || key_len == 0) {
5861                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5862                 return 0;
5863         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5864                 sizeof(uint32_t)) {
5865                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5866                 return -EINVAL;
5867         }
5868
5869         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5870                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5871                         (struct i40e_aqc_get_set_rss_key_data *)key;
5872
5873                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5874                 if (ret)
5875                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5876                                      "via AQ");
5877         } else {
5878                 uint32_t *hash_key = (uint32_t *)key;
5879                 uint16_t i;
5880
5881                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5882                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5883                 I40E_WRITE_FLUSH(hw);
5884         }
5885
5886         return ret;
5887 }
5888
5889 static int
5890 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5891 {
5892         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5893         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5894         int ret;
5895
5896         if (!key || !key_len)
5897                 return -EINVAL;
5898
5899         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5900                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5901                         (struct i40e_aqc_get_set_rss_key_data *)key);
5902                 if (ret) {
5903                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5904                         return ret;
5905                 }
5906         } else {
5907                 uint32_t *key_dw = (uint32_t *)key;
5908                 uint16_t i;
5909
5910                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5911                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5912         }
5913         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5914
5915         return 0;
5916 }
5917
5918 static int
5919 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5920 {
5921         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5922         uint64_t rss_hf;
5923         uint64_t hena;
5924         int ret;
5925
5926         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5927                                rss_conf->rss_key_len);
5928         if (ret)
5929                 return ret;
5930
5931         rss_hf = rss_conf->rss_hf;
5932         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5933         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5934         hena &= ~I40E_RSS_HENA_ALL;
5935         hena |= i40e_config_hena(rss_hf);
5936         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5937         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5938         I40E_WRITE_FLUSH(hw);
5939
5940         return 0;
5941 }
5942
5943 static int
5944 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5945                          struct rte_eth_rss_conf *rss_conf)
5946 {
5947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5949         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5950         uint64_t hena;
5951
5952         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5953         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5954         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5955                 if (rss_hf != 0) /* Enable RSS */
5956                         return -EINVAL;
5957                 return 0; /* Nothing to do */
5958         }
5959         /* RSS enabled */
5960         if (rss_hf == 0) /* Disable RSS */
5961                 return -EINVAL;
5962
5963         return i40e_hw_rss_hash_set(pf, rss_conf);
5964 }
5965
5966 static int
5967 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5968                            struct rte_eth_rss_conf *rss_conf)
5969 {
5970         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5972         uint64_t hena;
5973
5974         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5975                          &rss_conf->rss_key_len);
5976
5977         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5978         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5979         rss_conf->rss_hf = i40e_parse_hena(hena);
5980
5981         return 0;
5982 }
5983
5984 static int
5985 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5986 {
5987         switch (filter_type) {
5988         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5989                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5990                 break;
5991         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5992                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5993                 break;
5994         case RTE_TUNNEL_FILTER_IMAC_TENID:
5995                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5996                 break;
5997         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5998                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5999                 break;
6000         case ETH_TUNNEL_FILTER_IMAC:
6001                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6002                 break;
6003         case ETH_TUNNEL_FILTER_OIP:
6004                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6005                 break;
6006         case ETH_TUNNEL_FILTER_IIP:
6007                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6008                 break;
6009         default:
6010                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6011                 return -EINVAL;
6012         }
6013
6014         return 0;
6015 }
6016
6017 static int
6018 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6019                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6020                         uint8_t add)
6021 {
6022         uint16_t ip_type;
6023         uint8_t i, tun_type = 0;
6024         /* internal varialbe to convert ipv6 byte order */
6025         uint32_t convert_ipv6[4];
6026         int val, ret = 0;
6027         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6028         struct i40e_vsi *vsi = pf->main_vsi;
6029         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6030         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6031
6032         cld_filter = rte_zmalloc("tunnel_filter",
6033                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6034                 0);
6035
6036         if (NULL == cld_filter) {
6037                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6038                 return -EINVAL;
6039         }
6040         pfilter = cld_filter;
6041
6042         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6043         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6044
6045         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6046         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6047                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6048                 rte_memcpy(&pfilter->ipaddr.v4.data,
6049                                 &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
6050                                 sizeof(pfilter->ipaddr.v4.data));
6051         } else {
6052                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6053                 for (i = 0; i < 4; i++) {
6054                         convert_ipv6[i] =
6055                         rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
6056                 }
6057                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6058                                 sizeof(pfilter->ipaddr.v6.data));
6059         }
6060
6061         /* check tunneled type */
6062         switch (tunnel_filter->tunnel_type) {
6063         case RTE_TUNNEL_TYPE_VXLAN:
6064                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6065                 break;
6066         case RTE_TUNNEL_TYPE_NVGRE:
6067                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6068                 break;
6069         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6070                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6071                 break;
6072         default:
6073                 /* Other tunnel types is not supported. */
6074                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6075                 rte_free(cld_filter);
6076                 return -EINVAL;
6077         }
6078
6079         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6080                                                 &pfilter->flags);
6081         if (val < 0) {
6082                 rte_free(cld_filter);
6083                 return -EINVAL;
6084         }
6085
6086         pfilter->flags |= rte_cpu_to_le_16(
6087                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6088                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6089         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6090         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6091
6092         if (add)
6093                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6094         else
6095                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6096                                                 cld_filter, 1);
6097
6098         rte_free(cld_filter);
6099         return ret;
6100 }
6101
6102 static int
6103 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6104 {
6105         uint8_t i;
6106
6107         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6108                 if (pf->vxlan_ports[i] == port)
6109                         return i;
6110         }
6111
6112         return -1;
6113 }
6114
6115 static int
6116 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6117 {
6118         int  idx, ret;
6119         uint8_t filter_idx;
6120         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6121
6122         idx = i40e_get_vxlan_port_idx(pf, port);
6123
6124         /* Check if port already exists */
6125         if (idx >= 0) {
6126                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6127                 return -EINVAL;
6128         }
6129
6130         /* Now check if there is space to add the new port */
6131         idx = i40e_get_vxlan_port_idx(pf, 0);
6132         if (idx < 0) {
6133                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6134                         "not adding port %d", port);
6135                 return -ENOSPC;
6136         }
6137
6138         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6139                                         &filter_idx, NULL);
6140         if (ret < 0) {
6141                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6142                 return -1;
6143         }
6144
6145         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6146                          port,  filter_idx);
6147
6148         /* New port: add it and mark its index in the bitmap */
6149         pf->vxlan_ports[idx] = port;
6150         pf->vxlan_bitmap |= (1 << idx);
6151
6152         if (!(pf->flags & I40E_FLAG_VXLAN))
6153                 pf->flags |= I40E_FLAG_VXLAN;
6154
6155         return 0;
6156 }
6157
6158 static int
6159 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6160 {
6161         int idx;
6162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6163
6164         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6165                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6166                 return -EINVAL;
6167         }
6168
6169         idx = i40e_get_vxlan_port_idx(pf, port);
6170
6171         if (idx < 0) {
6172                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6173                 return -EINVAL;
6174         }
6175
6176         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6177                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6178                 return -1;
6179         }
6180
6181         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6182                         port, idx);
6183
6184         pf->vxlan_ports[idx] = 0;
6185         pf->vxlan_bitmap &= ~(1 << idx);
6186
6187         if (!pf->vxlan_bitmap)
6188                 pf->flags &= ~I40E_FLAG_VXLAN;
6189
6190         return 0;
6191 }
6192
6193 /* Add UDP tunneling port */
6194 static int
6195 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6196                              struct rte_eth_udp_tunnel *udp_tunnel)
6197 {
6198         int ret = 0;
6199         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6200
6201         if (udp_tunnel == NULL)
6202                 return -EINVAL;
6203
6204         switch (udp_tunnel->prot_type) {
6205         case RTE_TUNNEL_TYPE_VXLAN:
6206                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6207                 break;
6208
6209         case RTE_TUNNEL_TYPE_GENEVE:
6210         case RTE_TUNNEL_TYPE_TEREDO:
6211                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6212                 ret = -1;
6213                 break;
6214
6215         default:
6216                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6217                 ret = -1;
6218                 break;
6219         }
6220
6221         return ret;
6222 }
6223
6224 /* Remove UDP tunneling port */
6225 static int
6226 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6227                              struct rte_eth_udp_tunnel *udp_tunnel)
6228 {
6229         int ret = 0;
6230         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6231
6232         if (udp_tunnel == NULL)
6233                 return -EINVAL;
6234
6235         switch (udp_tunnel->prot_type) {
6236         case RTE_TUNNEL_TYPE_VXLAN:
6237                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6238                 break;
6239         case RTE_TUNNEL_TYPE_GENEVE:
6240         case RTE_TUNNEL_TYPE_TEREDO:
6241                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6242                 ret = -1;
6243                 break;
6244         default:
6245                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6246                 ret = -1;
6247                 break;
6248         }
6249
6250         return ret;
6251 }
6252
6253 /* Calculate the maximum number of contiguous PF queues that are configured */
6254 static int
6255 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6256 {
6257         struct rte_eth_dev_data *data = pf->dev_data;
6258         int i, num;
6259         struct i40e_rx_queue *rxq;
6260
6261         num = 0;
6262         for (i = 0; i < pf->lan_nb_qps; i++) {
6263                 rxq = data->rx_queues[i];
6264                 if (rxq && rxq->q_set)
6265                         num++;
6266                 else
6267                         break;
6268         }
6269
6270         return num;
6271 }
6272
6273 /* Configure RSS */
6274 static int
6275 i40e_pf_config_rss(struct i40e_pf *pf)
6276 {
6277         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6278         struct rte_eth_rss_conf rss_conf;
6279         uint32_t i, lut = 0;
6280         uint16_t j, num;
6281
6282         /*
6283          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6284          * It's necessary to calulate the actual PF queues that are configured.
6285          */
6286         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6287                 num = i40e_pf_calc_configured_queues_num(pf);
6288         else
6289                 num = pf->dev_data->nb_rx_queues;
6290
6291         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6292         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6293                         num);
6294
6295         if (num == 0) {
6296                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6297                 return -ENOTSUP;
6298         }
6299
6300         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6301                 if (j == num)
6302                         j = 0;
6303                 lut = (lut << 8) | (j & ((0x1 <<
6304                         hw->func_caps.rss_table_entry_width) - 1));
6305                 if ((i & 3) == 3)
6306                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6307         }
6308
6309         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6310         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6311                 i40e_pf_disable_rss(pf);
6312                 return 0;
6313         }
6314         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6315                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6316                 /* Random default keys */
6317                 static uint32_t rss_key_default[] = {0x6b793944,
6318                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6319                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6320                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6321
6322                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6323                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6324                                                         sizeof(uint32_t);
6325         }
6326
6327         return i40e_hw_rss_hash_set(pf, &rss_conf);
6328 }
6329
6330 static int
6331 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6332                                struct rte_eth_tunnel_filter_conf *filter)
6333 {
6334         if (pf == NULL || filter == NULL) {
6335                 PMD_DRV_LOG(ERR, "Invalid parameter");
6336                 return -EINVAL;
6337         }
6338
6339         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6340                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6341                 return -EINVAL;
6342         }
6343
6344         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6345                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6346                 return -EINVAL;
6347         }
6348
6349         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6350                 (is_zero_ether_addr(&filter->outer_mac))) {
6351                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6352                 return -EINVAL;
6353         }
6354
6355         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6356                 (is_zero_ether_addr(&filter->inner_mac))) {
6357                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6358                 return -EINVAL;
6359         }
6360
6361         return 0;
6362 }
6363
6364 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6365 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6366 static int
6367 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6368 {
6369         uint32_t val, reg;
6370         int ret = -EINVAL;
6371
6372         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6373         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6374
6375         if (len == 3) {
6376                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6377         } else if (len == 4) {
6378                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6379         } else {
6380                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6381                 return ret;
6382         }
6383
6384         if (reg != val) {
6385                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6386                                                    reg, NULL);
6387                 if (ret != 0)
6388                         return ret;
6389         } else {
6390                 ret = 0;
6391         }
6392         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6393                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6394
6395         return ret;
6396 }
6397
6398 static int
6399 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6400 {
6401         int ret = -EINVAL;
6402
6403         if (!hw || !cfg)
6404                 return -EINVAL;
6405
6406         switch (cfg->cfg_type) {
6407         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6408                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6409                 break;
6410         default:
6411                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6412                 break;
6413         }
6414
6415         return ret;
6416 }
6417
6418 static int
6419 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6420                                enum rte_filter_op filter_op,
6421                                void *arg)
6422 {
6423         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6424         int ret = I40E_ERR_PARAM;
6425
6426         switch (filter_op) {
6427         case RTE_ETH_FILTER_SET:
6428                 ret = i40e_dev_global_config_set(hw,
6429                         (struct rte_eth_global_cfg *)arg);
6430                 break;
6431         default:
6432                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6433                 break;
6434         }
6435
6436         return ret;
6437 }
6438
6439 static int
6440 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6441                           enum rte_filter_op filter_op,
6442                           void *arg)
6443 {
6444         struct rte_eth_tunnel_filter_conf *filter;
6445         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6446         int ret = I40E_SUCCESS;
6447
6448         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6449
6450         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6451                 return I40E_ERR_PARAM;
6452
6453         switch (filter_op) {
6454         case RTE_ETH_FILTER_NOP:
6455                 if (!(pf->flags & I40E_FLAG_VXLAN))
6456                         ret = I40E_NOT_SUPPORTED;
6457                 break;
6458         case RTE_ETH_FILTER_ADD:
6459                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6460                 break;
6461         case RTE_ETH_FILTER_DELETE:
6462                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6463                 break;
6464         default:
6465                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6466                 ret = I40E_ERR_PARAM;
6467                 break;
6468         }
6469
6470         return ret;
6471 }
6472
6473 static int
6474 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6475 {
6476         int ret = 0;
6477         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6478
6479         /* RSS setup */
6480         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6481                 ret = i40e_pf_config_rss(pf);
6482         else
6483                 i40e_pf_disable_rss(pf);
6484
6485         return ret;
6486 }
6487
6488 /* Get the symmetric hash enable configurations per port */
6489 static void
6490 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6491 {
6492         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6493
6494         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6495 }
6496
6497 /* Set the symmetric hash enable configurations per port */
6498 static void
6499 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6500 {
6501         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6502
6503         if (enable > 0) {
6504                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6505                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6506                                                         "been enabled");
6507                         return;
6508                 }
6509                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6510         } else {
6511                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6512                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6513                                                         "been disabled");
6514                         return;
6515                 }
6516                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6517         }
6518         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6519         I40E_WRITE_FLUSH(hw);
6520 }
6521
6522 /*
6523  * Get global configurations of hash function type and symmetric hash enable
6524  * per flow type (pctype). Note that global configuration means it affects all
6525  * the ports on the same NIC.
6526  */
6527 static int
6528 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6529                                    struct rte_eth_hash_global_conf *g_cfg)
6530 {
6531         uint32_t reg, mask = I40E_FLOW_TYPES;
6532         uint16_t i;
6533         enum i40e_filter_pctype pctype;
6534
6535         memset(g_cfg, 0, sizeof(*g_cfg));
6536         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6537         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6538                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6539         else
6540                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6541         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6542                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6543
6544         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6545                 if (!(mask & (1UL << i)))
6546                         continue;
6547                 mask &= ~(1UL << i);
6548                 /* Bit set indicats the coresponding flow type is supported */
6549                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6550                 pctype = i40e_flowtype_to_pctype(i);
6551                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6552                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6553                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6554         }
6555
6556         return 0;
6557 }
6558
6559 static int
6560 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6561 {
6562         uint32_t i;
6563         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6564
6565         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6566                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6567                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6568                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6569                                                 g_cfg->hash_func);
6570                 return -EINVAL;
6571         }
6572
6573         /*
6574          * As i40e supports less than 32 flow types, only first 32 bits need to
6575          * be checked.
6576          */
6577         mask0 = g_cfg->valid_bit_mask[0];
6578         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6579                 if (i == 0) {
6580                         /* Check if any unsupported flow type configured */
6581                         if ((mask0 | i40e_mask) ^ i40e_mask)
6582                                 goto mask_err;
6583                 } else {
6584                         if (g_cfg->valid_bit_mask[i])
6585                                 goto mask_err;
6586                 }
6587         }
6588
6589         return 0;
6590
6591 mask_err:
6592         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6593
6594         return -EINVAL;
6595 }
6596
6597 /*
6598  * Set global configurations of hash function type and symmetric hash enable
6599  * per flow type (pctype). Note any modifying global configuration will affect
6600  * all the ports on the same NIC.
6601  */
6602 static int
6603 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6604                                    struct rte_eth_hash_global_conf *g_cfg)
6605 {
6606         int ret;
6607         uint16_t i;
6608         uint32_t reg;
6609         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6610         enum i40e_filter_pctype pctype;
6611
6612         /* Check the input parameters */
6613         ret = i40e_hash_global_config_check(g_cfg);
6614         if (ret < 0)
6615                 return ret;
6616
6617         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6618                 if (!(mask0 & (1UL << i)))
6619                         continue;
6620                 mask0 &= ~(1UL << i);
6621                 pctype = i40e_flowtype_to_pctype(i);
6622                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6623                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6624                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6625         }
6626
6627         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6628         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6629                 /* Toeplitz */
6630                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6631                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6632                                                                 "Toeplitz");
6633                         goto out;
6634                 }
6635                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6636         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6637                 /* Simple XOR */
6638                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6639                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6640                                                         "Simple XOR");
6641                         goto out;
6642                 }
6643                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6644         } else
6645                 /* Use the default, and keep it as it is */
6646                 goto out;
6647
6648         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6649
6650 out:
6651         I40E_WRITE_FLUSH(hw);
6652
6653         return 0;
6654 }
6655
6656 /**
6657  * Valid input sets for hash and flow director filters per PCTYPE
6658  */
6659 static uint64_t
6660 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6661                 enum rte_filter_type filter)
6662 {
6663         uint64_t valid;
6664
6665         static const uint64_t valid_hash_inset_table[] = {
6666                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6667                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6668                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6669                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6670                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6671                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6672                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6673                         I40E_INSET_FLEX_PAYLOAD,
6674                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6675                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6676                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6677                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6678                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6679                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6680                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6681                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6682                         I40E_INSET_FLEX_PAYLOAD,
6683                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6684                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6685                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6686                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6687                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6688                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6689                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6690                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6691                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6692                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6693                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6694                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6695                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6696                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6697                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6698                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6699                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6700                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6701                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6702                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6703                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6704                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6705                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6706                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6707                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6708                         I40E_INSET_FLEX_PAYLOAD,
6709                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6710                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6711                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6712                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6713                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6714                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6715                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6716                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6717                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6718                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6719                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6720                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6721                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6722                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6723                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6724                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6725                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6726                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6727                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6728                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6729                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6730                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6731                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6732                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6733                         I40E_INSET_FLEX_PAYLOAD,
6734                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6735                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6736                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6737                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6738                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6739                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6740                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6741                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6742                         I40E_INSET_FLEX_PAYLOAD,
6743                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6744                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6745                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6746                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6747                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6748                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6749                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6750                         I40E_INSET_FLEX_PAYLOAD,
6751                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6752                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6753                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6754                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6755                         I40E_INSET_FLEX_PAYLOAD,
6756         };
6757
6758         /**
6759          * Flow director supports only fields defined in
6760          * union rte_eth_fdir_flow.
6761          */
6762         static const uint64_t valid_fdir_inset_table[] = {
6763                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6764                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6765                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6766                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6767                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6768                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6769                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6770                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6771                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6772                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6773                 I40E_INSET_SCTP_VT,
6774                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6775                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6776                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6777                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6778                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6779                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6780                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6781                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6782                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6783                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6784                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6785                 I40E_INSET_SCTP_VT,
6786                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6787                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6788                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6789                 I40E_INSET_LAST_ETHER_TYPE,
6790         };
6791
6792         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6793                 return 0;
6794         if (filter == RTE_ETH_FILTER_HASH)
6795                 valid = valid_hash_inset_table[pctype];
6796         else
6797                 valid = valid_fdir_inset_table[pctype];
6798
6799         return valid;
6800 }
6801
6802 /**
6803  * Validate if the input set is allowed for a specific PCTYPE
6804  */
6805 static int
6806 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6807                 enum rte_filter_type filter, uint64_t inset)
6808 {
6809         uint64_t valid;
6810
6811         valid = i40e_get_valid_input_set(pctype, filter);
6812         if (inset & (~valid))
6813                 return -EINVAL;
6814
6815         return 0;
6816 }
6817
6818 /* default input set fields combination per pctype */
6819 static uint64_t
6820 i40e_get_default_input_set(uint16_t pctype)
6821 {
6822         static const uint64_t default_inset_table[] = {
6823                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6824                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6825                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6826                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6827                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6828                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6829                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6830                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6831                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6832                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6833                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6834                         I40E_INSET_SCTP_VT,
6835                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6836                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6837                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6838                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6839                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6840                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6841                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6842                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6843                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6844                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6845                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6846                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6847                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6848                         I40E_INSET_SCTP_VT,
6849                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6850                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6851                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6852                         I40E_INSET_LAST_ETHER_TYPE,
6853         };
6854
6855         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6856                 return 0;
6857
6858         return default_inset_table[pctype];
6859 }
6860
6861 /**
6862  * Parse the input set from index to logical bit masks
6863  */
6864 static int
6865 i40e_parse_input_set(uint64_t *inset,
6866                      enum i40e_filter_pctype pctype,
6867                      enum rte_eth_input_set_field *field,
6868                      uint16_t size)
6869 {
6870         uint16_t i, j;
6871         int ret = -EINVAL;
6872
6873         static const struct {
6874                 enum rte_eth_input_set_field field;
6875                 uint64_t inset;
6876         } inset_convert_table[] = {
6877                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6878                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6879                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6880                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6881                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6882                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6883                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6884                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6885                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6886                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6887                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6888                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6889                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6890                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6891                         I40E_INSET_IPV6_NEXT_HDR},
6892                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6893                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6894                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6895                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6896                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6897                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6898                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6899                         I40E_INSET_SCTP_VT},
6900                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6901                         I40E_INSET_TUNNEL_DMAC},
6902                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6903                         I40E_INSET_VLAN_TUNNEL},
6904                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6905                         I40E_INSET_TUNNEL_ID},
6906                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6907                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6908                         I40E_INSET_FLEX_PAYLOAD_W1},
6909                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6910                         I40E_INSET_FLEX_PAYLOAD_W2},
6911                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6912                         I40E_INSET_FLEX_PAYLOAD_W3},
6913                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6914                         I40E_INSET_FLEX_PAYLOAD_W4},
6915                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6916                         I40E_INSET_FLEX_PAYLOAD_W5},
6917                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6918                         I40E_INSET_FLEX_PAYLOAD_W6},
6919                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6920                         I40E_INSET_FLEX_PAYLOAD_W7},
6921                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6922                         I40E_INSET_FLEX_PAYLOAD_W8},
6923         };
6924
6925         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6926                 return ret;
6927
6928         /* Only one item allowed for default or all */
6929         if (size == 1) {
6930                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6931                         *inset = i40e_get_default_input_set(pctype);
6932                         return 0;
6933                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6934                         *inset = I40E_INSET_NONE;
6935                         return 0;
6936                 }
6937         }
6938
6939         for (i = 0, *inset = 0; i < size; i++) {
6940                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6941                         if (field[i] == inset_convert_table[j].field) {
6942                                 *inset |= inset_convert_table[j].inset;
6943                                 break;
6944                         }
6945                 }
6946
6947                 /* It contains unsupported input set, return immediately */
6948                 if (j == RTE_DIM(inset_convert_table))
6949                         return ret;
6950         }
6951
6952         return 0;
6953 }
6954
6955 /**
6956  * Translate the input set from bit masks to register aware bit masks
6957  * and vice versa
6958  */
6959 static uint64_t
6960 i40e_translate_input_set_reg(uint64_t input)
6961 {
6962         uint64_t val = 0;
6963         uint16_t i;
6964
6965         static const struct {
6966                 uint64_t inset;
6967                 uint64_t inset_reg;
6968         } inset_map[] = {
6969                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6970                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6971                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6972                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6973                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6974                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6975                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6976                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6977                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6978                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6979                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6980                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6981                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6982                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6983                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6984                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6985                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6986                 {I40E_INSET_TUNNEL_DMAC,
6987                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6988                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6989                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6990                 {I40E_INSET_TUNNEL_SRC_PORT,
6991                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6992                 {I40E_INSET_TUNNEL_DST_PORT,
6993                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6994                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6995                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6996                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6997                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6998                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6999                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7000                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7001                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7002                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7003         };
7004
7005         if (input == 0)
7006                 return val;
7007
7008         /* Translate input set to register aware inset */
7009         for (i = 0; i < RTE_DIM(inset_map); i++) {
7010                 if (input & inset_map[i].inset)
7011                         val |= inset_map[i].inset_reg;
7012         }
7013
7014         return val;
7015 }
7016
7017 static int
7018 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7019 {
7020         uint8_t i, idx = 0;
7021
7022         static const struct {
7023                 uint64_t inset;
7024                 uint32_t mask;
7025         } inset_mask_map[] = {
7026                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7027                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7028                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7029                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7030         };
7031
7032         if (!inset || !mask || !nb_elem)
7033                 return 0;
7034
7035
7036         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7037                 if ((inset & inset_mask_map[i].inset) == inset_mask_map[i].inset) {
7038                         if (idx >= nb_elem) {
7039                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7040                                 return -EINVAL;
7041                         }
7042                         mask[idx] = inset_mask_map[i].mask;
7043                         idx++;
7044                 }
7045         }
7046
7047         return idx;
7048 }
7049
7050 static void
7051 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7052 {
7053         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7054
7055         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7056         if (reg != val)
7057                 i40e_write_rx_ctl(hw, addr, val);
7058         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7059                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7060 }
7061
7062 static void
7063 i40e_filter_input_set_init(struct i40e_pf *pf)
7064 {
7065         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7066         enum i40e_filter_pctype pctype;
7067         uint64_t input_set, inset_reg;
7068         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7069         int num, i;
7070
7071         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7072              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7073                 if (!I40E_VALID_PCTYPE(pctype))
7074                         continue;
7075                 input_set = i40e_get_default_input_set(pctype);
7076
7077                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7078                                                    I40E_INSET_MASK_NUM_REG);
7079                 if (num < 0)
7080                         return;
7081                 inset_reg = i40e_translate_input_set_reg(input_set);
7082
7083                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7084                                       (uint32_t)(inset_reg & UINT32_MAX));
7085                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7086                                      (uint32_t)((inset_reg >>
7087                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7088                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7089                                       (uint32_t)(inset_reg & UINT32_MAX));
7090                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7091                                      (uint32_t)((inset_reg >>
7092                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7093
7094                 for (i = 0; i < num; i++) {
7095                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7096                                              mask_reg[i]);
7097                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7098                                              mask_reg[i]);
7099                 }
7100                 /*clear unused mask registers of the pctype */
7101                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7102                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7103                                              0);
7104                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7105                                              0);
7106                 }
7107                 I40E_WRITE_FLUSH(hw);
7108
7109                 /* store the default input set */
7110                 pf->hash_input_set[pctype] = input_set;
7111                 pf->fdir.input_set[pctype] = input_set;
7112         }
7113 }
7114
7115 int
7116 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7117                          struct rte_eth_input_set_conf *conf)
7118 {
7119         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7120         enum i40e_filter_pctype pctype;
7121         uint64_t input_set, inset_reg = 0;
7122         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7123         int ret, i, num;
7124
7125         if (!conf) {
7126                 PMD_DRV_LOG(ERR, "Invalid pointer");
7127                 return -EFAULT;
7128         }
7129         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7130             conf->op != RTE_ETH_INPUT_SET_ADD) {
7131                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7132                 return -EINVAL;
7133         }
7134
7135         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7136         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7137                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7138                             conf->flow_type);
7139                 return -EINVAL;
7140         }
7141
7142         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7143                                    conf->inset_size);
7144         if (ret) {
7145                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7146                 return -EINVAL;
7147         }
7148         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7149                                     input_set) != 0) {
7150                 PMD_DRV_LOG(ERR, "Invalid input set");
7151                 return -EINVAL;
7152         }
7153         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7154                 /* get inset value in register */
7155                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7156                 inset_reg <<= I40E_32_BIT_WIDTH;
7157                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7158                 input_set |= pf->hash_input_set[pctype];
7159         }
7160         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7161                                            I40E_INSET_MASK_NUM_REG);
7162         if (num < 0)
7163                 return -EINVAL;
7164
7165         inset_reg |= i40e_translate_input_set_reg(input_set);
7166
7167         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7168                               (uint32_t)(inset_reg & UINT32_MAX));
7169         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7170                              (uint32_t)((inset_reg >>
7171                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7172
7173         for (i = 0; i < num; i++)
7174                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7175                                      mask_reg[i]);
7176         /*clear unused mask registers of the pctype */
7177         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7178                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7179                                      0);
7180         I40E_WRITE_FLUSH(hw);
7181
7182         pf->hash_input_set[pctype] = input_set;
7183         return 0;
7184 }
7185
7186 int
7187 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7188                          struct rte_eth_input_set_conf *conf)
7189 {
7190         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7191         enum i40e_filter_pctype pctype;
7192         uint64_t input_set, inset_reg = 0;
7193         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7194         int ret, i, num;
7195
7196         if (!hw || !conf) {
7197                 PMD_DRV_LOG(ERR, "Invalid pointer");
7198                 return -EFAULT;
7199         }
7200         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7201             conf->op != RTE_ETH_INPUT_SET_ADD) {
7202                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7203                 return -EINVAL;
7204         }
7205
7206         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7207         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7208                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7209                             conf->flow_type);
7210                 return -EINVAL;
7211         }
7212         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7213                                    conf->inset_size);
7214         if (ret) {
7215                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7216                 return -EINVAL;
7217         }
7218         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7219                                     input_set) != 0) {
7220                 PMD_DRV_LOG(ERR, "Invalid input set");
7221                 return -EINVAL;
7222         }
7223
7224         /* get inset value in register */
7225         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7226         inset_reg <<= I40E_32_BIT_WIDTH;
7227         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7228
7229         /* Can not change the inset reg for flex payload for fdir,
7230          * it is done by writing I40E_PRTQF_FD_FLXINSET
7231          * in i40e_set_flex_mask_on_pctype.
7232          */
7233         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7234                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7235         else
7236                 input_set |= pf->fdir.input_set[pctype];
7237         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7238                                            I40E_INSET_MASK_NUM_REG);
7239         if (num < 0)
7240                 return -EINVAL;
7241
7242         inset_reg |= i40e_translate_input_set_reg(input_set);
7243
7244         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7245                               (uint32_t)(inset_reg & UINT32_MAX));
7246         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7247                              (uint32_t)((inset_reg >>
7248                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7249
7250         for (i = 0; i < num; i++)
7251                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7252                                      mask_reg[i]);
7253         /*clear unused mask registers of the pctype */
7254         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7255                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7256                                      0);
7257         I40E_WRITE_FLUSH(hw);
7258
7259         pf->fdir.input_set[pctype] = input_set;
7260         return 0;
7261 }
7262
7263 static int
7264 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7265 {
7266         int ret = 0;
7267
7268         if (!hw || !info) {
7269                 PMD_DRV_LOG(ERR, "Invalid pointer");
7270                 return -EFAULT;
7271         }
7272
7273         switch (info->info_type) {
7274         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7275                 i40e_get_symmetric_hash_enable_per_port(hw,
7276                                         &(info->info.enable));
7277                 break;
7278         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7279                 ret = i40e_get_hash_filter_global_config(hw,
7280                                 &(info->info.global_conf));
7281                 break;
7282         default:
7283                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7284                                                         info->info_type);
7285                 ret = -EINVAL;
7286                 break;
7287         }
7288
7289         return ret;
7290 }
7291
7292 static int
7293 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7294 {
7295         int ret = 0;
7296
7297         if (!hw || !info) {
7298                 PMD_DRV_LOG(ERR, "Invalid pointer");
7299                 return -EFAULT;
7300         }
7301
7302         switch (info->info_type) {
7303         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7304                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7305                 break;
7306         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7307                 ret = i40e_set_hash_filter_global_config(hw,
7308                                 &(info->info.global_conf));
7309                 break;
7310         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7311                 ret = i40e_hash_filter_inset_select(hw,
7312                                                &(info->info.input_set_conf));
7313                 break;
7314
7315         default:
7316                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7317                                                         info->info_type);
7318                 ret = -EINVAL;
7319                 break;
7320         }
7321
7322         return ret;
7323 }
7324
7325 /* Operations for hash function */
7326 static int
7327 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7328                       enum rte_filter_op filter_op,
7329                       void *arg)
7330 {
7331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7332         int ret = 0;
7333
7334         switch (filter_op) {
7335         case RTE_ETH_FILTER_NOP:
7336                 break;
7337         case RTE_ETH_FILTER_GET:
7338                 ret = i40e_hash_filter_get(hw,
7339                         (struct rte_eth_hash_filter_info *)arg);
7340                 break;
7341         case RTE_ETH_FILTER_SET:
7342                 ret = i40e_hash_filter_set(hw,
7343                         (struct rte_eth_hash_filter_info *)arg);
7344                 break;
7345         default:
7346                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7347                                                                 filter_op);
7348                 ret = -ENOTSUP;
7349                 break;
7350         }
7351
7352         return ret;
7353 }
7354
7355 /*
7356  * Configure ethertype filter, which can director packet by filtering
7357  * with mac address and ether_type or only ether_type
7358  */
7359 static int
7360 i40e_ethertype_filter_set(struct i40e_pf *pf,
7361                         struct rte_eth_ethertype_filter *filter,
7362                         bool add)
7363 {
7364         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7365         struct i40e_control_filter_stats stats;
7366         uint16_t flags = 0;
7367         int ret;
7368
7369         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7370                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7371                 return -EINVAL;
7372         }
7373         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7374                 filter->ether_type == ETHER_TYPE_IPv6) {
7375                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7376                         " control packet filter.", filter->ether_type);
7377                 return -EINVAL;
7378         }
7379         if (filter->ether_type == ETHER_TYPE_VLAN)
7380                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7381                         " not supported.");
7382
7383         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7384                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7385         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7386                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7387         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7388
7389         memset(&stats, 0, sizeof(stats));
7390         ret = i40e_aq_add_rem_control_packet_filter(hw,
7391                         filter->mac_addr.addr_bytes,
7392                         filter->ether_type, flags,
7393                         pf->main_vsi->seid,
7394                         filter->queue, add, &stats, NULL);
7395
7396         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7397                          " mac_etype_used = %u, etype_used = %u,"
7398                          " mac_etype_free = %u, etype_free = %u\n",
7399                          ret, stats.mac_etype_used, stats.etype_used,
7400                          stats.mac_etype_free, stats.etype_free);
7401         if (ret < 0)
7402                 return -ENOSYS;
7403         return 0;
7404 }
7405
7406 /*
7407  * Handle operations for ethertype filter.
7408  */
7409 static int
7410 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7411                                 enum rte_filter_op filter_op,
7412                                 void *arg)
7413 {
7414         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7415         int ret = 0;
7416
7417         if (filter_op == RTE_ETH_FILTER_NOP)
7418                 return ret;
7419
7420         if (arg == NULL) {
7421                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7422                             filter_op);
7423                 return -EINVAL;
7424         }
7425
7426         switch (filter_op) {
7427         case RTE_ETH_FILTER_ADD:
7428                 ret = i40e_ethertype_filter_set(pf,
7429                         (struct rte_eth_ethertype_filter *)arg,
7430                         TRUE);
7431                 break;
7432         case RTE_ETH_FILTER_DELETE:
7433                 ret = i40e_ethertype_filter_set(pf,
7434                         (struct rte_eth_ethertype_filter *)arg,
7435                         FALSE);
7436                 break;
7437         default:
7438                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7439                 ret = -ENOSYS;
7440                 break;
7441         }
7442         return ret;
7443 }
7444
7445 static int
7446 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7447                      enum rte_filter_type filter_type,
7448                      enum rte_filter_op filter_op,
7449                      void *arg)
7450 {
7451         int ret = 0;
7452
7453         if (dev == NULL)
7454                 return -EINVAL;
7455
7456         switch (filter_type) {
7457         case RTE_ETH_FILTER_NONE:
7458                 /* For global configuration */
7459                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7460                 break;
7461         case RTE_ETH_FILTER_HASH:
7462                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7463                 break;
7464         case RTE_ETH_FILTER_MACVLAN:
7465                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7466                 break;
7467         case RTE_ETH_FILTER_ETHERTYPE:
7468                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7469                 break;
7470         case RTE_ETH_FILTER_TUNNEL:
7471                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7472                 break;
7473         case RTE_ETH_FILTER_FDIR:
7474                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7475                 break;
7476         default:
7477                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7478                                                         filter_type);
7479                 ret = -EINVAL;
7480                 break;
7481         }
7482
7483         return ret;
7484 }
7485
7486 /*
7487  * Check and enable Extended Tag.
7488  * Enabling Extended Tag is important for 40G performance.
7489  */
7490 static void
7491 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7492 {
7493         uint32_t buf = 0;
7494         int ret;
7495
7496         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7497                                       PCI_DEV_CAP_REG);
7498         if (ret < 0) {
7499                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7500                             PCI_DEV_CAP_REG);
7501                 return;
7502         }
7503         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7504                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7505                 return;
7506         }
7507
7508         buf = 0;
7509         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7510                                       PCI_DEV_CTRL_REG);
7511         if (ret < 0) {
7512                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7513                             PCI_DEV_CTRL_REG);
7514                 return;
7515         }
7516         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7517                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7518                 return;
7519         }
7520         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7521         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7522                                        PCI_DEV_CTRL_REG);
7523         if (ret < 0) {
7524                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7525                             PCI_DEV_CTRL_REG);
7526                 return;
7527         }
7528 }
7529
7530 /*
7531  * As some registers wouldn't be reset unless a global hardware reset,
7532  * hardware initialization is needed to put those registers into an
7533  * expected initial state.
7534  */
7535 static void
7536 i40e_hw_init(struct rte_eth_dev *dev)
7537 {
7538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7539
7540         i40e_enable_extended_tag(dev);
7541
7542         /* clear the PF Queue Filter control register */
7543         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7544
7545         /* Disable symmetric hash per port */
7546         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7547 }
7548
7549 enum i40e_filter_pctype
7550 i40e_flowtype_to_pctype(uint16_t flow_type)
7551 {
7552         static const enum i40e_filter_pctype pctype_table[] = {
7553                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7554                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7555                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7556                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7557                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7558                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7559                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7560                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7561                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7562                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7563                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7564                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7565                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7566                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7567                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7568                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7569                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7570                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7571                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7572         };
7573
7574         return pctype_table[flow_type];
7575 }
7576
7577 uint16_t
7578 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7579 {
7580         static const uint16_t flowtype_table[] = {
7581                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7582                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7583                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7584                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7585                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7586                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7587                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7588                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7589                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7590                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7591                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7592                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7593                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7594                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7595                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7596                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7597                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7598                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7599                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7600         };
7601
7602         return flowtype_table[pctype];
7603 }
7604
7605 /*
7606  * On X710, performance number is far from the expectation on recent firmware
7607  * versions; on XL710, performance number is also far from the expectation on
7608  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7609  * mode is enabled and port MAC address is equal to the packet destination MAC
7610  * address. The fix for this issue may not be integrated in the following
7611  * firmware version. So the workaround in software driver is needed. It needs
7612  * to modify the initial values of 3 internal only registers for both X710 and
7613  * XL710. Note that the values for X710 or XL710 could be different, and the
7614  * workaround can be removed when it is fixed in firmware in the future.
7615  */
7616
7617 /* For both X710 and XL710 */
7618 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7619 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7620
7621 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7622 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7623
7624 /* For X710 */
7625 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7626 /* For XL710 */
7627 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7628 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7629
7630 static void
7631 i40e_configure_registers(struct i40e_hw *hw)
7632 {
7633         static struct {
7634                 uint32_t addr;
7635                 uint64_t val;
7636         } reg_table[] = {
7637                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7638                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7639                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7640         };
7641         uint64_t reg;
7642         uint32_t i;
7643         int ret;
7644
7645         for (i = 0; i < RTE_DIM(reg_table); i++) {
7646                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7647                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7648                                 reg_table[i].val =
7649                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7650                         else /* For X710 */
7651                                 reg_table[i].val =
7652                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7653                 }
7654
7655                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7656                                                         &reg, NULL);
7657                 if (ret < 0) {
7658                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7659                                                         reg_table[i].addr);
7660                         break;
7661                 }
7662                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7663                                                 reg_table[i].addr, reg);
7664                 if (reg == reg_table[i].val)
7665                         continue;
7666
7667                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7668                                                 reg_table[i].val, NULL);
7669                 if (ret < 0) {
7670                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7671                                 "address of 0x%"PRIx32, reg_table[i].val,
7672                                                         reg_table[i].addr);
7673                         break;
7674                 }
7675                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7676                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7677         }
7678 }
7679
7680 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7681 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7682 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7683 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7684 static int
7685 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7686 {
7687         uint32_t reg;
7688         int ret;
7689
7690         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7691                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7692                 return -EINVAL;
7693         }
7694
7695         /* Configure for double VLAN RX stripping */
7696         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7697         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7698                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7699                 ret = i40e_aq_debug_write_register(hw,
7700                                                    I40E_VSI_TSR(vsi->vsi_id),
7701                                                    reg, NULL);
7702                 if (ret < 0) {
7703                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7704                                     vsi->vsi_id);
7705                         return I40E_ERR_CONFIG;
7706                 }
7707         }
7708
7709         /* Configure for double VLAN TX insertion */
7710         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7711         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7712                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7713                 ret = i40e_aq_debug_write_register(hw,
7714                                                    I40E_VSI_L2TAGSTXVALID(
7715                                                    vsi->vsi_id), reg, NULL);
7716                 if (ret < 0) {
7717                         PMD_DRV_LOG(ERR, "Failed to update "
7718                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7719                         return I40E_ERR_CONFIG;
7720                 }
7721         }
7722
7723         return 0;
7724 }
7725
7726 /**
7727  * i40e_aq_add_mirror_rule
7728  * @hw: pointer to the hardware structure
7729  * @seid: VEB seid to add mirror rule to
7730  * @dst_id: destination vsi seid
7731  * @entries: Buffer which contains the entities to be mirrored
7732  * @count: number of entities contained in the buffer
7733  * @rule_id:the rule_id of the rule to be added
7734  *
7735  * Add a mirror rule for a given veb.
7736  *
7737  **/
7738 static enum i40e_status_code
7739 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7740                         uint16_t seid, uint16_t dst_id,
7741                         uint16_t rule_type, uint16_t *entries,
7742                         uint16_t count, uint16_t *rule_id)
7743 {
7744         struct i40e_aq_desc desc;
7745         struct i40e_aqc_add_delete_mirror_rule cmd;
7746         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7747                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7748                 &desc.params.raw;
7749         uint16_t buff_len;
7750         enum i40e_status_code status;
7751
7752         i40e_fill_default_direct_cmd_desc(&desc,
7753                                           i40e_aqc_opc_add_mirror_rule);
7754         memset(&cmd, 0, sizeof(cmd));
7755
7756         buff_len = sizeof(uint16_t) * count;
7757         desc.datalen = rte_cpu_to_le_16(buff_len);
7758         if (buff_len > 0)
7759                 desc.flags |= rte_cpu_to_le_16(
7760                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7761         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7762                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7763         cmd.num_entries = rte_cpu_to_le_16(count);
7764         cmd.seid = rte_cpu_to_le_16(seid);
7765         cmd.destination = rte_cpu_to_le_16(dst_id);
7766
7767         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7768         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7769         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7770                          "rule_id = %u"
7771                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7772                          hw->aq.asq_last_status, resp->rule_id,
7773                          resp->mirror_rules_used, resp->mirror_rules_free);
7774         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7775
7776         return status;
7777 }
7778
7779 /**
7780  * i40e_aq_del_mirror_rule
7781  * @hw: pointer to the hardware structure
7782  * @seid: VEB seid to add mirror rule to
7783  * @entries: Buffer which contains the entities to be mirrored
7784  * @count: number of entities contained in the buffer
7785  * @rule_id:the rule_id of the rule to be delete
7786  *
7787  * Delete a mirror rule for a given veb.
7788  *
7789  **/
7790 static enum i40e_status_code
7791 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7792                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7793                 uint16_t count, uint16_t rule_id)
7794 {
7795         struct i40e_aq_desc desc;
7796         struct i40e_aqc_add_delete_mirror_rule cmd;
7797         uint16_t buff_len = 0;
7798         enum i40e_status_code status;
7799         void *buff = NULL;
7800
7801         i40e_fill_default_direct_cmd_desc(&desc,
7802                                           i40e_aqc_opc_delete_mirror_rule);
7803         memset(&cmd, 0, sizeof(cmd));
7804         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7805                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7806                                                           I40E_AQ_FLAG_RD));
7807                 cmd.num_entries = count;
7808                 buff_len = sizeof(uint16_t) * count;
7809                 desc.datalen = rte_cpu_to_le_16(buff_len);
7810                 buff = (void *)entries;
7811         } else
7812                 /* rule id is filled in destination field for deleting mirror rule */
7813                 cmd.destination = rte_cpu_to_le_16(rule_id);
7814
7815         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7816                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7817         cmd.seid = rte_cpu_to_le_16(seid);
7818
7819         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7820         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7821
7822         return status;
7823 }
7824
7825 /**
7826  * i40e_mirror_rule_set
7827  * @dev: pointer to the hardware structure
7828  * @mirror_conf: mirror rule info
7829  * @sw_id: mirror rule's sw_id
7830  * @on: enable/disable
7831  *
7832  * set a mirror rule.
7833  *
7834  **/
7835 static int
7836 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7837                         struct rte_eth_mirror_conf *mirror_conf,
7838                         uint8_t sw_id, uint8_t on)
7839 {
7840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7842         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7843         struct i40e_mirror_rule *parent = NULL;
7844         uint16_t seid, dst_seid, rule_id;
7845         uint16_t i, j = 0;
7846         int ret;
7847
7848         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7849
7850         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7851                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7852                         " without veb or vfs.");
7853                 return -ENOSYS;
7854         }
7855         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7856                 PMD_DRV_LOG(ERR, "mirror table is full.");
7857                 return -ENOSPC;
7858         }
7859         if (mirror_conf->dst_pool > pf->vf_num) {
7860                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7861                                  mirror_conf->dst_pool);
7862                 return -EINVAL;
7863         }
7864
7865         seid = pf->main_vsi->veb->seid;
7866
7867         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7868                 if (sw_id <= it->index) {
7869                         mirr_rule = it;
7870                         break;
7871                 }
7872                 parent = it;
7873         }
7874         if (mirr_rule && sw_id == mirr_rule->index) {
7875                 if (on) {
7876                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7877                         return -EEXIST;
7878                 } else {
7879                         ret = i40e_aq_del_mirror_rule(hw, seid,
7880                                         mirr_rule->rule_type,
7881                                         mirr_rule->entries,
7882                                         mirr_rule->num_entries, mirr_rule->id);
7883                         if (ret < 0) {
7884                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7885                                                    " ret = %d, aq_err = %d.",
7886                                                    ret, hw->aq.asq_last_status);
7887                                 return -ENOSYS;
7888                         }
7889                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7890                         rte_free(mirr_rule);
7891                         pf->nb_mirror_rule--;
7892                         return 0;
7893                 }
7894         } else if (!on) {
7895                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7896                 return -ENOENT;
7897         }
7898
7899         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7900                                 sizeof(struct i40e_mirror_rule) , 0);
7901         if (!mirr_rule) {
7902                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7903                 return I40E_ERR_NO_MEMORY;
7904         }
7905         switch (mirror_conf->rule_type) {
7906         case ETH_MIRROR_VLAN:
7907                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7908                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7909                                 mirr_rule->entries[j] =
7910                                         mirror_conf->vlan.vlan_id[i];
7911                                 j++;
7912                         }
7913                 }
7914                 if (j == 0) {
7915                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7916                         rte_free(mirr_rule);
7917                         return -EINVAL;
7918                 }
7919                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7920                 break;
7921         case ETH_MIRROR_VIRTUAL_POOL_UP:
7922         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7923                 /* check if the specified pool bit is out of range */
7924                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7925                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7926                         rte_free(mirr_rule);
7927                         return -EINVAL;
7928                 }
7929                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7930                         if (mirror_conf->pool_mask & (1ULL << i)) {
7931                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7932                                 j++;
7933                         }
7934                 }
7935                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7936                         /* add pf vsi to entries */
7937                         mirr_rule->entries[j] = pf->main_vsi_seid;
7938                         j++;
7939                 }
7940                 if (j == 0) {
7941                         PMD_DRV_LOG(ERR, "pool is not specified.");
7942                         rte_free(mirr_rule);
7943                         return -EINVAL;
7944                 }
7945                 /* egress and ingress in aq commands means from switch but not port */
7946                 mirr_rule->rule_type =
7947                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7948                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7949                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7950                 break;
7951         case ETH_MIRROR_UPLINK_PORT:
7952                 /* egress and ingress in aq commands means from switch but not port*/
7953                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7954                 break;
7955         case ETH_MIRROR_DOWNLINK_PORT:
7956                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7957                 break;
7958         default:
7959                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7960                         mirror_conf->rule_type);
7961                 rte_free(mirr_rule);
7962                 return -EINVAL;
7963         }
7964
7965         /* If the dst_pool is equal to vf_num, consider it as PF */
7966         if (mirror_conf->dst_pool == pf->vf_num)
7967                 dst_seid = pf->main_vsi_seid;
7968         else
7969                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7970
7971         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7972                                       mirr_rule->rule_type, mirr_rule->entries,
7973                                       j, &rule_id);
7974         if (ret < 0) {
7975                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7976                                    " ret = %d, aq_err = %d.",
7977                                    ret, hw->aq.asq_last_status);
7978                 rte_free(mirr_rule);
7979                 return -ENOSYS;
7980         }
7981
7982         mirr_rule->index = sw_id;
7983         mirr_rule->num_entries = j;
7984         mirr_rule->id = rule_id;
7985         mirr_rule->dst_vsi_seid = dst_seid;
7986
7987         if (parent)
7988                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7989         else
7990                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7991
7992         pf->nb_mirror_rule++;
7993         return 0;
7994 }
7995
7996 /**
7997  * i40e_mirror_rule_reset
7998  * @dev: pointer to the device
7999  * @sw_id: mirror rule's sw_id
8000  *
8001  * reset a mirror rule.
8002  *
8003  **/
8004 static int
8005 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8006 {
8007         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8009         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8010         uint16_t seid;
8011         int ret;
8012
8013         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8014
8015         seid = pf->main_vsi->veb->seid;
8016
8017         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8018                 if (sw_id == it->index) {
8019                         mirr_rule = it;
8020                         break;
8021                 }
8022         }
8023         if (mirr_rule) {
8024                 ret = i40e_aq_del_mirror_rule(hw, seid,
8025                                 mirr_rule->rule_type,
8026                                 mirr_rule->entries,
8027                                 mirr_rule->num_entries, mirr_rule->id);
8028                 if (ret < 0) {
8029                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8030                                            " status = %d, aq_err = %d.",
8031                                            ret, hw->aq.asq_last_status);
8032                         return -ENOSYS;
8033                 }
8034                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8035                 rte_free(mirr_rule);
8036                 pf->nb_mirror_rule--;
8037         } else {
8038                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8039                 return -ENOENT;
8040         }
8041         return 0;
8042 }
8043
8044 static uint64_t
8045 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8046 {
8047         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8048         uint64_t systim_cycles;
8049
8050         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8051         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8052                         << 32;
8053
8054         return systim_cycles;
8055 }
8056
8057 static uint64_t
8058 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8059 {
8060         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8061         uint64_t rx_tstamp;
8062
8063         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8064         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8065                         << 32;
8066
8067         return rx_tstamp;
8068 }
8069
8070 static uint64_t
8071 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8072 {
8073         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8074         uint64_t tx_tstamp;
8075
8076         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8077         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8078                         << 32;
8079
8080         return tx_tstamp;
8081 }
8082
8083 static void
8084 i40e_start_timecounters(struct rte_eth_dev *dev)
8085 {
8086         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8087         struct i40e_adapter *adapter =
8088                         (struct i40e_adapter *)dev->data->dev_private;
8089         struct rte_eth_link link;
8090         uint32_t tsync_inc_l;
8091         uint32_t tsync_inc_h;
8092
8093         /* Get current link speed. */
8094         memset(&link, 0, sizeof(link));
8095         i40e_dev_link_update(dev, 1);
8096         rte_i40e_dev_atomic_read_link_status(dev, &link);
8097
8098         switch (link.link_speed) {
8099         case ETH_LINK_SPEED_40G:
8100                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8101                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8102                 break;
8103         case ETH_LINK_SPEED_10G:
8104                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8105                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8106                 break;
8107         case ETH_LINK_SPEED_1000:
8108                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8109                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8110                 break;
8111         default:
8112                 tsync_inc_l = 0x0;
8113                 tsync_inc_h = 0x0;
8114         }
8115
8116         /* Set the timesync increment value. */
8117         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8118         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8119
8120         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8121         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8122         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8123
8124         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8125         adapter->systime_tc.cc_shift = 0;
8126         adapter->systime_tc.nsec_mask = 0;
8127
8128         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8129         adapter->rx_tstamp_tc.cc_shift = 0;
8130         adapter->rx_tstamp_tc.nsec_mask = 0;
8131
8132         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8133         adapter->tx_tstamp_tc.cc_shift = 0;
8134         adapter->tx_tstamp_tc.nsec_mask = 0;
8135 }
8136
8137 static int
8138 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8139 {
8140         struct i40e_adapter *adapter =
8141                         (struct i40e_adapter *)dev->data->dev_private;
8142
8143         adapter->systime_tc.nsec += delta;
8144         adapter->rx_tstamp_tc.nsec += delta;
8145         adapter->tx_tstamp_tc.nsec += delta;
8146
8147         return 0;
8148 }
8149
8150 static int
8151 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8152 {
8153         uint64_t ns;
8154         struct i40e_adapter *adapter =
8155                         (struct i40e_adapter *)dev->data->dev_private;
8156
8157         ns = rte_timespec_to_ns(ts);
8158
8159         /* Set the timecounters to a new value. */
8160         adapter->systime_tc.nsec = ns;
8161         adapter->rx_tstamp_tc.nsec = ns;
8162         adapter->tx_tstamp_tc.nsec = ns;
8163
8164         return 0;
8165 }
8166
8167 static int
8168 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8169 {
8170         uint64_t ns, systime_cycles;
8171         struct i40e_adapter *adapter =
8172                         (struct i40e_adapter *)dev->data->dev_private;
8173
8174         systime_cycles = i40e_read_systime_cyclecounter(dev);
8175         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8176         *ts = rte_ns_to_timespec(ns);
8177
8178         return 0;
8179 }
8180
8181 static int
8182 i40e_timesync_enable(struct rte_eth_dev *dev)
8183 {
8184         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8185         uint32_t tsync_ctl_l;
8186         uint32_t tsync_ctl_h;
8187
8188         /* Stop the timesync system time. */
8189         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8190         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8191         /* Reset the timesync system time value. */
8192         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8193         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8194
8195         i40e_start_timecounters(dev);
8196
8197         /* Clear timesync registers. */
8198         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8199         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8200         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8201         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8202         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8203         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8204
8205         /* Enable timestamping of PTP packets. */
8206         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8207         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8208
8209         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8210         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8211         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8212
8213         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8214         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8215
8216         return 0;
8217 }
8218
8219 static int
8220 i40e_timesync_disable(struct rte_eth_dev *dev)
8221 {
8222         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8223         uint32_t tsync_ctl_l;
8224         uint32_t tsync_ctl_h;
8225
8226         /* Disable timestamping of transmitted PTP packets. */
8227         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8228         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8229
8230         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8231         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8232
8233         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8234         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8235
8236         /* Reset the timesync increment value. */
8237         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8238         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8239
8240         return 0;
8241 }
8242
8243 static int
8244 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8245                                 struct timespec *timestamp, uint32_t flags)
8246 {
8247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8248         struct i40e_adapter *adapter =
8249                 (struct i40e_adapter *)dev->data->dev_private;
8250
8251         uint32_t sync_status;
8252         uint32_t index = flags & 0x03;
8253         uint64_t rx_tstamp_cycles;
8254         uint64_t ns;
8255
8256         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8257         if ((sync_status & (1 << index)) == 0)
8258                 return -EINVAL;
8259
8260         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8261         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8262         *timestamp = rte_ns_to_timespec(ns);
8263
8264         return 0;
8265 }
8266
8267 static int
8268 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8269                                 struct timespec *timestamp)
8270 {
8271         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8272         struct i40e_adapter *adapter =
8273                 (struct i40e_adapter *)dev->data->dev_private;
8274
8275         uint32_t sync_status;
8276         uint64_t tx_tstamp_cycles;
8277         uint64_t ns;
8278
8279         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8280         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8281                 return -EINVAL;
8282
8283         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8284         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8285         *timestamp = rte_ns_to_timespec(ns);
8286
8287         return 0;
8288 }
8289
8290 /*
8291  * i40e_parse_dcb_configure - parse dcb configure from user
8292  * @dev: the device being configured
8293  * @dcb_cfg: pointer of the result of parse
8294  * @*tc_map: bit map of enabled traffic classes
8295  *
8296  * Returns 0 on success, negative value on failure
8297  */
8298 static int
8299 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8300                          struct i40e_dcbx_config *dcb_cfg,
8301                          uint8_t *tc_map)
8302 {
8303         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8304         uint8_t i, tc_bw, bw_lf;
8305
8306         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8307
8308         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8309         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8310                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8311                 return -EINVAL;
8312         }
8313
8314         /* assume each tc has the same bw */
8315         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8316         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8317                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8318         /* to ensure the sum of tcbw is equal to 100 */
8319         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8320         for (i = 0; i < bw_lf; i++)
8321                 dcb_cfg->etscfg.tcbwtable[i]++;
8322
8323         /* assume each tc has the same Transmission Selection Algorithm */
8324         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8325                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8326
8327         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8328                 dcb_cfg->etscfg.prioritytable[i] =
8329                                 dcb_rx_conf->dcb_tc[i];
8330
8331         /* FW needs one App to configure HW */
8332         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8333         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8334         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8335         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8336
8337         if (dcb_rx_conf->nb_tcs == 0)
8338                 *tc_map = 1; /* tc0 only */
8339         else
8340                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8341
8342         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8343                 dcb_cfg->pfc.willing = 0;
8344                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8345                 dcb_cfg->pfc.pfcenable = *tc_map;
8346         }
8347         return 0;
8348 }
8349
8350
8351 static enum i40e_status_code
8352 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8353                               struct i40e_aqc_vsi_properties_data *info,
8354                               uint8_t enabled_tcmap)
8355 {
8356         enum i40e_status_code ret;
8357         int i, total_tc = 0;
8358         uint16_t qpnum_per_tc, bsf, qp_idx;
8359         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8360         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8361         uint16_t used_queues;
8362
8363         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8364         if (ret != I40E_SUCCESS)
8365                 return ret;
8366
8367         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8368                 if (enabled_tcmap & (1 << i))
8369                         total_tc++;
8370         }
8371         if (total_tc == 0)
8372                 total_tc = 1;
8373         vsi->enabled_tc = enabled_tcmap;
8374
8375         /* different VSI has different queues assigned */
8376         if (vsi->type == I40E_VSI_MAIN)
8377                 used_queues = dev_data->nb_rx_queues -
8378                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8379         else if (vsi->type == I40E_VSI_VMDQ2)
8380                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8381         else {
8382                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8383                 return I40E_ERR_NO_AVAILABLE_VSI;
8384         }
8385
8386         qpnum_per_tc = used_queues / total_tc;
8387         /* Number of queues per enabled TC */
8388         if (qpnum_per_tc == 0) {
8389                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8390                 return I40E_ERR_INVALID_QP_ID;
8391         }
8392         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8393                                 I40E_MAX_Q_PER_TC);
8394         bsf = rte_bsf32(qpnum_per_tc);
8395
8396         /**
8397          * Configure TC and queue mapping parameters, for enabled TC,
8398          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8399          * default queue will serve it.
8400          */
8401         qp_idx = 0;
8402         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8403                 if (vsi->enabled_tc & (1 << i)) {
8404                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8405                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8406                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8407                         qp_idx += qpnum_per_tc;
8408                 } else
8409                         info->tc_mapping[i] = 0;
8410         }
8411
8412         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8413         if (vsi->type == I40E_VSI_SRIOV) {
8414                 info->mapping_flags |=
8415                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8416                 for (i = 0; i < vsi->nb_qps; i++)
8417                         info->queue_mapping[i] =
8418                                 rte_cpu_to_le_16(vsi->base_queue + i);
8419         } else {
8420                 info->mapping_flags |=
8421                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8422                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8423         }
8424         info->valid_sections |=
8425                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8426
8427         return I40E_SUCCESS;
8428 }
8429
8430 /*
8431  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8432  * @veb: VEB to be configured
8433  * @tc_map: enabled TC bitmap
8434  *
8435  * Returns 0 on success, negative value on failure
8436  */
8437 static enum i40e_status_code
8438 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8439 {
8440         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8441         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8442         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8443         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8444         enum i40e_status_code ret = I40E_SUCCESS;
8445         int i;
8446         uint32_t bw_max;
8447
8448         /* Check if enabled_tc is same as existing or new TCs */
8449         if (veb->enabled_tc == tc_map)
8450                 return ret;
8451
8452         /* configure tc bandwidth */
8453         memset(&veb_bw, 0, sizeof(veb_bw));
8454         veb_bw.tc_valid_bits = tc_map;
8455         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8456         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8457                 if (tc_map & BIT_ULL(i))
8458                         veb_bw.tc_bw_share_credits[i] = 1;
8459         }
8460         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8461                                                    &veb_bw, NULL);
8462         if (ret) {
8463                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8464                                   " per TC failed = %d",
8465                                   hw->aq.asq_last_status);
8466                 return ret;
8467         }
8468
8469         memset(&ets_query, 0, sizeof(ets_query));
8470         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8471                                                    &ets_query, NULL);
8472         if (ret != I40E_SUCCESS) {
8473                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8474                                  " configuration %u", hw->aq.asq_last_status);
8475                 return ret;
8476         }
8477         memset(&bw_query, 0, sizeof(bw_query));
8478         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8479                                                   &bw_query, NULL);
8480         if (ret != I40E_SUCCESS) {
8481                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8482                                  " configuration %u", hw->aq.asq_last_status);
8483                 return ret;
8484         }
8485
8486         /* store and print out BW info */
8487         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8488         veb->bw_info.bw_max = ets_query.tc_bw_max;
8489         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8490         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8491         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8492                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8493                      I40E_16_BIT_WIDTH);
8494         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8495                 veb->bw_info.bw_ets_share_credits[i] =
8496                                 bw_query.tc_bw_share_credits[i];
8497                 veb->bw_info.bw_ets_credits[i] =
8498                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8499                 /* 4 bits per TC, 4th bit is reserved */
8500                 veb->bw_info.bw_ets_max[i] =
8501                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8502                                   RTE_LEN2MASK(3, uint8_t));
8503                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8504                             veb->bw_info.bw_ets_share_credits[i]);
8505                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8506                             veb->bw_info.bw_ets_credits[i]);
8507                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8508                             veb->bw_info.bw_ets_max[i]);
8509         }
8510
8511         veb->enabled_tc = tc_map;
8512
8513         return ret;
8514 }
8515
8516
8517 /*
8518  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8519  * @vsi: VSI to be configured
8520  * @tc_map: enabled TC bitmap
8521  *
8522  * Returns 0 on success, negative value on failure
8523  */
8524 static enum i40e_status_code
8525 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8526 {
8527         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8528         struct i40e_vsi_context ctxt;
8529         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8530         enum i40e_status_code ret = I40E_SUCCESS;
8531         int i;
8532
8533         /* Check if enabled_tc is same as existing or new TCs */
8534         if (vsi->enabled_tc == tc_map)
8535                 return ret;
8536
8537         /* configure tc bandwidth */
8538         memset(&bw_data, 0, sizeof(bw_data));
8539         bw_data.tc_valid_bits = tc_map;
8540         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8541         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8542                 if (tc_map & BIT_ULL(i))
8543                         bw_data.tc_bw_credits[i] = 1;
8544         }
8545         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8546         if (ret) {
8547                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8548                         " per TC failed = %d",
8549                         hw->aq.asq_last_status);
8550                 goto out;
8551         }
8552         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8553                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8554
8555         /* Update Queue Pairs Mapping for currently enabled UPs */
8556         ctxt.seid = vsi->seid;
8557         ctxt.pf_num = hw->pf_id;
8558         ctxt.vf_num = 0;
8559         ctxt.uplink_seid = vsi->uplink_seid;
8560         ctxt.info = vsi->info;
8561         i40e_get_cap(hw);
8562         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8563         if (ret)
8564                 goto out;
8565
8566         /* Update the VSI after updating the VSI queue-mapping information */
8567         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8568         if (ret) {
8569                 PMD_INIT_LOG(ERR, "Failed to configure "
8570                             "TC queue mapping = %d",
8571                             hw->aq.asq_last_status);
8572                 goto out;
8573         }
8574         /* update the local VSI info with updated queue map */
8575         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8576                                         sizeof(vsi->info.tc_mapping));
8577         (void)rte_memcpy(&vsi->info.queue_mapping,
8578                         &ctxt.info.queue_mapping,
8579                 sizeof(vsi->info.queue_mapping));
8580         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8581         vsi->info.valid_sections = 0;
8582
8583         /* query and update current VSI BW information */
8584         ret = i40e_vsi_get_bw_config(vsi);
8585         if (ret) {
8586                 PMD_INIT_LOG(ERR,
8587                          "Failed updating vsi bw info, err %s aq_err %s",
8588                          i40e_stat_str(hw, ret),
8589                          i40e_aq_str(hw, hw->aq.asq_last_status));
8590                 goto out;
8591         }
8592
8593         vsi->enabled_tc = tc_map;
8594
8595 out:
8596         return ret;
8597 }
8598
8599 /*
8600  * i40e_dcb_hw_configure - program the dcb setting to hw
8601  * @pf: pf the configuration is taken on
8602  * @new_cfg: new configuration
8603  * @tc_map: enabled TC bitmap
8604  *
8605  * Returns 0 on success, negative value on failure
8606  */
8607 static enum i40e_status_code
8608 i40e_dcb_hw_configure(struct i40e_pf *pf,
8609                       struct i40e_dcbx_config *new_cfg,
8610                       uint8_t tc_map)
8611 {
8612         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8613         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8614         struct i40e_vsi *main_vsi = pf->main_vsi;
8615         struct i40e_vsi_list *vsi_list;
8616         enum i40e_status_code ret;
8617         int i;
8618         uint32_t val;
8619
8620         /* Use the FW API if FW > v4.4*/
8621         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8622               (hw->aq.fw_maj_ver >= 5))) {
8623                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8624                                   " to configure DCB");
8625                 return I40E_ERR_FIRMWARE_API_VERSION;
8626         }
8627
8628         /* Check if need reconfiguration */
8629         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8630                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8631                 return I40E_SUCCESS;
8632         }
8633
8634         /* Copy the new config to the current config */
8635         *old_cfg = *new_cfg;
8636         old_cfg->etsrec = old_cfg->etscfg;
8637         ret = i40e_set_dcb_config(hw);
8638         if (ret) {
8639                 PMD_INIT_LOG(ERR,
8640                          "Set DCB Config failed, err %s aq_err %s\n",
8641                          i40e_stat_str(hw, ret),
8642                          i40e_aq_str(hw, hw->aq.asq_last_status));
8643                 return ret;
8644         }
8645         /* set receive Arbiter to RR mode and ETS scheme by default */
8646         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8647                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8648                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8649                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8650                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8651                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8652                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8653                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8654                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8655                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8656                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8657                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8658                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8659         }
8660         /* get local mib to check whether it is configured correctly */
8661         /* IEEE mode */
8662         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8663         /* Get Local DCB Config */
8664         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8665                                      &hw->local_dcbx_config);
8666
8667         /* if Veb is created, need to update TC of it at first */
8668         if (main_vsi->veb) {
8669                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8670                 if (ret)
8671                         PMD_INIT_LOG(WARNING,
8672                                  "Failed configuring TC for VEB seid=%d\n",
8673                                  main_vsi->veb->seid);
8674         }
8675         /* Update each VSI */
8676         i40e_vsi_config_tc(main_vsi, tc_map);
8677         if (main_vsi->veb) {
8678                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8679                         /* Beside main VSI and VMDQ VSIs, only enable default
8680                          * TC for other VSIs
8681                          */
8682                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8683                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8684                                                          tc_map);
8685                         else
8686                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8687                                                          I40E_DEFAULT_TCMAP);
8688                         if (ret)
8689                                 PMD_INIT_LOG(WARNING,
8690                                          "Failed configuring TC for VSI seid=%d\n",
8691                                          vsi_list->vsi->seid);
8692                         /* continue */
8693                 }
8694         }
8695         return I40E_SUCCESS;
8696 }
8697
8698 /*
8699  * i40e_dcb_init_configure - initial dcb config
8700  * @dev: device being configured
8701  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8702  *
8703  * Returns 0 on success, negative value on failure
8704  */
8705 static int
8706 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8707 {
8708         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8709         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8710         int ret = 0;
8711
8712         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8713                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8714                 return -ENOTSUP;
8715         }
8716
8717         /* DCB initialization:
8718          * Update DCB configuration from the Firmware and configure
8719          * LLDP MIB change event.
8720          */
8721         if (sw_dcb == TRUE) {
8722                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8723                 if (ret != I40E_SUCCESS)
8724                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8725
8726                 ret = i40e_init_dcb(hw);
8727                 /* if sw_dcb, lldp agent is stopped, the return from
8728                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8729                  * adminq status.
8730                  */
8731                 if (ret != I40E_SUCCESS &&
8732                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8733                         memset(&hw->local_dcbx_config, 0,
8734                                 sizeof(struct i40e_dcbx_config));
8735                         /* set dcb default configuration */
8736                         hw->local_dcbx_config.etscfg.willing = 0;
8737                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8738                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8739                         hw->local_dcbx_config.etscfg.tsatable[0] =
8740                                                 I40E_IEEE_TSA_ETS;
8741                         hw->local_dcbx_config.etsrec =
8742                                 hw->local_dcbx_config.etscfg;
8743                         hw->local_dcbx_config.pfc.willing = 0;
8744                         hw->local_dcbx_config.pfc.pfccap =
8745                                                 I40E_MAX_TRAFFIC_CLASS;
8746                         /* FW needs one App to configure HW */
8747                         hw->local_dcbx_config.numapps = 1;
8748                         hw->local_dcbx_config.app[0].selector =
8749                                                 I40E_APP_SEL_ETHTYPE;
8750                         hw->local_dcbx_config.app[0].priority = 3;
8751                         hw->local_dcbx_config.app[0].protocolid =
8752                                                 I40E_APP_PROTOID_FCOE;
8753                         ret = i40e_set_dcb_config(hw);
8754                         if (ret) {
8755                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8756                                         " err = %d, aq_err = %d.", ret,
8757                                           hw->aq.asq_last_status);
8758                                 return -ENOSYS;
8759                         }
8760                 } else {
8761                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8762                                           " aq_err = %d.", ret,
8763                                           hw->aq.asq_last_status);
8764                         return -ENOTSUP;
8765                 }
8766         } else {
8767                 ret = i40e_aq_start_lldp(hw, NULL);
8768                 if (ret != I40E_SUCCESS)
8769                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8770
8771                 ret = i40e_init_dcb(hw);
8772                 if (!ret) {
8773                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8774                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8775                                                   " DCBX offload.");
8776                                 return -ENOTSUP;
8777                         }
8778                 } else {
8779                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8780                                           " aq_err = %d.", ret,
8781                                           hw->aq.asq_last_status);
8782                         return -ENOTSUP;
8783                 }
8784         }
8785         return 0;
8786 }
8787
8788 /*
8789  * i40e_dcb_setup - setup dcb related config
8790  * @dev: device being configured
8791  *
8792  * Returns 0 on success, negative value on failure
8793  */
8794 static int
8795 i40e_dcb_setup(struct rte_eth_dev *dev)
8796 {
8797         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8798         struct i40e_dcbx_config dcb_cfg;
8799         uint8_t tc_map = 0;
8800         int ret = 0;
8801
8802         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8803                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8804                 return -ENOTSUP;
8805         }
8806
8807         if (pf->vf_num != 0)
8808                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8809
8810         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8811         if (ret) {
8812                 PMD_INIT_LOG(ERR, "invalid dcb config");
8813                 return -EINVAL;
8814         }
8815         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8816         if (ret) {
8817                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8818                 return -ENOSYS;
8819         }
8820
8821         return 0;
8822 }
8823
8824 static int
8825 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8826                       struct rte_eth_dcb_info *dcb_info)
8827 {
8828         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8830         struct i40e_vsi *vsi = pf->main_vsi;
8831         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8832         uint16_t bsf, tc_mapping;
8833         int i, j;
8834
8835         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8836                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8837         else
8838                 dcb_info->nb_tcs = 1;
8839         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8840                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8841         for (i = 0; i < dcb_info->nb_tcs; i++)
8842                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8843
8844         j = 0;
8845         do {
8846                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8847                         if (!(vsi->enabled_tc & (1 << i)))
8848                                 continue;
8849                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8850                         /* only main vsi support multi TCs */
8851                         dcb_info->tc_queue.tc_rxq[j][i].base =
8852                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8853                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8854                         dcb_info->tc_queue.tc_txq[j][i].base =
8855                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8856                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8857                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8858                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8859                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8860                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8861                 }
8862                 vsi = pf->vmdq[j].vsi;
8863                 j++;
8864         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8865         return 0;
8866 }
8867
8868 static int
8869 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8870 {
8871         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8873         uint16_t interval =
8874                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8875         uint16_t msix_intr;
8876
8877         msix_intr = intr_handle->intr_vec[queue_id];
8878         if (msix_intr == I40E_MISC_VEC_ID)
8879                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8880                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8881                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8882                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8883                                (interval <<
8884                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8885         else
8886                 I40E_WRITE_REG(hw,
8887                                I40E_PFINT_DYN_CTLN(msix_intr -
8888                                                    I40E_RX_VEC_START),
8889                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8890                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8891                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8892                                (interval <<
8893                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8894
8895         I40E_WRITE_FLUSH(hw);
8896         rte_intr_enable(&dev->pci_dev->intr_handle);
8897
8898         return 0;
8899 }
8900
8901 static int
8902 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8903 {
8904         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8906         uint16_t msix_intr;
8907
8908         msix_intr = intr_handle->intr_vec[queue_id];
8909         if (msix_intr == I40E_MISC_VEC_ID)
8910                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8911         else
8912                 I40E_WRITE_REG(hw,
8913                                I40E_PFINT_DYN_CTLN(msix_intr -
8914                                                    I40E_RX_VEC_START),
8915                                0);
8916         I40E_WRITE_FLUSH(hw);
8917
8918         return 0;
8919 }
8920
8921 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
8922 {
8923         /* Highest base addr + 32-bit word */
8924         return I40E_GLGEN_STAT_CLEAR + 4;
8925 }
8926
8927 static int i40e_get_regs(struct rte_eth_dev *dev,
8928                          struct rte_dev_reg_info *regs)
8929 {
8930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8931         uint32_t *ptr_data = regs->data;
8932         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
8933         const struct i40e_reg_info *reg_info;
8934
8935         /* The first few registers have to be read using AQ operations */
8936         reg_idx = 0;
8937         while (i40e_regs_adminq[reg_idx].name) {
8938                 reg_info = &i40e_regs_adminq[reg_idx++];
8939                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
8940                         for (arr_idx2 = 0;
8941                                         arr_idx2 <= reg_info->count2;
8942                                         arr_idx2++) {
8943                                 reg_offset = arr_idx * reg_info->stride1 +
8944                                         arr_idx2 * reg_info->stride2;
8945                                 ptr_data[reg_offset >> 2] =
8946                                         i40e_read_rx_ctl(hw, reg_offset);
8947                         }
8948         }
8949
8950         /* The remaining registers can be read using primitives */
8951         reg_idx = 0;
8952         while (i40e_regs_others[reg_idx].name) {
8953                 reg_info = &i40e_regs_others[reg_idx++];
8954                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
8955                         for (arr_idx2 = 0;
8956                                         arr_idx2 <= reg_info->count2;
8957                                         arr_idx2++) {
8958                                 reg_offset = arr_idx * reg_info->stride1 +
8959                                         arr_idx2 * reg_info->stride2;
8960                                 ptr_data[reg_offset >> 2] =
8961                                         I40E_READ_REG(hw, reg_offset);
8962                         }
8963         }
8964
8965         return 0;
8966 }
8967
8968 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
8969 {
8970         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8971
8972         /* Convert word count to byte count */
8973         return hw->nvm.sr_size << 1;
8974 }
8975
8976 static int i40e_get_eeprom(struct rte_eth_dev *dev,
8977                            struct rte_dev_eeprom_info *eeprom)
8978 {
8979         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8980         uint16_t *data = eeprom->data;
8981         uint16_t offset, length, cnt_words;
8982         int ret_code;
8983
8984         offset = eeprom->offset >> 1;
8985         length = eeprom->length >> 1;
8986         cnt_words = length;
8987
8988         if (offset > hw->nvm.sr_size ||
8989                 offset + length > hw->nvm.sr_size) {
8990                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
8991                 return -EINVAL;
8992         }
8993
8994         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
8995
8996         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
8997         if (ret_code != I40E_SUCCESS || cnt_words != length) {
8998                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
8999                 return -EIO;
9000         }
9001
9002         return 0;
9003 }
9004
9005 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9006                                       struct ether_addr *mac_addr)
9007 {
9008         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9009
9010         if (!is_valid_assigned_ether_addr(mac_addr)) {
9011                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9012                 return;
9013         }
9014
9015         /* Flags: 0x3 updates port address */
9016         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9017 }