drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA  0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 133
 134 #define I40E_MAX_PERCENT            100
 135 #define I40E_DEFAULT_DCB_APP_NUM    1
 136 #define I40E_DEFAULT_DCB_APP_PRIO   3
 137
 138 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 139 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 140 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 141 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 143 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 144
 145 #define I40E_INSET_NONE            0x00000000000000000ULL
 146
 147 /* bit0 ~ bit 7 */
 148 #define I40E_INSET_DMAC            0x0000000000000001ULL
 149 #define I40E_INSET_SMAC            0x0000000000000002ULL
 150 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 151 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 152 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 153
 154 /* bit 8 ~ bit 15 */
 155 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 156 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 157 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 158 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 159 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 160 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 161 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 162
 163 /* bit 16 ~ bit 31 */
 164 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 165 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 166 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 167 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 168 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 169 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 170 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 171 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 172
 173 /* bit 32 ~ bit 47, tunnel fields */
 174 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 175 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 176 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 177 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 178 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 179 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 180
 181 /* bit 48 ~ bit 55 */
 182 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 183
 184 /* bit 56 ~ bit 63, Flex Payload */
 185 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD \
 194         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 195         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 196         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 197         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 198
 199 /**
 200  * Below are values for writing un-exposed registers suggested
 201  * by silicon experts
 202  */
 203 /* Destination MAC address */
 204 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 205 /* Source MAC address */
 206 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 207 /* VLAN tag in the outer L2 header */
 208 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 209 /* VLAN tag in the inner L2 header */
 210 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 211 /* Source IPv4 address */
 212 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 213 /* Destination IPv4 address */
 214 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 215 /* IPv4 Type of Service (TOS) */
 216 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 217 /* IPv4 Protocol */
 218 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 219 /* Source IPv6 address */
 220 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 221 /* Destination IPv6 address */
 222 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 223 /* IPv6 Traffic Class (TC) */
 224 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 225 /* IPv6 Next Header */
 226 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263
 264 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 265
 266 #define I40E_TRANSLATE_INSET 0
 267 #define I40E_TRANSLATE_REG   1
 268
 269 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 270 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 271 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 272 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 273
 274 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 275 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 276 static int i40e_dev_configure(struct rte_eth_dev *dev);
 277 static int i40e_dev_start(struct rte_eth_dev *dev);
 278 static void i40e_dev_stop(struct rte_eth_dev *dev);
 279 static void i40e_dev_close(struct rte_eth_dev *dev);
 280 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 281 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 282 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 284 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 285 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 286 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 287                                struct rte_eth_stats *stats);
 288 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_xstats *xstats, unsigned n);
 290 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 291 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
 292 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 293                                             uint16_t queue_id,
 294                                             uint8_t stat_idx,
 295                                             uint8_t is_rx);
 296 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 297                               struct rte_eth_dev_info *dev_info);
 298 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 299                                 uint16_t vlan_id,
 300                                 int on);
 301 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 302 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 303 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 304                                       uint16_t queue,
 305                                       int on);
 306 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 307 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 308 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 309 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 310                               struct rte_eth_fc_conf *fc_conf);
 311 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 312                               struct rte_eth_fc_conf *fc_conf);
 313 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 314                                        struct rte_eth_pfc_conf *pfc_conf);
 315 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 316                           struct ether_addr *mac_addr,
 317                           uint32_t index,
 318                           uint32_t pool);
 319 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 320 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 321                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 322                                     uint16_t reta_size);
 323 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 324                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 325                                    uint16_t reta_size);
 326
 327 static int i40e_get_cap(struct i40e_hw *hw);
 328 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 329 static int i40e_pf_setup(struct i40e_pf *pf);
 330 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 331 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 332 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 333 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 334 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 335                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 336 static void i40e_stat_update_48(struct i40e_hw *hw,
 337                                uint32_t hireg,
 338                                uint32_t loreg,
 339                                bool offset_loaded,
 340                                uint64_t *offset,
 341                                uint64_t *stat);
 342 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 343 static void i40e_dev_interrupt_handler(
 344                 __rte_unused struct rte_intr_handle *handle, void *param);
 345 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 346                                 uint32_t base, uint32_t num);
 347 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 348 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 349                         uint32_t base);
 350 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 351                         uint16_t num);
 352 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 353 static int i40e_veb_release(struct i40e_veb *veb);
 354 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 355                                                 struct i40e_vsi *vsi);
 356 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 357 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 358 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 359                                              struct i40e_macvlan_filter *mv_f,
 360                                              int num,
 361                                              struct ether_addr *addr);
 362 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 363                                              struct i40e_macvlan_filter *mv_f,
 364                                              int num,
 365                                              uint16_t vlan);
 366 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 367 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 368                                     struct rte_eth_rss_conf *rss_conf);
 369 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 370                                       struct rte_eth_rss_conf *rss_conf);
 371 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 372                                 struct rte_eth_udp_tunnel *udp_tunnel);
 373 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 374                                 struct rte_eth_udp_tunnel *udp_tunnel);
 375 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 376                         struct rte_eth_ethertype_filter *filter,
 377                         bool add);
 378 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 379                                 enum rte_filter_op filter_op,
 380                                 void *arg);
 381 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 382                                 enum rte_filter_type filter_type,
 383                                 enum rte_filter_op filter_op,
 384                                 void *arg);
 385 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 386                                   struct rte_eth_dcb_info *dcb_info);
 387 static void i40e_configure_registers(struct i40e_hw *hw);
 388 static void i40e_hw_init(struct i40e_hw *hw);
 389 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 390 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 391                         struct rte_eth_mirror_conf *mirror_conf,
 392                         uint8_t sw_id, uint8_t on);
 393 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 394
 395 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 396 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 397 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 398                                            struct timespec *timestamp,
 399                                            uint32_t flags);
 400 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 401                                            struct timespec *timestamp);
 402 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 403 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 404                                          uint16_t queue_id);
 405 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 406                                           uint16_t queue_id);
 407
 408 static const struct rte_pci_id pci_id_i40e_map[] = {
 409 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 410 #include "rte_pci_dev_ids.h"
 411 { .vendor_id = 0, /* sentinel */ },
 412 };
 413
 414 static const struct eth_dev_ops i40e_eth_dev_ops = {
 415         .dev_configure                = i40e_dev_configure,
 416         .dev_start                    = i40e_dev_start,
 417         .dev_stop                     = i40e_dev_stop,
 418         .dev_close                    = i40e_dev_close,
 419         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 420         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 421         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 422         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 423         .dev_set_link_up              = i40e_dev_set_link_up,
 424         .dev_set_link_down            = i40e_dev_set_link_down,
 425         .link_update                  = i40e_dev_link_update,
 426         .stats_get                    = i40e_dev_stats_get,
 427         .xstats_get                   = i40e_dev_xstats_get,
 428         .stats_reset                  = i40e_dev_stats_reset,
 429         .xstats_reset                 = i40e_dev_xstats_reset,
 430         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 431         .dev_infos_get                = i40e_dev_info_get,
 432         .vlan_filter_set              = i40e_vlan_filter_set,
 433         .vlan_tpid_set                = i40e_vlan_tpid_set,
 434         .vlan_offload_set             = i40e_vlan_offload_set,
 435         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 436         .vlan_pvid_set                = i40e_vlan_pvid_set,
 437         .rx_queue_start               = i40e_dev_rx_queue_start,
 438         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 439         .tx_queue_start               = i40e_dev_tx_queue_start,
 440         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 441         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 442         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 443         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 444         .rx_queue_release             = i40e_dev_rx_queue_release,
 445         .rx_queue_count               = i40e_dev_rx_queue_count,
 446         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 447         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 448         .tx_queue_release             = i40e_dev_tx_queue_release,
 449         .dev_led_on                   = i40e_dev_led_on,
 450         .dev_led_off                  = i40e_dev_led_off,
 451         .flow_ctrl_get                = i40e_flow_ctrl_get,
 452         .flow_ctrl_set                = i40e_flow_ctrl_set,
 453         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 454         .mac_addr_add                 = i40e_macaddr_add,
 455         .mac_addr_remove              = i40e_macaddr_remove,
 456         .reta_update                  = i40e_dev_rss_reta_update,
 457         .reta_query                   = i40e_dev_rss_reta_query,
 458         .rss_hash_update              = i40e_dev_rss_hash_update,
 459         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 460         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 461         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 462         .filter_ctrl                  = i40e_dev_filter_ctrl,
 463         .rxq_info_get                 = i40e_rxq_info_get,
 464         .txq_info_get                 = i40e_txq_info_get,
 465         .mirror_rule_set              = i40e_mirror_rule_set,
 466         .mirror_rule_reset            = i40e_mirror_rule_reset,
 467         .timesync_enable              = i40e_timesync_enable,
 468         .timesync_disable             = i40e_timesync_disable,
 469         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 470         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 471         .get_dcb_info                 = i40e_dev_get_dcb_info,
 472 };
 473
 474 /* store statistics names and its offset in stats structure */
 475 struct rte_i40e_xstats_name_off {
 476         char name[RTE_ETH_XSTATS_NAME_SIZE];
 477         unsigned offset;
 478 };
 479
 480 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 481         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 482         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 483         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 484         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 485         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 486                 rx_unknown_protocol)},
 487         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 488         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 489         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 490         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 491 };
 492
 493 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 494         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 495                 tx_dropped_link_down)},
 496         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 497         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 498                 illegal_bytes)},
 499         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 500         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 501                 mac_local_faults)},
 502         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 503                 mac_remote_faults)},
 504         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 505                 rx_length_errors)},
 506         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 507         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 508         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 509         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 510         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 511         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 512                 rx_size_127)},
 513         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 514                 rx_size_255)},
 515         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 516                 rx_size_511)},
 517         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 518                 rx_size_1023)},
 519         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 520                 rx_size_1522)},
 521         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 522                 rx_size_big)},
 523         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 524                 rx_undersize)},
 525         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 526                 rx_oversize)},
 527         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 528                 mac_short_packet_dropped)},
 529         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 530                 rx_fragments)},
 531         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 532         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 533         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 534                 tx_size_127)},
 535         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 536                 tx_size_255)},
 537         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 538                 tx_size_511)},
 539         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 540                 tx_size_1023)},
 541         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 542                 tx_size_1522)},
 543         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 544                 tx_size_big)},
 545         {"rx_flow_director_atr_match_packets",
 546                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 547         {"rx_flow_director_sb_match_packets",
 548                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 549         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 550                 tx_lpi_status)},
 551         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 552                 rx_lpi_status)},
 553         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 554                 tx_lpi_count)},
 555         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 556                 rx_lpi_count)},
 557 };
 558
 559 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
 560 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
 561
 562 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 563                 sizeof(rte_i40e_stats_strings[0]))
 564 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 565                 sizeof(rte_i40e_hw_port_strings[0]))
 566 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
 567                 I40E_NB_HW_PORT_Q_STATS)
 568
 569 static struct eth_driver rte_i40e_pmd = {
 570         .pci_drv = {
 571                 .name = "rte_i40e_pmd",
 572                 .id_table = pci_id_i40e_map,
 573                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 574                         RTE_PCI_DRV_DETACHABLE,
 575         },
 576         .eth_dev_init = eth_i40e_dev_init,
 577         .eth_dev_uninit = eth_i40e_dev_uninit,
 578         .dev_private_size = sizeof(struct i40e_adapter),
 579 };
 580
 581 static inline int
 582 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 583                                      struct rte_eth_link *link)
 584 {
 585         struct rte_eth_link *dst = link;
 586         struct rte_eth_link *src = &(dev->data->dev_link);
 587
 588         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 589                                         *(uint64_t *)src) == 0)
 590                 return -1;
 591
 592         return 0;
 593 }
 594
 595 static inline int
 596 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 597                                       struct rte_eth_link *link)
 598 {
 599         struct rte_eth_link *dst = &(dev->data->dev_link);
 600         struct rte_eth_link *src = link;
 601
 602         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 603                                         *(uint64_t *)src) == 0)
 604                 return -1;
 605
 606         return 0;
 607 }
 608
 609 /*
 610  * Driver initialization routine.
 611  * Invoked once at EAL init time.
 612  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 613  */
 614 static int
 615 rte_i40e_pmd_init(const char *name __rte_unused,
 616                   const char *params __rte_unused)
 617 {
 618         PMD_INIT_FUNC_TRACE();
 619         rte_eth_driver_register(&rte_i40e_pmd);
 620
 621         return 0;
 622 }
 623
 624 static struct rte_driver rte_i40e_driver = {
 625         .type = PMD_PDEV,
 626         .init = rte_i40e_pmd_init,
 627 };
 628
 629 PMD_REGISTER_DRIVER(rte_i40e_driver);
 630
 631 /*
 632  * Initialize registers for flexible payload, which should be set by NVM.
 633  * This should be removed from code once it is fixed in NVM.
 634  */
 635 #ifndef I40E_GLQF_ORT
 636 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 637 #endif
 638 #ifndef I40E_GLQF_PIT
 639 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 640 #endif
 641
 642 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 643 {
 644         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 645         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 646         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 647         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 648         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 649         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 650         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 651         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 652         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 653         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 654
 655         /* GLQF_PIT Registers */
 656         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 657         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 658 }
 659
 660 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 661
 662 /*
 663  * Add a ethertype filter to drop all flow control frames transmitted
 664  * from VSIs.
 665 */
 666 static void
 667 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 668 {
 669         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 670         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 671                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 672                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 673         int ret;
 674
 675         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 676                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 677                                 pf->main_vsi_seid, 0,
 678                                 TRUE, NULL, NULL);
 679         if (ret)
 680                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 681                                   " frames from VSIs.");
 682 }
 683
 684 static int
 685 eth_i40e_dev_init(struct rte_eth_dev *dev)
 686 {
 687         struct rte_pci_device *pci_dev;
 688         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 690         struct i40e_vsi *vsi;
 691         int ret;
 692         uint32_t len;
 693         uint8_t aq_fail = 0;
 694
 695         PMD_INIT_FUNC_TRACE();
 696
 697         dev->dev_ops = &i40e_eth_dev_ops;
 698         dev->rx_pkt_burst = i40e_recv_pkts;
 699         dev->tx_pkt_burst = i40e_xmit_pkts;
 700
 701         /* for secondary processes, we don't initialise any further as primary
 702          * has already done this work. Only check we don't need a different
 703          * RX function */
 704         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 705                 i40e_set_rx_function(dev);
 706                 i40e_set_tx_function(dev);
 707                 return 0;
 708         }
 709         pci_dev = dev->pci_dev;
 710
 711         rte_eth_copy_pci_info(dev, pci_dev);
 712
 713         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 714         pf->adapter->eth_dev = dev;
 715         pf->dev_data = dev->data;
 716
 717         hw->back = I40E_PF_TO_ADAPTER(pf);
 718         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 719         if (!hw->hw_addr) {
 720                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 721                              "as address is NULL");
 722                 return -ENODEV;
 723         }
 724
 725         hw->vendor_id = pci_dev->id.vendor_id;
 726         hw->device_id = pci_dev->id.device_id;
 727         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 728         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 729         hw->bus.device = pci_dev->addr.devid;
 730         hw->bus.func = pci_dev->addr.function;
 731         hw->adapter_stopped = 0;
 732
 733         /* Make sure all is clean before doing PF reset */
 734         i40e_clear_hw(hw);
 735
 736         /* Initialize the hardware */
 737         i40e_hw_init(hw);
 738
 739         /* Reset here to make sure all is clean for each PF */
 740         ret = i40e_pf_reset(hw);
 741         if (ret) {
 742                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 743                 return ret;
 744         }
 745
 746         /* Initialize the shared code (base driver) */
 747         ret = i40e_init_shared_code(hw);
 748         if (ret) {
 749                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 750                 return ret;
 751         }
 752
 753         /*
 754          * To work around the NVM issue,initialize registers
 755          * for flexible payload by software.
 756          * It should be removed once issues are fixed in NVM.
 757          */
 758         i40e_flex_payload_reg_init(hw);
 759
 760         /* Initialize the parameters for adminq */
 761         i40e_init_adminq_parameter(hw);
 762         ret = i40e_init_adminq(hw);
 763         if (ret != I40E_SUCCESS) {
 764                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 765                 return -EIO;
 766         }
 767         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 768                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 769                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 770                      ((hw->nvm.version >> 12) & 0xf),
 771                      ((hw->nvm.version >> 4) & 0xff),
 772                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 773
 774         /* Clear PXE mode */
 775         i40e_clear_pxe_mode(hw);
 776
 777         /*
 778          * On X710, performance number is far from the expectation on recent
 779          * firmware versions. The fix for this issue may not be integrated in
 780          * the following firmware version. So the workaround in software driver
 781          * is needed. It needs to modify the initial values of 3 internal only
 782          * registers. Note that the workaround can be removed when it is fixed
 783          * in firmware in the future.
 784          */
 785         i40e_configure_registers(hw);
 786
 787         /* Get hw capabilities */
 788         ret = i40e_get_cap(hw);
 789         if (ret != I40E_SUCCESS) {
 790                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 791                 goto err_get_capabilities;
 792         }
 793
 794         /* Initialize parameters for PF */
 795         ret = i40e_pf_parameter_init(dev);
 796         if (ret != 0) {
 797                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 798                 goto err_parameter_init;
 799         }
 800
 801         /* Initialize the queue management */
 802         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 803         if (ret < 0) {
 804                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 805                 goto err_qp_pool_init;
 806         }
 807         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 808                                 hw->func_caps.num_msix_vectors - 1);
 809         if (ret < 0) {
 810                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 811                 goto err_msix_pool_init;
 812         }
 813
 814         /* Initialize lan hmc */
 815         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 816                                 hw->func_caps.num_rx_qp, 0, 0);
 817         if (ret != I40E_SUCCESS) {
 818                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 819                 goto err_init_lan_hmc;
 820         }
 821
 822         /* Configure lan hmc */
 823         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 824         if (ret != I40E_SUCCESS) {
 825                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 826                 goto err_configure_lan_hmc;
 827         }
 828
 829         /* Get and check the mac address */
 830         i40e_get_mac_addr(hw, hw->mac.addr);
 831         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 832                 PMD_INIT_LOG(ERR, "mac address is not valid");
 833                 ret = -EIO;
 834                 goto err_get_mac_addr;
 835         }
 836         /* Copy the permanent MAC address */
 837         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 838                         (struct ether_addr *) hw->mac.perm_addr);
 839
 840         /* Disable flow control */
 841         hw->fc.requested_mode = I40E_FC_NONE;
 842         i40e_set_fc(hw, &aq_fail, TRUE);
 843
 844         /* PF setup, which includes VSI setup */
 845         ret = i40e_pf_setup(pf);
 846         if (ret) {
 847                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 848                 goto err_setup_pf_switch;
 849         }
 850
 851         vsi = pf->main_vsi;
 852
 853         /* Disable double vlan by default */
 854         i40e_vsi_config_double_vlan(vsi, FALSE);
 855
 856         if (!vsi->max_macaddrs)
 857                 len = ETHER_ADDR_LEN;
 858         else
 859                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 860
 861         /* Should be after VSI initialized */
 862         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 863         if (!dev->data->mac_addrs) {
 864                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 865                                         "for storing mac address");
 866                 goto err_mac_alloc;
 867         }
 868         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 869                                         &dev->data->mac_addrs[0]);
 870
 871         /* initialize pf host driver to setup SRIOV resource if applicable */
 872         i40e_pf_host_init(dev);
 873
 874         /* register callback func to eal lib */
 875         rte_intr_callback_register(&(pci_dev->intr_handle),
 876                 i40e_dev_interrupt_handler, (void *)dev);
 877
 878         /* configure and enable device interrupt */
 879         i40e_pf_config_irq0(hw, TRUE);
 880         i40e_pf_enable_irq0(hw);
 881
 882         /* enable uio intr after callback register */
 883         rte_intr_enable(&(pci_dev->intr_handle));
 884         /*
 885          * Add an ethertype filter to drop all flow control frames transmitted
 886          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 887          * frames to wire.
 888          */
 889         i40e_add_tx_flow_control_drop_filter(pf);
 890
 891         /* initialize mirror rule list */
 892         TAILQ_INIT(&pf->mirror_list);
 893
 894         /* Init dcb to sw mode by default */
 895         ret = i40e_dcb_init_configure(dev, TRUE);
 896         if (ret != I40E_SUCCESS) {
 897                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 898                 pf->flags &= ~I40E_FLAG_DCB;
 899         }
 900
 901         return 0;
 902
 903 err_mac_alloc:
 904         i40e_vsi_release(pf->main_vsi);
 905 err_setup_pf_switch:
 906 err_get_mac_addr:
 907 err_configure_lan_hmc:
 908         (void)i40e_shutdown_lan_hmc(hw);
 909 err_init_lan_hmc:
 910         i40e_res_pool_destroy(&pf->msix_pool);
 911 err_msix_pool_init:
 912         i40e_res_pool_destroy(&pf->qp_pool);
 913 err_qp_pool_init:
 914 err_parameter_init:
 915 err_get_capabilities:
 916         (void)i40e_shutdown_adminq(hw);
 917
 918         return ret;
 919 }
 920
 921 static int
 922 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 923 {
 924         struct rte_pci_device *pci_dev;
 925         struct i40e_hw *hw;
 926         struct i40e_filter_control_settings settings;
 927         int ret;
 928         uint8_t aq_fail = 0;
 929
 930         PMD_INIT_FUNC_TRACE();
 931
 932         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 933                 return 0;
 934
 935         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         pci_dev = dev->pci_dev;
 937
 938         if (hw->adapter_stopped == 0)
 939                 i40e_dev_close(dev);
 940
 941         dev->dev_ops = NULL;
 942         dev->rx_pkt_burst = NULL;
 943         dev->tx_pkt_burst = NULL;
 944
 945         /* Disable LLDP */
 946         ret = i40e_aq_stop_lldp(hw, true, NULL);
 947         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 948                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 949
 950         /* Clear PXE mode */
 951         i40e_clear_pxe_mode(hw);
 952
 953         /* Unconfigure filter control */
 954         memset(&settings, 0, sizeof(settings));
 955         ret = i40e_set_filter_control(hw, &settings);
 956         if (ret)
 957                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 958                                         ret);
 959
 960         /* Disable flow control */
 961         hw->fc.requested_mode = I40E_FC_NONE;
 962         i40e_set_fc(hw, &aq_fail, TRUE);
 963
 964         /* uninitialize pf host driver */
 965         i40e_pf_host_uninit(dev);
 966
 967         rte_free(dev->data->mac_addrs);
 968         dev->data->mac_addrs = NULL;
 969
 970         /* disable uio intr before callback unregister */
 971         rte_intr_disable(&(pci_dev->intr_handle));
 972
 973         /* register callback func to eal lib */
 974         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 975                 i40e_dev_interrupt_handler, (void *)dev);
 976
 977         return 0;
 978 }
 979
 980 static int
 981 i40e_dev_configure(struct rte_eth_dev *dev)
 982 {
 983         struct i40e_adapter *ad =
 984                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 986         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 987         int i, ret;
 988
 989         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 990          * bulk allocation or vector Rx preconditions we will reset it.
 991          */
 992         ad->rx_bulk_alloc_allowed = true;
 993         ad->rx_vec_allowed = true;
 994         ad->tx_simple_allowed = true;
 995         ad->tx_vec_allowed = true;
 996
 997         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 998                 ret = i40e_fdir_setup(pf);
 999                 if (ret != I40E_SUCCESS) {
1000                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1001                         return -ENOTSUP;
1002                 }
1003                 ret = i40e_fdir_configure(dev);
1004                 if (ret < 0) {
1005                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1006                         goto err;
1007                 }
1008         } else
1009                 i40e_fdir_teardown(pf);
1010
1011         ret = i40e_dev_init_vlan(dev);
1012         if (ret < 0)
1013                 goto err;
1014
1015         /* VMDQ setup.
1016          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1017          *  RSS setting have different requirements.
1018          *  General PMD driver call sequence are NIC init, configure,
1019          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1020          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1021          *  applicable. So, VMDQ setting has to be done before
1022          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1023          *  For RSS setting, it will try to calculate actual configured RX queue
1024          *  number, which will be available after rx_queue_setup(). dev_start()
1025          *  function is good to place RSS setup.
1026          */
1027         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1028                 ret = i40e_vmdq_setup(dev);
1029                 if (ret)
1030                         goto err;
1031         }
1032
1033         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1034                 ret = i40e_dcb_setup(dev);
1035                 if (ret) {
1036                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1037                         goto err_dcb;
1038                 }
1039         }
1040
1041         return 0;
1042
1043 err_dcb:
1044         /* need to release vmdq resource if exists */
1045         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1046                 i40e_vsi_release(pf->vmdq[i].vsi);
1047                 pf->vmdq[i].vsi = NULL;
1048         }
1049         rte_free(pf->vmdq);
1050         pf->vmdq = NULL;
1051 err:
1052         /* need to release fdir resource if exists */
1053         i40e_fdir_teardown(pf);
1054         return ret;
1055 }
1056
1057 void
1058 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1059 {
1060         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1061         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1062         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1063         uint16_t msix_vect = vsi->msix_intr;
1064         uint16_t i;
1065
1066         for (i = 0; i < vsi->nb_qps; i++) {
1067                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1068                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1069                 rte_wmb();
1070         }
1071
1072         if (vsi->type != I40E_VSI_SRIOV) {
1073                 if (!rte_intr_allow_others(intr_handle)) {
1074                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1075                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1076                         I40E_WRITE_REG(hw,
1077                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1078                                        0);
1079                 } else {
1080                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1081                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1082                         I40E_WRITE_REG(hw,
1083                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1084                                                        msix_vect - 1), 0);
1085                 }
1086         } else {
1087                 uint32_t reg;
1088                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1089                         vsi->user_param + (msix_vect - 1);
1090
1091                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1092                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1093         }
1094         I40E_WRITE_FLUSH(hw);
1095 }
1096
1097 static void
1098 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1099                        int base_queue, int nb_queue)
1100 {
1101         int i;
1102         uint32_t val;
1103         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1104
1105         /* Bind all RX queues to allocated MSIX interrupt */
1106         for (i = 0; i < nb_queue; i++) {
1107                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1108                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1109                         ((base_queue + i + 1) <<
1110                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1111                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1112                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1113
1114                 if (i == nb_queue - 1)
1115                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1116                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1117         }
1118
1119         /* Write first RX queue to Link list register as the head element */
1120         if (vsi->type != I40E_VSI_SRIOV) {
1121                 uint16_t interval =
1122                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1123
1124                 if (msix_vect == I40E_MISC_VEC_ID) {
1125                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1126                                        (base_queue <<
1127                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1128                                        (0x0 <<
1129                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1130                         I40E_WRITE_REG(hw,
1131                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1132                                        interval);
1133                 } else {
1134                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1135                                        (base_queue <<
1136                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1137                                        (0x0 <<
1138                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1139                         I40E_WRITE_REG(hw,
1140                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1141                                                        msix_vect - 1),
1142                                        interval);
1143                 }
1144         } else {
1145                 uint32_t reg;
1146
1147                 if (msix_vect == I40E_MISC_VEC_ID) {
1148                         I40E_WRITE_REG(hw,
1149                                        I40E_VPINT_LNKLST0(vsi->user_param),
1150                                        (base_queue <<
1151                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1152                                        (0x0 <<
1153                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1154                 } else {
1155                         /* num_msix_vectors_vf needs to minus irq0 */
1156                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1157                                 vsi->user_param + (msix_vect - 1);
1158
1159                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1160                                        (base_queue <<
1161                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1162                                        (0x0 <<
1163                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1164                 }
1165         }
1166
1167         I40E_WRITE_FLUSH(hw);
1168 }
1169
1170 void
1171 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1172 {
1173         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1174         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1175         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1176         uint16_t msix_vect = vsi->msix_intr;
1177         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1178         uint16_t queue_idx = 0;
1179         int record = 0;
1180         uint32_t val;
1181         int i;
1182
1183         for (i = 0; i < vsi->nb_qps; i++) {
1184                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1185                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1186         }
1187
1188         /* INTENA flag is not auto-cleared for interrupt */
1189         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1190         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1191                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1192                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1193         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1194
1195         /* VF bind interrupt */
1196         if (vsi->type == I40E_VSI_SRIOV) {
1197                 __vsi_queues_bind_intr(vsi, msix_vect,
1198                                        vsi->base_queue, vsi->nb_qps);
1199                 return;
1200         }
1201
1202         /* PF & VMDq bind interrupt */
1203         if (rte_intr_dp_is_en(intr_handle)) {
1204                 if (vsi->type == I40E_VSI_MAIN) {
1205                         queue_idx = 0;
1206                         record = 1;
1207                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1208                         struct i40e_vsi *main_vsi =
1209                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1210                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1211                         record = 1;
1212                 }
1213         }
1214
1215         for (i = 0; i < vsi->nb_used_qps; i++) {
1216                 if (nb_msix <= 1) {
1217                         if (!rte_intr_allow_others(intr_handle))
1218                                 /* allow to share MISC_VEC_ID */
1219                                 msix_vect = I40E_MISC_VEC_ID;
1220
1221                         /* no enough msix_vect, map all to one */
1222                         __vsi_queues_bind_intr(vsi, msix_vect,
1223                                                vsi->base_queue + i,
1224                                                vsi->nb_used_qps - i);
1225                         for (; !!record && i < vsi->nb_used_qps; i++)
1226                                 intr_handle->intr_vec[queue_idx + i] =
1227                                         msix_vect;
1228                         break;
1229                 }
1230                 /* 1:1 queue/msix_vect mapping */
1231                 __vsi_queues_bind_intr(vsi, msix_vect,
1232                                        vsi->base_queue + i, 1);
1233                 if (!!record)
1234                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1235
1236                 msix_vect++;
1237                 nb_msix--;
1238         }
1239 }
1240
1241 static void
1242 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1243 {
1244         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1245         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1246         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1247         uint16_t interval = i40e_calc_itr_interval(\
1248                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1249         uint16_t msix_intr, i;
1250
1251         if (rte_intr_allow_others(intr_handle))
1252                 for (i = 0; i < vsi->nb_msix; i++) {
1253                         msix_intr = vsi->msix_intr + i;
1254                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1255                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1256                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1257                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1258                                 (interval <<
1259                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1260                 }
1261         else
1262                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1263                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1264                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1265                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1266                                (interval <<
1267                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1268
1269         I40E_WRITE_FLUSH(hw);
1270 }
1271
1272 static void
1273 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1274 {
1275         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1276         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1278         uint16_t msix_intr, i;
1279
1280         if (rte_intr_allow_others(intr_handle))
1281                 for (i = 0; i < vsi->nb_msix; i++) {
1282                         msix_intr = vsi->msix_intr + i;
1283                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1284                                        0);
1285                 }
1286         else
1287                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1288
1289         I40E_WRITE_FLUSH(hw);
1290 }
1291
1292 static inline uint8_t
1293 i40e_parse_link_speed(uint16_t eth_link_speed)
1294 {
1295         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1296
1297         switch (eth_link_speed) {
1298         case ETH_LINK_SPEED_40G:
1299                 link_speed = I40E_LINK_SPEED_40GB;
1300                 break;
1301         case ETH_LINK_SPEED_20G:
1302                 link_speed = I40E_LINK_SPEED_20GB;
1303                 break;
1304         case ETH_LINK_SPEED_10G:
1305                 link_speed = I40E_LINK_SPEED_10GB;
1306                 break;
1307         case ETH_LINK_SPEED_1000:
1308                 link_speed = I40E_LINK_SPEED_1GB;
1309                 break;
1310         case ETH_LINK_SPEED_100:
1311                 link_speed = I40E_LINK_SPEED_100MB;
1312                 break;
1313         }
1314
1315         return link_speed;
1316 }
1317
1318 static int
1319 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1320 {
1321         enum i40e_status_code status;
1322         struct i40e_aq_get_phy_abilities_resp phy_ab;
1323         struct i40e_aq_set_phy_config phy_conf;
1324         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1325                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1326                         I40E_AQ_PHY_FLAG_LOW_POWER;
1327         const uint8_t advt = I40E_LINK_SPEED_40GB |
1328                         I40E_LINK_SPEED_10GB |
1329                         I40E_LINK_SPEED_1GB |
1330                         I40E_LINK_SPEED_100MB;
1331         int ret = -ENOTSUP;
1332
1333         /* Skip it on 40G interfaces, as a workaround for the link issue */
1334         if (i40e_is_40G_device(hw->device_id))
1335                 return I40E_SUCCESS;
1336
1337         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1338                                               NULL);
1339         if (status)
1340                 return ret;
1341
1342         memset(&phy_conf, 0, sizeof(phy_conf));
1343
1344         /* bits 0-2 use the values from get_phy_abilities_resp */
1345         abilities &= ~mask;
1346         abilities |= phy_ab.abilities & mask;
1347
1348         /* update ablities and speed */
1349         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1350                 phy_conf.link_speed = advt;
1351         else
1352                 phy_conf.link_speed = force_speed;
1353
1354         phy_conf.abilities = abilities;
1355
1356         /* use get_phy_abilities_resp value for the rest */
1357         phy_conf.phy_type = phy_ab.phy_type;
1358         phy_conf.eee_capability = phy_ab.eee_capability;
1359         phy_conf.eeer = phy_ab.eeer_val;
1360         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1361
1362         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1363                     phy_ab.abilities, phy_ab.link_speed);
1364         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1365                     phy_conf.abilities, phy_conf.link_speed);
1366
1367         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1368         if (status)
1369                 return ret;
1370
1371         return I40E_SUCCESS;
1372 }
1373
1374 static int
1375 i40e_apply_link_speed(struct rte_eth_dev *dev)
1376 {
1377         uint8_t speed;
1378         uint8_t abilities = 0;
1379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380         struct rte_eth_conf *conf = &dev->data->dev_conf;
1381
1382         speed = i40e_parse_link_speed(conf->link_speed);
1383         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1384         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1385                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1386         else
1387                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1388
1389         return i40e_phy_conf_link(hw, abilities, speed);
1390 }
1391
1392 static int
1393 i40e_dev_start(struct rte_eth_dev *dev)
1394 {
1395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         struct i40e_vsi *main_vsi = pf->main_vsi;
1398         int ret, i;
1399         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1400         uint32_t intr_vector = 0;
1401
1402         hw->adapter_stopped = 0;
1403
1404         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1405                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1406                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1407                              dev->data->dev_conf.link_duplex,
1408                              dev->data->port_id);
1409                 return -EINVAL;
1410         }
1411
1412         rte_intr_disable(intr_handle);
1413
1414         if ((rte_intr_cap_multiple(intr_handle) ||
1415              !RTE_ETH_DEV_SRIOV(dev).active) &&
1416             dev->data->dev_conf.intr_conf.rxq != 0) {
1417                 intr_vector = dev->data->nb_rx_queues;
1418                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1419                         return -1;
1420         }
1421
1422         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1423                 intr_handle->intr_vec =
1424                         rte_zmalloc("intr_vec",
1425                                     dev->data->nb_rx_queues * sizeof(int),
1426                                     0);
1427                 if (!intr_handle->intr_vec) {
1428                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1429                                      " intr_vec\n", dev->data->nb_rx_queues);
1430                         return -ENOMEM;
1431                 }
1432         }
1433
1434         /* Initialize VSI */
1435         ret = i40e_dev_rxtx_init(pf);
1436         if (ret != I40E_SUCCESS) {
1437                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1438                 goto err_up;
1439         }
1440
1441         /* Map queues with MSIX interrupt */
1442         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1443                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1444         i40e_vsi_queues_bind_intr(main_vsi);
1445         i40e_vsi_enable_queues_intr(main_vsi);
1446
1447         /* Map VMDQ VSI queues with MSIX interrupt */
1448         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1449                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1450                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1451                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1452         }
1453
1454         /* enable FDIR MSIX interrupt */
1455         if (pf->fdir.fdir_vsi) {
1456                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1457                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1458         }
1459
1460         /* Enable all queues which have been configured */
1461         ret = i40e_dev_switch_queues(pf, TRUE);
1462         if (ret != I40E_SUCCESS) {
1463                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1464                 goto err_up;
1465         }
1466
1467         /* Enable receiving broadcast packets */
1468         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1469         if (ret != I40E_SUCCESS)
1470                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1471
1472         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1473                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1474                                                 true, NULL);
1475                 if (ret != I40E_SUCCESS)
1476                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1477         }
1478
1479         /* Apply link configure */
1480         ret = i40e_apply_link_speed(dev);
1481         if (I40E_SUCCESS != ret) {
1482                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1483                 goto err_up;
1484         }
1485
1486         if (!rte_intr_allow_others(intr_handle)) {
1487                 rte_intr_callback_unregister(intr_handle,
1488                                              i40e_dev_interrupt_handler,
1489                                              (void *)dev);
1490                 /* configure and enable device interrupt */
1491                 i40e_pf_config_irq0(hw, FALSE);
1492                 i40e_pf_enable_irq0(hw);
1493
1494                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1495                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1496                                      " no intr multiplex\n");
1497         }
1498
1499         /* enable uio intr after callback register */
1500         rte_intr_enable(intr_handle);
1501
1502         return I40E_SUCCESS;
1503
1504 err_up:
1505         i40e_dev_switch_queues(pf, FALSE);
1506         i40e_dev_clear_queues(dev);
1507
1508         return ret;
1509 }
1510
1511 static void
1512 i40e_dev_stop(struct rte_eth_dev *dev)
1513 {
1514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515         struct i40e_vsi *main_vsi = pf->main_vsi;
1516         struct i40e_mirror_rule *p_mirror;
1517         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1518         int i;
1519
1520         /* Disable all queues */
1521         i40e_dev_switch_queues(pf, FALSE);
1522
1523         /* un-map queues with interrupt registers */
1524         i40e_vsi_disable_queues_intr(main_vsi);
1525         i40e_vsi_queues_unbind_intr(main_vsi);
1526
1527         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1528                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1529                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1530         }
1531
1532         if (pf->fdir.fdir_vsi) {
1533                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1534                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1535         }
1536         /* Clear all queues and release memory */
1537         i40e_dev_clear_queues(dev);
1538
1539         /* Set link down */
1540         i40e_dev_set_link_down(dev);
1541
1542         /* Remove all mirror rules */
1543         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1544                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1545                 rte_free(p_mirror);
1546         }
1547         pf->nb_mirror_rule = 0;
1548
1549         if (!rte_intr_allow_others(intr_handle))
1550                 /* resume to the default handler */
1551                 rte_intr_callback_register(intr_handle,
1552                                            i40e_dev_interrupt_handler,
1553                                            (void *)dev);
1554
1555         /* Clean datapath event and queue/vec mapping */
1556         rte_intr_efd_disable(intr_handle);
1557         if (intr_handle->intr_vec) {
1558                 rte_free(intr_handle->intr_vec);
1559                 intr_handle->intr_vec = NULL;
1560         }
1561 }
1562
1563 static void
1564 i40e_dev_close(struct rte_eth_dev *dev)
1565 {
1566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568         uint32_t reg;
1569         int i;
1570
1571         PMD_INIT_FUNC_TRACE();
1572
1573         i40e_dev_stop(dev);
1574         hw->adapter_stopped = 1;
1575         i40e_dev_free_queues(dev);
1576
1577         /* Disable interrupt */
1578         i40e_pf_disable_irq0(hw);
1579         rte_intr_disable(&(dev->pci_dev->intr_handle));
1580
1581         /* shutdown and destroy the HMC */
1582         i40e_shutdown_lan_hmc(hw);
1583
1584         /* release all the existing VSIs and VEBs */
1585         i40e_fdir_teardown(pf);
1586         i40e_vsi_release(pf->main_vsi);
1587
1588         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1589                 i40e_vsi_release(pf->vmdq[i].vsi);
1590                 pf->vmdq[i].vsi = NULL;
1591         }
1592
1593         rte_free(pf->vmdq);
1594         pf->vmdq = NULL;
1595
1596         /* shutdown the adminq */
1597         i40e_aq_queue_shutdown(hw, true);
1598         i40e_shutdown_adminq(hw);
1599
1600         i40e_res_pool_destroy(&pf->qp_pool);
1601         i40e_res_pool_destroy(&pf->msix_pool);
1602
1603         /* force a PF reset to clean anything leftover */
1604         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1605         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1606                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1607         I40E_WRITE_FLUSH(hw);
1608 }
1609
1610 static void
1611 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1612 {
1613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1614         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615         struct i40e_vsi *vsi = pf->main_vsi;
1616         int status;
1617
1618         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1619                                                         true, NULL);
1620         if (status != I40E_SUCCESS)
1621                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1622
1623         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1624                                                         TRUE, NULL);
1625         if (status != I40E_SUCCESS)
1626                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1627
1628 }
1629
1630 static void
1631 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1632 {
1633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635         struct i40e_vsi *vsi = pf->main_vsi;
1636         int status;
1637
1638         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1639                                                         false, NULL);
1640         if (status != I40E_SUCCESS)
1641                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1642
1643         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1644                                                         false, NULL);
1645         if (status != I40E_SUCCESS)
1646                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1647 }
1648
1649 static void
1650 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1651 {
1652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         struct i40e_vsi *vsi = pf->main_vsi;
1655         int ret;
1656
1657         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1658         if (ret != I40E_SUCCESS)
1659                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1660 }
1661
1662 static void
1663 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1664 {
1665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667         struct i40e_vsi *vsi = pf->main_vsi;
1668         int ret;
1669
1670         if (dev->data->promiscuous == 1)
1671                 return; /* must remain in all_multicast mode */
1672
1673         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1674                                 vsi->seid, FALSE, NULL);
1675         if (ret != I40E_SUCCESS)
1676                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1677 }
1678
1679 /*
1680  * Set device link up.
1681  */
1682 static int
1683 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1684 {
1685         /* re-apply link speed setting */
1686         return i40e_apply_link_speed(dev);
1687 }
1688
1689 /*
1690  * Set device link down.
1691  */
1692 static int
1693 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1694 {
1695         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1696         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698
1699         return i40e_phy_conf_link(hw, abilities, speed);
1700 }
1701
1702 int
1703 i40e_dev_link_update(struct rte_eth_dev *dev,
1704                      int wait_to_complete)
1705 {
1706 #define CHECK_INTERVAL 100  /* 100ms */
1707 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         struct i40e_link_status link_status;
1710         struct rte_eth_link link, old;
1711         int status;
1712         unsigned rep_cnt = MAX_REPEAT_TIME;
1713
1714         memset(&link, 0, sizeof(link));
1715         memset(&old, 0, sizeof(old));
1716         memset(&link_status, 0, sizeof(link_status));
1717         rte_i40e_dev_atomic_read_link_status(dev, &old);
1718
1719         do {
1720                 /* Get link status information from hardware */
1721                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1722                 if (status != I40E_SUCCESS) {
1723                         link.link_speed = ETH_LINK_SPEED_100;
1724                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1725                         PMD_DRV_LOG(ERR, "Failed to get link info");
1726                         goto out;
1727                 }
1728
1729                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1730                 if (!wait_to_complete)
1731                         break;
1732
1733                 rte_delay_ms(CHECK_INTERVAL);
1734         } while (!link.link_status && rep_cnt--);
1735
1736         if (!link.link_status)
1737                 goto out;
1738
1739         /* i40e uses full duplex only */
1740         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1741
1742         /* Parse the link status */
1743         switch (link_status.link_speed) {
1744         case I40E_LINK_SPEED_100MB:
1745                 link.link_speed = ETH_LINK_SPEED_100;
1746                 break;
1747         case I40E_LINK_SPEED_1GB:
1748                 link.link_speed = ETH_LINK_SPEED_1000;
1749                 break;
1750         case I40E_LINK_SPEED_10GB:
1751                 link.link_speed = ETH_LINK_SPEED_10G;
1752                 break;
1753         case I40E_LINK_SPEED_20GB:
1754                 link.link_speed = ETH_LINK_SPEED_20G;
1755                 break;
1756         case I40E_LINK_SPEED_40GB:
1757                 link.link_speed = ETH_LINK_SPEED_40G;
1758                 break;
1759         default:
1760                 link.link_speed = ETH_LINK_SPEED_100;
1761                 break;
1762         }
1763
1764 out:
1765         rte_i40e_dev_atomic_write_link_status(dev, &link);
1766         if (link.link_status == old.link_status)
1767                 return -1;
1768
1769         return 0;
1770 }
1771
1772 /* Get all the statistics of a VSI */
1773 void
1774 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1775 {
1776         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1777         struct i40e_eth_stats *nes = &vsi->eth_stats;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1780
1781         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1782                             vsi->offset_loaded, &oes->rx_bytes,
1783                             &nes->rx_bytes);
1784         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1785                             vsi->offset_loaded, &oes->rx_unicast,
1786                             &nes->rx_unicast);
1787         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1788                             vsi->offset_loaded, &oes->rx_multicast,
1789                             &nes->rx_multicast);
1790         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1791                             vsi->offset_loaded, &oes->rx_broadcast,
1792                             &nes->rx_broadcast);
1793         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1794                             &oes->rx_discards, &nes->rx_discards);
1795         /* GLV_REPC not supported */
1796         /* GLV_RMPC not supported */
1797         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1798                             &oes->rx_unknown_protocol,
1799                             &nes->rx_unknown_protocol);
1800         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1801                             vsi->offset_loaded, &oes->tx_bytes,
1802                             &nes->tx_bytes);
1803         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1804                             vsi->offset_loaded, &oes->tx_unicast,
1805                             &nes->tx_unicast);
1806         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1807                             vsi->offset_loaded, &oes->tx_multicast,
1808                             &nes->tx_multicast);
1809         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1810                             vsi->offset_loaded,  &oes->tx_broadcast,
1811                             &nes->tx_broadcast);
1812         /* GLV_TDPC not supported */
1813         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1814                             &oes->tx_errors, &nes->tx_errors);
1815         vsi->offset_loaded = true;
1816
1817         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1818                     vsi->vsi_id);
1819         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1820         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1821         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1822         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1823         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1824         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1825                     nes->rx_unknown_protocol);
1826         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1827         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1828         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1829         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1830         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1831         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1832         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1833                     vsi->vsi_id);
1834 }
1835
1836 static void
1837 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1838 {
1839         unsigned int i;
1840         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1841         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1842         /* Get statistics of struct i40e_eth_stats */
1843         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1844                             I40E_GLPRT_GORCL(hw->port),
1845                             pf->offset_loaded, &os->eth.rx_bytes,
1846                             &ns->eth.rx_bytes);
1847         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1848                             I40E_GLPRT_UPRCL(hw->port),
1849                             pf->offset_loaded, &os->eth.rx_unicast,
1850                             &ns->eth.rx_unicast);
1851         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1852                             I40E_GLPRT_MPRCL(hw->port),
1853                             pf->offset_loaded, &os->eth.rx_multicast,
1854                             &ns->eth.rx_multicast);
1855         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1856                             I40E_GLPRT_BPRCL(hw->port),
1857                             pf->offset_loaded, &os->eth.rx_broadcast,
1858                             &ns->eth.rx_broadcast);
1859         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1860                             pf->offset_loaded, &os->eth.rx_discards,
1861                             &ns->eth.rx_discards);
1862         /* GLPRT_REPC not supported */
1863         /* GLPRT_RMPC not supported */
1864         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1865                             pf->offset_loaded,
1866                             &os->eth.rx_unknown_protocol,
1867                             &ns->eth.rx_unknown_protocol);
1868         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1869                             I40E_GLPRT_GOTCL(hw->port),
1870                             pf->offset_loaded, &os->eth.tx_bytes,
1871                             &ns->eth.tx_bytes);
1872         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1873                             I40E_GLPRT_UPTCL(hw->port),
1874                             pf->offset_loaded, &os->eth.tx_unicast,
1875                             &ns->eth.tx_unicast);
1876         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1877                             I40E_GLPRT_MPTCL(hw->port),
1878                             pf->offset_loaded, &os->eth.tx_multicast,
1879                             &ns->eth.tx_multicast);
1880         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1881                             I40E_GLPRT_BPTCL(hw->port),
1882                             pf->offset_loaded, &os->eth.tx_broadcast,
1883                             &ns->eth.tx_broadcast);
1884         /* GLPRT_TEPC not supported */
1885
1886         /* additional port specific stats */
1887         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1888                             pf->offset_loaded, &os->tx_dropped_link_down,
1889                             &ns->tx_dropped_link_down);
1890         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1891                             pf->offset_loaded, &os->crc_errors,
1892                             &ns->crc_errors);
1893         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1894                             pf->offset_loaded, &os->illegal_bytes,
1895                             &ns->illegal_bytes);
1896         /* GLPRT_ERRBC not supported */
1897         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1898                             pf->offset_loaded, &os->mac_local_faults,
1899                             &ns->mac_local_faults);
1900         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1901                             pf->offset_loaded, &os->mac_remote_faults,
1902                             &ns->mac_remote_faults);
1903         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1904                             pf->offset_loaded, &os->rx_length_errors,
1905                             &ns->rx_length_errors);
1906         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1907                             pf->offset_loaded, &os->link_xon_rx,
1908                             &ns->link_xon_rx);
1909         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1910                             pf->offset_loaded, &os->link_xoff_rx,
1911                             &ns->link_xoff_rx);
1912         for (i = 0; i < 8; i++) {
1913                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1914                                     pf->offset_loaded,
1915                                     &os->priority_xon_rx[i],
1916                                     &ns->priority_xon_rx[i]);
1917                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1918                                     pf->offset_loaded,
1919                                     &os->priority_xoff_rx[i],
1920                                     &ns->priority_xoff_rx[i]);
1921         }
1922         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1923                             pf->offset_loaded, &os->link_xon_tx,
1924                             &ns->link_xon_tx);
1925         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1926                             pf->offset_loaded, &os->link_xoff_tx,
1927                             &ns->link_xoff_tx);
1928         for (i = 0; i < 8; i++) {
1929                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1930                                     pf->offset_loaded,
1931                                     &os->priority_xon_tx[i],
1932                                     &ns->priority_xon_tx[i]);
1933                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1934                                     pf->offset_loaded,
1935                                     &os->priority_xoff_tx[i],
1936                                     &ns->priority_xoff_tx[i]);
1937                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1938                                     pf->offset_loaded,
1939                                     &os->priority_xon_2_xoff[i],
1940                                     &ns->priority_xon_2_xoff[i]);
1941         }
1942         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1943                             I40E_GLPRT_PRC64L(hw->port),
1944                             pf->offset_loaded, &os->rx_size_64,
1945                             &ns->rx_size_64);
1946         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1947                             I40E_GLPRT_PRC127L(hw->port),
1948                             pf->offset_loaded, &os->rx_size_127,
1949                             &ns->rx_size_127);
1950         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1951                             I40E_GLPRT_PRC255L(hw->port),
1952                             pf->offset_loaded, &os->rx_size_255,
1953                             &ns->rx_size_255);
1954         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1955                             I40E_GLPRT_PRC511L(hw->port),
1956                             pf->offset_loaded, &os->rx_size_511,
1957                             &ns->rx_size_511);
1958         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1959                             I40E_GLPRT_PRC1023L(hw->port),
1960                             pf->offset_loaded, &os->rx_size_1023,
1961                             &ns->rx_size_1023);
1962         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1963                             I40E_GLPRT_PRC1522L(hw->port),
1964                             pf->offset_loaded, &os->rx_size_1522,
1965                             &ns->rx_size_1522);
1966         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1967                             I40E_GLPRT_PRC9522L(hw->port),
1968                             pf->offset_loaded, &os->rx_size_big,
1969                             &ns->rx_size_big);
1970         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1971                             pf->offset_loaded, &os->rx_undersize,
1972                             &ns->rx_undersize);
1973         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1974                             pf->offset_loaded, &os->rx_fragments,
1975                             &ns->rx_fragments);
1976         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1977                             pf->offset_loaded, &os->rx_oversize,
1978                             &ns->rx_oversize);
1979         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1980                             pf->offset_loaded, &os->rx_jabber,
1981                             &ns->rx_jabber);
1982         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1983                             I40E_GLPRT_PTC64L(hw->port),
1984                             pf->offset_loaded, &os->tx_size_64,
1985                             &ns->tx_size_64);
1986         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1987                             I40E_GLPRT_PTC127L(hw->port),
1988                             pf->offset_loaded, &os->tx_size_127,
1989                             &ns->tx_size_127);
1990         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1991                             I40E_GLPRT_PTC255L(hw->port),
1992                             pf->offset_loaded, &os->tx_size_255,
1993                             &ns->tx_size_255);
1994         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1995                             I40E_GLPRT_PTC511L(hw->port),
1996                             pf->offset_loaded, &os->tx_size_511,
1997                             &ns->tx_size_511);
1998         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1999                             I40E_GLPRT_PTC1023L(hw->port),
2000                             pf->offset_loaded, &os->tx_size_1023,
2001                             &ns->tx_size_1023);
2002         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2003                             I40E_GLPRT_PTC1522L(hw->port),
2004                             pf->offset_loaded, &os->tx_size_1522,
2005                             &ns->tx_size_1522);
2006         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2007                             I40E_GLPRT_PTC9522L(hw->port),
2008                             pf->offset_loaded, &os->tx_size_big,
2009                             &ns->tx_size_big);
2010         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2011                            pf->offset_loaded,
2012                            &os->fd_sb_match, &ns->fd_sb_match);
2013         /* GLPRT_MSPDC not supported */
2014         /* GLPRT_XEC not supported */
2015
2016         pf->offset_loaded = true;
2017
2018         if (pf->main_vsi)
2019                 i40e_update_vsi_stats(pf->main_vsi);
2020 }
2021
2022 /* Get all statistics of a port */
2023 static void
2024 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2025 {
2026         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2027         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2029         unsigned i;
2030
2031         /* call read registers - updates values, now write them to struct */
2032         i40e_read_stats_registers(pf, hw);
2033
2034         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2035                         pf->main_vsi->eth_stats.rx_multicast +
2036                         pf->main_vsi->eth_stats.rx_broadcast -
2037                         pf->main_vsi->eth_stats.rx_discards;
2038         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2039                         pf->main_vsi->eth_stats.tx_multicast +
2040                         pf->main_vsi->eth_stats.tx_broadcast;
2041         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
2042         stats->obytes   = pf->main_vsi->eth_stats.tx_bytes;
2043         stats->oerrors  = ns->eth.tx_errors +
2044                         pf->main_vsi->eth_stats.tx_errors;
2045         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2046         stats->fdirmatch = ns->fd_sb_match;
2047
2048         /* Rx Errors */
2049         stats->ibadcrc  = ns->crc_errors;
2050         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
2051                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2052         stats->imissed  = ns->eth.rx_discards +
2053                         pf->main_vsi->eth_stats.rx_discards;
2054         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
2055
2056         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2057         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2058         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2059         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2060         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2061         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2062         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2063                     ns->eth.rx_unknown_protocol);
2064         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2065         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2066         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2067         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2068         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2069         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2070
2071         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2072                     ns->tx_dropped_link_down);
2073         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2074         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2075                     ns->illegal_bytes);
2076         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2077         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2078                     ns->mac_local_faults);
2079         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2080                     ns->mac_remote_faults);
2081         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2082                     ns->rx_length_errors);
2083         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2084         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2085         for (i = 0; i < 8; i++) {
2086                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2087                                 i, ns->priority_xon_rx[i]);
2088                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2089                                 i, ns->priority_xoff_rx[i]);
2090         }
2091         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2092         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2093         for (i = 0; i < 8; i++) {
2094                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2095                                 i, ns->priority_xon_tx[i]);
2096                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2097                                 i, ns->priority_xoff_tx[i]);
2098                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2099                                 i, ns->priority_xon_2_xoff[i]);
2100         }
2101         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2102         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2103         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2104         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2105         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2106         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2107         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2108         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2109         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2110         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2111         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2112         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2113         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2114         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2115         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2116         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2117         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2118         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2119         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2120                         ns->mac_short_packet_dropped);
2121         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2122                     ns->checksum_error);
2123         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2124         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2125 }
2126
2127 static void
2128 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
2129 {
2130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2133
2134         /* The hw registers are cleared on read */
2135         pf->offset_loaded = false;
2136         i40e_read_stats_registers(pf, hw);
2137
2138         /* reset software counters */
2139         memset(hw_stats, 0, sizeof(*hw_stats));
2140 }
2141
2142 static int
2143 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2144                     unsigned n)
2145 {
2146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         unsigned i, count = 0;
2149         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2150
2151         if (n < I40E_NB_XSTATS)
2152                 return I40E_NB_XSTATS;
2153
2154         i40e_read_stats_registers(pf, hw);
2155
2156         /* Reset */
2157         if (xstats == NULL)
2158                 return 0;
2159
2160         /* Get stats from i40e_eth_stats struct */
2161         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2162                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2163                          "%s", rte_i40e_stats_strings[i].name);
2164                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2165                         rte_i40e_stats_strings[i].offset);
2166                 count++;
2167         }
2168
2169         /* Get individiual stats from i40e_hw_port struct */
2170         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2171                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2172                          "%s", rte_i40e_hw_port_strings[i].name);
2173                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2174                                 rte_i40e_hw_port_strings[i].offset);
2175                 count++;
2176         }
2177
2178         /* Get per-queue stats from i40e_hw_port struct */
2179         for (i = 0; i < 8; i++) {
2180                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2181                          "rx_q%u_xon_priority_packets", i);
2182                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2183                                 offsetof(struct i40e_hw_port_stats,
2184                                          priority_xon_rx[i]));
2185                 count++;
2186
2187                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2188                          "rx_q%u_xoff_priority_packets", i);
2189                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2190                                 offsetof(struct i40e_hw_port_stats,
2191                                          priority_xoff_rx[i]));
2192                 count++;
2193
2194                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2195                          "tx_q%u_xon_priority_packets", i);
2196                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2197                                 offsetof(struct i40e_hw_port_stats,
2198                                          priority_xon_tx[i]));
2199                 count++;
2200
2201                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2202                          "tx_q%u_xoff_priority_packets", i);
2203                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2204                                 offsetof(struct i40e_hw_port_stats,
2205                                          priority_xoff_tx[i]));
2206                 count++;
2207
2208                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2209                          "xx_q%u_xon_to_xoff_priority_packets", i);
2210                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2211                                 offsetof(struct i40e_hw_port_stats,
2212                                          priority_xon_2_xoff[i]));
2213                 count++;
2214         }
2215
2216         return I40E_NB_XSTATS;
2217 }
2218
2219 /* Reset the statistics */
2220 static void
2221 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2222 {
2223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2224
2225         /* It results in reloading the start point of each counter */
2226         pf->offset_loaded = false;
2227 }
2228
2229 static int
2230 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2231                                  __rte_unused uint16_t queue_id,
2232                                  __rte_unused uint8_t stat_idx,
2233                                  __rte_unused uint8_t is_rx)
2234 {
2235         PMD_INIT_FUNC_TRACE();
2236
2237         return -ENOSYS;
2238 }
2239
2240 static void
2241 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2242 {
2243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244         struct i40e_vsi *vsi = pf->main_vsi;
2245
2246         dev_info->max_rx_queues = vsi->nb_qps;
2247         dev_info->max_tx_queues = vsi->nb_qps;
2248         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2249         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2250         dev_info->max_mac_addrs = vsi->max_macaddrs;
2251         dev_info->max_vfs = dev->pci_dev->max_vfs;
2252         dev_info->rx_offload_capa =
2253                 DEV_RX_OFFLOAD_VLAN_STRIP |
2254                 DEV_RX_OFFLOAD_QINQ_STRIP |
2255                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2256                 DEV_RX_OFFLOAD_UDP_CKSUM |
2257                 DEV_RX_OFFLOAD_TCP_CKSUM;
2258         dev_info->tx_offload_capa =
2259                 DEV_TX_OFFLOAD_VLAN_INSERT |
2260                 DEV_TX_OFFLOAD_QINQ_INSERT |
2261                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2262                 DEV_TX_OFFLOAD_UDP_CKSUM |
2263                 DEV_TX_OFFLOAD_TCP_CKSUM |
2264                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2265                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2266                 DEV_TX_OFFLOAD_TCP_TSO;
2267         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2268                                                 sizeof(uint32_t);
2269         dev_info->reta_size = pf->hash_lut_size;
2270         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2271
2272         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2273                 .rx_thresh = {
2274                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2275                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2276                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2277                 },
2278                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2279                 .rx_drop_en = 0,
2280         };
2281
2282         dev_info->default_txconf = (struct rte_eth_txconf) {
2283                 .tx_thresh = {
2284                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2285                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2286                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2287                 },
2288                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2289                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2290                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2291                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2292         };
2293
2294         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2295                 .nb_max = I40E_MAX_RING_DESC,
2296                 .nb_min = I40E_MIN_RING_DESC,
2297                 .nb_align = I40E_ALIGN_RING_DESC,
2298         };
2299
2300         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2301                 .nb_max = I40E_MAX_RING_DESC,
2302                 .nb_min = I40E_MIN_RING_DESC,
2303                 .nb_align = I40E_ALIGN_RING_DESC,
2304         };
2305
2306         if (pf->flags & I40E_FLAG_VMDQ) {
2307                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2308                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2309                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2310                                                 pf->max_nb_vmdq_vsi;
2311                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2312                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2313                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2314         }
2315 }
2316
2317 static int
2318 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2319 {
2320         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2321         struct i40e_vsi *vsi = pf->main_vsi;
2322         PMD_INIT_FUNC_TRACE();
2323
2324         if (on)
2325                 return i40e_vsi_add_vlan(vsi, vlan_id);
2326         else
2327                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2328 }
2329
2330 static void
2331 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2332                    __rte_unused uint16_t tpid)
2333 {
2334         PMD_INIT_FUNC_TRACE();
2335 }
2336
2337 static void
2338 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2339 {
2340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2341         struct i40e_vsi *vsi = pf->main_vsi;
2342
2343         if (mask & ETH_VLAN_STRIP_MASK) {
2344                 /* Enable or disable VLAN stripping */
2345                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2346                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2347                 else
2348                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2349         }
2350
2351         if (mask & ETH_VLAN_EXTEND_MASK) {
2352                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2353                         i40e_vsi_config_double_vlan(vsi, TRUE);
2354                 else
2355                         i40e_vsi_config_double_vlan(vsi, FALSE);
2356         }
2357 }
2358
2359 static void
2360 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2361                           __rte_unused uint16_t queue,
2362                           __rte_unused int on)
2363 {
2364         PMD_INIT_FUNC_TRACE();
2365 }
2366
2367 static int
2368 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2369 {
2370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2371         struct i40e_vsi *vsi = pf->main_vsi;
2372         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2373         struct i40e_vsi_vlan_pvid_info info;
2374
2375         memset(&info, 0, sizeof(info));
2376         info.on = on;
2377         if (info.on)
2378                 info.config.pvid = pvid;
2379         else {
2380                 info.config.reject.tagged =
2381                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2382                 info.config.reject.untagged =
2383                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2384         }
2385
2386         return i40e_vsi_vlan_pvid_set(vsi, &info);
2387 }
2388
2389 static int
2390 i40e_dev_led_on(struct rte_eth_dev *dev)
2391 {
2392         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393         uint32_t mode = i40e_led_get(hw);
2394
2395         if (mode == 0)
2396                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2397
2398         return 0;
2399 }
2400
2401 static int
2402 i40e_dev_led_off(struct rte_eth_dev *dev)
2403 {
2404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         uint32_t mode = i40e_led_get(hw);
2406
2407         if (mode != 0)
2408                 i40e_led_set(hw, 0, false);
2409
2410         return 0;
2411 }
2412
2413 static int
2414 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2415 {
2416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2418
2419         fc_conf->pause_time = pf->fc_conf.pause_time;
2420         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2421         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2422
2423          /* Return current mode according to actual setting*/
2424         switch (hw->fc.current_mode) {
2425         case I40E_FC_FULL:
2426                 fc_conf->mode = RTE_FC_FULL;
2427                 break;
2428         case I40E_FC_TX_PAUSE:
2429                 fc_conf->mode = RTE_FC_TX_PAUSE;
2430                 break;
2431         case I40E_FC_RX_PAUSE:
2432                 fc_conf->mode = RTE_FC_RX_PAUSE;
2433                 break;
2434         case I40E_FC_NONE:
2435         default:
2436                 fc_conf->mode = RTE_FC_NONE;
2437         };
2438
2439         return 0;
2440 }
2441
2442 static int
2443 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2444 {
2445         uint32_t mflcn_reg, fctrl_reg, reg;
2446         uint32_t max_high_water;
2447         uint8_t i, aq_failure;
2448         int err;
2449         struct i40e_hw *hw;
2450         struct i40e_pf *pf;
2451         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2452                 [RTE_FC_NONE] = I40E_FC_NONE,
2453                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2454                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2455                 [RTE_FC_FULL] = I40E_FC_FULL
2456         };
2457
2458         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2459
2460         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2461         if ((fc_conf->high_water > max_high_water) ||
2462                         (fc_conf->high_water < fc_conf->low_water)) {
2463                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2464                         "High_water must <= %d.", max_high_water);
2465                 return -EINVAL;
2466         }
2467
2468         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2471
2472         pf->fc_conf.pause_time = fc_conf->pause_time;
2473         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2474         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2475
2476         PMD_INIT_FUNC_TRACE();
2477
2478         /* All the link flow control related enable/disable register
2479          * configuration is handle by the F/W
2480          */
2481         err = i40e_set_fc(hw, &aq_failure, true);
2482         if (err < 0)
2483                 return -ENOSYS;
2484
2485         if (i40e_is_40G_device(hw->device_id)) {
2486                 /* Configure flow control refresh threshold,
2487                  * the value for stat_tx_pause_refresh_timer[8]
2488                  * is used for global pause operation.
2489                  */
2490
2491                 I40E_WRITE_REG(hw,
2492                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2493                                pf->fc_conf.pause_time);
2494
2495                 /* configure the timer value included in transmitted pause
2496                  * frame,
2497                  * the value for stat_tx_pause_quanta[8] is used for global
2498                  * pause operation
2499                  */
2500                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2501                                pf->fc_conf.pause_time);
2502
2503                 fctrl_reg = I40E_READ_REG(hw,
2504                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2505
2506                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2507                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2508                 else
2509                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2510
2511                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2512                                fctrl_reg);
2513         } else {
2514                 /* Configure pause time (2 TCs per register) */
2515                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2516                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2517                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2518
2519                 /* Configure flow control refresh threshold value */
2520                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2521                                pf->fc_conf.pause_time / 2);
2522
2523                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2524
2525                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2526                  *depending on configuration
2527                  */
2528                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2529                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2530                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2531                 } else {
2532                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2533                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2534                 }
2535
2536                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2537         }
2538
2539         /* config the water marker both based on the packets and bytes */
2540         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2541                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2542                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2543         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2544                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2545                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2546         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2547                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2548                        << I40E_KILOSHIFT);
2549         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2550                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2551                        << I40E_KILOSHIFT);
2552
2553         I40E_WRITE_FLUSH(hw);
2554
2555         return 0;
2556 }
2557
2558 static int
2559 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2560                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2561 {
2562         PMD_INIT_FUNC_TRACE();
2563
2564         return -ENOSYS;
2565 }
2566
2567 /* Add a MAC address, and update filters */
2568 static void
2569 i40e_macaddr_add(struct rte_eth_dev *dev,
2570                  struct ether_addr *mac_addr,
2571                  __rte_unused uint32_t index,
2572                  uint32_t pool)
2573 {
2574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575         struct i40e_mac_filter_info mac_filter;
2576         struct i40e_vsi *vsi;
2577         int ret;
2578
2579         /* If VMDQ not enabled or configured, return */
2580         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2581                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2582                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2583                         pool);
2584                 return;
2585         }
2586
2587         if (pool > pf->nb_cfg_vmdq_vsi) {
2588                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2589                                 pool, pf->nb_cfg_vmdq_vsi);
2590                 return;
2591         }
2592
2593         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2594         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2595
2596         if (pool == 0)
2597                 vsi = pf->main_vsi;
2598         else
2599                 vsi = pf->vmdq[pool - 1].vsi;
2600
2601         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2602         if (ret != I40E_SUCCESS) {
2603                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2604                 return;
2605         }
2606 }
2607
2608 /* Remove a MAC address, and update filters */
2609 static void
2610 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2611 {
2612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2613         struct i40e_vsi *vsi;
2614         struct rte_eth_dev_data *data = dev->data;
2615         struct ether_addr *macaddr;
2616         int ret;
2617         uint32_t i;
2618         uint64_t pool_sel;
2619
2620         macaddr = &(data->mac_addrs[index]);
2621
2622         pool_sel = dev->data->mac_pool_sel[index];
2623
2624         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2625                 if (pool_sel & (1ULL << i)) {
2626                         if (i == 0)
2627                                 vsi = pf->main_vsi;
2628                         else {
2629                                 /* No VMDQ pool enabled or configured */
2630                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2631                                         (i > pf->nb_cfg_vmdq_vsi)) {
2632                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2633                                                         "/configured");
2634                                         return;
2635                                 }
2636                                 vsi = pf->vmdq[i - 1].vsi;
2637                         }
2638                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2639
2640                         if (ret) {
2641                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2642                                 return;
2643                         }
2644                 }
2645         }
2646 }
2647
2648 /* Set perfect match or hash match of MAC and VLAN for a VF */
2649 static int
2650 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2651                  struct rte_eth_mac_filter *filter,
2652                  bool add)
2653 {
2654         struct i40e_hw *hw;
2655         struct i40e_mac_filter_info mac_filter;
2656         struct ether_addr old_mac;
2657         struct ether_addr *new_mac;
2658         struct i40e_pf_vf *vf = NULL;
2659         uint16_t vf_id;
2660         int ret;
2661
2662         if (pf == NULL) {
2663                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2664                 return -EINVAL;
2665         }
2666         hw = I40E_PF_TO_HW(pf);
2667
2668         if (filter == NULL) {
2669                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2670                 return -EINVAL;
2671         }
2672
2673         new_mac = &filter->mac_addr;
2674
2675         if (is_zero_ether_addr(new_mac)) {
2676                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2677                 return -EINVAL;
2678         }
2679
2680         vf_id = filter->dst_id;
2681
2682         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2683                 PMD_DRV_LOG(ERR, "Invalid argument.");
2684                 return -EINVAL;
2685         }
2686         vf = &pf->vfs[vf_id];
2687
2688         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2689                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2690                 return -EINVAL;
2691         }
2692
2693         if (add) {
2694                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2695                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2696                                 ETHER_ADDR_LEN);
2697                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2698                                  ETHER_ADDR_LEN);
2699
2700                 mac_filter.filter_type = filter->filter_type;
2701                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2702                 if (ret != I40E_SUCCESS) {
2703                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2704                         return -1;
2705                 }
2706                 ether_addr_copy(new_mac, &pf->dev_addr);
2707         } else {
2708                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2709                                 ETHER_ADDR_LEN);
2710                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2711                 if (ret != I40E_SUCCESS) {
2712                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2713                         return -1;
2714                 }
2715
2716                 /* Clear device address as it has been removed */
2717                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2718                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2719         }
2720
2721         return 0;
2722 }
2723
2724 /* MAC filter handle */
2725 static int
2726 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2727                 void *arg)
2728 {
2729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2730         struct rte_eth_mac_filter *filter;
2731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2732         int ret = I40E_NOT_SUPPORTED;
2733
2734         filter = (struct rte_eth_mac_filter *)(arg);
2735
2736         switch (filter_op) {
2737         case RTE_ETH_FILTER_NOP:
2738                 ret = I40E_SUCCESS;
2739                 break;
2740         case RTE_ETH_FILTER_ADD:
2741                 i40e_pf_disable_irq0(hw);
2742                 if (filter->is_vf)
2743                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2744                 i40e_pf_enable_irq0(hw);
2745                 break;
2746         case RTE_ETH_FILTER_DELETE:
2747                 i40e_pf_disable_irq0(hw);
2748                 if (filter->is_vf)
2749                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2750                 i40e_pf_enable_irq0(hw);
2751                 break;
2752         default:
2753                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2754                 ret = I40E_ERR_PARAM;
2755                 break;
2756         }
2757
2758         return ret;
2759 }
2760
2761 static int
2762 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2763 {
2764         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2765         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2766         int ret;
2767
2768         if (!lut)
2769                 return -EINVAL;
2770
2771         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2772                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2773                                           lut, lut_size);
2774                 if (ret) {
2775                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2776                         return ret;
2777                 }
2778         } else {
2779                 uint32_t *lut_dw = (uint32_t *)lut;
2780                 uint16_t i, lut_size_dw = lut_size / 4;
2781
2782                 for (i = 0; i < lut_size_dw; i++)
2783                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2784         }
2785
2786         return 0;
2787 }
2788
2789 static int
2790 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2791 {
2792         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2793         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2794         int ret;
2795
2796         if (!vsi || !lut)
2797                 return -EINVAL;
2798
2799         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2800                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2801                                           lut, lut_size);
2802                 if (ret) {
2803                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2804                         return ret;
2805                 }
2806         } else {
2807                 uint32_t *lut_dw = (uint32_t *)lut;
2808                 uint16_t i, lut_size_dw = lut_size / 4;
2809
2810                 for (i = 0; i < lut_size_dw; i++)
2811                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2812                 I40E_WRITE_FLUSH(hw);
2813         }
2814
2815         return 0;
2816 }
2817
2818 static int
2819 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2820                          struct rte_eth_rss_reta_entry64 *reta_conf,
2821                          uint16_t reta_size)
2822 {
2823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2824         uint16_t i, lut_size = pf->hash_lut_size;
2825         uint16_t idx, shift;
2826         uint8_t *lut;
2827         int ret;
2828
2829         if (reta_size != lut_size ||
2830                 reta_size > ETH_RSS_RETA_SIZE_512) {
2831                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2832                         "(%d) doesn't match the number hardware can supported "
2833                                         "(%d)\n", reta_size, lut_size);
2834                 return -EINVAL;
2835         }
2836
2837         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2838         if (!lut) {
2839                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2840                 return -ENOMEM;
2841         }
2842         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2843         if (ret)
2844                 goto out;
2845         for (i = 0; i < reta_size; i++) {
2846                 idx = i / RTE_RETA_GROUP_SIZE;
2847                 shift = i % RTE_RETA_GROUP_SIZE;
2848                 if (reta_conf[idx].mask & (1ULL << shift))
2849                         lut[i] = reta_conf[idx].reta[shift];
2850         }
2851         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2852
2853 out:
2854         rte_free(lut);
2855
2856         return ret;
2857 }
2858
2859 static int
2860 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2861                         struct rte_eth_rss_reta_entry64 *reta_conf,
2862                         uint16_t reta_size)
2863 {
2864         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2865         uint16_t i, lut_size = pf->hash_lut_size;
2866         uint16_t idx, shift;
2867         uint8_t *lut;
2868         int ret;
2869
2870         if (reta_size != lut_size ||
2871                 reta_size > ETH_RSS_RETA_SIZE_512) {
2872                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2873                         "(%d) doesn't match the number hardware can supported "
2874                                         "(%d)\n", reta_size, lut_size);
2875                 return -EINVAL;
2876         }
2877
2878         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2879         if (!lut) {
2880                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2881                 return -ENOMEM;
2882         }
2883
2884         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2885         if (ret)
2886                 goto out;
2887         for (i = 0; i < reta_size; i++) {
2888                 idx = i / RTE_RETA_GROUP_SIZE;
2889                 shift = i % RTE_RETA_GROUP_SIZE;
2890                 if (reta_conf[idx].mask & (1ULL << shift))
2891                         reta_conf[idx].reta[shift] = lut[i];
2892         }
2893
2894 out:
2895         rte_free(lut);
2896
2897         return ret;
2898 }
2899
2900 /**
2901  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2902  * @hw:   pointer to the HW structure
2903  * @mem:  pointer to mem struct to fill out
2904  * @size: size of memory requested
2905  * @alignment: what to align the allocation to
2906  **/
2907 enum i40e_status_code
2908 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2909                         struct i40e_dma_mem *mem,
2910                         u64 size,
2911                         u32 alignment)
2912 {
2913         static uint64_t id = 0;
2914         const struct rte_memzone *mz = NULL;
2915         char z_name[RTE_MEMZONE_NAMESIZE];
2916
2917         if (!mem)
2918                 return I40E_ERR_PARAM;
2919
2920         id++;
2921         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2922 #ifdef RTE_LIBRTE_XEN_DOM0
2923         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2924                                          alignment, RTE_PGSIZE_2M);
2925 #else
2926         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2927                                          alignment);
2928 #endif
2929         if (!mz)
2930                 return I40E_ERR_NO_MEMORY;
2931
2932         mem->id = id;
2933         mem->size = size;
2934         mem->va = mz->addr;
2935 #ifdef RTE_LIBRTE_XEN_DOM0
2936         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2937 #else
2938         mem->pa = mz->phys_addr;
2939 #endif
2940
2941         return I40E_SUCCESS;
2942 }
2943
2944 /**
2945  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2946  * @hw:   pointer to the HW structure
2947  * @mem:  ptr to mem struct to free
2948  **/
2949 enum i40e_status_code
2950 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2951                     struct i40e_dma_mem *mem)
2952 {
2953         if (!mem || !mem->va)
2954                 return I40E_ERR_PARAM;
2955
2956         mem->va = NULL;
2957         mem->pa = (u64)0;
2958
2959         return I40E_SUCCESS;
2960 }
2961
2962 /**
2963  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2964  * @hw:   pointer to the HW structure
2965  * @mem:  pointer to mem struct to fill out
2966  * @size: size of memory requested
2967  **/
2968 enum i40e_status_code
2969 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2970                          struct i40e_virt_mem *mem,
2971                          u32 size)
2972 {
2973         if (!mem)
2974                 return I40E_ERR_PARAM;
2975
2976         mem->size = size;
2977         mem->va = rte_zmalloc("i40e", size, 0);
2978
2979         if (mem->va)
2980                 return I40E_SUCCESS;
2981         else
2982                 return I40E_ERR_NO_MEMORY;
2983 }
2984
2985 /**
2986  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2987  * @hw:   pointer to the HW structure
2988  * @mem:  pointer to mem struct to free
2989  **/
2990 enum i40e_status_code
2991 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2992                      struct i40e_virt_mem *mem)
2993 {
2994         if (!mem)
2995                 return I40E_ERR_PARAM;
2996
2997         rte_free(mem->va);
2998         mem->va = NULL;
2999
3000         return I40E_SUCCESS;
3001 }
3002
3003 void
3004 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3005 {
3006         rte_spinlock_init(&sp->spinlock);
3007 }
3008
3009 void
3010 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3011 {
3012         rte_spinlock_lock(&sp->spinlock);
3013 }
3014
3015 void
3016 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3017 {
3018         rte_spinlock_unlock(&sp->spinlock);
3019 }
3020
3021 void
3022 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3023 {
3024         return;
3025 }
3026
3027 /**
3028  * Get the hardware capabilities, which will be parsed
3029  * and saved into struct i40e_hw.
3030  */
3031 static int
3032 i40e_get_cap(struct i40e_hw *hw)
3033 {
3034         struct i40e_aqc_list_capabilities_element_resp *buf;
3035         uint16_t len, size = 0;
3036         int ret;
3037
3038         /* Calculate a huge enough buff for saving response data temporarily */
3039         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3040                                                 I40E_MAX_CAP_ELE_NUM;
3041         buf = rte_zmalloc("i40e", len, 0);
3042         if (!buf) {
3043                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3044                 return I40E_ERR_NO_MEMORY;
3045         }
3046
3047         /* Get, parse the capabilities and save it to hw */
3048         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3049                         i40e_aqc_opc_list_func_capabilities, NULL);
3050         if (ret != I40E_SUCCESS)
3051                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3052
3053         /* Free the temporary buffer after being used */
3054         rte_free(buf);
3055
3056         return ret;
3057 }
3058
3059 static int
3060 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3061 {
3062         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3063         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3064         uint16_t qp_count = 0, vsi_count = 0;
3065
3066         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3067                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3068                 return -EINVAL;
3069         }
3070         /* Add the parameter init for LFC */
3071         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3072         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3073         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3074
3075         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3076         pf->max_num_vsi = hw->func_caps.num_vsis;
3077         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3078         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3079         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3080
3081         /* FDir queue/VSI allocation */
3082         pf->fdir_qp_offset = 0;
3083         if (hw->func_caps.fd) {
3084                 pf->flags |= I40E_FLAG_FDIR;
3085                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3086         } else {
3087                 pf->fdir_nb_qps = 0;
3088         }
3089         qp_count += pf->fdir_nb_qps;
3090         vsi_count += 1;
3091
3092         /* LAN queue/VSI allocation */
3093         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3094         if (!hw->func_caps.rss) {
3095                 pf->lan_nb_qps = 1;
3096         } else {
3097                 pf->flags |= I40E_FLAG_RSS;
3098                 if (hw->mac.type == I40E_MAC_X722)
3099                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3100                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3101         }
3102         qp_count += pf->lan_nb_qps;
3103         vsi_count += 1;
3104
3105         /* VF queue/VSI allocation */
3106         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3107         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3108                 pf->flags |= I40E_FLAG_SRIOV;
3109                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3110                 pf->vf_num = dev->pci_dev->max_vfs;
3111                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3112                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3113                             pf->vf_nb_qps * pf->vf_num);
3114         } else {
3115                 pf->vf_nb_qps = 0;
3116                 pf->vf_num = 0;
3117         }
3118         qp_count += pf->vf_nb_qps * pf->vf_num;
3119         vsi_count += pf->vf_num;
3120
3121         /* VMDq queue/VSI allocation */
3122         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3123         pf->vmdq_nb_qps = 0;
3124         pf->max_nb_vmdq_vsi = 0;
3125         if (hw->func_caps.vmdq) {
3126                 if (qp_count < hw->func_caps.num_tx_qp) {
3127                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3128                                 qp_count) / pf->vmdq_nb_qp_max;
3129
3130                         /* Limit the maximum number of VMDq vsi to the maximum
3131                          * ethdev can support
3132                          */
3133                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3134                                 ETH_64_POOLS);
3135                         if (pf->max_nb_vmdq_vsi) {
3136                                 pf->flags |= I40E_FLAG_VMDQ;
3137                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3138                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3139                                             "per VMDQ VSI, in total %u queues",
3140                                             pf->max_nb_vmdq_vsi,
3141                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3142                                             pf->max_nb_vmdq_vsi);
3143                         } else {
3144                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3145                                             "VMDq");
3146                         }
3147                 } else {
3148                         PMD_DRV_LOG(INFO, "No queue left for VMDq");
3149                 }
3150         }
3151         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3152         vsi_count += pf->max_nb_vmdq_vsi;
3153
3154         if (hw->func_caps.dcb)
3155                 pf->flags |= I40E_FLAG_DCB;
3156
3157         if (qp_count > hw->func_caps.num_tx_qp) {
3158                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3159                             "the hardware maximum %u", qp_count,
3160                             hw->func_caps.num_tx_qp);
3161                 return -EINVAL;
3162         }
3163         if (vsi_count > hw->func_caps.num_vsis) {
3164                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3165                             "the hardware maximum %u", vsi_count,
3166                             hw->func_caps.num_vsis);
3167                 return -EINVAL;
3168         }
3169
3170         return 0;
3171 }
3172
3173 static int
3174 i40e_pf_get_switch_config(struct i40e_pf *pf)
3175 {
3176         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3177         struct i40e_aqc_get_switch_config_resp *switch_config;
3178         struct i40e_aqc_switch_config_element_resp *element;
3179         uint16_t start_seid = 0, num_reported;
3180         int ret;
3181
3182         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3183                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3184         if (!switch_config) {
3185                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3186                 return -ENOMEM;
3187         }
3188
3189         /* Get the switch configurations */
3190         ret = i40e_aq_get_switch_config(hw, switch_config,
3191                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3192         if (ret != I40E_SUCCESS) {
3193                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3194                 goto fail;
3195         }
3196         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3197         if (num_reported != 1) { /* The number should be 1 */
3198                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3199                 goto fail;
3200         }
3201
3202         /* Parse the switch configuration elements */
3203         element = &(switch_config->element[0]);
3204         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3205                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3206                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3207         } else
3208                 PMD_DRV_LOG(INFO, "Unknown element type");
3209
3210 fail:
3211         rte_free(switch_config);
3212
3213         return ret;
3214 }
3215
3216 static int
3217 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3218                         uint32_t num)
3219 {
3220         struct pool_entry *entry;
3221
3222         if (pool == NULL || num == 0)
3223                 return -EINVAL;
3224
3225         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3226         if (entry == NULL) {
3227                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3228                 return -ENOMEM;
3229         }
3230
3231         /* queue heap initialize */
3232         pool->num_free = num;
3233         pool->num_alloc = 0;
3234         pool->base = base;
3235         LIST_INIT(&pool->alloc_list);
3236         LIST_INIT(&pool->free_list);
3237
3238         /* Initialize element  */
3239         entry->base = 0;
3240         entry->len = num;
3241
3242         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3243         return 0;
3244 }
3245
3246 static void
3247 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3248 {
3249         struct pool_entry *entry;
3250
3251         if (pool == NULL)
3252                 return;
3253
3254         LIST_FOREACH(entry, &pool->alloc_list, next) {
3255                 LIST_REMOVE(entry, next);
3256                 rte_free(entry);
3257         }
3258
3259         LIST_FOREACH(entry, &pool->free_list, next) {
3260                 LIST_REMOVE(entry, next);
3261                 rte_free(entry);
3262         }
3263
3264         pool->num_free = 0;
3265         pool->num_alloc = 0;
3266         pool->base = 0;
3267         LIST_INIT(&pool->alloc_list);
3268         LIST_INIT(&pool->free_list);
3269 }
3270
3271 static int
3272 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3273                        uint32_t base)
3274 {
3275         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3276         uint32_t pool_offset;
3277         int insert;
3278
3279         if (pool == NULL) {
3280                 PMD_DRV_LOG(ERR, "Invalid parameter");
3281                 return -EINVAL;
3282         }
3283
3284         pool_offset = base - pool->base;
3285         /* Lookup in alloc list */
3286         LIST_FOREACH(entry, &pool->alloc_list, next) {
3287                 if (entry->base == pool_offset) {
3288                         valid_entry = entry;
3289                         LIST_REMOVE(entry, next);
3290                         break;
3291                 }
3292         }
3293
3294         /* Not find, return */
3295         if (valid_entry == NULL) {
3296                 PMD_DRV_LOG(ERR, "Failed to find entry");
3297                 return -EINVAL;
3298         }
3299
3300         /**
3301          * Found it, move it to free list  and try to merge.
3302          * In order to make merge easier, always sort it by qbase.
3303          * Find adjacent prev and last entries.
3304          */
3305         prev = next = NULL;
3306         LIST_FOREACH(entry, &pool->free_list, next) {
3307                 if (entry->base > valid_entry->base) {
3308                         next = entry;
3309                         break;
3310                 }
3311                 prev = entry;
3312         }
3313
3314         insert = 0;
3315         /* Try to merge with next one*/
3316         if (next != NULL) {
3317                 /* Merge with next one */
3318                 if (valid_entry->base + valid_entry->len == next->base) {
3319                         next->base = valid_entry->base;
3320                         next->len += valid_entry->len;
3321                         rte_free(valid_entry);
3322                         valid_entry = next;
3323                         insert = 1;
3324                 }
3325         }
3326
3327         if (prev != NULL) {
3328                 /* Merge with previous one */
3329                 if (prev->base + prev->len == valid_entry->base) {
3330                         prev->len += valid_entry->len;
3331                         /* If it merge with next one, remove next node */
3332                         if (insert == 1) {
3333                                 LIST_REMOVE(valid_entry, next);
3334                                 rte_free(valid_entry);
3335                         } else {
3336                                 rte_free(valid_entry);
3337                                 insert = 1;
3338                         }
3339                 }
3340         }
3341
3342         /* Not find any entry to merge, insert */
3343         if (insert == 0) {
3344                 if (prev != NULL)
3345                         LIST_INSERT_AFTER(prev, valid_entry, next);
3346                 else if (next != NULL)
3347                         LIST_INSERT_BEFORE(next, valid_entry, next);
3348                 else /* It's empty list, insert to head */
3349                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3350         }
3351
3352         pool->num_free += valid_entry->len;
3353         pool->num_alloc -= valid_entry->len;
3354
3355         return 0;
3356 }
3357
3358 static int
3359 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3360                        uint16_t num)
3361 {
3362         struct pool_entry *entry, *valid_entry;
3363
3364         if (pool == NULL || num == 0) {
3365                 PMD_DRV_LOG(ERR, "Invalid parameter");
3366                 return -EINVAL;
3367         }
3368
3369         if (pool->num_free < num) {
3370                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3371                             num, pool->num_free);
3372                 return -ENOMEM;
3373         }
3374
3375         valid_entry = NULL;
3376         /* Lookup  in free list and find most fit one */
3377         LIST_FOREACH(entry, &pool->free_list, next) {
3378                 if (entry->len >= num) {
3379                         /* Find best one */
3380                         if (entry->len == num) {
3381                                 valid_entry = entry;
3382                                 break;
3383                         }
3384                         if (valid_entry == NULL || valid_entry->len > entry->len)
3385                                 valid_entry = entry;
3386                 }
3387         }
3388
3389         /* Not find one to satisfy the request, return */
3390         if (valid_entry == NULL) {
3391                 PMD_DRV_LOG(ERR, "No valid entry found");
3392                 return -ENOMEM;
3393         }
3394         /**
3395          * The entry have equal queue number as requested,
3396          * remove it from alloc_list.
3397          */
3398         if (valid_entry->len == num) {
3399                 LIST_REMOVE(valid_entry, next);
3400         } else {
3401                 /**
3402                  * The entry have more numbers than requested,
3403                  * create a new entry for alloc_list and minus its
3404                  * queue base and number in free_list.
3405                  */
3406                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3407                 if (entry == NULL) {
3408                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3409                                     "resource pool");
3410                         return -ENOMEM;
3411                 }
3412                 entry->base = valid_entry->base;
3413                 entry->len = num;
3414                 valid_entry->base += num;
3415                 valid_entry->len -= num;
3416                 valid_entry = entry;
3417         }
3418
3419         /* Insert it into alloc list, not sorted */
3420         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3421
3422         pool->num_free -= valid_entry->len;
3423         pool->num_alloc += valid_entry->len;
3424
3425         return (valid_entry->base + pool->base);
3426 }
3427
3428 /**
3429  * bitmap_is_subset - Check whether src2 is subset of src1
3430  **/
3431 static inline int
3432 bitmap_is_subset(uint8_t src1, uint8_t src2)
3433 {
3434         return !((src1 ^ src2) & src2);
3435 }
3436
3437 static enum i40e_status_code
3438 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3439 {
3440         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3441
3442         /* If DCB is not supported, only default TC is supported */
3443         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3444                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3445                 return I40E_NOT_SUPPORTED;
3446         }
3447
3448         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3449                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3450                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3451                             enabled_tcmap);
3452                 return I40E_NOT_SUPPORTED;
3453         }
3454         return I40E_SUCCESS;
3455 }
3456
3457 int
3458 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3459                                 struct i40e_vsi_vlan_pvid_info *info)
3460 {
3461         struct i40e_hw *hw;
3462         struct i40e_vsi_context ctxt;
3463         uint8_t vlan_flags = 0;
3464         int ret;
3465
3466         if (vsi == NULL || info == NULL) {
3467                 PMD_DRV_LOG(ERR, "invalid parameters");
3468                 return I40E_ERR_PARAM;
3469         }
3470
3471         if (info->on) {
3472                 vsi->info.pvid = info->config.pvid;
3473                 /**
3474                  * If insert pvid is enabled, only tagged pkts are
3475                  * allowed to be sent out.
3476                  */
3477                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3478                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3479         } else {
3480                 vsi->info.pvid = 0;
3481                 if (info->config.reject.tagged == 0)
3482                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3483
3484                 if (info->config.reject.untagged == 0)
3485                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3486         }
3487         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3488                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3489         vsi->info.port_vlan_flags |= vlan_flags;
3490         vsi->info.valid_sections =
3491                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3492         memset(&ctxt, 0, sizeof(ctxt));
3493         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3494         ctxt.seid = vsi->seid;
3495
3496         hw = I40E_VSI_TO_HW(vsi);
3497         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3498         if (ret != I40E_SUCCESS)
3499                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3500
3501         return ret;
3502 }
3503
3504 static int
3505 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3506 {
3507         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3508         int i, ret;
3509         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3510
3511         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3512         if (ret != I40E_SUCCESS)
3513                 return ret;
3514
3515         if (!vsi->seid) {
3516                 PMD_DRV_LOG(ERR, "seid not valid");
3517                 return -EINVAL;
3518         }
3519
3520         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3521         tc_bw_data.tc_valid_bits = enabled_tcmap;
3522         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3523                 tc_bw_data.tc_bw_credits[i] =
3524                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3525
3526         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3527         if (ret != I40E_SUCCESS) {
3528                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3529                 return ret;
3530         }
3531
3532         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3533                                         sizeof(vsi->info.qs_handle));
3534         return I40E_SUCCESS;
3535 }
3536
3537 static enum i40e_status_code
3538 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3539                                  struct i40e_aqc_vsi_properties_data *info,
3540                                  uint8_t enabled_tcmap)
3541 {
3542         enum i40e_status_code ret;
3543         int i, total_tc = 0;
3544         uint16_t qpnum_per_tc, bsf, qp_idx;
3545
3546         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3547         if (ret != I40E_SUCCESS)
3548                 return ret;
3549
3550         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3551                 if (enabled_tcmap & (1 << i))
3552                         total_tc++;
3553         vsi->enabled_tc = enabled_tcmap;
3554
3555         /* Number of queues per enabled TC */
3556         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3557         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3558         bsf = rte_bsf32(qpnum_per_tc);
3559
3560         /* Adjust the queue number to actual queues that can be applied */
3561         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3562                 vsi->nb_qps = qpnum_per_tc * total_tc;
3563
3564         /**
3565          * Configure TC and queue mapping parameters, for enabled TC,
3566          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3567          * default queue will serve it.
3568          */
3569         qp_idx = 0;
3570         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3571                 if (vsi->enabled_tc & (1 << i)) {
3572                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3573                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3574                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3575                         qp_idx += qpnum_per_tc;
3576                 } else
3577                         info->tc_mapping[i] = 0;
3578         }
3579
3580         /* Associate queue number with VSI */
3581         if (vsi->type == I40E_VSI_SRIOV) {
3582                 info->mapping_flags |=
3583                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3584                 for (i = 0; i < vsi->nb_qps; i++)
3585                         info->queue_mapping[i] =
3586                                 rte_cpu_to_le_16(vsi->base_queue + i);
3587         } else {
3588                 info->mapping_flags |=
3589                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3590                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3591         }
3592         info->valid_sections |=
3593                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3594
3595         return I40E_SUCCESS;
3596 }
3597
3598 static int
3599 i40e_veb_release(struct i40e_veb *veb)
3600 {
3601         struct i40e_vsi *vsi;
3602         struct i40e_hw *hw;
3603
3604         if (veb == NULL || veb->associate_vsi == NULL)
3605                 return -EINVAL;
3606
3607         if (!TAILQ_EMPTY(&veb->head)) {
3608                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3609                 return -EACCES;
3610         }
3611
3612         vsi = veb->associate_vsi;
3613         hw = I40E_VSI_TO_HW(vsi);
3614
3615         vsi->uplink_seid = veb->uplink_seid;
3616         i40e_aq_delete_element(hw, veb->seid, NULL);
3617         rte_free(veb);
3618         vsi->veb = NULL;
3619         return I40E_SUCCESS;
3620 }
3621
3622 /* Setup a veb */
3623 static struct i40e_veb *
3624 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3625 {
3626         struct i40e_veb *veb;
3627         int ret;
3628         struct i40e_hw *hw;
3629
3630         if (NULL == pf || vsi == NULL) {
3631                 PMD_DRV_LOG(ERR, "veb setup failed, "
3632                             "associated VSI shouldn't null");
3633                 return NULL;
3634         }
3635         hw = I40E_PF_TO_HW(pf);
3636
3637         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3638         if (!veb) {
3639                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3640                 goto fail;
3641         }
3642
3643         veb->associate_vsi = vsi;
3644         TAILQ_INIT(&veb->head);
3645         veb->uplink_seid = vsi->uplink_seid;
3646
3647         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3648                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3649
3650         if (ret != I40E_SUCCESS) {
3651                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3652                             hw->aq.asq_last_status);
3653                 goto fail;
3654         }
3655
3656         /* get statistics index */
3657         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3658                                 &veb->stats_idx, NULL, NULL, NULL);
3659         if (ret != I40E_SUCCESS) {
3660                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3661                             hw->aq.asq_last_status);
3662                 goto fail;
3663         }
3664
3665         /* Get VEB bandwidth, to be implemented */
3666         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3667         vsi->uplink_seid = veb->seid;
3668
3669         return veb;
3670 fail:
3671         rte_free(veb);
3672         return NULL;
3673 }
3674
3675 int
3676 i40e_vsi_release(struct i40e_vsi *vsi)
3677 {
3678         struct i40e_pf *pf;
3679         struct i40e_hw *hw;
3680         struct i40e_vsi_list *vsi_list;
3681         int ret;
3682         struct i40e_mac_filter *f;
3683
3684         if (!vsi)
3685                 return I40E_SUCCESS;
3686
3687         pf = I40E_VSI_TO_PF(vsi);
3688         hw = I40E_VSI_TO_HW(vsi);
3689
3690         /* VSI has child to attach, release child first */
3691         if (vsi->veb) {
3692                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3693                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3694                                 return -1;
3695                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3696                 }
3697                 i40e_veb_release(vsi->veb);
3698         }
3699
3700         /* Remove all macvlan filters of the VSI */
3701         i40e_vsi_remove_all_macvlan_filter(vsi);
3702         TAILQ_FOREACH(f, &vsi->mac_list, next)
3703                 rte_free(f);
3704
3705         if (vsi->type != I40E_VSI_MAIN) {
3706                 /* Remove vsi from parent's sibling list */
3707                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3708                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3709                         return I40E_ERR_PARAM;
3710                 }
3711                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3712                                 &vsi->sib_vsi_list, list);
3713
3714                 /* Remove all switch element of the VSI */
3715                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3716                 if (ret != I40E_SUCCESS)
3717                         PMD_DRV_LOG(ERR, "Failed to delete element");
3718         }
3719         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3720
3721         if (vsi->type != I40E_VSI_SRIOV)
3722                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3723         rte_free(vsi);
3724
3725         return I40E_SUCCESS;
3726 }
3727
3728 static int
3729 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3730 {
3731         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3732         struct i40e_aqc_remove_macvlan_element_data def_filter;
3733         struct i40e_mac_filter_info filter;
3734         int ret;
3735
3736         if (vsi->type != I40E_VSI_MAIN)
3737                 return I40E_ERR_CONFIG;
3738         memset(&def_filter, 0, sizeof(def_filter));
3739         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3740                                         ETH_ADDR_LEN);
3741         def_filter.vlan_tag = 0;
3742         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3743                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3744         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3745         if (ret != I40E_SUCCESS) {
3746                 struct i40e_mac_filter *f;
3747                 struct ether_addr *mac;
3748
3749                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3750                             "macvlan filter");
3751                 /* It needs to add the permanent mac into mac list */
3752                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3753                 if (f == NULL) {
3754                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3755                         return I40E_ERR_NO_MEMORY;
3756                 }
3757                 mac = &f->mac_info.mac_addr;
3758                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3759                                 ETH_ADDR_LEN);
3760                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3761                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3762                 vsi->mac_num++;
3763
3764                 return ret;
3765         }
3766         (void)rte_memcpy(&filter.mac_addr,
3767                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3768         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3769         return i40e_vsi_add_mac(vsi, &filter);
3770 }
3771
3772 static int
3773 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3774 {
3775         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3776         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3777         struct i40e_hw *hw = &vsi->adapter->hw;
3778         i40e_status ret;
3779         int i;
3780
3781         memset(&bw_config, 0, sizeof(bw_config));
3782         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3783         if (ret != I40E_SUCCESS) {
3784                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3785                             hw->aq.asq_last_status);
3786                 return ret;
3787         }
3788
3789         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3790         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3791                                         &ets_sla_config, NULL);
3792         if (ret != I40E_SUCCESS) {
3793                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3794                             "configuration %u", hw->aq.asq_last_status);
3795                 return ret;
3796         }
3797
3798         /* Not store the info yet, just print out */
3799         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3800         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3801         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3802                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3803                             ets_sla_config.share_credits[i]);
3804                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3805                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3806                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3807                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3808                             (i * 4));
3809         }
3810
3811         return 0;
3812 }
3813
3814 /* Setup a VSI */
3815 struct i40e_vsi *
3816 i40e_vsi_setup(struct i40e_pf *pf,
3817                enum i40e_vsi_type type,
3818                struct i40e_vsi *uplink_vsi,
3819                uint16_t user_param)
3820 {
3821         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3822         struct i40e_vsi *vsi;
3823         struct i40e_mac_filter_info filter;
3824         int ret;
3825         struct i40e_vsi_context ctxt;
3826         struct ether_addr broadcast =
3827                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3828
3829         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3830                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3831                             "VSI link shouldn't be NULL");
3832                 return NULL;
3833         }
3834
3835         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3836                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3837                             "uplink VSI should be NULL");
3838                 return NULL;
3839         }
3840
3841         /* If uplink vsi didn't setup VEB, create one first */
3842         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3843                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3844
3845                 if (NULL == uplink_vsi->veb) {
3846                         PMD_DRV_LOG(ERR, "VEB setup failed");
3847                         return NULL;
3848                 }
3849         }
3850
3851         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3852         if (!vsi) {
3853                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3854                 return NULL;
3855         }
3856         TAILQ_INIT(&vsi->mac_list);
3857         vsi->type = type;
3858         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3859         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3860         vsi->parent_vsi = uplink_vsi;
3861         vsi->user_param = user_param;
3862         /* Allocate queues */
3863         switch (vsi->type) {
3864         case I40E_VSI_MAIN  :
3865                 vsi->nb_qps = pf->lan_nb_qps;
3866                 break;
3867         case I40E_VSI_SRIOV :
3868                 vsi->nb_qps = pf->vf_nb_qps;
3869                 break;
3870         case I40E_VSI_VMDQ2:
3871                 vsi->nb_qps = pf->vmdq_nb_qps;
3872                 break;
3873         case I40E_VSI_FDIR:
3874                 vsi->nb_qps = pf->fdir_nb_qps;
3875                 break;
3876         default:
3877                 goto fail_mem;
3878         }
3879         /*
3880          * The filter status descriptor is reported in rx queue 0,
3881          * while the tx queue for fdir filter programming has no
3882          * such constraints, can be non-zero queues.
3883          * To simplify it, choose FDIR vsi use queue 0 pair.
3884          * To make sure it will use queue 0 pair, queue allocation
3885          * need be done before this function is called
3886          */
3887         if (type != I40E_VSI_FDIR) {
3888                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3889                         if (ret < 0) {
3890                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3891                                                 vsi->seid, ret);
3892                                 goto fail_mem;
3893                         }
3894                         vsi->base_queue = ret;
3895         } else
3896                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3897
3898         /* VF has MSIX interrupt in VF range, don't allocate here */
3899         if (type == I40E_VSI_MAIN) {
3900                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3901                                           RTE_MIN(vsi->nb_qps,
3902                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3903                 if (ret < 0) {
3904                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3905                                     vsi->seid, ret);
3906                         goto fail_queue_alloc;
3907                 }
3908                 vsi->msix_intr = ret;
3909                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3910         } else if (type != I40E_VSI_SRIOV) {
3911                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3912                 if (ret < 0) {
3913                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3914                         goto fail_queue_alloc;
3915                 }
3916                 vsi->msix_intr = ret;
3917                 vsi->nb_msix = 1;
3918         } else {
3919                 vsi->msix_intr = 0;
3920                 vsi->nb_msix = 0;
3921         }
3922
3923         /* Add VSI */
3924         if (type == I40E_VSI_MAIN) {
3925                 /* For main VSI, no need to add since it's default one */
3926                 vsi->uplink_seid = pf->mac_seid;
3927                 vsi->seid = pf->main_vsi_seid;
3928                 /* Bind queues with specific MSIX interrupt */
3929                 /**
3930                  * Needs 2 interrupt at least, one for misc cause which will
3931                  * enabled from OS side, Another for queues binding the
3932                  * interrupt from device side only.
3933                  */
3934
3935                 /* Get default VSI parameters from hardware */
3936                 memset(&ctxt, 0, sizeof(ctxt));
3937                 ctxt.seid = vsi->seid;
3938                 ctxt.pf_num = hw->pf_id;
3939                 ctxt.uplink_seid = vsi->uplink_seid;
3940                 ctxt.vf_num = 0;
3941                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3942                 if (ret != I40E_SUCCESS) {
3943                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3944                         goto fail_msix_alloc;
3945                 }
3946                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3947                         sizeof(struct i40e_aqc_vsi_properties_data));
3948                 vsi->vsi_id = ctxt.vsi_number;
3949                 vsi->info.valid_sections = 0;
3950
3951                 /* Configure tc, enabled TC0 only */
3952                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3953                         I40E_SUCCESS) {
3954                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3955                         goto fail_msix_alloc;
3956                 }
3957
3958                 /* TC, queue mapping */
3959                 memset(&ctxt, 0, sizeof(ctxt));
3960                 vsi->info.valid_sections |=
3961                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3962                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3963                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3964                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3965                         sizeof(struct i40e_aqc_vsi_properties_data));
3966                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3967                                                 I40E_DEFAULT_TCMAP);
3968                 if (ret != I40E_SUCCESS) {
3969                         PMD_DRV_LOG(ERR, "Failed to configure "
3970                                     "TC queue mapping");
3971                         goto fail_msix_alloc;
3972                 }
3973                 ctxt.seid = vsi->seid;
3974                 ctxt.pf_num = hw->pf_id;
3975                 ctxt.uplink_seid = vsi->uplink_seid;
3976                 ctxt.vf_num = 0;
3977
3978                 /* Update VSI parameters */
3979                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3980                 if (ret != I40E_SUCCESS) {
3981                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3982                         goto fail_msix_alloc;
3983                 }
3984
3985                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3986                                                 sizeof(vsi->info.tc_mapping));
3987                 (void)rte_memcpy(&vsi->info.queue_mapping,
3988                                 &ctxt.info.queue_mapping,
3989                         sizeof(vsi->info.queue_mapping));
3990                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3991                 vsi->info.valid_sections = 0;
3992
3993                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3994                                 ETH_ADDR_LEN);
3995
3996                 /**
3997                  * Updating default filter settings are necessary to prevent
3998                  * reception of tagged packets.
3999                  * Some old firmware configurations load a default macvlan
4000                  * filter which accepts both tagged and untagged packets.
4001                  * The updating is to use a normal filter instead if needed.
4002                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4003                  * The firmware with correct configurations load the default
4004                  * macvlan filter which is expected and cannot be removed.
4005                  */
4006                 i40e_update_default_filter_setting(vsi);
4007                 i40e_config_qinq(hw, vsi);
4008         } else if (type == I40E_VSI_SRIOV) {
4009                 memset(&ctxt, 0, sizeof(ctxt));
4010                 /**
4011                  * For other VSI, the uplink_seid equals to uplink VSI's
4012                  * uplink_seid since they share same VEB
4013                  */
4014                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4015                 ctxt.pf_num = hw->pf_id;
4016                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4017                 ctxt.uplink_seid = vsi->uplink_seid;
4018                 ctxt.connection_type = 0x1;
4019                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4020
4021                 /**
4022                  * Do not configure switch ID to enable VEB switch by
4023                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4024                  * if the source mac address of packet sent from VF is not
4025                  * listed in the VEB's mac table, the VEB will switch the
4026                  * packet back to the VF. Need to enable it when HW issue
4027                  * is fixed.
4028                  */
4029
4030                 /* Configure port/vlan */
4031                 ctxt.info.valid_sections |=
4032                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4033                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4034                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4035                                                 I40E_DEFAULT_TCMAP);
4036                 if (ret != I40E_SUCCESS) {
4037                         PMD_DRV_LOG(ERR, "Failed to configure "
4038                                     "TC queue mapping");
4039                         goto fail_msix_alloc;
4040                 }
4041                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4042                 ctxt.info.valid_sections |=
4043                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4044                 /**
4045                  * Since VSI is not created yet, only configure parameter,
4046                  * will add vsi below.
4047                  */
4048
4049                 i40e_config_qinq(hw, vsi);
4050         } else if (type == I40E_VSI_VMDQ2) {
4051                 memset(&ctxt, 0, sizeof(ctxt));
4052                 /*
4053                  * For other VSI, the uplink_seid equals to uplink VSI's
4054                  * uplink_seid since they share same VEB
4055                  */
4056                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4057                 ctxt.pf_num = hw->pf_id;
4058                 ctxt.vf_num = 0;
4059                 ctxt.uplink_seid = vsi->uplink_seid;
4060                 ctxt.connection_type = 0x1;
4061                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4062
4063                 ctxt.info.valid_sections |=
4064                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4065                 /* user_param carries flag to enable loop back */
4066                 if (user_param) {
4067                         ctxt.info.switch_id =
4068                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4069                         ctxt.info.switch_id |=
4070                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4071                 }
4072
4073                 /* Configure port/vlan */
4074                 ctxt.info.valid_sections |=
4075                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4076                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4077                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4078                                                 I40E_DEFAULT_TCMAP);
4079                 if (ret != I40E_SUCCESS) {
4080                         PMD_DRV_LOG(ERR, "Failed to configure "
4081                                         "TC queue mapping");
4082                         goto fail_msix_alloc;
4083                 }
4084                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4085                 ctxt.info.valid_sections |=
4086                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4087         } else if (type == I40E_VSI_FDIR) {
4088                 memset(&ctxt, 0, sizeof(ctxt));
4089                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4090                 ctxt.pf_num = hw->pf_id;
4091                 ctxt.vf_num = 0;
4092                 ctxt.uplink_seid = vsi->uplink_seid;
4093                 ctxt.connection_type = 0x1;     /* regular data port */
4094                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4095                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4096                                                 I40E_DEFAULT_TCMAP);
4097                 if (ret != I40E_SUCCESS) {
4098                         PMD_DRV_LOG(ERR, "Failed to configure "
4099                                         "TC queue mapping.");
4100                         goto fail_msix_alloc;
4101                 }
4102                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4103                 ctxt.info.valid_sections |=
4104                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4105         } else {
4106                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4107                 goto fail_msix_alloc;
4108         }
4109
4110         if (vsi->type != I40E_VSI_MAIN) {
4111                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4112                 if (ret != I40E_SUCCESS) {
4113                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4114                                     hw->aq.asq_last_status);
4115                         goto fail_msix_alloc;
4116                 }
4117                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4118                 vsi->info.valid_sections = 0;
4119                 vsi->seid = ctxt.seid;
4120                 vsi->vsi_id = ctxt.vsi_number;
4121                 vsi->sib_vsi_list.vsi = vsi;
4122                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4123                                 &vsi->sib_vsi_list, list);
4124         }
4125
4126         /* MAC/VLAN configuration */
4127         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4128         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4129
4130         ret = i40e_vsi_add_mac(vsi, &filter);
4131         if (ret != I40E_SUCCESS) {
4132                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4133                 goto fail_msix_alloc;
4134         }
4135
4136         /* Get VSI BW information */
4137         i40e_vsi_dump_bw_config(vsi);
4138         return vsi;
4139 fail_msix_alloc:
4140         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4141 fail_queue_alloc:
4142         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4143 fail_mem:
4144         rte_free(vsi);
4145         return NULL;
4146 }
4147
4148 /* Configure vlan stripping on or off */
4149 int
4150 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4151 {
4152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4153         struct i40e_vsi_context ctxt;
4154         uint8_t vlan_flags;
4155         int ret = I40E_SUCCESS;
4156
4157         /* Check if it has been already on or off */
4158         if (vsi->info.valid_sections &
4159                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4160                 if (on) {
4161                         if ((vsi->info.port_vlan_flags &
4162                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4163                                 return 0; /* already on */
4164                 } else {
4165                         if ((vsi->info.port_vlan_flags &
4166                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4167                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4168                                 return 0; /* already off */
4169                 }
4170         }
4171
4172         if (on)
4173                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4174         else
4175                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4176         vsi->info.valid_sections =
4177                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4178         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4179         vsi->info.port_vlan_flags |= vlan_flags;
4180         ctxt.seid = vsi->seid;
4181         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4182         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4183         if (ret)
4184                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4185                             on ? "enable" : "disable");
4186
4187         return ret;
4188 }
4189
4190 static int
4191 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4192 {
4193         struct rte_eth_dev_data *data = dev->data;
4194         int ret;
4195
4196         /* Apply vlan offload setting */
4197         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4198
4199         /* Apply double-vlan setting, not implemented yet */
4200
4201         /* Apply pvid setting */
4202         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4203                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4204         if (ret)
4205                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4206
4207         return ret;
4208 }
4209
4210 static int
4211 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4212 {
4213         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4214
4215         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4216 }
4217
4218 static int
4219 i40e_update_flow_control(struct i40e_hw *hw)
4220 {
4221 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4222         struct i40e_link_status link_status;
4223         uint32_t rxfc = 0, txfc = 0, reg;
4224         uint8_t an_info;
4225         int ret;
4226
4227         memset(&link_status, 0, sizeof(link_status));
4228         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4229         if (ret != I40E_SUCCESS) {
4230                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4231                 goto write_reg; /* Disable flow control */
4232         }
4233
4234         an_info = hw->phy.link_info.an_info;
4235         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4236                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4237                 ret = I40E_ERR_NOT_READY;
4238                 goto write_reg; /* Disable flow control */
4239         }
4240         /**
4241          * If link auto negotiation is enabled, flow control needs to
4242          * be configured according to it
4243          */
4244         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4245         case I40E_LINK_PAUSE_RXTX:
4246                 rxfc = 1;
4247                 txfc = 1;
4248                 hw->fc.current_mode = I40E_FC_FULL;
4249                 break;
4250         case I40E_AQ_LINK_PAUSE_RX:
4251                 rxfc = 1;
4252                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4253                 break;
4254         case I40E_AQ_LINK_PAUSE_TX:
4255                 txfc = 1;
4256                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4257                 break;
4258         default:
4259                 hw->fc.current_mode = I40E_FC_NONE;
4260                 break;
4261         }
4262
4263 write_reg:
4264         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4265                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4266         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4267         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4268         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4269         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4270
4271         return ret;
4272 }
4273
4274 /* PF setup */
4275 static int
4276 i40e_pf_setup(struct i40e_pf *pf)
4277 {
4278         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4279         struct i40e_filter_control_settings settings;
4280         struct i40e_vsi *vsi;
4281         int ret;
4282
4283         /* Clear all stats counters */
4284         pf->offset_loaded = FALSE;
4285         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4286         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4287
4288         ret = i40e_pf_get_switch_config(pf);
4289         if (ret != I40E_SUCCESS) {
4290                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4291                 return ret;
4292         }
4293         if (pf->flags & I40E_FLAG_FDIR) {
4294                 /* make queue allocated first, let FDIR use queue pair 0*/
4295                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4296                 if (ret != I40E_FDIR_QUEUE_ID) {
4297                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4298                                     " ret =%d", ret);
4299                         pf->flags &= ~I40E_FLAG_FDIR;
4300                 }
4301         }
4302         /*  main VSI setup */
4303         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4304         if (!vsi) {
4305                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4306                 return I40E_ERR_NOT_READY;
4307         }
4308         pf->main_vsi = vsi;
4309
4310         /* Configure filter control */
4311         memset(&settings, 0, sizeof(settings));
4312         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4313                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4314         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4315                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4316         else {
4317                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4318                                                 hw->func_caps.rss_table_size);
4319                 return I40E_ERR_PARAM;
4320         }
4321         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4322                         "size: %u\n", hw->func_caps.rss_table_size);
4323         pf->hash_lut_size = hw->func_caps.rss_table_size;
4324
4325         /* Enable ethtype and macvlan filters */
4326         settings.enable_ethtype = TRUE;
4327         settings.enable_macvlan = TRUE;
4328         ret = i40e_set_filter_control(hw, &settings);
4329         if (ret)
4330                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4331                                                                 ret);
4332
4333         /* Update flow control according to the auto negotiation */
4334         i40e_update_flow_control(hw);
4335
4336         return I40E_SUCCESS;
4337 }
4338
4339 int
4340 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4341 {
4342         uint32_t reg;
4343         uint16_t j;
4344
4345         /**
4346          * Set or clear TX Queue Disable flags,
4347          * which is required by hardware.
4348          */
4349         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4350         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4351
4352         /* Wait until the request is finished */
4353         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4354                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4355                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4356                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4357                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4358                                                         & 0x1))) {
4359                         break;
4360                 }
4361         }
4362         if (on) {
4363                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4364                         return I40E_SUCCESS; /* already on, skip next steps */
4365
4366                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4367                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4368         } else {
4369                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4370                         return I40E_SUCCESS; /* already off, skip next steps */
4371                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4372         }
4373         /* Write the register */
4374         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4375         /* Check the result */
4376         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4377                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4378                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4379                 if (on) {
4380                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4381                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4382                                 break;
4383                 } else {
4384                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4385                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4386                                 break;
4387                 }
4388         }
4389         /* Check if it is timeout */
4390         if (j >= I40E_CHK_Q_ENA_COUNT) {
4391                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4392                             (on ? "enable" : "disable"), q_idx);
4393                 return I40E_ERR_TIMEOUT;
4394         }
4395
4396         return I40E_SUCCESS;
4397 }
4398
4399 /* Swith on or off the tx queues */
4400 static int
4401 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4402 {
4403         struct rte_eth_dev_data *dev_data = pf->dev_data;
4404         struct i40e_tx_queue *txq;
4405         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4406         uint16_t i;
4407         int ret;
4408
4409         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4410                 txq = dev_data->tx_queues[i];
4411                 /* Don't operate the queue if not configured or
4412                  * if starting only per queue */
4413                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4414                         continue;
4415                 if (on)
4416                         ret = i40e_dev_tx_queue_start(dev, i);
4417                 else
4418                         ret = i40e_dev_tx_queue_stop(dev, i);
4419                 if ( ret != I40E_SUCCESS)
4420                         return ret;
4421         }
4422
4423         return I40E_SUCCESS;
4424 }
4425
4426 int
4427 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4428 {
4429         uint32_t reg;
4430         uint16_t j;
4431
4432         /* Wait until the request is finished */
4433         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4434                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4435                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4436                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4437                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4438                         break;
4439         }
4440
4441         if (on) {
4442                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4443                         return I40E_SUCCESS; /* Already on, skip next steps */
4444                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4445         } else {
4446                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4447                         return I40E_SUCCESS; /* Already off, skip next steps */
4448                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4449         }
4450
4451         /* Write the register */
4452         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4453         /* Check the result */
4454         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4455                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4456                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4457                 if (on) {
4458                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4459                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4460                                 break;
4461                 } else {
4462                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4463                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4464                                 break;
4465                 }
4466         }
4467
4468         /* Check if it is timeout */
4469         if (j >= I40E_CHK_Q_ENA_COUNT) {
4470                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4471                             (on ? "enable" : "disable"), q_idx);
4472                 return I40E_ERR_TIMEOUT;
4473         }
4474
4475         return I40E_SUCCESS;
4476 }
4477 /* Switch on or off the rx queues */
4478 static int
4479 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4480 {
4481         struct rte_eth_dev_data *dev_data = pf->dev_data;
4482         struct i40e_rx_queue *rxq;
4483         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4484         uint16_t i;
4485         int ret;
4486
4487         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4488                 rxq = dev_data->rx_queues[i];
4489                 /* Don't operate the queue if not configured or
4490                  * if starting only per queue */
4491                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4492                         continue;
4493                 if (on)
4494                         ret = i40e_dev_rx_queue_start(dev, i);
4495                 else
4496                         ret = i40e_dev_rx_queue_stop(dev, i);
4497                 if (ret != I40E_SUCCESS)
4498                         return ret;
4499         }
4500
4501         return I40E_SUCCESS;
4502 }
4503
4504 /* Switch on or off all the rx/tx queues */
4505 int
4506 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4507 {
4508         int ret;
4509
4510         if (on) {
4511                 /* enable rx queues before enabling tx queues */
4512                 ret = i40e_dev_switch_rx_queues(pf, on);
4513                 if (ret) {
4514                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4515                         return ret;
4516                 }
4517                 ret = i40e_dev_switch_tx_queues(pf, on);
4518         } else {
4519                 /* Stop tx queues before stopping rx queues */
4520                 ret = i40e_dev_switch_tx_queues(pf, on);
4521                 if (ret) {
4522                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4523                         return ret;
4524                 }
4525                 ret = i40e_dev_switch_rx_queues(pf, on);
4526         }
4527
4528         return ret;
4529 }
4530
4531 /* Initialize VSI for TX */
4532 static int
4533 i40e_dev_tx_init(struct i40e_pf *pf)
4534 {
4535         struct rte_eth_dev_data *data = pf->dev_data;
4536         uint16_t i;
4537         uint32_t ret = I40E_SUCCESS;
4538         struct i40e_tx_queue *txq;
4539
4540         for (i = 0; i < data->nb_tx_queues; i++) {
4541                 txq = data->tx_queues[i];
4542                 if (!txq || !txq->q_set)
4543                         continue;
4544                 ret = i40e_tx_queue_init(txq);
4545                 if (ret != I40E_SUCCESS)
4546                         break;
4547         }
4548         if (ret == I40E_SUCCESS)
4549                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4550                                      ->eth_dev);
4551
4552         return ret;
4553 }
4554
4555 /* Initialize VSI for RX */
4556 static int
4557 i40e_dev_rx_init(struct i40e_pf *pf)
4558 {
4559         struct rte_eth_dev_data *data = pf->dev_data;
4560         int ret = I40E_SUCCESS;
4561         uint16_t i;
4562         struct i40e_rx_queue *rxq;
4563
4564         i40e_pf_config_mq_rx(pf);
4565         for (i = 0; i < data->nb_rx_queues; i++) {
4566                 rxq = data->rx_queues[i];
4567                 if (!rxq || !rxq->q_set)
4568                         continue;
4569
4570                 ret = i40e_rx_queue_init(rxq);
4571                 if (ret != I40E_SUCCESS) {
4572                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4573                                     "initialization");
4574                         break;
4575                 }
4576         }
4577         if (ret == I40E_SUCCESS)
4578                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4579                                      ->eth_dev);
4580
4581         return ret;
4582 }
4583
4584 static int
4585 i40e_dev_rxtx_init(struct i40e_pf *pf)
4586 {
4587         int err;
4588
4589         err = i40e_dev_tx_init(pf);
4590         if (err) {
4591                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4592                 return err;
4593         }
4594         err = i40e_dev_rx_init(pf);
4595         if (err) {
4596                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4597                 return err;
4598         }
4599
4600         return err;
4601 }
4602
4603 static int
4604 i40e_vmdq_setup(struct rte_eth_dev *dev)
4605 {
4606         struct rte_eth_conf *conf = &dev->data->dev_conf;
4607         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4608         int i, err, conf_vsis, j, loop;
4609         struct i40e_vsi *vsi;
4610         struct i40e_vmdq_info *vmdq_info;
4611         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4612         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4613
4614         /*
4615          * Disable interrupt to avoid message from VF. Furthermore, it will
4616          * avoid race condition in VSI creation/destroy.
4617          */
4618         i40e_pf_disable_irq0(hw);
4619
4620         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4621                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4622                 return -ENOTSUP;
4623         }
4624
4625         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4626         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4627                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4628                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4629                         pf->max_nb_vmdq_vsi);
4630                 return -ENOTSUP;
4631         }
4632
4633         if (pf->vmdq != NULL) {
4634                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4635                 return 0;
4636         }
4637
4638         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4639                                 sizeof(*vmdq_info) * conf_vsis, 0);
4640
4641         if (pf->vmdq == NULL) {
4642                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4643                 return -ENOMEM;
4644         }
4645
4646         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4647
4648         /* Create VMDQ VSI */
4649         for (i = 0; i < conf_vsis; i++) {
4650                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4651                                 vmdq_conf->enable_loop_back);
4652                 if (vsi == NULL) {
4653                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4654                         err = -1;
4655                         goto err_vsi_setup;
4656                 }
4657                 vmdq_info = &pf->vmdq[i];
4658                 vmdq_info->pf = pf;
4659                 vmdq_info->vsi = vsi;
4660         }
4661         pf->nb_cfg_vmdq_vsi = conf_vsis;
4662
4663         /* Configure Vlan */
4664         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4665         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4666                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4667                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4668                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4669                                         vmdq_conf->pool_map[i].vlan_id, j);
4670
4671                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4672                                                 vmdq_conf->pool_map[i].vlan_id);
4673                                 if (err) {
4674                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4675                                         err = -1;
4676                                         goto err_vsi_setup;
4677                                 }
4678                         }
4679                 }
4680         }
4681
4682         i40e_pf_enable_irq0(hw);
4683
4684         return 0;
4685
4686 err_vsi_setup:
4687         for (i = 0; i < conf_vsis; i++)
4688                 if (pf->vmdq[i].vsi == NULL)
4689                         break;
4690                 else
4691                         i40e_vsi_release(pf->vmdq[i].vsi);
4692
4693         rte_free(pf->vmdq);
4694         pf->vmdq = NULL;
4695         i40e_pf_enable_irq0(hw);
4696         return err;
4697 }
4698
4699 static void
4700 i40e_stat_update_32(struct i40e_hw *hw,
4701                    uint32_t reg,
4702                    bool offset_loaded,
4703                    uint64_t *offset,
4704                    uint64_t *stat)
4705 {
4706         uint64_t new_data;
4707
4708         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4709         if (!offset_loaded)
4710                 *offset = new_data;
4711
4712         if (new_data >= *offset)
4713                 *stat = (uint64_t)(new_data - *offset);
4714         else
4715                 *stat = (uint64_t)((new_data +
4716                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4717 }
4718
4719 static void
4720 i40e_stat_update_48(struct i40e_hw *hw,
4721                    uint32_t hireg,
4722                    uint32_t loreg,
4723                    bool offset_loaded,
4724                    uint64_t *offset,
4725                    uint64_t *stat)
4726 {
4727         uint64_t new_data;
4728
4729         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4730         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4731                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4732
4733         if (!offset_loaded)
4734                 *offset = new_data;
4735
4736         if (new_data >= *offset)
4737                 *stat = new_data - *offset;
4738         else
4739                 *stat = (uint64_t)((new_data +
4740                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4741
4742         *stat &= I40E_48_BIT_MASK;
4743 }
4744
4745 /* Disable IRQ0 */
4746 void
4747 i40e_pf_disable_irq0(struct i40e_hw *hw)
4748 {
4749         /* Disable all interrupt types */
4750         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4751         I40E_WRITE_FLUSH(hw);
4752 }
4753
4754 /* Enable IRQ0 */
4755 void
4756 i40e_pf_enable_irq0(struct i40e_hw *hw)
4757 {
4758         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4759                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4760                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4761                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4762         I40E_WRITE_FLUSH(hw);
4763 }
4764
4765 static void
4766 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4767 {
4768         /* read pending request and disable first */
4769         i40e_pf_disable_irq0(hw);
4770         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4771         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4772                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4773
4774         if (no_queue)
4775                 /* Link no queues with irq0 */
4776                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4777                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4778 }
4779
4780 static void
4781 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4782 {
4783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4784         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4785         int i;
4786         uint16_t abs_vf_id;
4787         uint32_t index, offset, val;
4788
4789         if (!pf->vfs)
4790                 return;
4791         /**
4792          * Try to find which VF trigger a reset, use absolute VF id to access
4793          * since the reg is global register.
4794          */
4795         for (i = 0; i < pf->vf_num; i++) {
4796                 abs_vf_id = hw->func_caps.vf_base_id + i;
4797                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4798                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4799                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4800                 /* VFR event occured */
4801                 if (val & (0x1 << offset)) {
4802                         int ret;
4803
4804                         /* Clear the event first */
4805                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4806                                                         (0x1 << offset));
4807                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4808                         /**
4809                          * Only notify a VF reset event occured,
4810                          * don't trigger another SW reset
4811                          */
4812                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4813                         if (ret != I40E_SUCCESS)
4814                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4815                 }
4816         }
4817 }
4818
4819 static void
4820 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4821 {
4822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4823         struct i40e_arq_event_info info;
4824         uint16_t pending, opcode;
4825         int ret;
4826
4827         info.buf_len = I40E_AQ_BUF_SZ;
4828         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4829         if (!info.msg_buf) {
4830                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4831                 return;
4832         }
4833
4834         pending = 1;
4835         while (pending) {
4836                 ret = i40e_clean_arq_element(hw, &info, &pending);
4837
4838                 if (ret != I40E_SUCCESS) {
4839                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4840                                     "aq_err: %u", hw->aq.asq_last_status);
4841                         break;
4842                 }
4843                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4844
4845                 switch (opcode) {
4846                 case i40e_aqc_opc_send_msg_to_pf:
4847                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4848                         i40e_pf_host_handle_vf_msg(dev,
4849                                         rte_le_to_cpu_16(info.desc.retval),
4850                                         rte_le_to_cpu_32(info.desc.cookie_high),
4851                                         rte_le_to_cpu_32(info.desc.cookie_low),
4852                                         info.msg_buf,
4853                                         info.msg_len);
4854                         break;
4855                 default:
4856                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4857                                     opcode);
4858                         break;
4859                 }
4860         }
4861         rte_free(info.msg_buf);
4862 }
4863
4864 /*
4865  * Interrupt handler is registered as the alarm callback for handling LSC
4866  * interrupt in a definite of time, in order to wait the NIC into a stable
4867  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4868  * no need for link down interrupt.
4869  */
4870 static void
4871 i40e_dev_interrupt_delayed_handler(void *param)
4872 {
4873         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4875         uint32_t icr0;
4876
4877         /* read interrupt causes again */
4878         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4879
4880 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4881         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4882                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4883         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4884                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4885         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4886                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4887         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4888                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4889         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4890                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4891                                                                 "state\n");
4892         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4893                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4894         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4895                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4896 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4897
4898         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4899                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4900                 i40e_dev_handle_vfr_event(dev);
4901         }
4902         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4903                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4904                 i40e_dev_handle_aq_msg(dev);
4905         }
4906
4907         /* handle the link up interrupt in an alarm callback */
4908         i40e_dev_link_update(dev, 0);
4909         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4910
4911         i40e_pf_enable_irq0(hw);
4912         rte_intr_enable(&(dev->pci_dev->intr_handle));
4913 }
4914
4915 /**
4916  * Interrupt handler triggered by NIC  for handling
4917  * specific interrupt.
4918  *
4919  * @param handle
4920  *  Pointer to interrupt handle.
4921  * @param param
4922  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4923  *
4924  * @return
4925  *  void
4926  */
4927 static void
4928 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4929                            void *param)
4930 {
4931         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4933         uint32_t icr0;
4934
4935         /* Disable interrupt */
4936         i40e_pf_disable_irq0(hw);
4937
4938         /* read out interrupt causes */
4939         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4940
4941         /* No interrupt event indicated */
4942         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4943                 PMD_DRV_LOG(INFO, "No interrupt event");
4944                 goto done;
4945         }
4946 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4947         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4948                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4949         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4950                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4951         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4952                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4953         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4954                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4955         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4956                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4957         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4958                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4959         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4960                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4961 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4962
4963         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4964                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4965                 i40e_dev_handle_vfr_event(dev);
4966         }
4967         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4968                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4969                 i40e_dev_handle_aq_msg(dev);
4970         }
4971
4972         /* Link Status Change interrupt */
4973         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4974 #define I40E_US_PER_SECOND 1000000
4975                 struct rte_eth_link link;
4976
4977                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4978                 memset(&link, 0, sizeof(link));
4979                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4980                 i40e_dev_link_update(dev, 0);
4981
4982                 /*
4983                  * For link up interrupt, it needs to wait 1 second to let the
4984                  * hardware be a stable state. Otherwise several consecutive
4985                  * interrupts can be observed.
4986                  * For link down interrupt, no need to wait.
4987                  */
4988                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4989                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4990                         return;
4991                 else
4992                         _rte_eth_dev_callback_process(dev,
4993                                 RTE_ETH_EVENT_INTR_LSC);
4994         }
4995
4996 done:
4997         /* Enable interrupt */
4998         i40e_pf_enable_irq0(hw);
4999         rte_intr_enable(&(dev->pci_dev->intr_handle));
5000 }
5001
5002 static int
5003 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5004                          struct i40e_macvlan_filter *filter,
5005                          int total)
5006 {
5007         int ele_num, ele_buff_size;
5008         int num, actual_num, i;
5009         uint16_t flags;
5010         int ret = I40E_SUCCESS;
5011         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5012         struct i40e_aqc_add_macvlan_element_data *req_list;
5013
5014         if (filter == NULL  || total == 0)
5015                 return I40E_ERR_PARAM;
5016         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5017         ele_buff_size = hw->aq.asq_buf_size;
5018
5019         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5020         if (req_list == NULL) {
5021                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5022                 return I40E_ERR_NO_MEMORY;
5023         }
5024
5025         num = 0;
5026         do {
5027                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5028                 memset(req_list, 0, ele_buff_size);
5029
5030                 for (i = 0; i < actual_num; i++) {
5031                         (void)rte_memcpy(req_list[i].mac_addr,
5032                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5033                         req_list[i].vlan_tag =
5034                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5035
5036                         switch (filter[num + i].filter_type) {
5037                         case RTE_MAC_PERFECT_MATCH:
5038                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5039                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5040                                 break;
5041                         case RTE_MACVLAN_PERFECT_MATCH:
5042                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5043                                 break;
5044                         case RTE_MAC_HASH_MATCH:
5045                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5046                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5047                                 break;
5048                         case RTE_MACVLAN_HASH_MATCH:
5049                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5050                                 break;
5051                         default:
5052                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5053                                 ret = I40E_ERR_PARAM;
5054                                 goto DONE;
5055                         }
5056
5057                         req_list[i].queue_number = 0;
5058
5059                         req_list[i].flags = rte_cpu_to_le_16(flags);
5060                 }
5061
5062                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5063                                                 actual_num, NULL);
5064                 if (ret != I40E_SUCCESS) {
5065                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5066                         goto DONE;
5067                 }
5068                 num += actual_num;
5069         } while (num < total);
5070
5071 DONE:
5072         rte_free(req_list);
5073         return ret;
5074 }
5075
5076 static int
5077 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5078                             struct i40e_macvlan_filter *filter,
5079                             int total)
5080 {
5081         int ele_num, ele_buff_size;
5082         int num, actual_num, i;
5083         uint16_t flags;
5084         int ret = I40E_SUCCESS;
5085         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5086         struct i40e_aqc_remove_macvlan_element_data *req_list;
5087
5088         if (filter == NULL  || total == 0)
5089                 return I40E_ERR_PARAM;
5090
5091         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5092         ele_buff_size = hw->aq.asq_buf_size;
5093
5094         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5095         if (req_list == NULL) {
5096                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5097                 return I40E_ERR_NO_MEMORY;
5098         }
5099
5100         num = 0;
5101         do {
5102                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5103                 memset(req_list, 0, ele_buff_size);
5104
5105                 for (i = 0; i < actual_num; i++) {
5106                         (void)rte_memcpy(req_list[i].mac_addr,
5107                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5108                         req_list[i].vlan_tag =
5109                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5110
5111                         switch (filter[num + i].filter_type) {
5112                         case RTE_MAC_PERFECT_MATCH:
5113                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5114                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5115                                 break;
5116                         case RTE_MACVLAN_PERFECT_MATCH:
5117                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5118                                 break;
5119                         case RTE_MAC_HASH_MATCH:
5120                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5121                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5122                                 break;
5123                         case RTE_MACVLAN_HASH_MATCH:
5124                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5125                                 break;
5126                         default:
5127                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5128                                 ret = I40E_ERR_PARAM;
5129                                 goto DONE;
5130                         }
5131                         req_list[i].flags = rte_cpu_to_le_16(flags);
5132                 }
5133
5134                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5135                                                 actual_num, NULL);
5136                 if (ret != I40E_SUCCESS) {
5137                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5138                         goto DONE;
5139                 }
5140                 num += actual_num;
5141         } while (num < total);
5142
5143 DONE:
5144         rte_free(req_list);
5145         return ret;
5146 }
5147
5148 /* Find out specific MAC filter */
5149 static struct i40e_mac_filter *
5150 i40e_find_mac_filter(struct i40e_vsi *vsi,
5151                          struct ether_addr *macaddr)
5152 {
5153         struct i40e_mac_filter *f;
5154
5155         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5156                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5157                         return f;
5158         }
5159
5160         return NULL;
5161 }
5162
5163 static bool
5164 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5165                          uint16_t vlan_id)
5166 {
5167         uint32_t vid_idx, vid_bit;
5168
5169         if (vlan_id > ETH_VLAN_ID_MAX)
5170                 return 0;
5171
5172         vid_idx = I40E_VFTA_IDX(vlan_id);
5173         vid_bit = I40E_VFTA_BIT(vlan_id);
5174
5175         if (vsi->vfta[vid_idx] & vid_bit)
5176                 return 1;
5177         else
5178                 return 0;
5179 }
5180
5181 static void
5182 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5183                          uint16_t vlan_id, bool on)
5184 {
5185         uint32_t vid_idx, vid_bit;
5186
5187         if (vlan_id > ETH_VLAN_ID_MAX)
5188                 return;
5189
5190         vid_idx = I40E_VFTA_IDX(vlan_id);
5191         vid_bit = I40E_VFTA_BIT(vlan_id);
5192
5193         if (on)
5194                 vsi->vfta[vid_idx] |= vid_bit;
5195         else
5196                 vsi->vfta[vid_idx] &= ~vid_bit;
5197 }
5198
5199 /**
5200  * Find all vlan options for specific mac addr,
5201  * return with actual vlan found.
5202  */
5203 static inline int
5204 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5205                            struct i40e_macvlan_filter *mv_f,
5206                            int num, struct ether_addr *addr)
5207 {
5208         int i;
5209         uint32_t j, k;
5210
5211         /**
5212          * Not to use i40e_find_vlan_filter to decrease the loop time,
5213          * although the code looks complex.
5214           */
5215         if (num < vsi->vlan_num)
5216                 return I40E_ERR_PARAM;
5217
5218         i = 0;
5219         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5220                 if (vsi->vfta[j]) {
5221                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5222                                 if (vsi->vfta[j] & (1 << k)) {
5223                                         if (i > num - 1) {
5224                                                 PMD_DRV_LOG(ERR, "vlan number "
5225                                                             "not match");
5226                                                 return I40E_ERR_PARAM;
5227                                         }
5228                                         (void)rte_memcpy(&mv_f[i].macaddr,
5229                                                         addr, ETH_ADDR_LEN);
5230                                         mv_f[i].vlan_id =
5231                                                 j * I40E_UINT32_BIT_SIZE + k;
5232                                         i++;
5233                                 }
5234                         }
5235                 }
5236         }
5237         return I40E_SUCCESS;
5238 }
5239
5240 static inline int
5241 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5242                            struct i40e_macvlan_filter *mv_f,
5243                            int num,
5244                            uint16_t vlan)
5245 {
5246         int i = 0;
5247         struct i40e_mac_filter *f;
5248
5249         if (num < vsi->mac_num)
5250                 return I40E_ERR_PARAM;
5251
5252         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5253                 if (i > num - 1) {
5254                         PMD_DRV_LOG(ERR, "buffer number not match");
5255                         return I40E_ERR_PARAM;
5256                 }
5257                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5258                                 ETH_ADDR_LEN);
5259                 mv_f[i].vlan_id = vlan;
5260                 mv_f[i].filter_type = f->mac_info.filter_type;
5261                 i++;
5262         }
5263
5264         return I40E_SUCCESS;
5265 }
5266
5267 static int
5268 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5269 {
5270         int i, num;
5271         struct i40e_mac_filter *f;
5272         struct i40e_macvlan_filter *mv_f;
5273         int ret = I40E_SUCCESS;
5274
5275         if (vsi == NULL || vsi->mac_num == 0)
5276                 return I40E_ERR_PARAM;
5277
5278         /* Case that no vlan is set */
5279         if (vsi->vlan_num == 0)
5280                 num = vsi->mac_num;
5281         else
5282                 num = vsi->mac_num * vsi->vlan_num;
5283
5284         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5285         if (mv_f == NULL) {
5286                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5287                 return I40E_ERR_NO_MEMORY;
5288         }
5289
5290         i = 0;
5291         if (vsi->vlan_num == 0) {
5292                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5293                         (void)rte_memcpy(&mv_f[i].macaddr,
5294                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5295                         mv_f[i].vlan_id = 0;
5296                         i++;
5297                 }
5298         } else {
5299                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5300                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5301                                         vsi->vlan_num, &f->mac_info.mac_addr);
5302                         if (ret != I40E_SUCCESS)
5303                                 goto DONE;
5304                         i += vsi->vlan_num;
5305                 }
5306         }
5307
5308         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5309 DONE:
5310         rte_free(mv_f);
5311
5312         return ret;
5313 }
5314
5315 int
5316 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5317 {
5318         struct i40e_macvlan_filter *mv_f;
5319         int mac_num;
5320         int ret = I40E_SUCCESS;
5321
5322         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5323                 return I40E_ERR_PARAM;
5324
5325         /* If it's already set, just return */
5326         if (i40e_find_vlan_filter(vsi,vlan))
5327                 return I40E_SUCCESS;
5328
5329         mac_num = vsi->mac_num;
5330
5331         if (mac_num == 0) {
5332                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5333                 return I40E_ERR_PARAM;
5334         }
5335
5336         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5337
5338         if (mv_f == NULL) {
5339                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5340                 return I40E_ERR_NO_MEMORY;
5341         }
5342
5343         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5344
5345         if (ret != I40E_SUCCESS)
5346                 goto DONE;
5347
5348         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5349
5350         if (ret != I40E_SUCCESS)
5351                 goto DONE;
5352
5353         i40e_set_vlan_filter(vsi, vlan, 1);
5354
5355         vsi->vlan_num++;
5356         ret = I40E_SUCCESS;
5357 DONE:
5358         rte_free(mv_f);
5359         return ret;
5360 }
5361
5362 int
5363 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5364 {
5365         struct i40e_macvlan_filter *mv_f;
5366         int mac_num;
5367         int ret = I40E_SUCCESS;
5368
5369         /**
5370          * Vlan 0 is the generic filter for untagged packets
5371          * and can't be removed.
5372          */
5373         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5374                 return I40E_ERR_PARAM;
5375
5376         /* If can't find it, just return */
5377         if (!i40e_find_vlan_filter(vsi, vlan))
5378                 return I40E_ERR_PARAM;
5379
5380         mac_num = vsi->mac_num;
5381
5382         if (mac_num == 0) {
5383                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5384                 return I40E_ERR_PARAM;
5385         }
5386
5387         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5388
5389         if (mv_f == NULL) {
5390                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5391                 return I40E_ERR_NO_MEMORY;
5392         }
5393
5394         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5395
5396         if (ret != I40E_SUCCESS)
5397                 goto DONE;
5398
5399         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5400
5401         if (ret != I40E_SUCCESS)
5402                 goto DONE;
5403
5404         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5405         if (vsi->vlan_num == 1) {
5406                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5407                 if (ret != I40E_SUCCESS)
5408                         goto DONE;
5409
5410                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5411                 if (ret != I40E_SUCCESS)
5412                         goto DONE;
5413         }
5414
5415         i40e_set_vlan_filter(vsi, vlan, 0);
5416
5417         vsi->vlan_num--;
5418         ret = I40E_SUCCESS;
5419 DONE:
5420         rte_free(mv_f);
5421         return ret;
5422 }
5423
5424 int
5425 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5426 {
5427         struct i40e_mac_filter *f;
5428         struct i40e_macvlan_filter *mv_f;
5429         int i, vlan_num = 0;
5430         int ret = I40E_SUCCESS;
5431
5432         /* If it's add and we've config it, return */
5433         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5434         if (f != NULL)
5435                 return I40E_SUCCESS;
5436         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5437                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5438
5439                 /**
5440                  * If vlan_num is 0, that's the first time to add mac,
5441                  * set mask for vlan_id 0.
5442                  */
5443                 if (vsi->vlan_num == 0) {
5444                         i40e_set_vlan_filter(vsi, 0, 1);
5445                         vsi->vlan_num = 1;
5446                 }
5447                 vlan_num = vsi->vlan_num;
5448         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5449                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5450                 vlan_num = 1;
5451
5452         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5453         if (mv_f == NULL) {
5454                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5455                 return I40E_ERR_NO_MEMORY;
5456         }
5457
5458         for (i = 0; i < vlan_num; i++) {
5459                 mv_f[i].filter_type = mac_filter->filter_type;
5460                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5461                                 ETH_ADDR_LEN);
5462         }
5463
5464         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5465                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5466                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5467                                         &mac_filter->mac_addr);
5468                 if (ret != I40E_SUCCESS)
5469                         goto DONE;
5470         }
5471
5472         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5473         if (ret != I40E_SUCCESS)
5474                 goto DONE;
5475
5476         /* Add the mac addr into mac list */
5477         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5478         if (f == NULL) {
5479                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5480                 ret = I40E_ERR_NO_MEMORY;
5481                 goto DONE;
5482         }
5483         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5484                         ETH_ADDR_LEN);
5485         f->mac_info.filter_type = mac_filter->filter_type;
5486         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5487         vsi->mac_num++;
5488
5489         ret = I40E_SUCCESS;
5490 DONE:
5491         rte_free(mv_f);
5492
5493         return ret;
5494 }
5495
5496 int
5497 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5498 {
5499         struct i40e_mac_filter *f;
5500         struct i40e_macvlan_filter *mv_f;
5501         int i, vlan_num;
5502         enum rte_mac_filter_type filter_type;
5503         int ret = I40E_SUCCESS;
5504
5505         /* Can't find it, return an error */
5506         f = i40e_find_mac_filter(vsi, addr);
5507         if (f == NULL)
5508                 return I40E_ERR_PARAM;
5509
5510         vlan_num = vsi->vlan_num;
5511         filter_type = f->mac_info.filter_type;
5512         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5513                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5514                 if (vlan_num == 0) {
5515                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5516                         return I40E_ERR_PARAM;
5517                 }
5518         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5519                         filter_type == RTE_MAC_HASH_MATCH)
5520                 vlan_num = 1;
5521
5522         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5523         if (mv_f == NULL) {
5524                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5525                 return I40E_ERR_NO_MEMORY;
5526         }
5527
5528         for (i = 0; i < vlan_num; i++) {
5529                 mv_f[i].filter_type = filter_type;
5530                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5531                                 ETH_ADDR_LEN);
5532         }
5533         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5534                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5535                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5536                 if (ret != I40E_SUCCESS)
5537                         goto DONE;
5538         }
5539
5540         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5541         if (ret != I40E_SUCCESS)
5542                 goto DONE;
5543
5544         /* Remove the mac addr into mac list */
5545         TAILQ_REMOVE(&vsi->mac_list, f, next);
5546         rte_free(f);
5547         vsi->mac_num--;
5548
5549         ret = I40E_SUCCESS;
5550 DONE:
5551         rte_free(mv_f);
5552         return ret;
5553 }
5554
5555 /* Configure hash enable flags for RSS */
5556 uint64_t
5557 i40e_config_hena(uint64_t flags)
5558 {
5559         uint64_t hena = 0;
5560
5561         if (!flags)
5562                 return hena;
5563
5564         if (flags & ETH_RSS_FRAG_IPV4)
5565                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5566         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5567                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5568         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5569                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5570         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5571                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5572         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5573                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5574         if (flags & ETH_RSS_FRAG_IPV6)
5575                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5576         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5577                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5578         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5579                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5580         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5581                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5582         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5583                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5584         if (flags & ETH_RSS_L2_PAYLOAD)
5585                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5586
5587         return hena;
5588 }
5589
5590 /* Parse the hash enable flags */
5591 uint64_t
5592 i40e_parse_hena(uint64_t flags)
5593 {
5594         uint64_t rss_hf = 0;
5595
5596         if (!flags)
5597                 return rss_hf;
5598         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5599                 rss_hf |= ETH_RSS_FRAG_IPV4;
5600         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5601                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5602         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5603                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5604         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5605                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5606         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5607                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5608         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5609                 rss_hf |= ETH_RSS_FRAG_IPV6;
5610         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5611                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5612         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5613                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5614         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5615                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5616         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5617                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5618         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5619                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5620
5621         return rss_hf;
5622 }
5623
5624 /* Disable RSS */
5625 static void
5626 i40e_pf_disable_rss(struct i40e_pf *pf)
5627 {
5628         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5629         uint64_t hena;
5630
5631         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5632         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5633         hena &= ~I40E_RSS_HENA_ALL;
5634         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5635         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5636         I40E_WRITE_FLUSH(hw);
5637 }
5638
5639 static int
5640 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5641 {
5642         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5643         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5644         int ret = 0;
5645
5646         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5647                 sizeof(uint32_t)))
5648                 return -EINVAL;
5649
5650         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5651                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5652                         (struct i40e_aqc_get_set_rss_key_data *)key;
5653
5654                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5655                 if (ret)
5656                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5657                                      "via AQ");
5658         } else {
5659                 uint32_t *hash_key = (uint32_t *)key;
5660                 uint16_t i;
5661
5662                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5663                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5664                 I40E_WRITE_FLUSH(hw);
5665         }
5666
5667         return ret;
5668 }
5669
5670 static int
5671 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5672 {
5673         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5674         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5675         int ret;
5676
5677         if (!key || !key_len)
5678                 return -EINVAL;
5679
5680         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5681                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5682                         (struct i40e_aqc_get_set_rss_key_data *)key);
5683                 if (ret) {
5684                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5685                         return ret;
5686                 }
5687         } else {
5688                 uint32_t *key_dw = (uint32_t *)key;
5689                 uint16_t i;
5690
5691                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5692                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5693         }
5694         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5695
5696         return 0;
5697 }
5698
5699 static int
5700 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5701 {
5702         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5703         uint64_t rss_hf;
5704         uint64_t hena;
5705         int ret;
5706
5707         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5708                                rss_conf->rss_key_len);
5709         if (ret)
5710                 return ret;
5711
5712         rss_hf = rss_conf->rss_hf;
5713         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5714         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5715         hena &= ~I40E_RSS_HENA_ALL;
5716         hena |= i40e_config_hena(rss_hf);
5717         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5718         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5719         I40E_WRITE_FLUSH(hw);
5720
5721         return 0;
5722 }
5723
5724 static int
5725 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5726                          struct rte_eth_rss_conf *rss_conf)
5727 {
5728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5729         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5730         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5731         uint64_t hena;
5732
5733         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5734         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5735         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5736                 if (rss_hf != 0) /* Enable RSS */
5737                         return -EINVAL;
5738                 return 0; /* Nothing to do */
5739         }
5740         /* RSS enabled */
5741         if (rss_hf == 0) /* Disable RSS */
5742                 return -EINVAL;
5743
5744         return i40e_hw_rss_hash_set(pf, rss_conf);
5745 }
5746
5747 static int
5748 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5749                            struct rte_eth_rss_conf *rss_conf)
5750 {
5751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5753         uint64_t hena;
5754
5755         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5756                          &rss_conf->rss_key_len);
5757
5758         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5759         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5760         rss_conf->rss_hf = i40e_parse_hena(hena);
5761
5762         return 0;
5763 }
5764
5765 static int
5766 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5767 {
5768         switch (filter_type) {
5769         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5770                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5771                 break;
5772         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5773                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5774                 break;
5775         case RTE_TUNNEL_FILTER_IMAC_TENID:
5776                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5777                 break;
5778         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5779                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5780                 break;
5781         case ETH_TUNNEL_FILTER_IMAC:
5782                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5783                 break;
5784         default:
5785                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5786                 return -EINVAL;
5787         }
5788
5789         return 0;
5790 }
5791
5792 static int
5793 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5794                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5795                         uint8_t add)
5796 {
5797         uint16_t ip_type;
5798         uint8_t tun_type = 0;
5799         int val, ret = 0;
5800         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5801         struct i40e_vsi *vsi = pf->main_vsi;
5802         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5803         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5804
5805         cld_filter = rte_zmalloc("tunnel_filter",
5806                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5807                 0);
5808
5809         if (NULL == cld_filter) {
5810                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5811                 return -EINVAL;
5812         }
5813         pfilter = cld_filter;
5814
5815         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5816                         sizeof(struct ether_addr));
5817         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5818                         sizeof(struct ether_addr));
5819
5820         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5821         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5822                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5823                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5824                                 &tunnel_filter->ip_addr,
5825                                 sizeof(pfilter->ipaddr.v4.data));
5826         } else {
5827                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5828                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5829                                 &tunnel_filter->ip_addr,
5830                                 sizeof(pfilter->ipaddr.v6.data));
5831         }
5832
5833         /* check tunneled type */
5834         switch (tunnel_filter->tunnel_type) {
5835         case RTE_TUNNEL_TYPE_VXLAN:
5836                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5837                 break;
5838         case RTE_TUNNEL_TYPE_NVGRE:
5839                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5840                 break;
5841         default:
5842                 /* Other tunnel types is not supported. */
5843                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5844                 rte_free(cld_filter);
5845                 return -EINVAL;
5846         }
5847
5848         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5849                                                 &pfilter->flags);
5850         if (val < 0) {
5851                 rte_free(cld_filter);
5852                 return -EINVAL;
5853         }
5854
5855         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5856                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5857         pfilter->tenant_id = tunnel_filter->tenant_id;
5858         pfilter->queue_number = tunnel_filter->queue_id;
5859
5860         if (add)
5861                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5862         else
5863                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5864                                                 cld_filter, 1);
5865
5866         rte_free(cld_filter);
5867         return ret;
5868 }
5869
5870 static int
5871 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5872 {
5873         uint8_t i;
5874
5875         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5876                 if (pf->vxlan_ports[i] == port)
5877                         return i;
5878         }
5879
5880         return -1;
5881 }
5882
5883 static int
5884 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5885 {
5886         int  idx, ret;
5887         uint8_t filter_idx;
5888         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5889
5890         idx = i40e_get_vxlan_port_idx(pf, port);
5891
5892         /* Check if port already exists */
5893         if (idx >= 0) {
5894                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5895                 return -EINVAL;
5896         }
5897
5898         /* Now check if there is space to add the new port */
5899         idx = i40e_get_vxlan_port_idx(pf, 0);
5900         if (idx < 0) {
5901                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5902                         "not adding port %d", port);
5903                 return -ENOSPC;
5904         }
5905
5906         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5907                                         &filter_idx, NULL);
5908         if (ret < 0) {
5909                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5910                 return -1;
5911         }
5912
5913         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5914                          port,  filter_idx);
5915
5916         /* New port: add it and mark its index in the bitmap */
5917         pf->vxlan_ports[idx] = port;
5918         pf->vxlan_bitmap |= (1 << idx);
5919
5920         if (!(pf->flags & I40E_FLAG_VXLAN))
5921                 pf->flags |= I40E_FLAG_VXLAN;
5922
5923         return 0;
5924 }
5925
5926 static int
5927 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5928 {
5929         int idx;
5930         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5931
5932         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5933                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5934                 return -EINVAL;
5935         }
5936
5937         idx = i40e_get_vxlan_port_idx(pf, port);
5938
5939         if (idx < 0) {
5940                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5941                 return -EINVAL;
5942         }
5943
5944         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5945                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5946                 return -1;
5947         }
5948
5949         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5950                         port, idx);
5951
5952         pf->vxlan_ports[idx] = 0;
5953         pf->vxlan_bitmap &= ~(1 << idx);
5954
5955         if (!pf->vxlan_bitmap)
5956                 pf->flags &= ~I40E_FLAG_VXLAN;
5957
5958         return 0;
5959 }
5960
5961 /* Add UDP tunneling port */
5962 static int
5963 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5964                         struct rte_eth_udp_tunnel *udp_tunnel)
5965 {
5966         int ret = 0;
5967         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5968
5969         if (udp_tunnel == NULL)
5970                 return -EINVAL;
5971
5972         switch (udp_tunnel->prot_type) {
5973         case RTE_TUNNEL_TYPE_VXLAN:
5974                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5975                 break;
5976
5977         case RTE_TUNNEL_TYPE_GENEVE:
5978         case RTE_TUNNEL_TYPE_TEREDO:
5979                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5980                 ret = -1;
5981                 break;
5982
5983         default:
5984                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5985                 ret = -1;
5986                 break;
5987         }
5988
5989         return ret;
5990 }
5991
5992 /* Remove UDP tunneling port */
5993 static int
5994 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5995                         struct rte_eth_udp_tunnel *udp_tunnel)
5996 {
5997         int ret = 0;
5998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5999
6000         if (udp_tunnel == NULL)
6001                 return -EINVAL;
6002
6003         switch (udp_tunnel->prot_type) {
6004         case RTE_TUNNEL_TYPE_VXLAN:
6005                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6006                 break;
6007         case RTE_TUNNEL_TYPE_GENEVE:
6008         case RTE_TUNNEL_TYPE_TEREDO:
6009                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6010                 ret = -1;
6011                 break;
6012         default:
6013                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6014                 ret = -1;
6015                 break;
6016         }
6017
6018         return ret;
6019 }
6020
6021 /* Calculate the maximum number of contiguous PF queues that are configured */
6022 static int
6023 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6024 {
6025         struct rte_eth_dev_data *data = pf->dev_data;
6026         int i, num;
6027         struct i40e_rx_queue *rxq;
6028
6029         num = 0;
6030         for (i = 0; i < pf->lan_nb_qps; i++) {
6031                 rxq = data->rx_queues[i];
6032                 if (rxq && rxq->q_set)
6033                         num++;
6034                 else
6035                         break;
6036         }
6037
6038         return num;
6039 }
6040
6041 /* Configure RSS */
6042 static int
6043 i40e_pf_config_rss(struct i40e_pf *pf)
6044 {
6045         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6046         struct rte_eth_rss_conf rss_conf;
6047         uint32_t i, lut = 0;
6048         uint16_t j, num;
6049
6050         /*
6051          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6052          * It's necessary to calulate the actual PF queues that are configured.
6053          */
6054         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6055                 num = i40e_pf_calc_configured_queues_num(pf);
6056         else
6057                 num = pf->dev_data->nb_rx_queues;
6058
6059         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6060         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6061                         num);
6062
6063         if (num == 0) {
6064                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6065                 return -ENOTSUP;
6066         }
6067
6068         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6069                 if (j == num)
6070                         j = 0;
6071                 lut = (lut << 8) | (j & ((0x1 <<
6072                         hw->func_caps.rss_table_entry_width) - 1));
6073                 if ((i & 3) == 3)
6074                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6075         }
6076
6077         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6078         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6079                 i40e_pf_disable_rss(pf);
6080                 return 0;
6081         }
6082         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6083                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6084                 /* Random default keys */
6085                 static uint32_t rss_key_default[] = {0x6b793944,
6086                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6087                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6088                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6089
6090                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6091                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6092                                                         sizeof(uint32_t);
6093         }
6094
6095         return i40e_hw_rss_hash_set(pf, &rss_conf);
6096 }
6097
6098 static int
6099 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6100                                struct rte_eth_tunnel_filter_conf *filter)
6101 {
6102         if (pf == NULL || filter == NULL) {
6103                 PMD_DRV_LOG(ERR, "Invalid parameter");
6104                 return -EINVAL;
6105         }
6106
6107         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6108                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6109                 return -EINVAL;
6110         }
6111
6112         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6113                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6114                 return -EINVAL;
6115         }
6116
6117         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6118                 (is_zero_ether_addr(filter->outer_mac))) {
6119                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6120                 return -EINVAL;
6121         }
6122
6123         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6124                 (is_zero_ether_addr(filter->inner_mac))) {
6125                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6126                 return -EINVAL;
6127         }
6128
6129         return 0;
6130 }
6131
6132 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6133 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6134 static int
6135 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6136 {
6137         uint32_t val, reg;
6138         int ret = -EINVAL;
6139
6140         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6141         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6142
6143         if (len == 3) {
6144                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6145         } else if (len == 4) {
6146                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6147         } else {
6148                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6149                 return ret;
6150         }
6151
6152         if (reg != val) {
6153                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6154                                                    reg, NULL);
6155                 if (ret != 0)
6156                         return ret;
6157         } else {
6158                 ret = 0;
6159         }
6160         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6161                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6162
6163         return ret;
6164 }
6165
6166 static int
6167 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6168 {
6169         int ret = -EINVAL;
6170
6171         if (!hw || !cfg)
6172                 return -EINVAL;
6173
6174         switch (cfg->cfg_type) {
6175         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6176                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6177                 break;
6178         default:
6179                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6180                 break;
6181         }
6182
6183         return ret;
6184 }
6185
6186 static int
6187 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6188                                enum rte_filter_op filter_op,
6189                                void *arg)
6190 {
6191         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6192         int ret = I40E_ERR_PARAM;
6193
6194         switch (filter_op) {
6195         case RTE_ETH_FILTER_SET:
6196                 ret = i40e_dev_global_config_set(hw,
6197                         (struct rte_eth_global_cfg *)arg);
6198                 break;
6199         default:
6200                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6201                 break;
6202         }
6203
6204         return ret;
6205 }
6206
6207 static int
6208 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6209                           enum rte_filter_op filter_op,
6210                           void *arg)
6211 {
6212         struct rte_eth_tunnel_filter_conf *filter;
6213         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6214         int ret = I40E_SUCCESS;
6215
6216         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6217
6218         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6219                 return I40E_ERR_PARAM;
6220
6221         switch (filter_op) {
6222         case RTE_ETH_FILTER_NOP:
6223                 if (!(pf->flags & I40E_FLAG_VXLAN))
6224                         ret = I40E_NOT_SUPPORTED;
6225                 break;
6226         case RTE_ETH_FILTER_ADD:
6227                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6228                 break;
6229         case RTE_ETH_FILTER_DELETE:
6230                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6231                 break;
6232         default:
6233                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6234                 ret = I40E_ERR_PARAM;
6235                 break;
6236         }
6237
6238         return ret;
6239 }
6240
6241 static int
6242 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6243 {
6244         int ret = 0;
6245         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6246
6247         /* RSS setup */
6248         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6249                 ret = i40e_pf_config_rss(pf);
6250         else
6251                 i40e_pf_disable_rss(pf);
6252
6253         return ret;
6254 }
6255
6256 /* Get the symmetric hash enable configurations per port */
6257 static void
6258 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6259 {
6260         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6261
6262         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6263 }
6264
6265 /* Set the symmetric hash enable configurations per port */
6266 static void
6267 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6268 {
6269         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6270
6271         if (enable > 0) {
6272                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6273                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6274                                                         "been enabled");
6275                         return;
6276                 }
6277                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6278         } else {
6279                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6280                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6281                                                         "been disabled");
6282                         return;
6283                 }
6284                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6285         }
6286         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6287         I40E_WRITE_FLUSH(hw);
6288 }
6289
6290 /*
6291  * Get global configurations of hash function type and symmetric hash enable
6292  * per flow type (pctype). Note that global configuration means it affects all
6293  * the ports on the same NIC.
6294  */
6295 static int
6296 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6297                                    struct rte_eth_hash_global_conf *g_cfg)
6298 {
6299         uint32_t reg, mask = I40E_FLOW_TYPES;
6300         uint16_t i;
6301         enum i40e_filter_pctype pctype;
6302
6303         memset(g_cfg, 0, sizeof(*g_cfg));
6304         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6305         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6306                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6307         else
6308                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6309         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6310                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6311
6312         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6313                 if (!(mask & (1UL << i)))
6314                         continue;
6315                 mask &= ~(1UL << i);
6316                 /* Bit set indicats the coresponding flow type is supported */
6317                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6318                 pctype = i40e_flowtype_to_pctype(i);
6319                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6320                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6321                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6322         }
6323
6324         return 0;
6325 }
6326
6327 static int
6328 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6329 {
6330         uint32_t i;
6331         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6332
6333         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6334                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6335                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6336                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6337                                                 g_cfg->hash_func);
6338                 return -EINVAL;
6339         }
6340
6341         /*
6342          * As i40e supports less than 32 flow types, only first 32 bits need to
6343          * be checked.
6344          */
6345         mask0 = g_cfg->valid_bit_mask[0];
6346         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6347                 if (i == 0) {
6348                         /* Check if any unsupported flow type configured */
6349                         if ((mask0 | i40e_mask) ^ i40e_mask)
6350                                 goto mask_err;
6351                 } else {
6352                         if (g_cfg->valid_bit_mask[i])
6353                                 goto mask_err;
6354                 }
6355         }
6356
6357         return 0;
6358
6359 mask_err:
6360         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6361
6362         return -EINVAL;
6363 }
6364
6365 /*
6366  * Set global configurations of hash function type and symmetric hash enable
6367  * per flow type (pctype). Note any modifying global configuration will affect
6368  * all the ports on the same NIC.
6369  */
6370 static int
6371 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6372                                    struct rte_eth_hash_global_conf *g_cfg)
6373 {
6374         int ret;
6375         uint16_t i;
6376         uint32_t reg;
6377         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6378         enum i40e_filter_pctype pctype;
6379
6380         /* Check the input parameters */
6381         ret = i40e_hash_global_config_check(g_cfg);
6382         if (ret < 0)
6383                 return ret;
6384
6385         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6386                 if (!(mask0 & (1UL << i)))
6387                         continue;
6388                 mask0 &= ~(1UL << i);
6389                 pctype = i40e_flowtype_to_pctype(i);
6390                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6391                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6392                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6393         }
6394
6395         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6396         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6397                 /* Toeplitz */
6398                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6399                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6400                                                                 "Toeplitz");
6401                         goto out;
6402                 }
6403                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6404         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6405                 /* Simple XOR */
6406                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6407                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6408                                                         "Simple XOR");
6409                         goto out;
6410                 }
6411                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6412         } else
6413                 /* Use the default, and keep it as it is */
6414                 goto out;
6415
6416         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6417
6418 out:
6419         I40E_WRITE_FLUSH(hw);
6420
6421         return 0;
6422 }
6423
6424 /**
6425  * Valid input sets for hash and flow director filters per PCTYPE
6426  */
6427 static uint64_t
6428 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6429                 enum rte_filter_type filter)
6430 {
6431         uint64_t valid;
6432
6433         static const uint64_t valid_hash_inset_table[] = {
6434                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6435                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6436                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6437                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6438                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6439                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6440                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6441                         I40E_INSET_FLEX_PAYLOAD,
6442                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6443                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6444                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6445                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6446                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6447                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6448                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6449                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6450                         I40E_INSET_FLEX_PAYLOAD,
6451                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6452                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6453                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6454                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6455                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6456                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6457                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6458                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6459                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6460                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6461                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6462                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6463                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6464                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6465                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6466                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6467                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6468                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6469                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6470                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6471                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6472                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6473                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6474                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6475                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6476                         I40E_INSET_FLEX_PAYLOAD,
6477                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6478                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6479                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6480                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6481                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6482                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6483                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6484                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6485                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6486                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6487                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6488                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6489                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6490                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6491                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6492                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6493                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6494                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6495                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6496                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6497                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6498                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6499                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6500                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6501                         I40E_INSET_FLEX_PAYLOAD,
6502                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6503                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6504                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6505                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6506                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6507                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6508                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6509                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6510                         I40E_INSET_FLEX_PAYLOAD,
6511                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6512                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6513                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6514                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6515                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6516                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6517                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6518                         I40E_INSET_FLEX_PAYLOAD,
6519                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6520                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6521                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6522                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6523                         I40E_INSET_FLEX_PAYLOAD,
6524         };
6525
6526         /**
6527          * Flow director supports only fields defined in
6528          * union rte_eth_fdir_flow.
6529          */
6530         static const uint64_t valid_fdir_inset_table[] = {
6531                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6532                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6533                 I40E_INSET_FLEX_PAYLOAD,
6534                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6535                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6536                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6537                 I40E_INSET_FLEX_PAYLOAD,
6538                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6539                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6540                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6541                 I40E_INSET_FLEX_PAYLOAD,
6542                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6543                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6544                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6545                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6546                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6547                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6548                 I40E_INSET_FLEX_PAYLOAD,
6549                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6550                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6551                 I40E_INSET_FLEX_PAYLOAD,
6552                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6553                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6554                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6555                 I40E_INSET_FLEX_PAYLOAD,
6556                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6557                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6558                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6559                 I40E_INSET_FLEX_PAYLOAD,
6560                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6561                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6562                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6563                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6564                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6565                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6566                 I40E_INSET_FLEX_PAYLOAD,
6567                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6568                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6569         };
6570
6571         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6572                 return 0;
6573         if (filter == RTE_ETH_FILTER_HASH)
6574                 valid = valid_hash_inset_table[pctype];
6575         else
6576                 valid = valid_fdir_inset_table[pctype];
6577
6578         return valid;
6579 }
6580
6581 /**
6582  * Validate if the input set is allowed for a specific PCTYPE
6583  */
6584 static int
6585 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6586                 enum rte_filter_type filter, uint64_t inset)
6587 {
6588         uint64_t valid;
6589
6590         valid = i40e_get_valid_input_set(pctype, filter);
6591         if (inset & (~valid))
6592                 return -EINVAL;
6593
6594         return 0;
6595 }
6596
6597 /* default input set fields combination per pctype */
6598 static uint64_t
6599 i40e_get_default_input_set(uint16_t pctype)
6600 {
6601         static const uint64_t default_inset_table[] = {
6602                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6603                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6604                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6605                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6606                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6607                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6608                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6609                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6610                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6611                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6612                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6613                         I40E_INSET_SCTP_VT,
6614                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6615                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6616                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6617                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6618                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6619                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6620                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6621                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6622                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6623                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6624                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6625                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6626                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6627                         I40E_INSET_SCTP_VT,
6628                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6629                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6630                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6631                         I40E_INSET_LAST_ETHER_TYPE,
6632         };
6633
6634         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6635                 return 0;
6636
6637         return default_inset_table[pctype];
6638 }
6639
6640 /**
6641  * Parse the input set from index to logical bit masks
6642  */
6643 static int
6644 i40e_parse_input_set(uint64_t *inset,
6645                      enum i40e_filter_pctype pctype,
6646                      enum rte_eth_input_set_field *field,
6647                      uint16_t size)
6648 {
6649         uint16_t i, j;
6650         int ret = -EINVAL;
6651
6652         static const struct {
6653                 enum rte_eth_input_set_field field;
6654                 uint64_t inset;
6655         } inset_convert_table[] = {
6656                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6657                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6658                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6659                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6660                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6661                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6662                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6663                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6664                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6665                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6666                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6667                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6668                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6669                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6670                         I40E_INSET_IPV6_NEXT_HDR},
6671                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6672                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6673                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6674                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6675                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6676                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6677                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6678                         I40E_INSET_SCTP_VT},
6679                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6680                         I40E_INSET_TUNNEL_DMAC},
6681                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6682                         I40E_INSET_VLAN_TUNNEL},
6683                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6684                         I40E_INSET_TUNNEL_ID},
6685                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6686                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6687                         I40E_INSET_FLEX_PAYLOAD_W1},
6688                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6689                         I40E_INSET_FLEX_PAYLOAD_W2},
6690                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6691                         I40E_INSET_FLEX_PAYLOAD_W3},
6692                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6693                         I40E_INSET_FLEX_PAYLOAD_W4},
6694                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6695                         I40E_INSET_FLEX_PAYLOAD_W5},
6696                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6697                         I40E_INSET_FLEX_PAYLOAD_W6},
6698                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6699                         I40E_INSET_FLEX_PAYLOAD_W7},
6700                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6701                         I40E_INSET_FLEX_PAYLOAD_W8},
6702         };
6703
6704         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6705                 return ret;
6706
6707         /* Only one item allowed for default or all */
6708         if (size == 1) {
6709                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6710                         *inset = i40e_get_default_input_set(pctype);
6711                         return 0;
6712                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6713                         *inset = I40E_INSET_NONE;
6714                         return 0;
6715                 }
6716         }
6717
6718         for (i = 0, *inset = 0; i < size; i++) {
6719                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6720                         if (field[i] == inset_convert_table[j].field) {
6721                                 *inset |= inset_convert_table[j].inset;
6722                                 break;
6723                         }
6724                 }
6725
6726                 /* It contains unsupported input set, return immediately */
6727                 if (j == RTE_DIM(inset_convert_table))
6728                         return ret;
6729         }
6730
6731         return 0;
6732 }
6733
6734 /**
6735  * Translate the input set from bit masks to register aware bit masks
6736  * and vice versa
6737  */
6738 static uint64_t
6739 i40e_translate_input_set_reg(uint64_t input)
6740 {
6741         uint64_t val = 0;
6742         uint16_t i;
6743
6744         static const struct {
6745                 uint64_t inset;
6746                 uint64_t inset_reg;
6747         } inset_map[] = {
6748                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6749                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6750                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6751                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6752                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6753                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6754                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6755                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6756                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6757                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6758                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6759                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6760                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6761                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6762                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6763                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6764                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6765                 {I40E_INSET_TUNNEL_DMAC,
6766                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6767                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6768                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6769                 {I40E_INSET_TUNNEL_SRC_PORT,
6770                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6771                 {I40E_INSET_TUNNEL_DST_PORT,
6772                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6773                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6774                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6775                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6776                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6777                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6778                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6779                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6780                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6781                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6782         };
6783
6784         if (input == 0)
6785                 return val;
6786
6787         /* Translate input set to register aware inset */
6788         for (i = 0; i < RTE_DIM(inset_map); i++) {
6789                 if (input & inset_map[i].inset)
6790                         val |= inset_map[i].inset_reg;
6791         }
6792
6793         return val;
6794 }
6795
6796 static uint8_t
6797 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6798 {
6799         uint8_t i, idx = 0;
6800
6801         static const struct {
6802                 uint64_t inset;
6803                 uint32_t mask;
6804         } inset_mask_map[] = {
6805                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6806                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6807                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6808                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6809         };
6810
6811         if (!inset || !mask || !nb_elem)
6812                 return 0;
6813
6814         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6815                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6816                         mask[i] = 0;
6817                 return I40E_INSET_MASK_NUM_REG;
6818         }
6819
6820         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6821                 if (idx >= nb_elem)
6822                         break;
6823                 if (inset & inset_mask_map[i].inset) {
6824                         mask[idx] = inset_mask_map[i].mask;
6825                         idx++;
6826                 }
6827         }
6828
6829         return idx;
6830 }
6831
6832 static uint64_t
6833 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6834                             enum i40e_filter_pctype pctype)
6835 {
6836         uint64_t reg = 0;
6837
6838         if (filter == RTE_ETH_FILTER_HASH) {
6839                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6840                 reg <<= I40E_32_BIT_WIDTH;
6841                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6842         } else if (filter == RTE_ETH_FILTER_FDIR) {
6843                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6844                 reg <<= I40E_32_BIT_WIDTH;
6845                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6846         }
6847
6848         return reg;
6849 }
6850
6851 static void
6852 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6853 {
6854         uint32_t reg = I40E_READ_REG(hw, addr);
6855
6856         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6857         if (reg != val)
6858                 I40E_WRITE_REG(hw, addr, val);
6859         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6860                     (uint32_t)I40E_READ_REG(hw, addr));
6861 }
6862
6863 static int
6864 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6865                          enum i40e_filter_pctype pctype,
6866                          enum rte_filter_input_set_op op,
6867                          uint32_t *mask_reg,
6868                          uint8_t num)
6869 {
6870         uint32_t reg;
6871         uint8_t i;
6872
6873         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6874                 return -EINVAL;
6875
6876         if (op == RTE_ETH_INPUT_SET_SELECT) {
6877                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6878                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6879                                              0);
6880                         if (i >= num)
6881                                 continue;
6882                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6883                                              mask_reg[i]);
6884                 }
6885         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6886                 uint8_t j, count = 0;
6887
6888                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6889                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6890                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6891                                 count++;
6892                 }
6893                 if (count + num > I40E_INSET_MASK_NUM_REG)
6894                         return -EINVAL;
6895
6896                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6897                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6898                                              mask_reg[j]);
6899         }
6900
6901         return 0;
6902 }
6903
6904 static int
6905 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6906                        enum i40e_filter_pctype pctype,
6907                        enum rte_filter_input_set_op op,
6908                        uint32_t *mask_reg,
6909                        uint8_t num)
6910 {
6911         uint32_t reg;
6912         uint8_t i;
6913
6914         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6915                 return -EINVAL;
6916
6917         if (op == RTE_ETH_INPUT_SET_SELECT) {
6918                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6919                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6920                                              0);
6921                         if (i >= num)
6922                                 continue;
6923                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6924                                              mask_reg[i]);
6925                 }
6926         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6927                 uint8_t j, count = 0;
6928
6929                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6930                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6931                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6932                                 count++;
6933                 }
6934                 if (count + num > I40E_INSET_MASK_NUM_REG)
6935                         return -EINVAL;
6936
6937                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6938                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6939                                              mask_reg[j]);
6940         }
6941
6942         return 0;
6943 }
6944
6945 int
6946 i40e_filter_inset_select(struct i40e_hw *hw,
6947                          struct rte_eth_input_set_conf *conf,
6948                          enum rte_filter_type filter)
6949 {
6950         enum i40e_filter_pctype pctype;
6951         uint64_t inset_reg = 0, input_set;
6952         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6953         uint8_t num;
6954         int ret;
6955
6956         if (!hw || !conf) {
6957                 PMD_DRV_LOG(ERR, "Invalid pointer");
6958                 return -EFAULT;
6959         }
6960
6961         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6962         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6963                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6964                             conf->flow_type);
6965                 return -EINVAL;
6966         }
6967         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6968                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6969                 return -EINVAL;
6970         }
6971
6972         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6973                                    conf->inset_size);
6974         if (ret) {
6975                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6976                 return -EINVAL;
6977         }
6978         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6979                 PMD_DRV_LOG(ERR, "Invalid input set");
6980                 return -EINVAL;
6981         }
6982
6983         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6984                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6985         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6986                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6987                 return -EINVAL;
6988         }
6989         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6990                                            I40E_INSET_MASK_NUM_REG);
6991         inset_reg |= i40e_translate_input_set_reg(input_set);
6992
6993         if (filter == RTE_ETH_FILTER_HASH) {
6994                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
6995                                                num);
6996                 if (ret)
6997                         return -EINVAL;
6998
6999                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7000                                       (uint32_t)(inset_reg & UINT32_MAX));
7001                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7002                                      (uint32_t)((inset_reg >>
7003                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7004         } else if (filter == RTE_ETH_FILTER_FDIR) {
7005                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7006                                              num);
7007                 if (ret)
7008                         return -EINVAL;
7009
7010                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7011                                       (uint32_t)(inset_reg & UINT32_MAX));
7012                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7013                                      (uint32_t)((inset_reg >>
7014                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7015         } else {
7016                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7017                 return -EINVAL;
7018         }
7019         I40E_WRITE_FLUSH(hw);
7020
7021         return 0;
7022 }
7023
7024 static int
7025 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7026 {
7027         int ret = 0;
7028
7029         if (!hw || !info) {
7030                 PMD_DRV_LOG(ERR, "Invalid pointer");
7031                 return -EFAULT;
7032         }
7033
7034         switch (info->info_type) {
7035         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7036                 i40e_get_symmetric_hash_enable_per_port(hw,
7037                                         &(info->info.enable));
7038                 break;
7039         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7040                 ret = i40e_get_hash_filter_global_config(hw,
7041                                 &(info->info.global_conf));
7042                 break;
7043         default:
7044                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7045                                                         info->info_type);
7046                 ret = -EINVAL;
7047                 break;
7048         }
7049
7050         return ret;
7051 }
7052
7053 static int
7054 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7055 {
7056         int ret = 0;
7057
7058         if (!hw || !info) {
7059                 PMD_DRV_LOG(ERR, "Invalid pointer");
7060                 return -EFAULT;
7061         }
7062
7063         switch (info->info_type) {
7064         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7065                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7066                 break;
7067         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7068                 ret = i40e_set_hash_filter_global_config(hw,
7069                                 &(info->info.global_conf));
7070                 break;
7071         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7072                 ret = i40e_filter_inset_select(hw,
7073                                                &(info->info.input_set_conf),
7074                                                RTE_ETH_FILTER_HASH);
7075                 break;
7076
7077         default:
7078                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7079                                                         info->info_type);
7080                 ret = -EINVAL;
7081                 break;
7082         }
7083
7084         return ret;
7085 }
7086
7087 /* Operations for hash function */
7088 static int
7089 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7090                       enum rte_filter_op filter_op,
7091                       void *arg)
7092 {
7093         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7094         int ret = 0;
7095
7096         switch (filter_op) {
7097         case RTE_ETH_FILTER_NOP:
7098                 break;
7099         case RTE_ETH_FILTER_GET:
7100                 ret = i40e_hash_filter_get(hw,
7101                         (struct rte_eth_hash_filter_info *)arg);
7102                 break;
7103         case RTE_ETH_FILTER_SET:
7104                 ret = i40e_hash_filter_set(hw,
7105                         (struct rte_eth_hash_filter_info *)arg);
7106                 break;
7107         default:
7108                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7109                                                                 filter_op);
7110                 ret = -ENOTSUP;
7111                 break;
7112         }
7113
7114         return ret;
7115 }
7116
7117 /*
7118  * Configure ethertype filter, which can director packet by filtering
7119  * with mac address and ether_type or only ether_type
7120  */
7121 static int
7122 i40e_ethertype_filter_set(struct i40e_pf *pf,
7123                         struct rte_eth_ethertype_filter *filter,
7124                         bool add)
7125 {
7126         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7127         struct i40e_control_filter_stats stats;
7128         uint16_t flags = 0;
7129         int ret;
7130
7131         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7132                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7133                 return -EINVAL;
7134         }
7135         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7136                 filter->ether_type == ETHER_TYPE_IPv6) {
7137                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7138                         " control packet filter.", filter->ether_type);
7139                 return -EINVAL;
7140         }
7141         if (filter->ether_type == ETHER_TYPE_VLAN)
7142                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7143                         " not supported.");
7144
7145         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7146                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7147         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7148                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7149         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7150
7151         memset(&stats, 0, sizeof(stats));
7152         ret = i40e_aq_add_rem_control_packet_filter(hw,
7153                         filter->mac_addr.addr_bytes,
7154                         filter->ether_type, flags,
7155                         pf->main_vsi->seid,
7156                         filter->queue, add, &stats, NULL);
7157
7158         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7159                          " mac_etype_used = %u, etype_used = %u,"
7160                          " mac_etype_free = %u, etype_free = %u\n",
7161                          ret, stats.mac_etype_used, stats.etype_used,
7162                          stats.mac_etype_free, stats.etype_free);
7163         if (ret < 0)
7164                 return -ENOSYS;
7165         return 0;
7166 }
7167
7168 /*
7169  * Handle operations for ethertype filter.
7170  */
7171 static int
7172 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7173                                 enum rte_filter_op filter_op,
7174                                 void *arg)
7175 {
7176         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7177         int ret = 0;
7178
7179         if (filter_op == RTE_ETH_FILTER_NOP)
7180                 return ret;
7181
7182         if (arg == NULL) {
7183                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7184                             filter_op);
7185                 return -EINVAL;
7186         }
7187
7188         switch (filter_op) {
7189         case RTE_ETH_FILTER_ADD:
7190                 ret = i40e_ethertype_filter_set(pf,
7191                         (struct rte_eth_ethertype_filter *)arg,
7192                         TRUE);
7193                 break;
7194         case RTE_ETH_FILTER_DELETE:
7195                 ret = i40e_ethertype_filter_set(pf,
7196                         (struct rte_eth_ethertype_filter *)arg,
7197                         FALSE);
7198                 break;
7199         default:
7200                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7201                 ret = -ENOSYS;
7202                 break;
7203         }
7204         return ret;
7205 }
7206
7207 static int
7208 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7209                      enum rte_filter_type filter_type,
7210                      enum rte_filter_op filter_op,
7211                      void *arg)
7212 {
7213         int ret = 0;
7214
7215         if (dev == NULL)
7216                 return -EINVAL;
7217
7218         switch (filter_type) {
7219         case RTE_ETH_FILTER_NONE:
7220                 /* For global configuration */
7221                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7222                 break;
7223         case RTE_ETH_FILTER_HASH:
7224                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7225                 break;
7226         case RTE_ETH_FILTER_MACVLAN:
7227                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7228                 break;
7229         case RTE_ETH_FILTER_ETHERTYPE:
7230                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7231                 break;
7232         case RTE_ETH_FILTER_TUNNEL:
7233                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7234                 break;
7235         case RTE_ETH_FILTER_FDIR:
7236                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7237                 break;
7238         default:
7239                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7240                                                         filter_type);
7241                 ret = -EINVAL;
7242                 break;
7243         }
7244
7245         return ret;
7246 }
7247
7248 /*
7249  * As some registers wouldn't be reset unless a global hardware reset,
7250  * hardware initialization is needed to put those registers into an
7251  * expected initial state.
7252  */
7253 static void
7254 i40e_hw_init(struct i40e_hw *hw)
7255 {
7256         /* clear the PF Queue Filter control register */
7257         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7258
7259         /* Disable symmetric hash per port */
7260         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7261 }
7262
7263 enum i40e_filter_pctype
7264 i40e_flowtype_to_pctype(uint16_t flow_type)
7265 {
7266         static const enum i40e_filter_pctype pctype_table[] = {
7267                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7268                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7269                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7270                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7271                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7272                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7273                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7274                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7275                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7276                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7277                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7278                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7279                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7280                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7281                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7282                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7283                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7284                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7285                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7286         };
7287
7288         return pctype_table[flow_type];
7289 }
7290
7291 uint16_t
7292 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7293 {
7294         static const uint16_t flowtype_table[] = {
7295                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7296                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7297                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7298                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7299                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7300                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7301                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7302                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7303                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7304                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7305                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7306                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7307                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7308                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7309                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7310                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7311                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7312                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7313                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7314         };
7315
7316         return flowtype_table[pctype];
7317 }
7318
7319 /*
7320  * On X710, performance number is far from the expectation on recent firmware
7321  * versions; on XL710, performance number is also far from the expectation on
7322  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7323  * mode is enabled and port MAC address is equal to the packet destination MAC
7324  * address. The fix for this issue may not be integrated in the following
7325  * firmware version. So the workaround in software driver is needed. It needs
7326  * to modify the initial values of 3 internal only registers for both X710 and
7327  * XL710. Note that the values for X710 or XL710 could be different, and the
7328  * workaround can be removed when it is fixed in firmware in the future.
7329  */
7330
7331 /* For both X710 and XL710 */
7332 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7333 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7334
7335 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7336 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7337
7338 /* For X710 */
7339 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7340 /* For XL710 */
7341 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7342 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7343
7344 static void
7345 i40e_configure_registers(struct i40e_hw *hw)
7346 {
7347         static struct {
7348                 uint32_t addr;
7349                 uint64_t val;
7350         } reg_table[] = {
7351                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7352                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7353                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7354         };
7355         uint64_t reg;
7356         uint32_t i;
7357         int ret;
7358
7359         for (i = 0; i < RTE_DIM(reg_table); i++) {
7360                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7361                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7362                                 reg_table[i].val =
7363                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7364                         else /* For X710 */
7365                                 reg_table[i].val =
7366                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7367                 }
7368
7369                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7370                                                         &reg, NULL);
7371                 if (ret < 0) {
7372                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7373                                                         reg_table[i].addr);
7374                         break;
7375                 }
7376                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7377                                                 reg_table[i].addr, reg);
7378                 if (reg == reg_table[i].val)
7379                         continue;
7380
7381                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7382                                                 reg_table[i].val, NULL);
7383                 if (ret < 0) {
7384                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7385                                 "address of 0x%"PRIx32, reg_table[i].val,
7386                                                         reg_table[i].addr);
7387                         break;
7388                 }
7389                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7390                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7391         }
7392 }
7393
7394 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7395 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7396 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7397 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7398 static int
7399 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7400 {
7401         uint32_t reg;
7402         int ret;
7403
7404         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7405                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7406                 return -EINVAL;
7407         }
7408
7409         /* Configure for double VLAN RX stripping */
7410         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7411         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7412                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7413                 ret = i40e_aq_debug_write_register(hw,
7414                                                    I40E_VSI_TSR(vsi->vsi_id),
7415                                                    reg, NULL);
7416                 if (ret < 0) {
7417                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7418                                     vsi->vsi_id);
7419                         return I40E_ERR_CONFIG;
7420                 }
7421         }
7422
7423         /* Configure for double VLAN TX insertion */
7424         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7425         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7426                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7427                 ret = i40e_aq_debug_write_register(hw,
7428                                                    I40E_VSI_L2TAGSTXVALID(
7429                                                    vsi->vsi_id), reg, NULL);
7430                 if (ret < 0) {
7431                         PMD_DRV_LOG(ERR, "Failed to update "
7432                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7433                         return I40E_ERR_CONFIG;
7434                 }
7435         }
7436
7437         return 0;
7438 }
7439
7440 /**
7441  * i40e_aq_add_mirror_rule
7442  * @hw: pointer to the hardware structure
7443  * @seid: VEB seid to add mirror rule to
7444  * @dst_id: destination vsi seid
7445  * @entries: Buffer which contains the entities to be mirrored
7446  * @count: number of entities contained in the buffer
7447  * @rule_id:the rule_id of the rule to be added
7448  *
7449  * Add a mirror rule for a given veb.
7450  *
7451  **/
7452 static enum i40e_status_code
7453 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7454                         uint16_t seid, uint16_t dst_id,
7455                         uint16_t rule_type, uint16_t *entries,
7456                         uint16_t count, uint16_t *rule_id)
7457 {
7458         struct i40e_aq_desc desc;
7459         struct i40e_aqc_add_delete_mirror_rule cmd;
7460         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7461                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7462                 &desc.params.raw;
7463         uint16_t buff_len;
7464         enum i40e_status_code status;
7465
7466         i40e_fill_default_direct_cmd_desc(&desc,
7467                                           i40e_aqc_opc_add_mirror_rule);
7468         memset(&cmd, 0, sizeof(cmd));
7469
7470         buff_len = sizeof(uint16_t) * count;
7471         desc.datalen = rte_cpu_to_le_16(buff_len);
7472         if (buff_len > 0)
7473                 desc.flags |= rte_cpu_to_le_16(
7474                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7475         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7476                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7477         cmd.num_entries = rte_cpu_to_le_16(count);
7478         cmd.seid = rte_cpu_to_le_16(seid);
7479         cmd.destination = rte_cpu_to_le_16(dst_id);
7480
7481         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7482         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7483         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7484                          "rule_id = %u"
7485                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7486                          hw->aq.asq_last_status, resp->rule_id,
7487                          resp->mirror_rules_used, resp->mirror_rules_free);
7488         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7489
7490         return status;
7491 }
7492
7493 /**
7494  * i40e_aq_del_mirror_rule
7495  * @hw: pointer to the hardware structure
7496  * @seid: VEB seid to add mirror rule to
7497  * @entries: Buffer which contains the entities to be mirrored
7498  * @count: number of entities contained in the buffer
7499  * @rule_id:the rule_id of the rule to be delete
7500  *
7501  * Delete a mirror rule for a given veb.
7502  *
7503  **/
7504 static enum i40e_status_code
7505 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7506                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7507                 uint16_t count, uint16_t rule_id)
7508 {
7509         struct i40e_aq_desc desc;
7510         struct i40e_aqc_add_delete_mirror_rule cmd;
7511         uint16_t buff_len = 0;
7512         enum i40e_status_code status;
7513         void *buff = NULL;
7514
7515         i40e_fill_default_direct_cmd_desc(&desc,
7516                                           i40e_aqc_opc_delete_mirror_rule);
7517         memset(&cmd, 0, sizeof(cmd));
7518         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7519                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7520                                                           I40E_AQ_FLAG_RD));
7521                 cmd.num_entries = count;
7522                 buff_len = sizeof(uint16_t) * count;
7523                 desc.datalen = rte_cpu_to_le_16(buff_len);
7524                 buff = (void *)entries;
7525         } else
7526                 /* rule id is filled in destination field for deleting mirror rule */
7527                 cmd.destination = rte_cpu_to_le_16(rule_id);
7528
7529         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7530                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7531         cmd.seid = rte_cpu_to_le_16(seid);
7532
7533         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7534         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7535
7536         return status;
7537 }
7538
7539 /**
7540  * i40e_mirror_rule_set
7541  * @dev: pointer to the hardware structure
7542  * @mirror_conf: mirror rule info
7543  * @sw_id: mirror rule's sw_id
7544  * @on: enable/disable
7545  *
7546  * set a mirror rule.
7547  *
7548  **/
7549 static int
7550 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7551                         struct rte_eth_mirror_conf *mirror_conf,
7552                         uint8_t sw_id, uint8_t on)
7553 {
7554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7556         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7557         struct i40e_mirror_rule *parent = NULL;
7558         uint16_t seid, dst_seid, rule_id;
7559         uint16_t i, j = 0;
7560         int ret;
7561
7562         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7563
7564         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7565                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7566                         " without veb or vfs.");
7567                 return -ENOSYS;
7568         }
7569         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7570                 PMD_DRV_LOG(ERR, "mirror table is full.");
7571                 return -ENOSPC;
7572         }
7573         if (mirror_conf->dst_pool > pf->vf_num) {
7574                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7575                                  mirror_conf->dst_pool);
7576                 return -EINVAL;
7577         }
7578
7579         seid = pf->main_vsi->veb->seid;
7580
7581         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7582                 if (sw_id <= it->index) {
7583                         mirr_rule = it;
7584                         break;
7585                 }
7586                 parent = it;
7587         }
7588         if (mirr_rule && sw_id == mirr_rule->index) {
7589                 if (on) {
7590                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7591                         return -EEXIST;
7592                 } else {
7593                         ret = i40e_aq_del_mirror_rule(hw, seid,
7594                                         mirr_rule->rule_type,
7595                                         mirr_rule->entries,
7596                                         mirr_rule->num_entries, mirr_rule->id);
7597                         if (ret < 0) {
7598                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7599                                                    " ret = %d, aq_err = %d.",
7600                                                    ret, hw->aq.asq_last_status);
7601                                 return -ENOSYS;
7602                         }
7603                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7604                         rte_free(mirr_rule);
7605                         pf->nb_mirror_rule--;
7606                         return 0;
7607                 }
7608         } else if (!on) {
7609                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7610                 return -ENOENT;
7611         }
7612
7613         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7614                                 sizeof(struct i40e_mirror_rule) , 0);
7615         if (!mirr_rule) {
7616                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7617                 return I40E_ERR_NO_MEMORY;
7618         }
7619         switch (mirror_conf->rule_type) {
7620         case ETH_MIRROR_VLAN:
7621                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7622                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7623                                 mirr_rule->entries[j] =
7624                                         mirror_conf->vlan.vlan_id[i];
7625                                 j++;
7626                         }
7627                 }
7628                 if (j == 0) {
7629                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7630                         rte_free(mirr_rule);
7631                         return -EINVAL;
7632                 }
7633                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7634                 break;
7635         case ETH_MIRROR_VIRTUAL_POOL_UP:
7636         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7637                 /* check if the specified pool bit is out of range */
7638                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7639                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7640                         rte_free(mirr_rule);
7641                         return -EINVAL;
7642                 }
7643                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7644                         if (mirror_conf->pool_mask & (1ULL << i)) {
7645                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7646                                 j++;
7647                         }
7648                 }
7649                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7650                         /* add pf vsi to entries */
7651                         mirr_rule->entries[j] = pf->main_vsi_seid;
7652                         j++;
7653                 }
7654                 if (j == 0) {
7655                         PMD_DRV_LOG(ERR, "pool is not specified.");
7656                         rte_free(mirr_rule);
7657                         return -EINVAL;
7658                 }
7659                 /* egress and ingress in aq commands means from switch but not port */
7660                 mirr_rule->rule_type =
7661                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7662                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7663                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7664                 break;
7665         case ETH_MIRROR_UPLINK_PORT:
7666                 /* egress and ingress in aq commands means from switch but not port*/
7667                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7668                 break;
7669         case ETH_MIRROR_DOWNLINK_PORT:
7670                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7671                 break;
7672         default:
7673                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7674                         mirror_conf->rule_type);
7675                 rte_free(mirr_rule);
7676                 return -EINVAL;
7677         }
7678
7679         /* If the dst_pool is equal to vf_num, consider it as PF */
7680         if (mirror_conf->dst_pool == pf->vf_num)
7681                 dst_seid = pf->main_vsi_seid;
7682         else
7683                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7684
7685         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7686                                       mirr_rule->rule_type, mirr_rule->entries,
7687                                       j, &rule_id);
7688         if (ret < 0) {
7689                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7690                                    " ret = %d, aq_err = %d.",
7691                                    ret, hw->aq.asq_last_status);
7692                 rte_free(mirr_rule);
7693                 return -ENOSYS;
7694         }
7695
7696         mirr_rule->index = sw_id;
7697         mirr_rule->num_entries = j;
7698         mirr_rule->id = rule_id;
7699         mirr_rule->dst_vsi_seid = dst_seid;
7700
7701         if (parent)
7702                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7703         else
7704                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7705
7706         pf->nb_mirror_rule++;
7707         return 0;
7708 }
7709
7710 /**
7711  * i40e_mirror_rule_reset
7712  * @dev: pointer to the device
7713  * @sw_id: mirror rule's sw_id
7714  *
7715  * reset a mirror rule.
7716  *
7717  **/
7718 static int
7719 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7720 {
7721         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7722         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7723         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7724         uint16_t seid;
7725         int ret;
7726
7727         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7728
7729         seid = pf->main_vsi->veb->seid;
7730
7731         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7732                 if (sw_id == it->index) {
7733                         mirr_rule = it;
7734                         break;
7735                 }
7736         }
7737         if (mirr_rule) {
7738                 ret = i40e_aq_del_mirror_rule(hw, seid,
7739                                 mirr_rule->rule_type,
7740                                 mirr_rule->entries,
7741                                 mirr_rule->num_entries, mirr_rule->id);
7742                 if (ret < 0) {
7743                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7744                                            " status = %d, aq_err = %d.",
7745                                            ret, hw->aq.asq_last_status);
7746                         return -ENOSYS;
7747                 }
7748                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7749                 rte_free(mirr_rule);
7750                 pf->nb_mirror_rule--;
7751         } else {
7752                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7753                 return -ENOENT;
7754         }
7755         return 0;
7756 }
7757
7758 static int
7759 i40e_timesync_enable(struct rte_eth_dev *dev)
7760 {
7761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7762         struct rte_eth_link *link = &dev->data->dev_link;
7763         uint32_t tsync_ctl_l;
7764         uint32_t tsync_ctl_h;
7765         uint32_t tsync_inc_l;
7766         uint32_t tsync_inc_h;
7767
7768         switch (link->link_speed) {
7769         case ETH_LINK_SPEED_40G:
7770                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7771                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7772                 break;
7773         case ETH_LINK_SPEED_10G:
7774                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7775                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7776                 break;
7777         case ETH_LINK_SPEED_1000:
7778                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7779                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7780                 break;
7781         default:
7782                 tsync_inc_l = 0x0;
7783                 tsync_inc_h = 0x0;
7784         }
7785
7786         /* Clear timesync registers. */
7787         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7788         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7789         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7790         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7791         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7792         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7793         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7794
7795         /* Set the timesync increment value. */
7796         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7797         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7798
7799         /* Enable timestamping of PTP packets. */
7800         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7801         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7802
7803         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7804         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7805         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7806
7807         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7808         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7809
7810         return 0;
7811 }
7812
7813 static int
7814 i40e_timesync_disable(struct rte_eth_dev *dev)
7815 {
7816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817         uint32_t tsync_ctl_l;
7818         uint32_t tsync_ctl_h;
7819
7820         /* Disable timestamping of transmitted PTP packets. */
7821         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7822         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7823
7824         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7825         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7826
7827         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7828         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7829
7830         /* Set the timesync increment value. */
7831         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7832         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7833
7834         return 0;
7835 }
7836
7837 static int
7838 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7839                                 struct timespec *timestamp, uint32_t flags)
7840 {
7841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7842         uint32_t sync_status;
7843         uint32_t rx_stmpl;
7844         uint32_t rx_stmph;
7845         uint32_t index = flags & 0x03;
7846
7847         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7848         if ((sync_status & (1 << index)) == 0)
7849                 return -EINVAL;
7850
7851         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7852         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7853
7854         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7855         timestamp->tv_nsec = 0;
7856
7857         return  0;
7858 }
7859
7860 static int
7861 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7862                                 struct timespec *timestamp)
7863 {
7864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7865         uint32_t sync_status;
7866         uint32_t tx_stmpl;
7867         uint32_t tx_stmph;
7868
7869         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7870         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7871                 return -EINVAL;
7872
7873         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7874         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7875
7876         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7877         timestamp->tv_nsec = 0;
7878
7879         return  0;
7880 }
7881
7882 /*
7883  * i40e_parse_dcb_configure - parse dcb configure from user
7884  * @dev: the device being configured
7885  * @dcb_cfg: pointer of the result of parse
7886  * @*tc_map: bit map of enabled traffic classes
7887  *
7888  * Returns 0 on success, negative value on failure
7889  */
7890 static int
7891 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7892                          struct i40e_dcbx_config *dcb_cfg,
7893                          uint8_t *tc_map)
7894 {
7895         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7896         uint8_t i, tc_bw, bw_lf;
7897
7898         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7899
7900         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7901         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7902                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7903                 return -EINVAL;
7904         }
7905
7906         /* assume each tc has the same bw */
7907         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7908         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7909                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7910         /* to ensure the sum of tcbw is equal to 100 */
7911         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7912         for (i = 0; i < bw_lf; i++)
7913                 dcb_cfg->etscfg.tcbwtable[i]++;
7914
7915         /* assume each tc has the same Transmission Selection Algorithm */
7916         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7917                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7918
7919         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7920                 dcb_cfg->etscfg.prioritytable[i] =
7921                                 dcb_rx_conf->dcb_tc[i];
7922
7923         /* FW needs one App to configure HW */
7924         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7925         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7926         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7927         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7928
7929         if (dcb_rx_conf->nb_tcs == 0)
7930                 *tc_map = 1; /* tc0 only */
7931         else
7932                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7933
7934         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7935                 dcb_cfg->pfc.willing = 0;
7936                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7937                 dcb_cfg->pfc.pfcenable = *tc_map;
7938         }
7939         return 0;
7940 }
7941
7942 /*
7943  * i40e_vsi_get_bw_info - Query VSI BW Information
7944  * @vsi: the VSI being queried
7945  *
7946  * Returns 0 on success, negative value on failure
7947  */
7948 static enum i40e_status_code
7949 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7950 {
7951         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7952         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7953         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7954         enum i40e_status_code ret;
7955         int i;
7956         uint32_t tc_bw_max;
7957
7958         /* Get the VSI level BW configuration */
7959         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7960         if (ret) {
7961                 PMD_INIT_LOG(ERR,
7962                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
7963                          i40e_stat_str(hw, ret),
7964                          i40e_aq_str(hw, hw->aq.asq_last_status));
7965                 return ret;
7966         }
7967
7968         /* Get the VSI level BW configuration per TC */
7969         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7970                                                   NULL);
7971         if (ret) {
7972                 PMD_INIT_LOG(ERR,
7973                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7974                          i40e_stat_str(hw, ret),
7975                          i40e_aq_str(hw, hw->aq.asq_last_status));
7976                 return ret;
7977         }
7978
7979         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7980                 PMD_INIT_LOG(WARNING,
7981                          "Enabled TCs mismatch from querying VSI BW info"
7982                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7983                          bw_ets_config.tc_valid_bits);
7984                 /* Still continuing */
7985         }
7986
7987         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
7988         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
7989         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
7990                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
7991         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7992                 vsi->bw_info.bw_ets_share_credits[i] =
7993                                 bw_ets_config.share_credits[i];
7994                 vsi->bw_info.bw_ets_limit_credits[i] =
7995                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
7996                 /* 3 bits out of 4 for each TC */
7997                 vsi->bw_info.bw_ets_max_quanta[i] =
7998                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
7999                 PMD_INIT_LOG(DEBUG,
8000                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
8001                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
8002         }
8003
8004         return ret;
8005 }
8006
8007 static enum i40e_status_code
8008 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8009                               struct i40e_aqc_vsi_properties_data *info,
8010                               uint8_t enabled_tcmap)
8011 {
8012         enum i40e_status_code ret;
8013         int i, total_tc = 0;
8014         uint16_t qpnum_per_tc, bsf, qp_idx;
8015         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8016
8017         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8018         if (ret != I40E_SUCCESS)
8019                 return ret;
8020
8021         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8022                 if (enabled_tcmap & (1 << i))
8023                         total_tc++;
8024         }
8025         if (total_tc == 0)
8026                 total_tc = 1;
8027         vsi->enabled_tc = enabled_tcmap;
8028
8029         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8030         /* Number of queues per enabled TC */
8031         if (qpnum_per_tc == 0) {
8032                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8033                 return I40E_ERR_INVALID_QP_ID;
8034         }
8035         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8036                                 I40E_MAX_Q_PER_TC);
8037         bsf = rte_bsf32(qpnum_per_tc);
8038
8039         /**
8040          * Configure TC and queue mapping parameters, for enabled TC,
8041          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8042          * default queue will serve it.
8043          */
8044         qp_idx = 0;
8045         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8046                 if (vsi->enabled_tc & (1 << i)) {
8047                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8048                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8049                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8050                         qp_idx += qpnum_per_tc;
8051                 } else
8052                         info->tc_mapping[i] = 0;
8053         }
8054
8055         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8056         if (vsi->type == I40E_VSI_SRIOV) {
8057                 info->mapping_flags |=
8058                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8059                 for (i = 0; i < vsi->nb_qps; i++)
8060                         info->queue_mapping[i] =
8061                                 rte_cpu_to_le_16(vsi->base_queue + i);
8062         } else {
8063                 info->mapping_flags |=
8064                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8065                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8066         }
8067         info->valid_sections |=
8068                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8069
8070         return I40E_SUCCESS;
8071 }
8072
8073 /*
8074  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8075  * @vsi: VSI to be configured
8076  * @tc_map: enabled TC bitmap
8077  *
8078  * Returns 0 on success, negative value on failure
8079  */
8080 static enum i40e_status_code
8081 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8082 {
8083         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8084         struct i40e_vsi_context ctxt;
8085         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8086         enum i40e_status_code ret = I40E_SUCCESS;
8087         int i;
8088
8089         /* Check if enabled_tc is same as existing or new TCs */
8090         if (vsi->enabled_tc == tc_map)
8091                 return ret;
8092
8093         /* configure tc bandwidth */
8094         memset(&bw_data, 0, sizeof(bw_data));
8095         bw_data.tc_valid_bits = tc_map;
8096         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8097         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8098                 if (tc_map & BIT_ULL(i))
8099                         bw_data.tc_bw_credits[i] = 1;
8100         }
8101         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8102         if (ret) {
8103                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8104                         " per TC failed = %d",
8105                         hw->aq.asq_last_status);
8106                 goto out;
8107         }
8108         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8109                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8110
8111         /* Update Queue Pairs Mapping for currently enabled UPs */
8112         ctxt.seid = vsi->seid;
8113         ctxt.pf_num = hw->pf_id;
8114         ctxt.vf_num = 0;
8115         ctxt.uplink_seid = vsi->uplink_seid;
8116         ctxt.info = vsi->info;
8117         i40e_get_cap(hw);
8118         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8119         if (ret)
8120                 goto out;
8121
8122         /* Update the VSI after updating the VSI queue-mapping information */
8123         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8124         if (ret) {
8125                 PMD_INIT_LOG(ERR, "Failed to configure "
8126                             "TC queue mapping = %d",
8127                             hw->aq.asq_last_status);
8128                 goto out;
8129         }
8130         /* update the local VSI info with updated queue map */
8131         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8132                                         sizeof(vsi->info.tc_mapping));
8133         (void)rte_memcpy(&vsi->info.queue_mapping,
8134                         &ctxt.info.queue_mapping,
8135                 sizeof(vsi->info.queue_mapping));
8136         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8137         vsi->info.valid_sections = 0;
8138
8139         /* Update current VSI BW information */
8140         ret = i40e_vsi_get_bw_info(vsi);
8141         if (ret) {
8142                 PMD_INIT_LOG(ERR,
8143                          "Failed updating vsi bw info, err %s aq_err %s",
8144                          i40e_stat_str(hw, ret),
8145                          i40e_aq_str(hw, hw->aq.asq_last_status));
8146                 goto out;
8147         }
8148
8149         vsi->enabled_tc = tc_map;
8150
8151 out:
8152         return ret;
8153 }
8154
8155 /*
8156  * i40e_dcb_hw_configure - program the dcb setting to hw
8157  * @pf: pf the configuration is taken on
8158  * @new_cfg: new configuration
8159  * @tc_map: enabled TC bitmap
8160  *
8161  * Returns 0 on success, negative value on failure
8162  */
8163 static enum i40e_status_code
8164 i40e_dcb_hw_configure(struct i40e_pf *pf,
8165                       struct i40e_dcbx_config *new_cfg,
8166                       uint8_t tc_map)
8167 {
8168         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8169         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8170         struct i40e_vsi *main_vsi = pf->main_vsi;
8171         struct i40e_vsi_list *vsi_list;
8172         enum i40e_status_code ret;
8173         int i;
8174         uint32_t val;
8175
8176         /* Use the FW API if FW > v4.4*/
8177         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8178                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8179                                   " to configure DCB");
8180                 return I40E_ERR_FIRMWARE_API_VERSION;
8181         }
8182
8183         /* Check if need reconfiguration */
8184         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8185                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8186                 return I40E_SUCCESS;
8187         }
8188
8189         /* Copy the new config to the current config */
8190         *old_cfg = *new_cfg;
8191         old_cfg->etsrec = old_cfg->etscfg;
8192         ret = i40e_set_dcb_config(hw);
8193         if (ret) {
8194                 PMD_INIT_LOG(ERR,
8195                          "Set DCB Config failed, err %s aq_err %s\n",
8196                          i40e_stat_str(hw, ret),
8197                          i40e_aq_str(hw, hw->aq.asq_last_status));
8198                 return ret;
8199         }
8200         /* set receive Arbiter to RR mode and ETS scheme by default */
8201         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8202                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8203                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8204                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8205                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8206                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8207                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8208                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8209                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8210                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8211                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8212                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8213                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8214         }
8215         /* get local mib to check whether it is configured correctly */
8216         /* IEEE mode */
8217         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8218         /* Get Local DCB Config */
8219         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8220                                      &hw->local_dcbx_config);
8221
8222         /* Update each VSI */
8223         i40e_vsi_config_tc(main_vsi, tc_map);
8224         if (main_vsi->veb) {
8225                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8226                         /* Beside main VSI, only enable default
8227                          * TC for other VSIs
8228                          */
8229                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8230                                                 I40E_DEFAULT_TCMAP);
8231                         if (ret)
8232                                 PMD_INIT_LOG(WARNING,
8233                                          "Failed configuring TC for VSI seid=%d\n",
8234                                          vsi_list->vsi->seid);
8235                         /* continue */
8236                 }
8237         }
8238         return I40E_SUCCESS;
8239 }
8240
8241 /*
8242  * i40e_dcb_init_configure - initial dcb config
8243  * @dev: device being configured
8244  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8245  *
8246  * Returns 0 on success, negative value on failure
8247  */
8248 static int
8249 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8250 {
8251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8253         int ret = 0;
8254
8255         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8256                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8257                 return -ENOTSUP;
8258         }
8259
8260         /* DCB initialization:
8261          * Update DCB configuration from the Firmware and configure
8262          * LLDP MIB change event.
8263          */
8264         if (sw_dcb == TRUE) {
8265                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8266                 if (ret != I40E_SUCCESS)
8267                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8268
8269                 ret = i40e_init_dcb(hw);
8270                 /* if sw_dcb, lldp agent is stopped, the return from
8271                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8272                  * adminq status.
8273                  */
8274                 if (ret != I40E_SUCCESS &&
8275                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8276                         memset(&hw->local_dcbx_config, 0,
8277                                 sizeof(struct i40e_dcbx_config));
8278                         /* set dcb default configuration */
8279                         hw->local_dcbx_config.etscfg.willing = 0;
8280                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8281                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8282                         hw->local_dcbx_config.etscfg.tsatable[0] =
8283                                                 I40E_IEEE_TSA_ETS;
8284                         hw->local_dcbx_config.etsrec =
8285                                 hw->local_dcbx_config.etscfg;
8286                         hw->local_dcbx_config.pfc.willing = 0;
8287                         hw->local_dcbx_config.pfc.pfccap =
8288                                                 I40E_MAX_TRAFFIC_CLASS;
8289                         /* FW needs one App to configure HW */
8290                         hw->local_dcbx_config.numapps = 1;
8291                         hw->local_dcbx_config.app[0].selector =
8292                                                 I40E_APP_SEL_ETHTYPE;
8293                         hw->local_dcbx_config.app[0].priority = 3;
8294                         hw->local_dcbx_config.app[0].protocolid =
8295                                                 I40E_APP_PROTOID_FCOE;
8296                         ret = i40e_set_dcb_config(hw);
8297                         if (ret) {
8298                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8299                                         " err = %d, aq_err = %d.", ret,
8300                                           hw->aq.asq_last_status);
8301                                 return -ENOSYS;
8302                         }
8303                 } else {
8304                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8305                                           " aq_err = %d.", ret,
8306                                           hw->aq.asq_last_status);
8307                         return -ENOTSUP;
8308                 }
8309         } else {
8310                 ret = i40e_aq_start_lldp(hw, NULL);
8311                 if (ret != I40E_SUCCESS)
8312                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8313
8314                 ret = i40e_init_dcb(hw);
8315                 if (!ret) {
8316                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8317                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8318                                                   " DCBX offload.");
8319                                 return -ENOTSUP;
8320                         }
8321                 } else {
8322                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8323                                           " aq_err = %d.", ret,
8324                                           hw->aq.asq_last_status);
8325                         return -ENOTSUP;
8326                 }
8327         }
8328         return 0;
8329 }
8330
8331 /*
8332  * i40e_dcb_setup - setup dcb related config
8333  * @dev: device being configured
8334  *
8335  * Returns 0 on success, negative value on failure
8336  */
8337 static int
8338 i40e_dcb_setup(struct rte_eth_dev *dev)
8339 {
8340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8341         struct i40e_dcbx_config dcb_cfg;
8342         uint8_t tc_map = 0;
8343         int ret = 0;
8344
8345         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8346                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8347                 return -ENOTSUP;
8348         }
8349
8350         if (pf->vf_num != 0 ||
8351             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8352                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8353
8354         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8355         if (ret) {
8356                 PMD_INIT_LOG(ERR, "invalid dcb config");
8357                 return -EINVAL;
8358         }
8359         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8360         if (ret) {
8361                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8362                 return -ENOSYS;
8363         }
8364
8365         return 0;
8366 }
8367
8368 static int
8369 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8370                       struct rte_eth_dcb_info *dcb_info)
8371 {
8372         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8373         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8374         struct i40e_vsi *vsi = pf->main_vsi;
8375         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8376         uint16_t bsf, tc_mapping;
8377         int i;
8378
8379         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8380                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8381         else
8382                 dcb_info->nb_tcs = 1;
8383         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8384                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8385         for (i = 0; i < dcb_info->nb_tcs; i++)
8386                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8387
8388         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8389                 if (vsi->enabled_tc & (1 << i)) {
8390                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8391                         /* only main vsi support multi TCs */
8392                         dcb_info->tc_queue.tc_rxq[0][i].base =
8393                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8394                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8395                         dcb_info->tc_queue.tc_txq[0][i].base =
8396                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8397                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8398                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8399                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8400                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8401                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8402                 }
8403         }
8404
8405         return 0;
8406 }
8407
8408 static int
8409 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8410 {
8411         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8412         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8413         uint16_t interval =
8414                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8415         uint16_t msix_intr;
8416
8417         msix_intr = intr_handle->intr_vec[queue_id];
8418         if (msix_intr == I40E_MISC_VEC_ID)
8419                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8420                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8421                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8422                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8423                                (interval <<
8424                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8425         else
8426                 I40E_WRITE_REG(hw,
8427                                I40E_PFINT_DYN_CTLN(msix_intr -
8428                                                    I40E_RX_VEC_START),
8429                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8430                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8431                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8432                                (interval <<
8433                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8434
8435         I40E_WRITE_FLUSH(hw);
8436         rte_intr_enable(&dev->pci_dev->intr_handle);
8437
8438         return 0;
8439 }
8440
8441 static int
8442 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8443 {
8444         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8445         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8446         uint16_t msix_intr;
8447
8448         msix_intr = intr_handle->intr_vec[queue_id];
8449         if (msix_intr == I40E_MISC_VEC_ID)
8450                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8451         else
8452                 I40E_WRITE_REG(hw,
8453                                I40E_PFINT_DYN_CTLN(msix_intr -
8454                                                    I40E_RX_VEC_START),
8455                                0);
8456         I40E_WRITE_FLUSH(hw);
8457
8458         return 0;
8459 }