drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  49
  50 #define I40E_CLEAR_PXE_WAIT_MS     200
  51 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  52 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  53
  54 /* Maximun number of capability elements */
  55 #define I40E_MAX_CAP_ELE_NUM       128
  56
  57 /* Wait count and interval */
  58 #define I40E_CHK_Q_ENA_COUNT       1000
  59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  60
  61 /* Maximun number of VSI */
  62 #define I40E_MAX_NUM_VSIS          (384UL)
  63
  64 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  65
  66 /* Flow control default timer */
  67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  68
  69 /* Flow control enable fwd bit */
  70 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  71
  72 /* Receive Packet Buffer size */
  73 #define I40E_RXPBSIZE (968 * 1024)
  74
  75 /* Kilobytes shift */
  76 #define I40E_KILOSHIFT 10
  77
  78 /* Flow control default high water */
  79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Flow control default low water */
  82 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  83
  84 /* Receive Average Packet Size in Byte*/
  85 #define I40E_PACKET_AVERAGE_SIZE 128
  86
  87 /* Mask of PF interrupt causes */
  88 #define I40E_PFINT_ICR0_ENA_MASK ( \
  89                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  93                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  94                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  98
  99 #define I40E_FLOW_TYPES ( \
 100         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 105         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 110         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 111
 112 /* Additional timesync values. */
 113 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 114 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 115 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 116 #define I40E_PRTTSYN_TSYNENA     0x80000000
 117 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 118 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 119
 120 /**
 121  * Below are values for writing un-exposed registers suggested
 122  * by silicon experts
 123  */
 124 /* Destination MAC address */
 125 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 126 /* Source MAC address */
 127 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 129 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 131 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 132 /* Single VLAN tag in the inner L2 header */
 133 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 134 /* Source IPv4 address */
 135 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 136 /* Destination IPv4 address */
 137 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 138 /* Source IPv4 address for X722 */
 139 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 140 /* Destination IPv4 address for X722 */
 141 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 142 /* IPv4 Protocol for X722 */
 143 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 144 /* IPv4 Time to Live for X722 */
 145 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 146 /* IPv4 Type of Service (TOS) */
 147 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 148 /* IPv4 Protocol */
 149 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 150 /* IPv4 Time to Live */
 151 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 152 /* Source IPv6 address */
 153 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 154 /* Destination IPv6 address */
 155 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 156 /* IPv6 Traffic Class (TC) */
 157 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 158 /* IPv6 Next Header */
 159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 160 /* IPv6 Hop Limit */
 161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 162 /* Source L4 port */
 163 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 164 /* Destination L4 port */
 165 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 166 /* SCTP verification tag */
 167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 170 /* Source port of tunneling UDP */
 171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 172 /* Destination port of tunneling UDP */
 173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 174 /* UDP Tunneling ID, NVGRE/GRE key */
 175 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 176 /* Last ether type */
 177 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 178 /* Tunneling outer destination IPv4 address */
 179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 180 /* Tunneling outer destination IPv6 address */
 181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 182 /* 1st word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 184 /* 2nd word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 186 /* 3rd word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 188 /* 4th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 190 /* 5th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 192 /* 6th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 194 /* 7th word of flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 196 /* 8th word of flex payload */
 197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 198 /* all 8 words flex payload */
 199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 200 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 201
 202 #define I40E_TRANSLATE_INSET 0
 203 #define I40E_TRANSLATE_REG   1
 204
 205 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 206 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 207 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 208 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 210 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 211
 212 /* PCI offset for querying capability */
 213 #define PCI_DEV_CAP_REG            0xA4
 214 /* PCI offset for enabling/disabling Extended Tag */
 215 #define PCI_DEV_CTRL_REG           0xA8
 216 /* Bit mask of Extended Tag capability */
 217 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 218 /* Bit shift of Extended Tag enable/disable */
 219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 220 /* Bit mask of Extended Tag enable/disable */
 221 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 222
 223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 225 static int i40e_dev_configure(struct rte_eth_dev *dev);
 226 static int i40e_dev_start(struct rte_eth_dev *dev);
 227 static void i40e_dev_stop(struct rte_eth_dev *dev);
 228 static int i40e_dev_close(struct rte_eth_dev *dev);
 229 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_stats *stats);
 238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 239                                struct rte_eth_xstat *xstats, unsigned n);
 240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 241                                      struct rte_eth_xstat_name *xstats_names,
 242                                      unsigned limit);
 243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 247                              struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct rte_ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 309                                              struct i40e_macvlan_filter *mv_f,
 310                                              int num,
 311                                              uint16_t vlan);
 312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 314                                     struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 316                                       struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 322 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 326                                 enum rte_filter_type filter_type,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                   struct rte_eth_dcb_info *dcb_info);
 331 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 332 static void i40e_configure_registers(struct i40e_hw *hw);
 333 static void i40e_hw_init(struct rte_eth_dev *dev);
 334 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 335 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 336                                                      uint16_t seid,
 337                                                      uint16_t rule_type,
 338                                                      uint16_t *entries,
 339                                                      uint16_t count,
 340                                                      uint16_t rule_id);
 341 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 342                         struct rte_eth_mirror_conf *mirror_conf,
 343                         uint8_t sw_id, uint8_t on);
 344 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 345
 346 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 347 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 348 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp,
 350                                            uint32_t flags);
 351 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 352                                            struct timespec *timestamp);
 353 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 354
 355 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 356
 357 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 358                                    struct timespec *timestamp);
 359 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 360                                     const struct timespec *timestamp);
 361
 362 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 363                                          uint16_t queue_id);
 364 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 365                                           uint16_t queue_id);
 366
 367 static int i40e_get_regs(struct rte_eth_dev *dev,
 368                          struct rte_dev_reg_info *regs);
 369
 370 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 371
 372 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 373                            struct rte_dev_eeprom_info *eeprom);
 374
 375 static int i40e_get_module_info(struct rte_eth_dev *dev,
 376                                 struct rte_eth_dev_module_info *modinfo);
 377 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 378                                   struct rte_dev_eeprom_info *info);
 379
 380 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 381                                       struct rte_ether_addr *mac_addr);
 382
 383 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 384
 385 static int i40e_ethertype_filter_convert(
 386         const struct rte_eth_ethertype_filter *input,
 387         struct i40e_ethertype_filter *filter);
 388 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 389                                    struct i40e_ethertype_filter *filter);
 390
 391 static int i40e_tunnel_filter_convert(
 392         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 393         struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 395                                 struct i40e_tunnel_filter *tunnel_filter);
 396 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 397
 398 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 399 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 400 static void i40e_filter_restore(struct i40e_pf *pf);
 401 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 402 static int i40e_pf_config_rss(struct i40e_pf *pf);
 403
 404 static const char *const valid_keys[] = {
 405         ETH_I40E_FLOATING_VEB_ARG,
 406         ETH_I40E_FLOATING_VEB_LIST_ARG,
 407         ETH_I40E_SUPPORT_MULTI_DRIVER,
 408         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 409         ETH_I40E_USE_LATEST_VEC,
 410         ETH_I40E_VF_MSG_CFG,
 411         NULL};
 412
 413 static const struct rte_pci_id pci_id_i40e_map[] = {
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 440         { .vendor_id = 0, /* sentinel */ },
 441 };
 442
 443 static const struct eth_dev_ops i40e_eth_dev_ops = {
 444         .dev_configure                = i40e_dev_configure,
 445         .dev_start                    = i40e_dev_start,
 446         .dev_stop                     = i40e_dev_stop,
 447         .dev_close                    = i40e_dev_close,
 448         .dev_reset                    = i40e_dev_reset,
 449         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 450         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 451         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 452         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 453         .dev_set_link_up              = i40e_dev_set_link_up,
 454         .dev_set_link_down            = i40e_dev_set_link_down,
 455         .link_update                  = i40e_dev_link_update,
 456         .stats_get                    = i40e_dev_stats_get,
 457         .xstats_get                   = i40e_dev_xstats_get,
 458         .xstats_get_names             = i40e_dev_xstats_get_names,
 459         .stats_reset                  = i40e_dev_stats_reset,
 460         .xstats_reset                 = i40e_dev_stats_reset,
 461         .fw_version_get               = i40e_fw_version_get,
 462         .dev_infos_get                = i40e_dev_info_get,
 463         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 464         .vlan_filter_set              = i40e_vlan_filter_set,
 465         .vlan_tpid_set                = i40e_vlan_tpid_set,
 466         .vlan_offload_set             = i40e_vlan_offload_set,
 467         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 468         .vlan_pvid_set                = i40e_vlan_pvid_set,
 469         .rx_queue_start               = i40e_dev_rx_queue_start,
 470         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 471         .tx_queue_start               = i40e_dev_tx_queue_start,
 472         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 473         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 474         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 475         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 476         .rx_queue_release             = i40e_dev_rx_queue_release,
 477         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 478         .tx_queue_release             = i40e_dev_tx_queue_release,
 479         .dev_led_on                   = i40e_dev_led_on,
 480         .dev_led_off                  = i40e_dev_led_off,
 481         .flow_ctrl_get                = i40e_flow_ctrl_get,
 482         .flow_ctrl_set                = i40e_flow_ctrl_set,
 483         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 484         .mac_addr_add                 = i40e_macaddr_add,
 485         .mac_addr_remove              = i40e_macaddr_remove,
 486         .reta_update                  = i40e_dev_rss_reta_update,
 487         .reta_query                   = i40e_dev_rss_reta_query,
 488         .rss_hash_update              = i40e_dev_rss_hash_update,
 489         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 490         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 491         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 492         .filter_ctrl                  = i40e_dev_filter_ctrl,
 493         .rxq_info_get                 = i40e_rxq_info_get,
 494         .txq_info_get                 = i40e_txq_info_get,
 495         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 496         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 497         .mirror_rule_set              = i40e_mirror_rule_set,
 498         .mirror_rule_reset            = i40e_mirror_rule_reset,
 499         .timesync_enable              = i40e_timesync_enable,
 500         .timesync_disable             = i40e_timesync_disable,
 501         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 502         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 503         .get_dcb_info                 = i40e_dev_get_dcb_info,
 504         .timesync_adjust_time         = i40e_timesync_adjust_time,
 505         .timesync_read_time           = i40e_timesync_read_time,
 506         .timesync_write_time          = i40e_timesync_write_time,
 507         .get_reg                      = i40e_get_regs,
 508         .get_eeprom_length            = i40e_get_eeprom_length,
 509         .get_eeprom                   = i40e_get_eeprom,
 510         .get_module_info              = i40e_get_module_info,
 511         .get_module_eeprom            = i40e_get_module_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514         .tm_ops_get                   = i40e_tm_ops_get,
 515         .tx_done_cleanup              = i40e_tx_done_cleanup,
 516 };
 517
 518 /* store statistics names and its offset in stats structure */
 519 struct rte_i40e_xstats_name_off {
 520         char name[RTE_ETH_XSTATS_NAME_SIZE];
 521         unsigned offset;
 522 };
 523
 524 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 525         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 526         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 527         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 528         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 529         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 530                 rx_unknown_protocol)},
 531         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 532         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 533         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 534         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 535 };
 536
 537 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 538                 sizeof(rte_i40e_stats_strings[0]))
 539
 540 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 541         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 542                 tx_dropped_link_down)},
 543         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 544         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 545                 illegal_bytes)},
 546         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 547         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 548                 mac_local_faults)},
 549         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_remote_faults)},
 551         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_length_errors)},
 553         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 554         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 555         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 556         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 557         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 558         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_127)},
 560         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_255)},
 562         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_511)},
 564         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_1023)},
 566         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1522)},
 568         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_big)},
 570         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 571                 rx_undersize)},
 572         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_oversize)},
 574         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 575                 mac_short_packet_dropped)},
 576         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 577                 rx_fragments)},
 578         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 579         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 580         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_127)},
 582         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_255)},
 584         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_511)},
 586         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_1023)},
 588         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1522)},
 590         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_big)},
 592         {"rx_flow_director_atr_match_packets",
 593                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 594         {"rx_flow_director_sb_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 596         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 597                 tx_lpi_status)},
 598         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 rx_lpi_status)},
 600         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 601                 tx_lpi_count)},
 602         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 rx_lpi_count)},
 604 };
 605
 606 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 607                 sizeof(rte_i40e_hw_port_strings[0]))
 608
 609 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 610         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 611                 priority_xon_rx)},
 612         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xoff_rx)},
 614 };
 615
 616 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 617                 sizeof(rte_i40e_rxq_prio_strings[0]))
 618
 619 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 620         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xon_tx)},
 622         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xoff_tx)},
 624         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_2_xoff)},
 626 };
 627
 628 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 629                 sizeof(rte_i40e_txq_prio_strings[0]))
 630
 631 static int
 632 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 633         struct rte_pci_device *pci_dev)
 634 {
 635         char name[RTE_ETH_NAME_MAX_LEN];
 636         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 637         int i, retval;
 638
 639         if (pci_dev->device.devargs) {
 640                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 641                                 &eth_da);
 642                 if (retval)
 643                         return retval;
 644         }
 645
 646         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 647                 sizeof(struct i40e_adapter),
 648                 eth_dev_pci_specific_init, pci_dev,
 649                 eth_i40e_dev_init, NULL);
 650
 651         if (retval || eth_da.nb_representor_ports < 1)
 652                 return retval;
 653
 654         /* probe VF representor ports */
 655         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 656                 pci_dev->device.name);
 657
 658         if (pf_ethdev == NULL)
 659                 return -ENODEV;
 660
 661         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 662                 struct i40e_vf_representor representor = {
 663                         .vf_id = eth_da.representor_ports[i],
 664                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 665                                 pf_ethdev->data->dev_private)->switch_domain_id,
 666                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 667                                 pf_ethdev->data->dev_private)
 668                 };
 669
 670                 /* representor port net_bdf_port */
 671                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 672                         pci_dev->device.name, eth_da.representor_ports[i]);
 673
 674                 retval = rte_eth_dev_create(&pci_dev->device, name,
 675                         sizeof(struct i40e_vf_representor), NULL, NULL,
 676                         i40e_vf_representor_init, &representor);
 677
 678                 if (retval)
 679                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 680                                 "representor %s.", name);
 681         }
 682
 683         return 0;
 684 }
 685
 686 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 687 {
 688         struct rte_eth_dev *ethdev;
 689
 690         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 691         if (!ethdev)
 692                 return 0;
 693
 694         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 695                 return rte_eth_dev_pci_generic_remove(pci_dev,
 696                                         i40e_vf_representor_uninit);
 697         else
 698                 return rte_eth_dev_pci_generic_remove(pci_dev,
 699                                                 eth_i40e_dev_uninit);
 700 }
 701
 702 static struct rte_pci_driver rte_i40e_pmd = {
 703         .id_table = pci_id_i40e_map,
 704         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 705         .probe = eth_i40e_pci_probe,
 706         .remove = eth_i40e_pci_remove,
 707 };
 708
 709 static inline void
 710 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 711                          uint32_t reg_val)
 712 {
 713         uint32_t ori_reg_val;
 714         struct rte_eth_dev *dev;
 715
 716         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 717         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 718         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 719         if (ori_reg_val != reg_val)
 720                 PMD_DRV_LOG(WARNING,
 721                             "i40e device %s changed global register [0x%08x]."
 722                             " original: 0x%08x, new: 0x%08x",
 723                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 724 }
 725
 726 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 727 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 728 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 729
 730 #ifndef I40E_GLQF_ORT
 731 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 732 #endif
 733 #ifndef I40E_GLQF_PIT
 734 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 735 #endif
 736 #ifndef I40E_GLQF_L3_MAP
 737 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 738 #endif
 739
 740 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 741 {
 742         /*
 743          * Initialize registers for parsing packet type of QinQ
 744          * This should be removed from code once proper
 745          * configuration API is added to avoid configuration conflicts
 746          * between ports of the same device.
 747          */
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 750 }
 751
 752 static inline void i40e_config_automask(struct i40e_pf *pf)
 753 {
 754         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 755         uint32_t val;
 756
 757         /* INTENA flag is not auto-cleared for interrupt */
 758         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 759         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 760                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 761
 762         /* If support multi-driver, PF will use INT0. */
 763         if (!pf->support_multi_driver)
 764                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 765
 766         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 767 }
 768
 769 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 770
 771 /*
 772  * Add a ethertype filter to drop all flow control frames transmitted
 773  * from VSIs.
 774 */
 775 static void
 776 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 777 {
 778         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 779         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 780                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 781                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 782         int ret;
 783
 784         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 785                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 786                                 pf->main_vsi_seid, 0,
 787                                 TRUE, NULL, NULL);
 788         if (ret)
 789                 PMD_INIT_LOG(ERR,
 790                         "Failed to add filter to drop flow control frames from VSIs.");
 791 }
 792
 793 static int
 794 floating_veb_list_handler(__rte_unused const char *key,
 795                           const char *floating_veb_value,
 796                           void *opaque)
 797 {
 798         int idx = 0;
 799         unsigned int count = 0;
 800         char *end = NULL;
 801         int min, max;
 802         bool *vf_floating_veb = opaque;
 803
 804         while (isblank(*floating_veb_value))
 805                 floating_veb_value++;
 806
 807         /* Reset floating VEB configuration for VFs */
 808         for (idx = 0; idx < I40E_MAX_VF; idx++)
 809                 vf_floating_veb[idx] = false;
 810
 811         min = I40E_MAX_VF;
 812         do {
 813                 while (isblank(*floating_veb_value))
 814                         floating_veb_value++;
 815                 if (*floating_veb_value == '\0')
 816                         return -1;
 817                 errno = 0;
 818                 idx = strtoul(floating_veb_value, &end, 10);
 819                 if (errno || end == NULL)
 820                         return -1;
 821                 while (isblank(*end))
 822                         end++;
 823                 if (*end == '-') {
 824                         min = idx;
 825                 } else if ((*end == ';') || (*end == '\0')) {
 826                         max = idx;
 827                         if (min == I40E_MAX_VF)
 828                                 min = idx;
 829                         if (max >= I40E_MAX_VF)
 830                                 max = I40E_MAX_VF - 1;
 831                         for (idx = min; idx <= max; idx++) {
 832                                 vf_floating_veb[idx] = true;
 833                                 count++;
 834                         }
 835                         min = I40E_MAX_VF;
 836                 } else {
 837                         return -1;
 838                 }
 839                 floating_veb_value = end + 1;
 840         } while (*end != '\0');
 841
 842         if (count == 0)
 843                 return -1;
 844
 845         return 0;
 846 }
 847
 848 static void
 849 config_vf_floating_veb(struct rte_devargs *devargs,
 850                        uint16_t floating_veb,
 851                        bool *vf_floating_veb)
 852 {
 853         struct rte_kvargs *kvlist;
 854         int i;
 855         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 856
 857         if (!floating_veb)
 858                 return;
 859         /* All the VFs attach to the floating VEB by default
 860          * when the floating VEB is enabled.
 861          */
 862         for (i = 0; i < I40E_MAX_VF; i++)
 863                 vf_floating_veb[i] = true;
 864
 865         if (devargs == NULL)
 866                 return;
 867
 868         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 869         if (kvlist == NULL)
 870                 return;
 871
 872         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 873                 rte_kvargs_free(kvlist);
 874                 return;
 875         }
 876         /* When the floating_veb_list parameter exists, all the VFs
 877          * will attach to the legacy VEB firstly, then configure VFs
 878          * to the floating VEB according to the floating_veb_list.
 879          */
 880         if (rte_kvargs_process(kvlist, floating_veb_list,
 881                                floating_veb_list_handler,
 882                                vf_floating_veb) < 0) {
 883                 rte_kvargs_free(kvlist);
 884                 return;
 885         }
 886         rte_kvargs_free(kvlist);
 887 }
 888
 889 static int
 890 i40e_check_floating_handler(__rte_unused const char *key,
 891                             const char *value,
 892                             __rte_unused void *opaque)
 893 {
 894         if (strcmp(value, "1"))
 895                 return -1;
 896
 897         return 0;
 898 }
 899
 900 static int
 901 is_floating_veb_supported(struct rte_devargs *devargs)
 902 {
 903         struct rte_kvargs *kvlist;
 904         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 905
 906         if (devargs == NULL)
 907                 return 0;
 908
 909         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 910         if (kvlist == NULL)
 911                 return 0;
 912
 913         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 914                 rte_kvargs_free(kvlist);
 915                 return 0;
 916         }
 917         /* Floating VEB is enabled when there's key-value:
 918          * enable_floating_veb=1
 919          */
 920         if (rte_kvargs_process(kvlist, floating_veb_key,
 921                                i40e_check_floating_handler, NULL) < 0) {
 922                 rte_kvargs_free(kvlist);
 923                 return 0;
 924         }
 925         rte_kvargs_free(kvlist);
 926
 927         return 1;
 928 }
 929
 930 static void
 931 config_floating_veb(struct rte_eth_dev *dev)
 932 {
 933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936
 937         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 938
 939         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 940                 pf->floating_veb =
 941                         is_floating_veb_supported(pci_dev->device.devargs);
 942                 config_vf_floating_veb(pci_dev->device.devargs,
 943                                        pf->floating_veb,
 944                                        pf->floating_veb_list);
 945         } else {
 946                 pf->floating_veb = false;
 947         }
 948 }
 949
 950 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 951 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 952
 953 static int
 954 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 955 {
 956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 957         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 958         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 959         int ret;
 960
 961         struct rte_hash_parameters ethertype_hash_params = {
 962                 .name = ethertype_hash_name,
 963                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 964                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 965                 .hash_func = rte_hash_crc,
 966                 .hash_func_init_val = 0,
 967                 .socket_id = rte_socket_id(),
 968         };
 969
 970         /* Initialize ethertype filter rule list and hash */
 971         TAILQ_INIT(&ethertype_rule->ethertype_list);
 972         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 973                  "ethertype_%s", dev->device->name);
 974         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 975         if (!ethertype_rule->hash_table) {
 976                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 977                 return -EINVAL;
 978         }
 979         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 980                                        sizeof(struct i40e_ethertype_filter *) *
 981                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 982                                        0);
 983         if (!ethertype_rule->hash_map) {
 984                 PMD_INIT_LOG(ERR,
 985                              "Failed to allocate memory for ethertype hash map!");
 986                 ret = -ENOMEM;
 987                 goto err_ethertype_hash_map_alloc;
 988         }
 989
 990         return 0;
 991
 992 err_ethertype_hash_map_alloc:
 993         rte_hash_free(ethertype_rule->hash_table);
 994
 995         return ret;
 996 }
 997
 998 static int
 999 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 {
1001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1003         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1004         int ret;
1005
1006         struct rte_hash_parameters tunnel_hash_params = {
1007                 .name = tunnel_hash_name,
1008                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1009                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1010                 .hash_func = rte_hash_crc,
1011                 .hash_func_init_val = 0,
1012                 .socket_id = rte_socket_id(),
1013         };
1014
1015         /* Initialize tunnel filter rule list and hash */
1016         TAILQ_INIT(&tunnel_rule->tunnel_list);
1017         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1018                  "tunnel_%s", dev->device->name);
1019         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1020         if (!tunnel_rule->hash_table) {
1021                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1022                 return -EINVAL;
1023         }
1024         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1025                                     sizeof(struct i40e_tunnel_filter *) *
1026                                     I40E_MAX_TUNNEL_FILTER_NUM,
1027                                     0);
1028         if (!tunnel_rule->hash_map) {
1029                 PMD_INIT_LOG(ERR,
1030                              "Failed to allocate memory for tunnel hash map!");
1031                 ret = -ENOMEM;
1032                 goto err_tunnel_hash_map_alloc;
1033         }
1034
1035         return 0;
1036
1037 err_tunnel_hash_map_alloc:
1038         rte_hash_free(tunnel_rule->hash_table);
1039
1040         return ret;
1041 }
1042
1043 static int
1044 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 {
1046         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1048         struct i40e_fdir_info *fdir_info = &pf->fdir;
1049         char fdir_hash_name[RTE_HASH_NAMESIZE];
1050         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1051         uint32_t best = hw->func_caps.fd_filters_best_effort;
1052         struct rte_bitmap *bmp = NULL;
1053         uint32_t bmp_size;
1054         void *mem = NULL;
1055         uint32_t i = 0;
1056         int ret;
1057
1058         struct rte_hash_parameters fdir_hash_params = {
1059                 .name = fdir_hash_name,
1060                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1061                 .key_len = sizeof(struct i40e_fdir_input),
1062                 .hash_func = rte_hash_crc,
1063                 .hash_func_init_val = 0,
1064                 .socket_id = rte_socket_id(),
1065         };
1066
1067         /* Initialize flow director filter rule list and hash */
1068         TAILQ_INIT(&fdir_info->fdir_list);
1069         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1070                  "fdir_%s", dev->device->name);
1071         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1072         if (!fdir_info->hash_table) {
1073                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1074                 return -EINVAL;
1075         }
1076
1077         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078                                           sizeof(struct i40e_fdir_filter *) *
1079                                           I40E_MAX_FDIR_FILTER_NUM,
1080                                           0);
1081         if (!fdir_info->hash_map) {
1082                 PMD_INIT_LOG(ERR,
1083                              "Failed to allocate memory for fdir hash map!");
1084                 ret = -ENOMEM;
1085                 goto err_fdir_hash_map_alloc;
1086         }
1087
1088         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1089                         sizeof(struct i40e_fdir_filter) *
1090                         I40E_MAX_FDIR_FILTER_NUM,
1091                         0);
1092
1093         if (!fdir_info->fdir_filter_array) {
1094                 PMD_INIT_LOG(ERR,
1095                              "Failed to allocate memory for fdir filter array!");
1096                 ret = -ENOMEM;
1097                 goto err_fdir_filter_array_alloc;
1098         }
1099
1100         fdir_info->fdir_space_size = alloc + best;
1101         fdir_info->fdir_actual_cnt = 0;
1102         fdir_info->fdir_guarantee_total_space = alloc;
1103         fdir_info->fdir_guarantee_free_space =
1104                 fdir_info->fdir_guarantee_total_space;
1105
1106         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1107
1108         fdir_info->fdir_flow_pool.pool =
1109                         rte_zmalloc("i40e_fdir_entry",
1110                                 sizeof(struct i40e_fdir_entry) *
1111                                 fdir_info->fdir_space_size,
1112                                 0);
1113
1114         if (!fdir_info->fdir_flow_pool.pool) {
1115                 PMD_INIT_LOG(ERR,
1116                              "Failed to allocate memory for bitmap flow!");
1117                 ret = -ENOMEM;
1118                 goto err_fdir_bitmap_flow_alloc;
1119         }
1120
1121         for (i = 0; i < fdir_info->fdir_space_size; i++)
1122                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1123
1124         bmp_size =
1125                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1126         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1127         if (mem == NULL) {
1128                 PMD_INIT_LOG(ERR,
1129                              "Failed to allocate memory for fdir bitmap!");
1130                 ret = -ENOMEM;
1131                 goto err_fdir_mem_alloc;
1132         }
1133         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1134         if (bmp == NULL) {
1135                 PMD_INIT_LOG(ERR,
1136                              "Failed to initialization fdir bitmap!");
1137                 ret = -ENOMEM;
1138                 goto err_fdir_bmp_alloc;
1139         }
1140         for (i = 0; i < fdir_info->fdir_space_size; i++)
1141                 rte_bitmap_set(bmp, i);
1142
1143         fdir_info->fdir_flow_pool.bitmap = bmp;
1144
1145         return 0;
1146
1147 err_fdir_bmp_alloc:
1148         rte_free(mem);
1149 err_fdir_mem_alloc:
1150         rte_free(fdir_info->fdir_flow_pool.pool);
1151 err_fdir_bitmap_flow_alloc:
1152         rte_free(fdir_info->fdir_filter_array);
1153 err_fdir_filter_array_alloc:
1154         rte_free(fdir_info->hash_map);
1155 err_fdir_hash_map_alloc:
1156         rte_hash_free(fdir_info->hash_table);
1157
1158         return ret;
1159 }
1160
1161 static void
1162 i40e_init_customized_info(struct i40e_pf *pf)
1163 {
1164         int i;
1165
1166         /* Initialize customized pctype */
1167         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1168                 pf->customized_pctype[i].index = i;
1169                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1170                 pf->customized_pctype[i].valid = false;
1171         }
1172
1173         pf->gtp_support = false;
1174         pf->esp_support = false;
1175 }
1176
1177 static void
1178 i40e_init_filter_invalidation(struct i40e_pf *pf)
1179 {
1180         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1181         struct i40e_fdir_info *fdir_info = &pf->fdir;
1182         uint32_t glqf_ctl_reg = 0;
1183
1184         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1185         if (!pf->support_multi_driver) {
1186                 fdir_info->fdir_invalprio = 1;
1187                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1188                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1189                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1190         } else {
1191                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1192                         fdir_info->fdir_invalprio = 1;
1193                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1194                 } else {
1195                         fdir_info->fdir_invalprio = 0;
1196                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1197                 }
1198         }
1199 }
1200
1201 void
1202 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1203 {
1204         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1206         struct i40e_queue_regions *info = &pf->queue_region;
1207         uint16_t i;
1208
1209         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1210                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1211
1212         memset(info, 0, sizeof(struct i40e_queue_regions));
1213 }
1214
1215 static int
1216 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1217                                const char *value,
1218                                void *opaque)
1219 {
1220         struct i40e_pf *pf;
1221         unsigned long support_multi_driver;
1222         char *end;
1223
1224         pf = (struct i40e_pf *)opaque;
1225
1226         errno = 0;
1227         support_multi_driver = strtoul(value, &end, 10);
1228         if (errno != 0 || end == value || *end != 0) {
1229                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1230                 return -(EINVAL);
1231         }
1232
1233         if (support_multi_driver == 1 || support_multi_driver == 0)
1234                 pf->support_multi_driver = (bool)support_multi_driver;
1235         else
1236                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1237                             "enable global configuration by default."
1238                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1239         return 0;
1240 }
1241
1242 static int
1243 i40e_support_multi_driver(struct rte_eth_dev *dev)
1244 {
1245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1246         struct rte_kvargs *kvlist;
1247         int kvargs_count;
1248
1249         /* Enable global configuration by default */
1250         pf->support_multi_driver = false;
1251
1252         if (!dev->device->devargs)
1253                 return 0;
1254
1255         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1256         if (!kvlist)
1257                 return -EINVAL;
1258
1259         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1260         if (!kvargs_count) {
1261                 rte_kvargs_free(kvlist);
1262                 return 0;
1263         }
1264
1265         if (kvargs_count > 1)
1266                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1267                             "the first invalid or last valid one is used !",
1268                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1269
1270         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1271                                i40e_parse_multi_drv_handler, pf) < 0) {
1272                 rte_kvargs_free(kvlist);
1273                 return -EINVAL;
1274         }
1275
1276         rte_kvargs_free(kvlist);
1277         return 0;
1278 }
1279
1280 static int
1281 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1282                                     uint32_t reg_addr, uint64_t reg_val,
1283                                     struct i40e_asq_cmd_details *cmd_details)
1284 {
1285         uint64_t ori_reg_val;
1286         struct rte_eth_dev *dev;
1287         int ret;
1288
1289         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1290         if (ret != I40E_SUCCESS) {
1291                 PMD_DRV_LOG(ERR,
1292                             "Fail to debug read from 0x%08x",
1293                             reg_addr);
1294                 return -EIO;
1295         }
1296         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1297
1298         if (ori_reg_val != reg_val)
1299                 PMD_DRV_LOG(WARNING,
1300                             "i40e device %s changed global register [0x%08x]."
1301                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1302                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1303
1304         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1305 }
1306
1307 static int
1308 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1309                                 const char *value,
1310                                 void *opaque)
1311 {
1312         struct i40e_adapter *ad = opaque;
1313         int use_latest_vec;
1314
1315         use_latest_vec = atoi(value);
1316
1317         if (use_latest_vec != 0 && use_latest_vec != 1)
1318                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1319
1320         ad->use_latest_vec = (uint8_t)use_latest_vec;
1321
1322         return 0;
1323 }
1324
1325 static int
1326 i40e_use_latest_vec(struct rte_eth_dev *dev)
1327 {
1328         struct i40e_adapter *ad =
1329                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1330         struct rte_kvargs *kvlist;
1331         int kvargs_count;
1332
1333         ad->use_latest_vec = false;
1334
1335         if (!dev->device->devargs)
1336                 return 0;
1337
1338         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1339         if (!kvlist)
1340                 return -EINVAL;
1341
1342         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1343         if (!kvargs_count) {
1344                 rte_kvargs_free(kvlist);
1345                 return 0;
1346         }
1347
1348         if (kvargs_count > 1)
1349                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1350                             "the first invalid or last valid one is used !",
1351                             ETH_I40E_USE_LATEST_VEC);
1352
1353         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1354                                 i40e_parse_latest_vec_handler, ad) < 0) {
1355                 rte_kvargs_free(kvlist);
1356                 return -EINVAL;
1357         }
1358
1359         rte_kvargs_free(kvlist);
1360         return 0;
1361 }
1362
1363 static int
1364 read_vf_msg_config(__rte_unused const char *key,
1365                                const char *value,
1366                                void *opaque)
1367 {
1368         struct i40e_vf_msg_cfg *cfg = opaque;
1369
1370         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1371                         &cfg->ignore_second) != 3) {
1372                 memset(cfg, 0, sizeof(*cfg));
1373                 PMD_DRV_LOG(ERR, "format error! example: "
1374                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1375                 return -EINVAL;
1376         }
1377
1378         /*
1379          * If the message validation function been enabled, the 'period'
1380          * and 'ignore_second' must greater than 0.
1381          */
1382         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1383                 memset(cfg, 0, sizeof(*cfg));
1384                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1385                                 " number must be greater than 0!",
1386                                 ETH_I40E_VF_MSG_CFG);
1387                 return -EINVAL;
1388         }
1389
1390         return 0;
1391 }
1392
1393 static int
1394 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1395                 struct i40e_vf_msg_cfg *msg_cfg)
1396 {
1397         struct rte_kvargs *kvlist;
1398         int kvargs_count;
1399         int ret = 0;
1400
1401         memset(msg_cfg, 0, sizeof(*msg_cfg));
1402
1403         if (!dev->device->devargs)
1404                 return ret;
1405
1406         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1407         if (!kvlist)
1408                 return -EINVAL;
1409
1410         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1411         if (!kvargs_count)
1412                 goto free_end;
1413
1414         if (kvargs_count > 1) {
1415                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1416                                 ETH_I40E_VF_MSG_CFG);
1417                 ret = -EINVAL;
1418                 goto free_end;
1419         }
1420
1421         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1422                         read_vf_msg_config, msg_cfg) < 0)
1423                 ret = -EINVAL;
1424
1425 free_end:
1426         rte_kvargs_free(kvlist);
1427         return ret;
1428 }
1429
1430 #define I40E_ALARM_INTERVAL 50000 /* us */
1431
1432 static int
1433 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1434 {
1435         struct rte_pci_device *pci_dev;
1436         struct rte_intr_handle *intr_handle;
1437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1439         struct i40e_vsi *vsi;
1440         int ret;
1441         uint32_t len, val;
1442         uint8_t aq_fail = 0;
1443
1444         PMD_INIT_FUNC_TRACE();
1445
1446         dev->dev_ops = &i40e_eth_dev_ops;
1447         dev->rx_queue_count = i40e_dev_rx_queue_count;
1448         dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1449         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1450         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1451         dev->rx_pkt_burst = i40e_recv_pkts;
1452         dev->tx_pkt_burst = i40e_xmit_pkts;
1453         dev->tx_pkt_prepare = i40e_prep_pkts;
1454
1455         /* for secondary processes, we don't initialise any further as primary
1456          * has already done this work. Only check we don't need a different
1457          * RX function */
1458         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459                 i40e_set_rx_function(dev);
1460                 i40e_set_tx_function(dev);
1461                 return 0;
1462         }
1463         i40e_set_default_ptype_table(dev);
1464         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1465         intr_handle = &pci_dev->intr_handle;
1466
1467         rte_eth_copy_pci_info(dev, pci_dev);
1468
1469         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1470         pf->adapter->eth_dev = dev;
1471         pf->dev_data = dev->data;
1472
1473         hw->back = I40E_PF_TO_ADAPTER(pf);
1474         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1475         if (!hw->hw_addr) {
1476                 PMD_INIT_LOG(ERR,
1477                         "Hardware is not available, as address is NULL");
1478                 return -ENODEV;
1479         }
1480
1481         hw->vendor_id = pci_dev->id.vendor_id;
1482         hw->device_id = pci_dev->id.device_id;
1483         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1484         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1485         hw->bus.device = pci_dev->addr.devid;
1486         hw->bus.func = pci_dev->addr.function;
1487         hw->adapter_stopped = 0;
1488         hw->adapter_closed = 0;
1489
1490         /* Init switch device pointer */
1491         hw->switch_dev = NULL;
1492
1493         /*
1494          * Switch Tag value should not be identical to either the First Tag
1495          * or Second Tag values. So set something other than common Ethertype
1496          * for internal switching.
1497          */
1498         hw->switch_tag = 0xffff;
1499
1500         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1501         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1502                 PMD_INIT_LOG(ERR, "\nERROR: "
1503                         "Firmware recovery mode detected. Limiting functionality.\n"
1504                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1505                         "User Guide for details on firmware recovery mode.");
1506                 return -EIO;
1507         }
1508
1509         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1510         /* Check if need to support multi-driver */
1511         i40e_support_multi_driver(dev);
1512         /* Check if users want the latest supported vec path */
1513         i40e_use_latest_vec(dev);
1514
1515         /* Make sure all is clean before doing PF reset */
1516         i40e_clear_hw(hw);
1517
1518         /* Reset here to make sure all is clean for each PF */
1519         ret = i40e_pf_reset(hw);
1520         if (ret) {
1521                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1522                 return ret;
1523         }
1524
1525         /* Initialize the shared code (base driver) */
1526         ret = i40e_init_shared_code(hw);
1527         if (ret) {
1528                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1529                 return ret;
1530         }
1531
1532         /* Initialize the parameters for adminq */
1533         i40e_init_adminq_parameter(hw);
1534         ret = i40e_init_adminq(hw);
1535         if (ret != I40E_SUCCESS) {
1536                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1537                 return -EIO;
1538         }
1539         /* Firmware of SFP x722 does not support adminq option */
1540         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1541                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1542
1543         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1544                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1545                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1546                      ((hw->nvm.version >> 12) & 0xf),
1547                      ((hw->nvm.version >> 4) & 0xff),
1548                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1549
1550         /* Initialize the hardware */
1551         i40e_hw_init(dev);
1552
1553         i40e_config_automask(pf);
1554
1555         i40e_set_default_pctype_table(dev);
1556
1557         /*
1558          * To work around the NVM issue, initialize registers
1559          * for packet type of QinQ by software.
1560          * It should be removed once issues are fixed in NVM.
1561          */
1562         if (!pf->support_multi_driver)
1563                 i40e_GLQF_reg_init(hw);
1564
1565         /* Initialize the input set for filters (hash and fd) to default value */
1566         i40e_filter_input_set_init(pf);
1567
1568         /* initialise the L3_MAP register */
1569         if (!pf->support_multi_driver) {
1570                 ret = i40e_aq_debug_write_global_register(hw,
1571                                                    I40E_GLQF_L3_MAP(40),
1572                                                    0x00000028,  NULL);
1573                 if (ret)
1574                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1575                                      ret);
1576                 PMD_INIT_LOG(DEBUG,
1577                              "Global register 0x%08x is changed with 0x28",
1578                              I40E_GLQF_L3_MAP(40));
1579         }
1580
1581         /* Need the special FW version to support floating VEB */
1582         config_floating_veb(dev);
1583         /* Clear PXE mode */
1584         i40e_clear_pxe_mode(hw);
1585         i40e_dev_sync_phy_type(hw);
1586
1587         /*
1588          * On X710, performance number is far from the expectation on recent
1589          * firmware versions. The fix for this issue may not be integrated in
1590          * the following firmware version. So the workaround in software driver
1591          * is needed. It needs to modify the initial values of 3 internal only
1592          * registers. Note that the workaround can be removed when it is fixed
1593          * in firmware in the future.
1594          */
1595         i40e_configure_registers(hw);
1596
1597         /* Get hw capabilities */
1598         ret = i40e_get_cap(hw);
1599         if (ret != I40E_SUCCESS) {
1600                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1601                 goto err_get_capabilities;
1602         }
1603
1604         /* Initialize parameters for PF */
1605         ret = i40e_pf_parameter_init(dev);
1606         if (ret != 0) {
1607                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1608                 goto err_parameter_init;
1609         }
1610
1611         /* Initialize the queue management */
1612         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1613         if (ret < 0) {
1614                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1615                 goto err_qp_pool_init;
1616         }
1617         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1618                                 hw->func_caps.num_msix_vectors - 1);
1619         if (ret < 0) {
1620                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1621                 goto err_msix_pool_init;
1622         }
1623
1624         /* Initialize lan hmc */
1625         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1626                                 hw->func_caps.num_rx_qp, 0, 0);
1627         if (ret != I40E_SUCCESS) {
1628                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1629                 goto err_init_lan_hmc;
1630         }
1631
1632         /* Configure lan hmc */
1633         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1634         if (ret != I40E_SUCCESS) {
1635                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1636                 goto err_configure_lan_hmc;
1637         }
1638
1639         /* Get and check the mac address */
1640         i40e_get_mac_addr(hw, hw->mac.addr);
1641         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1642                 PMD_INIT_LOG(ERR, "mac address is not valid");
1643                 ret = -EIO;
1644                 goto err_get_mac_addr;
1645         }
1646         /* Copy the permanent MAC address */
1647         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1648                         (struct rte_ether_addr *)hw->mac.perm_addr);
1649
1650         /* Disable flow control */
1651         hw->fc.requested_mode = I40E_FC_NONE;
1652         i40e_set_fc(hw, &aq_fail, TRUE);
1653
1654         /* Set the global registers with default ether type value */
1655         if (!pf->support_multi_driver) {
1656                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1657                                          RTE_ETHER_TYPE_VLAN);
1658                 if (ret != I40E_SUCCESS) {
1659                         PMD_INIT_LOG(ERR,
1660                                      "Failed to set the default outer "
1661                                      "VLAN ether type");
1662                         goto err_setup_pf_switch;
1663                 }
1664         }
1665
1666         /* PF setup, which includes VSI setup */
1667         ret = i40e_pf_setup(pf);
1668         if (ret) {
1669                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1670                 goto err_setup_pf_switch;
1671         }
1672
1673         vsi = pf->main_vsi;
1674
1675         /* Disable double vlan by default */
1676         i40e_vsi_config_double_vlan(vsi, FALSE);
1677
1678         /* Disable S-TAG identification when floating_veb is disabled */
1679         if (!pf->floating_veb) {
1680                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1681                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1682                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1683                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1684                 }
1685         }
1686
1687         if (!vsi->max_macaddrs)
1688                 len = RTE_ETHER_ADDR_LEN;
1689         else
1690                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1691
1692         /* Should be after VSI initialized */
1693         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1694         if (!dev->data->mac_addrs) {
1695                 PMD_INIT_LOG(ERR,
1696                         "Failed to allocated memory for storing mac address");
1697                 goto err_mac_alloc;
1698         }
1699         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1700                                         &dev->data->mac_addrs[0]);
1701
1702         /* Pass the information to the rte_eth_dev_close() that it should also
1703          * release the private port resources.
1704          */
1705         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1706
1707         /* Init dcb to sw mode by default */
1708         ret = i40e_dcb_init_configure(dev, TRUE);
1709         if (ret != I40E_SUCCESS) {
1710                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1711                 pf->flags &= ~I40E_FLAG_DCB;
1712         }
1713         /* Update HW struct after DCB configuration */
1714         i40e_get_cap(hw);
1715
1716         /* initialize pf host driver to setup SRIOV resource if applicable */
1717         i40e_pf_host_init(dev);
1718
1719         /* register callback func to eal lib */
1720         rte_intr_callback_register(intr_handle,
1721                                    i40e_dev_interrupt_handler, dev);
1722
1723         /* configure and enable device interrupt */
1724         i40e_pf_config_irq0(hw, TRUE);
1725         i40e_pf_enable_irq0(hw);
1726
1727         /* enable uio intr after callback register */
1728         rte_intr_enable(intr_handle);
1729
1730         /* By default disable flexible payload in global configuration */
1731         if (!pf->support_multi_driver)
1732                 i40e_flex_payload_reg_set_default(hw);
1733
1734         /*
1735          * Add an ethertype filter to drop all flow control frames transmitted
1736          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1737          * frames to wire.
1738          */
1739         i40e_add_tx_flow_control_drop_filter(pf);
1740
1741         /* Set the max frame size to 0x2600 by default,
1742          * in case other drivers changed the default value.
1743          */
1744         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1745
1746         /* initialize mirror rule list */
1747         TAILQ_INIT(&pf->mirror_list);
1748
1749         /* initialize RSS rule list */
1750         TAILQ_INIT(&pf->rss_config_list);
1751
1752         /* initialize Traffic Manager configuration */
1753         i40e_tm_conf_init(dev);
1754
1755         /* Initialize customized information */
1756         i40e_init_customized_info(pf);
1757
1758         /* Initialize the filter invalidation configuration */
1759         i40e_init_filter_invalidation(pf);
1760
1761         ret = i40e_init_ethtype_filter_list(dev);
1762         if (ret < 0)
1763                 goto err_init_ethtype_filter_list;
1764         ret = i40e_init_tunnel_filter_list(dev);
1765         if (ret < 0)
1766                 goto err_init_tunnel_filter_list;
1767         ret = i40e_init_fdir_filter_list(dev);
1768         if (ret < 0)
1769                 goto err_init_fdir_filter_list;
1770
1771         /* initialize queue region configuration */
1772         i40e_init_queue_region_conf(dev);
1773
1774         /* initialize RSS configuration from rte_flow */
1775         memset(&pf->rss_info, 0,
1776                 sizeof(struct i40e_rte_flow_rss_conf));
1777
1778         /* reset all stats of the device, including pf and main vsi */
1779         i40e_dev_stats_reset(dev);
1780
1781         return 0;
1782
1783 err_init_fdir_filter_list:
1784         rte_free(pf->tunnel.hash_table);
1785         rte_free(pf->tunnel.hash_map);
1786 err_init_tunnel_filter_list:
1787         rte_free(pf->ethertype.hash_table);
1788         rte_free(pf->ethertype.hash_map);
1789 err_init_ethtype_filter_list:
1790         rte_free(dev->data->mac_addrs);
1791         dev->data->mac_addrs = NULL;
1792 err_mac_alloc:
1793         i40e_vsi_release(pf->main_vsi);
1794 err_setup_pf_switch:
1795 err_get_mac_addr:
1796 err_configure_lan_hmc:
1797         (void)i40e_shutdown_lan_hmc(hw);
1798 err_init_lan_hmc:
1799         i40e_res_pool_destroy(&pf->msix_pool);
1800 err_msix_pool_init:
1801         i40e_res_pool_destroy(&pf->qp_pool);
1802 err_qp_pool_init:
1803 err_parameter_init:
1804 err_get_capabilities:
1805         (void)i40e_shutdown_adminq(hw);
1806
1807         return ret;
1808 }
1809
1810 static void
1811 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1812 {
1813         struct i40e_ethertype_filter *p_ethertype;
1814         struct i40e_ethertype_rule *ethertype_rule;
1815
1816         ethertype_rule = &pf->ethertype;
1817         /* Remove all ethertype filter rules and hash */
1818         if (ethertype_rule->hash_map)
1819                 rte_free(ethertype_rule->hash_map);
1820         if (ethertype_rule->hash_table)
1821                 rte_hash_free(ethertype_rule->hash_table);
1822
1823         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1824                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1825                              p_ethertype, rules);
1826                 rte_free(p_ethertype);
1827         }
1828 }
1829
1830 static void
1831 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1832 {
1833         struct i40e_tunnel_filter *p_tunnel;
1834         struct i40e_tunnel_rule *tunnel_rule;
1835
1836         tunnel_rule = &pf->tunnel;
1837         /* Remove all tunnel director rules and hash */
1838         if (tunnel_rule->hash_map)
1839                 rte_free(tunnel_rule->hash_map);
1840         if (tunnel_rule->hash_table)
1841                 rte_hash_free(tunnel_rule->hash_table);
1842
1843         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1844                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1845                 rte_free(p_tunnel);
1846         }
1847 }
1848
1849 static void
1850 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1851 {
1852         struct i40e_fdir_filter *p_fdir;
1853         struct i40e_fdir_info *fdir_info;
1854
1855         fdir_info = &pf->fdir;
1856
1857         /* Remove all flow director rules */
1858         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1859                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1860 }
1861
1862 static void
1863 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1864 {
1865         struct i40e_fdir_info *fdir_info;
1866
1867         fdir_info = &pf->fdir;
1868
1869         /* flow director memory cleanup */
1870         if (fdir_info->hash_map)
1871                 rte_free(fdir_info->hash_map);
1872         if (fdir_info->hash_table)
1873                 rte_hash_free(fdir_info->hash_table);
1874         if (fdir_info->fdir_flow_pool.bitmap)
1875                 rte_free(fdir_info->fdir_flow_pool.bitmap);
1876         if (fdir_info->fdir_flow_pool.pool)
1877                 rte_free(fdir_info->fdir_flow_pool.pool);
1878         if (fdir_info->fdir_filter_array)
1879                 rte_free(fdir_info->fdir_filter_array);
1880 }
1881
1882 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1883 {
1884         /*
1885          * Disable by default flexible payload
1886          * for corresponding L2/L3/L4 layers.
1887          */
1888         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1889         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1890         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1891 }
1892
1893 static int
1894 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1895 {
1896         struct i40e_hw *hw;
1897
1898         PMD_INIT_FUNC_TRACE();
1899
1900         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1901                 return 0;
1902
1903         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904
1905         if (hw->adapter_closed == 0)
1906                 i40e_dev_close(dev);
1907
1908         return 0;
1909 }
1910
1911 static int
1912 i40e_dev_configure(struct rte_eth_dev *dev)
1913 {
1914         struct i40e_adapter *ad =
1915                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1919         int i, ret;
1920
1921         ret = i40e_dev_sync_phy_type(hw);
1922         if (ret)
1923                 return ret;
1924
1925         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1926          * bulk allocation or vector Rx preconditions we will reset it.
1927          */
1928         ad->rx_bulk_alloc_allowed = true;
1929         ad->rx_vec_allowed = true;
1930         ad->tx_simple_allowed = true;
1931         ad->tx_vec_allowed = true;
1932
1933         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1934                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1935
1936         /* Only legacy filter API needs the following fdir config. So when the
1937          * legacy filter API is deprecated, the following codes should also be
1938          * removed.
1939          */
1940         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1941                 ret = i40e_fdir_setup(pf);
1942                 if (ret != I40E_SUCCESS) {
1943                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1944                         return -ENOTSUP;
1945                 }
1946                 ret = i40e_fdir_configure(dev);
1947                 if (ret < 0) {
1948                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1949                         goto err;
1950                 }
1951         } else
1952                 i40e_fdir_teardown(pf);
1953
1954         ret = i40e_dev_init_vlan(dev);
1955         if (ret < 0)
1956                 goto err;
1957
1958         /* VMDQ setup.
1959          *  General PMD driver call sequence are NIC init, configure,
1960          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1961          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1962          *  applicable. So, VMDQ setting has to be done before
1963          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1964          *  For RSS setting, it will try to calculate actual configured RX queue
1965          *  number, which will be available after rx_queue_setup(). dev_start()
1966          *  function is good to place RSS setup.
1967          */
1968         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1969                 ret = i40e_vmdq_setup(dev);
1970                 if (ret)
1971                         goto err;
1972         }
1973
1974         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1975                 ret = i40e_dcb_setup(dev);
1976                 if (ret) {
1977                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1978                         goto err_dcb;
1979                 }
1980         }
1981
1982         TAILQ_INIT(&pf->flow_list);
1983
1984         return 0;
1985
1986 err_dcb:
1987         /* need to release vmdq resource if exists */
1988         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989                 i40e_vsi_release(pf->vmdq[i].vsi);
1990                 pf->vmdq[i].vsi = NULL;
1991         }
1992         rte_free(pf->vmdq);
1993         pf->vmdq = NULL;
1994 err:
1995         /* Need to release fdir resource if exists.
1996          * Only legacy filter API needs the following fdir config. So when the
1997          * legacy filter API is deprecated, the following code should also be
1998          * removed.
1999          */
2000         i40e_fdir_teardown(pf);
2001         return ret;
2002 }
2003
2004 void
2005 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2006 {
2007         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011         uint16_t msix_vect = vsi->msix_intr;
2012         uint16_t i;
2013
2014         for (i = 0; i < vsi->nb_qps; i++) {
2015                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2017                 rte_wmb();
2018         }
2019
2020         if (vsi->type != I40E_VSI_SRIOV) {
2021                 if (!rte_intr_allow_others(intr_handle)) {
2022                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2023                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2024                         I40E_WRITE_REG(hw,
2025                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2026                                        0);
2027                 } else {
2028                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2029                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2030                         I40E_WRITE_REG(hw,
2031                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2032                                                        msix_vect - 1), 0);
2033                 }
2034         } else {
2035                 uint32_t reg;
2036                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2037                         vsi->user_param + (msix_vect - 1);
2038
2039                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2040                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2041         }
2042         I40E_WRITE_FLUSH(hw);
2043 }
2044
2045 static void
2046 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2047                        int base_queue, int nb_queue,
2048                        uint16_t itr_idx)
2049 {
2050         int i;
2051         uint32_t val;
2052         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2054
2055         /* Bind all RX queues to allocated MSIX interrupt */
2056         for (i = 0; i < nb_queue; i++) {
2057                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2058                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2059                         ((base_queue + i + 1) <<
2060                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2061                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2062                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2063
2064                 if (i == nb_queue - 1)
2065                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2066                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2067         }
2068
2069         /* Write first RX queue to Link list register as the head element */
2070         if (vsi->type != I40E_VSI_SRIOV) {
2071                 uint16_t interval =
2072                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2073
2074                 if (msix_vect == I40E_MISC_VEC_ID) {
2075                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2076                                        (base_queue <<
2077                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2078                                        (0x0 <<
2079                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2080                         I40E_WRITE_REG(hw,
2081                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2082                                        interval);
2083                 } else {
2084                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2085                                        (base_queue <<
2086                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2087                                        (0x0 <<
2088                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2089                         I40E_WRITE_REG(hw,
2090                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2091                                                        msix_vect - 1),
2092                                        interval);
2093                 }
2094         } else {
2095                 uint32_t reg;
2096
2097                 if (msix_vect == I40E_MISC_VEC_ID) {
2098                         I40E_WRITE_REG(hw,
2099                                        I40E_VPINT_LNKLST0(vsi->user_param),
2100                                        (base_queue <<
2101                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2102                                        (0x0 <<
2103                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2104                 } else {
2105                         /* num_msix_vectors_vf needs to minus irq0 */
2106                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2107                                 vsi->user_param + (msix_vect - 1);
2108
2109                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2110                                        (base_queue <<
2111                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2112                                        (0x0 <<
2113                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2114                 }
2115         }
2116
2117         I40E_WRITE_FLUSH(hw);
2118 }
2119
2120 int
2121 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2122 {
2123         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2124         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2126         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2127         uint16_t msix_vect = vsi->msix_intr;
2128         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2129         uint16_t queue_idx = 0;
2130         int record = 0;
2131         int i;
2132
2133         for (i = 0; i < vsi->nb_qps; i++) {
2134                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2135                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2136         }
2137
2138         /* VF bind interrupt */
2139         if (vsi->type == I40E_VSI_SRIOV) {
2140                 if (vsi->nb_msix == 0) {
2141                         PMD_DRV_LOG(ERR, "No msix resource");
2142                         return -EINVAL;
2143                 }
2144                 __vsi_queues_bind_intr(vsi, msix_vect,
2145                                        vsi->base_queue, vsi->nb_qps,
2146                                        itr_idx);
2147                 return 0;
2148         }
2149
2150         /* PF & VMDq bind interrupt */
2151         if (rte_intr_dp_is_en(intr_handle)) {
2152                 if (vsi->type == I40E_VSI_MAIN) {
2153                         queue_idx = 0;
2154                         record = 1;
2155                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2156                         struct i40e_vsi *main_vsi =
2157                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2158                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2159                         record = 1;
2160                 }
2161         }
2162
2163         for (i = 0; i < vsi->nb_used_qps; i++) {
2164                 if (vsi->nb_msix == 0) {
2165                         PMD_DRV_LOG(ERR, "No msix resource");
2166                         return -EINVAL;
2167                 } else if (nb_msix <= 1) {
2168                         if (!rte_intr_allow_others(intr_handle))
2169                                 /* allow to share MISC_VEC_ID */
2170                                 msix_vect = I40E_MISC_VEC_ID;
2171
2172                         /* no enough msix_vect, map all to one */
2173                         __vsi_queues_bind_intr(vsi, msix_vect,
2174                                                vsi->base_queue + i,
2175                                                vsi->nb_used_qps - i,
2176                                                itr_idx);
2177                         for (; !!record && i < vsi->nb_used_qps; i++)
2178                                 intr_handle->intr_vec[queue_idx + i] =
2179                                         msix_vect;
2180                         break;
2181                 }
2182                 /* 1:1 queue/msix_vect mapping */
2183                 __vsi_queues_bind_intr(vsi, msix_vect,
2184                                        vsi->base_queue + i, 1,
2185                                        itr_idx);
2186                 if (!!record)
2187                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2188
2189                 msix_vect++;
2190                 nb_msix--;
2191         }
2192
2193         return 0;
2194 }
2195
2196 void
2197 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2198 {
2199         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2200         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2202         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2203         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2204         uint16_t msix_intr, i;
2205
2206         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2207                 for (i = 0; i < vsi->nb_msix; i++) {
2208                         msix_intr = vsi->msix_intr + i;
2209                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2210                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2211                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2212                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2213                 }
2214         else
2215                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2216                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2217                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2218                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2219
2220         I40E_WRITE_FLUSH(hw);
2221 }
2222
2223 void
2224 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2225 {
2226         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2227         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2229         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2230         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2231         uint16_t msix_intr, i;
2232
2233         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2234                 for (i = 0; i < vsi->nb_msix; i++) {
2235                         msix_intr = vsi->msix_intr + i;
2236                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2237                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2238                 }
2239         else
2240                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2241                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2242
2243         I40E_WRITE_FLUSH(hw);
2244 }
2245
2246 static inline uint8_t
2247 i40e_parse_link_speeds(uint16_t link_speeds)
2248 {
2249         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2250
2251         if (link_speeds & ETH_LINK_SPEED_40G)
2252                 link_speed |= I40E_LINK_SPEED_40GB;
2253         if (link_speeds & ETH_LINK_SPEED_25G)
2254                 link_speed |= I40E_LINK_SPEED_25GB;
2255         if (link_speeds & ETH_LINK_SPEED_20G)
2256                 link_speed |= I40E_LINK_SPEED_20GB;
2257         if (link_speeds & ETH_LINK_SPEED_10G)
2258                 link_speed |= I40E_LINK_SPEED_10GB;
2259         if (link_speeds & ETH_LINK_SPEED_1G)
2260                 link_speed |= I40E_LINK_SPEED_1GB;
2261         if (link_speeds & ETH_LINK_SPEED_100M)
2262                 link_speed |= I40E_LINK_SPEED_100MB;
2263
2264         return link_speed;
2265 }
2266
2267 static int
2268 i40e_phy_conf_link(struct i40e_hw *hw,
2269                    uint8_t abilities,
2270                    uint8_t force_speed,
2271                    bool is_up)
2272 {
2273         enum i40e_status_code status;
2274         struct i40e_aq_get_phy_abilities_resp phy_ab;
2275         struct i40e_aq_set_phy_config phy_conf;
2276         enum i40e_aq_phy_type cnt;
2277         uint8_t avail_speed;
2278         uint32_t phy_type_mask = 0;
2279
2280         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2281                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2282                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2283                         I40E_AQ_PHY_FLAG_LOW_POWER;
2284         int ret = -ENOTSUP;
2285
2286         /* To get phy capabilities of available speeds. */
2287         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2288                                               NULL);
2289         if (status) {
2290                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2291                                 status);
2292                 return ret;
2293         }
2294         avail_speed = phy_ab.link_speed;
2295
2296         /* To get the current phy config. */
2297         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2298                                               NULL);
2299         if (status) {
2300                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2301                                 status);
2302                 return ret;
2303         }
2304
2305         /* If link needs to go up and it is in autoneg mode the speed is OK,
2306          * no need to set up again.
2307          */
2308         if (is_up && phy_ab.phy_type != 0 &&
2309                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2310                      phy_ab.link_speed != 0)
2311                 return I40E_SUCCESS;
2312
2313         memset(&phy_conf, 0, sizeof(phy_conf));
2314
2315         /* bits 0-2 use the values from get_phy_abilities_resp */
2316         abilities &= ~mask;
2317         abilities |= phy_ab.abilities & mask;
2318
2319         phy_conf.abilities = abilities;
2320
2321         /* If link needs to go up, but the force speed is not supported,
2322          * Warn users and config the default available speeds.
2323          */
2324         if (is_up && !(force_speed & avail_speed)) {
2325                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2326                 phy_conf.link_speed = avail_speed;
2327         } else {
2328                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2329         }
2330
2331         /* PHY type mask needs to include each type except PHY type extension */
2332         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2333                 phy_type_mask |= 1 << cnt;
2334
2335         /* use get_phy_abilities_resp value for the rest */
2336         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2337         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2338                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2339                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2340         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2341         phy_conf.eee_capability = phy_ab.eee_capability;
2342         phy_conf.eeer = phy_ab.eeer_val;
2343         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2344
2345         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2346                     phy_ab.abilities, phy_ab.link_speed);
2347         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2348                     phy_conf.abilities, phy_conf.link_speed);
2349
2350         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2351         if (status)
2352                 return ret;
2353
2354         return I40E_SUCCESS;
2355 }
2356
2357 static int
2358 i40e_apply_link_speed(struct rte_eth_dev *dev)
2359 {
2360         uint8_t speed;
2361         uint8_t abilities = 0;
2362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363         struct rte_eth_conf *conf = &dev->data->dev_conf;
2364
2365         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2366                      I40E_AQ_PHY_LINK_ENABLED;
2367
2368         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2369                 conf->link_speeds = ETH_LINK_SPEED_40G |
2370                                     ETH_LINK_SPEED_25G |
2371                                     ETH_LINK_SPEED_20G |
2372                                     ETH_LINK_SPEED_10G |
2373                                     ETH_LINK_SPEED_1G |
2374                                     ETH_LINK_SPEED_100M;
2375
2376                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2377         } else {
2378                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2379         }
2380         speed = i40e_parse_link_speeds(conf->link_speeds);
2381
2382         return i40e_phy_conf_link(hw, abilities, speed, true);
2383 }
2384
2385 static int
2386 i40e_dev_start(struct rte_eth_dev *dev)
2387 {
2388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390         struct i40e_vsi *main_vsi = pf->main_vsi;
2391         int ret, i;
2392         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2393         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394         uint32_t intr_vector = 0;
2395         struct i40e_vsi *vsi;
2396         uint16_t nb_rxq, nb_txq;
2397
2398         hw->adapter_stopped = 0;
2399
2400         rte_intr_disable(intr_handle);
2401
2402         if ((rte_intr_cap_multiple(intr_handle) ||
2403              !RTE_ETH_DEV_SRIOV(dev).active) &&
2404             dev->data->dev_conf.intr_conf.rxq != 0) {
2405                 intr_vector = dev->data->nb_rx_queues;
2406                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2407                 if (ret)
2408                         return ret;
2409         }
2410
2411         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2412                 intr_handle->intr_vec =
2413                         rte_zmalloc("intr_vec",
2414                                     dev->data->nb_rx_queues * sizeof(int),
2415                                     0);
2416                 if (!intr_handle->intr_vec) {
2417                         PMD_INIT_LOG(ERR,
2418                                 "Failed to allocate %d rx_queues intr_vec",
2419                                 dev->data->nb_rx_queues);
2420                         return -ENOMEM;
2421                 }
2422         }
2423
2424         /* Initialize VSI */
2425         ret = i40e_dev_rxtx_init(pf);
2426         if (ret != I40E_SUCCESS) {
2427                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2428                 return ret;
2429         }
2430
2431         /* Map queues with MSIX interrupt */
2432         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2433                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2434         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2435         if (ret < 0)
2436                 return ret;
2437         i40e_vsi_enable_queues_intr(main_vsi);
2438
2439         /* Map VMDQ VSI queues with MSIX interrupt */
2440         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2441                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2442                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2443                                                 I40E_ITR_INDEX_DEFAULT);
2444                 if (ret < 0)
2445                         return ret;
2446                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2447         }
2448
2449         /* Enable all queues which have been configured */
2450         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2451                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2452                 if (ret)
2453                         goto rx_err;
2454         }
2455
2456         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2457                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2458                 if (ret)
2459                         goto tx_err;
2460         }
2461
2462         /* Enable receiving broadcast packets */
2463         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2464         if (ret != I40E_SUCCESS)
2465                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2466
2467         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2468                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2469                                                 true, NULL);
2470                 if (ret != I40E_SUCCESS)
2471                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2472         }
2473
2474         /* Enable the VLAN promiscuous mode. */
2475         if (pf->vfs) {
2476                 for (i = 0; i < pf->vf_num; i++) {
2477                         vsi = pf->vfs[i].vsi;
2478                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2479                                                      true, NULL);
2480                 }
2481         }
2482
2483         /* Enable mac loopback mode */
2484         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2485             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2486                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2487                 if (ret != I40E_SUCCESS) {
2488                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2489                         goto tx_err;
2490                 }
2491         }
2492
2493         /* Apply link configure */
2494         ret = i40e_apply_link_speed(dev);
2495         if (I40E_SUCCESS != ret) {
2496                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2497                 goto tx_err;
2498         }
2499
2500         if (!rte_intr_allow_others(intr_handle)) {
2501                 rte_intr_callback_unregister(intr_handle,
2502                                              i40e_dev_interrupt_handler,
2503                                              (void *)dev);
2504                 /* configure and enable device interrupt */
2505                 i40e_pf_config_irq0(hw, FALSE);
2506                 i40e_pf_enable_irq0(hw);
2507
2508                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2509                         PMD_INIT_LOG(INFO,
2510                                 "lsc won't enable because of no intr multiplex");
2511         } else {
2512                 ret = i40e_aq_set_phy_int_mask(hw,
2513                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2514                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2515                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2516                 if (ret != I40E_SUCCESS)
2517                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2518
2519                 /* Call get_link_info aq commond to enable/disable LSE */
2520                 i40e_dev_link_update(dev, 0);
2521         }
2522
2523         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2524                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2525                                   i40e_dev_alarm_handler, dev);
2526         } else {
2527                 /* enable uio intr after callback register */
2528                 rte_intr_enable(intr_handle);
2529         }
2530
2531         i40e_filter_restore(pf);
2532
2533         if (pf->tm_conf.root && !pf->tm_conf.committed)
2534                 PMD_DRV_LOG(WARNING,
2535                             "please call hierarchy_commit() "
2536                             "before starting the port");
2537
2538         return I40E_SUCCESS;
2539
2540 tx_err:
2541         for (i = 0; i < nb_txq; i++)
2542                 i40e_dev_tx_queue_stop(dev, i);
2543 rx_err:
2544         for (i = 0; i < nb_rxq; i++)
2545                 i40e_dev_rx_queue_stop(dev, i);
2546
2547         return ret;
2548 }
2549
2550 static void
2551 i40e_dev_stop(struct rte_eth_dev *dev)
2552 {
2553         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         struct i40e_vsi *main_vsi = pf->main_vsi;
2556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2558         int i;
2559
2560         if (hw->adapter_stopped == 1)
2561                 return;
2562
2563         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2564                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2565                 rte_intr_enable(intr_handle);
2566         }
2567
2568         /* Disable all queues */
2569         for (i = 0; i < dev->data->nb_tx_queues; i++)
2570                 i40e_dev_tx_queue_stop(dev, i);
2571
2572         for (i = 0; i < dev->data->nb_rx_queues; i++)
2573                 i40e_dev_rx_queue_stop(dev, i);
2574
2575         /* un-map queues with interrupt registers */
2576         i40e_vsi_disable_queues_intr(main_vsi);
2577         i40e_vsi_queues_unbind_intr(main_vsi);
2578
2579         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2580                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2581                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2582         }
2583
2584         /* Clear all queues and release memory */
2585         i40e_dev_clear_queues(dev);
2586
2587         /* Set link down */
2588         i40e_dev_set_link_down(dev);
2589
2590         if (!rte_intr_allow_others(intr_handle))
2591                 /* resume to the default handler */
2592                 rte_intr_callback_register(intr_handle,
2593                                            i40e_dev_interrupt_handler,
2594                                            (void *)dev);
2595
2596         /* Clean datapath event and queue/vec mapping */
2597         rte_intr_efd_disable(intr_handle);
2598         if (intr_handle->intr_vec) {
2599                 rte_free(intr_handle->intr_vec);
2600                 intr_handle->intr_vec = NULL;
2601         }
2602
2603         /* reset hierarchy commit */
2604         pf->tm_conf.committed = false;
2605
2606         hw->adapter_stopped = 1;
2607
2608         pf->adapter->rss_reta_updated = 0;
2609 }
2610
2611 static int
2612 i40e_dev_close(struct rte_eth_dev *dev)
2613 {
2614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2618         struct i40e_mirror_rule *p_mirror;
2619         struct i40e_filter_control_settings settings;
2620         struct rte_flow *p_flow;
2621         uint32_t reg;
2622         int i;
2623         int ret;
2624         uint8_t aq_fail = 0;
2625         int retries = 0;
2626
2627         PMD_INIT_FUNC_TRACE();
2628
2629         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2630         if (ret)
2631                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2632
2633
2634         i40e_dev_stop(dev);
2635
2636         /* Remove all mirror rules */
2637         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2638                 ret = i40e_aq_del_mirror_rule(hw,
2639                                               pf->main_vsi->veb->seid,
2640                                               p_mirror->rule_type,
2641                                               p_mirror->entries,
2642                                               p_mirror->num_entries,
2643                                               p_mirror->id);
2644                 if (ret < 0)
2645                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2646                                     "status = %d, aq_err = %d.", ret,
2647                                     hw->aq.asq_last_status);
2648
2649                 /* remove mirror software resource anyway */
2650                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2651                 rte_free(p_mirror);
2652                 pf->nb_mirror_rule--;
2653         }
2654
2655         i40e_dev_free_queues(dev);
2656
2657         /* Disable interrupt */
2658         i40e_pf_disable_irq0(hw);
2659         rte_intr_disable(intr_handle);
2660
2661         /*
2662          * Only legacy filter API needs the following fdir config. So when the
2663          * legacy filter API is deprecated, the following code should also be
2664          * removed.
2665          */
2666         i40e_fdir_teardown(pf);
2667
2668         /* shutdown and destroy the HMC */
2669         i40e_shutdown_lan_hmc(hw);
2670
2671         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2672                 i40e_vsi_release(pf->vmdq[i].vsi);
2673                 pf->vmdq[i].vsi = NULL;
2674         }
2675         rte_free(pf->vmdq);
2676         pf->vmdq = NULL;
2677
2678         /* release all the existing VSIs and VEBs */
2679         i40e_vsi_release(pf->main_vsi);
2680
2681         /* shutdown the adminq */
2682         i40e_aq_queue_shutdown(hw, true);
2683         i40e_shutdown_adminq(hw);
2684
2685         i40e_res_pool_destroy(&pf->qp_pool);
2686         i40e_res_pool_destroy(&pf->msix_pool);
2687
2688         /* Disable flexible payload in global configuration */
2689         if (!pf->support_multi_driver)
2690                 i40e_flex_payload_reg_set_default(hw);
2691
2692         /* force a PF reset to clean anything leftover */
2693         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2694         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2695                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2696         I40E_WRITE_FLUSH(hw);
2697
2698         dev->dev_ops = NULL;
2699         dev->rx_pkt_burst = NULL;
2700         dev->tx_pkt_burst = NULL;
2701
2702         /* Clear PXE mode */
2703         i40e_clear_pxe_mode(hw);
2704
2705         /* Unconfigure filter control */
2706         memset(&settings, 0, sizeof(settings));
2707         ret = i40e_set_filter_control(hw, &settings);
2708         if (ret)
2709                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2710                                         ret);
2711
2712         /* Disable flow control */
2713         hw->fc.requested_mode = I40E_FC_NONE;
2714         i40e_set_fc(hw, &aq_fail, TRUE);
2715
2716         /* uninitialize pf host driver */
2717         i40e_pf_host_uninit(dev);
2718
2719         do {
2720                 ret = rte_intr_callback_unregister(intr_handle,
2721                                 i40e_dev_interrupt_handler, dev);
2722                 if (ret >= 0 || ret == -ENOENT) {
2723                         break;
2724                 } else if (ret != -EAGAIN) {
2725                         PMD_INIT_LOG(ERR,
2726                                  "intr callback unregister failed: %d",
2727                                  ret);
2728                 }
2729                 i40e_msec_delay(500);
2730         } while (retries++ < 5);
2731
2732         i40e_rm_ethtype_filter_list(pf);
2733         i40e_rm_tunnel_filter_list(pf);
2734         i40e_rm_fdir_filter_list(pf);
2735
2736         /* Remove all flows */
2737         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2738                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2739                 /* Do not free FDIR flows since they are static allocated */
2740                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2741                         rte_free(p_flow);
2742         }
2743
2744         /* release the fdir static allocated memory */
2745         i40e_fdir_memory_cleanup(pf);
2746
2747         /* Remove all Traffic Manager configuration */
2748         i40e_tm_conf_uninit(dev);
2749
2750         hw->adapter_closed = 1;
2751         return 0;
2752 }
2753
2754 /*
2755  * Reset PF device only to re-initialize resources in PMD layer
2756  */
2757 static int
2758 i40e_dev_reset(struct rte_eth_dev *dev)
2759 {
2760         int ret;
2761
2762         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2763          * its VF to make them align with it. The detailed notification
2764          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2765          * To avoid unexpected behavior in VF, currently reset of PF with
2766          * SR-IOV activation is not supported. It might be supported later.
2767          */
2768         if (dev->data->sriov.active)
2769                 return -ENOTSUP;
2770
2771         ret = eth_i40e_dev_uninit(dev);
2772         if (ret)
2773                 return ret;
2774
2775         ret = eth_i40e_dev_init(dev, NULL);
2776
2777         return ret;
2778 }
2779
2780 static int
2781 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2782 {
2783         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2784         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2785         struct i40e_vsi *vsi = pf->main_vsi;
2786         int status;
2787
2788         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2789                                                      true, NULL, true);
2790         if (status != I40E_SUCCESS) {
2791                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2792                 return -EAGAIN;
2793         }
2794
2795         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2796                                                         TRUE, NULL);
2797         if (status != I40E_SUCCESS) {
2798                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2799                 /* Rollback unicast promiscuous mode */
2800                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2801                                                     false, NULL, true);
2802                 return -EAGAIN;
2803         }
2804
2805         return 0;
2806 }
2807
2808 static int
2809 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2810 {
2811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         struct i40e_vsi *vsi = pf->main_vsi;
2814         int status;
2815
2816         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2817                                                      false, NULL, true);
2818         if (status != I40E_SUCCESS) {
2819                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2820                 return -EAGAIN;
2821         }
2822
2823         /* must remain in all_multicast mode */
2824         if (dev->data->all_multicast == 1)
2825                 return 0;
2826
2827         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2828                                                         false, NULL);
2829         if (status != I40E_SUCCESS) {
2830                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2831                 /* Rollback unicast promiscuous mode */
2832                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2833                                                     true, NULL, true);
2834                 return -EAGAIN;
2835         }
2836
2837         return 0;
2838 }
2839
2840 static int
2841 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2842 {
2843         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845         struct i40e_vsi *vsi = pf->main_vsi;
2846         int ret;
2847
2848         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2849         if (ret != I40E_SUCCESS) {
2850                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2851                 return -EAGAIN;
2852         }
2853
2854         return 0;
2855 }
2856
2857 static int
2858 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2859 {
2860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         struct i40e_vsi *vsi = pf->main_vsi;
2863         int ret;
2864
2865         if (dev->data->promiscuous == 1)
2866                 return 0; /* must remain in all_multicast mode */
2867
2868         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2869                                 vsi->seid, FALSE, NULL);
2870         if (ret != I40E_SUCCESS) {
2871                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2872                 return -EAGAIN;
2873         }
2874
2875         return 0;
2876 }
2877
2878 /*
2879  * Set device link up.
2880  */
2881 static int
2882 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2883 {
2884         /* re-apply link speed setting */
2885         return i40e_apply_link_speed(dev);
2886 }
2887
2888 /*
2889  * Set device link down.
2890  */
2891 static int
2892 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2893 {
2894         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2895         uint8_t abilities = 0;
2896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897
2898         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2899         return i40e_phy_conf_link(hw, abilities, speed, false);
2900 }
2901
2902 static __rte_always_inline void
2903 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2904 {
2905 /* Link status registers and values*/
2906 #define I40E_PRTMAC_LINKSTA             0x001E2420
2907 #define I40E_REG_LINK_UP                0x40000080
2908 #define I40E_PRTMAC_MACC                0x001E24E0
2909 #define I40E_REG_MACC_25GB              0x00020000
2910 #define I40E_REG_SPEED_MASK             0x38000000
2911 #define I40E_REG_SPEED_0                0x00000000
2912 #define I40E_REG_SPEED_1                0x08000000
2913 #define I40E_REG_SPEED_2                0x10000000
2914 #define I40E_REG_SPEED_3                0x18000000
2915 #define I40E_REG_SPEED_4                0x20000000
2916         uint32_t link_speed;
2917         uint32_t reg_val;
2918
2919         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2920         link_speed = reg_val & I40E_REG_SPEED_MASK;
2921         reg_val &= I40E_REG_LINK_UP;
2922         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2923
2924         if (unlikely(link->link_status == 0))
2925                 return;
2926
2927         /* Parse the link status */
2928         switch (link_speed) {
2929         case I40E_REG_SPEED_0:
2930                 link->link_speed = ETH_SPEED_NUM_100M;
2931                 break;
2932         case I40E_REG_SPEED_1:
2933                 link->link_speed = ETH_SPEED_NUM_1G;
2934                 break;
2935         case I40E_REG_SPEED_2:
2936                 if (hw->mac.type == I40E_MAC_X722)
2937                         link->link_speed = ETH_SPEED_NUM_2_5G;
2938                 else
2939                         link->link_speed = ETH_SPEED_NUM_10G;
2940                 break;
2941         case I40E_REG_SPEED_3:
2942                 if (hw->mac.type == I40E_MAC_X722) {
2943                         link->link_speed = ETH_SPEED_NUM_5G;
2944                 } else {
2945                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2946
2947                         if (reg_val & I40E_REG_MACC_25GB)
2948                                 link->link_speed = ETH_SPEED_NUM_25G;
2949                         else
2950                                 link->link_speed = ETH_SPEED_NUM_40G;
2951                 }
2952                 break;
2953         case I40E_REG_SPEED_4:
2954                 if (hw->mac.type == I40E_MAC_X722)
2955                         link->link_speed = ETH_SPEED_NUM_10G;
2956                 else
2957                         link->link_speed = ETH_SPEED_NUM_20G;
2958                 break;
2959         default:
2960                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2961                 break;
2962         }
2963 }
2964
2965 static __rte_always_inline void
2966 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2967         bool enable_lse, int wait_to_complete)
2968 {
2969 #define CHECK_INTERVAL             100  /* 100ms */
2970 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2971         uint32_t rep_cnt = MAX_REPEAT_TIME;
2972         struct i40e_link_status link_status;
2973         int status;
2974
2975         memset(&link_status, 0, sizeof(link_status));
2976
2977         do {
2978                 memset(&link_status, 0, sizeof(link_status));
2979
2980                 /* Get link status information from hardware */
2981                 status = i40e_aq_get_link_info(hw, enable_lse,
2982                                                 &link_status, NULL);
2983                 if (unlikely(status != I40E_SUCCESS)) {
2984                         link->link_speed = ETH_SPEED_NUM_NONE;
2985                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2986                         PMD_DRV_LOG(ERR, "Failed to get link info");
2987                         return;
2988                 }
2989
2990                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2991                 if (!wait_to_complete || link->link_status)
2992                         break;
2993
2994                 rte_delay_ms(CHECK_INTERVAL);
2995         } while (--rep_cnt);
2996
2997         /* Parse the link status */
2998         switch (link_status.link_speed) {
2999         case I40E_LINK_SPEED_100MB:
3000                 link->link_speed = ETH_SPEED_NUM_100M;
3001                 break;
3002         case I40E_LINK_SPEED_1GB:
3003                 link->link_speed = ETH_SPEED_NUM_1G;
3004                 break;
3005         case I40E_LINK_SPEED_10GB:
3006                 link->link_speed = ETH_SPEED_NUM_10G;
3007                 break;
3008         case I40E_LINK_SPEED_20GB:
3009                 link->link_speed = ETH_SPEED_NUM_20G;
3010                 break;
3011         case I40E_LINK_SPEED_25GB:
3012                 link->link_speed = ETH_SPEED_NUM_25G;
3013                 break;
3014         case I40E_LINK_SPEED_40GB:
3015                 link->link_speed = ETH_SPEED_NUM_40G;
3016                 break;
3017         default:
3018                 if (link->link_status)
3019                         link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3020                 else
3021                         link->link_speed = ETH_SPEED_NUM_NONE;
3022                 break;
3023         }
3024 }
3025
3026 int
3027 i40e_dev_link_update(struct rte_eth_dev *dev,
3028                      int wait_to_complete)
3029 {
3030         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3031         struct rte_eth_link link;
3032         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3033         int ret;
3034
3035         memset(&link, 0, sizeof(link));
3036
3037         /* i40e uses full duplex only */
3038         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3039         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3040                         ETH_LINK_SPEED_FIXED);
3041
3042         if (!wait_to_complete && !enable_lse)
3043                 update_link_reg(hw, &link);
3044         else
3045                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3046
3047         if (hw->switch_dev)
3048                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3049
3050         ret = rte_eth_linkstatus_set(dev, &link);
3051         i40e_notify_all_vfs_link_status(dev);
3052
3053         return ret;
3054 }
3055
3056 static void
3057 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3058                           uint32_t loreg, bool offset_loaded, uint64_t *offset,
3059                           uint64_t *stat, uint64_t *prev_stat)
3060 {
3061         i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3062         /* enlarge the limitation when statistics counters overflowed */
3063         if (offset_loaded) {
3064                 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3065                         *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3066                 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3067         }
3068         *prev_stat = *stat;
3069 }
3070
3071 /* Get all the statistics of a VSI */
3072 void
3073 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3074 {
3075         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3076         struct i40e_eth_stats *nes = &vsi->eth_stats;
3077         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3078         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3079
3080         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3081                                   vsi->offset_loaded, &oes->rx_bytes,
3082                                   &nes->rx_bytes, &vsi->prev_rx_bytes);
3083         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3084                             vsi->offset_loaded, &oes->rx_unicast,
3085                             &nes->rx_unicast);
3086         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3087                             vsi->offset_loaded, &oes->rx_multicast,
3088                             &nes->rx_multicast);
3089         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3090                             vsi->offset_loaded, &oes->rx_broadcast,
3091                             &nes->rx_broadcast);
3092         /* exclude CRC bytes */
3093         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3094                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3095
3096         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3097                             &oes->rx_discards, &nes->rx_discards);
3098         /* GLV_REPC not supported */
3099         /* GLV_RMPC not supported */
3100         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3101                             &oes->rx_unknown_protocol,
3102                             &nes->rx_unknown_protocol);
3103         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3104                                   vsi->offset_loaded, &oes->tx_bytes,
3105                                   &nes->tx_bytes, &vsi->prev_tx_bytes);
3106         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3107                             vsi->offset_loaded, &oes->tx_unicast,
3108                             &nes->tx_unicast);
3109         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3110                             vsi->offset_loaded, &oes->tx_multicast,
3111                             &nes->tx_multicast);
3112         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3113                             vsi->offset_loaded,  &oes->tx_broadcast,
3114                             &nes->tx_broadcast);
3115         /* GLV_TDPC not supported */
3116         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3117                             &oes->tx_errors, &nes->tx_errors);
3118         vsi->offset_loaded = true;
3119
3120         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3121                     vsi->vsi_id);
3122         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3123         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3124         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3125         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3126         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3127         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3128                     nes->rx_unknown_protocol);
3129         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3130         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3131         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3132         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3133         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3134         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3135         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3136                     vsi->vsi_id);
3137 }
3138
3139 static void
3140 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3141 {
3142         unsigned int i;
3143         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3144         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3145
3146         /* Get rx/tx bytes of internal transfer packets */
3147         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3148                                   I40E_GLV_GORCL(hw->port),
3149                                   pf->offset_loaded,
3150                                   &pf->internal_stats_offset.rx_bytes,
3151                                   &pf->internal_stats.rx_bytes,
3152                                   &pf->internal_prev_rx_bytes);
3153         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3154                                   I40E_GLV_GOTCL(hw->port),
3155                                   pf->offset_loaded,
3156                                   &pf->internal_stats_offset.tx_bytes,
3157                                   &pf->internal_stats.tx_bytes,
3158                                   &pf->internal_prev_tx_bytes);
3159         /* Get total internal rx packet count */
3160         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3161                             I40E_GLV_UPRCL(hw->port),
3162                             pf->offset_loaded,
3163                             &pf->internal_stats_offset.rx_unicast,
3164                             &pf->internal_stats.rx_unicast);
3165         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3166                             I40E_GLV_MPRCL(hw->port),
3167                             pf->offset_loaded,
3168                             &pf->internal_stats_offset.rx_multicast,
3169                             &pf->internal_stats.rx_multicast);
3170         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3171                             I40E_GLV_BPRCL(hw->port),
3172                             pf->offset_loaded,
3173                             &pf->internal_stats_offset.rx_broadcast,
3174                             &pf->internal_stats.rx_broadcast);
3175         /* Get total internal tx packet count */
3176         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3177                             I40E_GLV_UPTCL(hw->port),
3178                             pf->offset_loaded,
3179                             &pf->internal_stats_offset.tx_unicast,
3180                             &pf->internal_stats.tx_unicast);
3181         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3182                             I40E_GLV_MPTCL(hw->port),
3183                             pf->offset_loaded,
3184                             &pf->internal_stats_offset.tx_multicast,
3185                             &pf->internal_stats.tx_multicast);
3186         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3187                             I40E_GLV_BPTCL(hw->port),
3188                             pf->offset_loaded,
3189                             &pf->internal_stats_offset.tx_broadcast,
3190                             &pf->internal_stats.tx_broadcast);
3191
3192         /* exclude CRC size */
3193         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3194                 pf->internal_stats.rx_multicast +
3195                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3196
3197         /* Get statistics of struct i40e_eth_stats */
3198         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3199                                   I40E_GLPRT_GORCL(hw->port),
3200                                   pf->offset_loaded, &os->eth.rx_bytes,
3201                                   &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3202         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3203                             I40E_GLPRT_UPRCL(hw->port),
3204                             pf->offset_loaded, &os->eth.rx_unicast,
3205                             &ns->eth.rx_unicast);
3206         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3207                             I40E_GLPRT_MPRCL(hw->port),
3208                             pf->offset_loaded, &os->eth.rx_multicast,
3209                             &ns->eth.rx_multicast);
3210         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3211                             I40E_GLPRT_BPRCL(hw->port),
3212                             pf->offset_loaded, &os->eth.rx_broadcast,
3213                             &ns->eth.rx_broadcast);
3214         /* Workaround: CRC size should not be included in byte statistics,
3215          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3216          * packet.
3217          */
3218         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3219                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3220
3221         /* exclude internal rx bytes
3222          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3223          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3224          * value.
3225          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3226          */
3227         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3228                 ns->eth.rx_bytes = 0;
3229         else
3230                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3231
3232         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3233                 ns->eth.rx_unicast = 0;
3234         else
3235                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3236
3237         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3238                 ns->eth.rx_multicast = 0;
3239         else
3240                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3241
3242         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3243                 ns->eth.rx_broadcast = 0;
3244         else
3245                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3246
3247         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3248                             pf->offset_loaded, &os->eth.rx_discards,
3249                             &ns->eth.rx_discards);
3250         /* GLPRT_REPC not supported */
3251         /* GLPRT_RMPC not supported */
3252         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3253                             pf->offset_loaded,
3254                             &os->eth.rx_unknown_protocol,
3255                             &ns->eth.rx_unknown_protocol);
3256         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3257                                   I40E_GLPRT_GOTCL(hw->port),
3258                                   pf->offset_loaded, &os->eth.tx_bytes,
3259                                   &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3260         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3261                             I40E_GLPRT_UPTCL(hw->port),
3262                             pf->offset_loaded, &os->eth.tx_unicast,
3263                             &ns->eth.tx_unicast);
3264         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3265                             I40E_GLPRT_MPTCL(hw->port),
3266                             pf->offset_loaded, &os->eth.tx_multicast,
3267                             &ns->eth.tx_multicast);
3268         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3269                             I40E_GLPRT_BPTCL(hw->port),
3270                             pf->offset_loaded, &os->eth.tx_broadcast,
3271                             &ns->eth.tx_broadcast);
3272         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3273                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3274
3275         /* exclude internal tx bytes
3276          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3277          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3278          * value.
3279          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3280          */
3281         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3282                 ns->eth.tx_bytes = 0;
3283         else
3284                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3285
3286         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3287                 ns->eth.tx_unicast = 0;
3288         else
3289                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3290
3291         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3292                 ns->eth.tx_multicast = 0;
3293         else
3294                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3295
3296         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3297                 ns->eth.tx_broadcast = 0;
3298         else
3299                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3300
3301         /* GLPRT_TEPC not supported */
3302
3303         /* additional port specific stats */
3304         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3305                             pf->offset_loaded, &os->tx_dropped_link_down,
3306                             &ns->tx_dropped_link_down);
3307         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3308                             pf->offset_loaded, &os->crc_errors,
3309                             &ns->crc_errors);
3310         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3311                             pf->offset_loaded, &os->illegal_bytes,
3312                             &ns->illegal_bytes);
3313         /* GLPRT_ERRBC not supported */
3314         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3315                             pf->offset_loaded, &os->mac_local_faults,
3316                             &ns->mac_local_faults);
3317         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3318                             pf->offset_loaded, &os->mac_remote_faults,
3319                             &ns->mac_remote_faults);
3320         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3321                             pf->offset_loaded, &os->rx_length_errors,
3322                             &ns->rx_length_errors);
3323         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3324                             pf->offset_loaded, &os->link_xon_rx,
3325                             &ns->link_xon_rx);
3326         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3327                             pf->offset_loaded, &os->link_xoff_rx,
3328                             &ns->link_xoff_rx);
3329         for (i = 0; i < 8; i++) {
3330                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3331                                     pf->offset_loaded,
3332                                     &os->priority_xon_rx[i],
3333                                     &ns->priority_xon_rx[i]);
3334                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3335                                     pf->offset_loaded,
3336                                     &os->priority_xoff_rx[i],
3337                                     &ns->priority_xoff_rx[i]);
3338         }
3339         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3340                             pf->offset_loaded, &os->link_xon_tx,
3341                             &ns->link_xon_tx);
3342         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3343                             pf->offset_loaded, &os->link_xoff_tx,
3344                             &ns->link_xoff_tx);
3345         for (i = 0; i < 8; i++) {
3346                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3347                                     pf->offset_loaded,
3348                                     &os->priority_xon_tx[i],
3349                                     &ns->priority_xon_tx[i]);
3350                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3351                                     pf->offset_loaded,
3352                                     &os->priority_xoff_tx[i],
3353                                     &ns->priority_xoff_tx[i]);
3354                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3355                                     pf->offset_loaded,
3356                                     &os->priority_xon_2_xoff[i],
3357                                     &ns->priority_xon_2_xoff[i]);
3358         }
3359         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3360                             I40E_GLPRT_PRC64L(hw->port),
3361                             pf->offset_loaded, &os->rx_size_64,
3362                             &ns->rx_size_64);
3363         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3364                             I40E_GLPRT_PRC127L(hw->port),
3365                             pf->offset_loaded, &os->rx_size_127,
3366                             &ns->rx_size_127);
3367         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3368                             I40E_GLPRT_PRC255L(hw->port),
3369                             pf->offset_loaded, &os->rx_size_255,
3370                             &ns->rx_size_255);
3371         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3372                             I40E_GLPRT_PRC511L(hw->port),
3373                             pf->offset_loaded, &os->rx_size_511,
3374                             &ns->rx_size_511);
3375         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3376                             I40E_GLPRT_PRC1023L(hw->port),
3377                             pf->offset_loaded, &os->rx_size_1023,
3378                             &ns->rx_size_1023);
3379         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3380                             I40E_GLPRT_PRC1522L(hw->port),
3381                             pf->offset_loaded, &os->rx_size_1522,
3382                             &ns->rx_size_1522);
3383         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3384                             I40E_GLPRT_PRC9522L(hw->port),
3385                             pf->offset_loaded, &os->rx_size_big,
3386                             &ns->rx_size_big);
3387         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3388                             pf->offset_loaded, &os->rx_undersize,
3389                             &ns->rx_undersize);
3390         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3391                             pf->offset_loaded, &os->rx_fragments,
3392                             &ns->rx_fragments);
3393         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3394                             pf->offset_loaded, &os->rx_oversize,
3395                             &ns->rx_oversize);
3396         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3397                             pf->offset_loaded, &os->rx_jabber,
3398                             &ns->rx_jabber);
3399         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3400                             I40E_GLPRT_PTC64L(hw->port),
3401                             pf->offset_loaded, &os->tx_size_64,
3402                             &ns->tx_size_64);
3403         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3404                             I40E_GLPRT_PTC127L(hw->port),
3405                             pf->offset_loaded, &os->tx_size_127,
3406                             &ns->tx_size_127);
3407         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3408                             I40E_GLPRT_PTC255L(hw->port),
3409                             pf->offset_loaded, &os->tx_size_255,
3410                             &ns->tx_size_255);
3411         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3412                             I40E_GLPRT_PTC511L(hw->port),
3413                             pf->offset_loaded, &os->tx_size_511,
3414                             &ns->tx_size_511);
3415         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3416                             I40E_GLPRT_PTC1023L(hw->port),
3417                             pf->offset_loaded, &os->tx_size_1023,
3418                             &ns->tx_size_1023);
3419         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3420                             I40E_GLPRT_PTC1522L(hw->port),
3421                             pf->offset_loaded, &os->tx_size_1522,
3422                             &ns->tx_size_1522);
3423         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3424                             I40E_GLPRT_PTC9522L(hw->port),
3425                             pf->offset_loaded, &os->tx_size_big,
3426                             &ns->tx_size_big);
3427         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3428                            pf->offset_loaded,
3429                            &os->fd_sb_match, &ns->fd_sb_match);
3430         /* GLPRT_MSPDC not supported */
3431         /* GLPRT_XEC not supported */
3432
3433         pf->offset_loaded = true;
3434
3435         if (pf->main_vsi)
3436                 i40e_update_vsi_stats(pf->main_vsi);
3437 }
3438
3439 /* Get all statistics of a port */
3440 static int
3441 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3442 {
3443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3444         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3445         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3446         struct i40e_vsi *vsi;
3447         unsigned i;
3448
3449         /* call read registers - updates values, now write them to struct */
3450         i40e_read_stats_registers(pf, hw);
3451
3452         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3453                         pf->main_vsi->eth_stats.rx_multicast +
3454                         pf->main_vsi->eth_stats.rx_broadcast -
3455                         pf->main_vsi->eth_stats.rx_discards;
3456         stats->opackets = ns->eth.tx_unicast +
3457                         ns->eth.tx_multicast +
3458                         ns->eth.tx_broadcast;
3459         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3460         stats->obytes   = ns->eth.tx_bytes;
3461         stats->oerrors  = ns->eth.tx_errors +
3462                         pf->main_vsi->eth_stats.tx_errors;
3463
3464         /* Rx Errors */
3465         stats->imissed  = ns->eth.rx_discards +
3466                         pf->main_vsi->eth_stats.rx_discards;
3467         stats->ierrors  = ns->crc_errors +
3468                         ns->rx_length_errors + ns->rx_undersize +
3469                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3470
3471         if (pf->vfs) {
3472                 for (i = 0; i < pf->vf_num; i++) {
3473                         vsi = pf->vfs[i].vsi;
3474                         i40e_update_vsi_stats(vsi);
3475
3476                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3477                                         vsi->eth_stats.rx_multicast +
3478                                         vsi->eth_stats.rx_broadcast -
3479                                         vsi->eth_stats.rx_discards);
3480                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3481                         stats->oerrors  += vsi->eth_stats.tx_errors;
3482                         stats->imissed  += vsi->eth_stats.rx_discards;
3483                 }
3484         }
3485
3486         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3487         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3488         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3489         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3490         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3491         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3492         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3493                     ns->eth.rx_unknown_protocol);
3494         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3495         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3496         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3497         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3498         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3499         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3500
3501         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3502                     ns->tx_dropped_link_down);
3503         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3504         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3505                     ns->illegal_bytes);
3506         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3507         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3508                     ns->mac_local_faults);
3509         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3510                     ns->mac_remote_faults);
3511         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3512                     ns->rx_length_errors);
3513         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3514         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3515         for (i = 0; i < 8; i++) {
3516                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3517                                 i, ns->priority_xon_rx[i]);
3518                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3519                                 i, ns->priority_xoff_rx[i]);
3520         }
3521         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3522         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3523         for (i = 0; i < 8; i++) {
3524                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3525                                 i, ns->priority_xon_tx[i]);
3526                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3527                                 i, ns->priority_xoff_tx[i]);
3528                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3529                                 i, ns->priority_xon_2_xoff[i]);
3530         }
3531         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3532         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3533         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3534         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3535         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3536         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3537         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3538         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3539         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3540         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3541         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3542         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3543         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3544         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3545         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3546         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3547         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3548         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3549         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3550                         ns->mac_short_packet_dropped);
3551         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3552                     ns->checksum_error);
3553         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3554         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3555         return 0;
3556 }
3557
3558 /* Reset the statistics */
3559 static int
3560 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3561 {
3562         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3563         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564
3565         /* Mark PF and VSI stats to update the offset, aka "reset" */
3566         pf->offset_loaded = false;
3567         if (pf->main_vsi)
3568                 pf->main_vsi->offset_loaded = false;
3569
3570         /* read the stats, reading current register values into offset */
3571         i40e_read_stats_registers(pf, hw);
3572
3573         return 0;
3574 }
3575
3576 static uint32_t
3577 i40e_xstats_calc_num(void)
3578 {
3579         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3580                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3581                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3582 }
3583
3584 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3585                                      struct rte_eth_xstat_name *xstats_names,
3586                                      __rte_unused unsigned limit)
3587 {
3588         unsigned count = 0;
3589         unsigned i, prio;
3590
3591         if (xstats_names == NULL)
3592                 return i40e_xstats_calc_num();
3593
3594         /* Note: limit checked in rte_eth_xstats_names() */
3595
3596         /* Get stats from i40e_eth_stats struct */
3597         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3598                 strlcpy(xstats_names[count].name,
3599                         rte_i40e_stats_strings[i].name,
3600                         sizeof(xstats_names[count].name));
3601                 count++;
3602         }
3603
3604         /* Get individiual stats from i40e_hw_port struct */
3605         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3606                 strlcpy(xstats_names[count].name,
3607                         rte_i40e_hw_port_strings[i].name,
3608                         sizeof(xstats_names[count].name));
3609                 count++;
3610         }
3611
3612         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3613                 for (prio = 0; prio < 8; prio++) {
3614                         snprintf(xstats_names[count].name,
3615                                  sizeof(xstats_names[count].name),
3616                                  "rx_priority%u_%s", prio,
3617                                  rte_i40e_rxq_prio_strings[i].name);
3618                         count++;
3619                 }
3620         }
3621
3622         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3623                 for (prio = 0; prio < 8; prio++) {
3624                         snprintf(xstats_names[count].name,
3625                                  sizeof(xstats_names[count].name),
3626                                  "tx_priority%u_%s", prio,
3627                                  rte_i40e_txq_prio_strings[i].name);
3628                         count++;
3629                 }
3630         }
3631         return count;
3632 }
3633
3634 static int
3635 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3636                     unsigned n)
3637 {
3638         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3640         unsigned i, count, prio;
3641         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3642
3643         count = i40e_xstats_calc_num();
3644         if (n < count)
3645                 return count;
3646
3647         i40e_read_stats_registers(pf, hw);
3648
3649         if (xstats == NULL)
3650                 return 0;
3651
3652         count = 0;
3653
3654         /* Get stats from i40e_eth_stats struct */
3655         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3656                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3657                         rte_i40e_stats_strings[i].offset);
3658                 xstats[count].id = count;
3659                 count++;
3660         }
3661
3662         /* Get individiual stats from i40e_hw_port struct */
3663         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3664                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3665                         rte_i40e_hw_port_strings[i].offset);
3666                 xstats[count].id = count;
3667                 count++;
3668         }
3669
3670         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3671                 for (prio = 0; prio < 8; prio++) {
3672                         xstats[count].value =
3673                                 *(uint64_t *)(((char *)hw_stats) +
3674                                 rte_i40e_rxq_prio_strings[i].offset +
3675                                 (sizeof(uint64_t) * prio));
3676                         xstats[count].id = count;
3677                         count++;
3678                 }
3679         }
3680
3681         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3682                 for (prio = 0; prio < 8; prio++) {
3683                         xstats[count].value =
3684                                 *(uint64_t *)(((char *)hw_stats) +
3685                                 rte_i40e_txq_prio_strings[i].offset +
3686                                 (sizeof(uint64_t) * prio));
3687                         xstats[count].id = count;
3688                         count++;
3689                 }
3690         }
3691
3692         return count;
3693 }
3694
3695 static int
3696 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3697 {
3698         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3699         u32 full_ver;
3700         u8 ver, patch;
3701         u16 build;
3702         int ret;
3703
3704         full_ver = hw->nvm.oem_ver;
3705         ver = (u8)(full_ver >> 24);
3706         build = (u16)((full_ver >> 8) & 0xffff);
3707         patch = (u8)(full_ver & 0xff);
3708
3709         ret = snprintf(fw_version, fw_size,
3710                  "%d.%d%d 0x%08x %d.%d.%d",
3711                  ((hw->nvm.version >> 12) & 0xf),
3712                  ((hw->nvm.version >> 4) & 0xff),
3713                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3714                  ver, build, patch);
3715
3716         ret += 1; /* add the size of '\0' */
3717         if (fw_size < (u32)ret)
3718                 return ret;
3719         else
3720                 return 0;
3721 }
3722
3723 /*
3724  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3725  * the Rx data path does not hang if the FW LLDP is stopped.
3726  * return true if lldp need to stop
3727  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3728  */
3729 static bool
3730 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3731 {
3732         double nvm_ver;
3733         char ver_str[64] = {0};
3734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3735
3736         i40e_fw_version_get(dev, ver_str, 64);
3737         nvm_ver = atof(ver_str);
3738         if ((hw->mac.type == I40E_MAC_X722 ||
3739              hw->mac.type == I40E_MAC_X722_VF) &&
3740              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3741                 return true;
3742         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3743                 return true;
3744
3745         return false;
3746 }
3747
3748 static int
3749 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3750 {
3751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3753         struct i40e_vsi *vsi = pf->main_vsi;
3754         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3755
3756         dev_info->max_rx_queues = vsi->nb_qps;
3757         dev_info->max_tx_queues = vsi->nb_qps;
3758         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3759         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3760         dev_info->max_mac_addrs = vsi->max_macaddrs;
3761         dev_info->max_vfs = pci_dev->max_vfs;
3762         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3763         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3764         dev_info->rx_queue_offload_capa = 0;
3765         dev_info->rx_offload_capa =
3766                 DEV_RX_OFFLOAD_VLAN_STRIP |
3767                 DEV_RX_OFFLOAD_QINQ_STRIP |
3768                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3769                 DEV_RX_OFFLOAD_UDP_CKSUM |
3770                 DEV_RX_OFFLOAD_TCP_CKSUM |
3771                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3772                 DEV_RX_OFFLOAD_KEEP_CRC |
3773                 DEV_RX_OFFLOAD_SCATTER |
3774                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3775                 DEV_RX_OFFLOAD_VLAN_FILTER |
3776                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3777                 DEV_RX_OFFLOAD_RSS_HASH;
3778
3779         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3780         dev_info->tx_offload_capa =
3781                 DEV_TX_OFFLOAD_VLAN_INSERT |
3782                 DEV_TX_OFFLOAD_QINQ_INSERT |
3783                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3784                 DEV_TX_OFFLOAD_UDP_CKSUM |
3785                 DEV_TX_OFFLOAD_TCP_CKSUM |
3786                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3787                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3788                 DEV_TX_OFFLOAD_TCP_TSO |
3789                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3790                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3791                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3792                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3793                 DEV_TX_OFFLOAD_MULTI_SEGS |
3794                 dev_info->tx_queue_offload_capa;
3795         dev_info->dev_capa =
3796                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3797                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3798
3799         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3800                                                 sizeof(uint32_t);
3801         dev_info->reta_size = pf->hash_lut_size;
3802         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3803
3804         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3805                 .rx_thresh = {
3806                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3807                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3808                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3809                 },
3810                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3811                 .rx_drop_en = 0,
3812                 .offloads = 0,
3813         };
3814
3815         dev_info->default_txconf = (struct rte_eth_txconf) {
3816                 .tx_thresh = {
3817                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3818                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3819                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3820                 },
3821                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3822                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3823                 .offloads = 0,
3824         };
3825
3826         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3827                 .nb_max = I40E_MAX_RING_DESC,
3828                 .nb_min = I40E_MIN_RING_DESC,
3829                 .nb_align = I40E_ALIGN_RING_DESC,
3830         };
3831
3832         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3833                 .nb_max = I40E_MAX_RING_DESC,
3834                 .nb_min = I40E_MIN_RING_DESC,
3835                 .nb_align = I40E_ALIGN_RING_DESC,
3836                 .nb_seg_max = I40E_TX_MAX_SEG,
3837                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3838         };
3839
3840         if (pf->flags & I40E_FLAG_VMDQ) {
3841                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3842                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3843                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3844                                                 pf->max_nb_vmdq_vsi;
3845                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3846                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3847                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3848         }
3849
3850         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3851                 /* For XL710 */
3852                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3853                 dev_info->default_rxportconf.nb_queues = 2;
3854                 dev_info->default_txportconf.nb_queues = 2;
3855                 if (dev->data->nb_rx_queues == 1)
3856                         dev_info->default_rxportconf.ring_size = 2048;
3857                 else
3858                         dev_info->default_rxportconf.ring_size = 1024;
3859                 if (dev->data->nb_tx_queues == 1)
3860                         dev_info->default_txportconf.ring_size = 1024;
3861                 else
3862                         dev_info->default_txportconf.ring_size = 512;
3863
3864         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3865                 /* For XXV710 */
3866                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3867                 dev_info->default_rxportconf.nb_queues = 1;
3868                 dev_info->default_txportconf.nb_queues = 1;
3869                 dev_info->default_rxportconf.ring_size = 256;
3870                 dev_info->default_txportconf.ring_size = 256;
3871         } else {
3872                 /* For X710 */
3873                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3874                 dev_info->default_rxportconf.nb_queues = 1;
3875                 dev_info->default_txportconf.nb_queues = 1;
3876                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3877                         dev_info->default_rxportconf.ring_size = 512;
3878                         dev_info->default_txportconf.ring_size = 256;
3879                 } else {
3880                         dev_info->default_rxportconf.ring_size = 256;
3881                         dev_info->default_txportconf.ring_size = 256;
3882                 }
3883         }
3884         dev_info->default_rxportconf.burst_size = 32;
3885         dev_info->default_txportconf.burst_size = 32;
3886
3887         return 0;
3888 }
3889
3890 static int
3891 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3892 {
3893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3894         struct i40e_vsi *vsi = pf->main_vsi;
3895         PMD_INIT_FUNC_TRACE();
3896
3897         if (on)
3898                 return i40e_vsi_add_vlan(vsi, vlan_id);
3899         else
3900                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3901 }
3902
3903 static int
3904 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3905                                 enum rte_vlan_type vlan_type,
3906                                 uint16_t tpid, int qinq)
3907 {
3908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3909         uint64_t reg_r = 0;
3910         uint64_t reg_w = 0;
3911         uint16_t reg_id = 3;
3912         int ret;
3913
3914         if (qinq) {
3915                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3916                         reg_id = 2;
3917         }
3918
3919         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3920                                           &reg_r, NULL);
3921         if (ret != I40E_SUCCESS) {
3922                 PMD_DRV_LOG(ERR,
3923                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3924                            reg_id);
3925                 return -EIO;
3926         }
3927         PMD_DRV_LOG(DEBUG,
3928                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3929                     reg_id, reg_r);
3930
3931         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3932         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3933         if (reg_r == reg_w) {
3934                 PMD_DRV_LOG(DEBUG, "No need to write");
3935                 return 0;
3936         }
3937
3938         ret = i40e_aq_debug_write_global_register(hw,
3939                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3940                                            reg_w, NULL);
3941         if (ret != I40E_SUCCESS) {
3942                 PMD_DRV_LOG(ERR,
3943                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3944                             reg_id);
3945                 return -EIO;
3946         }
3947         PMD_DRV_LOG(DEBUG,
3948                     "Global register 0x%08x is changed with value 0x%08x",
3949                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3950
3951         return 0;
3952 }
3953
3954 static int
3955 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3956                    enum rte_vlan_type vlan_type,
3957                    uint16_t tpid)
3958 {
3959         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3961         int qinq = dev->data->dev_conf.rxmode.offloads &
3962                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3963         int ret = 0;
3964
3965         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3966              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3967             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3968                 PMD_DRV_LOG(ERR,
3969                             "Unsupported vlan type.");
3970                 return -EINVAL;
3971         }
3972
3973         if (pf->support_multi_driver) {
3974                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3975                 return -ENOTSUP;
3976         }
3977
3978         /* 802.1ad frames ability is added in NVM API 1.7*/
3979         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3980                 if (qinq) {
3981                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3982                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3983                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3984                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3985                 } else {
3986                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3987                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3988                 }
3989                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3990                 if (ret != I40E_SUCCESS) {
3991                         PMD_DRV_LOG(ERR,
3992                                     "Set switch config failed aq_err: %d",
3993                                     hw->aq.asq_last_status);
3994                         ret = -EIO;
3995                 }
3996         } else
3997                 /* If NVM API < 1.7, keep the register setting */
3998                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3999                                                       tpid, qinq);
4000
4001         return ret;
4002 }
4003
4004 /* Configure outer vlan stripping on or off in QinQ mode */
4005 static int
4006 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
4007 {
4008         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4009         int ret = I40E_SUCCESS;
4010         uint32_t reg;
4011
4012         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
4013                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
4014                 return -EINVAL;
4015         }
4016
4017         /* Configure for outer VLAN RX stripping */
4018         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4019
4020         if (on)
4021                 reg |= I40E_VSI_TSR_QINQ_STRIP;
4022         else
4023                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4024
4025         ret = i40e_aq_debug_write_register(hw,
4026                                                    I40E_VSI_TSR(vsi->vsi_id),
4027                                                    reg, NULL);
4028         if (ret < 0) {
4029                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4030                                     vsi->vsi_id);
4031                 return I40E_ERR_CONFIG;
4032         }
4033
4034         return ret;
4035 }
4036
4037 static int
4038 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4039 {
4040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4041         struct i40e_vsi *vsi = pf->main_vsi;
4042         struct rte_eth_rxmode *rxmode;
4043
4044         rxmode = &dev->data->dev_conf.rxmode;
4045         if (mask & ETH_VLAN_FILTER_MASK) {
4046                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4047                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4048                 else
4049                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4050         }
4051
4052         if (mask & ETH_VLAN_STRIP_MASK) {
4053                 /* Enable or disable VLAN stripping */
4054                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4055                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4056                 else
4057                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4058         }
4059
4060         if (mask & ETH_VLAN_EXTEND_MASK) {
4061                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4062                         i40e_vsi_config_double_vlan(vsi, TRUE);
4063                         /* Set global registers with default ethertype. */
4064                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4065                                            RTE_ETHER_TYPE_VLAN);
4066                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4067                                            RTE_ETHER_TYPE_VLAN);
4068                 }
4069                 else
4070                         i40e_vsi_config_double_vlan(vsi, FALSE);
4071         }
4072
4073         if (mask & ETH_QINQ_STRIP_MASK) {
4074                 /* Enable or disable outer VLAN stripping */
4075                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4076                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4077                 else
4078                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4079         }
4080
4081         return 0;
4082 }
4083
4084 static void
4085 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4086                           __rte_unused uint16_t queue,
4087                           __rte_unused int on)
4088 {
4089         PMD_INIT_FUNC_TRACE();
4090 }
4091
4092 static int
4093 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4094 {
4095         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4096         struct i40e_vsi *vsi = pf->main_vsi;
4097         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4098         struct i40e_vsi_vlan_pvid_info info;
4099
4100         memset(&info, 0, sizeof(info));
4101         info.on = on;
4102         if (info.on)
4103                 info.config.pvid = pvid;
4104         else {
4105                 info.config.reject.tagged =
4106                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4107                 info.config.reject.untagged =
4108                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4109         }
4110
4111         return i40e_vsi_vlan_pvid_set(vsi, &info);
4112 }
4113
4114 static int
4115 i40e_dev_led_on(struct rte_eth_dev *dev)
4116 {
4117         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4118         uint32_t mode = i40e_led_get(hw);
4119
4120         if (mode == 0)
4121                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4122
4123         return 0;
4124 }
4125
4126 static int
4127 i40e_dev_led_off(struct rte_eth_dev *dev)
4128 {
4129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4130         uint32_t mode = i40e_led_get(hw);
4131
4132         if (mode != 0)
4133                 i40e_led_set(hw, 0, false);
4134
4135         return 0;
4136 }
4137
4138 static int
4139 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4140 {
4141         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4143
4144         fc_conf->pause_time = pf->fc_conf.pause_time;
4145
4146         /* read out from register, in case they are modified by other port */
4147         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4148                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4149         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4150                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4151
4152         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4153         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4154
4155          /* Return current mode according to actual setting*/
4156         switch (hw->fc.current_mode) {
4157         case I40E_FC_FULL:
4158                 fc_conf->mode = RTE_FC_FULL;
4159                 break;
4160         case I40E_FC_TX_PAUSE:
4161                 fc_conf->mode = RTE_FC_TX_PAUSE;
4162                 break;
4163         case I40E_FC_RX_PAUSE:
4164                 fc_conf->mode = RTE_FC_RX_PAUSE;
4165                 break;
4166         case I40E_FC_NONE:
4167         default:
4168                 fc_conf->mode = RTE_FC_NONE;
4169         };
4170
4171         return 0;
4172 }
4173
4174 static int
4175 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4176 {
4177         uint32_t mflcn_reg, fctrl_reg, reg;
4178         uint32_t max_high_water;
4179         uint8_t i, aq_failure;
4180         int err;
4181         struct i40e_hw *hw;
4182         struct i40e_pf *pf;
4183         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4184                 [RTE_FC_NONE] = I40E_FC_NONE,
4185                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4186                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4187                 [RTE_FC_FULL] = I40E_FC_FULL
4188         };
4189
4190         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4191
4192         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4193         if ((fc_conf->high_water > max_high_water) ||
4194                         (fc_conf->high_water < fc_conf->low_water)) {
4195                 PMD_INIT_LOG(ERR,
4196                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4197                         max_high_water);
4198                 return -EINVAL;
4199         }
4200
4201         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4203         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4204
4205         pf->fc_conf.pause_time = fc_conf->pause_time;
4206         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4207         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4208
4209         PMD_INIT_FUNC_TRACE();
4210
4211         /* All the link flow control related enable/disable register
4212          * configuration is handle by the F/W
4213          */
4214         err = i40e_set_fc(hw, &aq_failure, true);
4215         if (err < 0)
4216                 return -ENOSYS;
4217
4218         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4219                 /* Configure flow control refresh threshold,
4220                  * the value for stat_tx_pause_refresh_timer[8]
4221                  * is used for global pause operation.
4222                  */
4223
4224                 I40E_WRITE_REG(hw,
4225                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4226                                pf->fc_conf.pause_time);
4227
4228                 /* configure the timer value included in transmitted pause
4229                  * frame,
4230                  * the value for stat_tx_pause_quanta[8] is used for global
4231                  * pause operation
4232                  */
4233                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4234                                pf->fc_conf.pause_time);
4235
4236                 fctrl_reg = I40E_READ_REG(hw,
4237                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4238
4239                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4240                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4241                 else
4242                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4243
4244                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4245                                fctrl_reg);
4246         } else {
4247                 /* Configure pause time (2 TCs per register) */
4248                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4249                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4250                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4251
4252                 /* Configure flow control refresh threshold value */
4253                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4254                                pf->fc_conf.pause_time / 2);
4255
4256                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4257
4258                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4259                  *depending on configuration
4260                  */
4261                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4262                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4263                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4264                 } else {
4265                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4266                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4267                 }
4268
4269                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4270         }
4271
4272         if (!pf->support_multi_driver) {
4273                 /* config water marker both based on the packets and bytes */
4274                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4275                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4276                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4277                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4278                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4279                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4280                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4281                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4282                                   << I40E_KILOSHIFT);
4283                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4284                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4285                                    << I40E_KILOSHIFT);
4286         } else {
4287                 PMD_DRV_LOG(ERR,
4288                             "Water marker configuration is not supported.");
4289         }
4290
4291         I40E_WRITE_FLUSH(hw);
4292
4293         return 0;
4294 }
4295
4296 static int
4297 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4298                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4299 {
4300         PMD_INIT_FUNC_TRACE();
4301
4302         return -ENOSYS;
4303 }
4304
4305 /* Add a MAC address, and update filters */
4306 static int
4307 i40e_macaddr_add(struct rte_eth_dev *dev,
4308                  struct rte_ether_addr *mac_addr,
4309                  __rte_unused uint32_t index,
4310                  uint32_t pool)
4311 {
4312         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4313         struct i40e_mac_filter_info mac_filter;
4314         struct i40e_vsi *vsi;
4315         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4316         int ret;
4317
4318         /* If VMDQ not enabled or configured, return */
4319         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4320                           !pf->nb_cfg_vmdq_vsi)) {
4321                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4322                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4323                         pool);
4324                 return -ENOTSUP;
4325         }
4326
4327         if (pool > pf->nb_cfg_vmdq_vsi) {
4328                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4329                                 pool, pf->nb_cfg_vmdq_vsi);
4330                 return -EINVAL;
4331         }
4332
4333         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4334         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4335                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4336         else
4337                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4338
4339         if (pool == 0)
4340                 vsi = pf->main_vsi;
4341         else
4342                 vsi = pf->vmdq[pool - 1].vsi;
4343
4344         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4345         if (ret != I40E_SUCCESS) {
4346                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4347                 return -ENODEV;
4348         }
4349         return 0;
4350 }
4351
4352 /* Remove a MAC address, and update filters */
4353 static void
4354 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4355 {
4356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4357         struct i40e_vsi *vsi;
4358         struct rte_eth_dev_data *data = dev->data;
4359         struct rte_ether_addr *macaddr;
4360         int ret;
4361         uint32_t i;
4362         uint64_t pool_sel;
4363
4364         macaddr = &(data->mac_addrs[index]);
4365
4366         pool_sel = dev->data->mac_pool_sel[index];
4367
4368         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4369                 if (pool_sel & (1ULL << i)) {
4370                         if (i == 0)
4371                                 vsi = pf->main_vsi;
4372                         else {
4373                                 /* No VMDQ pool enabled or configured */
4374                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4375                                         (i > pf->nb_cfg_vmdq_vsi)) {
4376                                         PMD_DRV_LOG(ERR,
4377                                                 "No VMDQ pool enabled/configured");
4378                                         return;
4379                                 }
4380                                 vsi = pf->vmdq[i - 1].vsi;
4381                         }
4382                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4383
4384                         if (ret) {
4385                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4386                                 return;
4387                         }
4388                 }
4389         }
4390 }
4391
4392 /* Set perfect match or hash match of MAC and VLAN for a VF */
4393 static int
4394 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4395                  struct rte_eth_mac_filter *filter,
4396                  bool add)
4397 {
4398         struct i40e_hw *hw;
4399         struct i40e_mac_filter_info mac_filter;
4400         struct rte_ether_addr old_mac;
4401         struct rte_ether_addr *new_mac;
4402         struct i40e_pf_vf *vf = NULL;
4403         uint16_t vf_id;
4404         int ret;
4405
4406         if (pf == NULL) {
4407                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4408                 return -EINVAL;
4409         }
4410         hw = I40E_PF_TO_HW(pf);
4411
4412         if (filter == NULL) {
4413                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4414                 return -EINVAL;
4415         }
4416
4417         new_mac = &filter->mac_addr;
4418
4419         if (rte_is_zero_ether_addr(new_mac)) {
4420                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4421                 return -EINVAL;
4422         }
4423
4424         vf_id = filter->dst_id;
4425
4426         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4427                 PMD_DRV_LOG(ERR, "Invalid argument.");
4428                 return -EINVAL;
4429         }
4430         vf = &pf->vfs[vf_id];
4431
4432         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4433                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4434                 return -EINVAL;
4435         }
4436
4437         if (add) {
4438                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4439                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4440                                 RTE_ETHER_ADDR_LEN);
4441                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4442                                  RTE_ETHER_ADDR_LEN);
4443
4444                 mac_filter.filter_type = filter->filter_type;
4445                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4446                 if (ret != I40E_SUCCESS) {
4447                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4448                         return -1;
4449                 }
4450                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4451         } else {
4452                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4453                                 RTE_ETHER_ADDR_LEN);
4454                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4455                 if (ret != I40E_SUCCESS) {
4456                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4457                         return -1;
4458                 }
4459
4460                 /* Clear device address as it has been removed */
4461                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4462                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4463         }
4464
4465         return 0;
4466 }
4467
4468 /* MAC filter handle */
4469 static int
4470 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4471                 void *arg)
4472 {
4473         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4474         struct rte_eth_mac_filter *filter;
4475         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4476         int ret = I40E_NOT_SUPPORTED;
4477
4478         filter = (struct rte_eth_mac_filter *)(arg);
4479
4480         switch (filter_op) {
4481         case RTE_ETH_FILTER_NOP:
4482                 ret = I40E_SUCCESS;
4483                 break;
4484         case RTE_ETH_FILTER_ADD:
4485                 i40e_pf_disable_irq0(hw);
4486                 if (filter->is_vf)
4487                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4488                 i40e_pf_enable_irq0(hw);
4489                 break;
4490         case RTE_ETH_FILTER_DELETE:
4491                 i40e_pf_disable_irq0(hw);
4492                 if (filter->is_vf)
4493                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4494                 i40e_pf_enable_irq0(hw);
4495                 break;
4496         default:
4497                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4498                 ret = I40E_ERR_PARAM;
4499                 break;
4500         }
4501
4502         return ret;
4503 }
4504
4505 static int
4506 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4507 {
4508         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4509         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4510         uint32_t reg;
4511         int ret;
4512
4513         if (!lut)
4514                 return -EINVAL;
4515
4516         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4517                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4518                                           vsi->type != I40E_VSI_SRIOV,
4519                                           lut, lut_size);
4520                 if (ret) {
4521                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4522                         return ret;
4523                 }
4524         } else {
4525                 uint32_t *lut_dw = (uint32_t *)lut;
4526                 uint16_t i, lut_size_dw = lut_size / 4;
4527
4528                 if (vsi->type == I40E_VSI_SRIOV) {
4529                         for (i = 0; i <= lut_size_dw; i++) {
4530                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4531                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4532                         }
4533                 } else {
4534                         for (i = 0; i < lut_size_dw; i++)
4535                                 lut_dw[i] = I40E_READ_REG(hw,
4536                                                           I40E_PFQF_HLUT(i));
4537                 }
4538         }
4539
4540         return 0;
4541 }
4542
4543 int
4544 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4545 {
4546         struct i40e_pf *pf;
4547         struct i40e_hw *hw;
4548         int ret;
4549
4550         if (!vsi || !lut)
4551                 return -EINVAL;
4552
4553         pf = I40E_VSI_TO_PF(vsi);
4554         hw = I40E_VSI_TO_HW(vsi);
4555
4556         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4557                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4558                                           vsi->type != I40E_VSI_SRIOV,
4559                                           lut, lut_size);
4560                 if (ret) {
4561                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4562                         return ret;
4563                 }
4564         } else {
4565                 uint32_t *lut_dw = (uint32_t *)lut;
4566                 uint16_t i, lut_size_dw = lut_size / 4;
4567
4568                 if (vsi->type == I40E_VSI_SRIOV) {
4569                         for (i = 0; i < lut_size_dw; i++)
4570                                 I40E_WRITE_REG(
4571                                         hw,
4572                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4573                                         lut_dw[i]);
4574                 } else {
4575                         for (i = 0; i < lut_size_dw; i++)
4576                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4577                                                lut_dw[i]);
4578                 }
4579                 I40E_WRITE_FLUSH(hw);
4580         }
4581
4582         return 0;
4583 }
4584
4585 static int
4586 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4587                          struct rte_eth_rss_reta_entry64 *reta_conf,
4588                          uint16_t reta_size)
4589 {
4590         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4591         uint16_t i, lut_size = pf->hash_lut_size;
4592         uint16_t idx, shift;
4593         uint8_t *lut;
4594         int ret;
4595
4596         if (reta_size != lut_size ||
4597                 reta_size > ETH_RSS_RETA_SIZE_512) {
4598                 PMD_DRV_LOG(ERR,
4599                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4600                         reta_size, lut_size);
4601                 return -EINVAL;
4602         }
4603
4604         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4605         if (!lut) {
4606                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4607                 return -ENOMEM;
4608         }
4609         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4610         if (ret)
4611                 goto out;
4612         for (i = 0; i < reta_size; i++) {
4613                 idx = i / RTE_RETA_GROUP_SIZE;
4614                 shift = i % RTE_RETA_GROUP_SIZE;
4615                 if (reta_conf[idx].mask & (1ULL << shift))
4616                         lut[i] = reta_conf[idx].reta[shift];
4617         }
4618         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4619
4620         pf->adapter->rss_reta_updated = 1;
4621
4622 out:
4623         rte_free(lut);
4624
4625         return ret;
4626 }
4627
4628 static int
4629 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4630                         struct rte_eth_rss_reta_entry64 *reta_conf,
4631                         uint16_t reta_size)
4632 {
4633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4634         uint16_t i, lut_size = pf->hash_lut_size;
4635         uint16_t idx, shift;
4636         uint8_t *lut;
4637         int ret;
4638
4639         if (reta_size != lut_size ||
4640                 reta_size > ETH_RSS_RETA_SIZE_512) {
4641                 PMD_DRV_LOG(ERR,
4642                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4643                         reta_size, lut_size);
4644                 return -EINVAL;
4645         }
4646
4647         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4648         if (!lut) {
4649                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4650                 return -ENOMEM;
4651         }
4652
4653         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4654         if (ret)
4655                 goto out;
4656         for (i = 0; i < reta_size; i++) {
4657                 idx = i / RTE_RETA_GROUP_SIZE;
4658                 shift = i % RTE_RETA_GROUP_SIZE;
4659                 if (reta_conf[idx].mask & (1ULL << shift))
4660                         reta_conf[idx].reta[shift] = lut[i];
4661         }
4662
4663 out:
4664         rte_free(lut);
4665
4666         return ret;
4667 }
4668
4669 /**
4670  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4671  * @hw:   pointer to the HW structure
4672  * @mem:  pointer to mem struct to fill out
4673  * @size: size of memory requested
4674  * @alignment: what to align the allocation to
4675  **/
4676 enum i40e_status_code
4677 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4678                         struct i40e_dma_mem *mem,
4679                         u64 size,
4680                         u32 alignment)
4681 {
4682         const struct rte_memzone *mz = NULL;
4683         char z_name[RTE_MEMZONE_NAMESIZE];
4684
4685         if (!mem)
4686                 return I40E_ERR_PARAM;
4687
4688         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4689         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4690                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4691         if (!mz)
4692                 return I40E_ERR_NO_MEMORY;
4693
4694         mem->size = size;
4695         mem->va = mz->addr;
4696         mem->pa = mz->iova;
4697         mem->zone = (const void *)mz;
4698         PMD_DRV_LOG(DEBUG,
4699                 "memzone %s allocated with physical address: %"PRIu64,
4700                 mz->name, mem->pa);
4701
4702         return I40E_SUCCESS;
4703 }
4704
4705 /**
4706  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4707  * @hw:   pointer to the HW structure
4708  * @mem:  ptr to mem struct to free
4709  **/
4710 enum i40e_status_code
4711 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4712                     struct i40e_dma_mem *mem)
4713 {
4714         if (!mem)
4715                 return I40E_ERR_PARAM;
4716
4717         PMD_DRV_LOG(DEBUG,
4718                 "memzone %s to be freed with physical address: %"PRIu64,
4719                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4720         rte_memzone_free((const struct rte_memzone *)mem->zone);
4721         mem->zone = NULL;
4722         mem->va = NULL;
4723         mem->pa = (u64)0;
4724
4725         return I40E_SUCCESS;
4726 }
4727
4728 /**
4729  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4730  * @hw:   pointer to the HW structure
4731  * @mem:  pointer to mem struct to fill out
4732  * @size: size of memory requested
4733  **/
4734 enum i40e_status_code
4735 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4736                          struct i40e_virt_mem *mem,
4737                          u32 size)
4738 {
4739         if (!mem)
4740                 return I40E_ERR_PARAM;
4741
4742         mem->size = size;
4743         mem->va = rte_zmalloc("i40e", size, 0);
4744
4745         if (mem->va)
4746                 return I40E_SUCCESS;
4747         else
4748                 return I40E_ERR_NO_MEMORY;
4749 }
4750
4751 /**
4752  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4753  * @hw:   pointer to the HW structure
4754  * @mem:  pointer to mem struct to free
4755  **/
4756 enum i40e_status_code
4757 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4758                      struct i40e_virt_mem *mem)
4759 {
4760         if (!mem)
4761                 return I40E_ERR_PARAM;
4762
4763         rte_free(mem->va);
4764         mem->va = NULL;
4765
4766         return I40E_SUCCESS;
4767 }
4768
4769 void
4770 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4771 {
4772         rte_spinlock_init(&sp->spinlock);
4773 }
4774
4775 void
4776 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4777 {
4778         rte_spinlock_lock(&sp->spinlock);
4779 }
4780
4781 void
4782 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4783 {
4784         rte_spinlock_unlock(&sp->spinlock);
4785 }
4786
4787 void
4788 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4789 {
4790         return;
4791 }
4792
4793 /**
4794  * Get the hardware capabilities, which will be parsed
4795  * and saved into struct i40e_hw.
4796  */
4797 static int
4798 i40e_get_cap(struct i40e_hw *hw)
4799 {
4800         struct i40e_aqc_list_capabilities_element_resp *buf;
4801         uint16_t len, size = 0;
4802         int ret;
4803
4804         /* Calculate a huge enough buff for saving response data temporarily */
4805         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4806                                                 I40E_MAX_CAP_ELE_NUM;
4807         buf = rte_zmalloc("i40e", len, 0);
4808         if (!buf) {
4809                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4810                 return I40E_ERR_NO_MEMORY;
4811         }
4812
4813         /* Get, parse the capabilities and save it to hw */
4814         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4815                         i40e_aqc_opc_list_func_capabilities, NULL);
4816         if (ret != I40E_SUCCESS)
4817                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4818
4819         /* Free the temporary buffer after being used */
4820         rte_free(buf);
4821
4822         return ret;
4823 }
4824
4825 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4826
4827 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4828                 const char *value,
4829                 void *opaque)
4830 {
4831         struct i40e_pf *pf;
4832         unsigned long num;
4833         char *end;
4834
4835         pf = (struct i40e_pf *)opaque;
4836         RTE_SET_USED(key);
4837
4838         errno = 0;
4839         num = strtoul(value, &end, 0);
4840         if (errno != 0 || end == value || *end != 0) {
4841                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4842                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4843                 return -(EINVAL);
4844         }
4845
4846         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4847                 pf->vf_nb_qp_max = (uint16_t)num;
4848         else
4849                 /* here return 0 to make next valid same argument work */
4850                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4851                             "power of 2 and equal or less than 16 !, Now it is "
4852                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4853
4854         return 0;
4855 }
4856
4857 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4858 {
4859         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4860         struct rte_kvargs *kvlist;
4861         int kvargs_count;
4862
4863         /* set default queue number per VF as 4 */
4864         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4865
4866         if (dev->device->devargs == NULL)
4867                 return 0;
4868
4869         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4870         if (kvlist == NULL)
4871                 return -(EINVAL);
4872
4873         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4874         if (!kvargs_count) {
4875                 rte_kvargs_free(kvlist);
4876                 return 0;
4877         }
4878
4879         if (kvargs_count > 1)
4880                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4881                             "the first invalid or last valid one is used !",
4882                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4883
4884         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4885                            i40e_pf_parse_vf_queue_number_handler, pf);
4886
4887         rte_kvargs_free(kvlist);
4888
4889         return 0;
4890 }
4891
4892 static int
4893 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4894 {
4895         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4896         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4897         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4898         uint16_t qp_count = 0, vsi_count = 0;
4899
4900         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4901                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4902                 return -EINVAL;
4903         }
4904
4905         i40e_pf_config_vf_rxq_number(dev);
4906
4907         /* Add the parameter init for LFC */
4908         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4909         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4910         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4911
4912         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4913         pf->max_num_vsi = hw->func_caps.num_vsis;
4914         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4915         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4916
4917         /* FDir queue/VSI allocation */
4918         pf->fdir_qp_offset = 0;
4919         if (hw->func_caps.fd) {
4920                 pf->flags |= I40E_FLAG_FDIR;
4921                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4922         } else {
4923                 pf->fdir_nb_qps = 0;
4924         }
4925         qp_count += pf->fdir_nb_qps;
4926         vsi_count += 1;
4927
4928         /* LAN queue/VSI allocation */
4929         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4930         if (!hw->func_caps.rss) {
4931                 pf->lan_nb_qps = 1;
4932         } else {
4933                 pf->flags |= I40E_FLAG_RSS;
4934                 if (hw->mac.type == I40E_MAC_X722)
4935                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4936                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4937         }
4938         qp_count += pf->lan_nb_qps;
4939         vsi_count += 1;
4940
4941         /* VF queue/VSI allocation */
4942         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4943         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4944                 pf->flags |= I40E_FLAG_SRIOV;
4945                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4946                 pf->vf_num = pci_dev->max_vfs;
4947                 PMD_DRV_LOG(DEBUG,
4948                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4949                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4950         } else {
4951                 pf->vf_nb_qps = 0;
4952                 pf->vf_num = 0;
4953         }
4954         qp_count += pf->vf_nb_qps * pf->vf_num;
4955         vsi_count += pf->vf_num;
4956
4957         /* VMDq queue/VSI allocation */
4958         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4959         pf->vmdq_nb_qps = 0;
4960         pf->max_nb_vmdq_vsi = 0;
4961         if (hw->func_caps.vmdq) {
4962                 if (qp_count < hw->func_caps.num_tx_qp &&
4963                         vsi_count < hw->func_caps.num_vsis) {
4964                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4965                                 qp_count) / pf->vmdq_nb_qp_max;
4966
4967                         /* Limit the maximum number of VMDq vsi to the maximum
4968                          * ethdev can support
4969                          */
4970                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4971                                 hw->func_caps.num_vsis - vsi_count);
4972                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4973                                 ETH_64_POOLS);
4974                         if (pf->max_nb_vmdq_vsi) {
4975                                 pf->flags |= I40E_FLAG_VMDQ;
4976                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4977                                 PMD_DRV_LOG(DEBUG,
4978                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4979                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4980                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4981                         } else {
4982                                 PMD_DRV_LOG(INFO,
4983                                         "No enough queues left for VMDq");
4984                         }
4985                 } else {
4986                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4987                 }
4988         }
4989         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4990         vsi_count += pf->max_nb_vmdq_vsi;
4991
4992         if (hw->func_caps.dcb)
4993                 pf->flags |= I40E_FLAG_DCB;
4994
4995         if (qp_count > hw->func_caps.num_tx_qp) {
4996                 PMD_DRV_LOG(ERR,
4997                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4998                         qp_count, hw->func_caps.num_tx_qp);
4999                 return -EINVAL;
5000         }
5001         if (vsi_count > hw->func_caps.num_vsis) {
5002                 PMD_DRV_LOG(ERR,
5003                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
5004                         vsi_count, hw->func_caps.num_vsis);
5005                 return -EINVAL;
5006         }
5007
5008         return 0;
5009 }
5010
5011 static int
5012 i40e_pf_get_switch_config(struct i40e_pf *pf)
5013 {
5014         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5015         struct i40e_aqc_get_switch_config_resp *switch_config;
5016         struct i40e_aqc_switch_config_element_resp *element;
5017         uint16_t start_seid = 0, num_reported;
5018         int ret;
5019
5020         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
5021                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
5022         if (!switch_config) {
5023                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
5024                 return -ENOMEM;
5025         }
5026
5027         /* Get the switch configurations */
5028         ret = i40e_aq_get_switch_config(hw, switch_config,
5029                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
5030         if (ret != I40E_SUCCESS) {
5031                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
5032                 goto fail;
5033         }
5034         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
5035         if (num_reported != 1) { /* The number should be 1 */
5036                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
5037                 goto fail;
5038         }
5039
5040         /* Parse the switch configuration elements */
5041         element = &(switch_config->element[0]);
5042         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
5043                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
5044                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
5045         } else
5046                 PMD_DRV_LOG(INFO, "Unknown element type");
5047
5048 fail:
5049         rte_free(switch_config);
5050
5051         return ret;
5052 }
5053
5054 static int
5055 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
5056                         uint32_t num)
5057 {
5058         struct pool_entry *entry;
5059
5060         if (pool == NULL || num == 0)
5061                 return -EINVAL;
5062
5063         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5064         if (entry == NULL) {
5065                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5066                 return -ENOMEM;
5067         }
5068
5069         /* queue heap initialize */
5070         pool->num_free = num;
5071         pool->num_alloc = 0;
5072         pool->base = base;
5073         LIST_INIT(&pool->alloc_list);
5074         LIST_INIT(&pool->free_list);
5075
5076         /* Initialize element  */
5077         entry->base = 0;
5078         entry->len = num;
5079
5080         LIST_INSERT_HEAD(&pool->free_list, entry, next);
5081         return 0;
5082 }
5083
5084 static void
5085 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5086 {
5087         struct pool_entry *entry, *next_entry;
5088
5089         if (pool == NULL)
5090                 return;
5091
5092         for (entry = LIST_FIRST(&pool->alloc_list);
5093                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5094                         entry = next_entry) {
5095                 LIST_REMOVE(entry, next);
5096                 rte_free(entry);
5097         }
5098
5099         for (entry = LIST_FIRST(&pool->free_list);
5100                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5101                         entry = next_entry) {
5102                 LIST_REMOVE(entry, next);
5103                 rte_free(entry);
5104         }
5105
5106         pool->num_free = 0;
5107         pool->num_alloc = 0;
5108         pool->base = 0;
5109         LIST_INIT(&pool->alloc_list);
5110         LIST_INIT(&pool->free_list);
5111 }
5112
5113 static int
5114 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5115                        uint32_t base)
5116 {
5117         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5118         uint32_t pool_offset;
5119         uint16_t len;
5120         int insert;
5121
5122         if (pool == NULL) {
5123                 PMD_DRV_LOG(ERR, "Invalid parameter");
5124                 return -EINVAL;
5125         }
5126
5127         pool_offset = base - pool->base;
5128         /* Lookup in alloc list */
5129         LIST_FOREACH(entry, &pool->alloc_list, next) {
5130                 if (entry->base == pool_offset) {
5131                         valid_entry = entry;
5132                         LIST_REMOVE(entry, next);
5133                         break;
5134                 }
5135         }
5136
5137         /* Not find, return */
5138         if (valid_entry == NULL) {
5139                 PMD_DRV_LOG(ERR, "Failed to find entry");
5140                 return -EINVAL;
5141         }
5142
5143         /**
5144          * Found it, move it to free list  and try to merge.
5145          * In order to make merge easier, always sort it by qbase.
5146          * Find adjacent prev and last entries.
5147          */
5148         prev = next = NULL;
5149         LIST_FOREACH(entry, &pool->free_list, next) {
5150                 if (entry->base > valid_entry->base) {
5151                         next = entry;
5152                         break;
5153                 }
5154                 prev = entry;
5155         }
5156
5157         insert = 0;
5158         len = valid_entry->len;
5159         /* Try to merge with next one*/
5160         if (next != NULL) {
5161                 /* Merge with next one */
5162                 if (valid_entry->base + len == next->base) {
5163                         next->base = valid_entry->base;
5164                         next->len += len;
5165                         rte_free(valid_entry);
5166                         valid_entry = next;
5167                         insert = 1;
5168                 }
5169         }
5170
5171         if (prev != NULL) {
5172                 /* Merge with previous one */
5173                 if (prev->base + prev->len == valid_entry->base) {
5174                         prev->len += len;
5175                         /* If it merge with next one, remove next node */
5176                         if (insert == 1) {
5177                                 LIST_REMOVE(valid_entry, next);
5178                                 rte_free(valid_entry);
5179                                 valid_entry = NULL;
5180                         } else {
5181                                 rte_free(valid_entry);
5182                                 valid_entry = NULL;
5183                                 insert = 1;
5184                         }
5185                 }
5186         }
5187
5188         /* Not find any entry to merge, insert */
5189         if (insert == 0) {
5190                 if (prev != NULL)
5191                         LIST_INSERT_AFTER(prev, valid_entry, next);
5192                 else if (next != NULL)
5193                         LIST_INSERT_BEFORE(next, valid_entry, next);
5194                 else /* It's empty list, insert to head */
5195                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5196         }
5197
5198         pool->num_free += len;
5199         pool->num_alloc -= len;
5200
5201         return 0;
5202 }
5203
5204 static int
5205 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5206                        uint16_t num)
5207 {
5208         struct pool_entry *entry, *valid_entry;
5209
5210         if (pool == NULL || num == 0) {
5211                 PMD_DRV_LOG(ERR, "Invalid parameter");
5212                 return -EINVAL;
5213         }
5214
5215         if (pool->num_free < num) {
5216                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5217                             num, pool->num_free);
5218                 return -ENOMEM;
5219         }
5220
5221         valid_entry = NULL;
5222         /* Lookup  in free list and find most fit one */
5223         LIST_FOREACH(entry, &pool->free_list, next) {
5224                 if (entry->len >= num) {
5225                         /* Find best one */
5226                         if (entry->len == num) {
5227                                 valid_entry = entry;
5228                                 break;
5229                         }
5230                         if (valid_entry == NULL || valid_entry->len > entry->len)
5231                                 valid_entry = entry;
5232                 }
5233         }
5234
5235         /* Not find one to satisfy the request, return */
5236         if (valid_entry == NULL) {
5237                 PMD_DRV_LOG(ERR, "No valid entry found");
5238                 return -ENOMEM;
5239         }
5240         /**
5241          * The entry have equal queue number as requested,
5242          * remove it from alloc_list.
5243          */
5244         if (valid_entry->len == num) {
5245                 LIST_REMOVE(valid_entry, next);
5246         } else {
5247                 /**
5248                  * The entry have more numbers than requested,
5249                  * create a new entry for alloc_list and minus its
5250                  * queue base and number in free_list.
5251                  */
5252                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5253                 if (entry == NULL) {
5254                         PMD_DRV_LOG(ERR,
5255                                 "Failed to allocate memory for resource pool");
5256                         return -ENOMEM;
5257                 }
5258                 entry->base = valid_entry->base;
5259                 entry->len = num;
5260                 valid_entry->base += num;
5261                 valid_entry->len -= num;
5262                 valid_entry = entry;
5263         }
5264
5265         /* Insert it into alloc list, not sorted */
5266         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5267
5268         pool->num_free -= valid_entry->len;
5269         pool->num_alloc += valid_entry->len;
5270
5271         return valid_entry->base + pool->base;
5272 }
5273
5274 /**
5275  * bitmap_is_subset - Check whether src2 is subset of src1
5276  **/
5277 static inline int
5278 bitmap_is_subset(uint8_t src1, uint8_t src2)
5279 {
5280         return !((src1 ^ src2) & src2);
5281 }
5282
5283 static enum i40e_status_code
5284 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5285 {
5286         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5287
5288         /* If DCB is not supported, only default TC is supported */
5289         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5290                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5291                 return I40E_NOT_SUPPORTED;
5292         }
5293
5294         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5295                 PMD_DRV_LOG(ERR,
5296                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5297                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5298                 return I40E_NOT_SUPPORTED;
5299         }
5300         return I40E_SUCCESS;
5301 }
5302
5303 int
5304 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5305                                 struct i40e_vsi_vlan_pvid_info *info)
5306 {
5307         struct i40e_hw *hw;
5308         struct i40e_vsi_context ctxt;
5309         uint8_t vlan_flags = 0;
5310         int ret;
5311
5312         if (vsi == NULL || info == NULL) {
5313                 PMD_DRV_LOG(ERR, "invalid parameters");
5314                 return I40E_ERR_PARAM;
5315         }
5316
5317         if (info->on) {
5318                 vsi->info.pvid = info->config.pvid;
5319                 /**
5320                  * If insert pvid is enabled, only tagged pkts are
5321                  * allowed to be sent out.
5322                  */
5323                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5324                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5325         } else {
5326                 vsi->info.pvid = 0;
5327                 if (info->config.reject.tagged == 0)
5328                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5329
5330                 if (info->config.reject.untagged == 0)
5331                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5332         }
5333         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5334                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5335         vsi->info.port_vlan_flags |= vlan_flags;
5336         vsi->info.valid_sections =
5337                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5338         memset(&ctxt, 0, sizeof(ctxt));
5339         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5340         ctxt.seid = vsi->seid;
5341
5342         hw = I40E_VSI_TO_HW(vsi);
5343         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5344         if (ret != I40E_SUCCESS)
5345                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5346
5347         return ret;
5348 }
5349
5350 static int
5351 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5352 {
5353         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5354         int i, ret;
5355         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5356
5357         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5358         if (ret != I40E_SUCCESS)
5359                 return ret;
5360
5361         if (!vsi->seid) {
5362                 PMD_DRV_LOG(ERR, "seid not valid");
5363                 return -EINVAL;
5364         }
5365
5366         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5367         tc_bw_data.tc_valid_bits = enabled_tcmap;
5368         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5369                 tc_bw_data.tc_bw_credits[i] =
5370                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5371
5372         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5373         if (ret != I40E_SUCCESS) {
5374                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5375                 return ret;
5376         }
5377
5378         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5379                                         sizeof(vsi->info.qs_handle));
5380         return I40E_SUCCESS;
5381 }
5382
5383 static enum i40e_status_code
5384 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5385                                  struct i40e_aqc_vsi_properties_data *info,
5386                                  uint8_t enabled_tcmap)
5387 {
5388         enum i40e_status_code ret;
5389         int i, total_tc = 0;
5390         uint16_t qpnum_per_tc, bsf, qp_idx;
5391
5392         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5393         if (ret != I40E_SUCCESS)
5394                 return ret;
5395
5396         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5397                 if (enabled_tcmap & (1 << i))
5398                         total_tc++;
5399         if (total_tc == 0)
5400                 total_tc = 1;
5401         vsi->enabled_tc = enabled_tcmap;
5402
5403         /* Number of queues per enabled TC */
5404         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5405         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5406         bsf = rte_bsf32(qpnum_per_tc);
5407
5408         /* Adjust the queue number to actual queues that can be applied */
5409         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5410                 vsi->nb_qps = qpnum_per_tc * total_tc;
5411
5412         /**
5413          * Configure TC and queue mapping parameters, for enabled TC,
5414          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5415          * default queue will serve it.
5416          */
5417         qp_idx = 0;
5418         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5419                 if (vsi->enabled_tc & (1 << i)) {
5420                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5421                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5422                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5423                         qp_idx += qpnum_per_tc;
5424                 } else
5425                         info->tc_mapping[i] = 0;
5426         }
5427
5428         /* Associate queue number with VSI */
5429         if (vsi->type == I40E_VSI_SRIOV) {
5430                 info->mapping_flags |=
5431                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5432                 for (i = 0; i < vsi->nb_qps; i++)
5433                         info->queue_mapping[i] =
5434                                 rte_cpu_to_le_16(vsi->base_queue + i);
5435         } else {
5436                 info->mapping_flags |=
5437                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5438                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5439         }
5440         info->valid_sections |=
5441                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5442
5443         return I40E_SUCCESS;
5444 }
5445
5446 static int
5447 i40e_veb_release(struct i40e_veb *veb)
5448 {
5449         struct i40e_vsi *vsi;
5450         struct i40e_hw *hw;
5451
5452         if (veb == NULL)
5453                 return -EINVAL;
5454
5455         if (!TAILQ_EMPTY(&veb->head)) {
5456                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5457                 return -EACCES;
5458         }
5459         /* associate_vsi field is NULL for floating VEB */
5460         if (veb->associate_vsi != NULL) {
5461                 vsi = veb->associate_vsi;
5462                 hw = I40E_VSI_TO_HW(vsi);
5463
5464                 vsi->uplink_seid = veb->uplink_seid;
5465                 vsi->veb = NULL;
5466         } else {
5467                 veb->associate_pf->main_vsi->floating_veb = NULL;
5468                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5469         }
5470
5471         i40e_aq_delete_element(hw, veb->seid, NULL);
5472         rte_free(veb);
5473         return I40E_SUCCESS;
5474 }
5475
5476 /* Setup a veb */
5477 static struct i40e_veb *
5478 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5479 {
5480         struct i40e_veb *veb;
5481         int ret;
5482         struct i40e_hw *hw;
5483
5484         if (pf == NULL) {
5485                 PMD_DRV_LOG(ERR,
5486                             "veb setup failed, associated PF shouldn't null");
5487                 return NULL;
5488         }
5489         hw = I40E_PF_TO_HW(pf);
5490
5491         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5492         if (!veb) {
5493                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5494                 goto fail;
5495         }
5496
5497         veb->associate_vsi = vsi;
5498         veb->associate_pf = pf;
5499         TAILQ_INIT(&veb->head);
5500         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5501
5502         /* create floating veb if vsi is NULL */
5503         if (vsi != NULL) {
5504                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5505                                       I40E_DEFAULT_TCMAP, false,
5506                                       &veb->seid, false, NULL);
5507         } else {
5508                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5509                                       true, &veb->seid, false, NULL);
5510         }
5511
5512         if (ret != I40E_SUCCESS) {
5513                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5514                             hw->aq.asq_last_status);
5515                 goto fail;
5516         }
5517         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5518
5519         /* get statistics index */
5520         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5521                                 &veb->stats_idx, NULL, NULL, NULL);
5522         if (ret != I40E_SUCCESS) {
5523                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5524                             hw->aq.asq_last_status);
5525                 goto fail;
5526         }
5527         /* Get VEB bandwidth, to be implemented */
5528         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5529         if (vsi)
5530                 vsi->uplink_seid = veb->seid;
5531
5532         return veb;
5533 fail:
5534         rte_free(veb);
5535         return NULL;
5536 }
5537
5538 int
5539 i40e_vsi_release(struct i40e_vsi *vsi)
5540 {
5541         struct i40e_pf *pf;
5542         struct i40e_hw *hw;
5543         struct i40e_vsi_list *vsi_list;
5544         void *temp;
5545         int ret;
5546         struct i40e_mac_filter *f;
5547         uint16_t user_param;
5548
5549         if (!vsi)
5550                 return I40E_SUCCESS;
5551
5552         if (!vsi->adapter)
5553                 return -EFAULT;
5554
5555         user_param = vsi->user_param;
5556
5557         pf = I40E_VSI_TO_PF(vsi);
5558         hw = I40E_VSI_TO_HW(vsi);
5559
5560         /* VSI has child to attach, release child first */
5561         if (vsi->veb) {
5562                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5563                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5564                                 return -1;
5565                 }
5566                 i40e_veb_release(vsi->veb);
5567         }
5568
5569         if (vsi->floating_veb) {
5570                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5571                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5572                                 return -1;
5573                 }
5574         }
5575
5576         /* Remove all macvlan filters of the VSI */
5577         i40e_vsi_remove_all_macvlan_filter(vsi);
5578         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5579                 rte_free(f);
5580
5581         if (vsi->type != I40E_VSI_MAIN &&
5582             ((vsi->type != I40E_VSI_SRIOV) ||
5583             !pf->floating_veb_list[user_param])) {
5584                 /* Remove vsi from parent's sibling list */
5585                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5586                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5587                         return I40E_ERR_PARAM;
5588                 }
5589                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5590                                 &vsi->sib_vsi_list, list);
5591
5592                 /* Remove all switch element of the VSI */
5593                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5594                 if (ret != I40E_SUCCESS)
5595                         PMD_DRV_LOG(ERR, "Failed to delete element");
5596         }
5597
5598         if ((vsi->type == I40E_VSI_SRIOV) &&
5599             pf->floating_veb_list[user_param]) {
5600                 /* Remove vsi from parent's sibling list */
5601                 if (vsi->parent_vsi == NULL ||
5602                     vsi->parent_vsi->floating_veb == NULL) {
5603                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5604                         return I40E_ERR_PARAM;
5605                 }
5606                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5607                              &vsi->sib_vsi_list, list);
5608
5609                 /* Remove all switch element of the VSI */
5610                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5611                 if (ret != I40E_SUCCESS)
5612                         PMD_DRV_LOG(ERR, "Failed to delete element");
5613         }
5614
5615         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5616
5617         if (vsi->type != I40E_VSI_SRIOV)
5618                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5619         rte_free(vsi);
5620
5621         return I40E_SUCCESS;
5622 }
5623
5624 static int
5625 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5626 {
5627         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5628         struct i40e_aqc_remove_macvlan_element_data def_filter;
5629         struct i40e_mac_filter_info filter;
5630         int ret;
5631
5632         if (vsi->type != I40E_VSI_MAIN)
5633                 return I40E_ERR_CONFIG;
5634         memset(&def_filter, 0, sizeof(def_filter));
5635         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5636                                         ETH_ADDR_LEN);
5637         def_filter.vlan_tag = 0;
5638         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5639                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5640         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5641         if (ret != I40E_SUCCESS) {
5642                 struct i40e_mac_filter *f;
5643                 struct rte_ether_addr *mac;
5644
5645                 PMD_DRV_LOG(DEBUG,
5646                             "Cannot remove the default macvlan filter");
5647                 /* It needs to add the permanent mac into mac list */
5648                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5649                 if (f == NULL) {
5650                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5651                         return I40E_ERR_NO_MEMORY;
5652                 }
5653                 mac = &f->mac_info.mac_addr;
5654                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5655                                 ETH_ADDR_LEN);
5656                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5657                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5658                 vsi->mac_num++;
5659
5660                 return ret;
5661         }
5662         rte_memcpy(&filter.mac_addr,
5663                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5664         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5665         return i40e_vsi_add_mac(vsi, &filter);
5666 }
5667
5668 /*
5669  * i40e_vsi_get_bw_config - Query VSI BW Information
5670  * @vsi: the VSI to be queried
5671  *
5672  * Returns 0 on success, negative value on failure
5673  */
5674 static enum i40e_status_code
5675 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5676 {
5677         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5678         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5679         struct i40e_hw *hw = &vsi->adapter->hw;
5680         i40e_status ret;
5681         int i;
5682         uint32_t bw_max;
5683
5684         memset(&bw_config, 0, sizeof(bw_config));
5685         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5686         if (ret != I40E_SUCCESS) {
5687                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5688                             hw->aq.asq_last_status);
5689                 return ret;
5690         }
5691
5692         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5693         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5694                                         &ets_sla_config, NULL);
5695         if (ret != I40E_SUCCESS) {
5696                 PMD_DRV_LOG(ERR,
5697                         "VSI failed to get TC bandwdith configuration %u",
5698                         hw->aq.asq_last_status);
5699                 return ret;
5700         }
5701
5702         /* store and print out BW info */
5703         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5704         vsi->bw_info.bw_max = bw_config.max_bw;
5705         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5706         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5707         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5708                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5709                      I40E_16_BIT_WIDTH);
5710         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5711                 vsi->bw_info.bw_ets_share_credits[i] =
5712                                 ets_sla_config.share_credits[i];
5713                 vsi->bw_info.bw_ets_credits[i] =
5714                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5715                 /* 4 bits per TC, 4th bit is reserved */
5716                 vsi->bw_info.bw_ets_max[i] =
5717                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5718                                   RTE_LEN2MASK(3, uint8_t));
5719                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5720                             vsi->bw_info.bw_ets_share_credits[i]);
5721                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5722                             vsi->bw_info.bw_ets_credits[i]);
5723                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5724                             vsi->bw_info.bw_ets_max[i]);
5725         }
5726
5727         return I40E_SUCCESS;
5728 }
5729
5730 /* i40e_enable_pf_lb
5731  * @pf: pointer to the pf structure
5732  *
5733  * allow loopback on pf
5734  */
5735 static inline void
5736 i40e_enable_pf_lb(struct i40e_pf *pf)
5737 {
5738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5739         struct i40e_vsi_context ctxt;
5740         int ret;
5741
5742         /* Use the FW API if FW >= v5.0 */
5743         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5744                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5745                 return;
5746         }
5747
5748         memset(&ctxt, 0, sizeof(ctxt));
5749         ctxt.seid = pf->main_vsi_seid;
5750         ctxt.pf_num = hw->pf_id;
5751         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5752         if (ret) {
5753                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5754                             ret, hw->aq.asq_last_status);
5755                 return;
5756         }
5757         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5758         ctxt.info.valid_sections =
5759                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5760         ctxt.info.switch_id |=
5761                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5762
5763         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5764         if (ret)
5765                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5766                             hw->aq.asq_last_status);
5767 }
5768
5769 /* Setup a VSI */
5770 struct i40e_vsi *
5771 i40e_vsi_setup(struct i40e_pf *pf,
5772                enum i40e_vsi_type type,
5773                struct i40e_vsi *uplink_vsi,
5774                uint16_t user_param)
5775 {
5776         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5777         struct i40e_vsi *vsi;
5778         struct i40e_mac_filter_info filter;
5779         int ret;
5780         struct i40e_vsi_context ctxt;
5781         struct rte_ether_addr broadcast =
5782                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5783
5784         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5785             uplink_vsi == NULL) {
5786                 PMD_DRV_LOG(ERR,
5787                         "VSI setup failed, VSI link shouldn't be NULL");
5788                 return NULL;
5789         }
5790
5791         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5792                 PMD_DRV_LOG(ERR,
5793                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5794                 return NULL;
5795         }
5796
5797         /* two situations
5798          * 1.type is not MAIN and uplink vsi is not NULL
5799          * If uplink vsi didn't setup VEB, create one first under veb field
5800          * 2.type is SRIOV and the uplink is NULL
5801          * If floating VEB is NULL, create one veb under floating veb field
5802          */
5803
5804         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5805             uplink_vsi->veb == NULL) {
5806                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5807
5808                 if (uplink_vsi->veb == NULL) {
5809                         PMD_DRV_LOG(ERR, "VEB setup failed");
5810                         return NULL;
5811                 }
5812                 /* set ALLOWLOOPBACk on pf, when veb is created */
5813                 i40e_enable_pf_lb(pf);
5814         }
5815
5816         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5817             pf->main_vsi->floating_veb == NULL) {
5818                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5819
5820                 if (pf->main_vsi->floating_veb == NULL) {
5821                         PMD_DRV_LOG(ERR, "VEB setup failed");
5822                         return NULL;
5823                 }
5824         }
5825
5826         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5827         if (!vsi) {
5828                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5829                 return NULL;
5830         }
5831         TAILQ_INIT(&vsi->mac_list);
5832         vsi->type = type;
5833         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5834         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5835         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5836         vsi->user_param = user_param;
5837         vsi->vlan_anti_spoof_on = 0;
5838         vsi->vlan_filter_on = 0;
5839         /* Allocate queues */
5840         switch (vsi->type) {
5841         case I40E_VSI_MAIN  :
5842                 vsi->nb_qps = pf->lan_nb_qps;
5843                 break;
5844         case I40E_VSI_SRIOV :
5845                 vsi->nb_qps = pf->vf_nb_qps;
5846                 break;
5847         case I40E_VSI_VMDQ2:
5848                 vsi->nb_qps = pf->vmdq_nb_qps;
5849                 break;
5850         case I40E_VSI_FDIR:
5851                 vsi->nb_qps = pf->fdir_nb_qps;
5852                 break;
5853         default:
5854                 goto fail_mem;
5855         }
5856         /*
5857          * The filter status descriptor is reported in rx queue 0,
5858          * while the tx queue for fdir filter programming has no
5859          * such constraints, can be non-zero queues.
5860          * To simplify it, choose FDIR vsi use queue 0 pair.
5861          * To make sure it will use queue 0 pair, queue allocation
5862          * need be done before this function is called
5863          */
5864         if (type != I40E_VSI_FDIR) {
5865                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5866                         if (ret < 0) {
5867                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5868                                                 vsi->seid, ret);
5869                                 goto fail_mem;
5870                         }
5871                         vsi->base_queue = ret;
5872         } else
5873                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5874
5875         /* VF has MSIX interrupt in VF range, don't allocate here */
5876         if (type == I40E_VSI_MAIN) {
5877                 if (pf->support_multi_driver) {
5878                         /* If support multi-driver, need to use INT0 instead of
5879                          * allocating from msix pool. The Msix pool is init from
5880                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5881                          * to 1 without calling i40e_res_pool_alloc.
5882                          */
5883                         vsi->msix_intr = 0;
5884                         vsi->nb_msix = 1;
5885                 } else {
5886                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5887                                                   RTE_MIN(vsi->nb_qps,
5888                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5889                         if (ret < 0) {
5890                                 PMD_DRV_LOG(ERR,
5891                                             "VSI MAIN %d get heap failed %d",
5892                                             vsi->seid, ret);
5893                                 goto fail_queue_alloc;
5894                         }
5895                         vsi->msix_intr = ret;
5896                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5897                                                RTE_MAX_RXTX_INTR_VEC_ID);
5898                 }
5899         } else if (type != I40E_VSI_SRIOV) {
5900                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5901                 if (ret < 0) {
5902                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5903                         if (type != I40E_VSI_FDIR)
5904                                 goto fail_queue_alloc;
5905                         vsi->msix_intr = 0;
5906                         vsi->nb_msix = 0;
5907                 } else {
5908                         vsi->msix_intr = ret;
5909                         vsi->nb_msix = 1;
5910                 }
5911         } else {
5912                 vsi->msix_intr = 0;
5913                 vsi->nb_msix = 0;
5914         }
5915
5916         /* Add VSI */
5917         if (type == I40E_VSI_MAIN) {
5918                 /* For main VSI, no need to add since it's default one */
5919                 vsi->uplink_seid = pf->mac_seid;
5920                 vsi->seid = pf->main_vsi_seid;
5921                 /* Bind queues with specific MSIX interrupt */
5922                 /**
5923                  * Needs 2 interrupt at least, one for misc cause which will
5924                  * enabled from OS side, Another for queues binding the
5925                  * interrupt from device side only.
5926                  */
5927
5928                 /* Get default VSI parameters from hardware */
5929                 memset(&ctxt, 0, sizeof(ctxt));
5930                 ctxt.seid = vsi->seid;
5931                 ctxt.pf_num = hw->pf_id;
5932                 ctxt.uplink_seid = vsi->uplink_seid;
5933                 ctxt.vf_num = 0;
5934                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5935                 if (ret != I40E_SUCCESS) {
5936                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5937                         goto fail_msix_alloc;
5938                 }
5939                 rte_memcpy(&vsi->info, &ctxt.info,
5940                         sizeof(struct i40e_aqc_vsi_properties_data));
5941                 vsi->vsi_id = ctxt.vsi_number;
5942                 vsi->info.valid_sections = 0;
5943
5944                 /* Configure tc, enabled TC0 only */
5945                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5946                         I40E_SUCCESS) {
5947                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5948                         goto fail_msix_alloc;
5949                 }
5950
5951                 /* TC, queue mapping */
5952                 memset(&ctxt, 0, sizeof(ctxt));
5953                 vsi->info.valid_sections |=
5954                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5955                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5956                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5957                 rte_memcpy(&ctxt.info, &vsi->info,
5958                         sizeof(struct i40e_aqc_vsi_properties_data));
5959                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5960                                                 I40E_DEFAULT_TCMAP);
5961                 if (ret != I40E_SUCCESS) {
5962                         PMD_DRV_LOG(ERR,
5963                                 "Failed to configure TC queue mapping");
5964                         goto fail_msix_alloc;
5965                 }
5966                 ctxt.seid = vsi->seid;
5967                 ctxt.pf_num = hw->pf_id;
5968                 ctxt.uplink_seid = vsi->uplink_seid;
5969                 ctxt.vf_num = 0;
5970
5971                 /* Update VSI parameters */
5972                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5973                 if (ret != I40E_SUCCESS) {
5974                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5975                         goto fail_msix_alloc;
5976                 }
5977
5978                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5979                                                 sizeof(vsi->info.tc_mapping));
5980                 rte_memcpy(&vsi->info.queue_mapping,
5981                                 &ctxt.info.queue_mapping,
5982                         sizeof(vsi->info.queue_mapping));
5983                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5984                 vsi->info.valid_sections = 0;
5985
5986                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5987                                 ETH_ADDR_LEN);
5988
5989                 /**
5990                  * Updating default filter settings are necessary to prevent
5991                  * reception of tagged packets.
5992                  * Some old firmware configurations load a default macvlan
5993                  * filter which accepts both tagged and untagged packets.
5994                  * The updating is to use a normal filter instead if needed.
5995                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5996                  * The firmware with correct configurations load the default
5997                  * macvlan filter which is expected and cannot be removed.
5998                  */
5999                 i40e_update_default_filter_setting(vsi);
6000                 i40e_config_qinq(hw, vsi);
6001         } else if (type == I40E_VSI_SRIOV) {
6002                 memset(&ctxt, 0, sizeof(ctxt));
6003                 /**
6004                  * For other VSI, the uplink_seid equals to uplink VSI's
6005                  * uplink_seid since they share same VEB
6006                  */
6007                 if (uplink_vsi == NULL)
6008                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
6009                 else
6010                         vsi->uplink_seid = uplink_vsi->uplink_seid;
6011                 ctxt.pf_num = hw->pf_id;
6012                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
6013                 ctxt.uplink_seid = vsi->uplink_seid;
6014                 ctxt.connection_type = 0x1;
6015                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
6016
6017                 /* Use the VEB configuration if FW >= v5.0 */
6018                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
6019                         /* Configure switch ID */
6020                         ctxt.info.valid_sections |=
6021                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6022                         ctxt.info.switch_id =
6023                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6024                 }
6025
6026                 /* Configure port/vlan */
6027                 ctxt.info.valid_sections |=
6028                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6029                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6030                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6031                                                 hw->func_caps.enabled_tcmap);
6032                 if (ret != I40E_SUCCESS) {
6033                         PMD_DRV_LOG(ERR,
6034                                 "Failed to configure TC queue mapping");
6035                         goto fail_msix_alloc;
6036                 }
6037
6038                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
6039                 ctxt.info.valid_sections |=
6040                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6041                 /**
6042                  * Since VSI is not created yet, only configure parameter,
6043                  * will add vsi below.
6044                  */
6045
6046                 i40e_config_qinq(hw, vsi);
6047         } else if (type == I40E_VSI_VMDQ2) {
6048                 memset(&ctxt, 0, sizeof(ctxt));
6049                 /*
6050                  * For other VSI, the uplink_seid equals to uplink VSI's
6051                  * uplink_seid since they share same VEB
6052                  */
6053                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6054                 ctxt.pf_num = hw->pf_id;
6055                 ctxt.vf_num = 0;
6056                 ctxt.uplink_seid = vsi->uplink_seid;
6057                 ctxt.connection_type = 0x1;
6058                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6059
6060                 ctxt.info.valid_sections |=
6061                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6062                 /* user_param carries flag to enable loop back */
6063                 if (user_param) {
6064                         ctxt.info.switch_id =
6065                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6066                         ctxt.info.switch_id |=
6067                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6068                 }
6069
6070                 /* Configure port/vlan */
6071                 ctxt.info.valid_sections |=
6072                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6073                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6074                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6075                                                 I40E_DEFAULT_TCMAP);
6076                 if (ret != I40E_SUCCESS) {
6077                         PMD_DRV_LOG(ERR,
6078                                 "Failed to configure TC queue mapping");
6079                         goto fail_msix_alloc;
6080                 }
6081                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6082                 ctxt.info.valid_sections |=
6083                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6084         } else if (type == I40E_VSI_FDIR) {
6085                 memset(&ctxt, 0, sizeof(ctxt));
6086                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6087                 ctxt.pf_num = hw->pf_id;
6088                 ctxt.vf_num = 0;
6089                 ctxt.uplink_seid = vsi->uplink_seid;
6090                 ctxt.connection_type = 0x1;     /* regular data port */
6091                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6092                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6093                                                 I40E_DEFAULT_TCMAP);
6094                 if (ret != I40E_SUCCESS) {
6095                         PMD_DRV_LOG(ERR,
6096                                 "Failed to configure TC queue mapping.");
6097                         goto fail_msix_alloc;
6098                 }
6099                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6100                 ctxt.info.valid_sections |=
6101                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6102         } else {
6103                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6104                 goto fail_msix_alloc;
6105         }
6106
6107         if (vsi->type != I40E_VSI_MAIN) {
6108                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6109                 if (ret != I40E_SUCCESS) {
6110                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6111                                     hw->aq.asq_last_status);
6112                         goto fail_msix_alloc;
6113                 }
6114                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6115                 vsi->info.valid_sections = 0;
6116                 vsi->seid = ctxt.seid;
6117                 vsi->vsi_id = ctxt.vsi_number;
6118                 vsi->sib_vsi_list.vsi = vsi;
6119                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6120                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6121                                           &vsi->sib_vsi_list, list);
6122                 } else {
6123                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6124                                           &vsi->sib_vsi_list, list);
6125                 }
6126         }
6127
6128         /* MAC/VLAN configuration */
6129         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6130         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6131
6132         ret = i40e_vsi_add_mac(vsi, &filter);
6133         if (ret != I40E_SUCCESS) {
6134                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6135                 goto fail_msix_alloc;
6136         }
6137
6138         /* Get VSI BW information */
6139         i40e_vsi_get_bw_config(vsi);
6140         return vsi;
6141 fail_msix_alloc:
6142         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6143 fail_queue_alloc:
6144         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6145 fail_mem:
6146         rte_free(vsi);
6147         return NULL;
6148 }
6149
6150 /* Configure vlan filter on or off */
6151 int
6152 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6153 {
6154         int i, num;
6155         struct i40e_mac_filter *f;
6156         void *temp;
6157         struct i40e_mac_filter_info *mac_filter;
6158         enum rte_mac_filter_type desired_filter;
6159         int ret = I40E_SUCCESS;
6160
6161         if (on) {
6162                 /* Filter to match MAC and VLAN */
6163                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6164         } else {
6165                 /* Filter to match only MAC */
6166                 desired_filter = RTE_MAC_PERFECT_MATCH;
6167         }
6168
6169         num = vsi->mac_num;
6170
6171         mac_filter = rte_zmalloc("mac_filter_info_data",
6172                                  num * sizeof(*mac_filter), 0);
6173         if (mac_filter == NULL) {
6174                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6175                 return I40E_ERR_NO_MEMORY;
6176         }
6177
6178         i = 0;
6179
6180         /* Remove all existing mac */
6181         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6182                 mac_filter[i] = f->mac_info;
6183                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6184                 if (ret) {
6185                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6186                                     on ? "enable" : "disable");
6187                         goto DONE;
6188                 }
6189                 i++;
6190         }
6191
6192         /* Override with new filter */
6193         for (i = 0; i < num; i++) {
6194                 mac_filter[i].filter_type = desired_filter;
6195                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6196                 if (ret) {
6197                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6198                                     on ? "enable" : "disable");
6199                         goto DONE;
6200                 }
6201         }
6202
6203 DONE:
6204         rte_free(mac_filter);
6205         return ret;
6206 }
6207
6208 /* Configure vlan stripping on or off */
6209 int
6210 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6211 {
6212         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6213         struct i40e_vsi_context ctxt;
6214         uint8_t vlan_flags;
6215         int ret = I40E_SUCCESS;
6216
6217         /* Check if it has been already on or off */
6218         if (vsi->info.valid_sections &
6219                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6220                 if (on) {
6221                         if ((vsi->info.port_vlan_flags &
6222                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6223                                 return 0; /* already on */
6224                 } else {
6225                         if ((vsi->info.port_vlan_flags &
6226                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6227                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6228                                 return 0; /* already off */
6229                 }
6230         }
6231
6232         if (on)
6233                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6234         else
6235                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6236         vsi->info.valid_sections =
6237                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6238         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6239         vsi->info.port_vlan_flags |= vlan_flags;
6240         ctxt.seid = vsi->seid;
6241         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6242         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6243         if (ret)
6244                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6245                             on ? "enable" : "disable");
6246
6247         return ret;
6248 }
6249
6250 static int
6251 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6252 {
6253         struct rte_eth_dev_data *data = dev->data;
6254         int ret;
6255         int mask = 0;
6256
6257         /* Apply vlan offload setting */
6258         mask = ETH_VLAN_STRIP_MASK |
6259                ETH_QINQ_STRIP_MASK |
6260                ETH_VLAN_FILTER_MASK |
6261                ETH_VLAN_EXTEND_MASK;
6262         ret = i40e_vlan_offload_set(dev, mask);
6263         if (ret) {
6264                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6265                 return ret;
6266         }
6267
6268         /* Apply pvid setting */
6269         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6270                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6271         if (ret)
6272                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6273
6274         return ret;
6275 }
6276
6277 static int
6278 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6279 {
6280         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6281
6282         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6283 }
6284
6285 static int
6286 i40e_update_flow_control(struct i40e_hw *hw)
6287 {
6288 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6289         struct i40e_link_status link_status;
6290         uint32_t rxfc = 0, txfc = 0, reg;
6291         uint8_t an_info;
6292         int ret;
6293
6294         memset(&link_status, 0, sizeof(link_status));
6295         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6296         if (ret != I40E_SUCCESS) {
6297                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6298                 goto write_reg; /* Disable flow control */
6299         }
6300
6301         an_info = hw->phy.link_info.an_info;
6302         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6303                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6304                 ret = I40E_ERR_NOT_READY;
6305                 goto write_reg; /* Disable flow control */
6306         }
6307         /**
6308          * If link auto negotiation is enabled, flow control needs to
6309          * be configured according to it
6310          */
6311         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6312         case I40E_LINK_PAUSE_RXTX:
6313                 rxfc = 1;
6314                 txfc = 1;
6315                 hw->fc.current_mode = I40E_FC_FULL;
6316                 break;
6317         case I40E_AQ_LINK_PAUSE_RX:
6318                 rxfc = 1;
6319                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6320                 break;
6321         case I40E_AQ_LINK_PAUSE_TX:
6322                 txfc = 1;
6323                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6324                 break;
6325         default:
6326                 hw->fc.current_mode = I40E_FC_NONE;
6327                 break;
6328         }
6329
6330 write_reg:
6331         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6332                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6333         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6334         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6335         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6336         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6337
6338         return ret;
6339 }
6340
6341 /* PF setup */
6342 static int
6343 i40e_pf_setup(struct i40e_pf *pf)
6344 {
6345         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6346         struct i40e_filter_control_settings settings;
6347         struct i40e_vsi *vsi;
6348         int ret;
6349
6350         /* Clear all stats counters */
6351         pf->offset_loaded = FALSE;
6352         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6353         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6354         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6355         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6356
6357         ret = i40e_pf_get_switch_config(pf);
6358         if (ret != I40E_SUCCESS) {
6359                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6360                 return ret;
6361         }
6362
6363         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6364         if (ret)
6365                 PMD_INIT_LOG(WARNING,
6366                         "failed to allocate switch domain for device %d", ret);
6367
6368         if (pf->flags & I40E_FLAG_FDIR) {
6369                 /* make queue allocated first, let FDIR use queue pair 0*/
6370                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6371                 if (ret != I40E_FDIR_QUEUE_ID) {
6372                         PMD_DRV_LOG(ERR,
6373                                 "queue allocation fails for FDIR: ret =%d",
6374                                 ret);
6375                         pf->flags &= ~I40E_FLAG_FDIR;
6376                 }
6377         }
6378         /*  main VSI setup */
6379         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6380         if (!vsi) {
6381                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6382                 return I40E_ERR_NOT_READY;
6383         }
6384         pf->main_vsi = vsi;
6385
6386         /* Configure filter control */
6387         memset(&settings, 0, sizeof(settings));
6388         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6389                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6390         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6391                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6392         else {
6393                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6394                         hw->func_caps.rss_table_size);
6395                 return I40E_ERR_PARAM;
6396         }
6397         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6398                 hw->func_caps.rss_table_size);
6399         pf->hash_lut_size = hw->func_caps.rss_table_size;
6400
6401         /* Enable ethtype and macvlan filters */
6402         settings.enable_ethtype = TRUE;
6403         settings.enable_macvlan = TRUE;
6404         ret = i40e_set_filter_control(hw, &settings);
6405         if (ret)
6406                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6407                                                                 ret);
6408
6409         /* Update flow control according to the auto negotiation */
6410         i40e_update_flow_control(hw);
6411
6412         return I40E_SUCCESS;
6413 }
6414
6415 int
6416 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6417 {
6418         uint32_t reg;
6419         uint16_t j;
6420
6421         /**
6422          * Set or clear TX Queue Disable flags,
6423          * which is required by hardware.
6424          */
6425         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6426         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6427
6428         /* Wait until the request is finished */
6429         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6430                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6431                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6432                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6433                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6434                                                         & 0x1))) {
6435                         break;
6436                 }
6437         }
6438         if (on) {
6439                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6440                         return I40E_SUCCESS; /* already on, skip next steps */
6441
6442                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6443                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6444         } else {
6445                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6446                         return I40E_SUCCESS; /* already off, skip next steps */
6447                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6448         }
6449         /* Write the register */
6450         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6451         /* Check the result */
6452         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6453                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6454                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6455                 if (on) {
6456                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6457                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6458                                 break;
6459                 } else {
6460                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6461                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6462                                 break;
6463                 }
6464         }
6465         /* Check if it is timeout */
6466         if (j >= I40E_CHK_Q_ENA_COUNT) {
6467                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6468                             (on ? "enable" : "disable"), q_idx);
6469                 return I40E_ERR_TIMEOUT;
6470         }
6471
6472         return I40E_SUCCESS;
6473 }
6474
6475 int
6476 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6477 {
6478         uint32_t reg;
6479         uint16_t j;
6480
6481         /* Wait until the request is finished */
6482         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6483                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6484                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6485                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6486                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6487                         break;
6488         }
6489
6490         if (on) {
6491                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6492                         return I40E_SUCCESS; /* Already on, skip next steps */
6493                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6494         } else {
6495                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6496                         return I40E_SUCCESS; /* Already off, skip next steps */
6497                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6498         }
6499
6500         /* Write the register */
6501         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6502         /* Check the result */
6503         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6504                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6505                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6506                 if (on) {
6507                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6508                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6509                                 break;
6510                 } else {
6511                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6512                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6513                                 break;
6514                 }
6515         }
6516
6517         /* Check if it is timeout */
6518         if (j >= I40E_CHK_Q_ENA_COUNT) {
6519                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6520                             (on ? "enable" : "disable"), q_idx);
6521                 return I40E_ERR_TIMEOUT;
6522         }
6523
6524         return I40E_SUCCESS;
6525 }
6526
6527 /* Initialize VSI for TX */
6528 static int
6529 i40e_dev_tx_init(struct i40e_pf *pf)
6530 {
6531         struct rte_eth_dev_data *data = pf->dev_data;
6532         uint16_t i;
6533         uint32_t ret = I40E_SUCCESS;
6534         struct i40e_tx_queue *txq;
6535
6536         for (i = 0; i < data->nb_tx_queues; i++) {
6537                 txq = data->tx_queues[i];
6538                 if (!txq || !txq->q_set)
6539                         continue;
6540                 ret = i40e_tx_queue_init(txq);
6541                 if (ret != I40E_SUCCESS)
6542                         break;
6543         }
6544         if (ret == I40E_SUCCESS)
6545                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6546                                      ->eth_dev);
6547
6548         return ret;
6549 }
6550
6551 /* Initialize VSI for RX */
6552 static int
6553 i40e_dev_rx_init(struct i40e_pf *pf)
6554 {
6555         struct rte_eth_dev_data *data = pf->dev_data;
6556         int ret = I40E_SUCCESS;
6557         uint16_t i;
6558         struct i40e_rx_queue *rxq;
6559
6560         i40e_pf_config_rss(pf);
6561         for (i = 0; i < data->nb_rx_queues; i++) {
6562                 rxq = data->rx_queues[i];
6563                 if (!rxq || !rxq->q_set)
6564                         continue;
6565
6566                 ret = i40e_rx_queue_init(rxq);
6567                 if (ret != I40E_SUCCESS) {
6568                         PMD_DRV_LOG(ERR,
6569                                 "Failed to do RX queue initialization");
6570                         break;
6571                 }
6572         }
6573         if (ret == I40E_SUCCESS)
6574                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6575                                      ->eth_dev);
6576
6577         return ret;
6578 }
6579
6580 static int
6581 i40e_dev_rxtx_init(struct i40e_pf *pf)
6582 {
6583         int err;
6584
6585         err = i40e_dev_tx_init(pf);
6586         if (err) {
6587                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6588                 return err;
6589         }
6590         err = i40e_dev_rx_init(pf);
6591         if (err) {
6592                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6593                 return err;
6594         }
6595
6596         return err;
6597 }
6598
6599 static int
6600 i40e_vmdq_setup(struct rte_eth_dev *dev)
6601 {
6602         struct rte_eth_conf *conf = &dev->data->dev_conf;
6603         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6604         int i, err, conf_vsis, j, loop;
6605         struct i40e_vsi *vsi;
6606         struct i40e_vmdq_info *vmdq_info;
6607         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6608         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6609
6610         /*
6611          * Disable interrupt to avoid message from VF. Furthermore, it will
6612          * avoid race condition in VSI creation/destroy.
6613          */
6614         i40e_pf_disable_irq0(hw);
6615
6616         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6617                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6618                 return -ENOTSUP;
6619         }
6620
6621         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6622         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6623                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6624                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6625                         pf->max_nb_vmdq_vsi);
6626                 return -ENOTSUP;
6627         }
6628
6629         if (pf->vmdq != NULL) {
6630                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6631                 return 0;
6632         }
6633
6634         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6635                                 sizeof(*vmdq_info) * conf_vsis, 0);
6636
6637         if (pf->vmdq == NULL) {
6638                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6639                 return -ENOMEM;
6640         }
6641
6642         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6643
6644         /* Create VMDQ VSI */
6645         for (i = 0; i < conf_vsis; i++) {
6646                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6647                                 vmdq_conf->enable_loop_back);
6648                 if (vsi == NULL) {
6649                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6650                         err = -1;
6651                         goto err_vsi_setup;
6652                 }
6653                 vmdq_info = &pf->vmdq[i];
6654                 vmdq_info->pf = pf;
6655                 vmdq_info->vsi = vsi;
6656         }
6657         pf->nb_cfg_vmdq_vsi = conf_vsis;
6658
6659         /* Configure Vlan */
6660         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6661         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6662                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6663                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6664                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6665                                         vmdq_conf->pool_map[i].vlan_id, j);
6666
6667                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6668                                                 vmdq_conf->pool_map[i].vlan_id);
6669                                 if (err) {
6670                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6671                                         err = -1;
6672                                         goto err_vsi_setup;
6673                                 }
6674                         }
6675                 }
6676         }
6677
6678         i40e_pf_enable_irq0(hw);
6679
6680         return 0;
6681
6682 err_vsi_setup:
6683         for (i = 0; i < conf_vsis; i++)
6684                 if (pf->vmdq[i].vsi == NULL)
6685                         break;
6686                 else
6687                         i40e_vsi_release(pf->vmdq[i].vsi);
6688
6689         rte_free(pf->vmdq);
6690         pf->vmdq = NULL;
6691         i40e_pf_enable_irq0(hw);
6692         return err;
6693 }
6694
6695 static void
6696 i40e_stat_update_32(struct i40e_hw *hw,
6697                    uint32_t reg,
6698                    bool offset_loaded,
6699                    uint64_t *offset,
6700                    uint64_t *stat)
6701 {
6702         uint64_t new_data;
6703
6704         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6705         if (!offset_loaded)
6706                 *offset = new_data;
6707
6708         if (new_data >= *offset)
6709                 *stat = (uint64_t)(new_data - *offset);
6710         else
6711                 *stat = (uint64_t)((new_data +
6712                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6713 }
6714
6715 static void
6716 i40e_stat_update_48(struct i40e_hw *hw,
6717                    uint32_t hireg,
6718                    uint32_t loreg,
6719                    bool offset_loaded,
6720                    uint64_t *offset,
6721                    uint64_t *stat)
6722 {
6723         uint64_t new_data;
6724
6725         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6726         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6727                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6728
6729         if (!offset_loaded)
6730                 *offset = new_data;
6731
6732         if (new_data >= *offset)
6733                 *stat = new_data - *offset;
6734         else
6735                 *stat = (uint64_t)((new_data +
6736                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6737
6738         *stat &= I40E_48_BIT_MASK;
6739 }
6740
6741 /* Disable IRQ0 */
6742 void
6743 i40e_pf_disable_irq0(struct i40e_hw *hw)
6744 {
6745         /* Disable all interrupt types */
6746         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6747                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6748         I40E_WRITE_FLUSH(hw);
6749 }
6750
6751 /* Enable IRQ0 */
6752 void
6753 i40e_pf_enable_irq0(struct i40e_hw *hw)
6754 {
6755         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6756                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6757                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6758                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6759         I40E_WRITE_FLUSH(hw);
6760 }
6761
6762 static void
6763 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6764 {
6765         /* read pending request and disable first */
6766         i40e_pf_disable_irq0(hw);
6767         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6768         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6769                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6770
6771         if (no_queue)
6772                 /* Link no queues with irq0 */
6773                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6774                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6775 }
6776
6777 static void
6778 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6779 {
6780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6781         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6782         int i;
6783         uint16_t abs_vf_id;
6784         uint32_t index, offset, val;
6785
6786         if (!pf->vfs)
6787                 return;
6788         /**
6789          * Try to find which VF trigger a reset, use absolute VF id to access
6790          * since the reg is global register.
6791          */
6792         for (i = 0; i < pf->vf_num; i++) {
6793                 abs_vf_id = hw->func_caps.vf_base_id + i;
6794                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6795                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6796                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6797                 /* VFR event occurred */
6798                 if (val & (0x1 << offset)) {
6799                         int ret;
6800
6801                         /* Clear the event first */
6802                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6803                                                         (0x1 << offset));
6804                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6805                         /**
6806                          * Only notify a VF reset event occurred,
6807                          * don't trigger another SW reset
6808                          */
6809                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6810                         if (ret != I40E_SUCCESS)
6811                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6812                 }
6813         }
6814 }
6815
6816 static void
6817 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6818 {
6819         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6820         int i;
6821
6822         for (i = 0; i < pf->vf_num; i++)
6823                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6824 }
6825
6826 static void
6827 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6828 {
6829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6830         struct i40e_arq_event_info info;
6831         uint16_t pending, opcode;
6832         int ret;
6833
6834         info.buf_len = I40E_AQ_BUF_SZ;
6835         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6836         if (!info.msg_buf) {
6837                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6838                 return;
6839         }
6840
6841         pending = 1;
6842         while (pending) {
6843                 ret = i40e_clean_arq_element(hw, &info, &pending);
6844
6845                 if (ret != I40E_SUCCESS) {
6846                         PMD_DRV_LOG(INFO,
6847                                 "Failed to read msg from AdminQ, aq_err: %u",
6848                                 hw->aq.asq_last_status);
6849                         break;
6850                 }
6851                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6852
6853                 switch (opcode) {
6854                 case i40e_aqc_opc_send_msg_to_pf:
6855                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6856                         i40e_pf_host_handle_vf_msg(dev,
6857                                         rte_le_to_cpu_16(info.desc.retval),
6858                                         rte_le_to_cpu_32(info.desc.cookie_high),
6859                                         rte_le_to_cpu_32(info.desc.cookie_low),
6860                                         info.msg_buf,
6861                                         info.msg_len);
6862                         break;
6863                 case i40e_aqc_opc_get_link_status:
6864                         ret = i40e_dev_link_update(dev, 0);
6865                         if (!ret)
6866                                 rte_eth_dev_callback_process(dev,
6867                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6868                         break;
6869                 default:
6870                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6871                                     opcode);
6872                         break;
6873                 }
6874         }
6875         rte_free(info.msg_buf);
6876 }
6877
6878 static void
6879 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6880 {
6881 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6882 #define I40E_MDD_CLEAR16 0xFFFF
6883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6885         bool mdd_detected = false;
6886         struct i40e_pf_vf *vf;
6887         uint32_t reg;
6888         int i;
6889
6890         /* find what triggered the MDD event */
6891         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6892         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6893                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6894                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6895                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6896                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6897                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6898                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6899                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6900                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6901                                         hw->func_caps.base_queue;
6902                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6903                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6904                                 event, queue, pf_num, vf_num, dev->data->name);
6905                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6906                 mdd_detected = true;
6907         }
6908         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6909         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6910                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6911                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6912                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6913                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6914                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6915                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6916                                         hw->func_caps.base_queue;
6917
6918                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6919                                 "queue %d of function 0x%02x device %s\n",
6920                                         event, queue, func, dev->data->name);
6921                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6922                 mdd_detected = true;
6923         }
6924
6925         if (mdd_detected) {
6926                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6927                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6928                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6929                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6930                 }
6931                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6932                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6933                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6934                                         I40E_MDD_CLEAR16);
6935                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6936                 }
6937         }
6938
6939         /* see if one of the VFs needs its hand slapped */
6940         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6941                 vf = &pf->vfs[i];
6942                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6943                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6944                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6945                                         I40E_MDD_CLEAR16);
6946                         vf->num_mdd_events++;
6947                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6948                                         PRIu64 "times\n",
6949                                         i, vf->num_mdd_events);
6950                 }
6951
6952                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6953                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6954                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6955                                         I40E_MDD_CLEAR16);
6956                         vf->num_mdd_events++;
6957                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6958                                         PRIu64 "times\n",
6959                                         i, vf->num_mdd_events);
6960                 }
6961         }
6962 }
6963
6964 /**
6965  * Interrupt handler triggered by NIC  for handling
6966  * specific interrupt.
6967  *
6968  * @param handle
6969  *  Pointer to interrupt handle.
6970  * @param param
6971  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6972  *
6973  * @return
6974  *  void
6975  */
6976 static void
6977 i40e_dev_interrupt_handler(void *param)
6978 {
6979         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6980         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981         uint32_t icr0;
6982
6983         /* Disable interrupt */
6984         i40e_pf_disable_irq0(hw);
6985
6986         /* read out interrupt causes */
6987         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6988
6989         /* No interrupt event indicated */
6990         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6991                 PMD_DRV_LOG(INFO, "No interrupt event");
6992                 goto done;
6993         }
6994         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6995                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6996         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6997                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6998                 i40e_handle_mdd_event(dev);
6999         }
7000         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7001                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7002         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7003                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7004         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7005                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7006         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7007                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7008         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7009                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7010
7011         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7012                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7013                 i40e_dev_handle_vfr_event(dev);
7014         }
7015         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7016                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7017                 i40e_dev_handle_aq_msg(dev);
7018         }
7019
7020 done:
7021         /* Enable interrupt */
7022         i40e_pf_enable_irq0(hw);
7023 }
7024
7025 static void
7026 i40e_dev_alarm_handler(void *param)
7027 {
7028         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7030         uint32_t icr0;
7031
7032         /* Disable interrupt */
7033         i40e_pf_disable_irq0(hw);
7034
7035         /* read out interrupt causes */
7036         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
7037
7038         /* No interrupt event indicated */
7039         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
7040                 goto done;
7041         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
7042                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
7043         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
7044                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
7045                 i40e_handle_mdd_event(dev);
7046         }
7047         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7048                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7049         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7050                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7051         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7052                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7053         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7054                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7055         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7056                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7057
7058         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7059                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7060                 i40e_dev_handle_vfr_event(dev);
7061         }
7062         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7063                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7064                 i40e_dev_handle_aq_msg(dev);
7065         }
7066
7067 done:
7068         /* Enable interrupt */
7069         i40e_pf_enable_irq0(hw);
7070         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7071                           i40e_dev_alarm_handler, dev);
7072 }
7073
7074 int
7075 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7076                          struct i40e_macvlan_filter *filter,
7077                          int total)
7078 {
7079         int ele_num, ele_buff_size;
7080         int num, actual_num, i;
7081         uint16_t flags;
7082         int ret = I40E_SUCCESS;
7083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7084         struct i40e_aqc_add_macvlan_element_data *req_list;
7085
7086         if (filter == NULL  || total == 0)
7087                 return I40E_ERR_PARAM;
7088         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7089         ele_buff_size = hw->aq.asq_buf_size;
7090
7091         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7092         if (req_list == NULL) {
7093                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7094                 return I40E_ERR_NO_MEMORY;
7095         }
7096
7097         num = 0;
7098         do {
7099                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7100                 memset(req_list, 0, ele_buff_size);
7101
7102                 for (i = 0; i < actual_num; i++) {
7103                         rte_memcpy(req_list[i].mac_addr,
7104                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7105                         req_list[i].vlan_tag =
7106                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7107
7108                         switch (filter[num + i].filter_type) {
7109                         case RTE_MAC_PERFECT_MATCH:
7110                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7111                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7112                                 break;
7113                         case RTE_MACVLAN_PERFECT_MATCH:
7114                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7115                                 break;
7116                         case RTE_MAC_HASH_MATCH:
7117                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7118                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7119                                 break;
7120                         case RTE_MACVLAN_HASH_MATCH:
7121                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7122                                 break;
7123                         default:
7124                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7125                                 ret = I40E_ERR_PARAM;
7126                                 goto DONE;
7127                         }
7128
7129                         req_list[i].queue_number = 0;
7130
7131                         req_list[i].flags = rte_cpu_to_le_16(flags);
7132                 }
7133
7134                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7135                                                 actual_num, NULL);
7136                 if (ret != I40E_SUCCESS) {
7137                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7138                         goto DONE;
7139                 }
7140                 num += actual_num;
7141         } while (num < total);
7142
7143 DONE:
7144         rte_free(req_list);
7145         return ret;
7146 }
7147
7148 int
7149 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7150                             struct i40e_macvlan_filter *filter,
7151                             int total)
7152 {
7153         int ele_num, ele_buff_size;
7154         int num, actual_num, i;
7155         uint16_t flags;
7156         int ret = I40E_SUCCESS;
7157         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7158         struct i40e_aqc_remove_macvlan_element_data *req_list;
7159
7160         if (filter == NULL  || total == 0)
7161                 return I40E_ERR_PARAM;
7162
7163         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7164         ele_buff_size = hw->aq.asq_buf_size;
7165
7166         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7167         if (req_list == NULL) {
7168                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7169                 return I40E_ERR_NO_MEMORY;
7170         }
7171
7172         num = 0;
7173         do {
7174                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7175                 memset(req_list, 0, ele_buff_size);
7176
7177                 for (i = 0; i < actual_num; i++) {
7178                         rte_memcpy(req_list[i].mac_addr,
7179                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7180                         req_list[i].vlan_tag =
7181                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7182
7183                         switch (filter[num + i].filter_type) {
7184                         case RTE_MAC_PERFECT_MATCH:
7185                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7186                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7187                                 break;
7188                         case RTE_MACVLAN_PERFECT_MATCH:
7189                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7190                                 break;
7191                         case RTE_MAC_HASH_MATCH:
7192                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7193                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7194                                 break;
7195                         case RTE_MACVLAN_HASH_MATCH:
7196                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7197                                 break;
7198                         default:
7199                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7200                                 ret = I40E_ERR_PARAM;
7201                                 goto DONE;
7202                         }
7203                         req_list[i].flags = rte_cpu_to_le_16(flags);
7204                 }
7205
7206                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7207                                                 actual_num, NULL);
7208                 if (ret != I40E_SUCCESS) {
7209                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7210                         goto DONE;
7211                 }
7212                 num += actual_num;
7213         } while (num < total);
7214
7215 DONE:
7216         rte_free(req_list);
7217         return ret;
7218 }
7219
7220 /* Find out specific MAC filter */
7221 static struct i40e_mac_filter *
7222 i40e_find_mac_filter(struct i40e_vsi *vsi,
7223                          struct rte_ether_addr *macaddr)
7224 {
7225         struct i40e_mac_filter *f;
7226
7227         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7228                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7229                         return f;
7230         }
7231
7232         return NULL;
7233 }
7234
7235 static bool
7236 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7237                          uint16_t vlan_id)
7238 {
7239         uint32_t vid_idx, vid_bit;
7240
7241         if (vlan_id > ETH_VLAN_ID_MAX)
7242                 return 0;
7243
7244         vid_idx = I40E_VFTA_IDX(vlan_id);
7245         vid_bit = I40E_VFTA_BIT(vlan_id);
7246
7247         if (vsi->vfta[vid_idx] & vid_bit)
7248                 return 1;
7249         else
7250                 return 0;
7251 }
7252
7253 static void
7254 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7255                        uint16_t vlan_id, bool on)
7256 {
7257         uint32_t vid_idx, vid_bit;
7258
7259         vid_idx = I40E_VFTA_IDX(vlan_id);
7260         vid_bit = I40E_VFTA_BIT(vlan_id);
7261
7262         if (on)
7263                 vsi->vfta[vid_idx] |= vid_bit;
7264         else
7265                 vsi->vfta[vid_idx] &= ~vid_bit;
7266 }
7267
7268 void
7269 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7270                      uint16_t vlan_id, bool on)
7271 {
7272         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7273         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7274         int ret;
7275
7276         if (vlan_id > ETH_VLAN_ID_MAX)
7277                 return;
7278
7279         i40e_store_vlan_filter(vsi, vlan_id, on);
7280
7281         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7282                 return;
7283
7284         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7285
7286         if (on) {
7287                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7288                                        &vlan_data, 1, NULL);
7289                 if (ret != I40E_SUCCESS)
7290                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7291         } else {
7292                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7293                                           &vlan_data, 1, NULL);
7294                 if (ret != I40E_SUCCESS)
7295                         PMD_DRV_LOG(ERR,
7296                                     "Failed to remove vlan filter");
7297         }
7298 }
7299
7300 /**
7301  * Find all vlan options for specific mac addr,
7302  * return with actual vlan found.
7303  */
7304 int
7305 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7306                            struct i40e_macvlan_filter *mv_f,
7307                            int num, struct rte_ether_addr *addr)
7308 {
7309         int i;
7310         uint32_t j, k;
7311
7312         /**
7313          * Not to use i40e_find_vlan_filter to decrease the loop time,
7314          * although the code looks complex.
7315           */
7316         if (num < vsi->vlan_num)
7317                 return I40E_ERR_PARAM;
7318
7319         i = 0;
7320         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7321                 if (vsi->vfta[j]) {
7322                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7323                                 if (vsi->vfta[j] & (1 << k)) {
7324                                         if (i > num - 1) {
7325                                                 PMD_DRV_LOG(ERR,
7326                                                         "vlan number doesn't match");
7327                                                 return I40E_ERR_PARAM;
7328                                         }
7329                                         rte_memcpy(&mv_f[i].macaddr,
7330                                                         addr, ETH_ADDR_LEN);
7331                                         mv_f[i].vlan_id =
7332                                                 j * I40E_UINT32_BIT_SIZE + k;
7333                                         i++;
7334                                 }
7335                         }
7336                 }
7337         }
7338         return I40E_SUCCESS;
7339 }
7340
7341 static inline int
7342 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7343                            struct i40e_macvlan_filter *mv_f,
7344                            int num,
7345                            uint16_t vlan)
7346 {
7347         int i = 0;
7348         struct i40e_mac_filter *f;
7349
7350         if (num < vsi->mac_num)
7351                 return I40E_ERR_PARAM;
7352
7353         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7354                 if (i > num - 1) {
7355                         PMD_DRV_LOG(ERR, "buffer number not match");
7356                         return I40E_ERR_PARAM;
7357                 }
7358                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7359                                 ETH_ADDR_LEN);
7360                 mv_f[i].vlan_id = vlan;
7361                 mv_f[i].filter_type = f->mac_info.filter_type;
7362                 i++;
7363         }
7364
7365         return I40E_SUCCESS;
7366 }
7367
7368 static int
7369 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7370 {
7371         int i, j, num;
7372         struct i40e_mac_filter *f;
7373         struct i40e_macvlan_filter *mv_f;
7374         int ret = I40E_SUCCESS;
7375
7376         if (vsi == NULL || vsi->mac_num == 0)
7377                 return I40E_ERR_PARAM;
7378
7379         /* Case that no vlan is set */
7380         if (vsi->vlan_num == 0)
7381                 num = vsi->mac_num;
7382         else
7383                 num = vsi->mac_num * vsi->vlan_num;
7384
7385         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7386         if (mv_f == NULL) {
7387                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7388                 return I40E_ERR_NO_MEMORY;
7389         }
7390
7391         i = 0;
7392         if (vsi->vlan_num == 0) {
7393                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7394                         rte_memcpy(&mv_f[i].macaddr,
7395                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7396                         mv_f[i].filter_type = f->mac_info.filter_type;
7397                         mv_f[i].vlan_id = 0;
7398                         i++;
7399                 }
7400         } else {
7401                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7402                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7403                                         vsi->vlan_num, &f->mac_info.mac_addr);
7404                         if (ret != I40E_SUCCESS)
7405                                 goto DONE;
7406                         for (j = i; j < i + vsi->vlan_num; j++)
7407                                 mv_f[j].filter_type = f->mac_info.filter_type;
7408                         i += vsi->vlan_num;
7409                 }
7410         }
7411
7412         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7413 DONE:
7414         rte_free(mv_f);
7415
7416         return ret;
7417 }
7418
7419 int
7420 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7421 {
7422         struct i40e_macvlan_filter *mv_f;
7423         int mac_num;
7424         int ret = I40E_SUCCESS;
7425
7426         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7427                 return I40E_ERR_PARAM;
7428
7429         /* If it's already set, just return */
7430         if (i40e_find_vlan_filter(vsi,vlan))
7431                 return I40E_SUCCESS;
7432
7433         mac_num = vsi->mac_num;
7434
7435         if (mac_num == 0) {
7436                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7437                 return I40E_ERR_PARAM;
7438         }
7439
7440         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7441
7442         if (mv_f == NULL) {
7443                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7444                 return I40E_ERR_NO_MEMORY;
7445         }
7446
7447         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7448
7449         if (ret != I40E_SUCCESS)
7450                 goto DONE;
7451
7452         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7453
7454         if (ret != I40E_SUCCESS)
7455                 goto DONE;
7456
7457         i40e_set_vlan_filter(vsi, vlan, 1);
7458
7459         vsi->vlan_num++;
7460         ret = I40E_SUCCESS;
7461 DONE:
7462         rte_free(mv_f);
7463         return ret;
7464 }
7465
7466 int
7467 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7468 {
7469         struct i40e_macvlan_filter *mv_f;
7470         int mac_num;
7471         int ret = I40E_SUCCESS;
7472
7473         /**
7474          * Vlan 0 is the generic filter for untagged packets
7475          * and can't be removed.
7476          */
7477         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7478                 return I40E_ERR_PARAM;
7479
7480         /* If can't find it, just return */
7481         if (!i40e_find_vlan_filter(vsi, vlan))
7482                 return I40E_ERR_PARAM;
7483
7484         mac_num = vsi->mac_num;
7485
7486         if (mac_num == 0) {
7487                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7488                 return I40E_ERR_PARAM;
7489         }
7490
7491         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7492
7493         if (mv_f == NULL) {
7494                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7495                 return I40E_ERR_NO_MEMORY;
7496         }
7497
7498         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7499
7500         if (ret != I40E_SUCCESS)
7501                 goto DONE;
7502
7503         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7504
7505         if (ret != I40E_SUCCESS)
7506                 goto DONE;
7507
7508         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7509         if (vsi->vlan_num == 1) {
7510                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7511                 if (ret != I40E_SUCCESS)
7512                         goto DONE;
7513
7514                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7515                 if (ret != I40E_SUCCESS)
7516                         goto DONE;
7517         }
7518
7519         i40e_set_vlan_filter(vsi, vlan, 0);
7520
7521         vsi->vlan_num--;
7522         ret = I40E_SUCCESS;
7523 DONE:
7524         rte_free(mv_f);
7525         return ret;
7526 }
7527
7528 int
7529 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7530 {
7531         struct i40e_mac_filter *f;
7532         struct i40e_macvlan_filter *mv_f;
7533         int i, vlan_num = 0;
7534         int ret = I40E_SUCCESS;
7535
7536         /* If it's add and we've config it, return */
7537         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7538         if (f != NULL)
7539                 return I40E_SUCCESS;
7540         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7541                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7542
7543                 /**
7544                  * If vlan_num is 0, that's the first time to add mac,
7545                  * set mask for vlan_id 0.
7546                  */
7547                 if (vsi->vlan_num == 0) {
7548                         i40e_set_vlan_filter(vsi, 0, 1);
7549                         vsi->vlan_num = 1;
7550                 }
7551                 vlan_num = vsi->vlan_num;
7552         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7553                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7554                 vlan_num = 1;
7555
7556         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7557         if (mv_f == NULL) {
7558                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7559                 return I40E_ERR_NO_MEMORY;
7560         }
7561
7562         for (i = 0; i < vlan_num; i++) {
7563                 mv_f[i].filter_type = mac_filter->filter_type;
7564                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7565                                 ETH_ADDR_LEN);
7566         }
7567
7568         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7569                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7570                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7571                                         &mac_filter->mac_addr);
7572                 if (ret != I40E_SUCCESS)
7573                         goto DONE;
7574         }
7575
7576         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7577         if (ret != I40E_SUCCESS)
7578                 goto DONE;
7579
7580         /* Add the mac addr into mac list */
7581         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7582         if (f == NULL) {
7583                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7584                 ret = I40E_ERR_NO_MEMORY;
7585                 goto DONE;
7586         }
7587         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7588                         ETH_ADDR_LEN);
7589         f->mac_info.filter_type = mac_filter->filter_type;
7590         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7591         vsi->mac_num++;
7592
7593         ret = I40E_SUCCESS;
7594 DONE:
7595         rte_free(mv_f);
7596
7597         return ret;
7598 }
7599
7600 int
7601 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7602 {
7603         struct i40e_mac_filter *f;
7604         struct i40e_macvlan_filter *mv_f;
7605         int i, vlan_num;
7606         enum rte_mac_filter_type filter_type;
7607         int ret = I40E_SUCCESS;
7608
7609         /* Can't find it, return an error */
7610         f = i40e_find_mac_filter(vsi, addr);
7611         if (f == NULL)
7612                 return I40E_ERR_PARAM;
7613
7614         vlan_num = vsi->vlan_num;
7615         filter_type = f->mac_info.filter_type;
7616         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7617                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7618                 if (vlan_num == 0) {
7619                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7620                         return I40E_ERR_PARAM;
7621                 }
7622         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7623                         filter_type == RTE_MAC_HASH_MATCH)
7624                 vlan_num = 1;
7625
7626         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7627         if (mv_f == NULL) {
7628                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7629                 return I40E_ERR_NO_MEMORY;
7630         }
7631
7632         for (i = 0; i < vlan_num; i++) {
7633                 mv_f[i].filter_type = filter_type;
7634                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7635                                 ETH_ADDR_LEN);
7636         }
7637         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7638                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7639                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7640                 if (ret != I40E_SUCCESS)
7641                         goto DONE;
7642         }
7643
7644         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7645         if (ret != I40E_SUCCESS)
7646                 goto DONE;
7647
7648         /* Remove the mac addr into mac list */
7649         TAILQ_REMOVE(&vsi->mac_list, f, next);
7650         rte_free(f);
7651         vsi->mac_num--;
7652
7653         ret = I40E_SUCCESS;
7654 DONE:
7655         rte_free(mv_f);
7656         return ret;
7657 }
7658
7659 /* Configure hash enable flags for RSS */
7660 uint64_t
7661 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7662 {
7663         uint64_t hena = 0;
7664         int i;
7665
7666         if (!flags)
7667                 return hena;
7668
7669         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7670                 if (flags & (1ULL << i))
7671                         hena |= adapter->pctypes_tbl[i];
7672         }
7673
7674         return hena;
7675 }
7676
7677 /* Parse the hash enable flags */
7678 uint64_t
7679 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7680 {
7681         uint64_t rss_hf = 0;
7682
7683         if (!flags)
7684                 return rss_hf;
7685         int i;
7686
7687         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7688                 if (flags & adapter->pctypes_tbl[i])
7689                         rss_hf |= (1ULL << i);
7690         }
7691         return rss_hf;
7692 }
7693
7694 /* Disable RSS */
7695 static void
7696 i40e_pf_disable_rss(struct i40e_pf *pf)
7697 {
7698         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7699
7700         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7701         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7702         I40E_WRITE_FLUSH(hw);
7703 }
7704
7705 int
7706 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7707 {
7708         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7709         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7710         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7711                            I40E_VFQF_HKEY_MAX_INDEX :
7712                            I40E_PFQF_HKEY_MAX_INDEX;
7713         int ret = 0;
7714
7715         if (!key || key_len == 0) {
7716                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7717                 return 0;
7718         } else if (key_len != (key_idx + 1) *
7719                 sizeof(uint32_t)) {
7720                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7721                 return -EINVAL;
7722         }
7723
7724         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7725                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7726                         (struct i40e_aqc_get_set_rss_key_data *)key;
7727
7728                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7729                 if (ret)
7730                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7731         } else {
7732                 uint32_t *hash_key = (uint32_t *)key;
7733                 uint16_t i;
7734
7735                 if (vsi->type == I40E_VSI_SRIOV) {
7736                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7737                                 I40E_WRITE_REG(
7738                                         hw,
7739                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7740                                         hash_key[i]);
7741
7742                 } else {
7743                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7744                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7745                                                hash_key[i]);
7746                 }
7747                 I40E_WRITE_FLUSH(hw);
7748         }
7749
7750         return ret;
7751 }
7752
7753 static int
7754 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7755 {
7756         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7757         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7758         uint32_t reg;
7759         int ret;
7760
7761         if (!key || !key_len)
7762                 return 0;
7763
7764         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7765                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7766                         (struct i40e_aqc_get_set_rss_key_data *)key);
7767                 if (ret) {
7768                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7769                         return ret;
7770                 }
7771         } else {
7772                 uint32_t *key_dw = (uint32_t *)key;
7773                 uint16_t i;
7774
7775                 if (vsi->type == I40E_VSI_SRIOV) {
7776                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7777                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7778                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7779                         }
7780                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7781                                    sizeof(uint32_t);
7782                 } else {
7783                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7784                                 reg = I40E_PFQF_HKEY(i);
7785                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7786                         }
7787                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7788                                    sizeof(uint32_t);
7789                 }
7790         }
7791         return 0;
7792 }
7793
7794 static int
7795 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7796 {
7797         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7798         uint64_t hena;
7799         int ret;
7800
7801         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7802                                rss_conf->rss_key_len);
7803         if (ret)
7804                 return ret;
7805
7806         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7807         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7808         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7809         I40E_WRITE_FLUSH(hw);
7810
7811         return 0;
7812 }
7813
7814 static int
7815 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7816                          struct rte_eth_rss_conf *rss_conf)
7817 {
7818         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7820         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7821         uint64_t hena;
7822
7823         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7824         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7825
7826         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7827                 if (rss_hf != 0) /* Enable RSS */
7828                         return -EINVAL;
7829                 return 0; /* Nothing to do */
7830         }
7831         /* RSS enabled */
7832         if (rss_hf == 0) /* Disable RSS */
7833                 return -EINVAL;
7834
7835         return i40e_hw_rss_hash_set(pf, rss_conf);
7836 }
7837
7838 static int
7839 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7840                            struct rte_eth_rss_conf *rss_conf)
7841 {
7842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7844         uint64_t hena;
7845         int ret;
7846
7847         if (!rss_conf)
7848                 return -EINVAL;
7849
7850         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7851                          &rss_conf->rss_key_len);
7852         if (ret)
7853                 return ret;
7854
7855         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7856         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7857         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7858
7859         return 0;
7860 }
7861
7862 static int
7863 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7864 {
7865         switch (filter_type) {
7866         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7867                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7868                 break;
7869         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7870                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7871                 break;
7872         case RTE_TUNNEL_FILTER_IMAC_TENID:
7873                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7874                 break;
7875         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7876                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7877                 break;
7878         case ETH_TUNNEL_FILTER_IMAC:
7879                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7880                 break;
7881         case ETH_TUNNEL_FILTER_OIP:
7882                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7883                 break;
7884         case ETH_TUNNEL_FILTER_IIP:
7885                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7886                 break;
7887         default:
7888                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7889                 return -EINVAL;
7890         }
7891
7892         return 0;
7893 }
7894
7895 /* Convert tunnel filter structure */
7896 static int
7897 i40e_tunnel_filter_convert(
7898         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7899         struct i40e_tunnel_filter *tunnel_filter)
7900 {
7901         rte_ether_addr_copy((struct rte_ether_addr *)
7902                         &cld_filter->element.outer_mac,
7903                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7904         rte_ether_addr_copy((struct rte_ether_addr *)
7905                         &cld_filter->element.inner_mac,
7906                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7907         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7908         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7909              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7910             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7911                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7912         else
7913                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7914         tunnel_filter->input.flags = cld_filter->element.flags;
7915         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7916         tunnel_filter->queue = cld_filter->element.queue_number;
7917         rte_memcpy(tunnel_filter->input.general_fields,
7918                    cld_filter->general_fields,
7919                    sizeof(cld_filter->general_fields));
7920
7921         return 0;
7922 }
7923
7924 /* Check if there exists the tunnel filter */
7925 struct i40e_tunnel_filter *
7926 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7927                              const struct i40e_tunnel_filter_input *input)
7928 {
7929         int ret;
7930
7931         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7932         if (ret < 0)
7933                 return NULL;
7934
7935         return tunnel_rule->hash_map[ret];
7936 }
7937
7938 /* Add a tunnel filter into the SW list */
7939 static int
7940 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7941                              struct i40e_tunnel_filter *tunnel_filter)
7942 {
7943         struct i40e_tunnel_rule *rule = &pf->tunnel;
7944         int ret;
7945
7946         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7947         if (ret < 0) {
7948                 PMD_DRV_LOG(ERR,
7949                             "Failed to insert tunnel filter to hash table %d!",
7950                             ret);
7951                 return ret;
7952         }
7953         rule->hash_map[ret] = tunnel_filter;
7954
7955         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7956
7957         return 0;
7958 }
7959
7960 /* Delete a tunnel filter from the SW list */
7961 int
7962 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7963                           struct i40e_tunnel_filter_input *input)
7964 {
7965         struct i40e_tunnel_rule *rule = &pf->tunnel;
7966         struct i40e_tunnel_filter *tunnel_filter;
7967         int ret;
7968
7969         ret = rte_hash_del_key(rule->hash_table, input);
7970         if (ret < 0) {
7971                 PMD_DRV_LOG(ERR,
7972                             "Failed to delete tunnel filter to hash table %d!",
7973                             ret);
7974                 return ret;
7975         }
7976         tunnel_filter = rule->hash_map[ret];
7977         rule->hash_map[ret] = NULL;
7978
7979         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7980         rte_free(tunnel_filter);
7981
7982         return 0;
7983 }
7984
7985 int
7986 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7987                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7988                         uint8_t add)
7989 {
7990         uint16_t ip_type;
7991         uint32_t ipv4_addr, ipv4_addr_le;
7992         uint8_t i, tun_type = 0;
7993         /* internal varialbe to convert ipv6 byte order */
7994         uint32_t convert_ipv6[4];
7995         int val, ret = 0;
7996         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7997         struct i40e_vsi *vsi = pf->main_vsi;
7998         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7999         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8000         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8001         struct i40e_tunnel_filter *tunnel, *node;
8002         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8003
8004         cld_filter = rte_zmalloc("tunnel_filter",
8005                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8006         0);
8007
8008         if (NULL == cld_filter) {
8009                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8010                 return -ENOMEM;
8011         }
8012         pfilter = cld_filter;
8013
8014         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8015                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8016         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8017                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8018
8019         pfilter->element.inner_vlan =
8020                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8021         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
8022                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8023                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8024                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8025                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8026                                 &ipv4_addr_le,
8027                                 sizeof(pfilter->element.ipaddr.v4.data));
8028         } else {
8029                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8030                 for (i = 0; i < 4; i++) {
8031                         convert_ipv6[i] =
8032                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
8033                 }
8034                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8035                            &convert_ipv6,
8036                            sizeof(pfilter->element.ipaddr.v6.data));
8037         }
8038
8039         /* check tunneled type */
8040         switch (tunnel_filter->tunnel_type) {
8041         case RTE_TUNNEL_TYPE_VXLAN:
8042                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8043                 break;
8044         case RTE_TUNNEL_TYPE_NVGRE:
8045                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8046                 break;
8047         case RTE_TUNNEL_TYPE_IP_IN_GRE:
8048                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8049                 break;
8050         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8051                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
8052                 break;
8053         default:
8054                 /* Other tunnel types is not supported. */
8055                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8056                 rte_free(cld_filter);
8057                 return -EINVAL;
8058         }
8059
8060         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8061                                        &pfilter->element.flags);
8062         if (val < 0) {
8063                 rte_free(cld_filter);
8064                 return -EINVAL;
8065         }
8066
8067         pfilter->element.flags |= rte_cpu_to_le_16(
8068                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8069                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8070         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8071         pfilter->element.queue_number =
8072                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8073
8074         /* Check if there is the filter in SW list */
8075         memset(&check_filter, 0, sizeof(check_filter));
8076         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8077         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8078         if (add && node) {
8079                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8080                 rte_free(cld_filter);
8081                 return -EINVAL;
8082         }
8083
8084         if (!add && !node) {
8085                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8086                 rte_free(cld_filter);
8087                 return -EINVAL;
8088         }
8089
8090         if (add) {
8091                 ret = i40e_aq_add_cloud_filters(hw,
8092                                         vsi->seid, &cld_filter->element, 1);
8093                 if (ret < 0) {
8094                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8095                         rte_free(cld_filter);
8096                         return -ENOTSUP;
8097                 }
8098                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8099                 if (tunnel == NULL) {
8100                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8101                         rte_free(cld_filter);
8102                         return -ENOMEM;
8103                 }
8104
8105                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8106                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8107                 if (ret < 0)
8108                         rte_free(tunnel);
8109         } else {
8110                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8111                                                    &cld_filter->element, 1);
8112                 if (ret < 0) {
8113                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8114                         rte_free(cld_filter);
8115                         return -ENOTSUP;
8116                 }
8117                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8118         }
8119
8120         rte_free(cld_filter);
8121         return ret;
8122 }
8123
8124 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8125 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
8126 #define I40E_TR_GENEVE_KEY_MASK                 0x8
8127 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
8128 #define I40E_TR_GRE_KEY_MASK                    0x400
8129 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
8130 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
8131 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8132 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8133 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8134 #define I40E_DIRECTION_INGRESS_KEY              0x8000
8135 #define I40E_TR_L4_TYPE_TCP                     0x2
8136 #define I40E_TR_L4_TYPE_UDP                     0x4
8137 #define I40E_TR_L4_TYPE_SCTP                    0x8
8138
8139 static enum
8140 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8141 {
8142         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8143         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8144         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8145         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8146         enum i40e_status_code status = I40E_SUCCESS;
8147
8148         if (pf->support_multi_driver) {
8149                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8150                 return I40E_NOT_SUPPORTED;
8151         }
8152
8153         memset(&filter_replace, 0,
8154                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8155         memset(&filter_replace_buf, 0,
8156                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8157
8158         /* create L1 filter */
8159         filter_replace.old_filter_type =
8160                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8161         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8162         filter_replace.tr_bit = 0;
8163
8164         /* Prepare the buffer, 3 entries */
8165         filter_replace_buf.data[0] =
8166                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8167         filter_replace_buf.data[0] |=
8168                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8169         filter_replace_buf.data[2] = 0xFF;
8170         filter_replace_buf.data[3] = 0xFF;
8171         filter_replace_buf.data[4] =
8172                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8173         filter_replace_buf.data[4] |=
8174                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8175         filter_replace_buf.data[7] = 0xF0;
8176         filter_replace_buf.data[8]
8177                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8178         filter_replace_buf.data[8] |=
8179                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8180         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8181                 I40E_TR_GENEVE_KEY_MASK |
8182                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8183         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8184                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8185                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8186
8187         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8188                                                &filter_replace_buf);
8189         if (!status && (filter_replace.old_filter_type !=
8190                         filter_replace.new_filter_type))
8191                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8192                             " original: 0x%x, new: 0x%x",
8193                             dev->device->name,
8194                             filter_replace.old_filter_type,
8195                             filter_replace.new_filter_type);
8196
8197         return status;
8198 }
8199
8200 static enum
8201 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8202 {
8203         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8204         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8205         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8206         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8207         enum i40e_status_code status = I40E_SUCCESS;
8208
8209         if (pf->support_multi_driver) {
8210                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8211                 return I40E_NOT_SUPPORTED;
8212         }
8213
8214         /* For MPLSoUDP */
8215         memset(&filter_replace, 0,
8216                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8217         memset(&filter_replace_buf, 0,
8218                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8219         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8220                 I40E_AQC_MIRROR_CLOUD_FILTER;
8221         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8222         filter_replace.new_filter_type =
8223                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8224         /* Prepare the buffer, 2 entries */
8225         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8226         filter_replace_buf.data[0] |=
8227                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8228         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8229         filter_replace_buf.data[4] |=
8230                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8231         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8232                                                &filter_replace_buf);
8233         if (status < 0)
8234                 return status;
8235         if (filter_replace.old_filter_type !=
8236             filter_replace.new_filter_type)
8237                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8238                             " original: 0x%x, new: 0x%x",
8239                             dev->device->name,
8240                             filter_replace.old_filter_type,
8241                             filter_replace.new_filter_type);
8242
8243         /* For MPLSoGRE */
8244         memset(&filter_replace, 0,
8245                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8246         memset(&filter_replace_buf, 0,
8247                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8248
8249         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8250                 I40E_AQC_MIRROR_CLOUD_FILTER;
8251         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8252         filter_replace.new_filter_type =
8253                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8254         /* Prepare the buffer, 2 entries */
8255         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8256         filter_replace_buf.data[0] |=
8257                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8258         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8259         filter_replace_buf.data[4] |=
8260                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8261
8262         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8263                                                &filter_replace_buf);
8264         if (!status && (filter_replace.old_filter_type !=
8265                         filter_replace.new_filter_type))
8266                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8267                             " original: 0x%x, new: 0x%x",
8268                             dev->device->name,
8269                             filter_replace.old_filter_type,
8270                             filter_replace.new_filter_type);
8271
8272         return status;
8273 }
8274
8275 static enum i40e_status_code
8276 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8277 {
8278         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8279         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8280         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8281         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8282         enum i40e_status_code status = I40E_SUCCESS;
8283
8284         if (pf->support_multi_driver) {
8285                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8286                 return I40E_NOT_SUPPORTED;
8287         }
8288
8289         /* For GTP-C */
8290         memset(&filter_replace, 0,
8291                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8292         memset(&filter_replace_buf, 0,
8293                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8294         /* create L1 filter */
8295         filter_replace.old_filter_type =
8296                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8297         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8298         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8299                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8300         /* Prepare the buffer, 2 entries */
8301         filter_replace_buf.data[0] =
8302                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8303         filter_replace_buf.data[0] |=
8304                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8305         filter_replace_buf.data[2] = 0xFF;
8306         filter_replace_buf.data[3] = 0xFF;
8307         filter_replace_buf.data[4] =
8308                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8309         filter_replace_buf.data[4] |=
8310                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8311         filter_replace_buf.data[6] = 0xFF;
8312         filter_replace_buf.data[7] = 0xFF;
8313         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8314                                                &filter_replace_buf);
8315         if (status < 0)
8316                 return status;
8317         if (filter_replace.old_filter_type !=
8318             filter_replace.new_filter_type)
8319                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8320                             " original: 0x%x, new: 0x%x",
8321                             dev->device->name,
8322                             filter_replace.old_filter_type,
8323                             filter_replace.new_filter_type);
8324
8325         /* for GTP-U */
8326         memset(&filter_replace, 0,
8327                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8328         memset(&filter_replace_buf, 0,
8329                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8330         /* create L1 filter */
8331         filter_replace.old_filter_type =
8332                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8333         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8334         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8335                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8336         /* Prepare the buffer, 2 entries */
8337         filter_replace_buf.data[0] =
8338                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8339         filter_replace_buf.data[0] |=
8340                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8341         filter_replace_buf.data[2] = 0xFF;
8342         filter_replace_buf.data[3] = 0xFF;
8343         filter_replace_buf.data[4] =
8344                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8345         filter_replace_buf.data[4] |=
8346                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8347         filter_replace_buf.data[6] = 0xFF;
8348         filter_replace_buf.data[7] = 0xFF;
8349
8350         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8351                                                &filter_replace_buf);
8352         if (!status && (filter_replace.old_filter_type !=
8353                         filter_replace.new_filter_type))
8354                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8355                             " original: 0x%x, new: 0x%x",
8356                             dev->device->name,
8357                             filter_replace.old_filter_type,
8358                             filter_replace.new_filter_type);
8359
8360         return status;
8361 }
8362
8363 static enum
8364 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8365 {
8366         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8367         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8368         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8369         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8370         enum i40e_status_code status = I40E_SUCCESS;
8371
8372         if (pf->support_multi_driver) {
8373                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8374                 return I40E_NOT_SUPPORTED;
8375         }
8376
8377         /* for GTP-C */
8378         memset(&filter_replace, 0,
8379                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8380         memset(&filter_replace_buf, 0,
8381                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8382         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8383         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8384         filter_replace.new_filter_type =
8385                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8386         /* Prepare the buffer, 2 entries */
8387         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8388         filter_replace_buf.data[0] |=
8389                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8390         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8391         filter_replace_buf.data[4] |=
8392                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8393         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8394                                                &filter_replace_buf);
8395         if (status < 0)
8396                 return status;
8397         if (filter_replace.old_filter_type !=
8398             filter_replace.new_filter_type)
8399                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8400                             " original: 0x%x, new: 0x%x",
8401                             dev->device->name,
8402                             filter_replace.old_filter_type,
8403                             filter_replace.new_filter_type);
8404
8405         /* for GTP-U */
8406         memset(&filter_replace, 0,
8407                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8408         memset(&filter_replace_buf, 0,
8409                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8410         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8411         filter_replace.old_filter_type =
8412                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8413         filter_replace.new_filter_type =
8414                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8415         /* Prepare the buffer, 2 entries */
8416         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8417         filter_replace_buf.data[0] |=
8418                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8419         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8420         filter_replace_buf.data[4] |=
8421                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8422
8423         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8424                                                &filter_replace_buf);
8425         if (!status && (filter_replace.old_filter_type !=
8426                         filter_replace.new_filter_type))
8427                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8428                             " original: 0x%x, new: 0x%x",
8429                             dev->device->name,
8430                             filter_replace.old_filter_type,
8431                             filter_replace.new_filter_type);
8432
8433         return status;
8434 }
8435
8436 static enum i40e_status_code
8437 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8438                             enum i40e_l4_port_type l4_port_type)
8439 {
8440         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8441         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8442         enum i40e_status_code status = I40E_SUCCESS;
8443         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8444         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8445
8446         if (pf->support_multi_driver) {
8447                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8448                 return I40E_NOT_SUPPORTED;
8449         }
8450
8451         memset(&filter_replace, 0,
8452                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8453         memset(&filter_replace_buf, 0,
8454                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8455
8456         /* create L1 filter */
8457         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8458                 filter_replace.old_filter_type =
8459                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8460                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8461                 filter_replace_buf.data[8] =
8462                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8463         } else {
8464                 filter_replace.old_filter_type =
8465                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8466                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8467                 filter_replace_buf.data[8] =
8468                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8469         }
8470
8471         filter_replace.tr_bit = 0;
8472         /* Prepare the buffer, 3 entries */
8473         filter_replace_buf.data[0] =
8474                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8475         filter_replace_buf.data[0] |=
8476                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8477         filter_replace_buf.data[2] = 0x00;
8478         filter_replace_buf.data[3] =
8479                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8480         filter_replace_buf.data[4] =
8481                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8482         filter_replace_buf.data[4] |=
8483                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8484         filter_replace_buf.data[5] = 0x00;
8485         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8486                 I40E_TR_L4_TYPE_TCP |
8487                 I40E_TR_L4_TYPE_SCTP;
8488         filter_replace_buf.data[7] = 0x00;
8489         filter_replace_buf.data[8] |=
8490                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8491         filter_replace_buf.data[9] = 0x00;
8492         filter_replace_buf.data[10] = 0xFF;
8493         filter_replace_buf.data[11] = 0xFF;
8494
8495         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8496                                                &filter_replace_buf);
8497         if (!status && filter_replace.old_filter_type !=
8498             filter_replace.new_filter_type)
8499                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8500                             " original: 0x%x, new: 0x%x",
8501                             dev->device->name,
8502                             filter_replace.old_filter_type,
8503                             filter_replace.new_filter_type);
8504
8505         return status;
8506 }
8507
8508 static enum i40e_status_code
8509 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8510                                enum i40e_l4_port_type l4_port_type)
8511 {
8512         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8513         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8514         enum i40e_status_code status = I40E_SUCCESS;
8515         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8516         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8517
8518         if (pf->support_multi_driver) {
8519                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8520                 return I40E_NOT_SUPPORTED;
8521         }
8522
8523         memset(&filter_replace, 0,
8524                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8525         memset(&filter_replace_buf, 0,
8526                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8527
8528         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8529                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8530                 filter_replace.new_filter_type =
8531                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8532                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8533         } else {
8534                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8535                 filter_replace.new_filter_type =
8536                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8537                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8538         }
8539
8540         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8541         filter_replace.tr_bit = 0;
8542         /* Prepare the buffer, 2 entries */
8543         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8544         filter_replace_buf.data[0] |=
8545                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8546         filter_replace_buf.data[4] |=
8547                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8548         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8549                                                &filter_replace_buf);
8550
8551         if (!status && filter_replace.old_filter_type !=
8552             filter_replace.new_filter_type)
8553                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8554                             " original: 0x%x, new: 0x%x",
8555                             dev->device->name,
8556                             filter_replace.old_filter_type,
8557                             filter_replace.new_filter_type);
8558
8559         return status;
8560 }
8561
8562 int
8563 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8564                       struct i40e_tunnel_filter_conf *tunnel_filter,
8565                       uint8_t add)
8566 {
8567         uint16_t ip_type;
8568         uint32_t ipv4_addr, ipv4_addr_le;
8569         uint8_t i, tun_type = 0;
8570         /* internal variable to convert ipv6 byte order */
8571         uint32_t convert_ipv6[4];
8572         int val, ret = 0;
8573         struct i40e_pf_vf *vf = NULL;
8574         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8575         struct i40e_vsi *vsi;
8576         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8577         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8578         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8579         struct i40e_tunnel_filter *tunnel, *node;
8580         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8581         uint32_t teid_le;
8582         bool big_buffer = 0;
8583
8584         cld_filter = rte_zmalloc("tunnel_filter",
8585                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8586                          0);
8587
8588         if (cld_filter == NULL) {
8589                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8590                 return -ENOMEM;
8591         }
8592         pfilter = cld_filter;
8593
8594         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8595                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8596         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8597                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8598
8599         pfilter->element.inner_vlan =
8600                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8601         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8602                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8603                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8604                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8605                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8606                                 &ipv4_addr_le,
8607                                 sizeof(pfilter->element.ipaddr.v4.data));
8608         } else {
8609                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8610                 for (i = 0; i < 4; i++) {
8611                         convert_ipv6[i] =
8612                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8613                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8614                 }
8615                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8616                            &convert_ipv6,
8617                            sizeof(pfilter->element.ipaddr.v6.data));
8618         }
8619
8620         /* check tunneled type */
8621         switch (tunnel_filter->tunnel_type) {
8622         case I40E_TUNNEL_TYPE_VXLAN:
8623                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8624                 break;
8625         case I40E_TUNNEL_TYPE_NVGRE:
8626                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8627                 break;
8628         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8629                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8630                 break;
8631         case I40E_TUNNEL_TYPE_MPLSoUDP:
8632                 if (!pf->mpls_replace_flag) {
8633                         i40e_replace_mpls_l1_filter(pf);
8634                         i40e_replace_mpls_cloud_filter(pf);
8635                         pf->mpls_replace_flag = 1;
8636                 }
8637                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8638                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8639                         teid_le >> 4;
8640                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8641                         (teid_le & 0xF) << 12;
8642                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8643                         0x40;
8644                 big_buffer = 1;
8645                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8646                 break;
8647         case I40E_TUNNEL_TYPE_MPLSoGRE:
8648                 if (!pf->mpls_replace_flag) {
8649                         i40e_replace_mpls_l1_filter(pf);
8650                         i40e_replace_mpls_cloud_filter(pf);
8651                         pf->mpls_replace_flag = 1;
8652                 }
8653                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8654                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8655                         teid_le >> 4;
8656                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8657                         (teid_le & 0xF) << 12;
8658                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8659                         0x0;
8660                 big_buffer = 1;
8661                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8662                 break;
8663         case I40E_TUNNEL_TYPE_GTPC:
8664                 if (!pf->gtp_replace_flag) {
8665                         i40e_replace_gtp_l1_filter(pf);
8666                         i40e_replace_gtp_cloud_filter(pf);
8667                         pf->gtp_replace_flag = 1;
8668                 }
8669                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8670                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8671                         (teid_le >> 16) & 0xFFFF;
8672                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8673                         teid_le & 0xFFFF;
8674                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8675                         0x0;
8676                 big_buffer = 1;
8677                 break;
8678         case I40E_TUNNEL_TYPE_GTPU:
8679                 if (!pf->gtp_replace_flag) {
8680                         i40e_replace_gtp_l1_filter(pf);
8681                         i40e_replace_gtp_cloud_filter(pf);
8682                         pf->gtp_replace_flag = 1;
8683                 }
8684                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8685                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8686                         (teid_le >> 16) & 0xFFFF;
8687                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8688                         teid_le & 0xFFFF;
8689                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8690                         0x0;
8691                 big_buffer = 1;
8692                 break;
8693         case I40E_TUNNEL_TYPE_QINQ:
8694                 if (!pf->qinq_replace_flag) {
8695                         ret = i40e_cloud_filter_qinq_create(pf);
8696                         if (ret < 0)
8697                                 PMD_DRV_LOG(DEBUG,
8698                                             "QinQ tunnel filter already created.");
8699                         pf->qinq_replace_flag = 1;
8700                 }
8701                 /*      Add in the General fields the values of
8702                  *      the Outer and Inner VLAN
8703                  *      Big Buffer should be set, see changes in
8704                  *      i40e_aq_add_cloud_filters
8705                  */
8706                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8707                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8708                 big_buffer = 1;
8709                 break;
8710         case I40E_CLOUD_TYPE_UDP:
8711         case I40E_CLOUD_TYPE_TCP:
8712         case I40E_CLOUD_TYPE_SCTP:
8713                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8714                         if (!pf->sport_replace_flag) {
8715                                 i40e_replace_port_l1_filter(pf,
8716                                                 tunnel_filter->l4_port_type);
8717                                 i40e_replace_port_cloud_filter(pf,
8718                                                 tunnel_filter->l4_port_type);
8719                                 pf->sport_replace_flag = 1;
8720                         }
8721                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8722                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8723                                 I40E_DIRECTION_INGRESS_KEY;
8724
8725                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8726                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8727                                         I40E_TR_L4_TYPE_UDP;
8728                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8729                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8730                                         I40E_TR_L4_TYPE_TCP;
8731                         else
8732                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8733                                         I40E_TR_L4_TYPE_SCTP;
8734
8735                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8736                                 (teid_le >> 16) & 0xFFFF;
8737                         big_buffer = 1;
8738                 } else {
8739                         if (!pf->dport_replace_flag) {
8740                                 i40e_replace_port_l1_filter(pf,
8741                                                 tunnel_filter->l4_port_type);
8742                                 i40e_replace_port_cloud_filter(pf,
8743                                                 tunnel_filter->l4_port_type);
8744                                 pf->dport_replace_flag = 1;
8745                         }
8746                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8747                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8748                                 I40E_DIRECTION_INGRESS_KEY;
8749
8750                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8751                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8752                                         I40E_TR_L4_TYPE_UDP;
8753                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8754                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8755                                         I40E_TR_L4_TYPE_TCP;
8756                         else
8757                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8758                                         I40E_TR_L4_TYPE_SCTP;
8759
8760                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8761                                 (teid_le >> 16) & 0xFFFF;
8762                         big_buffer = 1;
8763                 }
8764
8765                 break;
8766         default:
8767                 /* Other tunnel types is not supported. */
8768                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8769                 rte_free(cld_filter);
8770                 return -EINVAL;
8771         }
8772
8773         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8774                 pfilter->element.flags =
8775                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8776         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8777                 pfilter->element.flags =
8778                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8779         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8780                 pfilter->element.flags =
8781                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8782         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8783                 pfilter->element.flags =
8784                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8785         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8786                 pfilter->element.flags |=
8787                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8788         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8789                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8790                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8791                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8792                         pfilter->element.flags |=
8793                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8794                 else
8795                         pfilter->element.flags |=
8796                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8797         } else {
8798                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8799                                                 &pfilter->element.flags);
8800                 if (val < 0) {
8801                         rte_free(cld_filter);
8802                         return -EINVAL;
8803                 }
8804         }
8805
8806         pfilter->element.flags |= rte_cpu_to_le_16(
8807                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8808                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8809         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8810         pfilter->element.queue_number =
8811                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8812
8813         if (!tunnel_filter->is_to_vf)
8814                 vsi = pf->main_vsi;
8815         else {
8816                 if (tunnel_filter->vf_id >= pf->vf_num) {
8817                         PMD_DRV_LOG(ERR, "Invalid argument.");
8818                         rte_free(cld_filter);
8819                         return -EINVAL;
8820                 }
8821                 vf = &pf->vfs[tunnel_filter->vf_id];
8822                 vsi = vf->vsi;
8823         }
8824
8825         /* Check if there is the filter in SW list */
8826         memset(&check_filter, 0, sizeof(check_filter));
8827         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8828         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8829         check_filter.vf_id = tunnel_filter->vf_id;
8830         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8831         if (add && node) {
8832                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8833                 rte_free(cld_filter);
8834                 return -EINVAL;
8835         }
8836
8837         if (!add && !node) {
8838                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8839                 rte_free(cld_filter);
8840                 return -EINVAL;
8841         }
8842
8843         if (add) {
8844                 if (big_buffer)
8845                         ret = i40e_aq_add_cloud_filters_bb(hw,
8846                                                    vsi->seid, cld_filter, 1);
8847                 else
8848                         ret = i40e_aq_add_cloud_filters(hw,
8849                                         vsi->seid, &cld_filter->element, 1);
8850                 if (ret < 0) {
8851                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8852                         rte_free(cld_filter);
8853                         return -ENOTSUP;
8854                 }
8855                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8856                 if (tunnel == NULL) {
8857                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8858                         rte_free(cld_filter);
8859                         return -ENOMEM;
8860                 }
8861
8862                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8863                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8864                 if (ret < 0)
8865                         rte_free(tunnel);
8866         } else {
8867                 if (big_buffer)
8868                         ret = i40e_aq_rem_cloud_filters_bb(
8869                                 hw, vsi->seid, cld_filter, 1);
8870                 else
8871                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8872                                                 &cld_filter->element, 1);
8873                 if (ret < 0) {
8874                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8875                         rte_free(cld_filter);
8876                         return -ENOTSUP;
8877                 }
8878                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8879         }
8880
8881         rte_free(cld_filter);
8882         return ret;
8883 }
8884
8885 static int
8886 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8887 {
8888         uint8_t i;
8889
8890         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8891                 if (pf->vxlan_ports[i] == port)
8892                         return i;
8893         }
8894
8895         return -1;
8896 }
8897
8898 static int
8899 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8900 {
8901         int  idx, ret;
8902         uint8_t filter_idx = 0;
8903         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8904
8905         idx = i40e_get_vxlan_port_idx(pf, port);
8906
8907         /* Check if port already exists */
8908         if (idx >= 0) {
8909                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8910                 return -EINVAL;
8911         }
8912
8913         /* Now check if there is space to add the new port */
8914         idx = i40e_get_vxlan_port_idx(pf, 0);
8915         if (idx < 0) {
8916                 PMD_DRV_LOG(ERR,
8917                         "Maximum number of UDP ports reached, not adding port %d",
8918                         port);
8919                 return -ENOSPC;
8920         }
8921
8922         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8923                                         &filter_idx, NULL);
8924         if (ret < 0) {
8925                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8926                 return -1;
8927         }
8928
8929         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8930                          port,  filter_idx);
8931
8932         /* New port: add it and mark its index in the bitmap */
8933         pf->vxlan_ports[idx] = port;
8934         pf->vxlan_bitmap |= (1 << idx);
8935
8936         if (!(pf->flags & I40E_FLAG_VXLAN))
8937                 pf->flags |= I40E_FLAG_VXLAN;
8938
8939         return 0;
8940 }
8941
8942 static int
8943 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8944 {
8945         int idx;
8946         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8947
8948         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8949                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8950                 return -EINVAL;
8951         }
8952
8953         idx = i40e_get_vxlan_port_idx(pf, port);
8954
8955         if (idx < 0) {
8956                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8957                 return -EINVAL;
8958         }
8959
8960         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8961                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8962                 return -1;
8963         }
8964
8965         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8966                         port, idx);
8967
8968         pf->vxlan_ports[idx] = 0;
8969         pf->vxlan_bitmap &= ~(1 << idx);
8970
8971         if (!pf->vxlan_bitmap)
8972                 pf->flags &= ~I40E_FLAG_VXLAN;
8973
8974         return 0;
8975 }
8976
8977 /* Add UDP tunneling port */
8978 static int
8979 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8980                              struct rte_eth_udp_tunnel *udp_tunnel)
8981 {
8982         int ret = 0;
8983         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8984
8985         if (udp_tunnel == NULL)
8986                 return -EINVAL;
8987
8988         switch (udp_tunnel->prot_type) {
8989         case RTE_TUNNEL_TYPE_VXLAN:
8990                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8991                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8992                 break;
8993         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8994                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8995                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8996                 break;
8997         case RTE_TUNNEL_TYPE_GENEVE:
8998         case RTE_TUNNEL_TYPE_TEREDO:
8999                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9000                 ret = -1;
9001                 break;
9002
9003         default:
9004                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9005                 ret = -1;
9006                 break;
9007         }
9008
9009         return ret;
9010 }
9011
9012 /* Remove UDP tunneling port */
9013 static int
9014 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
9015                              struct rte_eth_udp_tunnel *udp_tunnel)
9016 {
9017         int ret = 0;
9018         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9019
9020         if (udp_tunnel == NULL)
9021                 return -EINVAL;
9022
9023         switch (udp_tunnel->prot_type) {
9024         case RTE_TUNNEL_TYPE_VXLAN:
9025         case RTE_TUNNEL_TYPE_VXLAN_GPE:
9026                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
9027                 break;
9028         case RTE_TUNNEL_TYPE_GENEVE:
9029         case RTE_TUNNEL_TYPE_TEREDO:
9030                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9031                 ret = -1;
9032                 break;
9033         default:
9034                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9035                 ret = -1;
9036                 break;
9037         }
9038
9039         return ret;
9040 }
9041
9042 /* Calculate the maximum number of contiguous PF queues that are configured */
9043 static int
9044 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
9045 {
9046         struct rte_eth_dev_data *data = pf->dev_data;
9047         int i, num;
9048         struct i40e_rx_queue *rxq;
9049
9050         num = 0;
9051         for (i = 0; i < pf->lan_nb_qps; i++) {
9052                 rxq = data->rx_queues[i];
9053                 if (rxq && rxq->q_set)
9054                         num++;
9055                 else
9056                         break;
9057         }
9058
9059         return num;
9060 }
9061
9062 /* Configure RSS */
9063 static int
9064 i40e_pf_config_rss(struct i40e_pf *pf)
9065 {
9066         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9067         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9068         struct rte_eth_rss_conf rss_conf;
9069         uint32_t i, lut = 0;
9070         uint16_t j, num;
9071
9072         /*
9073          * If both VMDQ and RSS enabled, not all of PF queues are configured.
9074          * It's necessary to calculate the actual PF queues that are configured.
9075          */
9076         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9077                 num = i40e_pf_calc_configured_queues_num(pf);
9078         else
9079                 num = pf->dev_data->nb_rx_queues;
9080
9081         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9082         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9083                         num);
9084
9085         if (num == 0) {
9086                 PMD_INIT_LOG(ERR,
9087                         "No PF queues are configured to enable RSS for port %u",
9088                         pf->dev_data->port_id);
9089                 return -ENOTSUP;
9090         }
9091
9092         if (pf->adapter->rss_reta_updated == 0) {
9093                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9094                         if (j == num)
9095                                 j = 0;
9096                         lut = (lut << 8) | (j & ((0x1 <<
9097                                 hw->func_caps.rss_table_entry_width) - 1));
9098                         if ((i & 3) == 3)
9099                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9100                                                rte_bswap32(lut));
9101                 }
9102         }
9103
9104         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9105         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
9106             !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
9107                 i40e_pf_disable_rss(pf);
9108                 return 0;
9109         }
9110         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9111                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9112                 /* Random default keys */
9113                 static uint32_t rss_key_default[] = {0x6b793944,
9114                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9115                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9116                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9117
9118                 rss_conf.rss_key = (uint8_t *)rss_key_default;
9119                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9120                                                         sizeof(uint32_t);
9121         }
9122
9123         return i40e_hw_rss_hash_set(pf, &rss_conf);
9124 }
9125
9126 static int
9127 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9128                                struct rte_eth_tunnel_filter_conf *filter)
9129 {
9130         if (pf == NULL || filter == NULL) {
9131                 PMD_DRV_LOG(ERR, "Invalid parameter");
9132                 return -EINVAL;
9133         }
9134
9135         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9136                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9137                 return -EINVAL;
9138         }
9139
9140         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9141                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9142                 return -EINVAL;
9143         }
9144
9145         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9146                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9147                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9148                 return -EINVAL;
9149         }
9150
9151         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9152                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9153                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9154                 return -EINVAL;
9155         }
9156
9157         return 0;
9158 }
9159
9160 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9161 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
9162 int
9163 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9164 {
9165         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9166         uint32_t val, reg;
9167         int ret = -EINVAL;
9168
9169         if (pf->support_multi_driver) {
9170                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9171                 return -ENOTSUP;
9172         }
9173
9174         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9175         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9176
9177         if (len == 3) {
9178                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9179         } else if (len == 4) {
9180                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9181         } else {
9182                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9183                 return ret;
9184         }
9185
9186         if (reg != val) {
9187                 ret = i40e_aq_debug_write_global_register(hw,
9188                                                    I40E_GL_PRS_FVBM(2),
9189                                                    reg, NULL);
9190                 if (ret != 0)
9191                         return ret;
9192                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9193                             "with value 0x%08x",
9194                             I40E_GL_PRS_FVBM(2), reg);
9195         } else {
9196                 ret = 0;
9197         }
9198         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9199                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9200
9201         return ret;
9202 }
9203
9204 static int
9205 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9206 {
9207         int ret = -EINVAL;
9208
9209         if (!hw || !cfg)
9210                 return -EINVAL;
9211
9212         switch (cfg->cfg_type) {
9213         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9214                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9215                 break;
9216         default:
9217                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9218                 break;
9219         }
9220
9221         return ret;
9222 }
9223
9224 static int
9225 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9226                                enum rte_filter_op filter_op,
9227                                void *arg)
9228 {
9229         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9230         int ret = I40E_ERR_PARAM;
9231
9232         switch (filter_op) {
9233         case RTE_ETH_FILTER_SET:
9234                 ret = i40e_dev_global_config_set(hw,
9235                         (struct rte_eth_global_cfg *)arg);
9236                 break;
9237         default:
9238                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9239                 break;
9240         }
9241
9242         return ret;
9243 }
9244
9245 static int
9246 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9247                           enum rte_filter_op filter_op,
9248                           void *arg)
9249 {
9250         struct rte_eth_tunnel_filter_conf *filter;
9251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9252         int ret = I40E_SUCCESS;
9253
9254         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9255
9256         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9257                 return I40E_ERR_PARAM;
9258
9259         switch (filter_op) {
9260         case RTE_ETH_FILTER_NOP:
9261                 if (!(pf->flags & I40E_FLAG_VXLAN))
9262                         ret = I40E_NOT_SUPPORTED;
9263                 break;
9264         case RTE_ETH_FILTER_ADD:
9265                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9266                 break;
9267         case RTE_ETH_FILTER_DELETE:
9268                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9269                 break;
9270         default:
9271                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9272                 ret = I40E_ERR_PARAM;
9273                 break;
9274         }
9275
9276         return ret;
9277 }
9278
9279 /* Get the symmetric hash enable configurations per port */
9280 static void
9281 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9282 {
9283         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9284
9285         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9286 }
9287
9288 /* Set the symmetric hash enable configurations per port */
9289 static void
9290 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9291 {
9292         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9293
9294         if (enable > 0) {
9295                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9296                         PMD_DRV_LOG(INFO,
9297                                 "Symmetric hash has already been enabled");
9298                         return;
9299                 }
9300                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9301         } else {
9302                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9303                         PMD_DRV_LOG(INFO,
9304                                 "Symmetric hash has already been disabled");
9305                         return;
9306                 }
9307                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9308         }
9309         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9310         I40E_WRITE_FLUSH(hw);
9311 }
9312
9313 /*
9314  * Get global configurations of hash function type and symmetric hash enable
9315  * per flow type (pctype). Note that global configuration means it affects all
9316  * the ports on the same NIC.
9317  */
9318 static int
9319 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9320                                    struct rte_eth_hash_global_conf *g_cfg)
9321 {
9322         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9323         uint32_t reg;
9324         uint16_t i, j;
9325
9326         memset(g_cfg, 0, sizeof(*g_cfg));
9327         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9328         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9329                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9330         else
9331                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9332         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9333                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9334
9335         /*
9336          * As i40e supports less than 64 flow types, only first 64 bits need to
9337          * be checked.
9338          */
9339         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9340                 g_cfg->valid_bit_mask[i] = 0ULL;
9341                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9342         }
9343
9344         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9345
9346         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9347                 if (!adapter->pctypes_tbl[i])
9348                         continue;
9349                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9350                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9351                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9352                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9353                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9354                                         g_cfg->sym_hash_enable_mask[0] |=
9355                                                                 (1ULL << i);
9356                                 }
9357                         }
9358                 }
9359         }
9360
9361         return 0;
9362 }
9363
9364 static int
9365 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9366                               const struct rte_eth_hash_global_conf *g_cfg)
9367 {
9368         uint32_t i;
9369         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9370
9371         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9372                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9373                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9374                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9375                                                 g_cfg->hash_func);
9376                 return -EINVAL;
9377         }
9378
9379         /*
9380          * As i40e supports less than 64 flow types, only first 64 bits need to
9381          * be checked.
9382          */
9383         mask0 = g_cfg->valid_bit_mask[0];
9384         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9385                 if (i == 0) {
9386                         /* Check if any unsupported flow type configured */
9387                         if ((mask0 | i40e_mask) ^ i40e_mask)
9388                                 goto mask_err;
9389                 } else {
9390                         if (g_cfg->valid_bit_mask[i])
9391                                 goto mask_err;
9392                 }
9393         }
9394
9395         return 0;
9396
9397 mask_err:
9398         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9399
9400         return -EINVAL;
9401 }
9402
9403 /*
9404  * Set global configurations of hash function type and symmetric hash enable
9405  * per flow type (pctype). Note any modifying global configuration will affect
9406  * all the ports on the same NIC.
9407  */
9408 static int
9409 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9410                                    struct rte_eth_hash_global_conf *g_cfg)
9411 {
9412         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9413         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9414         int ret;
9415         uint16_t i, j;
9416         uint32_t reg;
9417         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9418
9419         if (pf->support_multi_driver) {
9420                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9421                 return -ENOTSUP;
9422         }
9423
9424         /* Check the input parameters */
9425         ret = i40e_hash_global_config_check(adapter, g_cfg);
9426         if (ret < 0)
9427                 return ret;
9428
9429         /*
9430          * As i40e supports less than 64 flow types, only first 64 bits need to
9431          * be configured.
9432          */
9433         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9434                 if (mask0 & (1UL << i)) {
9435                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9436                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9437
9438                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9439                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9440                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9441                                         i40e_write_global_rx_ctl(hw,
9442                                                           I40E_GLQF_HSYM(j),
9443                                                           reg);
9444                         }
9445                 }
9446         }
9447
9448         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9449         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9450                 /* Toeplitz */
9451                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9452                         PMD_DRV_LOG(DEBUG,
9453                                 "Hash function already set to Toeplitz");
9454                         goto out;
9455                 }
9456                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9457         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9458                 /* Simple XOR */
9459                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9460                         PMD_DRV_LOG(DEBUG,
9461                                 "Hash function already set to Simple XOR");
9462                         goto out;
9463                 }
9464                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9465         } else
9466                 /* Use the default, and keep it as it is */
9467                 goto out;
9468
9469         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9470
9471 out:
9472         I40E_WRITE_FLUSH(hw);
9473
9474         return 0;
9475 }
9476
9477 /**
9478  * Valid input sets for hash and flow director filters per PCTYPE
9479  */
9480 static uint64_t
9481 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9482                 enum rte_filter_type filter)
9483 {
9484         uint64_t valid;
9485
9486         static const uint64_t valid_hash_inset_table[] = {
9487                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9488                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9489                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9490                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9491                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9492                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9493                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9494                         I40E_INSET_FLEX_PAYLOAD,
9495                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9496                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9497                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9498                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9499                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9500                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9501                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9502                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9503                         I40E_INSET_FLEX_PAYLOAD,
9504                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9505                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9506                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9507                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9508                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9509                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9510                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9511                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9512                         I40E_INSET_FLEX_PAYLOAD,
9513                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9514                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9515                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9516                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9517                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9518                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9519                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9520                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9521                         I40E_INSET_FLEX_PAYLOAD,
9522                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9523                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9524                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9525                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9526                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9527                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9528                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9529                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9530                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9531                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9532                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9533                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9534                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9535                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9536                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9537                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9538                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9539                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9540                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9541                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9542                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9543                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9544                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9545                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9546                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9547                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9548                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9549                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9550                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9551                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9552                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9553                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9554                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9555                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9556                         I40E_INSET_FLEX_PAYLOAD,
9557                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9558                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9559                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9560                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9561                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9562                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9563                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9564                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9565                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9566                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9567                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9568                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9569                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9570                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9571                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9572                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9573                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9574                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9575                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9576                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9577                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9578                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9579                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9580                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9581                         I40E_INSET_FLEX_PAYLOAD,
9582                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9583                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9584                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9585                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9586                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9587                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9588                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9589                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9590                         I40E_INSET_FLEX_PAYLOAD,
9591                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9592                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9593                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9594                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9595                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9596                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9597                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9598                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9599                         I40E_INSET_FLEX_PAYLOAD,
9600                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9601                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9602                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9603                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9604                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9605                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9606                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9607                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9608                         I40E_INSET_FLEX_PAYLOAD,
9609                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9610                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9611                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9612                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9613                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9614                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9615                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9616                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9617                         I40E_INSET_FLEX_PAYLOAD,
9618                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9619                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9620                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9621                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9622                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9623                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9624                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9625                         I40E_INSET_FLEX_PAYLOAD,
9626                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9627                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9628                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9629                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9630                         I40E_INSET_FLEX_PAYLOAD,
9631         };
9632
9633         /**
9634          * Flow director supports only fields defined in
9635          * union rte_eth_fdir_flow.
9636          */
9637         static const uint64_t valid_fdir_inset_table[] = {
9638                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9639                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9640                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9641                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9642                 I40E_INSET_IPV4_TTL,
9643                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9644                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9645                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9646                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9647                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9648                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9649                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9650                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9651                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9652                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9653                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9654                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9655                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9656                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9657                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9658                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9659                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9660                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9661                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9662                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9663                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9664                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9665                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9666                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9667                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9668                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9669                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9670                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9671                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9672                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9673                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9674                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9675                 I40E_INSET_SCTP_VT,
9676                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9677                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9678                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9679                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9680                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9681                 I40E_INSET_IPV4_TTL,
9682                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9683                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9684                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9685                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9686                 I40E_INSET_IPV6_HOP_LIMIT,
9687                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9688                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9689                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9690                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9691                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9692                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9693                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9694                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9695                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9696                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9697                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9698                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9699                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9700                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9701                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9702                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9703                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9704                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9705                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9706                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9707                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9708                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9709                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9710                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9711                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9712                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9713                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9714                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9715                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9716                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9717                 I40E_INSET_SCTP_VT,
9718                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9719                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9720                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9721                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9722                 I40E_INSET_IPV6_HOP_LIMIT,
9723                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9724                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9725                 I40E_INSET_LAST_ETHER_TYPE,
9726         };
9727
9728         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9729                 return 0;
9730         if (filter == RTE_ETH_FILTER_HASH)
9731                 valid = valid_hash_inset_table[pctype];
9732         else
9733                 valid = valid_fdir_inset_table[pctype];
9734
9735         return valid;
9736 }
9737
9738 /**
9739  * Validate if the input set is allowed for a specific PCTYPE
9740  */
9741 int
9742 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9743                 enum rte_filter_type filter, uint64_t inset)
9744 {
9745         uint64_t valid;
9746
9747         valid = i40e_get_valid_input_set(pctype, filter);
9748         if (inset & (~valid))
9749                 return -EINVAL;
9750
9751         return 0;
9752 }
9753
9754 /* default input set fields combination per pctype */
9755 uint64_t
9756 i40e_get_default_input_set(uint16_t pctype)
9757 {
9758         static const uint64_t default_inset_table[] = {
9759                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9760                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9761                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9762                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9763                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9764                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9765                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9766                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9767                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9768                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9769                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9770                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9771                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9772                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9773                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9774                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9775                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9776                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9777                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9779                         I40E_INSET_SCTP_VT,
9780                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9781                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9782                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9783                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9784                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9785                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9786                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9787                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9788                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9789                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9790                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9791                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9792                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9793                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9794                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9795                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9796                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9797                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9798                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9799                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9800                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9801                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9802                         I40E_INSET_SCTP_VT,
9803                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9804                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9805                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9806                         I40E_INSET_LAST_ETHER_TYPE,
9807         };
9808
9809         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9810                 return 0;
9811
9812         return default_inset_table[pctype];
9813 }
9814
9815 /**
9816  * Parse the input set from index to logical bit masks
9817  */
9818 static int
9819 i40e_parse_input_set(uint64_t *inset,
9820                      enum i40e_filter_pctype pctype,
9821                      enum rte_eth_input_set_field *field,
9822                      uint16_t size)
9823 {
9824         uint16_t i, j;
9825         int ret = -EINVAL;
9826
9827         static const struct {
9828                 enum rte_eth_input_set_field field;
9829                 uint64_t inset;
9830         } inset_convert_table[] = {
9831                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9832                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9833                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9834                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9835                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9836                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9837                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9838                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9839                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9840                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9841                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9842                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9843                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9844                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9845                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9846                         I40E_INSET_IPV6_NEXT_HDR},
9847                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9848                         I40E_INSET_IPV6_HOP_LIMIT},
9849                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9850                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9851                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9852                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9853                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9854                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9855                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9856                         I40E_INSET_SCTP_VT},
9857                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9858                         I40E_INSET_TUNNEL_DMAC},
9859                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9860                         I40E_INSET_VLAN_TUNNEL},
9861                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9862                         I40E_INSET_TUNNEL_ID},
9863                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9864                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9865                         I40E_INSET_FLEX_PAYLOAD_W1},
9866                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9867                         I40E_INSET_FLEX_PAYLOAD_W2},
9868                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9869                         I40E_INSET_FLEX_PAYLOAD_W3},
9870                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9871                         I40E_INSET_FLEX_PAYLOAD_W4},
9872                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9873                         I40E_INSET_FLEX_PAYLOAD_W5},
9874                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9875                         I40E_INSET_FLEX_PAYLOAD_W6},
9876                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9877                         I40E_INSET_FLEX_PAYLOAD_W7},
9878                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9879                         I40E_INSET_FLEX_PAYLOAD_W8},
9880         };
9881
9882         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9883                 return ret;
9884
9885         /* Only one item allowed for default or all */
9886         if (size == 1) {
9887                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9888                         *inset = i40e_get_default_input_set(pctype);
9889                         return 0;
9890                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9891                         *inset = I40E_INSET_NONE;
9892                         return 0;
9893                 }
9894         }
9895
9896         for (i = 0, *inset = 0; i < size; i++) {
9897                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9898                         if (field[i] == inset_convert_table[j].field) {
9899                                 *inset |= inset_convert_table[j].inset;
9900                                 break;
9901                         }
9902                 }
9903
9904                 /* It contains unsupported input set, return immediately */
9905                 if (j == RTE_DIM(inset_convert_table))
9906                         return ret;
9907         }
9908
9909         return 0;
9910 }
9911
9912 /**
9913  * Translate the input set from bit masks to register aware bit masks
9914  * and vice versa
9915  */
9916 uint64_t
9917 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9918 {
9919         uint64_t val = 0;
9920         uint16_t i;
9921
9922         struct inset_map {
9923                 uint64_t inset;
9924                 uint64_t inset_reg;
9925         };
9926
9927         static const struct inset_map inset_map_common[] = {
9928                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9929                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9930                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9931                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9932                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9933                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9934                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9935                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9936                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9937                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9938                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9939                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9940                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9941                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9942                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9943                 {I40E_INSET_TUNNEL_DMAC,
9944                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9945                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9946                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9947                 {I40E_INSET_TUNNEL_SRC_PORT,
9948                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9949                 {I40E_INSET_TUNNEL_DST_PORT,
9950                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9951                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9952                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9953                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9954                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9955                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9956                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9957                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9958                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9959                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9960         };
9961
9962     /* some different registers map in x722*/
9963         static const struct inset_map inset_map_diff_x722[] = {
9964                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9965                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9966                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9967                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9968         };
9969
9970         static const struct inset_map inset_map_diff_not_x722[] = {
9971                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9972                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9973                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9974                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9975         };
9976
9977         if (input == 0)
9978                 return val;
9979
9980         /* Translate input set to register aware inset */
9981         if (type == I40E_MAC_X722) {
9982                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9983                         if (input & inset_map_diff_x722[i].inset)
9984                                 val |= inset_map_diff_x722[i].inset_reg;
9985                 }
9986         } else {
9987                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9988                         if (input & inset_map_diff_not_x722[i].inset)
9989                                 val |= inset_map_diff_not_x722[i].inset_reg;
9990                 }
9991         }
9992
9993         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9994                 if (input & inset_map_common[i].inset)
9995                         val |= inset_map_common[i].inset_reg;
9996         }
9997
9998         return val;
9999 }
10000
10001 int
10002 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
10003 {
10004         uint8_t i, idx = 0;
10005         uint64_t inset_need_mask = inset;
10006
10007         static const struct {
10008                 uint64_t inset;
10009                 uint32_t mask;
10010         } inset_mask_map[] = {
10011                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
10012                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
10013                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
10014                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
10015                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
10016                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
10017                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
10018                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
10019         };
10020
10021         if (!inset || !mask || !nb_elem)
10022                 return 0;
10023
10024         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10025                 /* Clear the inset bit, if no MASK is required,
10026                  * for example proto + ttl
10027                  */
10028                 if ((inset & inset_mask_map[i].inset) ==
10029                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
10030                         inset_need_mask &= ~inset_mask_map[i].inset;
10031                 if (!inset_need_mask)
10032                         return 0;
10033         }
10034         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10035                 if ((inset_need_mask & inset_mask_map[i].inset) ==
10036                     inset_mask_map[i].inset) {
10037                         if (idx >= nb_elem) {
10038                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
10039                                 return -EINVAL;
10040                         }
10041                         mask[idx] = inset_mask_map[i].mask;
10042                         idx++;
10043                 }
10044         }
10045
10046         return idx;
10047 }
10048
10049 void
10050 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10051 {
10052         uint32_t reg = i40e_read_rx_ctl(hw, addr);
10053
10054         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
10055         if (reg != val)
10056                 i40e_write_rx_ctl(hw, addr, val);
10057         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
10058                     (uint32_t)i40e_read_rx_ctl(hw, addr));
10059 }
10060
10061 void
10062 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10063 {
10064         uint32_t reg = i40e_read_rx_ctl(hw, addr);
10065         struct rte_eth_dev *dev;
10066
10067         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10068         if (reg != val) {
10069                 i40e_write_rx_ctl(hw, addr, val);
10070                 PMD_DRV_LOG(WARNING,
10071                             "i40e device %s changed global register [0x%08x]."
10072                             " original: 0x%08x, new: 0x%08x",
10073                             dev->device->name, addr, reg,
10074                             (uint32_t)i40e_read_rx_ctl(hw, addr));
10075         }
10076 }
10077
10078 static void
10079 i40e_filter_input_set_init(struct i40e_pf *pf)
10080 {
10081         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10082         enum i40e_filter_pctype pctype;
10083         uint64_t input_set, inset_reg;
10084         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10085         int num, i;
10086         uint16_t flow_type;
10087
10088         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10089              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10090                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10091
10092                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10093                         continue;
10094
10095                 input_set = i40e_get_default_input_set(pctype);
10096
10097                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10098                                                    I40E_INSET_MASK_NUM_REG);
10099                 if (num < 0)
10100                         return;
10101                 if (pf->support_multi_driver && num > 0) {
10102                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10103                         return;
10104                 }
10105                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10106                                         input_set);
10107
10108                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10109                                       (uint32_t)(inset_reg & UINT32_MAX));
10110                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10111                                      (uint32_t)((inset_reg >>
10112                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
10113                 if (!pf->support_multi_driver) {
10114                         i40e_check_write_global_reg(hw,
10115                                             I40E_GLQF_HASH_INSET(0, pctype),
10116                                             (uint32_t)(inset_reg & UINT32_MAX));
10117                         i40e_check_write_global_reg(hw,
10118                                              I40E_GLQF_HASH_INSET(1, pctype),
10119                                              (uint32_t)((inset_reg >>
10120                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
10121
10122                         for (i = 0; i < num; i++) {
10123                                 i40e_check_write_global_reg(hw,
10124                                                     I40E_GLQF_FD_MSK(i, pctype),
10125                                                     mask_reg[i]);
10126                                 i40e_check_write_global_reg(hw,
10127                                                   I40E_GLQF_HASH_MSK(i, pctype),
10128                                                   mask_reg[i]);
10129                         }
10130                         /*clear unused mask registers of the pctype */
10131                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10132                                 i40e_check_write_global_reg(hw,
10133                                                     I40E_GLQF_FD_MSK(i, pctype),
10134                                                     0);
10135                                 i40e_check_write_global_reg(hw,
10136                                                   I40E_GLQF_HASH_MSK(i, pctype),
10137                                                   0);
10138                         }
10139                 } else {
10140                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10141                 }
10142                 I40E_WRITE_FLUSH(hw);
10143
10144                 /* store the default input set */
10145                 if (!pf->support_multi_driver)
10146                         pf->hash_input_set[pctype] = input_set;
10147                 pf->fdir.input_set[pctype] = input_set;
10148         }
10149 }
10150
10151 int
10152 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10153                          struct rte_eth_input_set_conf *conf)
10154 {
10155         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10156         enum i40e_filter_pctype pctype;
10157         uint64_t input_set, inset_reg = 0;
10158         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10159         int ret, i, num;
10160
10161         if (!conf) {
10162                 PMD_DRV_LOG(ERR, "Invalid pointer");
10163                 return -EFAULT;
10164         }
10165         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10166             conf->op != RTE_ETH_INPUT_SET_ADD) {
10167                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10168                 return -EINVAL;
10169         }
10170
10171         if (pf->support_multi_driver) {
10172                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10173                 return -ENOTSUP;
10174         }
10175
10176         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10177         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10178                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10179                 return -EINVAL;
10180         }
10181
10182         if (hw->mac.type == I40E_MAC_X722) {
10183                 /* get translated pctype value in fd pctype register */
10184                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10185                         I40E_GLQF_FD_PCTYPES((int)pctype));
10186         }
10187
10188         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10189                                    conf->inset_size);
10190         if (ret) {
10191                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10192                 return -EINVAL;
10193         }
10194
10195         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10196                 /* get inset value in register */
10197                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10198                 inset_reg <<= I40E_32_BIT_WIDTH;
10199                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10200                 input_set |= pf->hash_input_set[pctype];
10201         }
10202         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10203                                            I40E_INSET_MASK_NUM_REG);
10204         if (num < 0)
10205                 return -EINVAL;
10206
10207         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10208
10209         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10210                                     (uint32_t)(inset_reg & UINT32_MAX));
10211         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10212                                     (uint32_t)((inset_reg >>
10213                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
10214
10215         for (i = 0; i < num; i++)
10216                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10217                                             mask_reg[i]);
10218         /*clear unused mask registers of the pctype */
10219         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10220                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10221                                             0);
10222         I40E_WRITE_FLUSH(hw);
10223
10224         pf->hash_input_set[pctype] = input_set;
10225         return 0;
10226 }
10227
10228 int
10229 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10230                          struct rte_eth_input_set_conf *conf)
10231 {
10232         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10233         enum i40e_filter_pctype pctype;
10234         uint64_t input_set, inset_reg = 0;
10235         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10236         int ret, i, num;
10237
10238         if (!hw || !conf) {
10239                 PMD_DRV_LOG(ERR, "Invalid pointer");
10240                 return -EFAULT;
10241         }
10242         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10243             conf->op != RTE_ETH_INPUT_SET_ADD) {
10244                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10245                 return -EINVAL;
10246         }
10247
10248         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10249
10250         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10251                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10252                 return -EINVAL;
10253         }
10254
10255         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10256                                    conf->inset_size);
10257         if (ret) {
10258                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10259                 return -EINVAL;
10260         }
10261
10262         /* get inset value in register */
10263         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10264         inset_reg <<= I40E_32_BIT_WIDTH;
10265         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10266
10267         /* Can not change the inset reg for flex payload for fdir,
10268          * it is done by writing I40E_PRTQF_FD_FLXINSET
10269          * in i40e_set_flex_mask_on_pctype.
10270          */
10271         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10272                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10273         else
10274                 input_set |= pf->fdir.input_set[pctype];
10275         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10276                                            I40E_INSET_MASK_NUM_REG);
10277         if (num < 0)
10278                 return -EINVAL;
10279         if (pf->support_multi_driver && num > 0) {
10280                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10281                 return -ENOTSUP;
10282         }
10283
10284         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10285
10286         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10287                               (uint32_t)(inset_reg & UINT32_MAX));
10288         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10289                              (uint32_t)((inset_reg >>
10290                              I40E_32_BIT_WIDTH) & UINT32_MAX));
10291
10292         if (!pf->support_multi_driver) {
10293                 for (i = 0; i < num; i++)
10294                         i40e_check_write_global_reg(hw,
10295                                                     I40E_GLQF_FD_MSK(i, pctype),
10296                                                     mask_reg[i]);
10297                 /*clear unused mask registers of the pctype */
10298                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10299                         i40e_check_write_global_reg(hw,
10300                                                     I40E_GLQF_FD_MSK(i, pctype),
10301                                                     0);
10302         } else {
10303                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10304         }
10305         I40E_WRITE_FLUSH(hw);
10306
10307         pf->fdir.input_set[pctype] = input_set;
10308         return 0;
10309 }
10310
10311 static int
10312 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10313 {
10314         int ret = 0;
10315
10316         if (!hw || !info) {
10317                 PMD_DRV_LOG(ERR, "Invalid pointer");
10318                 return -EFAULT;
10319         }
10320
10321         switch (info->info_type) {
10322         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10323                 i40e_get_symmetric_hash_enable_per_port(hw,
10324                                         &(info->info.enable));
10325                 break;
10326         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10327                 ret = i40e_get_hash_filter_global_config(hw,
10328                                 &(info->info.global_conf));
10329                 break;
10330         default:
10331                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10332                                                         info->info_type);
10333                 ret = -EINVAL;
10334                 break;
10335         }
10336
10337         return ret;
10338 }
10339
10340 static int
10341 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10342 {
10343         int ret = 0;
10344
10345         if (!hw || !info) {
10346                 PMD_DRV_LOG(ERR, "Invalid pointer");
10347                 return -EFAULT;
10348         }
10349
10350         switch (info->info_type) {
10351         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10352                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10353                 break;
10354         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10355                 ret = i40e_set_hash_filter_global_config(hw,
10356                                 &(info->info.global_conf));
10357                 break;
10358         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10359                 ret = i40e_hash_filter_inset_select(hw,
10360                                                &(info->info.input_set_conf));
10361                 break;
10362
10363         default:
10364                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10365                                                         info->info_type);
10366                 ret = -EINVAL;
10367                 break;
10368         }
10369
10370         return ret;
10371 }
10372
10373 /* Operations for hash function */
10374 static int
10375 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10376                       enum rte_filter_op filter_op,
10377                       void *arg)
10378 {
10379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10380         int ret = 0;
10381
10382         switch (filter_op) {
10383         case RTE_ETH_FILTER_NOP:
10384                 break;
10385         case RTE_ETH_FILTER_GET:
10386                 ret = i40e_hash_filter_get(hw,
10387                         (struct rte_eth_hash_filter_info *)arg);
10388                 break;
10389         case RTE_ETH_FILTER_SET:
10390                 ret = i40e_hash_filter_set(hw,
10391                         (struct rte_eth_hash_filter_info *)arg);
10392                 break;
10393         default:
10394                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10395                                                                 filter_op);
10396                 ret = -ENOTSUP;
10397                 break;
10398         }
10399
10400         return ret;
10401 }
10402
10403 /* Convert ethertype filter structure */
10404 static int
10405 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10406                               struct i40e_ethertype_filter *filter)
10407 {
10408         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10409                 RTE_ETHER_ADDR_LEN);
10410         filter->input.ether_type = input->ether_type;
10411         filter->flags = input->flags;
10412         filter->queue = input->queue;
10413
10414         return 0;
10415 }
10416
10417 /* Check if there exists the ehtertype filter */
10418 struct i40e_ethertype_filter *
10419 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10420                                 const struct i40e_ethertype_filter_input *input)
10421 {
10422         int ret;
10423
10424         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10425         if (ret < 0)
10426                 return NULL;
10427
10428         return ethertype_rule->hash_map[ret];
10429 }
10430
10431 /* Add ethertype filter in SW list */
10432 static int
10433 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10434                                 struct i40e_ethertype_filter *filter)
10435 {
10436         struct i40e_ethertype_rule *rule = &pf->ethertype;
10437         int ret;
10438
10439         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10440         if (ret < 0) {
10441                 PMD_DRV_LOG(ERR,
10442                             "Failed to insert ethertype filter"
10443                             " to hash table %d!",
10444                             ret);
10445                 return ret;
10446         }
10447         rule->hash_map[ret] = filter;
10448
10449         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10450
10451         return 0;
10452 }
10453
10454 /* Delete ethertype filter in SW list */
10455 int
10456 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10457                              struct i40e_ethertype_filter_input *input)
10458 {
10459         struct i40e_ethertype_rule *rule = &pf->ethertype;
10460         struct i40e_ethertype_filter *filter;
10461         int ret;
10462
10463         ret = rte_hash_del_key(rule->hash_table, input);
10464         if (ret < 0) {
10465                 PMD_DRV_LOG(ERR,
10466                             "Failed to delete ethertype filter"
10467                             " to hash table %d!",
10468                             ret);
10469                 return ret;
10470         }
10471         filter = rule->hash_map[ret];
10472         rule->hash_map[ret] = NULL;
10473
10474         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10475         rte_free(filter);
10476
10477         return 0;
10478 }
10479
10480 /*
10481  * Configure ethertype filter, which can director packet by filtering
10482  * with mac address and ether_type or only ether_type
10483  */
10484 int
10485 i40e_ethertype_filter_set(struct i40e_pf *pf,
10486                         struct rte_eth_ethertype_filter *filter,
10487                         bool add)
10488 {
10489         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10490         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10491         struct i40e_ethertype_filter *ethertype_filter, *node;
10492         struct i40e_ethertype_filter check_filter;
10493         struct i40e_control_filter_stats stats;
10494         uint16_t flags = 0;
10495         int ret;
10496
10497         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10498                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10499                 return -EINVAL;
10500         }
10501         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10502                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10503                 PMD_DRV_LOG(ERR,
10504                         "unsupported ether_type(0x%04x) in control packet filter.",
10505                         filter->ether_type);
10506                 return -EINVAL;
10507         }
10508         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10509                 PMD_DRV_LOG(WARNING,
10510                         "filter vlan ether_type in first tag is not supported.");
10511
10512         /* Check if there is the filter in SW list */
10513         memset(&check_filter, 0, sizeof(check_filter));
10514         i40e_ethertype_filter_convert(filter, &check_filter);
10515         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10516                                                &check_filter.input);
10517         if (add && node) {
10518                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10519                 return -EINVAL;
10520         }
10521
10522         if (!add && !node) {
10523                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10524                 return -EINVAL;
10525         }
10526
10527         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10528                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10529         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10530                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10531         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10532
10533         memset(&stats, 0, sizeof(stats));
10534         ret = i40e_aq_add_rem_control_packet_filter(hw,
10535                         filter->mac_addr.addr_bytes,
10536                         filter->ether_type, flags,
10537                         pf->main_vsi->seid,
10538                         filter->queue, add, &stats, NULL);
10539
10540         PMD_DRV_LOG(INFO,
10541                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10542                 ret, stats.mac_etype_used, stats.etype_used,
10543                 stats.mac_etype_free, stats.etype_free);
10544         if (ret < 0)
10545                 return -ENOSYS;
10546
10547         /* Add or delete a filter in SW list */
10548         if (add) {
10549                 ethertype_filter = rte_zmalloc("ethertype_filter",
10550                                        sizeof(*ethertype_filter), 0);
10551                 if (ethertype_filter == NULL) {
10552                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10553                         return -ENOMEM;
10554                 }
10555
10556                 rte_memcpy(ethertype_filter, &check_filter,
10557                            sizeof(check_filter));
10558                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10559                 if (ret < 0)
10560                         rte_free(ethertype_filter);
10561         } else {
10562                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10563         }
10564
10565         return ret;
10566 }
10567
10568 /*
10569  * Handle operations for ethertype filter.
10570  */
10571 static int
10572 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10573                                 enum rte_filter_op filter_op,
10574                                 void *arg)
10575 {
10576         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10577         int ret = 0;
10578
10579         if (filter_op == RTE_ETH_FILTER_NOP)
10580                 return ret;
10581
10582         if (arg == NULL) {
10583                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10584                             filter_op);
10585                 return -EINVAL;
10586         }
10587
10588         switch (filter_op) {
10589         case RTE_ETH_FILTER_ADD:
10590                 ret = i40e_ethertype_filter_set(pf,
10591                         (struct rte_eth_ethertype_filter *)arg,
10592                         TRUE);
10593                 break;
10594         case RTE_ETH_FILTER_DELETE:
10595                 ret = i40e_ethertype_filter_set(pf,
10596                         (struct rte_eth_ethertype_filter *)arg,
10597                         FALSE);
10598                 break;
10599         default:
10600                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10601                 ret = -ENOSYS;
10602                 break;
10603         }
10604         return ret;
10605 }
10606
10607 static int
10608 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10609                      enum rte_filter_type filter_type,
10610                      enum rte_filter_op filter_op,
10611                      void *arg)
10612 {
10613         int ret = 0;
10614
10615         if (dev == NULL)
10616                 return -EINVAL;
10617
10618         switch (filter_type) {
10619         case RTE_ETH_FILTER_NONE:
10620                 /* For global configuration */
10621                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10622                 break;
10623         case RTE_ETH_FILTER_HASH:
10624                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10625                 break;
10626         case RTE_ETH_FILTER_MACVLAN:
10627                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10628                 break;
10629         case RTE_ETH_FILTER_ETHERTYPE:
10630                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10631                 break;
10632         case RTE_ETH_FILTER_TUNNEL:
10633                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10634                 break;
10635         case RTE_ETH_FILTER_FDIR:
10636                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10637                 break;
10638         case RTE_ETH_FILTER_GENERIC:
10639                 if (filter_op != RTE_ETH_FILTER_GET)
10640                         return -EINVAL;
10641                 *(const void **)arg = &i40e_flow_ops;
10642                 break;
10643         default:
10644                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10645                                                         filter_type);
10646                 ret = -EINVAL;
10647                 break;
10648         }
10649
10650         return ret;
10651 }
10652
10653 /*
10654  * Check and enable Extended Tag.
10655  * Enabling Extended Tag is important for 40G performance.
10656  */
10657 static void
10658 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10659 {
10660         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10661         uint32_t buf = 0;
10662         int ret;
10663
10664         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10665                                       PCI_DEV_CAP_REG);
10666         if (ret < 0) {
10667                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10668                             PCI_DEV_CAP_REG);
10669                 return;
10670         }
10671         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10672                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10673                 return;
10674         }
10675
10676         buf = 0;
10677         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10678                                       PCI_DEV_CTRL_REG);
10679         if (ret < 0) {
10680                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10681                             PCI_DEV_CTRL_REG);
10682                 return;
10683         }
10684         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10685                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10686                 return;
10687         }
10688         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10689         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10690                                        PCI_DEV_CTRL_REG);
10691         if (ret < 0) {
10692                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10693                             PCI_DEV_CTRL_REG);
10694                 return;
10695         }
10696 }
10697
10698 /*
10699  * As some registers wouldn't be reset unless a global hardware reset,
10700  * hardware initialization is needed to put those registers into an
10701  * expected initial state.
10702  */
10703 static void
10704 i40e_hw_init(struct rte_eth_dev *dev)
10705 {
10706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10707
10708         i40e_enable_extended_tag(dev);
10709
10710         /* clear the PF Queue Filter control register */
10711         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10712
10713         /* Disable symmetric hash per port */
10714         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10715 }
10716
10717 /*
10718  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10719  * however this function will return only one highest pctype index,
10720  * which is not quite correct. This is known problem of i40e driver
10721  * and needs to be fixed later.
10722  */
10723 enum i40e_filter_pctype
10724 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10725 {
10726         int i;
10727         uint64_t pctype_mask;
10728
10729         if (flow_type < I40E_FLOW_TYPE_MAX) {
10730                 pctype_mask = adapter->pctypes_tbl[flow_type];
10731                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10732                         if (pctype_mask & (1ULL << i))
10733                                 return (enum i40e_filter_pctype)i;
10734                 }
10735         }
10736         return I40E_FILTER_PCTYPE_INVALID;
10737 }
10738
10739 uint16_t
10740 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10741                         enum i40e_filter_pctype pctype)
10742 {
10743         uint16_t flowtype;
10744         uint64_t pctype_mask = 1ULL << pctype;
10745
10746         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10747              flowtype++) {
10748                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10749                         return flowtype;
10750         }
10751
10752         return RTE_ETH_FLOW_UNKNOWN;
10753 }
10754
10755 /*
10756  * On X710, performance number is far from the expectation on recent firmware
10757  * versions; on XL710, performance number is also far from the expectation on
10758  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10759  * mode is enabled and port MAC address is equal to the packet destination MAC
10760  * address. The fix for this issue may not be integrated in the following
10761  * firmware version. So the workaround in software driver is needed. It needs
10762  * to modify the initial values of 3 internal only registers for both X710 and
10763  * XL710. Note that the values for X710 or XL710 could be different, and the
10764  * workaround can be removed when it is fixed in firmware in the future.
10765  */
10766
10767 /* For both X710 and XL710 */
10768 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10769 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10770 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10771
10772 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10773 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10774
10775 /* For X722 */
10776 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10777 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10778
10779 /* For X710 */
10780 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10781 /* For XL710 */
10782 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10783 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10784
10785 /*
10786  * GL_SWR_PM_UP_THR:
10787  * The value is not impacted from the link speed, its value is set according
10788  * to the total number of ports for a better pipe-monitor configuration.
10789  */
10790 static bool
10791 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10792 {
10793 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10794                 .device_id = (dev),   \
10795                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10796
10797 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10798                 .device_id = (dev),   \
10799                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10800
10801         static const struct {
10802                 uint16_t device_id;
10803                 uint32_t val;
10804         } swr_pm_table[] = {
10805                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10806                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10807                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10808                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10809                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10810
10811                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10812                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10813                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10814                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10815                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10816                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10817                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10818         };
10819         uint32_t i;
10820
10821         if (value == NULL) {
10822                 PMD_DRV_LOG(ERR, "value is NULL");
10823                 return false;
10824         }
10825
10826         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10827                 if (hw->device_id == swr_pm_table[i].device_id) {
10828                         *value = swr_pm_table[i].val;
10829
10830                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10831                                     "value - 0x%08x",
10832                                     hw->device_id, *value);
10833                         return true;
10834                 }
10835         }
10836
10837         return false;
10838 }
10839
10840 static int
10841 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10842 {
10843         enum i40e_status_code status;
10844         struct i40e_aq_get_phy_abilities_resp phy_ab;
10845         int ret = -ENOTSUP;
10846         int retries = 0;
10847
10848         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10849                                               NULL);
10850
10851         while (status) {
10852                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10853                         status);
10854                 retries++;
10855                 rte_delay_us(100000);
10856                 if  (retries < 5)
10857                         status = i40e_aq_get_phy_capabilities(hw, false,
10858                                         true, &phy_ab, NULL);
10859                 else
10860                         return ret;
10861         }
10862         return 0;
10863 }
10864
10865 static void
10866 i40e_configure_registers(struct i40e_hw *hw)
10867 {
10868         static struct {
10869                 uint32_t addr;
10870                 uint64_t val;
10871         } reg_table[] = {
10872                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10873                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10874                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10875         };
10876         uint64_t reg;
10877         uint32_t i;
10878         int ret;
10879
10880         for (i = 0; i < RTE_DIM(reg_table); i++) {
10881                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10882                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10883                                 reg_table[i].val =
10884                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10885                         else /* For X710/XL710/XXV710 */
10886                                 if (hw->aq.fw_maj_ver < 6)
10887                                         reg_table[i].val =
10888                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10889                                 else
10890                                         reg_table[i].val =
10891                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10892                 }
10893
10894                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10895                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10896                                 reg_table[i].val =
10897                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10898                         else /* For X710/XL710/XXV710 */
10899                                 reg_table[i].val =
10900                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10901                 }
10902
10903                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10904                         uint32_t cfg_val;
10905
10906                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10907                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10908                                             "GL_SWR_PM_UP_THR value fixup",
10909                                             hw->device_id);
10910                                 continue;
10911                         }
10912
10913                         reg_table[i].val = cfg_val;
10914                 }
10915
10916                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10917                                                         &reg, NULL);
10918                 if (ret < 0) {
10919                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10920                                                         reg_table[i].addr);
10921                         break;
10922                 }
10923                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10924                                                 reg_table[i].addr, reg);
10925                 if (reg == reg_table[i].val)
10926                         continue;
10927
10928                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10929                                                 reg_table[i].val, NULL);
10930                 if (ret < 0) {
10931                         PMD_DRV_LOG(ERR,
10932                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10933                                 reg_table[i].val, reg_table[i].addr);
10934                         break;
10935                 }
10936                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10937                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10938         }
10939 }
10940
10941 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10942 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10943 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10944 static int
10945 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10946 {
10947         uint32_t reg;
10948         int ret;
10949
10950         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10951                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10952                 return -EINVAL;
10953         }
10954
10955         /* Configure for double VLAN RX stripping */
10956         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10957         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10958                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10959                 ret = i40e_aq_debug_write_register(hw,
10960                                                    I40E_VSI_TSR(vsi->vsi_id),
10961                                                    reg, NULL);
10962                 if (ret < 0) {
10963                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10964                                     vsi->vsi_id);
10965                         return I40E_ERR_CONFIG;
10966                 }
10967         }
10968
10969         /* Configure for double VLAN TX insertion */
10970         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10971         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10972                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10973                 ret = i40e_aq_debug_write_register(hw,
10974                                                    I40E_VSI_L2TAGSTXVALID(
10975                                                    vsi->vsi_id), reg, NULL);
10976                 if (ret < 0) {
10977                         PMD_DRV_LOG(ERR,
10978                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10979                                 vsi->vsi_id);
10980                         return I40E_ERR_CONFIG;
10981                 }
10982         }
10983
10984         return 0;
10985 }
10986
10987 /**
10988  * i40e_aq_add_mirror_rule
10989  * @hw: pointer to the hardware structure
10990  * @seid: VEB seid to add mirror rule to
10991  * @dst_id: destination vsi seid
10992  * @entries: Buffer which contains the entities to be mirrored
10993  * @count: number of entities contained in the buffer
10994  * @rule_id:the rule_id of the rule to be added
10995  *
10996  * Add a mirror rule for a given veb.
10997  *
10998  **/
10999 static enum i40e_status_code
11000 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
11001                         uint16_t seid, uint16_t dst_id,
11002                         uint16_t rule_type, uint16_t *entries,
11003                         uint16_t count, uint16_t *rule_id)
11004 {
11005         struct i40e_aq_desc desc;
11006         struct i40e_aqc_add_delete_mirror_rule cmd;
11007         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
11008                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
11009                 &desc.params.raw;
11010         uint16_t buff_len;
11011         enum i40e_status_code status;
11012
11013         i40e_fill_default_direct_cmd_desc(&desc,
11014                                           i40e_aqc_opc_add_mirror_rule);
11015         memset(&cmd, 0, sizeof(cmd));
11016
11017         buff_len = sizeof(uint16_t) * count;
11018         desc.datalen = rte_cpu_to_le_16(buff_len);
11019         if (buff_len > 0)
11020                 desc.flags |= rte_cpu_to_le_16(
11021                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
11022         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11023                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11024         cmd.num_entries = rte_cpu_to_le_16(count);
11025         cmd.seid = rte_cpu_to_le_16(seid);
11026         cmd.destination = rte_cpu_to_le_16(dst_id);
11027
11028         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11029         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
11030         PMD_DRV_LOG(INFO,
11031                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
11032                 hw->aq.asq_last_status, resp->rule_id,
11033                 resp->mirror_rules_used, resp->mirror_rules_free);
11034         *rule_id = rte_le_to_cpu_16(resp->rule_id);
11035
11036         return status;
11037 }
11038
11039 /**
11040  * i40e_aq_del_mirror_rule
11041  * @hw: pointer to the hardware structure
11042  * @seid: VEB seid to add mirror rule to
11043  * @entries: Buffer which contains the entities to be mirrored
11044  * @count: number of entities contained in the buffer
11045  * @rule_id:the rule_id of the rule to be delete
11046  *
11047  * Delete a mirror rule for a given veb.
11048  *
11049  **/
11050 static enum i40e_status_code
11051 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
11052                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
11053                 uint16_t count, uint16_t rule_id)
11054 {
11055         struct i40e_aq_desc desc;
11056         struct i40e_aqc_add_delete_mirror_rule cmd;
11057         uint16_t buff_len = 0;
11058         enum i40e_status_code status;
11059         void *buff = NULL;
11060
11061         i40e_fill_default_direct_cmd_desc(&desc,
11062                                           i40e_aqc_opc_delete_mirror_rule);
11063         memset(&cmd, 0, sizeof(cmd));
11064         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11065                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11066                                                           I40E_AQ_FLAG_RD));
11067                 cmd.num_entries = count;
11068                 buff_len = sizeof(uint16_t) * count;
11069                 desc.datalen = rte_cpu_to_le_16(buff_len);
11070                 buff = (void *)entries;
11071         } else
11072                 /* rule id is filled in destination field for deleting mirror rule */
11073                 cmd.destination = rte_cpu_to_le_16(rule_id);
11074
11075         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11076                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11077         cmd.seid = rte_cpu_to_le_16(seid);
11078
11079         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11080         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11081
11082         return status;
11083 }
11084
11085 /**
11086  * i40e_mirror_rule_set
11087  * @dev: pointer to the hardware structure
11088  * @mirror_conf: mirror rule info
11089  * @sw_id: mirror rule's sw_id
11090  * @on: enable/disable
11091  *
11092  * set a mirror rule.
11093  *
11094  **/
11095 static int
11096 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11097                         struct rte_eth_mirror_conf *mirror_conf,
11098                         uint8_t sw_id, uint8_t on)
11099 {
11100         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11102         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11103         struct i40e_mirror_rule *parent = NULL;
11104         uint16_t seid, dst_seid, rule_id;
11105         uint16_t i, j = 0;
11106         int ret;
11107
11108         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11109
11110         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11111                 PMD_DRV_LOG(ERR,
11112                         "mirror rule can not be configured without veb or vfs.");
11113                 return -ENOSYS;
11114         }
11115         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11116                 PMD_DRV_LOG(ERR, "mirror table is full.");
11117                 return -ENOSPC;
11118         }
11119         if (mirror_conf->dst_pool > pf->vf_num) {
11120                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11121                                  mirror_conf->dst_pool);
11122                 return -EINVAL;
11123         }
11124
11125         seid = pf->main_vsi->veb->seid;
11126
11127         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11128                 if (sw_id <= it->index) {
11129                         mirr_rule = it;
11130                         break;
11131                 }
11132                 parent = it;
11133         }
11134         if (mirr_rule && sw_id == mirr_rule->index) {
11135                 if (on) {
11136                         PMD_DRV_LOG(ERR, "mirror rule exists.");
11137                         return -EEXIST;
11138                 } else {
11139                         ret = i40e_aq_del_mirror_rule(hw, seid,
11140                                         mirr_rule->rule_type,
11141                                         mirr_rule->entries,
11142                                         mirr_rule->num_entries, mirr_rule->id);
11143                         if (ret < 0) {
11144                                 PMD_DRV_LOG(ERR,
11145                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
11146                                         ret, hw->aq.asq_last_status);
11147                                 return -ENOSYS;
11148                         }
11149                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11150                         rte_free(mirr_rule);
11151                         pf->nb_mirror_rule--;
11152                         return 0;
11153                 }
11154         } else if (!on) {
11155                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11156                 return -ENOENT;
11157         }
11158
11159         mirr_rule = rte_zmalloc("i40e_mirror_rule",
11160                                 sizeof(struct i40e_mirror_rule) , 0);
11161         if (!mirr_rule) {
11162                 PMD_DRV_LOG(ERR, "failed to allocate memory");
11163                 return I40E_ERR_NO_MEMORY;
11164         }
11165         switch (mirror_conf->rule_type) {
11166         case ETH_MIRROR_VLAN:
11167                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11168                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11169                                 mirr_rule->entries[j] =
11170                                         mirror_conf->vlan.vlan_id[i];
11171                                 j++;
11172                         }
11173                 }
11174                 if (j == 0) {
11175                         PMD_DRV_LOG(ERR, "vlan is not specified.");
11176                         rte_free(mirr_rule);
11177                         return -EINVAL;
11178                 }
11179                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11180                 break;
11181         case ETH_MIRROR_VIRTUAL_POOL_UP:
11182         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11183                 /* check if the specified pool bit is out of range */
11184                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11185                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
11186                         rte_free(mirr_rule);
11187                         return -EINVAL;
11188                 }
11189                 for (i = 0, j = 0; i < pf->vf_num; i++) {
11190                         if (mirror_conf->pool_mask & (1ULL << i)) {
11191                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11192                                 j++;
11193                         }
11194                 }
11195                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11196                         /* add pf vsi to entries */
11197                         mirr_rule->entries[j] = pf->main_vsi_seid;
11198                         j++;
11199                 }
11200                 if (j == 0) {
11201                         PMD_DRV_LOG(ERR, "pool is not specified.");
11202                         rte_free(mirr_rule);
11203                         return -EINVAL;
11204                 }
11205                 /* egress and ingress in aq commands means from switch but not port */
11206                 mirr_rule->rule_type =
11207                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11208                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11209                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11210                 break;
11211         case ETH_MIRROR_UPLINK_PORT:
11212                 /* egress and ingress in aq commands means from switch but not port*/
11213                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11214                 break;
11215         case ETH_MIRROR_DOWNLINK_PORT:
11216                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11217                 break;
11218         default:
11219                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11220                         mirror_conf->rule_type);
11221                 rte_free(mirr_rule);
11222                 return -EINVAL;
11223         }
11224
11225         /* If the dst_pool is equal to vf_num, consider it as PF */
11226         if (mirror_conf->dst_pool == pf->vf_num)
11227                 dst_seid = pf->main_vsi_seid;
11228         else
11229                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11230
11231         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11232                                       mirr_rule->rule_type, mirr_rule->entries,
11233                                       j, &rule_id);
11234         if (ret < 0) {
11235                 PMD_DRV_LOG(ERR,
11236                         "failed to add mirror rule: ret = %d, aq_err = %d.",
11237                         ret, hw->aq.asq_last_status);
11238                 rte_free(mirr_rule);
11239                 return -ENOSYS;
11240         }
11241
11242         mirr_rule->index = sw_id;
11243         mirr_rule->num_entries = j;
11244         mirr_rule->id = rule_id;
11245         mirr_rule->dst_vsi_seid = dst_seid;
11246
11247         if (parent)
11248                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11249         else
11250                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11251
11252         pf->nb_mirror_rule++;
11253         return 0;
11254 }
11255
11256 /**
11257  * i40e_mirror_rule_reset
11258  * @dev: pointer to the device
11259  * @sw_id: mirror rule's sw_id
11260  *
11261  * reset a mirror rule.
11262  *
11263  **/
11264 static int
11265 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11266 {
11267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11268         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11269         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11270         uint16_t seid;
11271         int ret;
11272
11273         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11274
11275         seid = pf->main_vsi->veb->seid;
11276
11277         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11278                 if (sw_id == it->index) {
11279                         mirr_rule = it;
11280                         break;
11281                 }
11282         }
11283         if (mirr_rule) {
11284                 ret = i40e_aq_del_mirror_rule(hw, seid,
11285                                 mirr_rule->rule_type,
11286                                 mirr_rule->entries,
11287                                 mirr_rule->num_entries, mirr_rule->id);
11288                 if (ret < 0) {
11289                         PMD_DRV_LOG(ERR,
11290                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
11291                                 ret, hw->aq.asq_last_status);
11292                         return -ENOSYS;
11293                 }
11294                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11295                 rte_free(mirr_rule);
11296                 pf->nb_mirror_rule--;
11297         } else {
11298                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11299                 return -ENOENT;
11300         }
11301         return 0;
11302 }
11303
11304 static uint64_t
11305 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11306 {
11307         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11308         uint64_t systim_cycles;
11309
11310         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11311         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11312                         << 32;
11313
11314         return systim_cycles;
11315 }
11316
11317 static uint64_t
11318 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11319 {
11320         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11321         uint64_t rx_tstamp;
11322
11323         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11324         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11325                         << 32;
11326
11327         return rx_tstamp;
11328 }
11329
11330 static uint64_t
11331 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11332 {
11333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11334         uint64_t tx_tstamp;
11335
11336         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11337         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11338                         << 32;
11339
11340         return tx_tstamp;
11341 }
11342
11343 static void
11344 i40e_start_timecounters(struct rte_eth_dev *dev)
11345 {
11346         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11347         struct i40e_adapter *adapter = dev->data->dev_private;
11348         struct rte_eth_link link;
11349         uint32_t tsync_inc_l;
11350         uint32_t tsync_inc_h;
11351
11352         /* Get current link speed. */
11353         i40e_dev_link_update(dev, 1);
11354         rte_eth_linkstatus_get(dev, &link);
11355
11356         switch (link.link_speed) {
11357         case ETH_SPEED_NUM_40G:
11358         case ETH_SPEED_NUM_25G:
11359                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11360                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11361                 break;
11362         case ETH_SPEED_NUM_10G:
11363                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11364                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11365                 break;
11366         case ETH_SPEED_NUM_1G:
11367                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11368                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11369                 break;
11370         default:
11371                 tsync_inc_l = 0x0;
11372                 tsync_inc_h = 0x0;
11373         }
11374
11375         /* Set the timesync increment value. */
11376         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11377         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11378
11379         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11380         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11381         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11382
11383         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11384         adapter->systime_tc.cc_shift = 0;
11385         adapter->systime_tc.nsec_mask = 0;
11386
11387         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11388         adapter->rx_tstamp_tc.cc_shift = 0;
11389         adapter->rx_tstamp_tc.nsec_mask = 0;
11390
11391         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11392         adapter->tx_tstamp_tc.cc_shift = 0;
11393         adapter->tx_tstamp_tc.nsec_mask = 0;
11394 }
11395
11396 static int
11397 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11398 {
11399         struct i40e_adapter *adapter = dev->data->dev_private;
11400
11401         adapter->systime_tc.nsec += delta;
11402         adapter->rx_tstamp_tc.nsec += delta;
11403         adapter->tx_tstamp_tc.nsec += delta;
11404
11405         return 0;
11406 }
11407
11408 static int
11409 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11410 {
11411         uint64_t ns;
11412         struct i40e_adapter *adapter = dev->data->dev_private;
11413
11414         ns = rte_timespec_to_ns(ts);
11415
11416         /* Set the timecounters to a new value. */
11417         adapter->systime_tc.nsec = ns;
11418         adapter->rx_tstamp_tc.nsec = ns;
11419         adapter->tx_tstamp_tc.nsec = ns;
11420
11421         return 0;
11422 }
11423
11424 static int
11425 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11426 {
11427         uint64_t ns, systime_cycles;
11428         struct i40e_adapter *adapter = dev->data->dev_private;
11429
11430         systime_cycles = i40e_read_systime_cyclecounter(dev);
11431         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11432         *ts = rte_ns_to_timespec(ns);
11433
11434         return 0;
11435 }
11436
11437 static int
11438 i40e_timesync_enable(struct rte_eth_dev *dev)
11439 {
11440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11441         uint32_t tsync_ctl_l;
11442         uint32_t tsync_ctl_h;
11443
11444         /* Stop the timesync system time. */
11445         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11446         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11447         /* Reset the timesync system time value. */
11448         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11449         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11450
11451         i40e_start_timecounters(dev);
11452
11453         /* Clear timesync registers. */
11454         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11455         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11456         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11457         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11458         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11459         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11460
11461         /* Enable timestamping of PTP packets. */
11462         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11463         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11464
11465         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11466         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11467         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11468
11469         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11470         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11471
11472         return 0;
11473 }
11474
11475 static int
11476 i40e_timesync_disable(struct rte_eth_dev *dev)
11477 {
11478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11479         uint32_t tsync_ctl_l;
11480         uint32_t tsync_ctl_h;
11481
11482         /* Disable timestamping of transmitted PTP packets. */
11483         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11484         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11485
11486         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11487         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11488
11489         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11490         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11491
11492         /* Reset the timesync increment value. */
11493         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11494         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11495
11496         return 0;
11497 }
11498
11499 static int
11500 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11501                                 struct timespec *timestamp, uint32_t flags)
11502 {
11503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11504         struct i40e_adapter *adapter = dev->data->dev_private;
11505         uint32_t sync_status;
11506         uint32_t index = flags & 0x03;
11507         uint64_t rx_tstamp_cycles;
11508         uint64_t ns;
11509
11510         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11511         if ((sync_status & (1 << index)) == 0)
11512                 return -EINVAL;
11513
11514         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11515         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11516         *timestamp = rte_ns_to_timespec(ns);
11517
11518         return 0;
11519 }
11520
11521 static int
11522 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11523                                 struct timespec *timestamp)
11524 {
11525         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11526         struct i40e_adapter *adapter = dev->data->dev_private;
11527         uint32_t sync_status;
11528         uint64_t tx_tstamp_cycles;
11529         uint64_t ns;
11530
11531         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11532         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11533                 return -EINVAL;
11534
11535         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11536         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11537         *timestamp = rte_ns_to_timespec(ns);
11538
11539         return 0;
11540 }
11541
11542 /*
11543  * i40e_parse_dcb_configure - parse dcb configure from user
11544  * @dev: the device being configured
11545  * @dcb_cfg: pointer of the result of parse
11546  * @*tc_map: bit map of enabled traffic classes
11547  *
11548  * Returns 0 on success, negative value on failure
11549  */
11550 static int
11551 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11552                          struct i40e_dcbx_config *dcb_cfg,
11553                          uint8_t *tc_map)
11554 {
11555         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11556         uint8_t i, tc_bw, bw_lf;
11557
11558         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11559
11560         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11561         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11562                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11563                 return -EINVAL;
11564         }
11565
11566         /* assume each tc has the same bw */
11567         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11568         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11569                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11570         /* to ensure the sum of tcbw is equal to 100 */
11571         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11572         for (i = 0; i < bw_lf; i++)
11573                 dcb_cfg->etscfg.tcbwtable[i]++;
11574
11575         /* assume each tc has the same Transmission Selection Algorithm */
11576         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11577                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11578
11579         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11580                 dcb_cfg->etscfg.prioritytable[i] =
11581                                 dcb_rx_conf->dcb_tc[i];
11582
11583         /* FW needs one App to configure HW */
11584         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11585         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11586         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11587         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11588
11589         if (dcb_rx_conf->nb_tcs == 0)
11590                 *tc_map = 1; /* tc0 only */
11591         else
11592                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11593
11594         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11595                 dcb_cfg->pfc.willing = 0;
11596                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11597                 dcb_cfg->pfc.pfcenable = *tc_map;
11598         }
11599         return 0;
11600 }
11601
11602
11603 static enum i40e_status_code
11604 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11605                               struct i40e_aqc_vsi_properties_data *info,
11606                               uint8_t enabled_tcmap)
11607 {
11608         enum i40e_status_code ret;
11609         int i, total_tc = 0;
11610         uint16_t qpnum_per_tc, bsf, qp_idx;
11611         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11612         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11613         uint16_t used_queues;
11614
11615         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11616         if (ret != I40E_SUCCESS)
11617                 return ret;
11618
11619         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11620                 if (enabled_tcmap & (1 << i))
11621                         total_tc++;
11622         }
11623         if (total_tc == 0)
11624                 total_tc = 1;
11625         vsi->enabled_tc = enabled_tcmap;
11626
11627         /* different VSI has different queues assigned */
11628         if (vsi->type == I40E_VSI_MAIN)
11629                 used_queues = dev_data->nb_rx_queues -
11630                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11631         else if (vsi->type == I40E_VSI_VMDQ2)
11632                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11633         else {
11634                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11635                 return I40E_ERR_NO_AVAILABLE_VSI;
11636         }
11637
11638         qpnum_per_tc = used_queues / total_tc;
11639         /* Number of queues per enabled TC */
11640         if (qpnum_per_tc == 0) {
11641                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11642                 return I40E_ERR_INVALID_QP_ID;
11643         }
11644         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11645                                 I40E_MAX_Q_PER_TC);
11646         bsf = rte_bsf32(qpnum_per_tc);
11647
11648         /**
11649          * Configure TC and queue mapping parameters, for enabled TC,
11650          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11651          * default queue will serve it.
11652          */
11653         qp_idx = 0;
11654         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11655                 if (vsi->enabled_tc & (1 << i)) {
11656                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11657                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11658                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11659                         qp_idx += qpnum_per_tc;
11660                 } else
11661                         info->tc_mapping[i] = 0;
11662         }
11663
11664         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11665         if (vsi->type == I40E_VSI_SRIOV) {
11666                 info->mapping_flags |=
11667                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11668                 for (i = 0; i < vsi->nb_qps; i++)
11669                         info->queue_mapping[i] =
11670                                 rte_cpu_to_le_16(vsi->base_queue + i);
11671         } else {
11672                 info->mapping_flags |=
11673                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11674                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11675         }
11676         info->valid_sections |=
11677                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11678
11679         return I40E_SUCCESS;
11680 }
11681
11682 /*
11683  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11684  * @veb: VEB to be configured
11685  * @tc_map: enabled TC bitmap
11686  *
11687  * Returns 0 on success, negative value on failure
11688  */
11689 static enum i40e_status_code
11690 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11691 {
11692         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11693         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11694         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11695         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11696         enum i40e_status_code ret = I40E_SUCCESS;
11697         int i;
11698         uint32_t bw_max;
11699
11700         /* Check if enabled_tc is same as existing or new TCs */
11701         if (veb->enabled_tc == tc_map)
11702                 return ret;
11703
11704         /* configure tc bandwidth */
11705         memset(&veb_bw, 0, sizeof(veb_bw));
11706         veb_bw.tc_valid_bits = tc_map;
11707         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11708         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11709                 if (tc_map & BIT_ULL(i))
11710                         veb_bw.tc_bw_share_credits[i] = 1;
11711         }
11712         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11713                                                    &veb_bw, NULL);
11714         if (ret) {
11715                 PMD_INIT_LOG(ERR,
11716                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11717                         hw->aq.asq_last_status);
11718                 return ret;
11719         }
11720
11721         memset(&ets_query, 0, sizeof(ets_query));
11722         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11723                                                    &ets_query, NULL);
11724         if (ret != I40E_SUCCESS) {
11725                 PMD_DRV_LOG(ERR,
11726                         "Failed to get switch_comp ETS configuration %u",
11727                         hw->aq.asq_last_status);
11728                 return ret;
11729         }
11730         memset(&bw_query, 0, sizeof(bw_query));
11731         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11732                                                   &bw_query, NULL);
11733         if (ret != I40E_SUCCESS) {
11734                 PMD_DRV_LOG(ERR,
11735                         "Failed to get switch_comp bandwidth configuration %u",
11736                         hw->aq.asq_last_status);
11737                 return ret;
11738         }
11739
11740         /* store and print out BW info */
11741         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11742         veb->bw_info.bw_max = ets_query.tc_bw_max;
11743         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11744         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11745         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11746                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11747                      I40E_16_BIT_WIDTH);
11748         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11749                 veb->bw_info.bw_ets_share_credits[i] =
11750                                 bw_query.tc_bw_share_credits[i];
11751                 veb->bw_info.bw_ets_credits[i] =
11752                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11753                 /* 4 bits per TC, 4th bit is reserved */
11754                 veb->bw_info.bw_ets_max[i] =
11755                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11756                                   RTE_LEN2MASK(3, uint8_t));
11757                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11758                             veb->bw_info.bw_ets_share_credits[i]);
11759                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11760                             veb->bw_info.bw_ets_credits[i]);
11761                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11762                             veb->bw_info.bw_ets_max[i]);
11763         }
11764
11765         veb->enabled_tc = tc_map;
11766
11767         return ret;
11768 }
11769
11770
11771 /*
11772  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11773  * @vsi: VSI to be configured
11774  * @tc_map: enabled TC bitmap
11775  *
11776  * Returns 0 on success, negative value on failure
11777  */
11778 static enum i40e_status_code
11779 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11780 {
11781         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11782         struct i40e_vsi_context ctxt;
11783         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11784         enum i40e_status_code ret = I40E_SUCCESS;
11785         int i;
11786
11787         /* Check if enabled_tc is same as existing or new TCs */
11788         if (vsi->enabled_tc == tc_map)
11789                 return ret;
11790
11791         /* configure tc bandwidth */
11792         memset(&bw_data, 0, sizeof(bw_data));
11793         bw_data.tc_valid_bits = tc_map;
11794         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11795         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11796                 if (tc_map & BIT_ULL(i))
11797                         bw_data.tc_bw_credits[i] = 1;
11798         }
11799         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11800         if (ret) {
11801                 PMD_INIT_LOG(ERR,
11802                         "AQ command Config VSI BW allocation per TC failed = %d",
11803                         hw->aq.asq_last_status);
11804                 goto out;
11805         }
11806         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11807                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11808
11809         /* Update Queue Pairs Mapping for currently enabled UPs */
11810         ctxt.seid = vsi->seid;
11811         ctxt.pf_num = hw->pf_id;
11812         ctxt.vf_num = 0;
11813         ctxt.uplink_seid = vsi->uplink_seid;
11814         ctxt.info = vsi->info;
11815         i40e_get_cap(hw);
11816         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11817         if (ret)
11818                 goto out;
11819
11820         /* Update the VSI after updating the VSI queue-mapping information */
11821         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11822         if (ret) {
11823                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11824                         hw->aq.asq_last_status);
11825                 goto out;
11826         }
11827         /* update the local VSI info with updated queue map */
11828         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11829                                         sizeof(vsi->info.tc_mapping));
11830         rte_memcpy(&vsi->info.queue_mapping,
11831                         &ctxt.info.queue_mapping,
11832                 sizeof(vsi->info.queue_mapping));
11833         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11834         vsi->info.valid_sections = 0;
11835
11836         /* query and update current VSI BW information */
11837         ret = i40e_vsi_get_bw_config(vsi);
11838         if (ret) {
11839                 PMD_INIT_LOG(ERR,
11840                          "Failed updating vsi bw info, err %s aq_err %s",
11841                          i40e_stat_str(hw, ret),
11842                          i40e_aq_str(hw, hw->aq.asq_last_status));
11843                 goto out;
11844         }
11845
11846         vsi->enabled_tc = tc_map;
11847
11848 out:
11849         return ret;
11850 }
11851
11852 /*
11853  * i40e_dcb_hw_configure - program the dcb setting to hw
11854  * @pf: pf the configuration is taken on
11855  * @new_cfg: new configuration
11856  * @tc_map: enabled TC bitmap
11857  *
11858  * Returns 0 on success, negative value on failure
11859  */
11860 static enum i40e_status_code
11861 i40e_dcb_hw_configure(struct i40e_pf *pf,
11862                       struct i40e_dcbx_config *new_cfg,
11863                       uint8_t tc_map)
11864 {
11865         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11866         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11867         struct i40e_vsi *main_vsi = pf->main_vsi;
11868         struct i40e_vsi_list *vsi_list;
11869         enum i40e_status_code ret;
11870         int i;
11871         uint32_t val;
11872
11873         /* Use the FW API if FW > v4.4*/
11874         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11875               (hw->aq.fw_maj_ver >= 5))) {
11876                 PMD_INIT_LOG(ERR,
11877                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11878                 return I40E_ERR_FIRMWARE_API_VERSION;
11879         }
11880
11881         /* Check if need reconfiguration */
11882         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11883                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11884                 return I40E_SUCCESS;
11885         }
11886
11887         /* Copy the new config to the current config */
11888         *old_cfg = *new_cfg;
11889         old_cfg->etsrec = old_cfg->etscfg;
11890         ret = i40e_set_dcb_config(hw);
11891         if (ret) {
11892                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11893                          i40e_stat_str(hw, ret),
11894                          i40e_aq_str(hw, hw->aq.asq_last_status));
11895                 return ret;
11896         }
11897         /* set receive Arbiter to RR mode and ETS scheme by default */
11898         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11899                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11900                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11901                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11902                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11903                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11904                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11905                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11906                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11907                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11908                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11909                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11910                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11911         }
11912         /* get local mib to check whether it is configured correctly */
11913         /* IEEE mode */
11914         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11915         /* Get Local DCB Config */
11916         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11917                                      &hw->local_dcbx_config);
11918
11919         /* if Veb is created, need to update TC of it at first */
11920         if (main_vsi->veb) {
11921                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11922                 if (ret)
11923                         PMD_INIT_LOG(WARNING,
11924                                  "Failed configuring TC for VEB seid=%d",
11925                                  main_vsi->veb->seid);
11926         }
11927         /* Update each VSI */
11928         i40e_vsi_config_tc(main_vsi, tc_map);
11929         if (main_vsi->veb) {
11930                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11931                         /* Beside main VSI and VMDQ VSIs, only enable default
11932                          * TC for other VSIs
11933                          */
11934                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11935                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11936                                                          tc_map);
11937                         else
11938                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11939                                                          I40E_DEFAULT_TCMAP);
11940                         if (ret)
11941                                 PMD_INIT_LOG(WARNING,
11942                                         "Failed configuring TC for VSI seid=%d",
11943                                         vsi_list->vsi->seid);
11944                         /* continue */
11945                 }
11946         }
11947         return I40E_SUCCESS;
11948 }
11949
11950 /*
11951  * i40e_dcb_init_configure - initial dcb config
11952  * @dev: device being configured
11953  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11954  *
11955  * Returns 0 on success, negative value on failure
11956  */
11957 int
11958 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11959 {
11960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11962         int i, ret = 0;
11963
11964         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11965                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11966                 return -ENOTSUP;
11967         }
11968
11969         /* DCB initialization:
11970          * Update DCB configuration from the Firmware and configure
11971          * LLDP MIB change event.
11972          */
11973         if (sw_dcb == TRUE) {
11974                 /* Stopping lldp is necessary for DPDK, but it will cause
11975                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11976                  * for successful initialization of DCB is that LLDP is
11977                  * enabled. So it is needed to start lldp before DCB init
11978                  * and stop it after initialization.
11979                  */
11980                 ret = i40e_aq_start_lldp(hw, true, NULL);
11981                 if (ret != I40E_SUCCESS)
11982                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11983
11984                 ret = i40e_init_dcb(hw, true);
11985                 /* If lldp agent is stopped, the return value from
11986                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11987                  * adminq status. Otherwise, it should return success.
11988                  */
11989                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11990                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11991                         memset(&hw->local_dcbx_config, 0,
11992                                 sizeof(struct i40e_dcbx_config));
11993                         /* set dcb default configuration */
11994                         hw->local_dcbx_config.etscfg.willing = 0;
11995                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11996                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11997                         hw->local_dcbx_config.etscfg.tsatable[0] =
11998                                                 I40E_IEEE_TSA_ETS;
11999                         /* all UPs mapping to TC0 */
12000                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12001                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
12002                         hw->local_dcbx_config.etsrec =
12003                                 hw->local_dcbx_config.etscfg;
12004                         hw->local_dcbx_config.pfc.willing = 0;
12005                         hw->local_dcbx_config.pfc.pfccap =
12006                                                 I40E_MAX_TRAFFIC_CLASS;
12007                         /* FW needs one App to configure HW */
12008                         hw->local_dcbx_config.numapps = 1;
12009                         hw->local_dcbx_config.app[0].selector =
12010                                                 I40E_APP_SEL_ETHTYPE;
12011                         hw->local_dcbx_config.app[0].priority = 3;
12012                         hw->local_dcbx_config.app[0].protocolid =
12013                                                 I40E_APP_PROTOID_FCOE;
12014                         ret = i40e_set_dcb_config(hw);
12015                         if (ret) {
12016                                 PMD_INIT_LOG(ERR,
12017                                         "default dcb config fails. err = %d, aq_err = %d.",
12018                                         ret, hw->aq.asq_last_status);
12019                                 return -ENOSYS;
12020                         }
12021                 } else {
12022                         PMD_INIT_LOG(ERR,
12023                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
12024                                 ret, hw->aq.asq_last_status);
12025                         return -ENOTSUP;
12026                 }
12027
12028                 if (i40e_need_stop_lldp(dev)) {
12029                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
12030                         if (ret != I40E_SUCCESS)
12031                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
12032                 }
12033         } else {
12034                 ret = i40e_aq_start_lldp(hw, true, NULL);
12035                 if (ret != I40E_SUCCESS)
12036                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
12037
12038                 ret = i40e_init_dcb(hw, true);
12039                 if (!ret) {
12040                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
12041                                 PMD_INIT_LOG(ERR,
12042                                         "HW doesn't support DCBX offload.");
12043                                 return -ENOTSUP;
12044                         }
12045                 } else {
12046                         PMD_INIT_LOG(ERR,
12047                                 "DCBX configuration failed, err = %d, aq_err = %d.",
12048                                 ret, hw->aq.asq_last_status);
12049                         return -ENOTSUP;
12050                 }
12051         }
12052         return 0;
12053 }
12054
12055 /*
12056  * i40e_dcb_setup - setup dcb related config
12057  * @dev: device being configured
12058  *
12059  * Returns 0 on success, negative value on failure
12060  */
12061 static int
12062 i40e_dcb_setup(struct rte_eth_dev *dev)
12063 {
12064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12065         struct i40e_dcbx_config dcb_cfg;
12066         uint8_t tc_map = 0;
12067         int ret = 0;
12068
12069         if ((pf->flags & I40E_FLAG_DCB) == 0) {
12070                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12071                 return -ENOTSUP;
12072         }
12073
12074         if (pf->vf_num != 0)
12075                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12076
12077         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12078         if (ret) {
12079                 PMD_INIT_LOG(ERR, "invalid dcb config");
12080                 return -EINVAL;
12081         }
12082         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12083         if (ret) {
12084                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12085                 return -ENOSYS;
12086         }
12087
12088         return 0;
12089 }
12090
12091 static int
12092 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12093                       struct rte_eth_dcb_info *dcb_info)
12094 {
12095         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12097         struct i40e_vsi *vsi = pf->main_vsi;
12098         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12099         uint16_t bsf, tc_mapping;
12100         int i, j = 0;
12101
12102         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12103                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12104         else
12105                 dcb_info->nb_tcs = 1;
12106         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12107                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12108         for (i = 0; i < dcb_info->nb_tcs; i++)
12109                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12110
12111         /* get queue mapping if vmdq is disabled */
12112         if (!pf->nb_cfg_vmdq_vsi) {
12113                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12114                         if (!(vsi->enabled_tc & (1 << i)))
12115                                 continue;
12116                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12117                         dcb_info->tc_queue.tc_rxq[j][i].base =
12118                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12119                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12120                         dcb_info->tc_queue.tc_txq[j][i].base =
12121                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12122                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12123                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12124                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12125                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12126                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12127                 }
12128                 return 0;
12129         }
12130
12131         /* get queue mapping if vmdq is enabled */
12132         do {
12133                 vsi = pf->vmdq[j].vsi;
12134                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12135                         if (!(vsi->enabled_tc & (1 << i)))
12136                                 continue;
12137                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12138                         dcb_info->tc_queue.tc_rxq[j][i].base =
12139                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12140                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12141                         dcb_info->tc_queue.tc_txq[j][i].base =
12142                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12143                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12144                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12145                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12146                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12147                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12148                 }
12149                 j++;
12150         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12151         return 0;
12152 }
12153
12154 static int
12155 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12156 {
12157         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12158         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12159         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12160         uint16_t msix_intr;
12161
12162         msix_intr = intr_handle->intr_vec[queue_id];
12163         if (msix_intr == I40E_MISC_VEC_ID)
12164                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12165                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
12166                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12167                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12168         else
12169                 I40E_WRITE_REG(hw,
12170                                I40E_PFINT_DYN_CTLN(msix_intr -
12171                                                    I40E_RX_VEC_START),
12172                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
12173                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12174                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12175
12176         I40E_WRITE_FLUSH(hw);
12177         rte_intr_ack(&pci_dev->intr_handle);
12178
12179         return 0;
12180 }
12181
12182 static int
12183 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12184 {
12185         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12186         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12188         uint16_t msix_intr;
12189
12190         msix_intr = intr_handle->intr_vec[queue_id];
12191         if (msix_intr == I40E_MISC_VEC_ID)
12192                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12193                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12194         else
12195                 I40E_WRITE_REG(hw,
12196                                I40E_PFINT_DYN_CTLN(msix_intr -
12197                                                    I40E_RX_VEC_START),
12198                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12199         I40E_WRITE_FLUSH(hw);
12200
12201         return 0;
12202 }
12203
12204 /**
12205  * This function is used to check if the register is valid.
12206  * Below is the valid registers list for X722 only:
12207  * 0x2b800--0x2bb00
12208  * 0x38700--0x38a00
12209  * 0x3d800--0x3db00
12210  * 0x208e00--0x209000
12211  * 0x20be00--0x20c000
12212  * 0x263c00--0x264000
12213  * 0x265c00--0x266000
12214  */
12215 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12216 {
12217         if ((type != I40E_MAC_X722) &&
12218             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12219              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12220              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12221              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12222              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12223              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12224              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12225                 return 0;
12226         else
12227                 return 1;
12228 }
12229
12230 static int i40e_get_regs(struct rte_eth_dev *dev,
12231                          struct rte_dev_reg_info *regs)
12232 {
12233         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12234         uint32_t *ptr_data = regs->data;
12235         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12236         const struct i40e_reg_info *reg_info;
12237
12238         if (ptr_data == NULL) {
12239                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12240                 regs->width = sizeof(uint32_t);
12241                 return 0;
12242         }
12243
12244         /* The first few registers have to be read using AQ operations */
12245         reg_idx = 0;
12246         while (i40e_regs_adminq[reg_idx].name) {
12247                 reg_info = &i40e_regs_adminq[reg_idx++];
12248                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12249                         for (arr_idx2 = 0;
12250                                         arr_idx2 <= reg_info->count2;
12251                                         arr_idx2++) {
12252                                 reg_offset = arr_idx * reg_info->stride1 +
12253                                         arr_idx2 * reg_info->stride2;
12254                                 reg_offset += reg_info->base_addr;
12255                                 ptr_data[reg_offset >> 2] =
12256                                         i40e_read_rx_ctl(hw, reg_offset);
12257                         }
12258         }
12259
12260         /* The remaining registers can be read using primitives */
12261         reg_idx = 0;
12262         while (i40e_regs_others[reg_idx].name) {
12263                 reg_info = &i40e_regs_others[reg_idx++];
12264                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12265                         for (arr_idx2 = 0;
12266                                         arr_idx2 <= reg_info->count2;
12267                                         arr_idx2++) {
12268                                 reg_offset = arr_idx * reg_info->stride1 +
12269                                         arr_idx2 * reg_info->stride2;
12270                                 reg_offset += reg_info->base_addr;
12271                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12272                                         ptr_data[reg_offset >> 2] = 0;
12273                                 else
12274                                         ptr_data[reg_offset >> 2] =
12275                                                 I40E_READ_REG(hw, reg_offset);
12276                         }
12277         }
12278
12279         return 0;
12280 }
12281
12282 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12283 {
12284         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12285
12286         /* Convert word count to byte count */
12287         return hw->nvm.sr_size << 1;
12288 }
12289
12290 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12291                            struct rte_dev_eeprom_info *eeprom)
12292 {
12293         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12294         uint16_t *data = eeprom->data;
12295         uint16_t offset, length, cnt_words;
12296         int ret_code;
12297
12298         offset = eeprom->offset >> 1;
12299         length = eeprom->length >> 1;
12300         cnt_words = length;
12301
12302         if (offset > hw->nvm.sr_size ||
12303                 offset + length > hw->nvm.sr_size) {
12304                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12305                 return -EINVAL;
12306         }
12307
12308         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12309
12310         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12311         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12312                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12313                 return -EIO;
12314         }
12315
12316         return 0;
12317 }
12318
12319 static int i40e_get_module_info(struct rte_eth_dev *dev,
12320                                 struct rte_eth_dev_module_info *modinfo)
12321 {
12322         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12323         uint32_t sff8472_comp = 0;
12324         uint32_t sff8472_swap = 0;
12325         uint32_t sff8636_rev = 0;
12326         i40e_status status;
12327         uint32_t type = 0;
12328
12329         /* Check if firmware supports reading module EEPROM. */
12330         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12331                 PMD_DRV_LOG(ERR,
12332                             "Module EEPROM memory read not supported. "
12333                             "Please update the NVM image.\n");
12334                 return -EINVAL;
12335         }
12336
12337         status = i40e_update_link_info(hw);
12338         if (status)
12339                 return -EIO;
12340
12341         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12342                 PMD_DRV_LOG(ERR,
12343                             "Cannot read module EEPROM memory. "
12344                             "No module connected.\n");
12345                 return -EINVAL;
12346         }
12347
12348         type = hw->phy.link_info.module_type[0];
12349
12350         switch (type) {
12351         case I40E_MODULE_TYPE_SFP:
12352                 status = i40e_aq_get_phy_register(hw,
12353                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12354                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12355                                 I40E_MODULE_SFF_8472_COMP,
12356                                 &sff8472_comp, NULL);
12357                 if (status)
12358                         return -EIO;
12359
12360                 status = i40e_aq_get_phy_register(hw,
12361                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12362                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12363                                 I40E_MODULE_SFF_8472_SWAP,
12364                                 &sff8472_swap, NULL);
12365                 if (status)
12366                         return -EIO;
12367
12368                 /* Check if the module requires address swap to access
12369                  * the other EEPROM memory page.
12370                  */
12371                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12372                         PMD_DRV_LOG(WARNING,
12373                                     "Module address swap to access "
12374                                     "page 0xA2 is not supported.\n");
12375                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12376                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12377                 } else if (sff8472_comp == 0x00) {
12378                         /* Module is not SFF-8472 compliant */
12379                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12380                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12381                 } else {
12382                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12383                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12384                 }
12385                 break;
12386         case I40E_MODULE_TYPE_QSFP_PLUS:
12387                 /* Read from memory page 0. */
12388                 status = i40e_aq_get_phy_register(hw,
12389                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12390                                 0, 1,
12391                                 I40E_MODULE_REVISION_ADDR,
12392                                 &sff8636_rev, NULL);
12393                 if (status)
12394                         return -EIO;
12395                 /* Determine revision compliance byte */
12396                 if (sff8636_rev > 0x02) {
12397                         /* Module is SFF-8636 compliant */
12398                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12399                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12400                 } else {
12401                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12402                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12403                 }
12404                 break;
12405         case I40E_MODULE_TYPE_QSFP28:
12406                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12407                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12408                 break;
12409         default:
12410                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12411                 return -EINVAL;
12412         }
12413         return 0;
12414 }
12415
12416 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12417                                   struct rte_dev_eeprom_info *info)
12418 {
12419         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12420         bool is_sfp = false;
12421         i40e_status status;
12422         uint8_t *data;
12423         uint32_t value = 0;
12424         uint32_t i;
12425
12426         if (!info || !info->length || !info->data)
12427                 return -EINVAL;
12428
12429         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12430                 is_sfp = true;
12431
12432         data = info->data;
12433         for (i = 0; i < info->length; i++) {
12434                 u32 offset = i + info->offset;
12435                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12436
12437                 /* Check if we need to access the other memory page */
12438                 if (is_sfp) {
12439                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12440                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12441                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12442                         }
12443                 } else {
12444                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12445                                 /* Compute memory page number and offset. */
12446                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12447                                 addr++;
12448                         }
12449                 }
12450                 status = i40e_aq_get_phy_register(hw,
12451                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12452                                 addr, 1, offset, &value, NULL);
12453                 if (status)
12454                         return -EIO;
12455                 data[i] = (uint8_t)value;
12456         }
12457         return 0;
12458 }
12459
12460 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12461                                      struct rte_ether_addr *mac_addr)
12462 {
12463         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12465         struct i40e_vsi *vsi = pf->main_vsi;
12466         struct i40e_mac_filter_info mac_filter;
12467         struct i40e_mac_filter *f;
12468         int ret;
12469
12470         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12471                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12472                 return -EINVAL;
12473         }
12474
12475         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12476                 if (rte_is_same_ether_addr(&pf->dev_addr,
12477                                                 &f->mac_info.mac_addr))
12478                         break;
12479         }
12480
12481         if (f == NULL) {
12482                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12483                 return -EIO;
12484         }
12485
12486         mac_filter = f->mac_info;
12487         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12488         if (ret != I40E_SUCCESS) {
12489                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12490                 return -EIO;
12491         }
12492         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12493         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12494         if (ret != I40E_SUCCESS) {
12495                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12496                 return -EIO;
12497         }
12498         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12499
12500         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12501                                         mac_addr->addr_bytes, NULL);
12502         if (ret != I40E_SUCCESS) {
12503                 PMD_DRV_LOG(ERR, "Failed to change mac");
12504                 return -EIO;
12505         }
12506
12507         return 0;
12508 }
12509
12510 static int
12511 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12512 {
12513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12514         struct rte_eth_dev_data *dev_data = pf->dev_data;
12515         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12516         int ret = 0;
12517
12518         /* check if mtu is within the allowed range */
12519         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12520                 return -EINVAL;
12521
12522         /* mtu setting is forbidden if port is start */
12523         if (dev_data->dev_started) {
12524                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12525                             dev_data->port_id);
12526                 return -EBUSY;
12527         }
12528
12529         if (frame_size > RTE_ETHER_MAX_LEN)
12530                 dev_data->dev_conf.rxmode.offloads |=
12531                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12532         else
12533                 dev_data->dev_conf.rxmode.offloads &=
12534                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12535
12536         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12537
12538         return ret;
12539 }
12540
12541 /* Restore ethertype filter */
12542 static void
12543 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12544 {
12545         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12546         struct i40e_ethertype_filter_list
12547                 *ethertype_list = &pf->ethertype.ethertype_list;
12548         struct i40e_ethertype_filter *f;
12549         struct i40e_control_filter_stats stats;
12550         uint16_t flags;
12551
12552         TAILQ_FOREACH(f, ethertype_list, rules) {
12553                 flags = 0;
12554                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12555                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12556                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12557                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12558                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12559
12560                 memset(&stats, 0, sizeof(stats));
12561                 i40e_aq_add_rem_control_packet_filter(hw,
12562                                             f->input.mac_addr.addr_bytes,
12563                                             f->input.ether_type,
12564                                             flags, pf->main_vsi->seid,
12565                                             f->queue, 1, &stats, NULL);
12566         }
12567         PMD_DRV_LOG(INFO, "Ethertype filter:"
12568                     " mac_etype_used = %u, etype_used = %u,"
12569                     " mac_etype_free = %u, etype_free = %u",
12570                     stats.mac_etype_used, stats.etype_used,
12571                     stats.mac_etype_free, stats.etype_free);
12572 }
12573
12574 /* Restore tunnel filter */
12575 static void
12576 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12577 {
12578         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12579         struct i40e_vsi *vsi;
12580         struct i40e_pf_vf *vf;
12581         struct i40e_tunnel_filter_list
12582                 *tunnel_list = &pf->tunnel.tunnel_list;
12583         struct i40e_tunnel_filter *f;
12584         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12585         bool big_buffer = 0;
12586
12587         TAILQ_FOREACH(f, tunnel_list, rules) {
12588                 if (!f->is_to_vf)
12589                         vsi = pf->main_vsi;
12590                 else {
12591                         vf = &pf->vfs[f->vf_id];
12592                         vsi = vf->vsi;
12593                 }
12594                 memset(&cld_filter, 0, sizeof(cld_filter));
12595                 rte_ether_addr_copy((struct rte_ether_addr *)
12596                                 &f->input.outer_mac,
12597                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12598                 rte_ether_addr_copy((struct rte_ether_addr *)
12599                                 &f->input.inner_mac,
12600                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12601                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12602                 cld_filter.element.flags = f->input.flags;
12603                 cld_filter.element.tenant_id = f->input.tenant_id;
12604                 cld_filter.element.queue_number = f->queue;
12605                 rte_memcpy(cld_filter.general_fields,
12606                            f->input.general_fields,
12607                            sizeof(f->input.general_fields));
12608
12609                 if (((f->input.flags &
12610                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12611                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12612                     ((f->input.flags &
12613                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12614                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12615                     ((f->input.flags &
12616                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12617                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12618                         big_buffer = 1;
12619
12620                 if (big_buffer)
12621                         i40e_aq_add_cloud_filters_bb(hw,
12622                                         vsi->seid, &cld_filter, 1);
12623                 else
12624                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12625                                                   &cld_filter.element, 1);
12626         }
12627 }
12628
12629 /* Restore RSS filter */
12630 static inline void
12631 i40e_rss_filter_restore(struct i40e_pf *pf)
12632 {
12633         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12634         struct i40e_rss_filter *filter;
12635
12636         TAILQ_FOREACH(filter, list, next) {
12637                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12638         }
12639 }
12640
12641 static void
12642 i40e_filter_restore(struct i40e_pf *pf)
12643 {
12644         i40e_ethertype_filter_restore(pf);
12645         i40e_tunnel_filter_restore(pf);
12646         i40e_fdir_filter_restore(pf);
12647         i40e_rss_filter_restore(pf);
12648 }
12649
12650 bool
12651 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12652 {
12653         if (strcmp(dev->device->driver->name, drv->driver.name))
12654                 return false;
12655
12656         return true;
12657 }
12658
12659 bool
12660 is_i40e_supported(struct rte_eth_dev *dev)
12661 {
12662         return is_device_supported(dev, &rte_i40e_pmd);
12663 }
12664
12665 struct i40e_customized_pctype*
12666 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12667 {
12668         int i;
12669
12670         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12671                 if (pf->customized_pctype[i].index == index)
12672                         return &pf->customized_pctype[i];
12673         }
12674         return NULL;
12675 }
12676
12677 static int
12678 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12679                               uint32_t pkg_size, uint32_t proto_num,
12680                               struct rte_pmd_i40e_proto_info *proto,
12681                               enum rte_pmd_i40e_package_op op)
12682 {
12683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12684         uint32_t pctype_num;
12685         struct rte_pmd_i40e_ptype_info *pctype;
12686         uint32_t buff_size;
12687         struct i40e_customized_pctype *new_pctype = NULL;
12688         uint8_t proto_id;
12689         uint8_t pctype_value;
12690         char name[64];
12691         uint32_t i, j, n;
12692         int ret;
12693
12694         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12695             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12696                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12697                 return -1;
12698         }
12699
12700         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12701                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12702                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12703         if (ret) {
12704                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12705                 return -1;
12706         }
12707         if (!pctype_num) {
12708                 PMD_DRV_LOG(INFO, "No new pctype added");
12709                 return -1;
12710         }
12711
12712         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12713         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12714         if (!pctype) {
12715                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12716                 return -1;
12717         }
12718         /* get information about new pctype list */
12719         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12720                                         (uint8_t *)pctype, buff_size,
12721                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12722         if (ret) {
12723                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12724                 rte_free(pctype);
12725                 return -1;
12726         }
12727
12728         /* Update customized pctype. */
12729         for (i = 0; i < pctype_num; i++) {
12730                 pctype_value = pctype[i].ptype_id;
12731                 memset(name, 0, sizeof(name));
12732                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12733                         proto_id = pctype[i].protocols[j];
12734                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12735                                 continue;
12736                         for (n = 0; n < proto_num; n++) {
12737                                 if (proto[n].proto_id != proto_id)
12738                                         continue;
12739                                 strlcat(name, proto[n].name, sizeof(name));
12740                                 strlcat(name, "_", sizeof(name));
12741                                 break;
12742                         }
12743                 }
12744                 name[strlen(name) - 1] = '\0';
12745                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12746                 if (!strcmp(name, "GTPC"))
12747                         new_pctype =
12748                                 i40e_find_customized_pctype(pf,
12749                                                       I40E_CUSTOMIZED_GTPC);
12750                 else if (!strcmp(name, "GTPU_IPV4"))
12751                         new_pctype =
12752                                 i40e_find_customized_pctype(pf,
12753                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12754                 else if (!strcmp(name, "GTPU_IPV6"))
12755                         new_pctype =
12756                                 i40e_find_customized_pctype(pf,
12757                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12758                 else if (!strcmp(name, "GTPU"))
12759                         new_pctype =
12760                                 i40e_find_customized_pctype(pf,
12761                                                       I40E_CUSTOMIZED_GTPU);
12762                 else if (!strcmp(name, "IPV4_L2TPV3"))
12763                         new_pctype =
12764                                 i40e_find_customized_pctype(pf,
12765                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12766                 else if (!strcmp(name, "IPV6_L2TPV3"))
12767                         new_pctype =
12768                                 i40e_find_customized_pctype(pf,
12769                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12770                 else if (!strcmp(name, "IPV4_ESP"))
12771                         new_pctype =
12772                                 i40e_find_customized_pctype(pf,
12773                                                 I40E_CUSTOMIZED_ESP_IPV4);
12774                 else if (!strcmp(name, "IPV6_ESP"))
12775                         new_pctype =
12776                                 i40e_find_customized_pctype(pf,
12777                                                 I40E_CUSTOMIZED_ESP_IPV6);
12778                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12779                         new_pctype =
12780                                 i40e_find_customized_pctype(pf,
12781                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12782                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12783                         new_pctype =
12784                                 i40e_find_customized_pctype(pf,
12785                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12786                 else if (!strcmp(name, "IPV4_AH"))
12787                         new_pctype =
12788                                 i40e_find_customized_pctype(pf,
12789                                                 I40E_CUSTOMIZED_AH_IPV4);
12790                 else if (!strcmp(name, "IPV6_AH"))
12791                         new_pctype =
12792                                 i40e_find_customized_pctype(pf,
12793                                                 I40E_CUSTOMIZED_AH_IPV6);
12794                 if (new_pctype) {
12795                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12796                                 new_pctype->pctype = pctype_value;
12797                                 new_pctype->valid = true;
12798                         } else {
12799                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12800                                 new_pctype->valid = false;
12801                         }
12802                 }
12803         }
12804
12805         rte_free(pctype);
12806         return 0;
12807 }
12808
12809 static int
12810 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12811                              uint32_t pkg_size, uint32_t proto_num,
12812                              struct rte_pmd_i40e_proto_info *proto,
12813                              enum rte_pmd_i40e_package_op op)
12814 {
12815         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12816         uint16_t port_id = dev->data->port_id;
12817         uint32_t ptype_num;
12818         struct rte_pmd_i40e_ptype_info *ptype;
12819         uint32_t buff_size;
12820         uint8_t proto_id;
12821         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12822         uint32_t i, j, n;
12823         bool in_tunnel;
12824         int ret;
12825
12826         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12827             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12828                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12829                 return -1;
12830         }
12831
12832         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12833                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12834                 return 0;
12835         }
12836
12837         /* get information about new ptype num */
12838         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12839                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12840                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12841         if (ret) {
12842                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12843                 return ret;
12844         }
12845         if (!ptype_num) {
12846                 PMD_DRV_LOG(INFO, "No new ptype added");
12847                 return -1;
12848         }
12849
12850         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12851         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12852         if (!ptype) {
12853                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12854                 return -1;
12855         }
12856
12857         /* get information about new ptype list */
12858         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12859                                         (uint8_t *)ptype, buff_size,
12860                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12861         if (ret) {
12862                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12863                 rte_free(ptype);
12864                 return ret;
12865         }
12866
12867         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12868         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12869         if (!ptype_mapping) {
12870                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12871                 rte_free(ptype);
12872                 return -1;
12873         }
12874
12875         /* Update ptype mapping table. */
12876         for (i = 0; i < ptype_num; i++) {
12877                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12878                 ptype_mapping[i].sw_ptype = 0;
12879                 in_tunnel = false;
12880                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12881                         proto_id = ptype[i].protocols[j];
12882                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12883                                 continue;
12884                         for (n = 0; n < proto_num; n++) {
12885                                 if (proto[n].proto_id != proto_id)
12886                                         continue;
12887                                 memset(name, 0, sizeof(name));
12888                                 strcpy(name, proto[n].name);
12889                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12890                                 if (!strncasecmp(name, "PPPOE", 5))
12891                                         ptype_mapping[i].sw_ptype |=
12892                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12893                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12894                                          !in_tunnel) {
12895                                         ptype_mapping[i].sw_ptype |=
12896                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12897                                         ptype_mapping[i].sw_ptype |=
12898                                                 RTE_PTYPE_L4_FRAG;
12899                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12900                                            in_tunnel) {
12901                                         ptype_mapping[i].sw_ptype |=
12902                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12903                                         ptype_mapping[i].sw_ptype |=
12904                                                 RTE_PTYPE_INNER_L4_FRAG;
12905                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12906                                         ptype_mapping[i].sw_ptype |=
12907                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12908                                         in_tunnel = true;
12909                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12910                                            !in_tunnel)
12911                                         ptype_mapping[i].sw_ptype |=
12912                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12913                                 else if (!strncasecmp(name, "IPV4", 4) &&
12914                                          in_tunnel)
12915                                         ptype_mapping[i].sw_ptype |=
12916                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12917                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12918                                          !in_tunnel) {
12919                                         ptype_mapping[i].sw_ptype |=
12920                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12921                                         ptype_mapping[i].sw_ptype |=
12922                                                 RTE_PTYPE_L4_FRAG;
12923                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12924                                            in_tunnel) {
12925                                         ptype_mapping[i].sw_ptype |=
12926                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12927                                         ptype_mapping[i].sw_ptype |=
12928                                                 RTE_PTYPE_INNER_L4_FRAG;
12929                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12930                                         ptype_mapping[i].sw_ptype |=
12931                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12932                                         in_tunnel = true;
12933                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12934                                            !in_tunnel)
12935                                         ptype_mapping[i].sw_ptype |=
12936                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12937                                 else if (!strncasecmp(name, "IPV6", 4) &&
12938                                          in_tunnel)
12939                                         ptype_mapping[i].sw_ptype |=
12940                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12941                                 else if (!strncasecmp(name, "UDP", 3) &&
12942                                          !in_tunnel)
12943                                         ptype_mapping[i].sw_ptype |=
12944                                                 RTE_PTYPE_L4_UDP;
12945                                 else if (!strncasecmp(name, "UDP", 3) &&
12946                                          in_tunnel)
12947                                         ptype_mapping[i].sw_ptype |=
12948                                                 RTE_PTYPE_INNER_L4_UDP;
12949                                 else if (!strncasecmp(name, "TCP", 3) &&
12950                                          !in_tunnel)
12951                                         ptype_mapping[i].sw_ptype |=
12952                                                 RTE_PTYPE_L4_TCP;
12953                                 else if (!strncasecmp(name, "TCP", 3) &&
12954                                          in_tunnel)
12955                                         ptype_mapping[i].sw_ptype |=
12956                                                 RTE_PTYPE_INNER_L4_TCP;
12957                                 else if (!strncasecmp(name, "SCTP", 4) &&
12958                                          !in_tunnel)
12959                                         ptype_mapping[i].sw_ptype |=
12960                                                 RTE_PTYPE_L4_SCTP;
12961                                 else if (!strncasecmp(name, "SCTP", 4) &&
12962                                          in_tunnel)
12963                                         ptype_mapping[i].sw_ptype |=
12964                                                 RTE_PTYPE_INNER_L4_SCTP;
12965                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12966                                           !strncasecmp(name, "ICMPV6", 6)) &&
12967                                          !in_tunnel)
12968                                         ptype_mapping[i].sw_ptype |=
12969                                                 RTE_PTYPE_L4_ICMP;
12970                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12971                                           !strncasecmp(name, "ICMPV6", 6)) &&
12972                                          in_tunnel)
12973                                         ptype_mapping[i].sw_ptype |=
12974                                                 RTE_PTYPE_INNER_L4_ICMP;
12975                                 else if (!strncasecmp(name, "GTPC", 4)) {
12976                                         ptype_mapping[i].sw_ptype |=
12977                                                 RTE_PTYPE_TUNNEL_GTPC;
12978                                         in_tunnel = true;
12979                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12980                                         ptype_mapping[i].sw_ptype |=
12981                                                 RTE_PTYPE_TUNNEL_GTPU;
12982                                         in_tunnel = true;
12983                                 } else if (!strncasecmp(name, "ESP", 3)) {
12984                                         ptype_mapping[i].sw_ptype |=
12985                                                 RTE_PTYPE_TUNNEL_ESP;
12986                                         in_tunnel = true;
12987                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12988                                         ptype_mapping[i].sw_ptype |=
12989                                                 RTE_PTYPE_TUNNEL_GRENAT;
12990                                         in_tunnel = true;
12991                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12992                                            !strncasecmp(name, "L2TPV2", 6) ||
12993                                            !strncasecmp(name, "L2TPV3", 6)) {
12994                                         ptype_mapping[i].sw_ptype |=
12995                                                 RTE_PTYPE_TUNNEL_L2TP;
12996                                         in_tunnel = true;
12997                                 }
12998
12999                                 break;
13000                         }
13001                 }
13002         }
13003
13004         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
13005                                                 ptype_num, 0);
13006         if (ret)
13007                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
13008
13009         rte_free(ptype_mapping);
13010         rte_free(ptype);
13011         return ret;
13012 }
13013
13014 void
13015 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
13016                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
13017 {
13018         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
13019         uint32_t proto_num;
13020         struct rte_pmd_i40e_proto_info *proto;
13021         uint32_t buff_size;
13022         uint32_t i;
13023         int ret;
13024
13025         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
13026             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
13027                 PMD_DRV_LOG(ERR, "Unsupported operation.");
13028                 return;
13029         }
13030
13031         /* get information about protocol number */
13032         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13033                                        (uint8_t *)&proto_num, sizeof(proto_num),
13034                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
13035         if (ret) {
13036                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
13037                 return;
13038         }
13039         if (!proto_num) {
13040                 PMD_DRV_LOG(INFO, "No new protocol added");
13041                 return;
13042         }
13043
13044         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
13045         proto = rte_zmalloc("new_proto", buff_size, 0);
13046         if (!proto) {
13047                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
13048                 return;
13049         }
13050
13051         /* get information about protocol list */
13052         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13053                                         (uint8_t *)proto, buff_size,
13054                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
13055         if (ret) {
13056                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
13057                 rte_free(proto);
13058                 return;
13059         }
13060
13061         /* Check if GTP is supported. */
13062         for (i = 0; i < proto_num; i++) {
13063                 if (!strncmp(proto[i].name, "GTP", 3)) {
13064                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13065                                 pf->gtp_support = true;
13066                         else
13067                                 pf->gtp_support = false;
13068                         break;
13069                 }
13070         }
13071
13072         /* Check if ESP is supported. */
13073         for (i = 0; i < proto_num; i++) {
13074                 if (!strncmp(proto[i].name, "ESP", 3)) {
13075                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13076                                 pf->esp_support = true;
13077                         else
13078                                 pf->esp_support = false;
13079                         break;
13080                 }
13081         }
13082
13083         /* Update customized pctype info */
13084         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13085                                             proto_num, proto, op);
13086         if (ret)
13087                 PMD_DRV_LOG(INFO, "No pctype is updated.");
13088
13089         /* Update customized ptype info */
13090         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13091                                            proto_num, proto, op);
13092         if (ret)
13093                 PMD_DRV_LOG(INFO, "No ptype is updated.");
13094
13095         rte_free(proto);
13096 }
13097
13098 /* Create a QinQ cloud filter
13099  *
13100  * The Fortville NIC has limited resources for tunnel filters,
13101  * so we can only reuse existing filters.
13102  *
13103  * In step 1 we define which Field Vector fields can be used for
13104  * filter types.
13105  * As we do not have the inner tag defined as a field,
13106  * we have to define it first, by reusing one of L1 entries.
13107  *
13108  * In step 2 we are replacing one of existing filter types with
13109  * a new one for QinQ.
13110  * As we reusing L1 and replacing L2, some of the default filter
13111  * types will disappear,which depends on L1 and L2 entries we reuse.
13112  *
13113  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13114  *
13115  * 1.   Create L1 filter of outer vlan (12b) which will be in use
13116  *              later when we define the cloud filter.
13117  *      a.      Valid_flags.replace_cloud = 0
13118  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
13119  *      c.      New_filter = 0x10
13120  *      d.      TR bit = 0xff (optional, not used here)
13121  *      e.      Buffer – 2 entries:
13122  *              i.      Byte 0 = 8 (outer vlan FV index).
13123  *                      Byte 1 = 0 (rsv)
13124  *                      Byte 2-3 = 0x0fff
13125  *              ii.     Byte 0 = 37 (inner vlan FV index).
13126  *                      Byte 1 =0 (rsv)
13127  *                      Byte 2-3 = 0x0fff
13128  *
13129  * Step 2:
13130  * 2.   Create cloud filter using two L1 filters entries: stag and
13131  *              new filter(outer vlan+ inner vlan)
13132  *      a.      Valid_flags.replace_cloud = 1
13133  *      b.      Old_filter = 1 (instead of outer IP)
13134  *      c.      New_filter = 0x10
13135  *      d.      Buffer – 2 entries:
13136  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
13137  *                      Byte 1-3 = 0 (rsv)
13138  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13139  *                      Byte 9-11 = 0 (rsv)
13140  */
13141 static int
13142 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13143 {
13144         int ret = -ENOTSUP;
13145         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
13146         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
13147         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13148         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13149
13150         if (pf->support_multi_driver) {
13151                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13152                 return ret;
13153         }
13154
13155         /* Init */
13156         memset(&filter_replace, 0,
13157                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13158         memset(&filter_replace_buf, 0,
13159                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13160
13161         /* create L1 filter */
13162         filter_replace.old_filter_type =
13163                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13164         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13165         filter_replace.tr_bit = 0;
13166
13167         /* Prepare the buffer, 2 entries */
13168         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13169         filter_replace_buf.data[0] |=
13170                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13171         /* Field Vector 12b mask */
13172         filter_replace_buf.data[2] = 0xff;
13173         filter_replace_buf.data[3] = 0x0f;
13174         filter_replace_buf.data[4] =
13175                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13176         filter_replace_buf.data[4] |=
13177                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13178         /* Field Vector 12b mask */
13179         filter_replace_buf.data[6] = 0xff;
13180         filter_replace_buf.data[7] = 0x0f;
13181         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13182                         &filter_replace_buf);
13183         if (ret != I40E_SUCCESS)
13184                 return ret;
13185
13186         if (filter_replace.old_filter_type !=
13187             filter_replace.new_filter_type)
13188                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13189                             " original: 0x%x, new: 0x%x",
13190                             dev->device->name,
13191                             filter_replace.old_filter_type,
13192                             filter_replace.new_filter_type);
13193
13194         /* Apply the second L2 cloud filter */
13195         memset(&filter_replace, 0,
13196                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13197         memset(&filter_replace_buf, 0,
13198                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13199
13200         /* create L2 filter, input for L2 filter will be L1 filter  */
13201         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13202         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13203         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13204
13205         /* Prepare the buffer, 2 entries */
13206         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13207         filter_replace_buf.data[0] |=
13208                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13209         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13210         filter_replace_buf.data[4] |=
13211                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13212         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13213                         &filter_replace_buf);
13214         if (!ret && (filter_replace.old_filter_type !=
13215                      filter_replace.new_filter_type))
13216                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13217                             " original: 0x%x, new: 0x%x",
13218                             dev->device->name,
13219                             filter_replace.old_filter_type,
13220                             filter_replace.new_filter_type);
13221
13222         return ret;
13223 }
13224
13225 int
13226 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13227                    const struct rte_flow_action_rss *in)
13228 {
13229         if (in->key_len > RTE_DIM(out->key) ||
13230             in->queue_num > RTE_DIM(out->queue))
13231                 return -EINVAL;
13232         if (!in->key && in->key_len)
13233                 return -EINVAL;
13234         out->conf = (struct rte_flow_action_rss){
13235                 .func = in->func,
13236                 .level = in->level,
13237                 .types = in->types,
13238                 .key_len = in->key_len,
13239                 .queue_num = in->queue_num,
13240                 .queue = memcpy(out->queue, in->queue,
13241                                 sizeof(*in->queue) * in->queue_num),
13242         };
13243         if (in->key)
13244                 out->conf.key = memcpy(out->key, in->key, in->key_len);
13245         return 0;
13246 }
13247
13248 /* Write HENA register to enable hash */
13249 static int
13250 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13251 {
13252         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13253         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13254         uint64_t hena;
13255         int ret;
13256
13257         ret = i40e_set_rss_key(pf->main_vsi, key,
13258                                rss_conf->conf.key_len);
13259         if (ret)
13260                 return ret;
13261
13262         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13263         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13264         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13265         I40E_WRITE_FLUSH(hw);
13266
13267         return 0;
13268 }
13269
13270 /* Configure hash input set */
13271 static int
13272 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13273 {
13274         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13275         struct rte_eth_input_set_conf conf;
13276         uint64_t mask0;
13277         int ret = 0;
13278         uint32_t j;
13279         int i;
13280         static const struct {
13281                 uint64_t type;
13282                 enum rte_eth_input_set_field field;
13283         } inset_match_table[] = {
13284                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13285                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13286                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13287                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13288                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13289                         RTE_ETH_INPUT_SET_UNKNOWN},
13290                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13291                         RTE_ETH_INPUT_SET_UNKNOWN},
13292
13293                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13294                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13295                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13296                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13297                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13298                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13299                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13300                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13301
13302                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13303                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13304                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13305                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13306                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13307                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13308                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13309                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13310
13311                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13312                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13313                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13314                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13315                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13316                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13317                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13318                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13319
13320                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13321                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13322                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13323                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13324                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13325                         RTE_ETH_INPUT_SET_UNKNOWN},
13326                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13327                         RTE_ETH_INPUT_SET_UNKNOWN},
13328
13329                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13330                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13331                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13332                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13333                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13334                         RTE_ETH_INPUT_SET_UNKNOWN},
13335                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13336                         RTE_ETH_INPUT_SET_UNKNOWN},
13337
13338                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13339                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13340                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13341                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13342                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13343                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13344                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13345                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13346
13347                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13348                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13349                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13350                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13351                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13352                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13353                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13354                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13355
13356                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13357                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13358                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13359                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13360                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13361                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13362                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13363                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13364
13365                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13366                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13367                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13368                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13369                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13370                         RTE_ETH_INPUT_SET_UNKNOWN},
13371                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13372                         RTE_ETH_INPUT_SET_UNKNOWN},
13373         };
13374
13375         mask0 = types & pf->adapter->flow_types_mask;
13376         conf.op = RTE_ETH_INPUT_SET_SELECT;
13377         conf.inset_size = 0;
13378         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13379                 if (mask0 & (1ULL << i)) {
13380                         conf.flow_type = i;
13381                         break;
13382                 }
13383         }
13384
13385         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13386                 if ((types & inset_match_table[j].type) ==
13387                     inset_match_table[j].type) {
13388                         if (inset_match_table[j].field ==
13389                             RTE_ETH_INPUT_SET_UNKNOWN)
13390                                 return -EINVAL;
13391
13392                         conf.field[conf.inset_size] =
13393                                 inset_match_table[j].field;
13394                         conf.inset_size++;
13395                 }
13396         }
13397
13398         if (conf.inset_size) {
13399                 ret = i40e_hash_filter_inset_select(hw, &conf);
13400                 if (ret)
13401                         return ret;
13402         }
13403
13404         return ret;
13405 }
13406
13407 /* Look up the conflicted rule then mark it as invalid */
13408 static void
13409 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13410                 struct i40e_rte_flow_rss_conf *conf)
13411 {
13412         struct i40e_rss_filter *rss_item;
13413         uint64_t rss_inset;
13414
13415         /* Clear input set bits before comparing the pctype */
13416         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13417                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13418
13419         /* Look up the conflicted rule then mark it as invalid */
13420         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13421                 if (!rss_item->rss_filter_info.valid)
13422                         continue;
13423
13424                 if (conf->conf.queue_num &&
13425                     rss_item->rss_filter_info.conf.queue_num)
13426                         rss_item->rss_filter_info.valid = false;
13427
13428                 if (conf->conf.types &&
13429                     (rss_item->rss_filter_info.conf.types &
13430                     rss_inset) ==
13431                     (conf->conf.types & rss_inset))
13432                         rss_item->rss_filter_info.valid = false;
13433
13434                 if (conf->conf.func ==
13435                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13436                     rss_item->rss_filter_info.conf.func ==
13437                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13438                         rss_item->rss_filter_info.valid = false;
13439         }
13440 }
13441
13442 /* Configure RSS hash function */
13443 static int
13444 i40e_rss_config_hash_function(struct i40e_pf *pf,
13445                 struct i40e_rte_flow_rss_conf *conf)
13446 {
13447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13448         uint32_t reg, i;
13449         uint64_t mask0;
13450         uint16_t j;
13451
13452         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13453                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13454                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13455                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13456                         I40E_WRITE_FLUSH(hw);
13457                         i40e_rss_mark_invalid_rule(pf, conf);
13458
13459                         return 0;
13460                 }
13461                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13462
13463                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13464                 I40E_WRITE_FLUSH(hw);
13465                 i40e_rss_mark_invalid_rule(pf, conf);
13466         } else if (conf->conf.func ==
13467                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13468                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13469
13470                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13471                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13472                         if (mask0 & (1UL << i))
13473                                 break;
13474                 }
13475
13476                 if (i == UINT64_BIT)
13477                         return -EINVAL;
13478
13479                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13480                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13481                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13482                                 i40e_write_global_rx_ctl(hw,
13483                                         I40E_GLQF_HSYM(j),
13484                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13485                 }
13486         }
13487
13488         return 0;
13489 }
13490
13491 /* Enable RSS according to the configuration */
13492 static int
13493 i40e_rss_enable_hash(struct i40e_pf *pf,
13494                 struct i40e_rte_flow_rss_conf *conf)
13495 {
13496         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13497         struct i40e_rte_flow_rss_conf rss_conf;
13498
13499         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13500                 return -ENOTSUP;
13501
13502         memset(&rss_conf, 0, sizeof(rss_conf));
13503         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13504
13505         /* Configure hash input set */
13506         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13507                 return -EINVAL;
13508
13509         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13510             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13511                 /* Random default keys */
13512                 static uint32_t rss_key_default[] = {0x6b793944,
13513                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13514                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13515                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13516
13517                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13518                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13519                                 sizeof(uint32_t);
13520                 PMD_DRV_LOG(INFO,
13521                         "No valid RSS key config for i40e, using default\n");
13522         }
13523
13524         rss_conf.conf.types |= rss_info->conf.types;
13525         i40e_rss_hash_set(pf, &rss_conf);
13526
13527         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13528                 i40e_rss_config_hash_function(pf, conf);
13529
13530         i40e_rss_mark_invalid_rule(pf, conf);
13531
13532         return 0;
13533 }
13534
13535 /* Configure RSS queue region */
13536 static int
13537 i40e_rss_config_queue_region(struct i40e_pf *pf,
13538                 struct i40e_rte_flow_rss_conf *conf)
13539 {
13540         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13541         uint32_t lut = 0;
13542         uint16_t j, num;
13543         uint32_t i;
13544
13545         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13546          * It's necessary to calculate the actual PF queues that are configured.
13547          */
13548         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13549                 num = i40e_pf_calc_configured_queues_num(pf);
13550         else
13551                 num = pf->dev_data->nb_rx_queues;
13552
13553         num = RTE_MIN(num, conf->conf.queue_num);
13554         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13555                         num);
13556
13557         if (num == 0) {
13558                 PMD_DRV_LOG(ERR,
13559                         "No PF queues are configured to enable RSS for port %u",
13560                         pf->dev_data->port_id);
13561                 return -ENOTSUP;
13562         }
13563
13564         /* Fill in redirection table */
13565         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13566                 if (j == num)
13567                         j = 0;
13568                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13569                         hw->func_caps.rss_table_entry_width) - 1));
13570                 if ((i & 3) == 3)
13571                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13572         }
13573
13574         i40e_rss_mark_invalid_rule(pf, conf);
13575
13576         return 0;
13577 }
13578
13579 /* Configure RSS hash function to default */
13580 static int
13581 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13582                 struct i40e_rte_flow_rss_conf *conf)
13583 {
13584         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13585         uint32_t i, reg;
13586         uint64_t mask0;
13587         uint16_t j;
13588
13589         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13590                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13591                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13592                         PMD_DRV_LOG(DEBUG,
13593                                 "Hash function already set to Toeplitz");
13594                         I40E_WRITE_FLUSH(hw);
13595
13596                         return 0;
13597                 }
13598                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13599
13600                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13601                 I40E_WRITE_FLUSH(hw);
13602         } else if (conf->conf.func ==
13603                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13604                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13605
13606                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13607                         if (mask0 & (1UL << i))
13608                                 break;
13609                 }
13610
13611                 if (i == UINT64_BIT)
13612                         return -EINVAL;
13613
13614                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13615                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13616                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13617                                 i40e_write_global_rx_ctl(hw,
13618                                         I40E_GLQF_HSYM(j),
13619                                         0);
13620                 }
13621         }
13622
13623         return 0;
13624 }
13625
13626 /* Disable RSS hash and configure default input set */
13627 static int
13628 i40e_rss_disable_hash(struct i40e_pf *pf,
13629                 struct i40e_rte_flow_rss_conf *conf)
13630 {
13631         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13632         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13633         struct i40e_rte_flow_rss_conf rss_conf;
13634         uint32_t i;
13635
13636         memset(&rss_conf, 0, sizeof(rss_conf));
13637         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13638
13639         /* Disable RSS hash */
13640         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13641         i40e_rss_hash_set(pf, &rss_conf);
13642
13643         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13644                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13645                     !(conf->conf.types & (1ULL << i)))
13646                         continue;
13647
13648                 /* Configure default input set */
13649                 struct rte_eth_input_set_conf input_conf = {
13650                         .op = RTE_ETH_INPUT_SET_SELECT,
13651                         .flow_type = i,
13652                         .inset_size = 1,
13653                 };
13654                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13655                 i40e_hash_filter_inset_select(hw, &input_conf);
13656         }
13657
13658         rss_info->conf.types = rss_conf.conf.types;
13659
13660         i40e_rss_clear_hash_function(pf, conf);
13661
13662         return 0;
13663 }
13664
13665 /* Configure RSS queue region to default */
13666 static int
13667 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13668 {
13669         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13670         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13671         uint16_t queue[I40E_MAX_Q_PER_TC];
13672         uint32_t num_rxq, i;
13673         uint32_t lut = 0;
13674         uint16_t j, num;
13675
13676         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13677
13678         for (j = 0; j < num_rxq; j++)
13679                 queue[j] = j;
13680
13681         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13682          * It's necessary to calculate the actual PF queues that are configured.
13683          */
13684         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13685                 num = i40e_pf_calc_configured_queues_num(pf);
13686         else
13687                 num = pf->dev_data->nb_rx_queues;
13688
13689         num = RTE_MIN(num, num_rxq);
13690         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13691                         num);
13692
13693         if (num == 0) {
13694                 PMD_DRV_LOG(ERR,
13695                         "No PF queues are configured to enable RSS for port %u",
13696                         pf->dev_data->port_id);
13697                 return -ENOTSUP;
13698         }
13699
13700         /* Fill in redirection table */
13701         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13702                 if (j == num)
13703                         j = 0;
13704                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13705                         hw->func_caps.rss_table_entry_width) - 1));
13706                 if ((i & 3) == 3)
13707                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13708         }
13709
13710         rss_info->conf.queue_num = 0;
13711         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13712
13713         return 0;
13714 }
13715
13716 int
13717 i40e_config_rss_filter(struct i40e_pf *pf,
13718                 struct i40e_rte_flow_rss_conf *conf, bool add)
13719 {
13720         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13721         struct rte_flow_action_rss update_conf = rss_info->conf;
13722         int ret = 0;
13723
13724         if (add) {
13725                 if (conf->conf.queue_num) {
13726                         /* Configure RSS queue region */
13727                         ret = i40e_rss_config_queue_region(pf, conf);
13728                         if (ret)
13729                                 return ret;
13730
13731                         update_conf.queue_num = conf->conf.queue_num;
13732                         update_conf.queue = conf->conf.queue;
13733                 } else if (conf->conf.func ==
13734                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13735                         /* Configure hash function */
13736                         ret = i40e_rss_config_hash_function(pf, conf);
13737                         if (ret)
13738                                 return ret;
13739
13740                         update_conf.func = conf->conf.func;
13741                 } else {
13742                         /* Configure hash enable and input set */
13743                         ret = i40e_rss_enable_hash(pf, conf);
13744                         if (ret)
13745                                 return ret;
13746
13747                         update_conf.types |= conf->conf.types;
13748                         update_conf.key = conf->conf.key;
13749                         update_conf.key_len = conf->conf.key_len;
13750                 }
13751
13752                 /* Update RSS info in pf */
13753                 if (i40e_rss_conf_init(rss_info, &update_conf))
13754                         return -EINVAL;
13755         } else {
13756                 if (!conf->valid)
13757                         return 0;
13758
13759                 if (conf->conf.queue_num)
13760                         i40e_rss_clear_queue_region(pf);
13761                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13762                         i40e_rss_clear_hash_function(pf, conf);
13763                 else
13764                         i40e_rss_disable_hash(pf, conf);
13765         }
13766
13767         return 0;
13768 }
13769
13770 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13771 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13772 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13773 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13774 #endif
13775 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13776 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13777 #endif
13778 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13779 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13780 #endif
13781
13782 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13783                               ETH_I40E_FLOATING_VEB_ARG "=1"
13784                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13785                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13786                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13787                               ETH_I40E_USE_LATEST_VEC "=0|1");