drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and inteval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518 };
 519
 520 /* store statistics names and its offset in stats structure */
 521 struct rte_i40e_xstats_name_off {
 522         char name[RTE_ETH_XSTATS_NAME_SIZE];
 523         unsigned offset;
 524 };
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 527         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 528         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 529         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 530         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 531         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 532                 rx_unknown_protocol)},
 533         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 534         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 535         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 536         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 537 };
 538
 539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 540                 sizeof(rte_i40e_stats_strings[0]))
 541
 542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 543         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 544                 tx_dropped_link_down)},
 545         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 546         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 547                 illegal_bytes)},
 548         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 549         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_local_faults)},
 551         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 552                 mac_remote_faults)},
 553         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 554                 rx_length_errors)},
 555         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 556         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 557         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 558         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 559         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 560         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_127)},
 562         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_255)},
 564         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_511)},
 566         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1023)},
 568         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_1522)},
 570         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_big)},
 572         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_undersize)},
 574         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_oversize)},
 576         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 577                 mac_short_packet_dropped)},
 578         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_fragments)},
 580         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 581         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 582         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_127)},
 584         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_255)},
 586         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_511)},
 588         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1023)},
 590         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_1522)},
 592         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_big)},
 594         {"rx_flow_director_atr_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 596         {"rx_flow_director_sb_match_packets",
 597                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 598         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_status)},
 600         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_status)},
 602         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 tx_lpi_count)},
 604         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 605                 rx_lpi_count)},
 606 };
 607
 608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 609                 sizeof(rte_i40e_hw_port_strings[0]))
 610
 611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 612         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xon_rx)},
 614         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 615                 priority_xoff_rx)},
 616 };
 617
 618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 619                 sizeof(rte_i40e_rxq_prio_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_tx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_tx)},
 626         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xon_2_xoff)},
 628 };
 629
 630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 631                 sizeof(rte_i40e_txq_prio_strings[0]))
 632
 633 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 634         struct rte_pci_device *pci_dev)
 635 {
 636         return rte_eth_dev_pci_generic_probe(pci_dev,
 637                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 638 }
 639
 640 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 641 {
 642         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 643 }
 644
 645 static struct rte_pci_driver rte_i40e_pmd = {
 646         .id_table = pci_id_i40e_map,
 647         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 648         .probe = eth_i40e_pci_probe,
 649         .remove = eth_i40e_pci_remove,
 650 };
 651
 652 static inline int
 653 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 654                                      struct rte_eth_link *link)
 655 {
 656         struct rte_eth_link *dst = link;
 657         struct rte_eth_link *src = &(dev->data->dev_link);
 658
 659         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 660                                         *(uint64_t *)src) == 0)
 661                 return -1;
 662
 663         return 0;
 664 }
 665
 666 static inline int
 667 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 668                                       struct rte_eth_link *link)
 669 {
 670         struct rte_eth_link *dst = &(dev->data->dev_link);
 671         struct rte_eth_link *src = link;
 672
 673         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 674                                         *(uint64_t *)src) == 0)
 675                 return -1;
 676
 677         return 0;
 678 }
 679
 680 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 681 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 682 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 683
 684 #ifndef I40E_GLQF_ORT
 685 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 686 #endif
 687 #ifndef I40E_GLQF_PIT
 688 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 689 #endif
 690 #ifndef I40E_GLQF_L3_MAP
 691 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 692 #endif
 693
 694 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 695 {
 696         /*
 697          * Initialize registers for flexible payload, which should be set by NVM.
 698          * This should be removed from code once it is fixed in NVM.
 699          */
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 710         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 712
 713         /* Initialize registers for parsing packet type of QinQ */
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 715         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 716 }
 717
 718 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 719
 720 /*
 721  * Add a ethertype filter to drop all flow control frames transmitted
 722  * from VSIs.
 723 */
 724 static void
 725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 726 {
 727         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 728         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 729                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 731         int ret;
 732
 733         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 734                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 735                                 pf->main_vsi_seid, 0,
 736                                 TRUE, NULL, NULL);
 737         if (ret)
 738                 PMD_INIT_LOG(ERR,
 739                         "Failed to add filter to drop flow control frames from VSIs.");
 740 }
 741
 742 static int
 743 floating_veb_list_handler(__rte_unused const char *key,
 744                           const char *floating_veb_value,
 745                           void *opaque)
 746 {
 747         int idx = 0;
 748         unsigned int count = 0;
 749         char *end = NULL;
 750         int min, max;
 751         bool *vf_floating_veb = opaque;
 752
 753         while (isblank(*floating_veb_value))
 754                 floating_veb_value++;
 755
 756         /* Reset floating VEB configuration for VFs */
 757         for (idx = 0; idx < I40E_MAX_VF; idx++)
 758                 vf_floating_veb[idx] = false;
 759
 760         min = I40E_MAX_VF;
 761         do {
 762                 while (isblank(*floating_veb_value))
 763                         floating_veb_value++;
 764                 if (*floating_veb_value == '\0')
 765                         return -1;
 766                 errno = 0;
 767                 idx = strtoul(floating_veb_value, &end, 10);
 768                 if (errno || end == NULL)
 769                         return -1;
 770                 while (isblank(*end))
 771                         end++;
 772                 if (*end == '-') {
 773                         min = idx;
 774                 } else if ((*end == ';') || (*end == '\0')) {
 775                         max = idx;
 776                         if (min == I40E_MAX_VF)
 777                                 min = idx;
 778                         if (max >= I40E_MAX_VF)
 779                                 max = I40E_MAX_VF - 1;
 780                         for (idx = min; idx <= max; idx++) {
 781                                 vf_floating_veb[idx] = true;
 782                                 count++;
 783                         }
 784                         min = I40E_MAX_VF;
 785                 } else {
 786                         return -1;
 787                 }
 788                 floating_veb_value = end + 1;
 789         } while (*end != '\0');
 790
 791         if (count == 0)
 792                 return -1;
 793
 794         return 0;
 795 }
 796
 797 static void
 798 config_vf_floating_veb(struct rte_devargs *devargs,
 799                        uint16_t floating_veb,
 800                        bool *vf_floating_veb)
 801 {
 802         struct rte_kvargs *kvlist;
 803         int i;
 804         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 805
 806         if (!floating_veb)
 807                 return;
 808         /* All the VFs attach to the floating VEB by default
 809          * when the floating VEB is enabled.
 810          */
 811         for (i = 0; i < I40E_MAX_VF; i++)
 812                 vf_floating_veb[i] = true;
 813
 814         if (devargs == NULL)
 815                 return;
 816
 817         kvlist = rte_kvargs_parse(devargs->args, NULL);
 818         if (kvlist == NULL)
 819                 return;
 820
 821         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 822                 rte_kvargs_free(kvlist);
 823                 return;
 824         }
 825         /* When the floating_veb_list parameter exists, all the VFs
 826          * will attach to the legacy VEB firstly, then configure VFs
 827          * to the floating VEB according to the floating_veb_list.
 828          */
 829         if (rte_kvargs_process(kvlist, floating_veb_list,
 830                                floating_veb_list_handler,
 831                                vf_floating_veb) < 0) {
 832                 rte_kvargs_free(kvlist);
 833                 return;
 834         }
 835         rte_kvargs_free(kvlist);
 836 }
 837
 838 static int
 839 i40e_check_floating_handler(__rte_unused const char *key,
 840                             const char *value,
 841                             __rte_unused void *opaque)
 842 {
 843         if (strcmp(value, "1"))
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 static int
 850 is_floating_veb_supported(struct rte_devargs *devargs)
 851 {
 852         struct rte_kvargs *kvlist;
 853         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 854
 855         if (devargs == NULL)
 856                 return 0;
 857
 858         kvlist = rte_kvargs_parse(devargs->args, NULL);
 859         if (kvlist == NULL)
 860                 return 0;
 861
 862         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 863                 rte_kvargs_free(kvlist);
 864                 return 0;
 865         }
 866         /* Floating VEB is enabled when there's key-value:
 867          * enable_floating_veb=1
 868          */
 869         if (rte_kvargs_process(kvlist, floating_veb_key,
 870                                i40e_check_floating_handler, NULL) < 0) {
 871                 rte_kvargs_free(kvlist);
 872                 return 0;
 873         }
 874         rte_kvargs_free(kvlist);
 875
 876         return 1;
 877 }
 878
 879 static void
 880 config_floating_veb(struct rte_eth_dev *dev)
 881 {
 882         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 885
 886         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 887
 888         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 889                 pf->floating_veb =
 890                         is_floating_veb_supported(pci_dev->device.devargs);
 891                 config_vf_floating_veb(pci_dev->device.devargs,
 892                                        pf->floating_veb,
 893                                        pf->floating_veb_list);
 894         } else {
 895                 pf->floating_veb = false;
 896         }
 897 }
 898
 899 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 900 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 901
 902 static int
 903 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 904 {
 905         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 906         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 907         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 908         int ret;
 909
 910         struct rte_hash_parameters ethertype_hash_params = {
 911                 .name = ethertype_hash_name,
 912                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 913                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 914                 .hash_func = rte_hash_crc,
 915                 .hash_func_init_val = 0,
 916                 .socket_id = rte_socket_id(),
 917         };
 918
 919         /* Initialize ethertype filter rule list and hash */
 920         TAILQ_INIT(&ethertype_rule->ethertype_list);
 921         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 922                  "ethertype_%s", dev->data->name);
 923         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 924         if (!ethertype_rule->hash_table) {
 925                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 926                 return -EINVAL;
 927         }
 928         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 929                                        sizeof(struct i40e_ethertype_filter *) *
 930                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 931                                        0);
 932         if (!ethertype_rule->hash_map) {
 933                 PMD_INIT_LOG(ERR,
 934                              "Failed to allocate memory for ethertype hash map!");
 935                 ret = -ENOMEM;
 936                 goto err_ethertype_hash_map_alloc;
 937         }
 938
 939         return 0;
 940
 941 err_ethertype_hash_map_alloc:
 942         rte_hash_free(ethertype_rule->hash_table);
 943
 944         return ret;
 945 }
 946
 947 static int
 948 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 949 {
 950         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 951         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 952         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 953         int ret;
 954
 955         struct rte_hash_parameters tunnel_hash_params = {
 956                 .name = tunnel_hash_name,
 957                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 958                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 959                 .hash_func = rte_hash_crc,
 960                 .hash_func_init_val = 0,
 961                 .socket_id = rte_socket_id(),
 962         };
 963
 964         /* Initialize tunnel filter rule list and hash */
 965         TAILQ_INIT(&tunnel_rule->tunnel_list);
 966         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 967                  "tunnel_%s", dev->data->name);
 968         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 969         if (!tunnel_rule->hash_table) {
 970                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 971                 return -EINVAL;
 972         }
 973         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 974                                     sizeof(struct i40e_tunnel_filter *) *
 975                                     I40E_MAX_TUNNEL_FILTER_NUM,
 976                                     0);
 977         if (!tunnel_rule->hash_map) {
 978                 PMD_INIT_LOG(ERR,
 979                              "Failed to allocate memory for tunnel hash map!");
 980                 ret = -ENOMEM;
 981                 goto err_tunnel_hash_map_alloc;
 982         }
 983
 984         return 0;
 985
 986 err_tunnel_hash_map_alloc:
 987         rte_hash_free(tunnel_rule->hash_table);
 988
 989         return ret;
 990 }
 991
 992 static int
 993 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 994 {
 995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 996         struct i40e_fdir_info *fdir_info = &pf->fdir;
 997         char fdir_hash_name[RTE_HASH_NAMESIZE];
 998         int ret;
 999
1000         struct rte_hash_parameters fdir_hash_params = {
1001                 .name = fdir_hash_name,
1002                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1003                 .key_len = sizeof(struct rte_eth_fdir_input),
1004                 .hash_func = rte_hash_crc,
1005                 .hash_func_init_val = 0,
1006                 .socket_id = rte_socket_id(),
1007         };
1008
1009         /* Initialize flow director filter rule list and hash */
1010         TAILQ_INIT(&fdir_info->fdir_list);
1011         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1012                  "fdir_%s", dev->data->name);
1013         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1014         if (!fdir_info->hash_table) {
1015                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1016                 return -EINVAL;
1017         }
1018         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1019                                           sizeof(struct i40e_fdir_filter *) *
1020                                           I40E_MAX_FDIR_FILTER_NUM,
1021                                           0);
1022         if (!fdir_info->hash_map) {
1023                 PMD_INIT_LOG(ERR,
1024                              "Failed to allocate memory for fdir hash map!");
1025                 ret = -ENOMEM;
1026                 goto err_fdir_hash_map_alloc;
1027         }
1028         return 0;
1029
1030 err_fdir_hash_map_alloc:
1031         rte_hash_free(fdir_info->hash_table);
1032
1033         return ret;
1034 }
1035
1036 static int
1037 eth_i40e_dev_init(struct rte_eth_dev *dev)
1038 {
1039         struct rte_pci_device *pci_dev;
1040         struct rte_intr_handle *intr_handle;
1041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043         struct i40e_vsi *vsi;
1044         int ret;
1045         uint32_t len;
1046         uint8_t aq_fail = 0;
1047
1048         PMD_INIT_FUNC_TRACE();
1049
1050         dev->dev_ops = &i40e_eth_dev_ops;
1051         dev->rx_pkt_burst = i40e_recv_pkts;
1052         dev->tx_pkt_burst = i40e_xmit_pkts;
1053         dev->tx_pkt_prepare = i40e_prep_pkts;
1054
1055         /* for secondary processes, we don't initialise any further as primary
1056          * has already done this work. Only check we don't need a different
1057          * RX function */
1058         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1059                 i40e_set_rx_function(dev);
1060                 i40e_set_tx_function(dev);
1061                 return 0;
1062         }
1063         i40e_set_default_ptype_table(dev);
1064         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1065         intr_handle = &pci_dev->intr_handle;
1066
1067         rte_eth_copy_pci_info(dev, pci_dev);
1068         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1069
1070         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071         pf->adapter->eth_dev = dev;
1072         pf->dev_data = dev->data;
1073
1074         hw->back = I40E_PF_TO_ADAPTER(pf);
1075         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1076         if (!hw->hw_addr) {
1077                 PMD_INIT_LOG(ERR,
1078                         "Hardware is not available, as address is NULL");
1079                 return -ENODEV;
1080         }
1081
1082         hw->vendor_id = pci_dev->id.vendor_id;
1083         hw->device_id = pci_dev->id.device_id;
1084         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086         hw->bus.device = pci_dev->addr.devid;
1087         hw->bus.func = pci_dev->addr.function;
1088         hw->adapter_stopped = 0;
1089
1090         /* Make sure all is clean before doing PF reset */
1091         i40e_clear_hw(hw);
1092
1093         /* Initialize the hardware */
1094         i40e_hw_init(dev);
1095
1096         /* Reset here to make sure all is clean for each PF */
1097         ret = i40e_pf_reset(hw);
1098         if (ret) {
1099                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1100                 return ret;
1101         }
1102
1103         /* Initialize the shared code (base driver) */
1104         ret = i40e_init_shared_code(hw);
1105         if (ret) {
1106                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1107                 return ret;
1108         }
1109
1110         /*
1111          * To work around the NVM issue, initialize registers
1112          * for flexible payload and packet type of QinQ by
1113          * software. It should be removed once issues are fixed
1114          * in NVM.
1115          */
1116         i40e_GLQF_reg_init(hw);
1117
1118         /* Initialize the input set for filters (hash and fd) to default value */
1119         i40e_filter_input_set_init(pf);
1120
1121         /* Initialize the parameters for adminq */
1122         i40e_init_adminq_parameter(hw);
1123         ret = i40e_init_adminq(hw);
1124         if (ret != I40E_SUCCESS) {
1125                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1126                 return -EIO;
1127         }
1128         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131                      ((hw->nvm.version >> 12) & 0xf),
1132                      ((hw->nvm.version >> 4) & 0xff),
1133                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1134
1135         /* initialise the L3_MAP register */
1136         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1137                                    0x00000028,  NULL);
1138         if (ret)
1139                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1140
1141         /* Need the special FW version to support floating VEB */
1142         config_floating_veb(dev);
1143         /* Clear PXE mode */
1144         i40e_clear_pxe_mode(hw);
1145         ret = i40e_dev_sync_phy_type(hw);
1146         if (ret) {
1147                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1148                 goto err_sync_phy_type;
1149         }
1150         /*
1151          * On X710, performance number is far from the expectation on recent
1152          * firmware versions. The fix for this issue may not be integrated in
1153          * the following firmware version. So the workaround in software driver
1154          * is needed. It needs to modify the initial values of 3 internal only
1155          * registers. Note that the workaround can be removed when it is fixed
1156          * in firmware in the future.
1157          */
1158         i40e_configure_registers(hw);
1159
1160         /* Get hw capabilities */
1161         ret = i40e_get_cap(hw);
1162         if (ret != I40E_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164                 goto err_get_capabilities;
1165         }
1166
1167         /* Initialize parameters for PF */
1168         ret = i40e_pf_parameter_init(dev);
1169         if (ret != 0) {
1170                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171                 goto err_parameter_init;
1172         }
1173
1174         /* Initialize the queue management */
1175         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1176         if (ret < 0) {
1177                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178                 goto err_qp_pool_init;
1179         }
1180         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181                                 hw->func_caps.num_msix_vectors - 1);
1182         if (ret < 0) {
1183                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184                 goto err_msix_pool_init;
1185         }
1186
1187         /* Initialize lan hmc */
1188         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189                                 hw->func_caps.num_rx_qp, 0, 0);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192                 goto err_init_lan_hmc;
1193         }
1194
1195         /* Configure lan hmc */
1196         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197         if (ret != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199                 goto err_configure_lan_hmc;
1200         }
1201
1202         /* Get and check the mac address */
1203         i40e_get_mac_addr(hw, hw->mac.addr);
1204         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205                 PMD_INIT_LOG(ERR, "mac address is not valid");
1206                 ret = -EIO;
1207                 goto err_get_mac_addr;
1208         }
1209         /* Copy the permanent MAC address */
1210         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211                         (struct ether_addr *) hw->mac.perm_addr);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* Set the global registers with default ether type value */
1218         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219         if (ret != I40E_SUCCESS) {
1220                 PMD_INIT_LOG(ERR,
1221                         "Failed to set the default outer VLAN ether type");
1222                 goto err_setup_pf_switch;
1223         }
1224
1225         /* PF setup, which includes VSI setup */
1226         ret = i40e_pf_setup(pf);
1227         if (ret) {
1228                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229                 goto err_setup_pf_switch;
1230         }
1231
1232         /* reset all stats of the device, including pf and main vsi */
1233         i40e_dev_stats_reset(dev);
1234
1235         vsi = pf->main_vsi;
1236
1237         /* Disable double vlan by default */
1238         i40e_vsi_config_double_vlan(vsi, FALSE);
1239
1240         /* Disable S-TAG identification when floating_veb is disabled */
1241         if (!pf->floating_veb) {
1242                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1246                 }
1247         }
1248
1249         if (!vsi->max_macaddrs)
1250                 len = ETHER_ADDR_LEN;
1251         else
1252                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1253
1254         /* Should be after VSI initialized */
1255         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256         if (!dev->data->mac_addrs) {
1257                 PMD_INIT_LOG(ERR,
1258                         "Failed to allocated memory for storing mac address");
1259                 goto err_mac_alloc;
1260         }
1261         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262                                         &dev->data->mac_addrs[0]);
1263
1264         /* Init dcb to sw mode by default */
1265         ret = i40e_dcb_init_configure(dev, TRUE);
1266         if (ret != I40E_SUCCESS) {
1267                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268                 pf->flags &= ~I40E_FLAG_DCB;
1269         }
1270         /* Update HW struct after DCB configuration */
1271         i40e_get_cap(hw);
1272
1273         /* initialize pf host driver to setup SRIOV resource if applicable */
1274         i40e_pf_host_init(dev);
1275
1276         /* register callback func to eal lib */
1277         rte_intr_callback_register(intr_handle,
1278                                    i40e_dev_interrupt_handler, dev);
1279
1280         /* configure and enable device interrupt */
1281         i40e_pf_config_irq0(hw, TRUE);
1282         i40e_pf_enable_irq0(hw);
1283
1284         /* enable uio intr after callback register */
1285         rte_intr_enable(intr_handle);
1286         /*
1287          * Add an ethertype filter to drop all flow control frames transmitted
1288          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1289          * frames to wire.
1290          */
1291         i40e_add_tx_flow_control_drop_filter(pf);
1292
1293         /* Set the max frame size to 0x2600 by default,
1294          * in case other drivers changed the default value.
1295          */
1296         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1297
1298         /* initialize mirror rule list */
1299         TAILQ_INIT(&pf->mirror_list);
1300
1301         ret = i40e_init_ethtype_filter_list(dev);
1302         if (ret < 0)
1303                 goto err_init_ethtype_filter_list;
1304         ret = i40e_init_tunnel_filter_list(dev);
1305         if (ret < 0)
1306                 goto err_init_tunnel_filter_list;
1307         ret = i40e_init_fdir_filter_list(dev);
1308         if (ret < 0)
1309                 goto err_init_fdir_filter_list;
1310
1311         return 0;
1312
1313 err_init_fdir_filter_list:
1314         rte_free(pf->tunnel.hash_table);
1315         rte_free(pf->tunnel.hash_map);
1316 err_init_tunnel_filter_list:
1317         rte_free(pf->ethertype.hash_table);
1318         rte_free(pf->ethertype.hash_map);
1319 err_init_ethtype_filter_list:
1320         rte_free(dev->data->mac_addrs);
1321 err_mac_alloc:
1322         i40e_vsi_release(pf->main_vsi);
1323 err_setup_pf_switch:
1324 err_get_mac_addr:
1325 err_configure_lan_hmc:
1326         (void)i40e_shutdown_lan_hmc(hw);
1327 err_init_lan_hmc:
1328         i40e_res_pool_destroy(&pf->msix_pool);
1329 err_msix_pool_init:
1330         i40e_res_pool_destroy(&pf->qp_pool);
1331 err_qp_pool_init:
1332 err_parameter_init:
1333 err_get_capabilities:
1334 err_sync_phy_type:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int
1468 i40e_dev_configure(struct rte_eth_dev *dev)
1469 {
1470         struct i40e_adapter *ad =
1471                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1473         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1474         int i, ret;
1475
1476         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1477          * bulk allocation or vector Rx preconditions we will reset it.
1478          */
1479         ad->rx_bulk_alloc_allowed = true;
1480         ad->rx_vec_allowed = true;
1481         ad->tx_simple_allowed = true;
1482         ad->tx_vec_allowed = true;
1483
1484         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1485                 ret = i40e_fdir_setup(pf);
1486                 if (ret != I40E_SUCCESS) {
1487                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1488                         return -ENOTSUP;
1489                 }
1490                 ret = i40e_fdir_configure(dev);
1491                 if (ret < 0) {
1492                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1493                         goto err;
1494                 }
1495         } else
1496                 i40e_fdir_teardown(pf);
1497
1498         ret = i40e_dev_init_vlan(dev);
1499         if (ret < 0)
1500                 goto err;
1501
1502         /* VMDQ setup.
1503          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1504          *  RSS setting have different requirements.
1505          *  General PMD driver call sequence are NIC init, configure,
1506          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1507          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1508          *  applicable. So, VMDQ setting has to be done before
1509          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1510          *  For RSS setting, it will try to calculate actual configured RX queue
1511          *  number, which will be available after rx_queue_setup(). dev_start()
1512          *  function is good to place RSS setup.
1513          */
1514         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1515                 ret = i40e_vmdq_setup(dev);
1516                 if (ret)
1517                         goto err;
1518         }
1519
1520         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1521                 ret = i40e_dcb_setup(dev);
1522                 if (ret) {
1523                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1524                         goto err_dcb;
1525                 }
1526         }
1527
1528         TAILQ_INIT(&pf->flow_list);
1529
1530         return 0;
1531
1532 err_dcb:
1533         /* need to release vmdq resource if exists */
1534         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1535                 i40e_vsi_release(pf->vmdq[i].vsi);
1536                 pf->vmdq[i].vsi = NULL;
1537         }
1538         rte_free(pf->vmdq);
1539         pf->vmdq = NULL;
1540 err:
1541         /* need to release fdir resource if exists */
1542         i40e_fdir_teardown(pf);
1543         return ret;
1544 }
1545
1546 void
1547 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1548 {
1549         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1550         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1551         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1553         uint16_t msix_vect = vsi->msix_intr;
1554         uint16_t i;
1555
1556         for (i = 0; i < vsi->nb_qps; i++) {
1557                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1558                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1559                 rte_wmb();
1560         }
1561
1562         if (vsi->type != I40E_VSI_SRIOV) {
1563                 if (!rte_intr_allow_others(intr_handle)) {
1564                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1565                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1566                         I40E_WRITE_REG(hw,
1567                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1568                                        0);
1569                 } else {
1570                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1571                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1572                         I40E_WRITE_REG(hw,
1573                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1574                                                        msix_vect - 1), 0);
1575                 }
1576         } else {
1577                 uint32_t reg;
1578                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1579                         vsi->user_param + (msix_vect - 1);
1580
1581                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1582                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1583         }
1584         I40E_WRITE_FLUSH(hw);
1585 }
1586
1587 static void
1588 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1589                        int base_queue, int nb_queue)
1590 {
1591         int i;
1592         uint32_t val;
1593         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1594
1595         /* Bind all RX queues to allocated MSIX interrupt */
1596         for (i = 0; i < nb_queue; i++) {
1597                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1598                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1599                         ((base_queue + i + 1) <<
1600                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1601                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1602                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1603
1604                 if (i == nb_queue - 1)
1605                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1606                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1607         }
1608
1609         /* Write first RX queue to Link list register as the head element */
1610         if (vsi->type != I40E_VSI_SRIOV) {
1611                 uint16_t interval =
1612                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1613
1614                 if (msix_vect == I40E_MISC_VEC_ID) {
1615                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1616                                        (base_queue <<
1617                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1618                                        (0x0 <<
1619                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1620                         I40E_WRITE_REG(hw,
1621                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1622                                        interval);
1623                 } else {
1624                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1625                                        (base_queue <<
1626                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1627                                        (0x0 <<
1628                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1629                         I40E_WRITE_REG(hw,
1630                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1631                                                        msix_vect - 1),
1632                                        interval);
1633                 }
1634         } else {
1635                 uint32_t reg;
1636
1637                 if (msix_vect == I40E_MISC_VEC_ID) {
1638                         I40E_WRITE_REG(hw,
1639                                        I40E_VPINT_LNKLST0(vsi->user_param),
1640                                        (base_queue <<
1641                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1642                                        (0x0 <<
1643                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1644                 } else {
1645                         /* num_msix_vectors_vf needs to minus irq0 */
1646                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1647                                 vsi->user_param + (msix_vect - 1);
1648
1649                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1650                                        (base_queue <<
1651                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1652                                        (0x0 <<
1653                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1654                 }
1655         }
1656
1657         I40E_WRITE_FLUSH(hw);
1658 }
1659
1660 void
1661 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1662 {
1663         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1664         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1665         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1667         uint16_t msix_vect = vsi->msix_intr;
1668         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1669         uint16_t queue_idx = 0;
1670         int record = 0;
1671         uint32_t val;
1672         int i;
1673
1674         for (i = 0; i < vsi->nb_qps; i++) {
1675                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1676                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1677         }
1678
1679         /* INTENA flag is not auto-cleared for interrupt */
1680         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1681         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1682                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1683                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1684         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1685
1686         /* VF bind interrupt */
1687         if (vsi->type == I40E_VSI_SRIOV) {
1688                 __vsi_queues_bind_intr(vsi, msix_vect,
1689                                        vsi->base_queue, vsi->nb_qps);
1690                 return;
1691         }
1692
1693         /* PF & VMDq bind interrupt */
1694         if (rte_intr_dp_is_en(intr_handle)) {
1695                 if (vsi->type == I40E_VSI_MAIN) {
1696                         queue_idx = 0;
1697                         record = 1;
1698                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1699                         struct i40e_vsi *main_vsi =
1700                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1701                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1702                         record = 1;
1703                 }
1704         }
1705
1706         for (i = 0; i < vsi->nb_used_qps; i++) {
1707                 if (nb_msix <= 1) {
1708                         if (!rte_intr_allow_others(intr_handle))
1709                                 /* allow to share MISC_VEC_ID */
1710                                 msix_vect = I40E_MISC_VEC_ID;
1711
1712                         /* no enough msix_vect, map all to one */
1713                         __vsi_queues_bind_intr(vsi, msix_vect,
1714                                                vsi->base_queue + i,
1715                                                vsi->nb_used_qps - i);
1716                         for (; !!record && i < vsi->nb_used_qps; i++)
1717                                 intr_handle->intr_vec[queue_idx + i] =
1718                                         msix_vect;
1719                         break;
1720                 }
1721                 /* 1:1 queue/msix_vect mapping */
1722                 __vsi_queues_bind_intr(vsi, msix_vect,
1723                                        vsi->base_queue + i, 1);
1724                 if (!!record)
1725                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1726
1727                 msix_vect++;
1728                 nb_msix--;
1729         }
1730 }
1731
1732 static void
1733 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1734 {
1735         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1736         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1737         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1738         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1739         uint16_t interval = i40e_calc_itr_interval(\
1740                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1741         uint16_t msix_intr, i;
1742
1743         if (rte_intr_allow_others(intr_handle))
1744                 for (i = 0; i < vsi->nb_msix; i++) {
1745                         msix_intr = vsi->msix_intr + i;
1746                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1747                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1748                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1749                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1750                                 (interval <<
1751                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1752                 }
1753         else
1754                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1755                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1756                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1757                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1758                                (interval <<
1759                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1760
1761         I40E_WRITE_FLUSH(hw);
1762 }
1763
1764 static void
1765 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1766 {
1767         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1769         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771         uint16_t msix_intr, i;
1772
1773         if (rte_intr_allow_others(intr_handle))
1774                 for (i = 0; i < vsi->nb_msix; i++) {
1775                         msix_intr = vsi->msix_intr + i;
1776                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1777                                        0);
1778                 }
1779         else
1780                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1781
1782         I40E_WRITE_FLUSH(hw);
1783 }
1784
1785 static inline uint8_t
1786 i40e_parse_link_speeds(uint16_t link_speeds)
1787 {
1788         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1789
1790         if (link_speeds & ETH_LINK_SPEED_40G)
1791                 link_speed |= I40E_LINK_SPEED_40GB;
1792         if (link_speeds & ETH_LINK_SPEED_25G)
1793                 link_speed |= I40E_LINK_SPEED_25GB;
1794         if (link_speeds & ETH_LINK_SPEED_20G)
1795                 link_speed |= I40E_LINK_SPEED_20GB;
1796         if (link_speeds & ETH_LINK_SPEED_10G)
1797                 link_speed |= I40E_LINK_SPEED_10GB;
1798         if (link_speeds & ETH_LINK_SPEED_1G)
1799                 link_speed |= I40E_LINK_SPEED_1GB;
1800         if (link_speeds & ETH_LINK_SPEED_100M)
1801                 link_speed |= I40E_LINK_SPEED_100MB;
1802
1803         return link_speed;
1804 }
1805
1806 static int
1807 i40e_phy_conf_link(struct i40e_hw *hw,
1808                    uint8_t abilities,
1809                    uint8_t force_speed)
1810 {
1811         enum i40e_status_code status;
1812         struct i40e_aq_get_phy_abilities_resp phy_ab;
1813         struct i40e_aq_set_phy_config phy_conf;
1814         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1815                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1816                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1817                         I40E_AQ_PHY_FLAG_LOW_POWER;
1818         const uint8_t advt = I40E_LINK_SPEED_40GB |
1819                         I40E_LINK_SPEED_25GB |
1820                         I40E_LINK_SPEED_10GB |
1821                         I40E_LINK_SPEED_1GB |
1822                         I40E_LINK_SPEED_100MB;
1823         int ret = -ENOTSUP;
1824
1825
1826         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1827                                               NULL);
1828         if (status)
1829                 return ret;
1830
1831         memset(&phy_conf, 0, sizeof(phy_conf));
1832
1833         /* bits 0-2 use the values from get_phy_abilities_resp */
1834         abilities &= ~mask;
1835         abilities |= phy_ab.abilities & mask;
1836
1837         /* update ablities and speed */
1838         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1839                 phy_conf.link_speed = advt;
1840         else
1841                 phy_conf.link_speed = force_speed;
1842
1843         phy_conf.abilities = abilities;
1844
1845         /* use get_phy_abilities_resp value for the rest */
1846         phy_conf.phy_type = phy_ab.phy_type;
1847         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1848         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1849         phy_conf.eee_capability = phy_ab.eee_capability;
1850         phy_conf.eeer = phy_ab.eeer_val;
1851         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1852
1853         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1854                     phy_ab.abilities, phy_ab.link_speed);
1855         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1856                     phy_conf.abilities, phy_conf.link_speed);
1857
1858         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1859         if (status)
1860                 return ret;
1861
1862         return I40E_SUCCESS;
1863 }
1864
1865 static int
1866 i40e_apply_link_speed(struct rte_eth_dev *dev)
1867 {
1868         uint8_t speed;
1869         uint8_t abilities = 0;
1870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         struct rte_eth_conf *conf = &dev->data->dev_conf;
1872
1873         speed = i40e_parse_link_speeds(conf->link_speeds);
1874         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1875         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1876                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1877         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1878
1879         /* Skip changing speed on 40G interfaces, FW does not support */
1880         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1881                 speed =  I40E_LINK_SPEED_UNKNOWN;
1882                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1883         }
1884
1885         return i40e_phy_conf_link(hw, abilities, speed);
1886 }
1887
1888 static int
1889 i40e_dev_start(struct rte_eth_dev *dev)
1890 {
1891         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893         struct i40e_vsi *main_vsi = pf->main_vsi;
1894         int ret, i;
1895         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1896         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897         uint32_t intr_vector = 0;
1898         struct i40e_vsi *vsi;
1899
1900         hw->adapter_stopped = 0;
1901
1902         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1903                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1904                              dev->data->port_id);
1905                 return -EINVAL;
1906         }
1907
1908         rte_intr_disable(intr_handle);
1909
1910         if ((rte_intr_cap_multiple(intr_handle) ||
1911              !RTE_ETH_DEV_SRIOV(dev).active) &&
1912             dev->data->dev_conf.intr_conf.rxq != 0) {
1913                 intr_vector = dev->data->nb_rx_queues;
1914                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1915                 if (ret)
1916                         return ret;
1917         }
1918
1919         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1920                 intr_handle->intr_vec =
1921                         rte_zmalloc("intr_vec",
1922                                     dev->data->nb_rx_queues * sizeof(int),
1923                                     0);
1924                 if (!intr_handle->intr_vec) {
1925                         PMD_INIT_LOG(ERR,
1926                                 "Failed to allocate %d rx_queues intr_vec",
1927                                 dev->data->nb_rx_queues);
1928                         return -ENOMEM;
1929                 }
1930         }
1931
1932         /* Initialize VSI */
1933         ret = i40e_dev_rxtx_init(pf);
1934         if (ret != I40E_SUCCESS) {
1935                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1936                 goto err_up;
1937         }
1938
1939         /* Map queues with MSIX interrupt */
1940         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1941                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1942         i40e_vsi_queues_bind_intr(main_vsi);
1943         i40e_vsi_enable_queues_intr(main_vsi);
1944
1945         /* Map VMDQ VSI queues with MSIX interrupt */
1946         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1947                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1948                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1949                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1950         }
1951
1952         /* enable FDIR MSIX interrupt */
1953         if (pf->fdir.fdir_vsi) {
1954                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1955                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1956         }
1957
1958         /* Enable all queues which have been configured */
1959         ret = i40e_dev_switch_queues(pf, TRUE);
1960         if (ret != I40E_SUCCESS) {
1961                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1962                 goto err_up;
1963         }
1964
1965         /* Enable receiving broadcast packets */
1966         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1967         if (ret != I40E_SUCCESS)
1968                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1969
1970         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1971                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1972                                                 true, NULL);
1973                 if (ret != I40E_SUCCESS)
1974                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1975         }
1976
1977         /* Enable the VLAN promiscuous mode. */
1978         if (pf->vfs) {
1979                 for (i = 0; i < pf->vf_num; i++) {
1980                         vsi = pf->vfs[i].vsi;
1981                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1982                                                      true, NULL);
1983                 }
1984         }
1985
1986         /* Apply link configure */
1987         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1988                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1989                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1990                                 ETH_LINK_SPEED_40G)) {
1991                 PMD_DRV_LOG(ERR, "Invalid link setting");
1992                 goto err_up;
1993         }
1994         ret = i40e_apply_link_speed(dev);
1995         if (I40E_SUCCESS != ret) {
1996                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1997                 goto err_up;
1998         }
1999
2000         if (!rte_intr_allow_others(intr_handle)) {
2001                 rte_intr_callback_unregister(intr_handle,
2002                                              i40e_dev_interrupt_handler,
2003                                              (void *)dev);
2004                 /* configure and enable device interrupt */
2005                 i40e_pf_config_irq0(hw, FALSE);
2006                 i40e_pf_enable_irq0(hw);
2007
2008                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2009                         PMD_INIT_LOG(INFO,
2010                                 "lsc won't enable because of no intr multiplex");
2011         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2012                 ret = i40e_aq_set_phy_int_mask(hw,
2013                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2014                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2015                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2016                 if (ret != I40E_SUCCESS)
2017                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2018
2019                 /* Call get_link_info aq commond to enable LSE */
2020                 i40e_dev_link_update(dev, 0);
2021         }
2022
2023         /* enable uio intr after callback register */
2024         rte_intr_enable(intr_handle);
2025
2026         i40e_filter_restore(pf);
2027
2028         return I40E_SUCCESS;
2029
2030 err_up:
2031         i40e_dev_switch_queues(pf, FALSE);
2032         i40e_dev_clear_queues(dev);
2033
2034         return ret;
2035 }
2036
2037 static void
2038 i40e_dev_stop(struct rte_eth_dev *dev)
2039 {
2040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2041         struct i40e_vsi *main_vsi = pf->main_vsi;
2042         struct i40e_mirror_rule *p_mirror;
2043         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2044         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2045         int i;
2046
2047         /* Disable all queues */
2048         i40e_dev_switch_queues(pf, FALSE);
2049
2050         /* un-map queues with interrupt registers */
2051         i40e_vsi_disable_queues_intr(main_vsi);
2052         i40e_vsi_queues_unbind_intr(main_vsi);
2053
2054         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2055                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2056                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2057         }
2058
2059         if (pf->fdir.fdir_vsi) {
2060                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2061                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2062         }
2063         /* Clear all queues and release memory */
2064         i40e_dev_clear_queues(dev);
2065
2066         /* Set link down */
2067         i40e_dev_set_link_down(dev);
2068
2069         /* Remove all mirror rules */
2070         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2071                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2072                 rte_free(p_mirror);
2073         }
2074         pf->nb_mirror_rule = 0;
2075
2076         if (!rte_intr_allow_others(intr_handle))
2077                 /* resume to the default handler */
2078                 rte_intr_callback_register(intr_handle,
2079                                            i40e_dev_interrupt_handler,
2080                                            (void *)dev);
2081
2082         /* Clean datapath event and queue/vec mapping */
2083         rte_intr_efd_disable(intr_handle);
2084         if (intr_handle->intr_vec) {
2085                 rte_free(intr_handle->intr_vec);
2086                 intr_handle->intr_vec = NULL;
2087         }
2088 }
2089
2090 static void
2091 i40e_dev_close(struct rte_eth_dev *dev)
2092 {
2093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2096         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2097         uint32_t reg;
2098         int i;
2099
2100         PMD_INIT_FUNC_TRACE();
2101
2102         i40e_dev_stop(dev);
2103         hw->adapter_stopped = 1;
2104         i40e_dev_free_queues(dev);
2105
2106         /* Disable interrupt */
2107         i40e_pf_disable_irq0(hw);
2108         rte_intr_disable(intr_handle);
2109
2110         /* shutdown and destroy the HMC */
2111         i40e_shutdown_lan_hmc(hw);
2112
2113         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114                 i40e_vsi_release(pf->vmdq[i].vsi);
2115                 pf->vmdq[i].vsi = NULL;
2116         }
2117         rte_free(pf->vmdq);
2118         pf->vmdq = NULL;
2119
2120         /* release all the existing VSIs and VEBs */
2121         i40e_fdir_teardown(pf);
2122         i40e_vsi_release(pf->main_vsi);
2123
2124         /* shutdown the adminq */
2125         i40e_aq_queue_shutdown(hw, true);
2126         i40e_shutdown_adminq(hw);
2127
2128         i40e_res_pool_destroy(&pf->qp_pool);
2129         i40e_res_pool_destroy(&pf->msix_pool);
2130
2131         /* force a PF reset to clean anything leftover */
2132         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2133         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2134                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2135         I40E_WRITE_FLUSH(hw);
2136 }
2137
2138 static void
2139 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2140 {
2141         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143         struct i40e_vsi *vsi = pf->main_vsi;
2144         int status;
2145
2146         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2147                                                      true, NULL, true);
2148         if (status != I40E_SUCCESS)
2149                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2150
2151         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2152                                                         TRUE, NULL);
2153         if (status != I40E_SUCCESS)
2154                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2155
2156 }
2157
2158 static void
2159 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2160 {
2161         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         struct i40e_vsi *vsi = pf->main_vsi;
2164         int status;
2165
2166         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2167                                                      false, NULL, true);
2168         if (status != I40E_SUCCESS)
2169                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2170
2171         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2172                                                         false, NULL);
2173         if (status != I40E_SUCCESS)
2174                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2175 }
2176
2177 static void
2178 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2179 {
2180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2181         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182         struct i40e_vsi *vsi = pf->main_vsi;
2183         int ret;
2184
2185         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2186         if (ret != I40E_SUCCESS)
2187                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2188 }
2189
2190 static void
2191 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2192 {
2193         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2194         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195         struct i40e_vsi *vsi = pf->main_vsi;
2196         int ret;
2197
2198         if (dev->data->promiscuous == 1)
2199                 return; /* must remain in all_multicast mode */
2200
2201         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2202                                 vsi->seid, FALSE, NULL);
2203         if (ret != I40E_SUCCESS)
2204                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2205 }
2206
2207 /*
2208  * Set device link up.
2209  */
2210 static int
2211 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2212 {
2213         /* re-apply link speed setting */
2214         return i40e_apply_link_speed(dev);
2215 }
2216
2217 /*
2218  * Set device link down.
2219  */
2220 static int
2221 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2222 {
2223         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2224         uint8_t abilities = 0;
2225         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226
2227         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2228         return i40e_phy_conf_link(hw, abilities, speed);
2229 }
2230
2231 int
2232 i40e_dev_link_update(struct rte_eth_dev *dev,
2233                      int wait_to_complete)
2234 {
2235 #define CHECK_INTERVAL 100  /* 100ms */
2236 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         struct i40e_link_status link_status;
2239         struct rte_eth_link link, old;
2240         int status;
2241         unsigned rep_cnt = MAX_REPEAT_TIME;
2242         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2243
2244         memset(&link, 0, sizeof(link));
2245         memset(&old, 0, sizeof(old));
2246         memset(&link_status, 0, sizeof(link_status));
2247         rte_i40e_dev_atomic_read_link_status(dev, &old);
2248
2249         do {
2250                 /* Get link status information from hardware */
2251                 status = i40e_aq_get_link_info(hw, enable_lse,
2252                                                 &link_status, NULL);
2253                 if (status != I40E_SUCCESS) {
2254                         link.link_speed = ETH_SPEED_NUM_100M;
2255                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2256                         PMD_DRV_LOG(ERR, "Failed to get link info");
2257                         goto out;
2258                 }
2259
2260                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2261                 if (!wait_to_complete || link.link_status)
2262                         break;
2263
2264                 rte_delay_ms(CHECK_INTERVAL);
2265         } while (--rep_cnt);
2266
2267         if (!link.link_status)
2268                 goto out;
2269
2270         /* i40e uses full duplex only */
2271         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2272
2273         /* Parse the link status */
2274         switch (link_status.link_speed) {
2275         case I40E_LINK_SPEED_100MB:
2276                 link.link_speed = ETH_SPEED_NUM_100M;
2277                 break;
2278         case I40E_LINK_SPEED_1GB:
2279                 link.link_speed = ETH_SPEED_NUM_1G;
2280                 break;
2281         case I40E_LINK_SPEED_10GB:
2282                 link.link_speed = ETH_SPEED_NUM_10G;
2283                 break;
2284         case I40E_LINK_SPEED_20GB:
2285                 link.link_speed = ETH_SPEED_NUM_20G;
2286                 break;
2287         case I40E_LINK_SPEED_25GB:
2288                 link.link_speed = ETH_SPEED_NUM_25G;
2289                 break;
2290         case I40E_LINK_SPEED_40GB:
2291                 link.link_speed = ETH_SPEED_NUM_40G;
2292                 break;
2293         default:
2294                 link.link_speed = ETH_SPEED_NUM_100M;
2295                 break;
2296         }
2297
2298         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2299                         ETH_LINK_SPEED_FIXED);
2300
2301 out:
2302         rte_i40e_dev_atomic_write_link_status(dev, &link);
2303         if (link.link_status == old.link_status)
2304                 return -1;
2305
2306         i40e_notify_all_vfs_link_status(dev);
2307
2308         return 0;
2309 }
2310
2311 /* Get all the statistics of a VSI */
2312 void
2313 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2314 {
2315         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2316         struct i40e_eth_stats *nes = &vsi->eth_stats;
2317         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2318         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2319
2320         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2321                             vsi->offset_loaded, &oes->rx_bytes,
2322                             &nes->rx_bytes);
2323         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2324                             vsi->offset_loaded, &oes->rx_unicast,
2325                             &nes->rx_unicast);
2326         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2327                             vsi->offset_loaded, &oes->rx_multicast,
2328                             &nes->rx_multicast);
2329         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2330                             vsi->offset_loaded, &oes->rx_broadcast,
2331                             &nes->rx_broadcast);
2332         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2333                             &oes->rx_discards, &nes->rx_discards);
2334         /* GLV_REPC not supported */
2335         /* GLV_RMPC not supported */
2336         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2337                             &oes->rx_unknown_protocol,
2338                             &nes->rx_unknown_protocol);
2339         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2340                             vsi->offset_loaded, &oes->tx_bytes,
2341                             &nes->tx_bytes);
2342         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2343                             vsi->offset_loaded, &oes->tx_unicast,
2344                             &nes->tx_unicast);
2345         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2346                             vsi->offset_loaded, &oes->tx_multicast,
2347                             &nes->tx_multicast);
2348         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2349                             vsi->offset_loaded,  &oes->tx_broadcast,
2350                             &nes->tx_broadcast);
2351         /* GLV_TDPC not supported */
2352         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2353                             &oes->tx_errors, &nes->tx_errors);
2354         vsi->offset_loaded = true;
2355
2356         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2357                     vsi->vsi_id);
2358         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2359         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2360         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2361         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2362         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2363         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2364                     nes->rx_unknown_protocol);
2365         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2366         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2367         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2368         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2369         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2370         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2371         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2372                     vsi->vsi_id);
2373 }
2374
2375 static void
2376 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2377 {
2378         unsigned int i;
2379         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2380         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2381
2382         /* Get rx/tx bytes of internal transfer packets */
2383         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2384                         I40E_GLV_GORCL(hw->port),
2385                         pf->offset_loaded,
2386                         &pf->internal_rx_bytes_offset,
2387                         &pf->internal_rx_bytes);
2388
2389         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2390                         I40E_GLV_GOTCL(hw->port),
2391                         pf->offset_loaded,
2392                         &pf->internal_tx_bytes_offset,
2393                         &pf->internal_tx_bytes);
2394
2395         /* Get statistics of struct i40e_eth_stats */
2396         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2397                             I40E_GLPRT_GORCL(hw->port),
2398                             pf->offset_loaded, &os->eth.rx_bytes,
2399                             &ns->eth.rx_bytes);
2400         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2401                             I40E_GLPRT_UPRCL(hw->port),
2402                             pf->offset_loaded, &os->eth.rx_unicast,
2403                             &ns->eth.rx_unicast);
2404         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2405                             I40E_GLPRT_MPRCL(hw->port),
2406                             pf->offset_loaded, &os->eth.rx_multicast,
2407                             &ns->eth.rx_multicast);
2408         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2409                             I40E_GLPRT_BPRCL(hw->port),
2410                             pf->offset_loaded, &os->eth.rx_broadcast,
2411                             &ns->eth.rx_broadcast);
2412         /* Workaround: CRC size should not be included in byte statistics,
2413          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2414          */
2415         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2416                 ns->eth.rx_broadcast) * ETHER_CRC_LEN + pf->internal_rx_bytes;
2417
2418         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2419                             pf->offset_loaded, &os->eth.rx_discards,
2420                             &ns->eth.rx_discards);
2421         /* GLPRT_REPC not supported */
2422         /* GLPRT_RMPC not supported */
2423         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2424                             pf->offset_loaded,
2425                             &os->eth.rx_unknown_protocol,
2426                             &ns->eth.rx_unknown_protocol);
2427         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2428                             I40E_GLPRT_GOTCL(hw->port),
2429                             pf->offset_loaded, &os->eth.tx_bytes,
2430                             &ns->eth.tx_bytes);
2431         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2432                             I40E_GLPRT_UPTCL(hw->port),
2433                             pf->offset_loaded, &os->eth.tx_unicast,
2434                             &ns->eth.tx_unicast);
2435         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2436                             I40E_GLPRT_MPTCL(hw->port),
2437                             pf->offset_loaded, &os->eth.tx_multicast,
2438                             &ns->eth.tx_multicast);
2439         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2440                             I40E_GLPRT_BPTCL(hw->port),
2441                             pf->offset_loaded, &os->eth.tx_broadcast,
2442                             &ns->eth.tx_broadcast);
2443         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2444                 ns->eth.tx_broadcast) * ETHER_CRC_LEN + pf->internal_tx_bytes;
2445         /* GLPRT_TEPC not supported */
2446
2447         /* additional port specific stats */
2448         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2449                             pf->offset_loaded, &os->tx_dropped_link_down,
2450                             &ns->tx_dropped_link_down);
2451         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2452                             pf->offset_loaded, &os->crc_errors,
2453                             &ns->crc_errors);
2454         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2455                             pf->offset_loaded, &os->illegal_bytes,
2456                             &ns->illegal_bytes);
2457         /* GLPRT_ERRBC not supported */
2458         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2459                             pf->offset_loaded, &os->mac_local_faults,
2460                             &ns->mac_local_faults);
2461         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2462                             pf->offset_loaded, &os->mac_remote_faults,
2463                             &ns->mac_remote_faults);
2464         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2465                             pf->offset_loaded, &os->rx_length_errors,
2466                             &ns->rx_length_errors);
2467         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2468                             pf->offset_loaded, &os->link_xon_rx,
2469                             &ns->link_xon_rx);
2470         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2471                             pf->offset_loaded, &os->link_xoff_rx,
2472                             &ns->link_xoff_rx);
2473         for (i = 0; i < 8; i++) {
2474                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2475                                     pf->offset_loaded,
2476                                     &os->priority_xon_rx[i],
2477                                     &ns->priority_xon_rx[i]);
2478                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2479                                     pf->offset_loaded,
2480                                     &os->priority_xoff_rx[i],
2481                                     &ns->priority_xoff_rx[i]);
2482         }
2483         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2484                             pf->offset_loaded, &os->link_xon_tx,
2485                             &ns->link_xon_tx);
2486         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2487                             pf->offset_loaded, &os->link_xoff_tx,
2488                             &ns->link_xoff_tx);
2489         for (i = 0; i < 8; i++) {
2490                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2491                                     pf->offset_loaded,
2492                                     &os->priority_xon_tx[i],
2493                                     &ns->priority_xon_tx[i]);
2494                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2495                                     pf->offset_loaded,
2496                                     &os->priority_xoff_tx[i],
2497                                     &ns->priority_xoff_tx[i]);
2498                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2499                                     pf->offset_loaded,
2500                                     &os->priority_xon_2_xoff[i],
2501                                     &ns->priority_xon_2_xoff[i]);
2502         }
2503         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2504                             I40E_GLPRT_PRC64L(hw->port),
2505                             pf->offset_loaded, &os->rx_size_64,
2506                             &ns->rx_size_64);
2507         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2508                             I40E_GLPRT_PRC127L(hw->port),
2509                             pf->offset_loaded, &os->rx_size_127,
2510                             &ns->rx_size_127);
2511         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2512                             I40E_GLPRT_PRC255L(hw->port),
2513                             pf->offset_loaded, &os->rx_size_255,
2514                             &ns->rx_size_255);
2515         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2516                             I40E_GLPRT_PRC511L(hw->port),
2517                             pf->offset_loaded, &os->rx_size_511,
2518                             &ns->rx_size_511);
2519         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2520                             I40E_GLPRT_PRC1023L(hw->port),
2521                             pf->offset_loaded, &os->rx_size_1023,
2522                             &ns->rx_size_1023);
2523         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2524                             I40E_GLPRT_PRC1522L(hw->port),
2525                             pf->offset_loaded, &os->rx_size_1522,
2526                             &ns->rx_size_1522);
2527         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2528                             I40E_GLPRT_PRC9522L(hw->port),
2529                             pf->offset_loaded, &os->rx_size_big,
2530                             &ns->rx_size_big);
2531         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2532                             pf->offset_loaded, &os->rx_undersize,
2533                             &ns->rx_undersize);
2534         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2535                             pf->offset_loaded, &os->rx_fragments,
2536                             &ns->rx_fragments);
2537         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2538                             pf->offset_loaded, &os->rx_oversize,
2539                             &ns->rx_oversize);
2540         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2541                             pf->offset_loaded, &os->rx_jabber,
2542                             &ns->rx_jabber);
2543         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2544                             I40E_GLPRT_PTC64L(hw->port),
2545                             pf->offset_loaded, &os->tx_size_64,
2546                             &ns->tx_size_64);
2547         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2548                             I40E_GLPRT_PTC127L(hw->port),
2549                             pf->offset_loaded, &os->tx_size_127,
2550                             &ns->tx_size_127);
2551         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2552                             I40E_GLPRT_PTC255L(hw->port),
2553                             pf->offset_loaded, &os->tx_size_255,
2554                             &ns->tx_size_255);
2555         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2556                             I40E_GLPRT_PTC511L(hw->port),
2557                             pf->offset_loaded, &os->tx_size_511,
2558                             &ns->tx_size_511);
2559         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2560                             I40E_GLPRT_PTC1023L(hw->port),
2561                             pf->offset_loaded, &os->tx_size_1023,
2562                             &ns->tx_size_1023);
2563         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2564                             I40E_GLPRT_PTC1522L(hw->port),
2565                             pf->offset_loaded, &os->tx_size_1522,
2566                             &ns->tx_size_1522);
2567         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2568                             I40E_GLPRT_PTC9522L(hw->port),
2569                             pf->offset_loaded, &os->tx_size_big,
2570                             &ns->tx_size_big);
2571         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2572                            pf->offset_loaded,
2573                            &os->fd_sb_match, &ns->fd_sb_match);
2574         /* GLPRT_MSPDC not supported */
2575         /* GLPRT_XEC not supported */
2576
2577         pf->offset_loaded = true;
2578
2579         if (pf->main_vsi)
2580                 i40e_update_vsi_stats(pf->main_vsi);
2581 }
2582
2583 /* Get all statistics of a port */
2584 static void
2585 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2586 {
2587         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2588         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2589         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2590         unsigned i;
2591
2592         /* call read registers - updates values, now write them to struct */
2593         i40e_read_stats_registers(pf, hw);
2594
2595         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2596                         pf->main_vsi->eth_stats.rx_multicast +
2597                         pf->main_vsi->eth_stats.rx_broadcast -
2598                         pf->main_vsi->eth_stats.rx_discards;
2599         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2600                         pf->main_vsi->eth_stats.tx_multicast +
2601                         pf->main_vsi->eth_stats.tx_broadcast;
2602         stats->ibytes   = ns->eth.rx_bytes;
2603         stats->obytes   = ns->eth.tx_bytes;
2604         stats->oerrors  = ns->eth.tx_errors +
2605                         pf->main_vsi->eth_stats.tx_errors;
2606
2607         /* Rx Errors */
2608         stats->imissed  = ns->eth.rx_discards +
2609                         pf->main_vsi->eth_stats.rx_discards;
2610         stats->ierrors  = ns->crc_errors +
2611                         ns->rx_length_errors + ns->rx_undersize +
2612                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2613
2614         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2615         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2616         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2617         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2618         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2619         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2620         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2621                     ns->eth.rx_unknown_protocol);
2622         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2623         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2624         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2625         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2626         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2627         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2628
2629         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2630                     ns->tx_dropped_link_down);
2631         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2632         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2633                     ns->illegal_bytes);
2634         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2635         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2636                     ns->mac_local_faults);
2637         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2638                     ns->mac_remote_faults);
2639         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2640                     ns->rx_length_errors);
2641         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2642         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2643         for (i = 0; i < 8; i++) {
2644                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2645                                 i, ns->priority_xon_rx[i]);
2646                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2647                                 i, ns->priority_xoff_rx[i]);
2648         }
2649         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2650         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2651         for (i = 0; i < 8; i++) {
2652                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2653                                 i, ns->priority_xon_tx[i]);
2654                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2655                                 i, ns->priority_xoff_tx[i]);
2656                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2657                                 i, ns->priority_xon_2_xoff[i]);
2658         }
2659         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2660         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2661         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2662         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2663         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2664         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2665         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2666         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2667         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2668         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2669         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2670         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2671         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2672         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2673         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2674         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2675         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2676         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2677         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2678                         ns->mac_short_packet_dropped);
2679         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2680                     ns->checksum_error);
2681         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2682         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2683 }
2684
2685 /* Reset the statistics */
2686 static void
2687 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2688 {
2689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2690         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2691
2692         /* Mark PF and VSI stats to update the offset, aka "reset" */
2693         pf->offset_loaded = false;
2694         if (pf->main_vsi)
2695                 pf->main_vsi->offset_loaded = false;
2696
2697         /* read the stats, reading current register values into offset */
2698         i40e_read_stats_registers(pf, hw);
2699 }
2700
2701 static uint32_t
2702 i40e_xstats_calc_num(void)
2703 {
2704         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2705                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2706                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2707 }
2708
2709 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2710                                      struct rte_eth_xstat_name *xstats_names,
2711                                      __rte_unused unsigned limit)
2712 {
2713         unsigned count = 0;
2714         unsigned i, prio;
2715
2716         if (xstats_names == NULL)
2717                 return i40e_xstats_calc_num();
2718
2719         /* Note: limit checked in rte_eth_xstats_names() */
2720
2721         /* Get stats from i40e_eth_stats struct */
2722         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2723                 snprintf(xstats_names[count].name,
2724                          sizeof(xstats_names[count].name),
2725                          "%s", rte_i40e_stats_strings[i].name);
2726                 count++;
2727         }
2728
2729         /* Get individiual stats from i40e_hw_port struct */
2730         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2731                 snprintf(xstats_names[count].name,
2732                         sizeof(xstats_names[count].name),
2733                          "%s", rte_i40e_hw_port_strings[i].name);
2734                 count++;
2735         }
2736
2737         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2738                 for (prio = 0; prio < 8; prio++) {
2739                         snprintf(xstats_names[count].name,
2740                                  sizeof(xstats_names[count].name),
2741                                  "rx_priority%u_%s", prio,
2742                                  rte_i40e_rxq_prio_strings[i].name);
2743                         count++;
2744                 }
2745         }
2746
2747         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2748                 for (prio = 0; prio < 8; prio++) {
2749                         snprintf(xstats_names[count].name,
2750                                  sizeof(xstats_names[count].name),
2751                                  "tx_priority%u_%s", prio,
2752                                  rte_i40e_txq_prio_strings[i].name);
2753                         count++;
2754                 }
2755         }
2756         return count;
2757 }
2758
2759 static int
2760 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2761                     unsigned n)
2762 {
2763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2764         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765         unsigned i, count, prio;
2766         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2767
2768         count = i40e_xstats_calc_num();
2769         if (n < count)
2770                 return count;
2771
2772         i40e_read_stats_registers(pf, hw);
2773
2774         if (xstats == NULL)
2775                 return 0;
2776
2777         count = 0;
2778
2779         /* Get stats from i40e_eth_stats struct */
2780         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2781                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2782                         rte_i40e_stats_strings[i].offset);
2783                 xstats[count].id = count;
2784                 count++;
2785         }
2786
2787         /* Get individiual stats from i40e_hw_port struct */
2788         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2789                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2790                         rte_i40e_hw_port_strings[i].offset);
2791                 xstats[count].id = count;
2792                 count++;
2793         }
2794
2795         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2796                 for (prio = 0; prio < 8; prio++) {
2797                         xstats[count].value =
2798                                 *(uint64_t *)(((char *)hw_stats) +
2799                                 rte_i40e_rxq_prio_strings[i].offset +
2800                                 (sizeof(uint64_t) * prio));
2801                         xstats[count].id = count;
2802                         count++;
2803                 }
2804         }
2805
2806         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2807                 for (prio = 0; prio < 8; prio++) {
2808                         xstats[count].value =
2809                                 *(uint64_t *)(((char *)hw_stats) +
2810                                 rte_i40e_txq_prio_strings[i].offset +
2811                                 (sizeof(uint64_t) * prio));
2812                         xstats[count].id = count;
2813                         count++;
2814                 }
2815         }
2816
2817         return count;
2818 }
2819
2820 static int
2821 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2822                                  __rte_unused uint16_t queue_id,
2823                                  __rte_unused uint8_t stat_idx,
2824                                  __rte_unused uint8_t is_rx)
2825 {
2826         PMD_INIT_FUNC_TRACE();
2827
2828         return -ENOSYS;
2829 }
2830
2831 static int
2832 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2833 {
2834         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835         u32 full_ver;
2836         u8 ver, patch;
2837         u16 build;
2838         int ret;
2839
2840         full_ver = hw->nvm.oem_ver;
2841         ver = (u8)(full_ver >> 24);
2842         build = (u16)((full_ver >> 8) & 0xffff);
2843         patch = (u8)(full_ver & 0xff);
2844
2845         ret = snprintf(fw_version, fw_size,
2846                  "%d.%d%d 0x%08x %d.%d.%d",
2847                  ((hw->nvm.version >> 12) & 0xf),
2848                  ((hw->nvm.version >> 4) & 0xff),
2849                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2850                  ver, build, patch);
2851
2852         ret += 1; /* add the size of '\0' */
2853         if (fw_size < (u32)ret)
2854                 return ret;
2855         else
2856                 return 0;
2857 }
2858
2859 static void
2860 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2861 {
2862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2864         struct i40e_vsi *vsi = pf->main_vsi;
2865         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2866
2867         dev_info->pci_dev = pci_dev;
2868         dev_info->max_rx_queues = vsi->nb_qps;
2869         dev_info->max_tx_queues = vsi->nb_qps;
2870         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2871         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2872         dev_info->max_mac_addrs = vsi->max_macaddrs;
2873         dev_info->max_vfs = pci_dev->max_vfs;
2874         dev_info->rx_offload_capa =
2875                 DEV_RX_OFFLOAD_VLAN_STRIP |
2876                 DEV_RX_OFFLOAD_QINQ_STRIP |
2877                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2878                 DEV_RX_OFFLOAD_UDP_CKSUM |
2879                 DEV_RX_OFFLOAD_TCP_CKSUM;
2880         dev_info->tx_offload_capa =
2881                 DEV_TX_OFFLOAD_VLAN_INSERT |
2882                 DEV_TX_OFFLOAD_QINQ_INSERT |
2883                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2884                 DEV_TX_OFFLOAD_UDP_CKSUM |
2885                 DEV_TX_OFFLOAD_TCP_CKSUM |
2886                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2887                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2888                 DEV_TX_OFFLOAD_TCP_TSO |
2889                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2890                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2891                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2892                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2893         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2894                                                 sizeof(uint32_t);
2895         dev_info->reta_size = pf->hash_lut_size;
2896         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2897
2898         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2899                 .rx_thresh = {
2900                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2901                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2902                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2903                 },
2904                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2905                 .rx_drop_en = 0,
2906         };
2907
2908         dev_info->default_txconf = (struct rte_eth_txconf) {
2909                 .tx_thresh = {
2910                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2911                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2912                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2913                 },
2914                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2915                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2916                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2917                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2918         };
2919
2920         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2921                 .nb_max = I40E_MAX_RING_DESC,
2922                 .nb_min = I40E_MIN_RING_DESC,
2923                 .nb_align = I40E_ALIGN_RING_DESC,
2924         };
2925
2926         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2927                 .nb_max = I40E_MAX_RING_DESC,
2928                 .nb_min = I40E_MIN_RING_DESC,
2929                 .nb_align = I40E_ALIGN_RING_DESC,
2930                 .nb_seg_max = I40E_TX_MAX_SEG,
2931                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2932         };
2933
2934         if (pf->flags & I40E_FLAG_VMDQ) {
2935                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2936                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2937                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2938                                                 pf->max_nb_vmdq_vsi;
2939                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2940                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2941                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2942         }
2943
2944         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2945                 /* For XL710 */
2946                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2947         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2948                 /* For XXV710 */
2949                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2950         else
2951                 /* For X710 */
2952                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2953 }
2954
2955 static int
2956 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2957 {
2958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2959         struct i40e_vsi *vsi = pf->main_vsi;
2960         PMD_INIT_FUNC_TRACE();
2961
2962         if (on)
2963                 return i40e_vsi_add_vlan(vsi, vlan_id);
2964         else
2965                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2966 }
2967
2968 static int
2969 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2970                    enum rte_vlan_type vlan_type,
2971                    uint16_t tpid)
2972 {
2973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974         uint64_t reg_r = 0, reg_w = 0;
2975         uint16_t reg_id = 0;
2976         int ret = 0;
2977         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2978
2979         switch (vlan_type) {
2980         case ETH_VLAN_TYPE_OUTER:
2981                 if (qinq)
2982                         reg_id = 2;
2983                 else
2984                         reg_id = 3;
2985                 break;
2986         case ETH_VLAN_TYPE_INNER:
2987                 if (qinq)
2988                         reg_id = 3;
2989                 else {
2990                         ret = -EINVAL;
2991                         PMD_DRV_LOG(ERR,
2992                                 "Unsupported vlan type in single vlan.");
2993                         return ret;
2994                 }
2995                 break;
2996         default:
2997                 ret = -EINVAL;
2998                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2999                 return ret;
3000         }
3001         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3002                                           &reg_r, NULL);
3003         if (ret != I40E_SUCCESS) {
3004                 PMD_DRV_LOG(ERR,
3005                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3006                            reg_id);
3007                 ret = -EIO;
3008                 return ret;
3009         }
3010         PMD_DRV_LOG(DEBUG,
3011                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3012                 reg_id, reg_r);
3013
3014         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3015         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3016         if (reg_r == reg_w) {
3017                 ret = 0;
3018                 PMD_DRV_LOG(DEBUG, "No need to write");
3019                 return ret;
3020         }
3021
3022         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3023                                            reg_w, NULL);
3024         if (ret != I40E_SUCCESS) {
3025                 ret = -EIO;
3026                 PMD_DRV_LOG(ERR,
3027                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3028                         reg_id);
3029                 return ret;
3030         }
3031         PMD_DRV_LOG(DEBUG,
3032                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3033                 reg_w, reg_id);
3034
3035         return ret;
3036 }
3037
3038 static void
3039 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3040 {
3041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3042         struct i40e_vsi *vsi = pf->main_vsi;
3043
3044         if (mask & ETH_VLAN_FILTER_MASK) {
3045                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3046                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3047                 else
3048                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3049         }
3050
3051         if (mask & ETH_VLAN_STRIP_MASK) {
3052                 /* Enable or disable VLAN stripping */
3053                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3054                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3055                 else
3056                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3057         }
3058
3059         if (mask & ETH_VLAN_EXTEND_MASK) {
3060                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3061                         i40e_vsi_config_double_vlan(vsi, TRUE);
3062                         /* Set global registers with default ether type value */
3063                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3064                                            ETHER_TYPE_VLAN);
3065                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3066                                            ETHER_TYPE_VLAN);
3067                 }
3068                 else
3069                         i40e_vsi_config_double_vlan(vsi, FALSE);
3070         }
3071 }
3072
3073 static void
3074 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3075                           __rte_unused uint16_t queue,
3076                           __rte_unused int on)
3077 {
3078         PMD_INIT_FUNC_TRACE();
3079 }
3080
3081 static int
3082 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3083 {
3084         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3085         struct i40e_vsi *vsi = pf->main_vsi;
3086         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3087         struct i40e_vsi_vlan_pvid_info info;
3088
3089         memset(&info, 0, sizeof(info));
3090         info.on = on;
3091         if (info.on)
3092                 info.config.pvid = pvid;
3093         else {
3094                 info.config.reject.tagged =
3095                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3096                 info.config.reject.untagged =
3097                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3098         }
3099
3100         return i40e_vsi_vlan_pvid_set(vsi, &info);
3101 }
3102
3103 static int
3104 i40e_dev_led_on(struct rte_eth_dev *dev)
3105 {
3106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3107         uint32_t mode = i40e_led_get(hw);
3108
3109         if (mode == 0)
3110                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3111
3112         return 0;
3113 }
3114
3115 static int
3116 i40e_dev_led_off(struct rte_eth_dev *dev)
3117 {
3118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119         uint32_t mode = i40e_led_get(hw);
3120
3121         if (mode != 0)
3122                 i40e_led_set(hw, 0, false);
3123
3124         return 0;
3125 }
3126
3127 static int
3128 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3129 {
3130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3132
3133         fc_conf->pause_time = pf->fc_conf.pause_time;
3134         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3135         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3136
3137          /* Return current mode according to actual setting*/
3138         switch (hw->fc.current_mode) {
3139         case I40E_FC_FULL:
3140                 fc_conf->mode = RTE_FC_FULL;
3141                 break;
3142         case I40E_FC_TX_PAUSE:
3143                 fc_conf->mode = RTE_FC_TX_PAUSE;
3144                 break;
3145         case I40E_FC_RX_PAUSE:
3146                 fc_conf->mode = RTE_FC_RX_PAUSE;
3147                 break;
3148         case I40E_FC_NONE:
3149         default:
3150                 fc_conf->mode = RTE_FC_NONE;
3151         };
3152
3153         return 0;
3154 }
3155
3156 static int
3157 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3158 {
3159         uint32_t mflcn_reg, fctrl_reg, reg;
3160         uint32_t max_high_water;
3161         uint8_t i, aq_failure;
3162         int err;
3163         struct i40e_hw *hw;
3164         struct i40e_pf *pf;
3165         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3166                 [RTE_FC_NONE] = I40E_FC_NONE,
3167                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3168                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3169                 [RTE_FC_FULL] = I40E_FC_FULL
3170         };
3171
3172         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3173
3174         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3175         if ((fc_conf->high_water > max_high_water) ||
3176                         (fc_conf->high_water < fc_conf->low_water)) {
3177                 PMD_INIT_LOG(ERR,
3178                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3179                         max_high_water);
3180                 return -EINVAL;
3181         }
3182
3183         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3185         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3186
3187         pf->fc_conf.pause_time = fc_conf->pause_time;
3188         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3189         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3190
3191         PMD_INIT_FUNC_TRACE();
3192
3193         /* All the link flow control related enable/disable register
3194          * configuration is handle by the F/W
3195          */
3196         err = i40e_set_fc(hw, &aq_failure, true);
3197         if (err < 0)
3198                 return -ENOSYS;
3199
3200         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3201                 /* Configure flow control refresh threshold,
3202                  * the value for stat_tx_pause_refresh_timer[8]
3203                  * is used for global pause operation.
3204                  */
3205
3206                 I40E_WRITE_REG(hw,
3207                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3208                                pf->fc_conf.pause_time);
3209
3210                 /* configure the timer value included in transmitted pause
3211                  * frame,
3212                  * the value for stat_tx_pause_quanta[8] is used for global
3213                  * pause operation
3214                  */
3215                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3216                                pf->fc_conf.pause_time);
3217
3218                 fctrl_reg = I40E_READ_REG(hw,
3219                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3220
3221                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3222                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3223                 else
3224                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3225
3226                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3227                                fctrl_reg);
3228         } else {
3229                 /* Configure pause time (2 TCs per register) */
3230                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3231                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3232                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3233
3234                 /* Configure flow control refresh threshold value */
3235                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3236                                pf->fc_conf.pause_time / 2);
3237
3238                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3239
3240                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3241                  *depending on configuration
3242                  */
3243                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3244                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3245                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3246                 } else {
3247                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3248                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3249                 }
3250
3251                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3252         }
3253
3254         /* config the water marker both based on the packets and bytes */
3255         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3256                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3257                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3258         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3259                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3260                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3261         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3262                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3263                        << I40E_KILOSHIFT);
3264         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3265                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3266                        << I40E_KILOSHIFT);
3267
3268         I40E_WRITE_FLUSH(hw);
3269
3270         return 0;
3271 }
3272
3273 static int
3274 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3275                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3276 {
3277         PMD_INIT_FUNC_TRACE();
3278
3279         return -ENOSYS;
3280 }
3281
3282 /* Add a MAC address, and update filters */
3283 static int
3284 i40e_macaddr_add(struct rte_eth_dev *dev,
3285                  struct ether_addr *mac_addr,
3286                  __rte_unused uint32_t index,
3287                  uint32_t pool)
3288 {
3289         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3290         struct i40e_mac_filter_info mac_filter;
3291         struct i40e_vsi *vsi;
3292         int ret;
3293
3294         /* If VMDQ not enabled or configured, return */
3295         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3296                           !pf->nb_cfg_vmdq_vsi)) {
3297                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3298                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3299                         pool);
3300                 return -ENOTSUP;
3301         }
3302
3303         if (pool > pf->nb_cfg_vmdq_vsi) {
3304                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3305                                 pool, pf->nb_cfg_vmdq_vsi);
3306                 return -EINVAL;
3307         }
3308
3309         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3310         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3311                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3312         else
3313                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3314
3315         if (pool == 0)
3316                 vsi = pf->main_vsi;
3317         else
3318                 vsi = pf->vmdq[pool - 1].vsi;
3319
3320         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3321         if (ret != I40E_SUCCESS) {
3322                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3323                 return -ENODEV;
3324         }
3325         return 0;
3326 }
3327
3328 /* Remove a MAC address, and update filters */
3329 static void
3330 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3331 {
3332         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3333         struct i40e_vsi *vsi;
3334         struct rte_eth_dev_data *data = dev->data;
3335         struct ether_addr *macaddr;
3336         int ret;
3337         uint32_t i;
3338         uint64_t pool_sel;
3339
3340         macaddr = &(data->mac_addrs[index]);
3341
3342         pool_sel = dev->data->mac_pool_sel[index];
3343
3344         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3345                 if (pool_sel & (1ULL << i)) {
3346                         if (i == 0)
3347                                 vsi = pf->main_vsi;
3348                         else {
3349                                 /* No VMDQ pool enabled or configured */
3350                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3351                                         (i > pf->nb_cfg_vmdq_vsi)) {
3352                                         PMD_DRV_LOG(ERR,
3353                                                 "No VMDQ pool enabled/configured");
3354                                         return;
3355                                 }
3356                                 vsi = pf->vmdq[i - 1].vsi;
3357                         }
3358                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3359
3360                         if (ret) {
3361                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3362                                 return;
3363                         }
3364                 }
3365         }
3366 }
3367
3368 /* Set perfect match or hash match of MAC and VLAN for a VF */
3369 static int
3370 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3371                  struct rte_eth_mac_filter *filter,
3372                  bool add)
3373 {
3374         struct i40e_hw *hw;
3375         struct i40e_mac_filter_info mac_filter;
3376         struct ether_addr old_mac;
3377         struct ether_addr *new_mac;
3378         struct i40e_pf_vf *vf = NULL;
3379         uint16_t vf_id;
3380         int ret;
3381
3382         if (pf == NULL) {
3383                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3384                 return -EINVAL;
3385         }
3386         hw = I40E_PF_TO_HW(pf);
3387
3388         if (filter == NULL) {
3389                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3390                 return -EINVAL;
3391         }
3392
3393         new_mac = &filter->mac_addr;
3394
3395         if (is_zero_ether_addr(new_mac)) {
3396                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3397                 return -EINVAL;
3398         }
3399
3400         vf_id = filter->dst_id;
3401
3402         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3403                 PMD_DRV_LOG(ERR, "Invalid argument.");
3404                 return -EINVAL;
3405         }
3406         vf = &pf->vfs[vf_id];
3407
3408         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3409                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3410                 return -EINVAL;
3411         }
3412
3413         if (add) {
3414                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3415                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3416                                 ETHER_ADDR_LEN);
3417                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3418                                  ETHER_ADDR_LEN);
3419
3420                 mac_filter.filter_type = filter->filter_type;
3421                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3422                 if (ret != I40E_SUCCESS) {
3423                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3424                         return -1;
3425                 }
3426                 ether_addr_copy(new_mac, &pf->dev_addr);
3427         } else {
3428                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3429                                 ETHER_ADDR_LEN);
3430                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3431                 if (ret != I40E_SUCCESS) {
3432                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3433                         return -1;
3434                 }
3435
3436                 /* Clear device address as it has been removed */
3437                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3438                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3439         }
3440
3441         return 0;
3442 }
3443
3444 /* MAC filter handle */
3445 static int
3446 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3447                 void *arg)
3448 {
3449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3450         struct rte_eth_mac_filter *filter;
3451         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3452         int ret = I40E_NOT_SUPPORTED;
3453
3454         filter = (struct rte_eth_mac_filter *)(arg);
3455
3456         switch (filter_op) {
3457         case RTE_ETH_FILTER_NOP:
3458                 ret = I40E_SUCCESS;
3459                 break;
3460         case RTE_ETH_FILTER_ADD:
3461                 i40e_pf_disable_irq0(hw);
3462                 if (filter->is_vf)
3463                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3464                 i40e_pf_enable_irq0(hw);
3465                 break;
3466         case RTE_ETH_FILTER_DELETE:
3467                 i40e_pf_disable_irq0(hw);
3468                 if (filter->is_vf)
3469                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3470                 i40e_pf_enable_irq0(hw);
3471                 break;
3472         default:
3473                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3474                 ret = I40E_ERR_PARAM;
3475                 break;
3476         }
3477
3478         return ret;
3479 }
3480
3481 static int
3482 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3483 {
3484         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3485         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3486         int ret;
3487
3488         if (!lut)
3489                 return -EINVAL;
3490
3491         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3492                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3493                                           lut, lut_size);
3494                 if (ret) {
3495                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3496                         return ret;
3497                 }
3498         } else {
3499                 uint32_t *lut_dw = (uint32_t *)lut;
3500                 uint16_t i, lut_size_dw = lut_size / 4;
3501
3502                 for (i = 0; i < lut_size_dw; i++)
3503                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3504         }
3505
3506         return 0;
3507 }
3508
3509 static int
3510 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3511 {
3512         struct i40e_pf *pf;
3513         struct i40e_hw *hw;
3514         int ret;
3515
3516         if (!vsi || !lut)
3517                 return -EINVAL;
3518
3519         pf = I40E_VSI_TO_PF(vsi);
3520         hw = I40E_VSI_TO_HW(vsi);
3521
3522         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3523                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3524                                           lut, lut_size);
3525                 if (ret) {
3526                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3527                         return ret;
3528                 }
3529         } else {
3530                 uint32_t *lut_dw = (uint32_t *)lut;
3531                 uint16_t i, lut_size_dw = lut_size / 4;
3532
3533                 for (i = 0; i < lut_size_dw; i++)
3534                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3535                 I40E_WRITE_FLUSH(hw);
3536         }
3537
3538         return 0;
3539 }
3540
3541 static int
3542 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3543                          struct rte_eth_rss_reta_entry64 *reta_conf,
3544                          uint16_t reta_size)
3545 {
3546         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3547         uint16_t i, lut_size = pf->hash_lut_size;
3548         uint16_t idx, shift;
3549         uint8_t *lut;
3550         int ret;
3551
3552         if (reta_size != lut_size ||
3553                 reta_size > ETH_RSS_RETA_SIZE_512) {
3554                 PMD_DRV_LOG(ERR,
3555                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3556                         reta_size, lut_size);
3557                 return -EINVAL;
3558         }
3559
3560         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3561         if (!lut) {
3562                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3563                 return -ENOMEM;
3564         }
3565         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3566         if (ret)
3567                 goto out;
3568         for (i = 0; i < reta_size; i++) {
3569                 idx = i / RTE_RETA_GROUP_SIZE;
3570                 shift = i % RTE_RETA_GROUP_SIZE;
3571                 if (reta_conf[idx].mask & (1ULL << shift))
3572                         lut[i] = reta_conf[idx].reta[shift];
3573         }
3574         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3575
3576 out:
3577         rte_free(lut);
3578
3579         return ret;
3580 }
3581
3582 static int
3583 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3584                         struct rte_eth_rss_reta_entry64 *reta_conf,
3585                         uint16_t reta_size)
3586 {
3587         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3588         uint16_t i, lut_size = pf->hash_lut_size;
3589         uint16_t idx, shift;
3590         uint8_t *lut;
3591         int ret;
3592
3593         if (reta_size != lut_size ||
3594                 reta_size > ETH_RSS_RETA_SIZE_512) {
3595                 PMD_DRV_LOG(ERR,
3596                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3597                         reta_size, lut_size);
3598                 return -EINVAL;
3599         }
3600
3601         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3602         if (!lut) {
3603                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3604                 return -ENOMEM;
3605         }
3606
3607         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3608         if (ret)
3609                 goto out;
3610         for (i = 0; i < reta_size; i++) {
3611                 idx = i / RTE_RETA_GROUP_SIZE;
3612                 shift = i % RTE_RETA_GROUP_SIZE;
3613                 if (reta_conf[idx].mask & (1ULL << shift))
3614                         reta_conf[idx].reta[shift] = lut[i];
3615         }
3616
3617 out:
3618         rte_free(lut);
3619
3620         return ret;
3621 }
3622
3623 /**
3624  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3625  * @hw:   pointer to the HW structure
3626  * @mem:  pointer to mem struct to fill out
3627  * @size: size of memory requested
3628  * @alignment: what to align the allocation to
3629  **/
3630 enum i40e_status_code
3631 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3632                         struct i40e_dma_mem *mem,
3633                         u64 size,
3634                         u32 alignment)
3635 {
3636         const struct rte_memzone *mz = NULL;
3637         char z_name[RTE_MEMZONE_NAMESIZE];
3638
3639         if (!mem)
3640                 return I40E_ERR_PARAM;
3641
3642         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3643         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3644                                          alignment, RTE_PGSIZE_2M);
3645         if (!mz)
3646                 return I40E_ERR_NO_MEMORY;
3647
3648         mem->size = size;
3649         mem->va = mz->addr;
3650         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3651         mem->zone = (const void *)mz;
3652         PMD_DRV_LOG(DEBUG,
3653                 "memzone %s allocated with physical address: %"PRIu64,
3654                 mz->name, mem->pa);
3655
3656         return I40E_SUCCESS;
3657 }
3658
3659 /**
3660  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3661  * @hw:   pointer to the HW structure
3662  * @mem:  ptr to mem struct to free
3663  **/
3664 enum i40e_status_code
3665 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3666                     struct i40e_dma_mem *mem)
3667 {
3668         if (!mem)
3669                 return I40E_ERR_PARAM;
3670
3671         PMD_DRV_LOG(DEBUG,
3672                 "memzone %s to be freed with physical address: %"PRIu64,
3673                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3674         rte_memzone_free((const struct rte_memzone *)mem->zone);
3675         mem->zone = NULL;
3676         mem->va = NULL;
3677         mem->pa = (u64)0;
3678
3679         return I40E_SUCCESS;
3680 }
3681
3682 /**
3683  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3684  * @hw:   pointer to the HW structure
3685  * @mem:  pointer to mem struct to fill out
3686  * @size: size of memory requested
3687  **/
3688 enum i40e_status_code
3689 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3690                          struct i40e_virt_mem *mem,
3691                          u32 size)
3692 {
3693         if (!mem)
3694                 return I40E_ERR_PARAM;
3695
3696         mem->size = size;
3697         mem->va = rte_zmalloc("i40e", size, 0);
3698
3699         if (mem->va)
3700                 return I40E_SUCCESS;
3701         else
3702                 return I40E_ERR_NO_MEMORY;
3703 }
3704
3705 /**
3706  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3707  * @hw:   pointer to the HW structure
3708  * @mem:  pointer to mem struct to free
3709  **/
3710 enum i40e_status_code
3711 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3712                      struct i40e_virt_mem *mem)
3713 {
3714         if (!mem)
3715                 return I40E_ERR_PARAM;
3716
3717         rte_free(mem->va);
3718         mem->va = NULL;
3719
3720         return I40E_SUCCESS;
3721 }
3722
3723 void
3724 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3725 {
3726         rte_spinlock_init(&sp->spinlock);
3727 }
3728
3729 void
3730 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3731 {
3732         rte_spinlock_lock(&sp->spinlock);
3733 }
3734
3735 void
3736 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3737 {
3738         rte_spinlock_unlock(&sp->spinlock);
3739 }
3740
3741 void
3742 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3743 {
3744         return;
3745 }
3746
3747 /**
3748  * Get the hardware capabilities, which will be parsed
3749  * and saved into struct i40e_hw.
3750  */
3751 static int
3752 i40e_get_cap(struct i40e_hw *hw)
3753 {
3754         struct i40e_aqc_list_capabilities_element_resp *buf;
3755         uint16_t len, size = 0;
3756         int ret;
3757
3758         /* Calculate a huge enough buff for saving response data temporarily */
3759         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3760                                                 I40E_MAX_CAP_ELE_NUM;
3761         buf = rte_zmalloc("i40e", len, 0);
3762         if (!buf) {
3763                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3764                 return I40E_ERR_NO_MEMORY;
3765         }
3766
3767         /* Get, parse the capabilities and save it to hw */
3768         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3769                         i40e_aqc_opc_list_func_capabilities, NULL);
3770         if (ret != I40E_SUCCESS)
3771                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3772
3773         /* Free the temporary buffer after being used */
3774         rte_free(buf);
3775
3776         return ret;
3777 }
3778
3779 static int
3780 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3781 {
3782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3783         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3784         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3785         uint16_t qp_count = 0, vsi_count = 0;
3786
3787         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3788                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3789                 return -EINVAL;
3790         }
3791         /* Add the parameter init for LFC */
3792         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3793         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3794         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3795
3796         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3797         pf->max_num_vsi = hw->func_caps.num_vsis;
3798         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3799         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3800         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3801
3802         /* FDir queue/VSI allocation */
3803         pf->fdir_qp_offset = 0;
3804         if (hw->func_caps.fd) {
3805                 pf->flags |= I40E_FLAG_FDIR;
3806                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3807         } else {
3808                 pf->fdir_nb_qps = 0;
3809         }
3810         qp_count += pf->fdir_nb_qps;
3811         vsi_count += 1;
3812
3813         /* LAN queue/VSI allocation */
3814         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3815         if (!hw->func_caps.rss) {
3816                 pf->lan_nb_qps = 1;
3817         } else {
3818                 pf->flags |= I40E_FLAG_RSS;
3819                 if (hw->mac.type == I40E_MAC_X722)
3820                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3821                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3822         }
3823         qp_count += pf->lan_nb_qps;
3824         vsi_count += 1;
3825
3826         /* VF queue/VSI allocation */
3827         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3828         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3829                 pf->flags |= I40E_FLAG_SRIOV;
3830                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3831                 pf->vf_num = pci_dev->max_vfs;
3832                 PMD_DRV_LOG(DEBUG,
3833                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3834                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3835         } else {
3836                 pf->vf_nb_qps = 0;
3837                 pf->vf_num = 0;
3838         }
3839         qp_count += pf->vf_nb_qps * pf->vf_num;
3840         vsi_count += pf->vf_num;
3841
3842         /* VMDq queue/VSI allocation */
3843         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3844         pf->vmdq_nb_qps = 0;
3845         pf->max_nb_vmdq_vsi = 0;
3846         if (hw->func_caps.vmdq) {
3847                 if (qp_count < hw->func_caps.num_tx_qp &&
3848                         vsi_count < hw->func_caps.num_vsis) {
3849                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3850                                 qp_count) / pf->vmdq_nb_qp_max;
3851
3852                         /* Limit the maximum number of VMDq vsi to the maximum
3853                          * ethdev can support
3854                          */
3855                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3856                                 hw->func_caps.num_vsis - vsi_count);
3857                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3858                                 ETH_64_POOLS);
3859                         if (pf->max_nb_vmdq_vsi) {
3860                                 pf->flags |= I40E_FLAG_VMDQ;
3861                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3862                                 PMD_DRV_LOG(DEBUG,
3863                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3864                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3865                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3866                         } else {
3867                                 PMD_DRV_LOG(INFO,
3868                                         "No enough queues left for VMDq");
3869                         }
3870                 } else {
3871                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3872                 }
3873         }
3874         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3875         vsi_count += pf->max_nb_vmdq_vsi;
3876
3877         if (hw->func_caps.dcb)
3878                 pf->flags |= I40E_FLAG_DCB;
3879
3880         if (qp_count > hw->func_caps.num_tx_qp) {
3881                 PMD_DRV_LOG(ERR,
3882                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3883                         qp_count, hw->func_caps.num_tx_qp);
3884                 return -EINVAL;
3885         }
3886         if (vsi_count > hw->func_caps.num_vsis) {
3887                 PMD_DRV_LOG(ERR,
3888                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3889                         vsi_count, hw->func_caps.num_vsis);
3890                 return -EINVAL;
3891         }
3892
3893         return 0;
3894 }
3895
3896 static int
3897 i40e_pf_get_switch_config(struct i40e_pf *pf)
3898 {
3899         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3900         struct i40e_aqc_get_switch_config_resp *switch_config;
3901         struct i40e_aqc_switch_config_element_resp *element;
3902         uint16_t start_seid = 0, num_reported;
3903         int ret;
3904
3905         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3906                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3907         if (!switch_config) {
3908                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3909                 return -ENOMEM;
3910         }
3911
3912         /* Get the switch configurations */
3913         ret = i40e_aq_get_switch_config(hw, switch_config,
3914                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3915         if (ret != I40E_SUCCESS) {
3916                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3917                 goto fail;
3918         }
3919         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3920         if (num_reported != 1) { /* The number should be 1 */
3921                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3922                 goto fail;
3923         }
3924
3925         /* Parse the switch configuration elements */
3926         element = &(switch_config->element[0]);
3927         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3928                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3929                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3930         } else
3931                 PMD_DRV_LOG(INFO, "Unknown element type");
3932
3933 fail:
3934         rte_free(switch_config);
3935
3936         return ret;
3937 }
3938
3939 static int
3940 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3941                         uint32_t num)
3942 {
3943         struct pool_entry *entry;
3944
3945         if (pool == NULL || num == 0)
3946                 return -EINVAL;
3947
3948         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3949         if (entry == NULL) {
3950                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3951                 return -ENOMEM;
3952         }
3953
3954         /* queue heap initialize */
3955         pool->num_free = num;
3956         pool->num_alloc = 0;
3957         pool->base = base;
3958         LIST_INIT(&pool->alloc_list);
3959         LIST_INIT(&pool->free_list);
3960
3961         /* Initialize element  */
3962         entry->base = 0;
3963         entry->len = num;
3964
3965         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3966         return 0;
3967 }
3968
3969 static void
3970 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3971 {
3972         struct pool_entry *entry, *next_entry;
3973
3974         if (pool == NULL)
3975                 return;
3976
3977         for (entry = LIST_FIRST(&pool->alloc_list);
3978                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3979                         entry = next_entry) {
3980                 LIST_REMOVE(entry, next);
3981                 rte_free(entry);
3982         }
3983
3984         for (entry = LIST_FIRST(&pool->free_list);
3985                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3986                         entry = next_entry) {
3987                 LIST_REMOVE(entry, next);
3988                 rte_free(entry);
3989         }
3990
3991         pool->num_free = 0;
3992         pool->num_alloc = 0;
3993         pool->base = 0;
3994         LIST_INIT(&pool->alloc_list);
3995         LIST_INIT(&pool->free_list);
3996 }
3997
3998 static int
3999 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4000                        uint32_t base)
4001 {
4002         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4003         uint32_t pool_offset;
4004         int insert;
4005
4006         if (pool == NULL) {
4007                 PMD_DRV_LOG(ERR, "Invalid parameter");
4008                 return -EINVAL;
4009         }
4010
4011         pool_offset = base - pool->base;
4012         /* Lookup in alloc list */
4013         LIST_FOREACH(entry, &pool->alloc_list, next) {
4014                 if (entry->base == pool_offset) {
4015                         valid_entry = entry;
4016                         LIST_REMOVE(entry, next);
4017                         break;
4018                 }
4019         }
4020
4021         /* Not find, return */
4022         if (valid_entry == NULL) {
4023                 PMD_DRV_LOG(ERR, "Failed to find entry");
4024                 return -EINVAL;
4025         }
4026
4027         /**
4028          * Found it, move it to free list  and try to merge.
4029          * In order to make merge easier, always sort it by qbase.
4030          * Find adjacent prev and last entries.
4031          */
4032         prev = next = NULL;
4033         LIST_FOREACH(entry, &pool->free_list, next) {
4034                 if (entry->base > valid_entry->base) {
4035                         next = entry;
4036                         break;
4037                 }
4038                 prev = entry;
4039         }
4040
4041         insert = 0;
4042         /* Try to merge with next one*/
4043         if (next != NULL) {
4044                 /* Merge with next one */
4045                 if (valid_entry->base + valid_entry->len == next->base) {
4046                         next->base = valid_entry->base;
4047                         next->len += valid_entry->len;
4048                         rte_free(valid_entry);
4049                         valid_entry = next;
4050                         insert = 1;
4051                 }
4052         }
4053
4054         if (prev != NULL) {
4055                 /* Merge with previous one */
4056                 if (prev->base + prev->len == valid_entry->base) {
4057                         prev->len += valid_entry->len;
4058                         /* If it merge with next one, remove next node */
4059                         if (insert == 1) {
4060                                 LIST_REMOVE(valid_entry, next);
4061                                 rte_free(valid_entry);
4062                         } else {
4063                                 rte_free(valid_entry);
4064                                 insert = 1;
4065                         }
4066                 }
4067         }
4068
4069         /* Not find any entry to merge, insert */
4070         if (insert == 0) {
4071                 if (prev != NULL)
4072                         LIST_INSERT_AFTER(prev, valid_entry, next);
4073                 else if (next != NULL)
4074                         LIST_INSERT_BEFORE(next, valid_entry, next);
4075                 else /* It's empty list, insert to head */
4076                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4077         }
4078
4079         pool->num_free += valid_entry->len;
4080         pool->num_alloc -= valid_entry->len;
4081
4082         return 0;
4083 }
4084
4085 static int
4086 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4087                        uint16_t num)
4088 {
4089         struct pool_entry *entry, *valid_entry;
4090
4091         if (pool == NULL || num == 0) {
4092                 PMD_DRV_LOG(ERR, "Invalid parameter");
4093                 return -EINVAL;
4094         }
4095
4096         if (pool->num_free < num) {
4097                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4098                             num, pool->num_free);
4099                 return -ENOMEM;
4100         }
4101
4102         valid_entry = NULL;
4103         /* Lookup  in free list and find most fit one */
4104         LIST_FOREACH(entry, &pool->free_list, next) {
4105                 if (entry->len >= num) {
4106                         /* Find best one */
4107                         if (entry->len == num) {
4108                                 valid_entry = entry;
4109                                 break;
4110                         }
4111                         if (valid_entry == NULL || valid_entry->len > entry->len)
4112                                 valid_entry = entry;
4113                 }
4114         }
4115
4116         /* Not find one to satisfy the request, return */
4117         if (valid_entry == NULL) {
4118                 PMD_DRV_LOG(ERR, "No valid entry found");
4119                 return -ENOMEM;
4120         }
4121         /**
4122          * The entry have equal queue number as requested,
4123          * remove it from alloc_list.
4124          */
4125         if (valid_entry->len == num) {
4126                 LIST_REMOVE(valid_entry, next);
4127         } else {
4128                 /**
4129                  * The entry have more numbers than requested,
4130                  * create a new entry for alloc_list and minus its
4131                  * queue base and number in free_list.
4132                  */
4133                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4134                 if (entry == NULL) {
4135                         PMD_DRV_LOG(ERR,
4136                                 "Failed to allocate memory for resource pool");
4137                         return -ENOMEM;
4138                 }
4139                 entry->base = valid_entry->base;
4140                 entry->len = num;
4141                 valid_entry->base += num;
4142                 valid_entry->len -= num;
4143                 valid_entry = entry;
4144         }
4145
4146         /* Insert it into alloc list, not sorted */
4147         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4148
4149         pool->num_free -= valid_entry->len;
4150         pool->num_alloc += valid_entry->len;
4151
4152         return valid_entry->base + pool->base;
4153 }
4154
4155 /**
4156  * bitmap_is_subset - Check whether src2 is subset of src1
4157  **/
4158 static inline int
4159 bitmap_is_subset(uint8_t src1, uint8_t src2)
4160 {
4161         return !((src1 ^ src2) & src2);
4162 }
4163
4164 static enum i40e_status_code
4165 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4166 {
4167         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4168
4169         /* If DCB is not supported, only default TC is supported */
4170         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4171                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4172                 return I40E_NOT_SUPPORTED;
4173         }
4174
4175         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4176                 PMD_DRV_LOG(ERR,
4177                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4178                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4179                 return I40E_NOT_SUPPORTED;
4180         }
4181         return I40E_SUCCESS;
4182 }
4183
4184 int
4185 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4186                                 struct i40e_vsi_vlan_pvid_info *info)
4187 {
4188         struct i40e_hw *hw;
4189         struct i40e_vsi_context ctxt;
4190         uint8_t vlan_flags = 0;
4191         int ret;
4192
4193         if (vsi == NULL || info == NULL) {
4194                 PMD_DRV_LOG(ERR, "invalid parameters");
4195                 return I40E_ERR_PARAM;
4196         }
4197
4198         if (info->on) {
4199                 vsi->info.pvid = info->config.pvid;
4200                 /**
4201                  * If insert pvid is enabled, only tagged pkts are
4202                  * allowed to be sent out.
4203                  */
4204                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4205                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4206         } else {
4207                 vsi->info.pvid = 0;
4208                 if (info->config.reject.tagged == 0)
4209                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4210
4211                 if (info->config.reject.untagged == 0)
4212                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4213         }
4214         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4215                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4216         vsi->info.port_vlan_flags |= vlan_flags;
4217         vsi->info.valid_sections =
4218                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4219         memset(&ctxt, 0, sizeof(ctxt));
4220         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4221         ctxt.seid = vsi->seid;
4222
4223         hw = I40E_VSI_TO_HW(vsi);
4224         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4225         if (ret != I40E_SUCCESS)
4226                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4227
4228         return ret;
4229 }
4230
4231 static int
4232 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4233 {
4234         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4235         int i, ret;
4236         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4237
4238         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4239         if (ret != I40E_SUCCESS)
4240                 return ret;
4241
4242         if (!vsi->seid) {
4243                 PMD_DRV_LOG(ERR, "seid not valid");
4244                 return -EINVAL;
4245         }
4246
4247         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4248         tc_bw_data.tc_valid_bits = enabled_tcmap;
4249         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4250                 tc_bw_data.tc_bw_credits[i] =
4251                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4252
4253         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4254         if (ret != I40E_SUCCESS) {
4255                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4256                 return ret;
4257         }
4258
4259         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4260                                         sizeof(vsi->info.qs_handle));
4261         return I40E_SUCCESS;
4262 }
4263
4264 static enum i40e_status_code
4265 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4266                                  struct i40e_aqc_vsi_properties_data *info,
4267                                  uint8_t enabled_tcmap)
4268 {
4269         enum i40e_status_code ret;
4270         int i, total_tc = 0;
4271         uint16_t qpnum_per_tc, bsf, qp_idx;
4272
4273         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4274         if (ret != I40E_SUCCESS)
4275                 return ret;
4276
4277         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4278                 if (enabled_tcmap & (1 << i))
4279                         total_tc++;
4280         vsi->enabled_tc = enabled_tcmap;
4281
4282         /* Number of queues per enabled TC */
4283         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4284         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4285         bsf = rte_bsf32(qpnum_per_tc);
4286
4287         /* Adjust the queue number to actual queues that can be applied */
4288         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4289                 vsi->nb_qps = qpnum_per_tc * total_tc;
4290
4291         /**
4292          * Configure TC and queue mapping parameters, for enabled TC,
4293          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4294          * default queue will serve it.
4295          */
4296         qp_idx = 0;
4297         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4298                 if (vsi->enabled_tc & (1 << i)) {
4299                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4300                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4301                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4302                         qp_idx += qpnum_per_tc;
4303                 } else
4304                         info->tc_mapping[i] = 0;
4305         }
4306
4307         /* Associate queue number with VSI */
4308         if (vsi->type == I40E_VSI_SRIOV) {
4309                 info->mapping_flags |=
4310                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4311                 for (i = 0; i < vsi->nb_qps; i++)
4312                         info->queue_mapping[i] =
4313                                 rte_cpu_to_le_16(vsi->base_queue + i);
4314         } else {
4315                 info->mapping_flags |=
4316                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4317                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4318         }
4319         info->valid_sections |=
4320                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4321
4322         return I40E_SUCCESS;
4323 }
4324
4325 static int
4326 i40e_veb_release(struct i40e_veb *veb)
4327 {
4328         struct i40e_vsi *vsi;
4329         struct i40e_hw *hw;
4330
4331         if (veb == NULL)
4332                 return -EINVAL;
4333
4334         if (!TAILQ_EMPTY(&veb->head)) {
4335                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4336                 return -EACCES;
4337         }
4338         /* associate_vsi field is NULL for floating VEB */
4339         if (veb->associate_vsi != NULL) {
4340                 vsi = veb->associate_vsi;
4341                 hw = I40E_VSI_TO_HW(vsi);
4342
4343                 vsi->uplink_seid = veb->uplink_seid;
4344                 vsi->veb = NULL;
4345         } else {
4346                 veb->associate_pf->main_vsi->floating_veb = NULL;
4347                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4348         }
4349
4350         i40e_aq_delete_element(hw, veb->seid, NULL);
4351         rte_free(veb);
4352         return I40E_SUCCESS;
4353 }
4354
4355 /* Setup a veb */
4356 static struct i40e_veb *
4357 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4358 {
4359         struct i40e_veb *veb;
4360         int ret;
4361         struct i40e_hw *hw;
4362
4363         if (pf == NULL) {
4364                 PMD_DRV_LOG(ERR,
4365                             "veb setup failed, associated PF shouldn't null");
4366                 return NULL;
4367         }
4368         hw = I40E_PF_TO_HW(pf);
4369
4370         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4371         if (!veb) {
4372                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4373                 goto fail;
4374         }
4375
4376         veb->associate_vsi = vsi;
4377         veb->associate_pf = pf;
4378         TAILQ_INIT(&veb->head);
4379         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4380
4381         /* create floating veb if vsi is NULL */
4382         if (vsi != NULL) {
4383                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4384                                       I40E_DEFAULT_TCMAP, false,
4385                                       &veb->seid, false, NULL);
4386         } else {
4387                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4388                                       true, &veb->seid, false, NULL);
4389         }
4390
4391         if (ret != I40E_SUCCESS) {
4392                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4393                             hw->aq.asq_last_status);
4394                 goto fail;
4395         }
4396         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4397
4398         /* get statistics index */
4399         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4400                                 &veb->stats_idx, NULL, NULL, NULL);
4401         if (ret != I40E_SUCCESS) {
4402                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4403                             hw->aq.asq_last_status);
4404                 goto fail;
4405         }
4406         /* Get VEB bandwidth, to be implemented */
4407         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4408         if (vsi)
4409                 vsi->uplink_seid = veb->seid;
4410
4411         return veb;
4412 fail:
4413         rte_free(veb);
4414         return NULL;
4415 }
4416
4417 int
4418 i40e_vsi_release(struct i40e_vsi *vsi)
4419 {
4420         struct i40e_pf *pf;
4421         struct i40e_hw *hw;
4422         struct i40e_vsi_list *vsi_list;
4423         void *temp;
4424         int ret;
4425         struct i40e_mac_filter *f;
4426         uint16_t user_param;
4427
4428         if (!vsi)
4429                 return I40E_SUCCESS;
4430
4431         if (!vsi->adapter)
4432                 return -EFAULT;
4433
4434         user_param = vsi->user_param;
4435
4436         pf = I40E_VSI_TO_PF(vsi);
4437         hw = I40E_VSI_TO_HW(vsi);
4438
4439         /* VSI has child to attach, release child first */
4440         if (vsi->veb) {
4441                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4442                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4443                                 return -1;
4444                 }
4445                 i40e_veb_release(vsi->veb);
4446         }
4447
4448         if (vsi->floating_veb) {
4449                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4450                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4451                                 return -1;
4452                 }
4453         }
4454
4455         /* Remove all macvlan filters of the VSI */
4456         i40e_vsi_remove_all_macvlan_filter(vsi);
4457         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4458                 rte_free(f);
4459
4460         if (vsi->type != I40E_VSI_MAIN &&
4461             ((vsi->type != I40E_VSI_SRIOV) ||
4462             !pf->floating_veb_list[user_param])) {
4463                 /* Remove vsi from parent's sibling list */
4464                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4465                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4466                         return I40E_ERR_PARAM;
4467                 }
4468                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4469                                 &vsi->sib_vsi_list, list);
4470
4471                 /* Remove all switch element of the VSI */
4472                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4473                 if (ret != I40E_SUCCESS)
4474                         PMD_DRV_LOG(ERR, "Failed to delete element");
4475         }
4476
4477         if ((vsi->type == I40E_VSI_SRIOV) &&
4478             pf->floating_veb_list[user_param]) {
4479                 /* Remove vsi from parent's sibling list */
4480                 if (vsi->parent_vsi == NULL ||
4481                     vsi->parent_vsi->floating_veb == NULL) {
4482                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4483                         return I40E_ERR_PARAM;
4484                 }
4485                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4486                              &vsi->sib_vsi_list, list);
4487
4488                 /* Remove all switch element of the VSI */
4489                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4490                 if (ret != I40E_SUCCESS)
4491                         PMD_DRV_LOG(ERR, "Failed to delete element");
4492         }
4493
4494         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4495
4496         if (vsi->type != I40E_VSI_SRIOV)
4497                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4498         rte_free(vsi);
4499
4500         return I40E_SUCCESS;
4501 }
4502
4503 static int
4504 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4505 {
4506         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4507         struct i40e_aqc_remove_macvlan_element_data def_filter;
4508         struct i40e_mac_filter_info filter;
4509         int ret;
4510
4511         if (vsi->type != I40E_VSI_MAIN)
4512                 return I40E_ERR_CONFIG;
4513         memset(&def_filter, 0, sizeof(def_filter));
4514         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4515                                         ETH_ADDR_LEN);
4516         def_filter.vlan_tag = 0;
4517         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4518                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4519         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4520         if (ret != I40E_SUCCESS) {
4521                 struct i40e_mac_filter *f;
4522                 struct ether_addr *mac;
4523
4524                 PMD_DRV_LOG(DEBUG,
4525                             "Cannot remove the default macvlan filter");
4526                 /* It needs to add the permanent mac into mac list */
4527                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4528                 if (f == NULL) {
4529                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4530                         return I40E_ERR_NO_MEMORY;
4531                 }
4532                 mac = &f->mac_info.mac_addr;
4533                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4534                                 ETH_ADDR_LEN);
4535                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4536                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4537                 vsi->mac_num++;
4538
4539                 return ret;
4540         }
4541         (void)rte_memcpy(&filter.mac_addr,
4542                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4543         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4544         return i40e_vsi_add_mac(vsi, &filter);
4545 }
4546
4547 /*
4548  * i40e_vsi_get_bw_config - Query VSI BW Information
4549  * @vsi: the VSI to be queried
4550  *
4551  * Returns 0 on success, negative value on failure
4552  */
4553 static enum i40e_status_code
4554 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4555 {
4556         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4557         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4558         struct i40e_hw *hw = &vsi->adapter->hw;
4559         i40e_status ret;
4560         int i;
4561         uint32_t bw_max;
4562
4563         memset(&bw_config, 0, sizeof(bw_config));
4564         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4565         if (ret != I40E_SUCCESS) {
4566                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4567                             hw->aq.asq_last_status);
4568                 return ret;
4569         }
4570
4571         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4572         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4573                                         &ets_sla_config, NULL);
4574         if (ret != I40E_SUCCESS) {
4575                 PMD_DRV_LOG(ERR,
4576                         "VSI failed to get TC bandwdith configuration %u",
4577                         hw->aq.asq_last_status);
4578                 return ret;
4579         }
4580
4581         /* store and print out BW info */
4582         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4583         vsi->bw_info.bw_max = bw_config.max_bw;
4584         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4585         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4586         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4587                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4588                      I40E_16_BIT_WIDTH);
4589         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4590                 vsi->bw_info.bw_ets_share_credits[i] =
4591                                 ets_sla_config.share_credits[i];
4592                 vsi->bw_info.bw_ets_credits[i] =
4593                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4594                 /* 4 bits per TC, 4th bit is reserved */
4595                 vsi->bw_info.bw_ets_max[i] =
4596                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4597                                   RTE_LEN2MASK(3, uint8_t));
4598                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4599                             vsi->bw_info.bw_ets_share_credits[i]);
4600                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4601                             vsi->bw_info.bw_ets_credits[i]);
4602                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4603                             vsi->bw_info.bw_ets_max[i]);
4604         }
4605
4606         return I40E_SUCCESS;
4607 }
4608
4609 /* i40e_enable_pf_lb
4610  * @pf: pointer to the pf structure
4611  *
4612  * allow loopback on pf
4613  */
4614 static inline void
4615 i40e_enable_pf_lb(struct i40e_pf *pf)
4616 {
4617         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4618         struct i40e_vsi_context ctxt;
4619         int ret;
4620
4621         /* Use the FW API if FW >= v5.0 */
4622         if (hw->aq.fw_maj_ver < 5) {
4623                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4624                 return;
4625         }
4626
4627         memset(&ctxt, 0, sizeof(ctxt));
4628         ctxt.seid = pf->main_vsi_seid;
4629         ctxt.pf_num = hw->pf_id;
4630         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4631         if (ret) {
4632                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4633                             ret, hw->aq.asq_last_status);
4634                 return;
4635         }
4636         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4637         ctxt.info.valid_sections =
4638                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4639         ctxt.info.switch_id |=
4640                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4641
4642         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4643         if (ret)
4644                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4645                             hw->aq.asq_last_status);
4646 }
4647
4648 /* Setup a VSI */
4649 struct i40e_vsi *
4650 i40e_vsi_setup(struct i40e_pf *pf,
4651                enum i40e_vsi_type type,
4652                struct i40e_vsi *uplink_vsi,
4653                uint16_t user_param)
4654 {
4655         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4656         struct i40e_vsi *vsi;
4657         struct i40e_mac_filter_info filter;
4658         int ret;
4659         struct i40e_vsi_context ctxt;
4660         struct ether_addr broadcast =
4661                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4662
4663         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4664             uplink_vsi == NULL) {
4665                 PMD_DRV_LOG(ERR,
4666                         "VSI setup failed, VSI link shouldn't be NULL");
4667                 return NULL;
4668         }
4669
4670         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4671                 PMD_DRV_LOG(ERR,
4672                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4673                 return NULL;
4674         }
4675
4676         /* two situations
4677          * 1.type is not MAIN and uplink vsi is not NULL
4678          * If uplink vsi didn't setup VEB, create one first under veb field
4679          * 2.type is SRIOV and the uplink is NULL
4680          * If floating VEB is NULL, create one veb under floating veb field
4681          */
4682
4683         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4684             uplink_vsi->veb == NULL) {
4685                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4686
4687                 if (uplink_vsi->veb == NULL) {
4688                         PMD_DRV_LOG(ERR, "VEB setup failed");
4689                         return NULL;
4690                 }
4691                 /* set ALLOWLOOPBACk on pf, when veb is created */
4692                 i40e_enable_pf_lb(pf);
4693         }
4694
4695         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4696             pf->main_vsi->floating_veb == NULL) {
4697                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4698
4699                 if (pf->main_vsi->floating_veb == NULL) {
4700                         PMD_DRV_LOG(ERR, "VEB setup failed");
4701                         return NULL;
4702                 }
4703         }
4704
4705         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4706         if (!vsi) {
4707                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4708                 return NULL;
4709         }
4710         TAILQ_INIT(&vsi->mac_list);
4711         vsi->type = type;
4712         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4713         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4714         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4715         vsi->user_param = user_param;
4716         vsi->vlan_anti_spoof_on = 0;
4717         vsi->vlan_filter_on = 0;
4718         /* Allocate queues */
4719         switch (vsi->type) {
4720         case I40E_VSI_MAIN  :
4721                 vsi->nb_qps = pf->lan_nb_qps;
4722                 break;
4723         case I40E_VSI_SRIOV :
4724                 vsi->nb_qps = pf->vf_nb_qps;
4725                 break;
4726         case I40E_VSI_VMDQ2:
4727                 vsi->nb_qps = pf->vmdq_nb_qps;
4728                 break;
4729         case I40E_VSI_FDIR:
4730                 vsi->nb_qps = pf->fdir_nb_qps;
4731                 break;
4732         default:
4733                 goto fail_mem;
4734         }
4735         /*
4736          * The filter status descriptor is reported in rx queue 0,
4737          * while the tx queue for fdir filter programming has no
4738          * such constraints, can be non-zero queues.
4739          * To simplify it, choose FDIR vsi use queue 0 pair.
4740          * To make sure it will use queue 0 pair, queue allocation
4741          * need be done before this function is called
4742          */
4743         if (type != I40E_VSI_FDIR) {
4744                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4745                         if (ret < 0) {
4746                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4747                                                 vsi->seid, ret);
4748                                 goto fail_mem;
4749                         }
4750                         vsi->base_queue = ret;
4751         } else
4752                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4753
4754         /* VF has MSIX interrupt in VF range, don't allocate here */
4755         if (type == I40E_VSI_MAIN) {
4756                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4757                                           RTE_MIN(vsi->nb_qps,
4758                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4759                 if (ret < 0) {
4760                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4761                                     vsi->seid, ret);
4762                         goto fail_queue_alloc;
4763                 }
4764                 vsi->msix_intr = ret;
4765                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4766         } else if (type != I40E_VSI_SRIOV) {
4767                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4768                 if (ret < 0) {
4769                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4770                         goto fail_queue_alloc;
4771                 }
4772                 vsi->msix_intr = ret;
4773                 vsi->nb_msix = 1;
4774         } else {
4775                 vsi->msix_intr = 0;
4776                 vsi->nb_msix = 0;
4777         }
4778
4779         /* Add VSI */
4780         if (type == I40E_VSI_MAIN) {
4781                 /* For main VSI, no need to add since it's default one */
4782                 vsi->uplink_seid = pf->mac_seid;
4783                 vsi->seid = pf->main_vsi_seid;
4784                 /* Bind queues with specific MSIX interrupt */
4785                 /**
4786                  * Needs 2 interrupt at least, one for misc cause which will
4787                  * enabled from OS side, Another for queues binding the
4788                  * interrupt from device side only.
4789                  */
4790
4791                 /* Get default VSI parameters from hardware */
4792                 memset(&ctxt, 0, sizeof(ctxt));
4793                 ctxt.seid = vsi->seid;
4794                 ctxt.pf_num = hw->pf_id;
4795                 ctxt.uplink_seid = vsi->uplink_seid;
4796                 ctxt.vf_num = 0;
4797                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4798                 if (ret != I40E_SUCCESS) {
4799                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4800                         goto fail_msix_alloc;
4801                 }
4802                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4803                         sizeof(struct i40e_aqc_vsi_properties_data));
4804                 vsi->vsi_id = ctxt.vsi_number;
4805                 vsi->info.valid_sections = 0;
4806
4807                 /* Configure tc, enabled TC0 only */
4808                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4809                         I40E_SUCCESS) {
4810                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4811                         goto fail_msix_alloc;
4812                 }
4813
4814                 /* TC, queue mapping */
4815                 memset(&ctxt, 0, sizeof(ctxt));
4816                 vsi->info.valid_sections |=
4817                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4818                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4819                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4820                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4821                         sizeof(struct i40e_aqc_vsi_properties_data));
4822                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4823                                                 I40E_DEFAULT_TCMAP);
4824                 if (ret != I40E_SUCCESS) {
4825                         PMD_DRV_LOG(ERR,
4826                                 "Failed to configure TC queue mapping");
4827                         goto fail_msix_alloc;
4828                 }
4829                 ctxt.seid = vsi->seid;
4830                 ctxt.pf_num = hw->pf_id;
4831                 ctxt.uplink_seid = vsi->uplink_seid;
4832                 ctxt.vf_num = 0;
4833
4834                 /* Update VSI parameters */
4835                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4836                 if (ret != I40E_SUCCESS) {
4837                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4838                         goto fail_msix_alloc;
4839                 }
4840
4841                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4842                                                 sizeof(vsi->info.tc_mapping));
4843                 (void)rte_memcpy(&vsi->info.queue_mapping,
4844                                 &ctxt.info.queue_mapping,
4845                         sizeof(vsi->info.queue_mapping));
4846                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4847                 vsi->info.valid_sections = 0;
4848
4849                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4850                                 ETH_ADDR_LEN);
4851
4852                 /**
4853                  * Updating default filter settings are necessary to prevent
4854                  * reception of tagged packets.
4855                  * Some old firmware configurations load a default macvlan
4856                  * filter which accepts both tagged and untagged packets.
4857                  * The updating is to use a normal filter instead if needed.
4858                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4859                  * The firmware with correct configurations load the default
4860                  * macvlan filter which is expected and cannot be removed.
4861                  */
4862                 i40e_update_default_filter_setting(vsi);
4863                 i40e_config_qinq(hw, vsi);
4864         } else if (type == I40E_VSI_SRIOV) {
4865                 memset(&ctxt, 0, sizeof(ctxt));
4866                 /**
4867                  * For other VSI, the uplink_seid equals to uplink VSI's
4868                  * uplink_seid since they share same VEB
4869                  */
4870                 if (uplink_vsi == NULL)
4871                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4872                 else
4873                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4874                 ctxt.pf_num = hw->pf_id;
4875                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4876                 ctxt.uplink_seid = vsi->uplink_seid;
4877                 ctxt.connection_type = 0x1;
4878                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4879
4880                 /* Use the VEB configuration if FW >= v5.0 */
4881                 if (hw->aq.fw_maj_ver >= 5) {
4882                         /* Configure switch ID */
4883                         ctxt.info.valid_sections |=
4884                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4885                         ctxt.info.switch_id =
4886                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4887                 }
4888
4889                 /* Configure port/vlan */
4890                 ctxt.info.valid_sections |=
4891                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4892                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4893                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4894                                                 hw->func_caps.enabled_tcmap);
4895                 if (ret != I40E_SUCCESS) {
4896                         PMD_DRV_LOG(ERR,
4897                                 "Failed to configure TC queue mapping");
4898                         goto fail_msix_alloc;
4899                 }
4900
4901                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4902                 ctxt.info.valid_sections |=
4903                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4904                 /**
4905                  * Since VSI is not created yet, only configure parameter,
4906                  * will add vsi below.
4907                  */
4908
4909                 i40e_config_qinq(hw, vsi);
4910         } else if (type == I40E_VSI_VMDQ2) {
4911                 memset(&ctxt, 0, sizeof(ctxt));
4912                 /*
4913                  * For other VSI, the uplink_seid equals to uplink VSI's
4914                  * uplink_seid since they share same VEB
4915                  */
4916                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4917                 ctxt.pf_num = hw->pf_id;
4918                 ctxt.vf_num = 0;
4919                 ctxt.uplink_seid = vsi->uplink_seid;
4920                 ctxt.connection_type = 0x1;
4921                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4922
4923                 ctxt.info.valid_sections |=
4924                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4925                 /* user_param carries flag to enable loop back */
4926                 if (user_param) {
4927                         ctxt.info.switch_id =
4928                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4929                         ctxt.info.switch_id |=
4930                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4931                 }
4932
4933                 /* Configure port/vlan */
4934                 ctxt.info.valid_sections |=
4935                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4936                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4937                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4938                                                 I40E_DEFAULT_TCMAP);
4939                 if (ret != I40E_SUCCESS) {
4940                         PMD_DRV_LOG(ERR,
4941                                 "Failed to configure TC queue mapping");
4942                         goto fail_msix_alloc;
4943                 }
4944                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4945                 ctxt.info.valid_sections |=
4946                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4947         } else if (type == I40E_VSI_FDIR) {
4948                 memset(&ctxt, 0, sizeof(ctxt));
4949                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4950                 ctxt.pf_num = hw->pf_id;
4951                 ctxt.vf_num = 0;
4952                 ctxt.uplink_seid = vsi->uplink_seid;
4953                 ctxt.connection_type = 0x1;     /* regular data port */
4954                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4955                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4956                                                 I40E_DEFAULT_TCMAP);
4957                 if (ret != I40E_SUCCESS) {
4958                         PMD_DRV_LOG(ERR,
4959                                 "Failed to configure TC queue mapping.");
4960                         goto fail_msix_alloc;
4961                 }
4962                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4963                 ctxt.info.valid_sections |=
4964                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4965         } else {
4966                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4967                 goto fail_msix_alloc;
4968         }
4969
4970         if (vsi->type != I40E_VSI_MAIN) {
4971                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4972                 if (ret != I40E_SUCCESS) {
4973                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4974                                     hw->aq.asq_last_status);
4975                         goto fail_msix_alloc;
4976                 }
4977                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4978                 vsi->info.valid_sections = 0;
4979                 vsi->seid = ctxt.seid;
4980                 vsi->vsi_id = ctxt.vsi_number;
4981                 vsi->sib_vsi_list.vsi = vsi;
4982                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4983                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4984                                           &vsi->sib_vsi_list, list);
4985                 } else {
4986                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4987                                           &vsi->sib_vsi_list, list);
4988                 }
4989         }
4990
4991         /* MAC/VLAN configuration */
4992         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4993         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4994
4995         ret = i40e_vsi_add_mac(vsi, &filter);
4996         if (ret != I40E_SUCCESS) {
4997                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4998                 goto fail_msix_alloc;
4999         }
5000
5001         /* Get VSI BW information */
5002         i40e_vsi_get_bw_config(vsi);
5003         return vsi;
5004 fail_msix_alloc:
5005         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5006 fail_queue_alloc:
5007         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5008 fail_mem:
5009         rte_free(vsi);
5010         return NULL;
5011 }
5012
5013 /* Configure vlan filter on or off */
5014 int
5015 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5016 {
5017         int i, num;
5018         struct i40e_mac_filter *f;
5019         void *temp;
5020         struct i40e_mac_filter_info *mac_filter;
5021         enum rte_mac_filter_type desired_filter;
5022         int ret = I40E_SUCCESS;
5023
5024         if (on) {
5025                 /* Filter to match MAC and VLAN */
5026                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5027         } else {
5028                 /* Filter to match only MAC */
5029                 desired_filter = RTE_MAC_PERFECT_MATCH;
5030         }
5031
5032         num = vsi->mac_num;
5033
5034         mac_filter = rte_zmalloc("mac_filter_info_data",
5035                                  num * sizeof(*mac_filter), 0);
5036         if (mac_filter == NULL) {
5037                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5038                 return I40E_ERR_NO_MEMORY;
5039         }
5040
5041         i = 0;
5042
5043         /* Remove all existing mac */
5044         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5045                 mac_filter[i] = f->mac_info;
5046                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5047                 if (ret) {
5048                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5049                                     on ? "enable" : "disable");
5050                         goto DONE;
5051                 }
5052                 i++;
5053         }
5054
5055         /* Override with new filter */
5056         for (i = 0; i < num; i++) {
5057                 mac_filter[i].filter_type = desired_filter;
5058                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5059                 if (ret) {
5060                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5061                                     on ? "enable" : "disable");
5062                         goto DONE;
5063                 }
5064         }
5065
5066 DONE:
5067         rte_free(mac_filter);
5068         return ret;
5069 }
5070
5071 /* Configure vlan stripping on or off */
5072 int
5073 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5074 {
5075         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5076         struct i40e_vsi_context ctxt;
5077         uint8_t vlan_flags;
5078         int ret = I40E_SUCCESS;
5079
5080         /* Check if it has been already on or off */
5081         if (vsi->info.valid_sections &
5082                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5083                 if (on) {
5084                         if ((vsi->info.port_vlan_flags &
5085                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5086                                 return 0; /* already on */
5087                 } else {
5088                         if ((vsi->info.port_vlan_flags &
5089                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5090                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5091                                 return 0; /* already off */
5092                 }
5093         }
5094
5095         if (on)
5096                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5097         else
5098                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5099         vsi->info.valid_sections =
5100                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5101         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5102         vsi->info.port_vlan_flags |= vlan_flags;
5103         ctxt.seid = vsi->seid;
5104         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5105         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5106         if (ret)
5107                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5108                             on ? "enable" : "disable");
5109
5110         return ret;
5111 }
5112
5113 static int
5114 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5115 {
5116         struct rte_eth_dev_data *data = dev->data;
5117         int ret;
5118         int mask = 0;
5119
5120         /* Apply vlan offload setting */
5121         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5122         i40e_vlan_offload_set(dev, mask);
5123
5124         /* Apply double-vlan setting, not implemented yet */
5125
5126         /* Apply pvid setting */
5127         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5128                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5129         if (ret)
5130                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5131
5132         return ret;
5133 }
5134
5135 static int
5136 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5137 {
5138         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5139
5140         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5141 }
5142
5143 static int
5144 i40e_update_flow_control(struct i40e_hw *hw)
5145 {
5146 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5147         struct i40e_link_status link_status;
5148         uint32_t rxfc = 0, txfc = 0, reg;
5149         uint8_t an_info;
5150         int ret;
5151
5152         memset(&link_status, 0, sizeof(link_status));
5153         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5154         if (ret != I40E_SUCCESS) {
5155                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5156                 goto write_reg; /* Disable flow control */
5157         }
5158
5159         an_info = hw->phy.link_info.an_info;
5160         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5161                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5162                 ret = I40E_ERR_NOT_READY;
5163                 goto write_reg; /* Disable flow control */
5164         }
5165         /**
5166          * If link auto negotiation is enabled, flow control needs to
5167          * be configured according to it
5168          */
5169         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5170         case I40E_LINK_PAUSE_RXTX:
5171                 rxfc = 1;
5172                 txfc = 1;
5173                 hw->fc.current_mode = I40E_FC_FULL;
5174                 break;
5175         case I40E_AQ_LINK_PAUSE_RX:
5176                 rxfc = 1;
5177                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5178                 break;
5179         case I40E_AQ_LINK_PAUSE_TX:
5180                 txfc = 1;
5181                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5182                 break;
5183         default:
5184                 hw->fc.current_mode = I40E_FC_NONE;
5185                 break;
5186         }
5187
5188 write_reg:
5189         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5190                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5191         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5192         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5193         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5194         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5195
5196         return ret;
5197 }
5198
5199 /* PF setup */
5200 static int
5201 i40e_pf_setup(struct i40e_pf *pf)
5202 {
5203         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5204         struct i40e_filter_control_settings settings;
5205         struct i40e_vsi *vsi;
5206         int ret;
5207
5208         /* Clear all stats counters */
5209         pf->offset_loaded = FALSE;
5210         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5211         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5212         pf->internal_rx_bytes = 0;
5213         pf->internal_tx_bytes = 0;
5214         pf->internal_rx_bytes_offset = 0;
5215         pf->internal_tx_bytes_offset = 0;
5216
5217         ret = i40e_pf_get_switch_config(pf);
5218         if (ret != I40E_SUCCESS) {
5219                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5220                 return ret;
5221         }
5222         if (pf->flags & I40E_FLAG_FDIR) {
5223                 /* make queue allocated first, let FDIR use queue pair 0*/
5224                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5225                 if (ret != I40E_FDIR_QUEUE_ID) {
5226                         PMD_DRV_LOG(ERR,
5227                                 "queue allocation fails for FDIR: ret =%d",
5228                                 ret);
5229                         pf->flags &= ~I40E_FLAG_FDIR;
5230                 }
5231         }
5232         /*  main VSI setup */
5233         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5234         if (!vsi) {
5235                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5236                 return I40E_ERR_NOT_READY;
5237         }
5238         pf->main_vsi = vsi;
5239
5240         /* Configure filter control */
5241         memset(&settings, 0, sizeof(settings));
5242         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5243                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5244         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5245                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5246         else {
5247                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5248                         hw->func_caps.rss_table_size);
5249                 return I40E_ERR_PARAM;
5250         }
5251         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5252                 hw->func_caps.rss_table_size);
5253         pf->hash_lut_size = hw->func_caps.rss_table_size;
5254
5255         /* Enable ethtype and macvlan filters */
5256         settings.enable_ethtype = TRUE;
5257         settings.enable_macvlan = TRUE;
5258         ret = i40e_set_filter_control(hw, &settings);
5259         if (ret)
5260                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5261                                                                 ret);
5262
5263         /* Update flow control according to the auto negotiation */
5264         i40e_update_flow_control(hw);
5265
5266         return I40E_SUCCESS;
5267 }
5268
5269 int
5270 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5271 {
5272         uint32_t reg;
5273         uint16_t j;
5274
5275         /**
5276          * Set or clear TX Queue Disable flags,
5277          * which is required by hardware.
5278          */
5279         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5280         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5281
5282         /* Wait until the request is finished */
5283         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5284                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5285                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5286                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5287                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5288                                                         & 0x1))) {
5289                         break;
5290                 }
5291         }
5292         if (on) {
5293                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5294                         return I40E_SUCCESS; /* already on, skip next steps */
5295
5296                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5297                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5298         } else {
5299                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5300                         return I40E_SUCCESS; /* already off, skip next steps */
5301                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5302         }
5303         /* Write the register */
5304         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5305         /* Check the result */
5306         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5307                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5308                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5309                 if (on) {
5310                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5311                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5312                                 break;
5313                 } else {
5314                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5315                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5316                                 break;
5317                 }
5318         }
5319         /* Check if it is timeout */
5320         if (j >= I40E_CHK_Q_ENA_COUNT) {
5321                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5322                             (on ? "enable" : "disable"), q_idx);
5323                 return I40E_ERR_TIMEOUT;
5324         }
5325
5326         return I40E_SUCCESS;
5327 }
5328
5329 /* Swith on or off the tx queues */
5330 static int
5331 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5332 {
5333         struct rte_eth_dev_data *dev_data = pf->dev_data;
5334         struct i40e_tx_queue *txq;
5335         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5336         uint16_t i;
5337         int ret;
5338
5339         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5340                 txq = dev_data->tx_queues[i];
5341                 /* Don't operate the queue if not configured or
5342                  * if starting only per queue */
5343                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5344                         continue;
5345                 if (on)
5346                         ret = i40e_dev_tx_queue_start(dev, i);
5347                 else
5348                         ret = i40e_dev_tx_queue_stop(dev, i);
5349                 if ( ret != I40E_SUCCESS)
5350                         return ret;
5351         }
5352
5353         return I40E_SUCCESS;
5354 }
5355
5356 int
5357 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5358 {
5359         uint32_t reg;
5360         uint16_t j;
5361
5362         /* Wait until the request is finished */
5363         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5364                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5365                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5366                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5367                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5368                         break;
5369         }
5370
5371         if (on) {
5372                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5373                         return I40E_SUCCESS; /* Already on, skip next steps */
5374                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5375         } else {
5376                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5377                         return I40E_SUCCESS; /* Already off, skip next steps */
5378                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5379         }
5380
5381         /* Write the register */
5382         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5383         /* Check the result */
5384         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5385                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5386                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5387                 if (on) {
5388                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5389                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5390                                 break;
5391                 } else {
5392                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5393                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5394                                 break;
5395                 }
5396         }
5397
5398         /* Check if it is timeout */
5399         if (j >= I40E_CHK_Q_ENA_COUNT) {
5400                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5401                             (on ? "enable" : "disable"), q_idx);
5402                 return I40E_ERR_TIMEOUT;
5403         }
5404
5405         return I40E_SUCCESS;
5406 }
5407 /* Switch on or off the rx queues */
5408 static int
5409 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5410 {
5411         struct rte_eth_dev_data *dev_data = pf->dev_data;
5412         struct i40e_rx_queue *rxq;
5413         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5414         uint16_t i;
5415         int ret;
5416
5417         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5418                 rxq = dev_data->rx_queues[i];
5419                 /* Don't operate the queue if not configured or
5420                  * if starting only per queue */
5421                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5422                         continue;
5423                 if (on)
5424                         ret = i40e_dev_rx_queue_start(dev, i);
5425                 else
5426                         ret = i40e_dev_rx_queue_stop(dev, i);
5427                 if (ret != I40E_SUCCESS)
5428                         return ret;
5429         }
5430
5431         return I40E_SUCCESS;
5432 }
5433
5434 /* Switch on or off all the rx/tx queues */
5435 int
5436 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5437 {
5438         int ret;
5439
5440         if (on) {
5441                 /* enable rx queues before enabling tx queues */
5442                 ret = i40e_dev_switch_rx_queues(pf, on);
5443                 if (ret) {
5444                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5445                         return ret;
5446                 }
5447                 ret = i40e_dev_switch_tx_queues(pf, on);
5448         } else {
5449                 /* Stop tx queues before stopping rx queues */
5450                 ret = i40e_dev_switch_tx_queues(pf, on);
5451                 if (ret) {
5452                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5453                         return ret;
5454                 }
5455                 ret = i40e_dev_switch_rx_queues(pf, on);
5456         }
5457
5458         return ret;
5459 }
5460
5461 /* Initialize VSI for TX */
5462 static int
5463 i40e_dev_tx_init(struct i40e_pf *pf)
5464 {
5465         struct rte_eth_dev_data *data = pf->dev_data;
5466         uint16_t i;
5467         uint32_t ret = I40E_SUCCESS;
5468         struct i40e_tx_queue *txq;
5469
5470         for (i = 0; i < data->nb_tx_queues; i++) {
5471                 txq = data->tx_queues[i];
5472                 if (!txq || !txq->q_set)
5473                         continue;
5474                 ret = i40e_tx_queue_init(txq);
5475                 if (ret != I40E_SUCCESS)
5476                         break;
5477         }
5478         if (ret == I40E_SUCCESS)
5479                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5480                                      ->eth_dev);
5481
5482         return ret;
5483 }
5484
5485 /* Initialize VSI for RX */
5486 static int
5487 i40e_dev_rx_init(struct i40e_pf *pf)
5488 {
5489         struct rte_eth_dev_data *data = pf->dev_data;
5490         int ret = I40E_SUCCESS;
5491         uint16_t i;
5492         struct i40e_rx_queue *rxq;
5493
5494         i40e_pf_config_mq_rx(pf);
5495         for (i = 0; i < data->nb_rx_queues; i++) {
5496                 rxq = data->rx_queues[i];
5497                 if (!rxq || !rxq->q_set)
5498                         continue;
5499
5500                 ret = i40e_rx_queue_init(rxq);
5501                 if (ret != I40E_SUCCESS) {
5502                         PMD_DRV_LOG(ERR,
5503                                 "Failed to do RX queue initialization");
5504                         break;
5505                 }
5506         }
5507         if (ret == I40E_SUCCESS)
5508                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5509                                      ->eth_dev);
5510
5511         return ret;
5512 }
5513
5514 static int
5515 i40e_dev_rxtx_init(struct i40e_pf *pf)
5516 {
5517         int err;
5518
5519         err = i40e_dev_tx_init(pf);
5520         if (err) {
5521                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5522                 return err;
5523         }
5524         err = i40e_dev_rx_init(pf);
5525         if (err) {
5526                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5527                 return err;
5528         }
5529
5530         return err;
5531 }
5532
5533 static int
5534 i40e_vmdq_setup(struct rte_eth_dev *dev)
5535 {
5536         struct rte_eth_conf *conf = &dev->data->dev_conf;
5537         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5538         int i, err, conf_vsis, j, loop;
5539         struct i40e_vsi *vsi;
5540         struct i40e_vmdq_info *vmdq_info;
5541         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5542         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5543
5544         /*
5545          * Disable interrupt to avoid message from VF. Furthermore, it will
5546          * avoid race condition in VSI creation/destroy.
5547          */
5548         i40e_pf_disable_irq0(hw);
5549
5550         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5551                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5552                 return -ENOTSUP;
5553         }
5554
5555         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5556         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5557                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5558                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5559                         pf->max_nb_vmdq_vsi);
5560                 return -ENOTSUP;
5561         }
5562
5563         if (pf->vmdq != NULL) {
5564                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5565                 return 0;
5566         }
5567
5568         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5569                                 sizeof(*vmdq_info) * conf_vsis, 0);
5570
5571         if (pf->vmdq == NULL) {
5572                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5573                 return -ENOMEM;
5574         }
5575
5576         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5577
5578         /* Create VMDQ VSI */
5579         for (i = 0; i < conf_vsis; i++) {
5580                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5581                                 vmdq_conf->enable_loop_back);
5582                 if (vsi == NULL) {
5583                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5584                         err = -1;
5585                         goto err_vsi_setup;
5586                 }
5587                 vmdq_info = &pf->vmdq[i];
5588                 vmdq_info->pf = pf;
5589                 vmdq_info->vsi = vsi;
5590         }
5591         pf->nb_cfg_vmdq_vsi = conf_vsis;
5592
5593         /* Configure Vlan */
5594         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5595         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5596                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5597                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5598                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5599                                         vmdq_conf->pool_map[i].vlan_id, j);
5600
5601                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5602                                                 vmdq_conf->pool_map[i].vlan_id);
5603                                 if (err) {
5604                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5605                                         err = -1;
5606                                         goto err_vsi_setup;
5607                                 }
5608                         }
5609                 }
5610         }
5611
5612         i40e_pf_enable_irq0(hw);
5613
5614         return 0;
5615
5616 err_vsi_setup:
5617         for (i = 0; i < conf_vsis; i++)
5618                 if (pf->vmdq[i].vsi == NULL)
5619                         break;
5620                 else
5621                         i40e_vsi_release(pf->vmdq[i].vsi);
5622
5623         rte_free(pf->vmdq);
5624         pf->vmdq = NULL;
5625         i40e_pf_enable_irq0(hw);
5626         return err;
5627 }
5628
5629 static void
5630 i40e_stat_update_32(struct i40e_hw *hw,
5631                    uint32_t reg,
5632                    bool offset_loaded,
5633                    uint64_t *offset,
5634                    uint64_t *stat)
5635 {
5636         uint64_t new_data;
5637
5638         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5639         if (!offset_loaded)
5640                 *offset = new_data;
5641
5642         if (new_data >= *offset)
5643                 *stat = (uint64_t)(new_data - *offset);
5644         else
5645                 *stat = (uint64_t)((new_data +
5646                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5647 }
5648
5649 static void
5650 i40e_stat_update_48(struct i40e_hw *hw,
5651                    uint32_t hireg,
5652                    uint32_t loreg,
5653                    bool offset_loaded,
5654                    uint64_t *offset,
5655                    uint64_t *stat)
5656 {
5657         uint64_t new_data;
5658
5659         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5660         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5661                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5662
5663         if (!offset_loaded)
5664                 *offset = new_data;
5665
5666         if (new_data >= *offset)
5667                 *stat = new_data - *offset;
5668         else
5669                 *stat = (uint64_t)((new_data +
5670                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5671
5672         *stat &= I40E_48_BIT_MASK;
5673 }
5674
5675 /* Disable IRQ0 */
5676 void
5677 i40e_pf_disable_irq0(struct i40e_hw *hw)
5678 {
5679         /* Disable all interrupt types */
5680         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5681         I40E_WRITE_FLUSH(hw);
5682 }
5683
5684 /* Enable IRQ0 */
5685 void
5686 i40e_pf_enable_irq0(struct i40e_hw *hw)
5687 {
5688         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5689                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5690                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5691                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5692         I40E_WRITE_FLUSH(hw);
5693 }
5694
5695 static void
5696 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5697 {
5698         /* read pending request and disable first */
5699         i40e_pf_disable_irq0(hw);
5700         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5701         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5702                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5703
5704         if (no_queue)
5705                 /* Link no queues with irq0 */
5706                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5707                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5708 }
5709
5710 static void
5711 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5712 {
5713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5715         int i;
5716         uint16_t abs_vf_id;
5717         uint32_t index, offset, val;
5718
5719         if (!pf->vfs)
5720                 return;
5721         /**
5722          * Try to find which VF trigger a reset, use absolute VF id to access
5723          * since the reg is global register.
5724          */
5725         for (i = 0; i < pf->vf_num; i++) {
5726                 abs_vf_id = hw->func_caps.vf_base_id + i;
5727                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5728                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5729                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5730                 /* VFR event occured */
5731                 if (val & (0x1 << offset)) {
5732                         int ret;
5733
5734                         /* Clear the event first */
5735                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5736                                                         (0x1 << offset));
5737                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5738                         /**
5739                          * Only notify a VF reset event occured,
5740                          * don't trigger another SW reset
5741                          */
5742                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5743                         if (ret != I40E_SUCCESS)
5744                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5745                 }
5746         }
5747 }
5748
5749 static void
5750 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5751 {
5752         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5753         int i;
5754
5755         for (i = 0; i < pf->vf_num; i++)
5756                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5757 }
5758
5759 static void
5760 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5761 {
5762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5763         struct i40e_arq_event_info info;
5764         uint16_t pending, opcode;
5765         int ret;
5766
5767         info.buf_len = I40E_AQ_BUF_SZ;
5768         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5769         if (!info.msg_buf) {
5770                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5771                 return;
5772         }
5773
5774         pending = 1;
5775         while (pending) {
5776                 ret = i40e_clean_arq_element(hw, &info, &pending);
5777
5778                 if (ret != I40E_SUCCESS) {
5779                         PMD_DRV_LOG(INFO,
5780                                 "Failed to read msg from AdminQ, aq_err: %u",
5781                                 hw->aq.asq_last_status);
5782                         break;
5783                 }
5784                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5785
5786                 switch (opcode) {
5787                 case i40e_aqc_opc_send_msg_to_pf:
5788                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5789                         i40e_pf_host_handle_vf_msg(dev,
5790                                         rte_le_to_cpu_16(info.desc.retval),
5791                                         rte_le_to_cpu_32(info.desc.cookie_high),
5792                                         rte_le_to_cpu_32(info.desc.cookie_low),
5793                                         info.msg_buf,
5794                                         info.msg_len);
5795                         break;
5796                 case i40e_aqc_opc_get_link_status:
5797                         ret = i40e_dev_link_update(dev, 0);
5798                         if (!ret)
5799                                 _rte_eth_dev_callback_process(dev,
5800                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5801                         break;
5802                 default:
5803                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5804                                     opcode);
5805                         break;
5806                 }
5807         }
5808         rte_free(info.msg_buf);
5809 }
5810
5811 /**
5812  * Interrupt handler triggered by NIC  for handling
5813  * specific interrupt.
5814  *
5815  * @param handle
5816  *  Pointer to interrupt handle.
5817  * @param param
5818  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5819  *
5820  * @return
5821  *  void
5822  */
5823 static void
5824 i40e_dev_interrupt_handler(void *param)
5825 {
5826         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5827         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5828         uint32_t icr0;
5829
5830         /* Disable interrupt */
5831         i40e_pf_disable_irq0(hw);
5832
5833         /* read out interrupt causes */
5834         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5835
5836         /* No interrupt event indicated */
5837         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5838                 PMD_DRV_LOG(INFO, "No interrupt event");
5839                 goto done;
5840         }
5841         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5842                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5843         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5844                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5845         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5846                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5847         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5848                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5849         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5850                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5851         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5852                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5853         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5854                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5855
5856         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5857                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5858                 i40e_dev_handle_vfr_event(dev);
5859         }
5860         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5861                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5862                 i40e_dev_handle_aq_msg(dev);
5863         }
5864
5865 done:
5866         /* Enable interrupt */
5867         i40e_pf_enable_irq0(hw);
5868         rte_intr_enable(dev->intr_handle);
5869 }
5870
5871 int
5872 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5873                          struct i40e_macvlan_filter *filter,
5874                          int total)
5875 {
5876         int ele_num, ele_buff_size;
5877         int num, actual_num, i;
5878         uint16_t flags;
5879         int ret = I40E_SUCCESS;
5880         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5881         struct i40e_aqc_add_macvlan_element_data *req_list;
5882
5883         if (filter == NULL  || total == 0)
5884                 return I40E_ERR_PARAM;
5885         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5886         ele_buff_size = hw->aq.asq_buf_size;
5887
5888         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5889         if (req_list == NULL) {
5890                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5891                 return I40E_ERR_NO_MEMORY;
5892         }
5893
5894         num = 0;
5895         do {
5896                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5897                 memset(req_list, 0, ele_buff_size);
5898
5899                 for (i = 0; i < actual_num; i++) {
5900                         (void)rte_memcpy(req_list[i].mac_addr,
5901                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5902                         req_list[i].vlan_tag =
5903                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5904
5905                         switch (filter[num + i].filter_type) {
5906                         case RTE_MAC_PERFECT_MATCH:
5907                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5908                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5909                                 break;
5910                         case RTE_MACVLAN_PERFECT_MATCH:
5911                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5912                                 break;
5913                         case RTE_MAC_HASH_MATCH:
5914                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5915                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5916                                 break;
5917                         case RTE_MACVLAN_HASH_MATCH:
5918                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5919                                 break;
5920                         default:
5921                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5922                                 ret = I40E_ERR_PARAM;
5923                                 goto DONE;
5924                         }
5925
5926                         req_list[i].queue_number = 0;
5927
5928                         req_list[i].flags = rte_cpu_to_le_16(flags);
5929                 }
5930
5931                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5932                                                 actual_num, NULL);
5933                 if (ret != I40E_SUCCESS) {
5934                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5935                         goto DONE;
5936                 }
5937                 num += actual_num;
5938         } while (num < total);
5939
5940 DONE:
5941         rte_free(req_list);
5942         return ret;
5943 }
5944
5945 int
5946 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5947                             struct i40e_macvlan_filter *filter,
5948                             int total)
5949 {
5950         int ele_num, ele_buff_size;
5951         int num, actual_num, i;
5952         uint16_t flags;
5953         int ret = I40E_SUCCESS;
5954         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5955         struct i40e_aqc_remove_macvlan_element_data *req_list;
5956
5957         if (filter == NULL  || total == 0)
5958                 return I40E_ERR_PARAM;
5959
5960         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5961         ele_buff_size = hw->aq.asq_buf_size;
5962
5963         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5964         if (req_list == NULL) {
5965                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5966                 return I40E_ERR_NO_MEMORY;
5967         }
5968
5969         num = 0;
5970         do {
5971                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5972                 memset(req_list, 0, ele_buff_size);
5973
5974                 for (i = 0; i < actual_num; i++) {
5975                         (void)rte_memcpy(req_list[i].mac_addr,
5976                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5977                         req_list[i].vlan_tag =
5978                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5979
5980                         switch (filter[num + i].filter_type) {
5981                         case RTE_MAC_PERFECT_MATCH:
5982                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5983                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5984                                 break;
5985                         case RTE_MACVLAN_PERFECT_MATCH:
5986                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5987                                 break;
5988                         case RTE_MAC_HASH_MATCH:
5989                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5990                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5991                                 break;
5992                         case RTE_MACVLAN_HASH_MATCH:
5993                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5994                                 break;
5995                         default:
5996                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5997                                 ret = I40E_ERR_PARAM;
5998                                 goto DONE;
5999                         }
6000                         req_list[i].flags = rte_cpu_to_le_16(flags);
6001                 }
6002
6003                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6004                                                 actual_num, NULL);
6005                 if (ret != I40E_SUCCESS) {
6006                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6007                         goto DONE;
6008                 }
6009                 num += actual_num;
6010         } while (num < total);
6011
6012 DONE:
6013         rte_free(req_list);
6014         return ret;
6015 }
6016
6017 /* Find out specific MAC filter */
6018 static struct i40e_mac_filter *
6019 i40e_find_mac_filter(struct i40e_vsi *vsi,
6020                          struct ether_addr *macaddr)
6021 {
6022         struct i40e_mac_filter *f;
6023
6024         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6025                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6026                         return f;
6027         }
6028
6029         return NULL;
6030 }
6031
6032 static bool
6033 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6034                          uint16_t vlan_id)
6035 {
6036         uint32_t vid_idx, vid_bit;
6037
6038         if (vlan_id > ETH_VLAN_ID_MAX)
6039                 return 0;
6040
6041         vid_idx = I40E_VFTA_IDX(vlan_id);
6042         vid_bit = I40E_VFTA_BIT(vlan_id);
6043
6044         if (vsi->vfta[vid_idx] & vid_bit)
6045                 return 1;
6046         else
6047                 return 0;
6048 }
6049
6050 static void
6051 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6052                        uint16_t vlan_id, bool on)
6053 {
6054         uint32_t vid_idx, vid_bit;
6055
6056         vid_idx = I40E_VFTA_IDX(vlan_id);
6057         vid_bit = I40E_VFTA_BIT(vlan_id);
6058
6059         if (on)
6060                 vsi->vfta[vid_idx] |= vid_bit;
6061         else
6062                 vsi->vfta[vid_idx] &= ~vid_bit;
6063 }
6064
6065 void
6066 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6067                      uint16_t vlan_id, bool on)
6068 {
6069         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6070         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6071         int ret;
6072
6073         if (vlan_id > ETH_VLAN_ID_MAX)
6074                 return;
6075
6076         i40e_store_vlan_filter(vsi, vlan_id, on);
6077
6078         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6079                 return;
6080
6081         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6082
6083         if (on) {
6084                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6085                                        &vlan_data, 1, NULL);
6086                 if (ret != I40E_SUCCESS)
6087                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6088         } else {
6089                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6090                                           &vlan_data, 1, NULL);
6091                 if (ret != I40E_SUCCESS)
6092                         PMD_DRV_LOG(ERR,
6093                                     "Failed to remove vlan filter");
6094         }
6095 }
6096
6097 /**
6098  * Find all vlan options for specific mac addr,
6099  * return with actual vlan found.
6100  */
6101 int
6102 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6103                            struct i40e_macvlan_filter *mv_f,
6104                            int num, struct ether_addr *addr)
6105 {
6106         int i;
6107         uint32_t j, k;
6108
6109         /**
6110          * Not to use i40e_find_vlan_filter to decrease the loop time,
6111          * although the code looks complex.
6112           */
6113         if (num < vsi->vlan_num)
6114                 return I40E_ERR_PARAM;
6115
6116         i = 0;
6117         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6118                 if (vsi->vfta[j]) {
6119                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6120                                 if (vsi->vfta[j] & (1 << k)) {
6121                                         if (i > num - 1) {
6122                                                 PMD_DRV_LOG(ERR,
6123                                                         "vlan number doesn't match");
6124                                                 return I40E_ERR_PARAM;
6125                                         }
6126                                         (void)rte_memcpy(&mv_f[i].macaddr,
6127                                                         addr, ETH_ADDR_LEN);
6128                                         mv_f[i].vlan_id =
6129                                                 j * I40E_UINT32_BIT_SIZE + k;
6130                                         i++;
6131                                 }
6132                         }
6133                 }
6134         }
6135         return I40E_SUCCESS;
6136 }
6137
6138 static inline int
6139 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6140                            struct i40e_macvlan_filter *mv_f,
6141                            int num,
6142                            uint16_t vlan)
6143 {
6144         int i = 0;
6145         struct i40e_mac_filter *f;
6146
6147         if (num < vsi->mac_num)
6148                 return I40E_ERR_PARAM;
6149
6150         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6151                 if (i > num - 1) {
6152                         PMD_DRV_LOG(ERR, "buffer number not match");
6153                         return I40E_ERR_PARAM;
6154                 }
6155                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6156                                 ETH_ADDR_LEN);
6157                 mv_f[i].vlan_id = vlan;
6158                 mv_f[i].filter_type = f->mac_info.filter_type;
6159                 i++;
6160         }
6161
6162         return I40E_SUCCESS;
6163 }
6164
6165 static int
6166 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6167 {
6168         int i, j, num;
6169         struct i40e_mac_filter *f;
6170         struct i40e_macvlan_filter *mv_f;
6171         int ret = I40E_SUCCESS;
6172
6173         if (vsi == NULL || vsi->mac_num == 0)
6174                 return I40E_ERR_PARAM;
6175
6176         /* Case that no vlan is set */
6177         if (vsi->vlan_num == 0)
6178                 num = vsi->mac_num;
6179         else
6180                 num = vsi->mac_num * vsi->vlan_num;
6181
6182         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6183         if (mv_f == NULL) {
6184                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6185                 return I40E_ERR_NO_MEMORY;
6186         }
6187
6188         i = 0;
6189         if (vsi->vlan_num == 0) {
6190                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6191                         (void)rte_memcpy(&mv_f[i].macaddr,
6192                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6193                         mv_f[i].filter_type = f->mac_info.filter_type;
6194                         mv_f[i].vlan_id = 0;
6195                         i++;
6196                 }
6197         } else {
6198                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6199                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6200                                         vsi->vlan_num, &f->mac_info.mac_addr);
6201                         if (ret != I40E_SUCCESS)
6202                                 goto DONE;
6203                         for (j = i; j < i + vsi->vlan_num; j++)
6204                                 mv_f[j].filter_type = f->mac_info.filter_type;
6205                         i += vsi->vlan_num;
6206                 }
6207         }
6208
6209         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6210 DONE:
6211         rte_free(mv_f);
6212
6213         return ret;
6214 }
6215
6216 int
6217 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6218 {
6219         struct i40e_macvlan_filter *mv_f;
6220         int mac_num;
6221         int ret = I40E_SUCCESS;
6222
6223         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6224                 return I40E_ERR_PARAM;
6225
6226         /* If it's already set, just return */
6227         if (i40e_find_vlan_filter(vsi,vlan))
6228                 return I40E_SUCCESS;
6229
6230         mac_num = vsi->mac_num;
6231
6232         if (mac_num == 0) {
6233                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6234                 return I40E_ERR_PARAM;
6235         }
6236
6237         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6238
6239         if (mv_f == NULL) {
6240                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6241                 return I40E_ERR_NO_MEMORY;
6242         }
6243
6244         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6245
6246         if (ret != I40E_SUCCESS)
6247                 goto DONE;
6248
6249         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6250
6251         if (ret != I40E_SUCCESS)
6252                 goto DONE;
6253
6254         i40e_set_vlan_filter(vsi, vlan, 1);
6255
6256         vsi->vlan_num++;
6257         ret = I40E_SUCCESS;
6258 DONE:
6259         rte_free(mv_f);
6260         return ret;
6261 }
6262
6263 int
6264 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6265 {
6266         struct i40e_macvlan_filter *mv_f;
6267         int mac_num;
6268         int ret = I40E_SUCCESS;
6269
6270         /**
6271          * Vlan 0 is the generic filter for untagged packets
6272          * and can't be removed.
6273          */
6274         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6275                 return I40E_ERR_PARAM;
6276
6277         /* If can't find it, just return */
6278         if (!i40e_find_vlan_filter(vsi, vlan))
6279                 return I40E_ERR_PARAM;
6280
6281         mac_num = vsi->mac_num;
6282
6283         if (mac_num == 0) {
6284                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6285                 return I40E_ERR_PARAM;
6286         }
6287
6288         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6289
6290         if (mv_f == NULL) {
6291                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6292                 return I40E_ERR_NO_MEMORY;
6293         }
6294
6295         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6296
6297         if (ret != I40E_SUCCESS)
6298                 goto DONE;
6299
6300         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6301
6302         if (ret != I40E_SUCCESS)
6303                 goto DONE;
6304
6305         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6306         if (vsi->vlan_num == 1) {
6307                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6308                 if (ret != I40E_SUCCESS)
6309                         goto DONE;
6310
6311                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6312                 if (ret != I40E_SUCCESS)
6313                         goto DONE;
6314         }
6315
6316         i40e_set_vlan_filter(vsi, vlan, 0);
6317
6318         vsi->vlan_num--;
6319         ret = I40E_SUCCESS;
6320 DONE:
6321         rte_free(mv_f);
6322         return ret;
6323 }
6324
6325 int
6326 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6327 {
6328         struct i40e_mac_filter *f;
6329         struct i40e_macvlan_filter *mv_f;
6330         int i, vlan_num = 0;
6331         int ret = I40E_SUCCESS;
6332
6333         /* If it's add and we've config it, return */
6334         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6335         if (f != NULL)
6336                 return I40E_SUCCESS;
6337         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6338                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6339
6340                 /**
6341                  * If vlan_num is 0, that's the first time to add mac,
6342                  * set mask for vlan_id 0.
6343                  */
6344                 if (vsi->vlan_num == 0) {
6345                         i40e_set_vlan_filter(vsi, 0, 1);
6346                         vsi->vlan_num = 1;
6347                 }
6348                 vlan_num = vsi->vlan_num;
6349         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6350                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6351                 vlan_num = 1;
6352
6353         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6354         if (mv_f == NULL) {
6355                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6356                 return I40E_ERR_NO_MEMORY;
6357         }
6358
6359         for (i = 0; i < vlan_num; i++) {
6360                 mv_f[i].filter_type = mac_filter->filter_type;
6361                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6362                                 ETH_ADDR_LEN);
6363         }
6364
6365         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6366                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6367                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6368                                         &mac_filter->mac_addr);
6369                 if (ret != I40E_SUCCESS)
6370                         goto DONE;
6371         }
6372
6373         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6374         if (ret != I40E_SUCCESS)
6375                 goto DONE;
6376
6377         /* Add the mac addr into mac list */
6378         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6379         if (f == NULL) {
6380                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6381                 ret = I40E_ERR_NO_MEMORY;
6382                 goto DONE;
6383         }
6384         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6385                         ETH_ADDR_LEN);
6386         f->mac_info.filter_type = mac_filter->filter_type;
6387         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6388         vsi->mac_num++;
6389
6390         ret = I40E_SUCCESS;
6391 DONE:
6392         rte_free(mv_f);
6393
6394         return ret;
6395 }
6396
6397 int
6398 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6399 {
6400         struct i40e_mac_filter *f;
6401         struct i40e_macvlan_filter *mv_f;
6402         int i, vlan_num;
6403         enum rte_mac_filter_type filter_type;
6404         int ret = I40E_SUCCESS;
6405
6406         /* Can't find it, return an error */
6407         f = i40e_find_mac_filter(vsi, addr);
6408         if (f == NULL)
6409                 return I40E_ERR_PARAM;
6410
6411         vlan_num = vsi->vlan_num;
6412         filter_type = f->mac_info.filter_type;
6413         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6414                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6415                 if (vlan_num == 0) {
6416                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6417                         return I40E_ERR_PARAM;
6418                 }
6419         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6420                         filter_type == RTE_MAC_HASH_MATCH)
6421                 vlan_num = 1;
6422
6423         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6424         if (mv_f == NULL) {
6425                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6426                 return I40E_ERR_NO_MEMORY;
6427         }
6428
6429         for (i = 0; i < vlan_num; i++) {
6430                 mv_f[i].filter_type = filter_type;
6431                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6432                                 ETH_ADDR_LEN);
6433         }
6434         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6435                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6436                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6437                 if (ret != I40E_SUCCESS)
6438                         goto DONE;
6439         }
6440
6441         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6442         if (ret != I40E_SUCCESS)
6443                 goto DONE;
6444
6445         /* Remove the mac addr into mac list */
6446         TAILQ_REMOVE(&vsi->mac_list, f, next);
6447         rte_free(f);
6448         vsi->mac_num--;
6449
6450         ret = I40E_SUCCESS;
6451 DONE:
6452         rte_free(mv_f);
6453         return ret;
6454 }
6455
6456 /* Configure hash enable flags for RSS */
6457 uint64_t
6458 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6459 {
6460         uint64_t hena = 0;
6461
6462         if (!flags)
6463                 return hena;
6464
6465         if (flags & ETH_RSS_FRAG_IPV4)
6466                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6467         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6468                 if (type == I40E_MAC_X722) {
6469                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6470                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6471                 } else
6472                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6473         }
6474         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6475                 if (type == I40E_MAC_X722) {
6476                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6477                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6478                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6479                 } else
6480                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6481         }
6482         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6483                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6484         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6485                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6486         if (flags & ETH_RSS_FRAG_IPV6)
6487                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6488         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6489                 if (type == I40E_MAC_X722) {
6490                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6491                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6492                 } else
6493                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6494         }
6495         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6496                 if (type == I40E_MAC_X722) {
6497                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6498                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6499                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6500                 } else
6501                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6502         }
6503         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6504                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6505         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6506                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6507         if (flags & ETH_RSS_L2_PAYLOAD)
6508                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6509
6510         return hena;
6511 }
6512
6513 /* Parse the hash enable flags */
6514 uint64_t
6515 i40e_parse_hena(uint64_t flags)
6516 {
6517         uint64_t rss_hf = 0;
6518
6519         if (!flags)
6520                 return rss_hf;
6521         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6522                 rss_hf |= ETH_RSS_FRAG_IPV4;
6523         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6524                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6525         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6526                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6527         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6528                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6529         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6530                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6531         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6532                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6533         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6534                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6535         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6536                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6537         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6538                 rss_hf |= ETH_RSS_FRAG_IPV6;
6539         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6540                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6541         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6542                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6543         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6544                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6545         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6546                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6547         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6548                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6549         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6550                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6551         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6552                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6553         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6554                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6555
6556         return rss_hf;
6557 }
6558
6559 /* Disable RSS */
6560 static void
6561 i40e_pf_disable_rss(struct i40e_pf *pf)
6562 {
6563         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6564         uint64_t hena;
6565
6566         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6567         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6568         if (hw->mac.type == I40E_MAC_X722)
6569                 hena &= ~I40E_RSS_HENA_ALL_X722;
6570         else
6571                 hena &= ~I40E_RSS_HENA_ALL;
6572         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6573         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6574         I40E_WRITE_FLUSH(hw);
6575 }
6576
6577 static int
6578 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6579 {
6580         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6581         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6582         int ret = 0;
6583
6584         if (!key || key_len == 0) {
6585                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6586                 return 0;
6587         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6588                 sizeof(uint32_t)) {
6589                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6590                 return -EINVAL;
6591         }
6592
6593         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6594                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6595                         (struct i40e_aqc_get_set_rss_key_data *)key;
6596
6597                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6598                 if (ret)
6599                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6600         } else {
6601                 uint32_t *hash_key = (uint32_t *)key;
6602                 uint16_t i;
6603
6604                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6605                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6606                 I40E_WRITE_FLUSH(hw);
6607         }
6608
6609         return ret;
6610 }
6611
6612 static int
6613 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6614 {
6615         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6616         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6617         int ret;
6618
6619         if (!key || !key_len)
6620                 return -EINVAL;
6621
6622         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6623                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6624                         (struct i40e_aqc_get_set_rss_key_data *)key);
6625                 if (ret) {
6626                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6627                         return ret;
6628                 }
6629         } else {
6630                 uint32_t *key_dw = (uint32_t *)key;
6631                 uint16_t i;
6632
6633                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6634                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6635         }
6636         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6637
6638         return 0;
6639 }
6640
6641 static int
6642 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6643 {
6644         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6645         uint64_t rss_hf;
6646         uint64_t hena;
6647         int ret;
6648
6649         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6650                                rss_conf->rss_key_len);
6651         if (ret)
6652                 return ret;
6653
6654         rss_hf = rss_conf->rss_hf;
6655         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6656         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6657         if (hw->mac.type == I40E_MAC_X722)
6658                 hena &= ~I40E_RSS_HENA_ALL_X722;
6659         else
6660                 hena &= ~I40E_RSS_HENA_ALL;
6661         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6662         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6663         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6664         I40E_WRITE_FLUSH(hw);
6665
6666         return 0;
6667 }
6668
6669 static int
6670 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6671                          struct rte_eth_rss_conf *rss_conf)
6672 {
6673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6675         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6676         uint64_t hena;
6677
6678         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6679         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6680         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6681                  ? I40E_RSS_HENA_ALL_X722
6682                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6683                 if (rss_hf != 0) /* Enable RSS */
6684                         return -EINVAL;
6685                 return 0; /* Nothing to do */
6686         }
6687         /* RSS enabled */
6688         if (rss_hf == 0) /* Disable RSS */
6689                 return -EINVAL;
6690
6691         return i40e_hw_rss_hash_set(pf, rss_conf);
6692 }
6693
6694 static int
6695 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6696                            struct rte_eth_rss_conf *rss_conf)
6697 {
6698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6699         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700         uint64_t hena;
6701
6702         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6703                          &rss_conf->rss_key_len);
6704
6705         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6706         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6707         rss_conf->rss_hf = i40e_parse_hena(hena);
6708
6709         return 0;
6710 }
6711
6712 static int
6713 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6714 {
6715         switch (filter_type) {
6716         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6717                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6718                 break;
6719         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6720                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6721                 break;
6722         case RTE_TUNNEL_FILTER_IMAC_TENID:
6723                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6724                 break;
6725         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6726                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6727                 break;
6728         case ETH_TUNNEL_FILTER_IMAC:
6729                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6730                 break;
6731         case ETH_TUNNEL_FILTER_OIP:
6732                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6733                 break;
6734         case ETH_TUNNEL_FILTER_IIP:
6735                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6736                 break;
6737         default:
6738                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6739                 return -EINVAL;
6740         }
6741
6742         return 0;
6743 }
6744
6745 /* Convert tunnel filter structure */
6746 static int
6747 i40e_tunnel_filter_convert(
6748         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6749         struct i40e_tunnel_filter *tunnel_filter)
6750 {
6751         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6752                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6753         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6754                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6755         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6756         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6757              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6758             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6759                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6760         else
6761                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6762         tunnel_filter->input.flags = cld_filter->element.flags;
6763         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6764         tunnel_filter->queue = cld_filter->element.queue_number;
6765         rte_memcpy(tunnel_filter->input.general_fields,
6766                    cld_filter->general_fields,
6767                    sizeof(cld_filter->general_fields));
6768
6769         return 0;
6770 }
6771
6772 /* Check if there exists the tunnel filter */
6773 struct i40e_tunnel_filter *
6774 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6775                              const struct i40e_tunnel_filter_input *input)
6776 {
6777         int ret;
6778
6779         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6780         if (ret < 0)
6781                 return NULL;
6782
6783         return tunnel_rule->hash_map[ret];
6784 }
6785
6786 /* Add a tunnel filter into the SW list */
6787 static int
6788 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6789                              struct i40e_tunnel_filter *tunnel_filter)
6790 {
6791         struct i40e_tunnel_rule *rule = &pf->tunnel;
6792         int ret;
6793
6794         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6795         if (ret < 0) {
6796                 PMD_DRV_LOG(ERR,
6797                             "Failed to insert tunnel filter to hash table %d!",
6798                             ret);
6799                 return ret;
6800         }
6801         rule->hash_map[ret] = tunnel_filter;
6802
6803         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6804
6805         return 0;
6806 }
6807
6808 /* Delete a tunnel filter from the SW list */
6809 int
6810 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6811                           struct i40e_tunnel_filter_input *input)
6812 {
6813         struct i40e_tunnel_rule *rule = &pf->tunnel;
6814         struct i40e_tunnel_filter *tunnel_filter;
6815         int ret;
6816
6817         ret = rte_hash_del_key(rule->hash_table, input);
6818         if (ret < 0) {
6819                 PMD_DRV_LOG(ERR,
6820                             "Failed to delete tunnel filter to hash table %d!",
6821                             ret);
6822                 return ret;
6823         }
6824         tunnel_filter = rule->hash_map[ret];
6825         rule->hash_map[ret] = NULL;
6826
6827         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6828         rte_free(tunnel_filter);
6829
6830         return 0;
6831 }
6832
6833 int
6834 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6835                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6836                         uint8_t add)
6837 {
6838         uint16_t ip_type;
6839         uint32_t ipv4_addr;
6840         uint8_t i, tun_type = 0;
6841         /* internal varialbe to convert ipv6 byte order */
6842         uint32_t convert_ipv6[4];
6843         int val, ret = 0;
6844         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6845         struct i40e_vsi *vsi = pf->main_vsi;
6846         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6847         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6848         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6849         struct i40e_tunnel_filter *tunnel, *node;
6850         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6851
6852         cld_filter = rte_zmalloc("tunnel_filter",
6853                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6854         0);
6855
6856         if (NULL == cld_filter) {
6857                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6858                 return -ENOMEM;
6859         }
6860         pfilter = cld_filter;
6861
6862         ether_addr_copy(&tunnel_filter->outer_mac,
6863                         (struct ether_addr *)&pfilter->element.outer_mac);
6864         ether_addr_copy(&tunnel_filter->inner_mac,
6865                         (struct ether_addr *)&pfilter->element.inner_mac);
6866
6867         pfilter->element.inner_vlan =
6868                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6869         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6870                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6871                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6872                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6873                                 &rte_cpu_to_le_32(ipv4_addr),
6874                                 sizeof(pfilter->element.ipaddr.v4.data));
6875         } else {
6876                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6877                 for (i = 0; i < 4; i++) {
6878                         convert_ipv6[i] =
6879                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6880                 }
6881                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6882                            &convert_ipv6,
6883                            sizeof(pfilter->element.ipaddr.v6.data));
6884         }
6885
6886         /* check tunneled type */
6887         switch (tunnel_filter->tunnel_type) {
6888         case RTE_TUNNEL_TYPE_VXLAN:
6889                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6890                 break;
6891         case RTE_TUNNEL_TYPE_NVGRE:
6892                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6893                 break;
6894         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6895                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6896                 break;
6897         default:
6898                 /* Other tunnel types is not supported. */
6899                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6900                 rte_free(cld_filter);
6901                 return -EINVAL;
6902         }
6903
6904         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6905                                        &pfilter->element.flags);
6906         if (val < 0) {
6907                 rte_free(cld_filter);
6908                 return -EINVAL;
6909         }
6910
6911         pfilter->element.flags |= rte_cpu_to_le_16(
6912                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6913                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6914         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6915         pfilter->element.queue_number =
6916                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6917
6918         /* Check if there is the filter in SW list */
6919         memset(&check_filter, 0, sizeof(check_filter));
6920         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6921         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6922         if (add && node) {
6923                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6924                 return -EINVAL;
6925         }
6926
6927         if (!add && !node) {
6928                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6929                 return -EINVAL;
6930         }
6931
6932         if (add) {
6933                 ret = i40e_aq_add_cloud_filters(hw,
6934                                         vsi->seid, &cld_filter->element, 1);
6935                 if (ret < 0) {
6936                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6937                         return -ENOTSUP;
6938                 }
6939                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6940                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6941                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6942         } else {
6943                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6944                                                    &cld_filter->element, 1);
6945                 if (ret < 0) {
6946                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6947                         return -ENOTSUP;
6948                 }
6949                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6950         }
6951
6952         rte_free(cld_filter);
6953         return ret;
6954 }
6955
6956 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6957 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
6958 #define I40E_TR_GENEVE_KEY_MASK                 0x8
6959 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
6960 #define I40E_TR_GRE_KEY_MASK                    0x400
6961 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
6962 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
6963
6964 static enum
6965 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6966 {
6967         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
6968         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
6969         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6970         enum i40e_status_code status = I40E_SUCCESS;
6971
6972         memset(&filter_replace, 0,
6973                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6974         memset(&filter_replace_buf, 0,
6975                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6976
6977         /* create L1 filter */
6978         filter_replace.old_filter_type =
6979                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6980         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6981         filter_replace.tr_bit = 0;
6982
6983         /* Prepare the buffer, 3 entries */
6984         filter_replace_buf.data[0] =
6985                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6986         filter_replace_buf.data[0] |=
6987                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6988         filter_replace_buf.data[2] = 0xFF;
6989         filter_replace_buf.data[3] = 0xFF;
6990         filter_replace_buf.data[4] =
6991                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6992         filter_replace_buf.data[4] |=
6993                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6994         filter_replace_buf.data[7] = 0xF0;
6995         filter_replace_buf.data[8]
6996                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6997         filter_replace_buf.data[8] |=
6998                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6999         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7000                 I40E_TR_GENEVE_KEY_MASK |
7001                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7002         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7003                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7004                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7005
7006         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7007                                                &filter_replace_buf);
7008         return status;
7009 }
7010
7011 static enum
7012 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7013 {
7014         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7015         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7016         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7017         enum i40e_status_code status = I40E_SUCCESS;
7018
7019         /* For MPLSoUDP */
7020         memset(&filter_replace, 0,
7021                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7022         memset(&filter_replace_buf, 0,
7023                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7024         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7025                 I40E_AQC_MIRROR_CLOUD_FILTER;
7026         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7027         filter_replace.new_filter_type =
7028                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7029         /* Prepare the buffer, 2 entries */
7030         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7031         filter_replace_buf.data[0] |=
7032                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7033         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7034         filter_replace_buf.data[4] |=
7035                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7036         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7037                                                &filter_replace_buf);
7038         if (status < 0)
7039                 return status;
7040
7041         /* For MPLSoGRE */
7042         memset(&filter_replace, 0,
7043                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7044         memset(&filter_replace_buf, 0,
7045                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7046
7047         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7048                 I40E_AQC_MIRROR_CLOUD_FILTER;
7049         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7050         filter_replace.new_filter_type =
7051                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7052         /* Prepare the buffer, 2 entries */
7053         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7054         filter_replace_buf.data[0] |=
7055                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7056         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7057         filter_replace_buf.data[4] |=
7058                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7059
7060         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7061                                                &filter_replace_buf);
7062         return status;
7063 }
7064
7065 int
7066 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7067                       struct i40e_tunnel_filter_conf *tunnel_filter,
7068                       uint8_t add)
7069 {
7070         uint16_t ip_type;
7071         uint32_t ipv4_addr;
7072         uint8_t i, tun_type = 0;
7073         /* internal variable to convert ipv6 byte order */
7074         uint32_t convert_ipv6[4];
7075         int val, ret = 0;
7076         struct i40e_pf_vf *vf = NULL;
7077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7078         struct i40e_vsi *vsi;
7079         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7080         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7081         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7082         struct i40e_tunnel_filter *tunnel, *node;
7083         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7084         uint32_t teid_le;
7085         bool big_buffer = 0;
7086
7087         cld_filter = rte_zmalloc("tunnel_filter",
7088                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7089                          0);
7090
7091         if (cld_filter == NULL) {
7092                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7093                 return -ENOMEM;
7094         }
7095         pfilter = cld_filter;
7096
7097         ether_addr_copy(&tunnel_filter->outer_mac,
7098                         (struct ether_addr *)&pfilter->element.outer_mac);
7099         ether_addr_copy(&tunnel_filter->inner_mac,
7100                         (struct ether_addr *)&pfilter->element.inner_mac);
7101
7102         pfilter->element.inner_vlan =
7103                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7104         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7105                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7106                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7107                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7108                                 &rte_cpu_to_le_32(ipv4_addr),
7109                                 sizeof(pfilter->element.ipaddr.v4.data));
7110         } else {
7111                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7112                 for (i = 0; i < 4; i++) {
7113                         convert_ipv6[i] =
7114                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7115                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7116                 }
7117                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7118                            &convert_ipv6,
7119                            sizeof(pfilter->element.ipaddr.v6.data));
7120         }
7121
7122         /* check tunneled type */
7123         switch (tunnel_filter->tunnel_type) {
7124         case I40E_TUNNEL_TYPE_VXLAN:
7125                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7126                 break;
7127         case I40E_TUNNEL_TYPE_NVGRE:
7128                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7129                 break;
7130         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7131                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7132                 break;
7133         case I40E_TUNNEL_TYPE_MPLSoUDP:
7134                 if (!pf->mpls_replace_flag) {
7135                         i40e_replace_mpls_l1_filter(pf);
7136                         i40e_replace_mpls_cloud_filter(pf);
7137                         pf->mpls_replace_flag = 1;
7138                 }
7139                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7140                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7141                         teid_le >> 4;
7142                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7143                         (teid_le & 0xF) << 12;
7144                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7145                         0x40;
7146                 big_buffer = 1;
7147                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7148                 break;
7149         case I40E_TUNNEL_TYPE_MPLSoGRE:
7150                 if (!pf->mpls_replace_flag) {
7151                         i40e_replace_mpls_l1_filter(pf);
7152                         i40e_replace_mpls_cloud_filter(pf);
7153                         pf->mpls_replace_flag = 1;
7154                 }
7155                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7156                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7157                         teid_le >> 4;
7158                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7159                         (teid_le & 0xF) << 12;
7160                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7161                         0x0;
7162                 big_buffer = 1;
7163                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7164                 break;
7165         case I40E_TUNNEL_TYPE_QINQ:
7166                 if (!pf->qinq_replace_flag) {
7167                         ret = i40e_cloud_filter_qinq_create(pf);
7168                         if (ret < 0)
7169                                 PMD_DRV_LOG(DEBUG,
7170                                             "QinQ tunnel filter already created.");
7171                         pf->qinq_replace_flag = 1;
7172                 }
7173                 /*      Add in the General fields the values of
7174                  *      the Outer and Inner VLAN
7175                  *      Big Buffer should be set, see changes in
7176                  *      i40e_aq_add_cloud_filters
7177                  */
7178                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7179                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7180                 big_buffer = 1;
7181                 break;
7182         default:
7183                 /* Other tunnel types is not supported. */
7184                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7185                 rte_free(cld_filter);
7186                 return -EINVAL;
7187         }
7188
7189         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7190                 pfilter->element.flags =
7191                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7192         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7193                 pfilter->element.flags =
7194                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7195         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7196                 pfilter->element.flags |=
7197                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7198         else {
7199                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7200                                                 &pfilter->element.flags);
7201                 if (val < 0) {
7202                         rte_free(cld_filter);
7203                         return -EINVAL;
7204                 }
7205         }
7206
7207         pfilter->element.flags |= rte_cpu_to_le_16(
7208                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7209                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7210         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7211         pfilter->element.queue_number =
7212                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7213
7214         if (!tunnel_filter->is_to_vf)
7215                 vsi = pf->main_vsi;
7216         else {
7217                 if (tunnel_filter->vf_id >= pf->vf_num) {
7218                         PMD_DRV_LOG(ERR, "Invalid argument.");
7219                         return -EINVAL;
7220                 }
7221                 vf = &pf->vfs[tunnel_filter->vf_id];
7222                 vsi = vf->vsi;
7223         }
7224
7225         /* Check if there is the filter in SW list */
7226         memset(&check_filter, 0, sizeof(check_filter));
7227         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7228         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7229         check_filter.vf_id = tunnel_filter->vf_id;
7230         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7231         if (add && node) {
7232                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7233                 return -EINVAL;
7234         }
7235
7236         if (!add && !node) {
7237                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7238                 return -EINVAL;
7239         }
7240
7241         if (add) {
7242                 if (big_buffer)
7243                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7244                                                    vsi->seid, cld_filter, 1);
7245                 else
7246                         ret = i40e_aq_add_cloud_filters(hw,
7247                                         vsi->seid, &cld_filter->element, 1);
7248                 if (ret < 0) {
7249                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7250                         return -ENOTSUP;
7251                 }
7252                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7253                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7254                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7255         } else {
7256                 if (big_buffer)
7257                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7258                                 hw, vsi->seid, cld_filter, 1);
7259                 else
7260                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7261                                                    &cld_filter->element, 1);
7262                 if (ret < 0) {
7263                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7264                         return -ENOTSUP;
7265                 }
7266                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7267         }
7268
7269         rte_free(cld_filter);
7270         return ret;
7271 }
7272
7273 static int
7274 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7275 {
7276         uint8_t i;
7277
7278         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7279                 if (pf->vxlan_ports[i] == port)
7280                         return i;
7281         }
7282
7283         return -1;
7284 }
7285
7286 static int
7287 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7288 {
7289         int  idx, ret;
7290         uint8_t filter_idx;
7291         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7292
7293         idx = i40e_get_vxlan_port_idx(pf, port);
7294
7295         /* Check if port already exists */
7296         if (idx >= 0) {
7297                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7298                 return -EINVAL;
7299         }
7300
7301         /* Now check if there is space to add the new port */
7302         idx = i40e_get_vxlan_port_idx(pf, 0);
7303         if (idx < 0) {
7304                 PMD_DRV_LOG(ERR,
7305                         "Maximum number of UDP ports reached, not adding port %d",
7306                         port);
7307                 return -ENOSPC;
7308         }
7309
7310         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7311                                         &filter_idx, NULL);
7312         if (ret < 0) {
7313                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7314                 return -1;
7315         }
7316
7317         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7318                          port,  filter_idx);
7319
7320         /* New port: add it and mark its index in the bitmap */
7321         pf->vxlan_ports[idx] = port;
7322         pf->vxlan_bitmap |= (1 << idx);
7323
7324         if (!(pf->flags & I40E_FLAG_VXLAN))
7325                 pf->flags |= I40E_FLAG_VXLAN;
7326
7327         return 0;
7328 }
7329
7330 static int
7331 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7332 {
7333         int idx;
7334         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7335
7336         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7337                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7338                 return -EINVAL;
7339         }
7340
7341         idx = i40e_get_vxlan_port_idx(pf, port);
7342
7343         if (idx < 0) {
7344                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7345                 return -EINVAL;
7346         }
7347
7348         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7349                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7350                 return -1;
7351         }
7352
7353         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7354                         port, idx);
7355
7356         pf->vxlan_ports[idx] = 0;
7357         pf->vxlan_bitmap &= ~(1 << idx);
7358
7359         if (!pf->vxlan_bitmap)
7360                 pf->flags &= ~I40E_FLAG_VXLAN;
7361
7362         return 0;
7363 }
7364
7365 /* Add UDP tunneling port */
7366 static int
7367 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7368                              struct rte_eth_udp_tunnel *udp_tunnel)
7369 {
7370         int ret = 0;
7371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7372
7373         if (udp_tunnel == NULL)
7374                 return -EINVAL;
7375
7376         switch (udp_tunnel->prot_type) {
7377         case RTE_TUNNEL_TYPE_VXLAN:
7378                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7379                 break;
7380
7381         case RTE_TUNNEL_TYPE_GENEVE:
7382         case RTE_TUNNEL_TYPE_TEREDO:
7383                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7384                 ret = -1;
7385                 break;
7386
7387         default:
7388                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7389                 ret = -1;
7390                 break;
7391         }
7392
7393         return ret;
7394 }
7395
7396 /* Remove UDP tunneling port */
7397 static int
7398 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7399                              struct rte_eth_udp_tunnel *udp_tunnel)
7400 {
7401         int ret = 0;
7402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7403
7404         if (udp_tunnel == NULL)
7405                 return -EINVAL;
7406
7407         switch (udp_tunnel->prot_type) {
7408         case RTE_TUNNEL_TYPE_VXLAN:
7409                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7410                 break;
7411         case RTE_TUNNEL_TYPE_GENEVE:
7412         case RTE_TUNNEL_TYPE_TEREDO:
7413                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7414                 ret = -1;
7415                 break;
7416         default:
7417                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7418                 ret = -1;
7419                 break;
7420         }
7421
7422         return ret;
7423 }
7424
7425 /* Calculate the maximum number of contiguous PF queues that are configured */
7426 static int
7427 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7428 {
7429         struct rte_eth_dev_data *data = pf->dev_data;
7430         int i, num;
7431         struct i40e_rx_queue *rxq;
7432
7433         num = 0;
7434         for (i = 0; i < pf->lan_nb_qps; i++) {
7435                 rxq = data->rx_queues[i];
7436                 if (rxq && rxq->q_set)
7437                         num++;
7438                 else
7439                         break;
7440         }
7441
7442         return num;
7443 }
7444
7445 /* Configure RSS */
7446 static int
7447 i40e_pf_config_rss(struct i40e_pf *pf)
7448 {
7449         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7450         struct rte_eth_rss_conf rss_conf;
7451         uint32_t i, lut = 0;
7452         uint16_t j, num;
7453
7454         /*
7455          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7456          * It's necessary to calulate the actual PF queues that are configured.
7457          */
7458         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7459                 num = i40e_pf_calc_configured_queues_num(pf);
7460         else
7461                 num = pf->dev_data->nb_rx_queues;
7462
7463         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7464         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7465                         num);
7466
7467         if (num == 0) {
7468                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7469                 return -ENOTSUP;
7470         }
7471
7472         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7473                 if (j == num)
7474                         j = 0;
7475                 lut = (lut << 8) | (j & ((0x1 <<
7476                         hw->func_caps.rss_table_entry_width) - 1));
7477                 if ((i & 3) == 3)
7478                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7479         }
7480
7481         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7482         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7483                 i40e_pf_disable_rss(pf);
7484                 return 0;
7485         }
7486         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7487                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7488                 /* Random default keys */
7489                 static uint32_t rss_key_default[] = {0x6b793944,
7490                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7491                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7492                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7493
7494                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7495                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7496                                                         sizeof(uint32_t);
7497         }
7498
7499         return i40e_hw_rss_hash_set(pf, &rss_conf);
7500 }
7501
7502 static int
7503 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7504                                struct rte_eth_tunnel_filter_conf *filter)
7505 {
7506         if (pf == NULL || filter == NULL) {
7507                 PMD_DRV_LOG(ERR, "Invalid parameter");
7508                 return -EINVAL;
7509         }
7510
7511         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7512                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7513                 return -EINVAL;
7514         }
7515
7516         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7517                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7518                 return -EINVAL;
7519         }
7520
7521         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7522                 (is_zero_ether_addr(&filter->outer_mac))) {
7523                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7524                 return -EINVAL;
7525         }
7526
7527         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7528                 (is_zero_ether_addr(&filter->inner_mac))) {
7529                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7530                 return -EINVAL;
7531         }
7532
7533         return 0;
7534 }
7535
7536 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7537 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7538 static int
7539 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7540 {
7541         uint32_t val, reg;
7542         int ret = -EINVAL;
7543
7544         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7545         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7546
7547         if (len == 3) {
7548                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7549         } else if (len == 4) {
7550                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7551         } else {
7552                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7553                 return ret;
7554         }
7555
7556         if (reg != val) {
7557                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7558                                                    reg, NULL);
7559                 if (ret != 0)
7560                         return ret;
7561         } else {
7562                 ret = 0;
7563         }
7564         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7565                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7566
7567         return ret;
7568 }
7569
7570 static int
7571 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7572 {
7573         int ret = -EINVAL;
7574
7575         if (!hw || !cfg)
7576                 return -EINVAL;
7577
7578         switch (cfg->cfg_type) {
7579         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7580                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7581                 break;
7582         default:
7583                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7584                 break;
7585         }
7586
7587         return ret;
7588 }
7589
7590 static int
7591 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7592                                enum rte_filter_op filter_op,
7593                                void *arg)
7594 {
7595         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7596         int ret = I40E_ERR_PARAM;
7597
7598         switch (filter_op) {
7599         case RTE_ETH_FILTER_SET:
7600                 ret = i40e_dev_global_config_set(hw,
7601                         (struct rte_eth_global_cfg *)arg);
7602                 break;
7603         default:
7604                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7605                 break;
7606         }
7607
7608         return ret;
7609 }
7610
7611 static int
7612 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7613                           enum rte_filter_op filter_op,
7614                           void *arg)
7615 {
7616         struct rte_eth_tunnel_filter_conf *filter;
7617         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7618         int ret = I40E_SUCCESS;
7619
7620         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7621
7622         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7623                 return I40E_ERR_PARAM;
7624
7625         switch (filter_op) {
7626         case RTE_ETH_FILTER_NOP:
7627                 if (!(pf->flags & I40E_FLAG_VXLAN))
7628                         ret = I40E_NOT_SUPPORTED;
7629                 break;
7630         case RTE_ETH_FILTER_ADD:
7631                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7632                 break;
7633         case RTE_ETH_FILTER_DELETE:
7634                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7635                 break;
7636         default:
7637                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7638                 ret = I40E_ERR_PARAM;
7639                 break;
7640         }
7641
7642         return ret;
7643 }
7644
7645 static int
7646 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7647 {
7648         int ret = 0;
7649         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7650
7651         /* RSS setup */
7652         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7653                 ret = i40e_pf_config_rss(pf);
7654         else
7655                 i40e_pf_disable_rss(pf);
7656
7657         return ret;
7658 }
7659
7660 /* Get the symmetric hash enable configurations per port */
7661 static void
7662 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7663 {
7664         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7665
7666         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7667 }
7668
7669 /* Set the symmetric hash enable configurations per port */
7670 static void
7671 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7672 {
7673         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7674
7675         if (enable > 0) {
7676                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7677                         PMD_DRV_LOG(INFO,
7678                                 "Symmetric hash has already been enabled");
7679                         return;
7680                 }
7681                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7682         } else {
7683                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7684                         PMD_DRV_LOG(INFO,
7685                                 "Symmetric hash has already been disabled");
7686                         return;
7687                 }
7688                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7689         }
7690         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7691         I40E_WRITE_FLUSH(hw);
7692 }
7693
7694 /*
7695  * Get global configurations of hash function type and symmetric hash enable
7696  * per flow type (pctype). Note that global configuration means it affects all
7697  * the ports on the same NIC.
7698  */
7699 static int
7700 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7701                                    struct rte_eth_hash_global_conf *g_cfg)
7702 {
7703         uint32_t reg, mask = I40E_FLOW_TYPES;
7704         uint16_t i;
7705         enum i40e_filter_pctype pctype;
7706
7707         memset(g_cfg, 0, sizeof(*g_cfg));
7708         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7709         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7710                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7711         else
7712                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7713         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7714                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7715
7716         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7717                 if (!(mask & (1UL << i)))
7718                         continue;
7719                 mask &= ~(1UL << i);
7720                 /* Bit set indicats the coresponding flow type is supported */
7721                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7722                 /* if flowtype is invalid, continue */
7723                 if (!I40E_VALID_FLOW(i))
7724                         continue;
7725                 pctype = i40e_flowtype_to_pctype(i);
7726                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7727                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7728                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7729         }
7730
7731         return 0;
7732 }
7733
7734 static int
7735 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7736 {
7737         uint32_t i;
7738         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7739
7740         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7741                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7742                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7743                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7744                                                 g_cfg->hash_func);
7745                 return -EINVAL;
7746         }
7747
7748         /*
7749          * As i40e supports less than 32 flow types, only first 32 bits need to
7750          * be checked.
7751          */
7752         mask0 = g_cfg->valid_bit_mask[0];
7753         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7754                 if (i == 0) {
7755                         /* Check if any unsupported flow type configured */
7756                         if ((mask0 | i40e_mask) ^ i40e_mask)
7757                                 goto mask_err;
7758                 } else {
7759                         if (g_cfg->valid_bit_mask[i])
7760                                 goto mask_err;
7761                 }
7762         }
7763
7764         return 0;
7765
7766 mask_err:
7767         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7768
7769         return -EINVAL;
7770 }
7771
7772 /*
7773  * Set global configurations of hash function type and symmetric hash enable
7774  * per flow type (pctype). Note any modifying global configuration will affect
7775  * all the ports on the same NIC.
7776  */
7777 static int
7778 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7779                                    struct rte_eth_hash_global_conf *g_cfg)
7780 {
7781         int ret;
7782         uint16_t i;
7783         uint32_t reg;
7784         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7785         enum i40e_filter_pctype pctype;
7786
7787         /* Check the input parameters */
7788         ret = i40e_hash_global_config_check(g_cfg);
7789         if (ret < 0)
7790                 return ret;
7791
7792         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7793                 if (!(mask0 & (1UL << i)))
7794                         continue;
7795                 mask0 &= ~(1UL << i);
7796                 /* if flowtype is invalid, continue */
7797                 if (!I40E_VALID_FLOW(i))
7798                         continue;
7799                 pctype = i40e_flowtype_to_pctype(i);
7800                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7801                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7802                 if (hw->mac.type == I40E_MAC_X722) {
7803                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7804                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7805                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7806                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7807                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7808                                   reg);
7809                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7810                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7811                                   reg);
7812                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7813                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7814                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7815                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7816                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7817                                   reg);
7818                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7819                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7820                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7821                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7822                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7823                                   reg);
7824                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7825                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7826                                   reg);
7827                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7828                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7829                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7830                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7831                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7832                                   reg);
7833                         } else {
7834                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7835                                   reg);
7836                         }
7837                 } else {
7838                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7839                 }
7840         }
7841
7842         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7843         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7844                 /* Toeplitz */
7845                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7846                         PMD_DRV_LOG(DEBUG,
7847                                 "Hash function already set to Toeplitz");
7848                         goto out;
7849                 }
7850                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7851         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7852                 /* Simple XOR */
7853                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7854                         PMD_DRV_LOG(DEBUG,
7855                                 "Hash function already set to Simple XOR");
7856                         goto out;
7857                 }
7858                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7859         } else
7860                 /* Use the default, and keep it as it is */
7861                 goto out;
7862
7863         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7864
7865 out:
7866         I40E_WRITE_FLUSH(hw);
7867
7868         return 0;
7869 }
7870
7871 /**
7872  * Valid input sets for hash and flow director filters per PCTYPE
7873  */
7874 static uint64_t
7875 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7876                 enum rte_filter_type filter)
7877 {
7878         uint64_t valid;
7879
7880         static const uint64_t valid_hash_inset_table[] = {
7881                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7882                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7883                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7884                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7885                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7886                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7887                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7888                         I40E_INSET_FLEX_PAYLOAD,
7889                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7890                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7891                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7892                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7893                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7894                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7895                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7896                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7897                         I40E_INSET_FLEX_PAYLOAD,
7898                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7899                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7900                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7901                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7902                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7903                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7904                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7905                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7906                         I40E_INSET_FLEX_PAYLOAD,
7907                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7908                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7909                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7910                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7911                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7912                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7913                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7914                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7915                         I40E_INSET_FLEX_PAYLOAD,
7916                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7917                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7918                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7919                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7920                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7921                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7922                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7923                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7924                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7925                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7926                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7927                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7928                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7929                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7930                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7931                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7932                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7933                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7934                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7935                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7936                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7937                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7938                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7939                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7940                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7941                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7942                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7943                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7944                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7945                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7946                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7947                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7948                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7949                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7950                         I40E_INSET_FLEX_PAYLOAD,
7951                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7952                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7953                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7954                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7955                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7956                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7957                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7958                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7959                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7960                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7961                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7962                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7963                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7964                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7965                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7966                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7967                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7968                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7969                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7970                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7971                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7972                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7973                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7974                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7975                         I40E_INSET_FLEX_PAYLOAD,
7976                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7977                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7978                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7979                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7980                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7981                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7982                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7983                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7984                         I40E_INSET_FLEX_PAYLOAD,
7985                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7986                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7987                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7988                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7989                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7990                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7991                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7992                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7993                         I40E_INSET_FLEX_PAYLOAD,
7994                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7995                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7996                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7997                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7998                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7999                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8000                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8001                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8002                         I40E_INSET_FLEX_PAYLOAD,
8003                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8004                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8005                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8006                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8007                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8008                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8009                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8010                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8011                         I40E_INSET_FLEX_PAYLOAD,
8012                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8013                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8014                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8015                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8016                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8017                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8018                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8019                         I40E_INSET_FLEX_PAYLOAD,
8020                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8021                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8022                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8023                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8024                         I40E_INSET_FLEX_PAYLOAD,
8025         };
8026
8027         /**
8028          * Flow director supports only fields defined in
8029          * union rte_eth_fdir_flow.
8030          */
8031         static const uint64_t valid_fdir_inset_table[] = {
8032                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8033                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8034                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8035                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8036                 I40E_INSET_IPV4_TTL,
8037                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8038                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8039                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8040                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8041                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8042                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8043                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8044                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8045                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8046                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8047                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8048                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8049                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8050                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8051                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8052                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8053                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8054                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8055                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8056                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8057                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8058                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8059                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8060                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8061                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8062                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8063                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8064                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8065                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8066                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8067                 I40E_INSET_SCTP_VT,
8068                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8069                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8070                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8071                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8072                 I40E_INSET_IPV4_TTL,
8073                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8074                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8075                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8076                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8077                 I40E_INSET_IPV6_HOP_LIMIT,
8078                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8079                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8080                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8081                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8082                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8083                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8084                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8085                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8086                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8087                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8088                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8089                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8090                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8091                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8092                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8093                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8094                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8095                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8096                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8097                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8098                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8099                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8100                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8101                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8102                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8103                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8104                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8105                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8106                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8107                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8108                 I40E_INSET_SCTP_VT,
8109                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8110                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8111                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8112                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8113                 I40E_INSET_IPV6_HOP_LIMIT,
8114                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8115                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8116                 I40E_INSET_LAST_ETHER_TYPE,
8117         };
8118
8119         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8120                 return 0;
8121         if (filter == RTE_ETH_FILTER_HASH)
8122                 valid = valid_hash_inset_table[pctype];
8123         else
8124                 valid = valid_fdir_inset_table[pctype];
8125
8126         return valid;
8127 }
8128
8129 /**
8130  * Validate if the input set is allowed for a specific PCTYPE
8131  */
8132 static int
8133 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8134                 enum rte_filter_type filter, uint64_t inset)
8135 {
8136         uint64_t valid;
8137
8138         valid = i40e_get_valid_input_set(pctype, filter);
8139         if (inset & (~valid))
8140                 return -EINVAL;
8141
8142         return 0;
8143 }
8144
8145 /* default input set fields combination per pctype */
8146 uint64_t
8147 i40e_get_default_input_set(uint16_t pctype)
8148 {
8149         static const uint64_t default_inset_table[] = {
8150                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8151                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8152                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8153                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8154                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8155                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8156                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8157                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8158                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8159                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8160                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8161                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8162                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8163                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8164                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8165                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8166                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8167                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8168                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8169                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8170                         I40E_INSET_SCTP_VT,
8171                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8172                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8173                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8174                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8175                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8176                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8177                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8178                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8179                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8180                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8181                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8182                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8183                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8184                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8185                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8186                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8187                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8188                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8189                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8190                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8191                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8192                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8193                         I40E_INSET_SCTP_VT,
8194                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8195                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8196                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8197                         I40E_INSET_LAST_ETHER_TYPE,
8198         };
8199
8200         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8201                 return 0;
8202
8203         return default_inset_table[pctype];
8204 }
8205
8206 /**
8207  * Parse the input set from index to logical bit masks
8208  */
8209 static int
8210 i40e_parse_input_set(uint64_t *inset,
8211                      enum i40e_filter_pctype pctype,
8212                      enum rte_eth_input_set_field *field,
8213                      uint16_t size)
8214 {
8215         uint16_t i, j;
8216         int ret = -EINVAL;
8217
8218         static const struct {
8219                 enum rte_eth_input_set_field field;
8220                 uint64_t inset;
8221         } inset_convert_table[] = {
8222                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8223                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8224                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8225                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8226                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8227                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8228                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8229                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8230                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8231                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8232                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8233                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8234                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8235                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8236                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8237                         I40E_INSET_IPV6_NEXT_HDR},
8238                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8239                         I40E_INSET_IPV6_HOP_LIMIT},
8240                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8241                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8242                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8243                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8244                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8245                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8246                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8247                         I40E_INSET_SCTP_VT},
8248                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8249                         I40E_INSET_TUNNEL_DMAC},
8250                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8251                         I40E_INSET_VLAN_TUNNEL},
8252                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8253                         I40E_INSET_TUNNEL_ID},
8254                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8255                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8256                         I40E_INSET_FLEX_PAYLOAD_W1},
8257                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8258                         I40E_INSET_FLEX_PAYLOAD_W2},
8259                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8260                         I40E_INSET_FLEX_PAYLOAD_W3},
8261                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8262                         I40E_INSET_FLEX_PAYLOAD_W4},
8263                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8264                         I40E_INSET_FLEX_PAYLOAD_W5},
8265                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8266                         I40E_INSET_FLEX_PAYLOAD_W6},
8267                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8268                         I40E_INSET_FLEX_PAYLOAD_W7},
8269                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8270                         I40E_INSET_FLEX_PAYLOAD_W8},
8271         };
8272
8273         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8274                 return ret;
8275
8276         /* Only one item allowed for default or all */
8277         if (size == 1) {
8278                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8279                         *inset = i40e_get_default_input_set(pctype);
8280                         return 0;
8281                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8282                         *inset = I40E_INSET_NONE;
8283                         return 0;
8284                 }
8285         }
8286
8287         for (i = 0, *inset = 0; i < size; i++) {
8288                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8289                         if (field[i] == inset_convert_table[j].field) {
8290                                 *inset |= inset_convert_table[j].inset;
8291                                 break;
8292                         }
8293                 }
8294
8295                 /* It contains unsupported input set, return immediately */
8296                 if (j == RTE_DIM(inset_convert_table))
8297                         return ret;
8298         }
8299
8300         return 0;
8301 }
8302
8303 /**
8304  * Translate the input set from bit masks to register aware bit masks
8305  * and vice versa
8306  */
8307 static uint64_t
8308 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8309 {
8310         uint64_t val = 0;
8311         uint16_t i;
8312
8313         struct inset_map {
8314                 uint64_t inset;
8315                 uint64_t inset_reg;
8316         };
8317
8318         static const struct inset_map inset_map_common[] = {
8319                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8320                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8321                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8322                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8323                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8324                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8325                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8326                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8327                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8328                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8329                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8330                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8331                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8332                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8333                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8334                 {I40E_INSET_TUNNEL_DMAC,
8335                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8336                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8337                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8338                 {I40E_INSET_TUNNEL_SRC_PORT,
8339                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8340                 {I40E_INSET_TUNNEL_DST_PORT,
8341                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8342                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8343                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8344                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8345                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8346                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8347                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8348                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8349                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8350                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8351         };
8352
8353     /* some different registers map in x722*/
8354         static const struct inset_map inset_map_diff_x722[] = {
8355                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8356                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8357                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8358                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8359         };
8360
8361         static const struct inset_map inset_map_diff_not_x722[] = {
8362                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8363                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8364                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8365                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8366         };
8367
8368         if (input == 0)
8369                 return val;
8370
8371         /* Translate input set to register aware inset */
8372         if (type == I40E_MAC_X722) {
8373                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8374                         if (input & inset_map_diff_x722[i].inset)
8375                                 val |= inset_map_diff_x722[i].inset_reg;
8376                 }
8377         } else {
8378                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8379                         if (input & inset_map_diff_not_x722[i].inset)
8380                                 val |= inset_map_diff_not_x722[i].inset_reg;
8381                 }
8382         }
8383
8384         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8385                 if (input & inset_map_common[i].inset)
8386                         val |= inset_map_common[i].inset_reg;
8387         }
8388
8389         return val;
8390 }
8391
8392 static int
8393 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8394 {
8395         uint8_t i, idx = 0;
8396         uint64_t inset_need_mask = inset;
8397
8398         static const struct {
8399                 uint64_t inset;
8400                 uint32_t mask;
8401         } inset_mask_map[] = {
8402                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8403                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8404                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8405                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8406                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8407                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8408                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8409                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8410         };
8411
8412         if (!inset || !mask || !nb_elem)
8413                 return 0;
8414
8415         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8416                 /* Clear the inset bit, if no MASK is required,
8417                  * for example proto + ttl
8418                  */
8419                 if ((inset & inset_mask_map[i].inset) ==
8420                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8421                         inset_need_mask &= ~inset_mask_map[i].inset;
8422                 if (!inset_need_mask)
8423                         return 0;
8424         }
8425         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8426                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8427                     inset_mask_map[i].inset) {
8428                         if (idx >= nb_elem) {
8429                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8430                                 return -EINVAL;
8431                         }
8432                         mask[idx] = inset_mask_map[i].mask;
8433                         idx++;
8434                 }
8435         }
8436
8437         return idx;
8438 }
8439
8440 static void
8441 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8442 {
8443         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8444
8445         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8446         if (reg != val)
8447                 i40e_write_rx_ctl(hw, addr, val);
8448         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8449                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8450 }
8451
8452 static void
8453 i40e_filter_input_set_init(struct i40e_pf *pf)
8454 {
8455         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8456         enum i40e_filter_pctype pctype;
8457         uint64_t input_set, inset_reg;
8458         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8459         int num, i;
8460
8461         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8462              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8463                 if (hw->mac.type == I40E_MAC_X722) {
8464                         if (!I40E_VALID_PCTYPE_X722(pctype))
8465                                 continue;
8466                 } else {
8467                         if (!I40E_VALID_PCTYPE(pctype))
8468                                 continue;
8469                 }
8470
8471                 input_set = i40e_get_default_input_set(pctype);
8472
8473                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8474                                                    I40E_INSET_MASK_NUM_REG);
8475                 if (num < 0)
8476                         return;
8477                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8478                                         input_set);
8479
8480                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8481                                       (uint32_t)(inset_reg & UINT32_MAX));
8482                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8483                                      (uint32_t)((inset_reg >>
8484                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8485                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8486                                       (uint32_t)(inset_reg & UINT32_MAX));
8487                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8488                                      (uint32_t)((inset_reg >>
8489                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8490
8491                 for (i = 0; i < num; i++) {
8492                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8493                                              mask_reg[i]);
8494                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8495                                              mask_reg[i]);
8496                 }
8497                 /*clear unused mask registers of the pctype */
8498                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8499                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8500                                              0);
8501                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8502                                              0);
8503                 }
8504                 I40E_WRITE_FLUSH(hw);
8505
8506                 /* store the default input set */
8507                 pf->hash_input_set[pctype] = input_set;
8508                 pf->fdir.input_set[pctype] = input_set;
8509         }
8510 }
8511
8512 int
8513 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8514                          struct rte_eth_input_set_conf *conf)
8515 {
8516         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8517         enum i40e_filter_pctype pctype;
8518         uint64_t input_set, inset_reg = 0;
8519         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8520         int ret, i, num;
8521
8522         if (!conf) {
8523                 PMD_DRV_LOG(ERR, "Invalid pointer");
8524                 return -EFAULT;
8525         }
8526         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8527             conf->op != RTE_ETH_INPUT_SET_ADD) {
8528                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8529                 return -EINVAL;
8530         }
8531
8532         if (!I40E_VALID_FLOW(conf->flow_type)) {
8533                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8534                 return -EINVAL;
8535         }
8536
8537         if (hw->mac.type == I40E_MAC_X722) {
8538                 /* get translated pctype value in fd pctype register */
8539                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8540                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8541                         conf->flow_type)));
8542         } else
8543                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8544
8545         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8546                                    conf->inset_size);
8547         if (ret) {
8548                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8549                 return -EINVAL;
8550         }
8551         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8552                                     input_set) != 0) {
8553                 PMD_DRV_LOG(ERR, "Invalid input set");
8554                 return -EINVAL;
8555         }
8556         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8557                 /* get inset value in register */
8558                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8559                 inset_reg <<= I40E_32_BIT_WIDTH;
8560                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8561                 input_set |= pf->hash_input_set[pctype];
8562         }
8563         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8564                                            I40E_INSET_MASK_NUM_REG);
8565         if (num < 0)
8566                 return -EINVAL;
8567
8568         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8569
8570         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8571                               (uint32_t)(inset_reg & UINT32_MAX));
8572         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8573                              (uint32_t)((inset_reg >>
8574                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8575
8576         for (i = 0; i < num; i++)
8577                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8578                                      mask_reg[i]);
8579         /*clear unused mask registers of the pctype */
8580         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8581                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8582                                      0);
8583         I40E_WRITE_FLUSH(hw);
8584
8585         pf->hash_input_set[pctype] = input_set;
8586         return 0;
8587 }
8588
8589 int
8590 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8591                          struct rte_eth_input_set_conf *conf)
8592 {
8593         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8594         enum i40e_filter_pctype pctype;
8595         uint64_t input_set, inset_reg = 0;
8596         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8597         int ret, i, num;
8598
8599         if (!hw || !conf) {
8600                 PMD_DRV_LOG(ERR, "Invalid pointer");
8601                 return -EFAULT;
8602         }
8603         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8604             conf->op != RTE_ETH_INPUT_SET_ADD) {
8605                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8606                 return -EINVAL;
8607         }
8608
8609         if (!I40E_VALID_FLOW(conf->flow_type)) {
8610                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8611                 return -EINVAL;
8612         }
8613
8614         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8615
8616         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8617                                    conf->inset_size);
8618         if (ret) {
8619                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8620                 return -EINVAL;
8621         }
8622         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8623                                     input_set) != 0) {
8624                 PMD_DRV_LOG(ERR, "Invalid input set");
8625                 return -EINVAL;
8626         }
8627
8628         /* get inset value in register */
8629         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8630         inset_reg <<= I40E_32_BIT_WIDTH;
8631         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8632
8633         /* Can not change the inset reg for flex payload for fdir,
8634          * it is done by writing I40E_PRTQF_FD_FLXINSET
8635          * in i40e_set_flex_mask_on_pctype.
8636          */
8637         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8638                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8639         else
8640                 input_set |= pf->fdir.input_set[pctype];
8641         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8642                                            I40E_INSET_MASK_NUM_REG);
8643         if (num < 0)
8644                 return -EINVAL;
8645
8646         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8647
8648         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8649                               (uint32_t)(inset_reg & UINT32_MAX));
8650         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8651                              (uint32_t)((inset_reg >>
8652                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8653
8654         for (i = 0; i < num; i++)
8655                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8656                                      mask_reg[i]);
8657         /*clear unused mask registers of the pctype */
8658         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8659                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8660                                      0);
8661         I40E_WRITE_FLUSH(hw);
8662
8663         pf->fdir.input_set[pctype] = input_set;
8664         return 0;
8665 }
8666
8667 static int
8668 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8669 {
8670         int ret = 0;
8671
8672         if (!hw || !info) {
8673                 PMD_DRV_LOG(ERR, "Invalid pointer");
8674                 return -EFAULT;
8675         }
8676
8677         switch (info->info_type) {
8678         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8679                 i40e_get_symmetric_hash_enable_per_port(hw,
8680                                         &(info->info.enable));
8681                 break;
8682         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8683                 ret = i40e_get_hash_filter_global_config(hw,
8684                                 &(info->info.global_conf));
8685                 break;
8686         default:
8687                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8688                                                         info->info_type);
8689                 ret = -EINVAL;
8690                 break;
8691         }
8692
8693         return ret;
8694 }
8695
8696 static int
8697 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8698 {
8699         int ret = 0;
8700
8701         if (!hw || !info) {
8702                 PMD_DRV_LOG(ERR, "Invalid pointer");
8703                 return -EFAULT;
8704         }
8705
8706         switch (info->info_type) {
8707         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8708                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8709                 break;
8710         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8711                 ret = i40e_set_hash_filter_global_config(hw,
8712                                 &(info->info.global_conf));
8713                 break;
8714         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8715                 ret = i40e_hash_filter_inset_select(hw,
8716                                                &(info->info.input_set_conf));
8717                 break;
8718
8719         default:
8720                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8721                                                         info->info_type);
8722                 ret = -EINVAL;
8723                 break;
8724         }
8725
8726         return ret;
8727 }
8728
8729 /* Operations for hash function */
8730 static int
8731 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8732                       enum rte_filter_op filter_op,
8733                       void *arg)
8734 {
8735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8736         int ret = 0;
8737
8738         switch (filter_op) {
8739         case RTE_ETH_FILTER_NOP:
8740                 break;
8741         case RTE_ETH_FILTER_GET:
8742                 ret = i40e_hash_filter_get(hw,
8743                         (struct rte_eth_hash_filter_info *)arg);
8744                 break;
8745         case RTE_ETH_FILTER_SET:
8746                 ret = i40e_hash_filter_set(hw,
8747                         (struct rte_eth_hash_filter_info *)arg);
8748                 break;
8749         default:
8750                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8751                                                                 filter_op);
8752                 ret = -ENOTSUP;
8753                 break;
8754         }
8755
8756         return ret;
8757 }
8758
8759 /* Convert ethertype filter structure */
8760 static int
8761 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8762                               struct i40e_ethertype_filter *filter)
8763 {
8764         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8765         filter->input.ether_type = input->ether_type;
8766         filter->flags = input->flags;
8767         filter->queue = input->queue;
8768
8769         return 0;
8770 }
8771
8772 /* Check if there exists the ehtertype filter */
8773 struct i40e_ethertype_filter *
8774 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8775                                 const struct i40e_ethertype_filter_input *input)
8776 {
8777         int ret;
8778
8779         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8780         if (ret < 0)
8781                 return NULL;
8782
8783         return ethertype_rule->hash_map[ret];
8784 }
8785
8786 /* Add ethertype filter in SW list */
8787 static int
8788 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8789                                 struct i40e_ethertype_filter *filter)
8790 {
8791         struct i40e_ethertype_rule *rule = &pf->ethertype;
8792         int ret;
8793
8794         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8795         if (ret < 0) {
8796                 PMD_DRV_LOG(ERR,
8797                             "Failed to insert ethertype filter"
8798                             " to hash table %d!",
8799                             ret);
8800                 return ret;
8801         }
8802         rule->hash_map[ret] = filter;
8803
8804         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8805
8806         return 0;
8807 }
8808
8809 /* Delete ethertype filter in SW list */
8810 int
8811 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8812                              struct i40e_ethertype_filter_input *input)
8813 {
8814         struct i40e_ethertype_rule *rule = &pf->ethertype;
8815         struct i40e_ethertype_filter *filter;
8816         int ret;
8817
8818         ret = rte_hash_del_key(rule->hash_table, input);
8819         if (ret < 0) {
8820                 PMD_DRV_LOG(ERR,
8821                             "Failed to delete ethertype filter"
8822                             " to hash table %d!",
8823                             ret);
8824                 return ret;
8825         }
8826         filter = rule->hash_map[ret];
8827         rule->hash_map[ret] = NULL;
8828
8829         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8830         rte_free(filter);
8831
8832         return 0;
8833 }
8834
8835 /*
8836  * Configure ethertype filter, which can director packet by filtering
8837  * with mac address and ether_type or only ether_type
8838  */
8839 int
8840 i40e_ethertype_filter_set(struct i40e_pf *pf,
8841                         struct rte_eth_ethertype_filter *filter,
8842                         bool add)
8843 {
8844         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8845         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8846         struct i40e_ethertype_filter *ethertype_filter, *node;
8847         struct i40e_ethertype_filter check_filter;
8848         struct i40e_control_filter_stats stats;
8849         uint16_t flags = 0;
8850         int ret;
8851
8852         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8853                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8854                 return -EINVAL;
8855         }
8856         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8857                 filter->ether_type == ETHER_TYPE_IPv6) {
8858                 PMD_DRV_LOG(ERR,
8859                         "unsupported ether_type(0x%04x) in control packet filter.",
8860                         filter->ether_type);
8861                 return -EINVAL;
8862         }
8863         if (filter->ether_type == ETHER_TYPE_VLAN)
8864                 PMD_DRV_LOG(WARNING,
8865                         "filter vlan ether_type in first tag is not supported.");
8866
8867         /* Check if there is the filter in SW list */
8868         memset(&check_filter, 0, sizeof(check_filter));
8869         i40e_ethertype_filter_convert(filter, &check_filter);
8870         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8871                                                &check_filter.input);
8872         if (add && node) {
8873                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8874                 return -EINVAL;
8875         }
8876
8877         if (!add && !node) {
8878                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8879                 return -EINVAL;
8880         }
8881
8882         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8883                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8884         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8885                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8886         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8887
8888         memset(&stats, 0, sizeof(stats));
8889         ret = i40e_aq_add_rem_control_packet_filter(hw,
8890                         filter->mac_addr.addr_bytes,
8891                         filter->ether_type, flags,
8892                         pf->main_vsi->seid,
8893                         filter->queue, add, &stats, NULL);
8894
8895         PMD_DRV_LOG(INFO,
8896                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8897                 ret, stats.mac_etype_used, stats.etype_used,
8898                 stats.mac_etype_free, stats.etype_free);
8899         if (ret < 0)
8900                 return -ENOSYS;
8901
8902         /* Add or delete a filter in SW list */
8903         if (add) {
8904                 ethertype_filter = rte_zmalloc("ethertype_filter",
8905                                        sizeof(*ethertype_filter), 0);
8906                 rte_memcpy(ethertype_filter, &check_filter,
8907                            sizeof(check_filter));
8908                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8909         } else {
8910                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8911         }
8912
8913         return ret;
8914 }
8915
8916 /*
8917  * Handle operations for ethertype filter.
8918  */
8919 static int
8920 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8921                                 enum rte_filter_op filter_op,
8922                                 void *arg)
8923 {
8924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8925         int ret = 0;
8926
8927         if (filter_op == RTE_ETH_FILTER_NOP)
8928                 return ret;
8929
8930         if (arg == NULL) {
8931                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8932                             filter_op);
8933                 return -EINVAL;
8934         }
8935
8936         switch (filter_op) {
8937         case RTE_ETH_FILTER_ADD:
8938                 ret = i40e_ethertype_filter_set(pf,
8939                         (struct rte_eth_ethertype_filter *)arg,
8940                         TRUE);
8941                 break;
8942         case RTE_ETH_FILTER_DELETE:
8943                 ret = i40e_ethertype_filter_set(pf,
8944                         (struct rte_eth_ethertype_filter *)arg,
8945                         FALSE);
8946                 break;
8947         default:
8948                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8949                 ret = -ENOSYS;
8950                 break;
8951         }
8952         return ret;
8953 }
8954
8955 static int
8956 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8957                      enum rte_filter_type filter_type,
8958                      enum rte_filter_op filter_op,
8959                      void *arg)
8960 {
8961         int ret = 0;
8962
8963         if (dev == NULL)
8964                 return -EINVAL;
8965
8966         switch (filter_type) {
8967         case RTE_ETH_FILTER_NONE:
8968                 /* For global configuration */
8969                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8970                 break;
8971         case RTE_ETH_FILTER_HASH:
8972                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8973                 break;
8974         case RTE_ETH_FILTER_MACVLAN:
8975                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8976                 break;
8977         case RTE_ETH_FILTER_ETHERTYPE:
8978                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8979                 break;
8980         case RTE_ETH_FILTER_TUNNEL:
8981                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8982                 break;
8983         case RTE_ETH_FILTER_FDIR:
8984                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8985                 break;
8986         case RTE_ETH_FILTER_GENERIC:
8987                 if (filter_op != RTE_ETH_FILTER_GET)
8988                         return -EINVAL;
8989                 *(const void **)arg = &i40e_flow_ops;
8990                 break;
8991         default:
8992                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8993                                                         filter_type);
8994                 ret = -EINVAL;
8995                 break;
8996         }
8997
8998         return ret;
8999 }
9000
9001 /*
9002  * Check and enable Extended Tag.
9003  * Enabling Extended Tag is important for 40G performance.
9004  */
9005 static void
9006 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9007 {
9008         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9009         uint32_t buf = 0;
9010         int ret;
9011
9012         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9013                                       PCI_DEV_CAP_REG);
9014         if (ret < 0) {
9015                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9016                             PCI_DEV_CAP_REG);
9017                 return;
9018         }
9019         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9020                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9021                 return;
9022         }
9023
9024         buf = 0;
9025         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9026                                       PCI_DEV_CTRL_REG);
9027         if (ret < 0) {
9028                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9029                             PCI_DEV_CTRL_REG);
9030                 return;
9031         }
9032         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9033                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9034                 return;
9035         }
9036         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9037         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9038                                        PCI_DEV_CTRL_REG);
9039         if (ret < 0) {
9040                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9041                             PCI_DEV_CTRL_REG);
9042                 return;
9043         }
9044 }
9045
9046 /*
9047  * As some registers wouldn't be reset unless a global hardware reset,
9048  * hardware initialization is needed to put those registers into an
9049  * expected initial state.
9050  */
9051 static void
9052 i40e_hw_init(struct rte_eth_dev *dev)
9053 {
9054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9055
9056         i40e_enable_extended_tag(dev);
9057
9058         /* clear the PF Queue Filter control register */
9059         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9060
9061         /* Disable symmetric hash per port */
9062         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9063 }
9064
9065 enum i40e_filter_pctype
9066 i40e_flowtype_to_pctype(uint16_t flow_type)
9067 {
9068         static const enum i40e_filter_pctype pctype_table[] = {
9069                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9070                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9071                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9072                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9073                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9074                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9075                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9076                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9077                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9078                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9079                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9080                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9081                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9082                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9083                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9084                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9085                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9086                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9087                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9088         };
9089
9090         return pctype_table[flow_type];
9091 }
9092
9093 uint16_t
9094 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9095 {
9096         static const uint16_t flowtype_table[] = {
9097                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9098                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9099                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9100                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9101                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9102                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9103                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9104                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9105                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9106                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9107                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9108                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9109                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9110                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9111                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9112                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9113                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9114                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9115                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9116                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9117                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9118                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9119                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9120                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9121                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9122                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9123                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9124                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9125                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9126                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9127                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9128         };
9129
9130         return flowtype_table[pctype];
9131 }
9132
9133 /*
9134  * On X710, performance number is far from the expectation on recent firmware
9135  * versions; on XL710, performance number is also far from the expectation on
9136  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9137  * mode is enabled and port MAC address is equal to the packet destination MAC
9138  * address. The fix for this issue may not be integrated in the following
9139  * firmware version. So the workaround in software driver is needed. It needs
9140  * to modify the initial values of 3 internal only registers for both X710 and
9141  * XL710. Note that the values for X710 or XL710 could be different, and the
9142  * workaround can be removed when it is fixed in firmware in the future.
9143  */
9144
9145 /* For both X710 and XL710 */
9146 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9147 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9148
9149 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9150 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9151
9152 /* For X722 */
9153 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9154 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9155
9156 /* For X710 */
9157 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9158 /* For XL710 */
9159 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9160 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9161
9162 static int
9163 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9164 {
9165         enum i40e_status_code status;
9166         struct i40e_aq_get_phy_abilities_resp phy_ab;
9167         int ret = -ENOTSUP;
9168
9169         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9170                                               NULL);
9171
9172         if (status)
9173                 return ret;
9174
9175         return 0;
9176 }
9177
9178 static void
9179 i40e_configure_registers(struct i40e_hw *hw)
9180 {
9181         static struct {
9182                 uint32_t addr;
9183                 uint64_t val;
9184         } reg_table[] = {
9185                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9186                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9187                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9188         };
9189         uint64_t reg;
9190         uint32_t i;
9191         int ret;
9192
9193         for (i = 0; i < RTE_DIM(reg_table); i++) {
9194                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9195                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9196                                 reg_table[i].val =
9197                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9198                         else /* For X710/XL710/XXV710 */
9199                                 reg_table[i].val =
9200                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9201                 }
9202
9203                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9204                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9205                                 reg_table[i].val =
9206                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9207                         else /* For X710/XL710/XXV710 */
9208                                 reg_table[i].val =
9209                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9210                 }
9211
9212                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9213                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9214                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9215                                 reg_table[i].val =
9216                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9217                         else /* For X710 */
9218                                 reg_table[i].val =
9219                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9220                 }
9221
9222                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9223                                                         &reg, NULL);
9224                 if (ret < 0) {
9225                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9226                                                         reg_table[i].addr);
9227                         break;
9228                 }
9229                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9230                                                 reg_table[i].addr, reg);
9231                 if (reg == reg_table[i].val)
9232                         continue;
9233
9234                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9235                                                 reg_table[i].val, NULL);
9236                 if (ret < 0) {
9237                         PMD_DRV_LOG(ERR,
9238                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9239                                 reg_table[i].val, reg_table[i].addr);
9240                         break;
9241                 }
9242                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9243                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9244         }
9245 }
9246
9247 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9248 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9249 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9250 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9251 static int
9252 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9253 {
9254         uint32_t reg;
9255         int ret;
9256
9257         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9258                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9259                 return -EINVAL;
9260         }
9261
9262         /* Configure for double VLAN RX stripping */
9263         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9264         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9265                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9266                 ret = i40e_aq_debug_write_register(hw,
9267                                                    I40E_VSI_TSR(vsi->vsi_id),
9268                                                    reg, NULL);
9269                 if (ret < 0) {
9270                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9271                                     vsi->vsi_id);
9272                         return I40E_ERR_CONFIG;
9273                 }
9274         }
9275
9276         /* Configure for double VLAN TX insertion */
9277         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9278         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9279                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9280                 ret = i40e_aq_debug_write_register(hw,
9281                                                    I40E_VSI_L2TAGSTXVALID(
9282                                                    vsi->vsi_id), reg, NULL);
9283                 if (ret < 0) {
9284                         PMD_DRV_LOG(ERR,
9285                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9286                                 vsi->vsi_id);
9287                         return I40E_ERR_CONFIG;
9288                 }
9289         }
9290
9291         return 0;
9292 }
9293
9294 /**
9295  * i40e_aq_add_mirror_rule
9296  * @hw: pointer to the hardware structure
9297  * @seid: VEB seid to add mirror rule to
9298  * @dst_id: destination vsi seid
9299  * @entries: Buffer which contains the entities to be mirrored
9300  * @count: number of entities contained in the buffer
9301  * @rule_id:the rule_id of the rule to be added
9302  *
9303  * Add a mirror rule for a given veb.
9304  *
9305  **/
9306 static enum i40e_status_code
9307 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9308                         uint16_t seid, uint16_t dst_id,
9309                         uint16_t rule_type, uint16_t *entries,
9310                         uint16_t count, uint16_t *rule_id)
9311 {
9312         struct i40e_aq_desc desc;
9313         struct i40e_aqc_add_delete_mirror_rule cmd;
9314         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9315                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9316                 &desc.params.raw;
9317         uint16_t buff_len;
9318         enum i40e_status_code status;
9319
9320         i40e_fill_default_direct_cmd_desc(&desc,
9321                                           i40e_aqc_opc_add_mirror_rule);
9322         memset(&cmd, 0, sizeof(cmd));
9323
9324         buff_len = sizeof(uint16_t) * count;
9325         desc.datalen = rte_cpu_to_le_16(buff_len);
9326         if (buff_len > 0)
9327                 desc.flags |= rte_cpu_to_le_16(
9328                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9329         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9330                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9331         cmd.num_entries = rte_cpu_to_le_16(count);
9332         cmd.seid = rte_cpu_to_le_16(seid);
9333         cmd.destination = rte_cpu_to_le_16(dst_id);
9334
9335         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9336         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9337         PMD_DRV_LOG(INFO,
9338                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9339                 hw->aq.asq_last_status, resp->rule_id,
9340                 resp->mirror_rules_used, resp->mirror_rules_free);
9341         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9342
9343         return status;
9344 }
9345
9346 /**
9347  * i40e_aq_del_mirror_rule
9348  * @hw: pointer to the hardware structure
9349  * @seid: VEB seid to add mirror rule to
9350  * @entries: Buffer which contains the entities to be mirrored
9351  * @count: number of entities contained in the buffer
9352  * @rule_id:the rule_id of the rule to be delete
9353  *
9354  * Delete a mirror rule for a given veb.
9355  *
9356  **/
9357 static enum i40e_status_code
9358 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9359                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9360                 uint16_t count, uint16_t rule_id)
9361 {
9362         struct i40e_aq_desc desc;
9363         struct i40e_aqc_add_delete_mirror_rule cmd;
9364         uint16_t buff_len = 0;
9365         enum i40e_status_code status;
9366         void *buff = NULL;
9367
9368         i40e_fill_default_direct_cmd_desc(&desc,
9369                                           i40e_aqc_opc_delete_mirror_rule);
9370         memset(&cmd, 0, sizeof(cmd));
9371         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9372                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9373                                                           I40E_AQ_FLAG_RD));
9374                 cmd.num_entries = count;
9375                 buff_len = sizeof(uint16_t) * count;
9376                 desc.datalen = rte_cpu_to_le_16(buff_len);
9377                 buff = (void *)entries;
9378         } else
9379                 /* rule id is filled in destination field for deleting mirror rule */
9380                 cmd.destination = rte_cpu_to_le_16(rule_id);
9381
9382         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9383                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9384         cmd.seid = rte_cpu_to_le_16(seid);
9385
9386         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9387         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9388
9389         return status;
9390 }
9391
9392 /**
9393  * i40e_mirror_rule_set
9394  * @dev: pointer to the hardware structure
9395  * @mirror_conf: mirror rule info
9396  * @sw_id: mirror rule's sw_id
9397  * @on: enable/disable
9398  *
9399  * set a mirror rule.
9400  *
9401  **/
9402 static int
9403 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9404                         struct rte_eth_mirror_conf *mirror_conf,
9405                         uint8_t sw_id, uint8_t on)
9406 {
9407         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9408         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9409         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9410         struct i40e_mirror_rule *parent = NULL;
9411         uint16_t seid, dst_seid, rule_id;
9412         uint16_t i, j = 0;
9413         int ret;
9414
9415         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9416
9417         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9418                 PMD_DRV_LOG(ERR,
9419                         "mirror rule can not be configured without veb or vfs.");
9420                 return -ENOSYS;
9421         }
9422         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9423                 PMD_DRV_LOG(ERR, "mirror table is full.");
9424                 return -ENOSPC;
9425         }
9426         if (mirror_conf->dst_pool > pf->vf_num) {
9427                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9428                                  mirror_conf->dst_pool);
9429                 return -EINVAL;
9430         }
9431
9432         seid = pf->main_vsi->veb->seid;
9433
9434         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9435                 if (sw_id <= it->index) {
9436                         mirr_rule = it;
9437                         break;
9438                 }
9439                 parent = it;
9440         }
9441         if (mirr_rule && sw_id == mirr_rule->index) {
9442                 if (on) {
9443                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9444                         return -EEXIST;
9445                 } else {
9446                         ret = i40e_aq_del_mirror_rule(hw, seid,
9447                                         mirr_rule->rule_type,
9448                                         mirr_rule->entries,
9449                                         mirr_rule->num_entries, mirr_rule->id);
9450                         if (ret < 0) {
9451                                 PMD_DRV_LOG(ERR,
9452                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9453                                         ret, hw->aq.asq_last_status);
9454                                 return -ENOSYS;
9455                         }
9456                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9457                         rte_free(mirr_rule);
9458                         pf->nb_mirror_rule--;
9459                         return 0;
9460                 }
9461         } else if (!on) {
9462                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9463                 return -ENOENT;
9464         }
9465
9466         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9467                                 sizeof(struct i40e_mirror_rule) , 0);
9468         if (!mirr_rule) {
9469                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9470                 return I40E_ERR_NO_MEMORY;
9471         }
9472         switch (mirror_conf->rule_type) {
9473         case ETH_MIRROR_VLAN:
9474                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9475                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9476                                 mirr_rule->entries[j] =
9477                                         mirror_conf->vlan.vlan_id[i];
9478                                 j++;
9479                         }
9480                 }
9481                 if (j == 0) {
9482                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9483                         rte_free(mirr_rule);
9484                         return -EINVAL;
9485                 }
9486                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9487                 break;
9488         case ETH_MIRROR_VIRTUAL_POOL_UP:
9489         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9490                 /* check if the specified pool bit is out of range */
9491                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9492                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9493                         rte_free(mirr_rule);
9494                         return -EINVAL;
9495                 }
9496                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9497                         if (mirror_conf->pool_mask & (1ULL << i)) {
9498                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9499                                 j++;
9500                         }
9501                 }
9502                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9503                         /* add pf vsi to entries */
9504                         mirr_rule->entries[j] = pf->main_vsi_seid;
9505                         j++;
9506                 }
9507                 if (j == 0) {
9508                         PMD_DRV_LOG(ERR, "pool is not specified.");
9509                         rte_free(mirr_rule);
9510                         return -EINVAL;
9511                 }
9512                 /* egress and ingress in aq commands means from switch but not port */
9513                 mirr_rule->rule_type =
9514                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9515                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9516                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9517                 break;
9518         case ETH_MIRROR_UPLINK_PORT:
9519                 /* egress and ingress in aq commands means from switch but not port*/
9520                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9521                 break;
9522         case ETH_MIRROR_DOWNLINK_PORT:
9523                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9524                 break;
9525         default:
9526                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9527                         mirror_conf->rule_type);
9528                 rte_free(mirr_rule);
9529                 return -EINVAL;
9530         }
9531
9532         /* If the dst_pool is equal to vf_num, consider it as PF */
9533         if (mirror_conf->dst_pool == pf->vf_num)
9534                 dst_seid = pf->main_vsi_seid;
9535         else
9536                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9537
9538         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9539                                       mirr_rule->rule_type, mirr_rule->entries,
9540                                       j, &rule_id);
9541         if (ret < 0) {
9542                 PMD_DRV_LOG(ERR,
9543                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9544                         ret, hw->aq.asq_last_status);
9545                 rte_free(mirr_rule);
9546                 return -ENOSYS;
9547         }
9548
9549         mirr_rule->index = sw_id;
9550         mirr_rule->num_entries = j;
9551         mirr_rule->id = rule_id;
9552         mirr_rule->dst_vsi_seid = dst_seid;
9553
9554         if (parent)
9555                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9556         else
9557                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9558
9559         pf->nb_mirror_rule++;
9560         return 0;
9561 }
9562
9563 /**
9564  * i40e_mirror_rule_reset
9565  * @dev: pointer to the device
9566  * @sw_id: mirror rule's sw_id
9567  *
9568  * reset a mirror rule.
9569  *
9570  **/
9571 static int
9572 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9573 {
9574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9576         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9577         uint16_t seid;
9578         int ret;
9579
9580         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9581
9582         seid = pf->main_vsi->veb->seid;
9583
9584         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9585                 if (sw_id == it->index) {
9586                         mirr_rule = it;
9587                         break;
9588                 }
9589         }
9590         if (mirr_rule) {
9591                 ret = i40e_aq_del_mirror_rule(hw, seid,
9592                                 mirr_rule->rule_type,
9593                                 mirr_rule->entries,
9594                                 mirr_rule->num_entries, mirr_rule->id);
9595                 if (ret < 0) {
9596                         PMD_DRV_LOG(ERR,
9597                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9598                                 ret, hw->aq.asq_last_status);
9599                         return -ENOSYS;
9600                 }
9601                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9602                 rte_free(mirr_rule);
9603                 pf->nb_mirror_rule--;
9604         } else {
9605                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9606                 return -ENOENT;
9607         }
9608         return 0;
9609 }
9610
9611 static uint64_t
9612 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9613 {
9614         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9615         uint64_t systim_cycles;
9616
9617         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9618         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9619                         << 32;
9620
9621         return systim_cycles;
9622 }
9623
9624 static uint64_t
9625 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9626 {
9627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9628         uint64_t rx_tstamp;
9629
9630         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9631         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9632                         << 32;
9633
9634         return rx_tstamp;
9635 }
9636
9637 static uint64_t
9638 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9639 {
9640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9641         uint64_t tx_tstamp;
9642
9643         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9644         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9645                         << 32;
9646
9647         return tx_tstamp;
9648 }
9649
9650 static void
9651 i40e_start_timecounters(struct rte_eth_dev *dev)
9652 {
9653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9654         struct i40e_adapter *adapter =
9655                         (struct i40e_adapter *)dev->data->dev_private;
9656         struct rte_eth_link link;
9657         uint32_t tsync_inc_l;
9658         uint32_t tsync_inc_h;
9659
9660         /* Get current link speed. */
9661         memset(&link, 0, sizeof(link));
9662         i40e_dev_link_update(dev, 1);
9663         rte_i40e_dev_atomic_read_link_status(dev, &link);
9664
9665         switch (link.link_speed) {
9666         case ETH_SPEED_NUM_40G:
9667                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9668                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9669                 break;
9670         case ETH_SPEED_NUM_10G:
9671                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9672                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9673                 break;
9674         case ETH_SPEED_NUM_1G:
9675                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9676                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9677                 break;
9678         default:
9679                 tsync_inc_l = 0x0;
9680                 tsync_inc_h = 0x0;
9681         }
9682
9683         /* Set the timesync increment value. */
9684         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9685         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9686
9687         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9688         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9689         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9690
9691         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9692         adapter->systime_tc.cc_shift = 0;
9693         adapter->systime_tc.nsec_mask = 0;
9694
9695         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9696         adapter->rx_tstamp_tc.cc_shift = 0;
9697         adapter->rx_tstamp_tc.nsec_mask = 0;
9698
9699         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9700         adapter->tx_tstamp_tc.cc_shift = 0;
9701         adapter->tx_tstamp_tc.nsec_mask = 0;
9702 }
9703
9704 static int
9705 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9706 {
9707         struct i40e_adapter *adapter =
9708                         (struct i40e_adapter *)dev->data->dev_private;
9709
9710         adapter->systime_tc.nsec += delta;
9711         adapter->rx_tstamp_tc.nsec += delta;
9712         adapter->tx_tstamp_tc.nsec += delta;
9713
9714         return 0;
9715 }
9716
9717 static int
9718 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9719 {
9720         uint64_t ns;
9721         struct i40e_adapter *adapter =
9722                         (struct i40e_adapter *)dev->data->dev_private;
9723
9724         ns = rte_timespec_to_ns(ts);
9725
9726         /* Set the timecounters to a new value. */
9727         adapter->systime_tc.nsec = ns;
9728         adapter->rx_tstamp_tc.nsec = ns;
9729         adapter->tx_tstamp_tc.nsec = ns;
9730
9731         return 0;
9732 }
9733
9734 static int
9735 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9736 {
9737         uint64_t ns, systime_cycles;
9738         struct i40e_adapter *adapter =
9739                         (struct i40e_adapter *)dev->data->dev_private;
9740
9741         systime_cycles = i40e_read_systime_cyclecounter(dev);
9742         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9743         *ts = rte_ns_to_timespec(ns);
9744
9745         return 0;
9746 }
9747
9748 static int
9749 i40e_timesync_enable(struct rte_eth_dev *dev)
9750 {
9751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9752         uint32_t tsync_ctl_l;
9753         uint32_t tsync_ctl_h;
9754
9755         /* Stop the timesync system time. */
9756         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9757         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9758         /* Reset the timesync system time value. */
9759         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9760         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9761
9762         i40e_start_timecounters(dev);
9763
9764         /* Clear timesync registers. */
9765         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9766         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9767         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9768         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9769         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9770         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9771
9772         /* Enable timestamping of PTP packets. */
9773         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9774         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9775
9776         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9777         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9778         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9779
9780         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9781         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9782
9783         return 0;
9784 }
9785
9786 static int
9787 i40e_timesync_disable(struct rte_eth_dev *dev)
9788 {
9789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9790         uint32_t tsync_ctl_l;
9791         uint32_t tsync_ctl_h;
9792
9793         /* Disable timestamping of transmitted PTP packets. */
9794         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9795         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9796
9797         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9798         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9799
9800         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9801         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9802
9803         /* Reset the timesync increment value. */
9804         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9805         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9806
9807         return 0;
9808 }
9809
9810 static int
9811 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9812                                 struct timespec *timestamp, uint32_t flags)
9813 {
9814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9815         struct i40e_adapter *adapter =
9816                 (struct i40e_adapter *)dev->data->dev_private;
9817
9818         uint32_t sync_status;
9819         uint32_t index = flags & 0x03;
9820         uint64_t rx_tstamp_cycles;
9821         uint64_t ns;
9822
9823         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9824         if ((sync_status & (1 << index)) == 0)
9825                 return -EINVAL;
9826
9827         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9828         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9829         *timestamp = rte_ns_to_timespec(ns);
9830
9831         return 0;
9832 }
9833
9834 static int
9835 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9836                                 struct timespec *timestamp)
9837 {
9838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9839         struct i40e_adapter *adapter =
9840                 (struct i40e_adapter *)dev->data->dev_private;
9841
9842         uint32_t sync_status;
9843         uint64_t tx_tstamp_cycles;
9844         uint64_t ns;
9845
9846         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9847         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9848                 return -EINVAL;
9849
9850         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9851         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9852         *timestamp = rte_ns_to_timespec(ns);
9853
9854         return 0;
9855 }
9856
9857 /*
9858  * i40e_parse_dcb_configure - parse dcb configure from user
9859  * @dev: the device being configured
9860  * @dcb_cfg: pointer of the result of parse
9861  * @*tc_map: bit map of enabled traffic classes
9862  *
9863  * Returns 0 on success, negative value on failure
9864  */
9865 static int
9866 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9867                          struct i40e_dcbx_config *dcb_cfg,
9868                          uint8_t *tc_map)
9869 {
9870         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9871         uint8_t i, tc_bw, bw_lf;
9872
9873         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9874
9875         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9876         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9877                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9878                 return -EINVAL;
9879         }
9880
9881         /* assume each tc has the same bw */
9882         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9883         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9884                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9885         /* to ensure the sum of tcbw is equal to 100 */
9886         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9887         for (i = 0; i < bw_lf; i++)
9888                 dcb_cfg->etscfg.tcbwtable[i]++;
9889
9890         /* assume each tc has the same Transmission Selection Algorithm */
9891         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9892                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9893
9894         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9895                 dcb_cfg->etscfg.prioritytable[i] =
9896                                 dcb_rx_conf->dcb_tc[i];
9897
9898         /* FW needs one App to configure HW */
9899         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9900         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9901         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9902         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9903
9904         if (dcb_rx_conf->nb_tcs == 0)
9905                 *tc_map = 1; /* tc0 only */
9906         else
9907                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9908
9909         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9910                 dcb_cfg->pfc.willing = 0;
9911                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9912                 dcb_cfg->pfc.pfcenable = *tc_map;
9913         }
9914         return 0;
9915 }
9916
9917
9918 static enum i40e_status_code
9919 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9920                               struct i40e_aqc_vsi_properties_data *info,
9921                               uint8_t enabled_tcmap)
9922 {
9923         enum i40e_status_code ret;
9924         int i, total_tc = 0;
9925         uint16_t qpnum_per_tc, bsf, qp_idx;
9926         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9927         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9928         uint16_t used_queues;
9929
9930         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9931         if (ret != I40E_SUCCESS)
9932                 return ret;
9933
9934         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9935                 if (enabled_tcmap & (1 << i))
9936                         total_tc++;
9937         }
9938         if (total_tc == 0)
9939                 total_tc = 1;
9940         vsi->enabled_tc = enabled_tcmap;
9941
9942         /* different VSI has different queues assigned */
9943         if (vsi->type == I40E_VSI_MAIN)
9944                 used_queues = dev_data->nb_rx_queues -
9945                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9946         else if (vsi->type == I40E_VSI_VMDQ2)
9947                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9948         else {
9949                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9950                 return I40E_ERR_NO_AVAILABLE_VSI;
9951         }
9952
9953         qpnum_per_tc = used_queues / total_tc;
9954         /* Number of queues per enabled TC */
9955         if (qpnum_per_tc == 0) {
9956                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9957                 return I40E_ERR_INVALID_QP_ID;
9958         }
9959         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9960                                 I40E_MAX_Q_PER_TC);
9961         bsf = rte_bsf32(qpnum_per_tc);
9962
9963         /**
9964          * Configure TC and queue mapping parameters, for enabled TC,
9965          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9966          * default queue will serve it.
9967          */
9968         qp_idx = 0;
9969         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9970                 if (vsi->enabled_tc & (1 << i)) {
9971                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9972                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9973                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9974                         qp_idx += qpnum_per_tc;
9975                 } else
9976                         info->tc_mapping[i] = 0;
9977         }
9978
9979         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9980         if (vsi->type == I40E_VSI_SRIOV) {
9981                 info->mapping_flags |=
9982                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9983                 for (i = 0; i < vsi->nb_qps; i++)
9984                         info->queue_mapping[i] =
9985                                 rte_cpu_to_le_16(vsi->base_queue + i);
9986         } else {
9987                 info->mapping_flags |=
9988                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9989                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9990         }
9991         info->valid_sections |=
9992                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9993
9994         return I40E_SUCCESS;
9995 }
9996
9997 /*
9998  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9999  * @veb: VEB to be configured
10000  * @tc_map: enabled TC bitmap
10001  *
10002  * Returns 0 on success, negative value on failure
10003  */
10004 static enum i40e_status_code
10005 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10006 {
10007         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10008         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10009         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10010         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10011         enum i40e_status_code ret = I40E_SUCCESS;
10012         int i;
10013         uint32_t bw_max;
10014
10015         /* Check if enabled_tc is same as existing or new TCs */
10016         if (veb->enabled_tc == tc_map)
10017                 return ret;
10018
10019         /* configure tc bandwidth */
10020         memset(&veb_bw, 0, sizeof(veb_bw));
10021         veb_bw.tc_valid_bits = tc_map;
10022         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10023         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10024                 if (tc_map & BIT_ULL(i))
10025                         veb_bw.tc_bw_share_credits[i] = 1;
10026         }
10027         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10028                                                    &veb_bw, NULL);
10029         if (ret) {
10030                 PMD_INIT_LOG(ERR,
10031                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10032                         hw->aq.asq_last_status);
10033                 return ret;
10034         }
10035
10036         memset(&ets_query, 0, sizeof(ets_query));
10037         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10038                                                    &ets_query, NULL);
10039         if (ret != I40E_SUCCESS) {
10040                 PMD_DRV_LOG(ERR,
10041                         "Failed to get switch_comp ETS configuration %u",
10042                         hw->aq.asq_last_status);
10043                 return ret;
10044         }
10045         memset(&bw_query, 0, sizeof(bw_query));
10046         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10047                                                   &bw_query, NULL);
10048         if (ret != I40E_SUCCESS) {
10049                 PMD_DRV_LOG(ERR,
10050                         "Failed to get switch_comp bandwidth configuration %u",
10051                         hw->aq.asq_last_status);
10052                 return ret;
10053         }
10054
10055         /* store and print out BW info */
10056         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10057         veb->bw_info.bw_max = ets_query.tc_bw_max;
10058         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10059         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10060         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10061                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10062                      I40E_16_BIT_WIDTH);
10063         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10064                 veb->bw_info.bw_ets_share_credits[i] =
10065                                 bw_query.tc_bw_share_credits[i];
10066                 veb->bw_info.bw_ets_credits[i] =
10067                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10068                 /* 4 bits per TC, 4th bit is reserved */
10069                 veb->bw_info.bw_ets_max[i] =
10070                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10071                                   RTE_LEN2MASK(3, uint8_t));
10072                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10073                             veb->bw_info.bw_ets_share_credits[i]);
10074                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10075                             veb->bw_info.bw_ets_credits[i]);
10076                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10077                             veb->bw_info.bw_ets_max[i]);
10078         }
10079
10080         veb->enabled_tc = tc_map;
10081
10082         return ret;
10083 }
10084
10085
10086 /*
10087  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10088  * @vsi: VSI to be configured
10089  * @tc_map: enabled TC bitmap
10090  *
10091  * Returns 0 on success, negative value on failure
10092  */
10093 static enum i40e_status_code
10094 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10095 {
10096         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10097         struct i40e_vsi_context ctxt;
10098         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10099         enum i40e_status_code ret = I40E_SUCCESS;
10100         int i;
10101
10102         /* Check if enabled_tc is same as existing or new TCs */
10103         if (vsi->enabled_tc == tc_map)
10104                 return ret;
10105
10106         /* configure tc bandwidth */
10107         memset(&bw_data, 0, sizeof(bw_data));
10108         bw_data.tc_valid_bits = tc_map;
10109         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10110         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10111                 if (tc_map & BIT_ULL(i))
10112                         bw_data.tc_bw_credits[i] = 1;
10113         }
10114         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10115         if (ret) {
10116                 PMD_INIT_LOG(ERR,
10117                         "AQ command Config VSI BW allocation per TC failed = %d",
10118                         hw->aq.asq_last_status);
10119                 goto out;
10120         }
10121         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10122                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10123
10124         /* Update Queue Pairs Mapping for currently enabled UPs */
10125         ctxt.seid = vsi->seid;
10126         ctxt.pf_num = hw->pf_id;
10127         ctxt.vf_num = 0;
10128         ctxt.uplink_seid = vsi->uplink_seid;
10129         ctxt.info = vsi->info;
10130         i40e_get_cap(hw);
10131         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10132         if (ret)
10133                 goto out;
10134
10135         /* Update the VSI after updating the VSI queue-mapping information */
10136         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10137         if (ret) {
10138                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10139                         hw->aq.asq_last_status);
10140                 goto out;
10141         }
10142         /* update the local VSI info with updated queue map */
10143         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10144                                         sizeof(vsi->info.tc_mapping));
10145         (void)rte_memcpy(&vsi->info.queue_mapping,
10146                         &ctxt.info.queue_mapping,
10147                 sizeof(vsi->info.queue_mapping));
10148         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10149         vsi->info.valid_sections = 0;
10150
10151         /* query and update current VSI BW information */
10152         ret = i40e_vsi_get_bw_config(vsi);
10153         if (ret) {
10154                 PMD_INIT_LOG(ERR,
10155                          "Failed updating vsi bw info, err %s aq_err %s",
10156                          i40e_stat_str(hw, ret),
10157                          i40e_aq_str(hw, hw->aq.asq_last_status));
10158                 goto out;
10159         }
10160
10161         vsi->enabled_tc = tc_map;
10162
10163 out:
10164         return ret;
10165 }
10166
10167 /*
10168  * i40e_dcb_hw_configure - program the dcb setting to hw
10169  * @pf: pf the configuration is taken on
10170  * @new_cfg: new configuration
10171  * @tc_map: enabled TC bitmap
10172  *
10173  * Returns 0 on success, negative value on failure
10174  */
10175 static enum i40e_status_code
10176 i40e_dcb_hw_configure(struct i40e_pf *pf,
10177                       struct i40e_dcbx_config *new_cfg,
10178                       uint8_t tc_map)
10179 {
10180         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10181         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10182         struct i40e_vsi *main_vsi = pf->main_vsi;
10183         struct i40e_vsi_list *vsi_list;
10184         enum i40e_status_code ret;
10185         int i;
10186         uint32_t val;
10187
10188         /* Use the FW API if FW > v4.4*/
10189         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10190               (hw->aq.fw_maj_ver >= 5))) {
10191                 PMD_INIT_LOG(ERR,
10192                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10193                 return I40E_ERR_FIRMWARE_API_VERSION;
10194         }
10195
10196         /* Check if need reconfiguration */
10197         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10198                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10199                 return I40E_SUCCESS;
10200         }
10201
10202         /* Copy the new config to the current config */
10203         *old_cfg = *new_cfg;
10204         old_cfg->etsrec = old_cfg->etscfg;
10205         ret = i40e_set_dcb_config(hw);
10206         if (ret) {
10207                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10208                          i40e_stat_str(hw, ret),
10209                          i40e_aq_str(hw, hw->aq.asq_last_status));
10210                 return ret;
10211         }
10212         /* set receive Arbiter to RR mode and ETS scheme by default */
10213         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10214                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10215                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10216                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10217                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10218                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10219                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10220                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10221                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10222                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10223                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10224                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10225                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10226         }
10227         /* get local mib to check whether it is configured correctly */
10228         /* IEEE mode */
10229         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10230         /* Get Local DCB Config */
10231         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10232                                      &hw->local_dcbx_config);
10233
10234         /* if Veb is created, need to update TC of it at first */
10235         if (main_vsi->veb) {
10236                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10237                 if (ret)
10238                         PMD_INIT_LOG(WARNING,
10239                                  "Failed configuring TC for VEB seid=%d",
10240                                  main_vsi->veb->seid);
10241         }
10242         /* Update each VSI */
10243         i40e_vsi_config_tc(main_vsi, tc_map);
10244         if (main_vsi->veb) {
10245                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10246                         /* Beside main VSI and VMDQ VSIs, only enable default
10247                          * TC for other VSIs
10248                          */
10249                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10250                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10251                                                          tc_map);
10252                         else
10253                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10254                                                          I40E_DEFAULT_TCMAP);
10255                         if (ret)
10256                                 PMD_INIT_LOG(WARNING,
10257                                         "Failed configuring TC for VSI seid=%d",
10258                                         vsi_list->vsi->seid);
10259                         /* continue */
10260                 }
10261         }
10262         return I40E_SUCCESS;
10263 }
10264
10265 /*
10266  * i40e_dcb_init_configure - initial dcb config
10267  * @dev: device being configured
10268  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10269  *
10270  * Returns 0 on success, negative value on failure
10271  */
10272 static int
10273 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10274 {
10275         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10277         int i, ret = 0;
10278
10279         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10280                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10281                 return -ENOTSUP;
10282         }
10283
10284         /* DCB initialization:
10285          * Update DCB configuration from the Firmware and configure
10286          * LLDP MIB change event.
10287          */
10288         if (sw_dcb == TRUE) {
10289                 ret = i40e_init_dcb(hw);
10290                 /* If lldp agent is stopped, the return value from
10291                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10292                  * adminq status. Otherwise, it should return success.
10293                  */
10294                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10295                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10296                         memset(&hw->local_dcbx_config, 0,
10297                                 sizeof(struct i40e_dcbx_config));
10298                         /* set dcb default configuration */
10299                         hw->local_dcbx_config.etscfg.willing = 0;
10300                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10301                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10302                         hw->local_dcbx_config.etscfg.tsatable[0] =
10303                                                 I40E_IEEE_TSA_ETS;
10304                         /* all UPs mapping to TC0 */
10305                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10306                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10307                         hw->local_dcbx_config.etsrec =
10308                                 hw->local_dcbx_config.etscfg;
10309                         hw->local_dcbx_config.pfc.willing = 0;
10310                         hw->local_dcbx_config.pfc.pfccap =
10311                                                 I40E_MAX_TRAFFIC_CLASS;
10312                         /* FW needs one App to configure HW */
10313                         hw->local_dcbx_config.numapps = 1;
10314                         hw->local_dcbx_config.app[0].selector =
10315                                                 I40E_APP_SEL_ETHTYPE;
10316                         hw->local_dcbx_config.app[0].priority = 3;
10317                         hw->local_dcbx_config.app[0].protocolid =
10318                                                 I40E_APP_PROTOID_FCOE;
10319                         ret = i40e_set_dcb_config(hw);
10320                         if (ret) {
10321                                 PMD_INIT_LOG(ERR,
10322                                         "default dcb config fails. err = %d, aq_err = %d.",
10323                                         ret, hw->aq.asq_last_status);
10324                                 return -ENOSYS;
10325                         }
10326                 } else {
10327                         PMD_INIT_LOG(ERR,
10328                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10329                                 ret, hw->aq.asq_last_status);
10330                         return -ENOTSUP;
10331                 }
10332         } else {
10333                 ret = i40e_aq_start_lldp(hw, NULL);
10334                 if (ret != I40E_SUCCESS)
10335                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10336
10337                 ret = i40e_init_dcb(hw);
10338                 if (!ret) {
10339                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10340                                 PMD_INIT_LOG(ERR,
10341                                         "HW doesn't support DCBX offload.");
10342                                 return -ENOTSUP;
10343                         }
10344                 } else {
10345                         PMD_INIT_LOG(ERR,
10346                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10347                                 ret, hw->aq.asq_last_status);
10348                         return -ENOTSUP;
10349                 }
10350         }
10351         return 0;
10352 }
10353
10354 /*
10355  * i40e_dcb_setup - setup dcb related config
10356  * @dev: device being configured
10357  *
10358  * Returns 0 on success, negative value on failure
10359  */
10360 static int
10361 i40e_dcb_setup(struct rte_eth_dev *dev)
10362 {
10363         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10364         struct i40e_dcbx_config dcb_cfg;
10365         uint8_t tc_map = 0;
10366         int ret = 0;
10367
10368         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10369                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10370                 return -ENOTSUP;
10371         }
10372
10373         if (pf->vf_num != 0)
10374                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10375
10376         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10377         if (ret) {
10378                 PMD_INIT_LOG(ERR, "invalid dcb config");
10379                 return -EINVAL;
10380         }
10381         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10382         if (ret) {
10383                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10384                 return -ENOSYS;
10385         }
10386
10387         return 0;
10388 }
10389
10390 static int
10391 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10392                       struct rte_eth_dcb_info *dcb_info)
10393 {
10394         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10396         struct i40e_vsi *vsi = pf->main_vsi;
10397         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10398         uint16_t bsf, tc_mapping;
10399         int i, j = 0;
10400
10401         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10402                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10403         else
10404                 dcb_info->nb_tcs = 1;
10405         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10406                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10407         for (i = 0; i < dcb_info->nb_tcs; i++)
10408                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10409
10410         /* get queue mapping if vmdq is disabled */
10411         if (!pf->nb_cfg_vmdq_vsi) {
10412                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10413                         if (!(vsi->enabled_tc & (1 << i)))
10414                                 continue;
10415                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10416                         dcb_info->tc_queue.tc_rxq[j][i].base =
10417                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10418                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10419                         dcb_info->tc_queue.tc_txq[j][i].base =
10420                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10421                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10422                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10423                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10424                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10425                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10426                 }
10427                 return 0;
10428         }
10429
10430         /* get queue mapping if vmdq is enabled */
10431         do {
10432                 vsi = pf->vmdq[j].vsi;
10433                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10434                         if (!(vsi->enabled_tc & (1 << i)))
10435                                 continue;
10436                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10437                         dcb_info->tc_queue.tc_rxq[j][i].base =
10438                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10439                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10440                         dcb_info->tc_queue.tc_txq[j][i].base =
10441                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10442                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10443                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10444                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10445                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10446                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10447                 }
10448                 j++;
10449         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10450         return 0;
10451 }
10452
10453 static int
10454 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10455 {
10456         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10457         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10458         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10459         uint16_t interval =
10460                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10461         uint16_t msix_intr;
10462
10463         msix_intr = intr_handle->intr_vec[queue_id];
10464         if (msix_intr == I40E_MISC_VEC_ID)
10465                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10466                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10467                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10468                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10469                                (interval <<
10470                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10471         else
10472                 I40E_WRITE_REG(hw,
10473                                I40E_PFINT_DYN_CTLN(msix_intr -
10474                                                    I40E_RX_VEC_START),
10475                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10476                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10477                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10478                                (interval <<
10479                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10480
10481         I40E_WRITE_FLUSH(hw);
10482         rte_intr_enable(&pci_dev->intr_handle);
10483
10484         return 0;
10485 }
10486
10487 static int
10488 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10489 {
10490         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10491         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10492         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10493         uint16_t msix_intr;
10494
10495         msix_intr = intr_handle->intr_vec[queue_id];
10496         if (msix_intr == I40E_MISC_VEC_ID)
10497                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10498         else
10499                 I40E_WRITE_REG(hw,
10500                                I40E_PFINT_DYN_CTLN(msix_intr -
10501                                                    I40E_RX_VEC_START),
10502                                0);
10503         I40E_WRITE_FLUSH(hw);
10504
10505         return 0;
10506 }
10507
10508 static int i40e_get_regs(struct rte_eth_dev *dev,
10509                          struct rte_dev_reg_info *regs)
10510 {
10511         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10512         uint32_t *ptr_data = regs->data;
10513         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10514         const struct i40e_reg_info *reg_info;
10515
10516         if (ptr_data == NULL) {
10517                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10518                 regs->width = sizeof(uint32_t);
10519                 return 0;
10520         }
10521
10522         /* The first few registers have to be read using AQ operations */
10523         reg_idx = 0;
10524         while (i40e_regs_adminq[reg_idx].name) {
10525                 reg_info = &i40e_regs_adminq[reg_idx++];
10526                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10527                         for (arr_idx2 = 0;
10528                                         arr_idx2 <= reg_info->count2;
10529                                         arr_idx2++) {
10530                                 reg_offset = arr_idx * reg_info->stride1 +
10531                                         arr_idx2 * reg_info->stride2;
10532                                 reg_offset += reg_info->base_addr;
10533                                 ptr_data[reg_offset >> 2] =
10534                                         i40e_read_rx_ctl(hw, reg_offset);
10535                         }
10536         }
10537
10538         /* The remaining registers can be read using primitives */
10539         reg_idx = 0;
10540         while (i40e_regs_others[reg_idx].name) {
10541                 reg_info = &i40e_regs_others[reg_idx++];
10542                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10543                         for (arr_idx2 = 0;
10544                                         arr_idx2 <= reg_info->count2;
10545                                         arr_idx2++) {
10546                                 reg_offset = arr_idx * reg_info->stride1 +
10547                                         arr_idx2 * reg_info->stride2;
10548                                 reg_offset += reg_info->base_addr;
10549                                 ptr_data[reg_offset >> 2] =
10550                                         I40E_READ_REG(hw, reg_offset);
10551                         }
10552         }
10553
10554         return 0;
10555 }
10556
10557 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10558 {
10559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10560
10561         /* Convert word count to byte count */
10562         return hw->nvm.sr_size << 1;
10563 }
10564
10565 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10566                            struct rte_dev_eeprom_info *eeprom)
10567 {
10568         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10569         uint16_t *data = eeprom->data;
10570         uint16_t offset, length, cnt_words;
10571         int ret_code;
10572
10573         offset = eeprom->offset >> 1;
10574         length = eeprom->length >> 1;
10575         cnt_words = length;
10576
10577         if (offset > hw->nvm.sr_size ||
10578                 offset + length > hw->nvm.sr_size) {
10579                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10580                 return -EINVAL;
10581         }
10582
10583         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10584
10585         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10586         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10587                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10588                 return -EIO;
10589         }
10590
10591         return 0;
10592 }
10593
10594 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10595                                       struct ether_addr *mac_addr)
10596 {
10597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10598
10599         if (!is_valid_assigned_ether_addr(mac_addr)) {
10600                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10601                 return;
10602         }
10603
10604         /* Flags: 0x3 updates port address */
10605         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10606 }
10607
10608 static int
10609 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10610 {
10611         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10612         struct rte_eth_dev_data *dev_data = pf->dev_data;
10613         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10614         int ret = 0;
10615
10616         /* check if mtu is within the allowed range */
10617         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10618                 return -EINVAL;
10619
10620         /* mtu setting is forbidden if port is start */
10621         if (dev_data->dev_started) {
10622                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10623                             dev_data->port_id);
10624                 return -EBUSY;
10625         }
10626
10627         if (frame_size > ETHER_MAX_LEN)
10628                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10629         else
10630                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10631
10632         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10633
10634         return ret;
10635 }
10636
10637 /* Restore ethertype filter */
10638 static void
10639 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10640 {
10641         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10642         struct i40e_ethertype_filter_list
10643                 *ethertype_list = &pf->ethertype.ethertype_list;
10644         struct i40e_ethertype_filter *f;
10645         struct i40e_control_filter_stats stats;
10646         uint16_t flags;
10647
10648         TAILQ_FOREACH(f, ethertype_list, rules) {
10649                 flags = 0;
10650                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10651                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10652                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10653                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10654                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10655
10656                 memset(&stats, 0, sizeof(stats));
10657                 i40e_aq_add_rem_control_packet_filter(hw,
10658                                             f->input.mac_addr.addr_bytes,
10659                                             f->input.ether_type,
10660                                             flags, pf->main_vsi->seid,
10661                                             f->queue, 1, &stats, NULL);
10662         }
10663         PMD_DRV_LOG(INFO, "Ethertype filter:"
10664                     " mac_etype_used = %u, etype_used = %u,"
10665                     " mac_etype_free = %u, etype_free = %u",
10666                     stats.mac_etype_used, stats.etype_used,
10667                     stats.mac_etype_free, stats.etype_free);
10668 }
10669
10670 /* Restore tunnel filter */
10671 static void
10672 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10673 {
10674         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10675         struct i40e_vsi *vsi;
10676         struct i40e_pf_vf *vf;
10677         struct i40e_tunnel_filter_list
10678                 *tunnel_list = &pf->tunnel.tunnel_list;
10679         struct i40e_tunnel_filter *f;
10680         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10681         bool big_buffer = 0;
10682
10683         TAILQ_FOREACH(f, tunnel_list, rules) {
10684                 if (!f->is_to_vf)
10685                         vsi = pf->main_vsi;
10686                 else {
10687                         vf = &pf->vfs[f->vf_id];
10688                         vsi = vf->vsi;
10689                 }
10690                 memset(&cld_filter, 0, sizeof(cld_filter));
10691                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10692                         (struct ether_addr *)&cld_filter.element.outer_mac);
10693                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10694                         (struct ether_addr *)&cld_filter.element.inner_mac);
10695                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10696                 cld_filter.element.flags = f->input.flags;
10697                 cld_filter.element.tenant_id = f->input.tenant_id;
10698                 cld_filter.element.queue_number = f->queue;
10699                 rte_memcpy(cld_filter.general_fields,
10700                            f->input.general_fields,
10701                            sizeof(f->input.general_fields));
10702
10703                 if (((f->input.flags &
10704                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10705                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10706                     ((f->input.flags &
10707                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10708                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10709                     ((f->input.flags &
10710                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10711                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10712                         big_buffer = 1;
10713
10714                 if (big_buffer)
10715                         i40e_aq_add_cloud_filters_big_buffer(hw,
10716                                              vsi->seid, &cld_filter, 1);
10717                 else
10718                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10719                                                   &cld_filter.element, 1);
10720         }
10721 }
10722
10723 static void
10724 i40e_filter_restore(struct i40e_pf *pf)
10725 {
10726         i40e_ethertype_filter_restore(pf);
10727         i40e_tunnel_filter_restore(pf);
10728         i40e_fdir_filter_restore(pf);
10729 }
10730
10731 static bool
10732 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10733 {
10734         if (strcmp(dev->data->drv_name,
10735                    drv->driver.name))
10736                 return false;
10737
10738         return true;
10739 }
10740
10741 bool
10742 is_i40e_supported(struct rte_eth_dev *dev)
10743 {
10744         return is_device_supported(dev, &rte_i40e_pmd);
10745 }
10746
10747 /* Create a QinQ cloud filter
10748  *
10749  * The Fortville NIC has limited resources for tunnel filters,
10750  * so we can only reuse existing filters.
10751  *
10752  * In step 1 we define which Field Vector fields can be used for
10753  * filter types.
10754  * As we do not have the inner tag defined as a field,
10755  * we have to define it first, by reusing one of L1 entries.
10756  *
10757  * In step 2 we are replacing one of existing filter types with
10758  * a new one for QinQ.
10759  * As we reusing L1 and replacing L2, some of the default filter
10760  * types will disappear,which depends on L1 and L2 entries we reuse.
10761  *
10762  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10763  *
10764  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10765  *              later when we define the cloud filter.
10766  *      a.      Valid_flags.replace_cloud = 0
10767  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10768  *      c.      New_filter = 0x10
10769  *      d.      TR bit = 0xff (optional, not used here)
10770  *      e.      Buffer – 2 entries:
10771  *              i.      Byte 0 = 8 (outer vlan FV index).
10772  *                      Byte 1 = 0 (rsv)
10773  *                      Byte 2-3 = 0x0fff
10774  *              ii.     Byte 0 = 37 (inner vlan FV index).
10775  *                      Byte 1 =0 (rsv)
10776  *                      Byte 2-3 = 0x0fff
10777  *
10778  * Step 2:
10779  * 2.   Create cloud filter using two L1 filters entries: stag and
10780  *              new filter(outer vlan+ inner vlan)
10781  *      a.      Valid_flags.replace_cloud = 1
10782  *      b.      Old_filter = 1 (instead of outer IP)
10783  *      c.      New_filter = 0x10
10784  *      d.      Buffer – 2 entries:
10785  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10786  *                      Byte 1-3 = 0 (rsv)
10787  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10788  *                      Byte 9-11 = 0 (rsv)
10789  */
10790 static int
10791 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10792 {
10793         int ret = -ENOTSUP;
10794         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10795         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10796         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10797
10798         /* Init */
10799         memset(&filter_replace, 0,
10800                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10801         memset(&filter_replace_buf, 0,
10802                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10803
10804         /* create L1 filter */
10805         filter_replace.old_filter_type =
10806                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10807         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10808         filter_replace.tr_bit = 0;
10809
10810         /* Prepare the buffer, 2 entries */
10811         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10812         filter_replace_buf.data[0] |=
10813                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10814         /* Field Vector 12b mask */
10815         filter_replace_buf.data[2] = 0xff;
10816         filter_replace_buf.data[3] = 0x0f;
10817         filter_replace_buf.data[4] =
10818                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10819         filter_replace_buf.data[4] |=
10820                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10821         /* Field Vector 12b mask */
10822         filter_replace_buf.data[6] = 0xff;
10823         filter_replace_buf.data[7] = 0x0f;
10824         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10825                         &filter_replace_buf);
10826         if (ret != I40E_SUCCESS)
10827                 return ret;
10828
10829         /* Apply the second L2 cloud filter */
10830         memset(&filter_replace, 0,
10831                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10832         memset(&filter_replace_buf, 0,
10833                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10834
10835         /* create L2 filter, input for L2 filter will be L1 filter  */
10836         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10837         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10838         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10839
10840         /* Prepare the buffer, 2 entries */
10841         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10842         filter_replace_buf.data[0] |=
10843                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10844         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10845         filter_replace_buf.data[4] |=
10846                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10847         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10848                         &filter_replace_buf);
10849         return ret;
10850 }
10851
10852 RTE_INIT(i40e_init_log);
10853 static void
10854 i40e_init_log(void)
10855 {
10856         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10857         if (i40e_logtype_init >= 0)
10858                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10859         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10860         if (i40e_logtype_driver >= 0)
10861                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10862 }