drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 /* Additional timesync values. */
 129 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 130 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 131 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 132 #define I40E_PRTTSYN_TSYNENA     0x80000000
 133 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 134 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 135
 136 #define I40E_MAX_PERCENT            100
 137 #define I40E_DEFAULT_DCB_APP_NUM    1
 138 #define I40E_DEFAULT_DCB_APP_PRIO   3
 139
 140 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 141 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 143 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 144 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 145 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 146
 147 #define I40E_INSET_NONE            0x00000000000000000ULL
 148
 149 /* bit0 ~ bit 7 */
 150 #define I40E_INSET_DMAC            0x0000000000000001ULL
 151 #define I40E_INSET_SMAC            0x0000000000000002ULL
 152 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 153 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 154 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 155
 156 /* bit 8 ~ bit 15 */
 157 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 158 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 159 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 160 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 161 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 162 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 163 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 164
 165 /* bit 16 ~ bit 31 */
 166 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 167 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 168 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 169 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 170 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 171 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 172 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 173 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 174
 175 /* bit 32 ~ bit 47, tunnel fields */
 176 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 177 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 178 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 179 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 180 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 181 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 182
 183 /* bit 48 ~ bit 55 */
 184 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 185
 186 /* bit 56 ~ bit 63, Flex Payload */
 187 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 194 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 195 #define I40E_INSET_FLEX_PAYLOAD \
 196         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 197         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 198         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 199         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 200
 201 /**
 202  * Below are values for writing un-exposed registers suggested
 203  * by silicon experts
 204  */
 205 /* Destination MAC address */
 206 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 207 /* Source MAC address */
 208 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 209 /* VLAN tag in the outer L2 header */
 210 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0080000000000000ULL
 211 /* VLAN tag in the inner L2 header */
 212 #define I40E_REG_INSET_L2_INNER_VLAN             0x0100000000000000ULL
 213 /* Source IPv4 address */
 214 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 215 /* Destination IPv4 address */
 216 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 217 /* IPv4 Type of Service (TOS) */
 218 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 219 /* IPv4 Protocol */
 220 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 221 /* Source IPv6 address */
 222 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 223 /* Destination IPv6 address */
 224 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 225 /* IPv6 Traffic Class (TC) */
 226 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 227 /* IPv6 Next Header */
 228 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 229 /* Source L4 port */
 230 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 231 /* Destination L4 port */
 232 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 233 /* SCTP verification tag */
 234 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 235 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 236 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 237 /* Source port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 239 /* Destination port of tunneling UDP */
 240 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 241 /* UDP Tunneling ID, NVGRE/GRE key */
 242 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 243 /* Last ether type */
 244 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 245 /* Tunneling outer destination IPv4 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 247 /* Tunneling outer destination IPv6 address */
 248 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 249 /* 1st word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 251 /* 2nd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 253 /* 3rd word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 255 /* 4th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 257 /* 5th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 259 /* 6th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 261 /* 7th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 263 /* 8th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 265
 266 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 267
 268 #define I40E_TRANSLATE_INSET 0
 269 #define I40E_TRANSLATE_REG   1
 270
 271 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 272 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 274 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 275
 276 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 277 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 279         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 280
 281 /* PCI offset for querying capability */
 282 #define PCI_DEV_CAP_REG            0xA4
 283 /* PCI offset for enabling/disabling Extended Tag */
 284 #define PCI_DEV_CTRL_REG           0xA8
 285 /* Bit mask of Extended Tag capability */
 286 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 287 /* Bit shift of Extended Tag enable/disable */
 288 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 289 /* Bit mask of Extended Tag enable/disable */
 290 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 291
 292 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 293 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 294 static int i40e_dev_configure(struct rte_eth_dev *dev);
 295 static int i40e_dev_start(struct rte_eth_dev *dev);
 296 static void i40e_dev_stop(struct rte_eth_dev *dev);
 297 static void i40e_dev_close(struct rte_eth_dev *dev);
 298 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 299 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 300 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 301 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 302 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 303 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 304 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 305                                struct rte_eth_stats *stats);
 306 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 307                                struct rte_eth_xstats *xstats, unsigned n);
 308 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 309 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 310                                             uint16_t queue_id,
 311                                             uint8_t stat_idx,
 312                                             uint8_t is_rx);
 313 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 314                               struct rte_eth_dev_info *dev_info);
 315 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 316                                 uint16_t vlan_id,
 317                                 int on);
 318 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 319                               enum rte_vlan_type vlan_type,
 320                               uint16_t tpid);
 321 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 322 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 323                                       uint16_t queue,
 324                                       int on);
 325 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 326 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 327 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 328 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 329                               struct rte_eth_fc_conf *fc_conf);
 330 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 331                               struct rte_eth_fc_conf *fc_conf);
 332 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 333                                        struct rte_eth_pfc_conf *pfc_conf);
 334 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 335                           struct ether_addr *mac_addr,
 336                           uint32_t index,
 337                           uint32_t pool);
 338 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 339 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 340                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 341                                     uint16_t reta_size);
 342 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 343                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 344                                    uint16_t reta_size);
 345
 346 static int i40e_get_cap(struct i40e_hw *hw);
 347 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 348 static int i40e_pf_setup(struct i40e_pf *pf);
 349 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 350 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 351 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 352 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 353 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 354                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 355 static void i40e_stat_update_48(struct i40e_hw *hw,
 356                                uint32_t hireg,
 357                                uint32_t loreg,
 358                                bool offset_loaded,
 359                                uint64_t *offset,
 360                                uint64_t *stat);
 361 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 362 static void i40e_dev_interrupt_handler(
 363                 __rte_unused struct rte_intr_handle *handle, void *param);
 364 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 365                                 uint32_t base, uint32_t num);
 366 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 367 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 368                         uint32_t base);
 369 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 370                         uint16_t num);
 371 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 372 static int i40e_veb_release(struct i40e_veb *veb);
 373 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 374                                                 struct i40e_vsi *vsi);
 375 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 376 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 377 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 378                                              struct i40e_macvlan_filter *mv_f,
 379                                              int num,
 380                                              struct ether_addr *addr);
 381 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 382                                              struct i40e_macvlan_filter *mv_f,
 383                                              int num,
 384                                              uint16_t vlan);
 385 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 386 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 387                                     struct rte_eth_rss_conf *rss_conf);
 388 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 389                                       struct rte_eth_rss_conf *rss_conf);
 390 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 391                                 struct rte_eth_udp_tunnel *udp_tunnel);
 392 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 393                                 struct rte_eth_udp_tunnel *udp_tunnel);
 394 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 395                         struct rte_eth_ethertype_filter *filter,
 396                         bool add);
 397 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 398                                 enum rte_filter_op filter_op,
 399                                 void *arg);
 400 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 401                                 enum rte_filter_type filter_type,
 402                                 enum rte_filter_op filter_op,
 403                                 void *arg);
 404 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 405                                   struct rte_eth_dcb_info *dcb_info);
 406 static void i40e_configure_registers(struct i40e_hw *hw);
 407 static void i40e_hw_init(struct rte_eth_dev *dev);
 408 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 409 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 410                         struct rte_eth_mirror_conf *mirror_conf,
 411                         uint8_t sw_id, uint8_t on);
 412 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 413
 414 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 415 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 416 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 417                                            struct timespec *timestamp,
 418                                            uint32_t flags);
 419 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 420                                            struct timespec *timestamp);
 421 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 422
 423 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 424
 425 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 426                                    struct timespec *timestamp);
 427 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 428                                     const struct timespec *timestamp);
 429
 430 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 431                                          uint16_t queue_id);
 432 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 433                                           uint16_t queue_id);
 434
 435
 436 static const struct rte_pci_id pci_id_i40e_map[] = {
 437 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 438 #include "rte_pci_dev_ids.h"
 439 { .vendor_id = 0, /* sentinel */ },
 440 };
 441
 442 static const struct eth_dev_ops i40e_eth_dev_ops = {
 443         .dev_configure                = i40e_dev_configure,
 444         .dev_start                    = i40e_dev_start,
 445         .dev_stop                     = i40e_dev_stop,
 446         .dev_close                    = i40e_dev_close,
 447         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 448         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 449         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 450         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 451         .dev_set_link_up              = i40e_dev_set_link_up,
 452         .dev_set_link_down            = i40e_dev_set_link_down,
 453         .link_update                  = i40e_dev_link_update,
 454         .stats_get                    = i40e_dev_stats_get,
 455         .xstats_get                   = i40e_dev_xstats_get,
 456         .stats_reset                  = i40e_dev_stats_reset,
 457         .xstats_reset                 = i40e_dev_stats_reset,
 458         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 459         .dev_infos_get                = i40e_dev_info_get,
 460         .vlan_filter_set              = i40e_vlan_filter_set,
 461         .vlan_tpid_set                = i40e_vlan_tpid_set,
 462         .vlan_offload_set             = i40e_vlan_offload_set,
 463         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 464         .vlan_pvid_set                = i40e_vlan_pvid_set,
 465         .rx_queue_start               = i40e_dev_rx_queue_start,
 466         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 467         .tx_queue_start               = i40e_dev_tx_queue_start,
 468         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 469         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 470         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 471         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 472         .rx_queue_release             = i40e_dev_rx_queue_release,
 473         .rx_queue_count               = i40e_dev_rx_queue_count,
 474         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 475         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 476         .tx_queue_release             = i40e_dev_tx_queue_release,
 477         .dev_led_on                   = i40e_dev_led_on,
 478         .dev_led_off                  = i40e_dev_led_off,
 479         .flow_ctrl_get                = i40e_flow_ctrl_get,
 480         .flow_ctrl_set                = i40e_flow_ctrl_set,
 481         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 482         .mac_addr_add                 = i40e_macaddr_add,
 483         .mac_addr_remove              = i40e_macaddr_remove,
 484         .reta_update                  = i40e_dev_rss_reta_update,
 485         .reta_query                   = i40e_dev_rss_reta_query,
 486         .rss_hash_update              = i40e_dev_rss_hash_update,
 487         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 488         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 489         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 490         .filter_ctrl                  = i40e_dev_filter_ctrl,
 491         .rxq_info_get                 = i40e_rxq_info_get,
 492         .txq_info_get                 = i40e_txq_info_get,
 493         .mirror_rule_set              = i40e_mirror_rule_set,
 494         .mirror_rule_reset            = i40e_mirror_rule_reset,
 495         .timesync_enable              = i40e_timesync_enable,
 496         .timesync_disable             = i40e_timesync_disable,
 497         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 498         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 499         .get_dcb_info                 = i40e_dev_get_dcb_info,
 500         .timesync_adjust_time         = i40e_timesync_adjust_time,
 501         .timesync_read_time           = i40e_timesync_read_time,
 502         .timesync_write_time          = i40e_timesync_write_time,
 503 };
 504
 505 /* store statistics names and its offset in stats structure */
 506 struct rte_i40e_xstats_name_off {
 507         char name[RTE_ETH_XSTATS_NAME_SIZE];
 508         unsigned offset;
 509 };
 510
 511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 512         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 513         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 514         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 515         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 516         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 517                 rx_unknown_protocol)},
 518         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 519         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 520         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 521         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 522 };
 523
 524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 525                 sizeof(rte_i40e_stats_strings[0]))
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 528         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 529                 tx_dropped_link_down)},
 530         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 531         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 532                 illegal_bytes)},
 533         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 534         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 535                 mac_local_faults)},
 536         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 537                 mac_remote_faults)},
 538         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 539                 rx_length_errors)},
 540         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 541         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 542         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 543         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 544         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 545         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_127)},
 547         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 550                 rx_size_511)},
 551         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 552                 rx_size_1023)},
 553         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 554                 rx_size_1522)},
 555         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_big)},
 557         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 558                 rx_undersize)},
 559         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 560                 rx_oversize)},
 561         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 562                 mac_short_packet_dropped)},
 563         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_fragments)},
 565         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 566         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_127)},
 569         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_255)},
 571         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 tx_size_511)},
 573         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 tx_size_1023)},
 575         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 tx_size_1522)},
 577         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_big)},
 579         {"rx_flow_director_atr_match_packets",
 580                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 581         {"rx_flow_director_sb_match_packets",
 582                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 583         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 584                 tx_lpi_status)},
 585         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 586                 rx_lpi_status)},
 587         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 588                 tx_lpi_count)},
 589         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 590                 rx_lpi_count)},
 591 };
 592
 593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 594                 sizeof(rte_i40e_hw_port_strings[0]))
 595
 596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 597         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 598                 priority_xon_rx)},
 599         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xoff_rx)},
 601 };
 602
 603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 604                 sizeof(rte_i40e_rxq_prio_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_tx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_tx)},
 611         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_2_xoff)},
 613 };
 614
 615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 616                 sizeof(rte_i40e_txq_prio_strings[0]))
 617
 618 static struct eth_driver rte_i40e_pmd = {
 619         .pci_drv = {
 620                 .name = "rte_i40e_pmd",
 621                 .id_table = pci_id_i40e_map,
 622                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 623                         RTE_PCI_DRV_DETACHABLE,
 624         },
 625         .eth_dev_init = eth_i40e_dev_init,
 626         .eth_dev_uninit = eth_i40e_dev_uninit,
 627         .dev_private_size = sizeof(struct i40e_adapter),
 628 };
 629
 630 static inline int
 631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 632                                      struct rte_eth_link *link)
 633 {
 634         struct rte_eth_link *dst = link;
 635         struct rte_eth_link *src = &(dev->data->dev_link);
 636
 637         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 638                                         *(uint64_t *)src) == 0)
 639                 return -1;
 640
 641         return 0;
 642 }
 643
 644 static inline int
 645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 646                                       struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = &(dev->data->dev_link);
 649         struct rte_eth_link *src = link;
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 /*
 659  * Driver initialization routine.
 660  * Invoked once at EAL init time.
 661  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 662  */
 663 static int
 664 rte_i40e_pmd_init(const char *name __rte_unused,
 665                   const char *params __rte_unused)
 666 {
 667         PMD_INIT_FUNC_TRACE();
 668         rte_eth_driver_register(&rte_i40e_pmd);
 669
 670         return 0;
 671 }
 672
 673 static struct rte_driver rte_i40e_driver = {
 674         .type = PMD_PDEV,
 675         .init = rte_i40e_pmd_init,
 676 };
 677
 678 PMD_REGISTER_DRIVER(rte_i40e_driver);
 679
 680 /*
 681  * Initialize registers for flexible payload, which should be set by NVM.
 682  * This should be removed from code once it is fixed in NVM.
 683  */
 684 #ifndef I40E_GLQF_ORT
 685 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 686 #endif
 687 #ifndef I40E_GLQF_PIT
 688 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 689 #endif
 690
 691 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 692 {
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 697         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 698         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 699         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 700         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 703
 704         /* GLQF_PIT Registers */
 705         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 706         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 707 }
 708
 709 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 710
 711 /*
 712  * Add a ethertype filter to drop all flow control frames transmitted
 713  * from VSIs.
 714 */
 715 static void
 716 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 717 {
 718         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 719         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 720                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 721                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 722         int ret;
 723
 724         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 725                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 726                                 pf->main_vsi_seid, 0,
 727                                 TRUE, NULL, NULL);
 728         if (ret)
 729                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 730                                   " frames from VSIs.");
 731 }
 732
 733 static int
 734 eth_i40e_dev_init(struct rte_eth_dev *dev)
 735 {
 736         struct rte_pci_device *pci_dev;
 737         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 739         struct i40e_vsi *vsi;
 740         int ret;
 741         uint32_t len;
 742         uint8_t aq_fail = 0;
 743
 744         PMD_INIT_FUNC_TRACE();
 745
 746         dev->dev_ops = &i40e_eth_dev_ops;
 747         dev->rx_pkt_burst = i40e_recv_pkts;
 748         dev->tx_pkt_burst = i40e_xmit_pkts;
 749
 750         /* for secondary processes, we don't initialise any further as primary
 751          * has already done this work. Only check we don't need a different
 752          * RX function */
 753         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 754                 i40e_set_rx_function(dev);
 755                 i40e_set_tx_function(dev);
 756                 return 0;
 757         }
 758         pci_dev = dev->pci_dev;
 759
 760         rte_eth_copy_pci_info(dev, pci_dev);
 761
 762         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 763         pf->adapter->eth_dev = dev;
 764         pf->dev_data = dev->data;
 765
 766         hw->back = I40E_PF_TO_ADAPTER(pf);
 767         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 768         if (!hw->hw_addr) {
 769                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 770                              "as address is NULL");
 771                 return -ENODEV;
 772         }
 773
 774         hw->vendor_id = pci_dev->id.vendor_id;
 775         hw->device_id = pci_dev->id.device_id;
 776         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 777         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 778         hw->bus.device = pci_dev->addr.devid;
 779         hw->bus.func = pci_dev->addr.function;
 780         hw->adapter_stopped = 0;
 781
 782         /* Make sure all is clean before doing PF reset */
 783         i40e_clear_hw(hw);
 784
 785         /* Initialize the hardware */
 786         i40e_hw_init(dev);
 787
 788         /* Reset here to make sure all is clean for each PF */
 789         ret = i40e_pf_reset(hw);
 790         if (ret) {
 791                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 792                 return ret;
 793         }
 794
 795         /* Initialize the shared code (base driver) */
 796         ret = i40e_init_shared_code(hw);
 797         if (ret) {
 798                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 799                 return ret;
 800         }
 801
 802         /*
 803          * To work around the NVM issue,initialize registers
 804          * for flexible payload by software.
 805          * It should be removed once issues are fixed in NVM.
 806          */
 807         i40e_flex_payload_reg_init(hw);
 808
 809         /* Initialize the parameters for adminq */
 810         i40e_init_adminq_parameter(hw);
 811         ret = i40e_init_adminq(hw);
 812         if (ret != I40E_SUCCESS) {
 813                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 814                 return -EIO;
 815         }
 816         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 817                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 818                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 819                      ((hw->nvm.version >> 12) & 0xf),
 820                      ((hw->nvm.version >> 4) & 0xff),
 821                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 822
 823         /* Clear PXE mode */
 824         i40e_clear_pxe_mode(hw);
 825
 826         /*
 827          * On X710, performance number is far from the expectation on recent
 828          * firmware versions. The fix for this issue may not be integrated in
 829          * the following firmware version. So the workaround in software driver
 830          * is needed. It needs to modify the initial values of 3 internal only
 831          * registers. Note that the workaround can be removed when it is fixed
 832          * in firmware in the future.
 833          */
 834         i40e_configure_registers(hw);
 835
 836         /* Get hw capabilities */
 837         ret = i40e_get_cap(hw);
 838         if (ret != I40E_SUCCESS) {
 839                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 840                 goto err_get_capabilities;
 841         }
 842
 843         /* Initialize parameters for PF */
 844         ret = i40e_pf_parameter_init(dev);
 845         if (ret != 0) {
 846                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 847                 goto err_parameter_init;
 848         }
 849
 850         /* Initialize the queue management */
 851         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 852         if (ret < 0) {
 853                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 854                 goto err_qp_pool_init;
 855         }
 856         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 857                                 hw->func_caps.num_msix_vectors - 1);
 858         if (ret < 0) {
 859                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 860                 goto err_msix_pool_init;
 861         }
 862
 863         /* Initialize lan hmc */
 864         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 865                                 hw->func_caps.num_rx_qp, 0, 0);
 866         if (ret != I40E_SUCCESS) {
 867                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 868                 goto err_init_lan_hmc;
 869         }
 870
 871         /* Configure lan hmc */
 872         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 873         if (ret != I40E_SUCCESS) {
 874                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 875                 goto err_configure_lan_hmc;
 876         }
 877
 878         /* Get and check the mac address */
 879         i40e_get_mac_addr(hw, hw->mac.addr);
 880         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 881                 PMD_INIT_LOG(ERR, "mac address is not valid");
 882                 ret = -EIO;
 883                 goto err_get_mac_addr;
 884         }
 885         /* Copy the permanent MAC address */
 886         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 887                         (struct ether_addr *) hw->mac.perm_addr);
 888
 889         /* Disable flow control */
 890         hw->fc.requested_mode = I40E_FC_NONE;
 891         i40e_set_fc(hw, &aq_fail, TRUE);
 892
 893         /* Set the global registers with default ether type value */
 894         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 895         if (ret != I40E_SUCCESS) {
 896                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 897                              "VLAN ether type");
 898                 goto err_setup_pf_switch;
 899         }
 900         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 901         if (ret != I40E_SUCCESS) {
 902                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 903                              "VLAN ether type");
 904                 goto err_setup_pf_switch;
 905         }
 906
 907         /* PF setup, which includes VSI setup */
 908         ret = i40e_pf_setup(pf);
 909         if (ret) {
 910                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 911                 goto err_setup_pf_switch;
 912         }
 913
 914         vsi = pf->main_vsi;
 915
 916         /* Disable double vlan by default */
 917         i40e_vsi_config_double_vlan(vsi, FALSE);
 918
 919         if (!vsi->max_macaddrs)
 920                 len = ETHER_ADDR_LEN;
 921         else
 922                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 923
 924         /* Should be after VSI initialized */
 925         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 926         if (!dev->data->mac_addrs) {
 927                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 928                                         "for storing mac address");
 929                 goto err_mac_alloc;
 930         }
 931         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 932                                         &dev->data->mac_addrs[0]);
 933
 934         /* initialize pf host driver to setup SRIOV resource if applicable */
 935         i40e_pf_host_init(dev);
 936
 937         /* register callback func to eal lib */
 938         rte_intr_callback_register(&(pci_dev->intr_handle),
 939                 i40e_dev_interrupt_handler, (void *)dev);
 940
 941         /* configure and enable device interrupt */
 942         i40e_pf_config_irq0(hw, TRUE);
 943         i40e_pf_enable_irq0(hw);
 944
 945         /* enable uio intr after callback register */
 946         rte_intr_enable(&(pci_dev->intr_handle));
 947         /*
 948          * Add an ethertype filter to drop all flow control frames transmitted
 949          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 950          * frames to wire.
 951          */
 952         i40e_add_tx_flow_control_drop_filter(pf);
 953
 954         /* Set the max frame size to 0x2600 by default,
 955          * in case other drivers changed the default value.
 956          */
 957         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 958
 959         /* initialize mirror rule list */
 960         TAILQ_INIT(&pf->mirror_list);
 961
 962         /* Init dcb to sw mode by default */
 963         ret = i40e_dcb_init_configure(dev, TRUE);
 964         if (ret != I40E_SUCCESS) {
 965                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 966                 pf->flags &= ~I40E_FLAG_DCB;
 967         }
 968
 969         return 0;
 970
 971 err_mac_alloc:
 972         i40e_vsi_release(pf->main_vsi);
 973 err_setup_pf_switch:
 974 err_get_mac_addr:
 975 err_configure_lan_hmc:
 976         (void)i40e_shutdown_lan_hmc(hw);
 977 err_init_lan_hmc:
 978         i40e_res_pool_destroy(&pf->msix_pool);
 979 err_msix_pool_init:
 980         i40e_res_pool_destroy(&pf->qp_pool);
 981 err_qp_pool_init:
 982 err_parameter_init:
 983 err_get_capabilities:
 984         (void)i40e_shutdown_adminq(hw);
 985
 986         return ret;
 987 }
 988
 989 static int
 990 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 991 {
 992         struct rte_pci_device *pci_dev;
 993         struct i40e_hw *hw;
 994         struct i40e_filter_control_settings settings;
 995         int ret;
 996         uint8_t aq_fail = 0;
 997
 998         PMD_INIT_FUNC_TRACE();
 999
1000         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1001                 return 0;
1002
1003         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1004         pci_dev = dev->pci_dev;
1005
1006         if (hw->adapter_stopped == 0)
1007                 i40e_dev_close(dev);
1008
1009         dev->dev_ops = NULL;
1010         dev->rx_pkt_burst = NULL;
1011         dev->tx_pkt_burst = NULL;
1012
1013         /* Disable LLDP */
1014         ret = i40e_aq_stop_lldp(hw, true, NULL);
1015         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1016                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1017
1018         /* Clear PXE mode */
1019         i40e_clear_pxe_mode(hw);
1020
1021         /* Unconfigure filter control */
1022         memset(&settings, 0, sizeof(settings));
1023         ret = i40e_set_filter_control(hw, &settings);
1024         if (ret)
1025                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1026                                         ret);
1027
1028         /* Disable flow control */
1029         hw->fc.requested_mode = I40E_FC_NONE;
1030         i40e_set_fc(hw, &aq_fail, TRUE);
1031
1032         /* uninitialize pf host driver */
1033         i40e_pf_host_uninit(dev);
1034
1035         rte_free(dev->data->mac_addrs);
1036         dev->data->mac_addrs = NULL;
1037
1038         /* disable uio intr before callback unregister */
1039         rte_intr_disable(&(pci_dev->intr_handle));
1040
1041         /* register callback func to eal lib */
1042         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1043                 i40e_dev_interrupt_handler, (void *)dev);
1044
1045         return 0;
1046 }
1047
1048 static int
1049 i40e_dev_configure(struct rte_eth_dev *dev)
1050 {
1051         struct i40e_adapter *ad =
1052                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1054         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1055         int i, ret;
1056
1057         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1058          * bulk allocation or vector Rx preconditions we will reset it.
1059          */
1060         ad->rx_bulk_alloc_allowed = true;
1061         ad->rx_vec_allowed = true;
1062         ad->tx_simple_allowed = true;
1063         ad->tx_vec_allowed = true;
1064
1065         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1066                 ret = i40e_fdir_setup(pf);
1067                 if (ret != I40E_SUCCESS) {
1068                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1069                         return -ENOTSUP;
1070                 }
1071                 ret = i40e_fdir_configure(dev);
1072                 if (ret < 0) {
1073                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1074                         goto err;
1075                 }
1076         } else
1077                 i40e_fdir_teardown(pf);
1078
1079         ret = i40e_dev_init_vlan(dev);
1080         if (ret < 0)
1081                 goto err;
1082
1083         /* VMDQ setup.
1084          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1085          *  RSS setting have different requirements.
1086          *  General PMD driver call sequence are NIC init, configure,
1087          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1088          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1089          *  applicable. So, VMDQ setting has to be done before
1090          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1091          *  For RSS setting, it will try to calculate actual configured RX queue
1092          *  number, which will be available after rx_queue_setup(). dev_start()
1093          *  function is good to place RSS setup.
1094          */
1095         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1096                 ret = i40e_vmdq_setup(dev);
1097                 if (ret)
1098                         goto err;
1099         }
1100
1101         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1102                 ret = i40e_dcb_setup(dev);
1103                 if (ret) {
1104                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1105                         goto err_dcb;
1106                 }
1107         }
1108
1109         return 0;
1110
1111 err_dcb:
1112         /* need to release vmdq resource if exists */
1113         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1114                 i40e_vsi_release(pf->vmdq[i].vsi);
1115                 pf->vmdq[i].vsi = NULL;
1116         }
1117         rte_free(pf->vmdq);
1118         pf->vmdq = NULL;
1119 err:
1120         /* need to release fdir resource if exists */
1121         i40e_fdir_teardown(pf);
1122         return ret;
1123 }
1124
1125 void
1126 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1127 {
1128         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1129         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1130         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1131         uint16_t msix_vect = vsi->msix_intr;
1132         uint16_t i;
1133
1134         for (i = 0; i < vsi->nb_qps; i++) {
1135                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1136                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1137                 rte_wmb();
1138         }
1139
1140         if (vsi->type != I40E_VSI_SRIOV) {
1141                 if (!rte_intr_allow_others(intr_handle)) {
1142                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1143                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1144                         I40E_WRITE_REG(hw,
1145                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1146                                        0);
1147                 } else {
1148                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1149                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1150                         I40E_WRITE_REG(hw,
1151                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1152                                                        msix_vect - 1), 0);
1153                 }
1154         } else {
1155                 uint32_t reg;
1156                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1157                         vsi->user_param + (msix_vect - 1);
1158
1159                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1160                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1161         }
1162         I40E_WRITE_FLUSH(hw);
1163 }
1164
1165 static void
1166 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1167                        int base_queue, int nb_queue)
1168 {
1169         int i;
1170         uint32_t val;
1171         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1172
1173         /* Bind all RX queues to allocated MSIX interrupt */
1174         for (i = 0; i < nb_queue; i++) {
1175                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1176                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1177                         ((base_queue + i + 1) <<
1178                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1179                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1180                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1181
1182                 if (i == nb_queue - 1)
1183                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1184                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1185         }
1186
1187         /* Write first RX queue to Link list register as the head element */
1188         if (vsi->type != I40E_VSI_SRIOV) {
1189                 uint16_t interval =
1190                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1191
1192                 if (msix_vect == I40E_MISC_VEC_ID) {
1193                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1194                                        (base_queue <<
1195                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1196                                        (0x0 <<
1197                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1198                         I40E_WRITE_REG(hw,
1199                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1200                                        interval);
1201                 } else {
1202                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1203                                        (base_queue <<
1204                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1205                                        (0x0 <<
1206                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1207                         I40E_WRITE_REG(hw,
1208                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1209                                                        msix_vect - 1),
1210                                        interval);
1211                 }
1212         } else {
1213                 uint32_t reg;
1214
1215                 if (msix_vect == I40E_MISC_VEC_ID) {
1216                         I40E_WRITE_REG(hw,
1217                                        I40E_VPINT_LNKLST0(vsi->user_param),
1218                                        (base_queue <<
1219                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1220                                        (0x0 <<
1221                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1222                 } else {
1223                         /* num_msix_vectors_vf needs to minus irq0 */
1224                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1225                                 vsi->user_param + (msix_vect - 1);
1226
1227                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1228                                        (base_queue <<
1229                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1230                                        (0x0 <<
1231                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1232                 }
1233         }
1234
1235         I40E_WRITE_FLUSH(hw);
1236 }
1237
1238 void
1239 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1240 {
1241         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1242         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1243         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1244         uint16_t msix_vect = vsi->msix_intr;
1245         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1246         uint16_t queue_idx = 0;
1247         int record = 0;
1248         uint32_t val;
1249         int i;
1250
1251         for (i = 0; i < vsi->nb_qps; i++) {
1252                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1253                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1254         }
1255
1256         /* INTENA flag is not auto-cleared for interrupt */
1257         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1258         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1259                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1260                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1261         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1262
1263         /* VF bind interrupt */
1264         if (vsi->type == I40E_VSI_SRIOV) {
1265                 __vsi_queues_bind_intr(vsi, msix_vect,
1266                                        vsi->base_queue, vsi->nb_qps);
1267                 return;
1268         }
1269
1270         /* PF & VMDq bind interrupt */
1271         if (rte_intr_dp_is_en(intr_handle)) {
1272                 if (vsi->type == I40E_VSI_MAIN) {
1273                         queue_idx = 0;
1274                         record = 1;
1275                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1276                         struct i40e_vsi *main_vsi =
1277                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1278                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1279                         record = 1;
1280                 }
1281         }
1282
1283         for (i = 0; i < vsi->nb_used_qps; i++) {
1284                 if (nb_msix <= 1) {
1285                         if (!rte_intr_allow_others(intr_handle))
1286                                 /* allow to share MISC_VEC_ID */
1287                                 msix_vect = I40E_MISC_VEC_ID;
1288
1289                         /* no enough msix_vect, map all to one */
1290                         __vsi_queues_bind_intr(vsi, msix_vect,
1291                                                vsi->base_queue + i,
1292                                                vsi->nb_used_qps - i);
1293                         for (; !!record && i < vsi->nb_used_qps; i++)
1294                                 intr_handle->intr_vec[queue_idx + i] =
1295                                         msix_vect;
1296                         break;
1297                 }
1298                 /* 1:1 queue/msix_vect mapping */
1299                 __vsi_queues_bind_intr(vsi, msix_vect,
1300                                        vsi->base_queue + i, 1);
1301                 if (!!record)
1302                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1303
1304                 msix_vect++;
1305                 nb_msix--;
1306         }
1307 }
1308
1309 static void
1310 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1311 {
1312         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1313         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1314         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1315         uint16_t interval = i40e_calc_itr_interval(\
1316                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1317         uint16_t msix_intr, i;
1318
1319         if (rte_intr_allow_others(intr_handle))
1320                 for (i = 0; i < vsi->nb_msix; i++) {
1321                         msix_intr = vsi->msix_intr + i;
1322                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1323                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1324                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1325                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1326                                 (interval <<
1327                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1328                 }
1329         else
1330                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1331                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1332                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1333                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1334                                (interval <<
1335                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1336
1337         I40E_WRITE_FLUSH(hw);
1338 }
1339
1340 static void
1341 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1342 {
1343         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1344         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1345         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1346         uint16_t msix_intr, i;
1347
1348         if (rte_intr_allow_others(intr_handle))
1349                 for (i = 0; i < vsi->nb_msix; i++) {
1350                         msix_intr = vsi->msix_intr + i;
1351                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1352                                        0);
1353                 }
1354         else
1355                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1356
1357         I40E_WRITE_FLUSH(hw);
1358 }
1359
1360 static inline uint8_t
1361 i40e_parse_link_speed(uint16_t eth_link_speed)
1362 {
1363         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1364
1365         switch (eth_link_speed) {
1366         case ETH_LINK_SPEED_40G:
1367                 link_speed = I40E_LINK_SPEED_40GB;
1368                 break;
1369         case ETH_LINK_SPEED_20G:
1370                 link_speed = I40E_LINK_SPEED_20GB;
1371                 break;
1372         case ETH_LINK_SPEED_10G:
1373                 link_speed = I40E_LINK_SPEED_10GB;
1374                 break;
1375         case ETH_LINK_SPEED_1000:
1376                 link_speed = I40E_LINK_SPEED_1GB;
1377                 break;
1378         case ETH_LINK_SPEED_100:
1379                 link_speed = I40E_LINK_SPEED_100MB;
1380                 break;
1381         }
1382
1383         return link_speed;
1384 }
1385
1386 static int
1387 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1388                    __rte_unused uint8_t abilities,
1389                    __rte_unused uint8_t force_speed)
1390 {
1391         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1392          * for the link control limitation of that all link control should be
1393          * handled by firmware. It should follow up if link control will be
1394          * opened to software driver in future firmware versions.
1395          */
1396         return I40E_SUCCESS;
1397 }
1398
1399 static int
1400 i40e_apply_link_speed(struct rte_eth_dev *dev)
1401 {
1402         uint8_t speed;
1403         uint8_t abilities = 0;
1404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1405         struct rte_eth_conf *conf = &dev->data->dev_conf;
1406
1407         speed = i40e_parse_link_speed(conf->link_speed);
1408         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1409         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1410                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1411         else
1412                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1413
1414         return i40e_phy_conf_link(hw, abilities, speed);
1415 }
1416
1417 static int
1418 i40e_dev_start(struct rte_eth_dev *dev)
1419 {
1420         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1421         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422         struct i40e_vsi *main_vsi = pf->main_vsi;
1423         int ret, i;
1424         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1425         uint32_t intr_vector = 0;
1426
1427         hw->adapter_stopped = 0;
1428
1429         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1430                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1431                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1432                              dev->data->dev_conf.link_duplex,
1433                              dev->data->port_id);
1434                 return -EINVAL;
1435         }
1436
1437         rte_intr_disable(intr_handle);
1438
1439         if ((rte_intr_cap_multiple(intr_handle) ||
1440              !RTE_ETH_DEV_SRIOV(dev).active) &&
1441             dev->data->dev_conf.intr_conf.rxq != 0) {
1442                 intr_vector = dev->data->nb_rx_queues;
1443                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1444                         return -1;
1445         }
1446
1447         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1448                 intr_handle->intr_vec =
1449                         rte_zmalloc("intr_vec",
1450                                     dev->data->nb_rx_queues * sizeof(int),
1451                                     0);
1452                 if (!intr_handle->intr_vec) {
1453                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1454                                      " intr_vec\n", dev->data->nb_rx_queues);
1455                         return -ENOMEM;
1456                 }
1457         }
1458
1459         /* Initialize VSI */
1460         ret = i40e_dev_rxtx_init(pf);
1461         if (ret != I40E_SUCCESS) {
1462                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1463                 goto err_up;
1464         }
1465
1466         /* Map queues with MSIX interrupt */
1467         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1468                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1469         i40e_vsi_queues_bind_intr(main_vsi);
1470         i40e_vsi_enable_queues_intr(main_vsi);
1471
1472         /* Map VMDQ VSI queues with MSIX interrupt */
1473         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1474                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1475                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1476                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1477         }
1478
1479         /* enable FDIR MSIX interrupt */
1480         if (pf->fdir.fdir_vsi) {
1481                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1482                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1483         }
1484
1485         /* Enable all queues which have been configured */
1486         ret = i40e_dev_switch_queues(pf, TRUE);
1487         if (ret != I40E_SUCCESS) {
1488                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1489                 goto err_up;
1490         }
1491
1492         /* Enable receiving broadcast packets */
1493         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1494         if (ret != I40E_SUCCESS)
1495                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1496
1497         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1498                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1499                                                 true, NULL);
1500                 if (ret != I40E_SUCCESS)
1501                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1502         }
1503
1504         /* Apply link configure */
1505         ret = i40e_apply_link_speed(dev);
1506         if (I40E_SUCCESS != ret) {
1507                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1508                 goto err_up;
1509         }
1510
1511         if (!rte_intr_allow_others(intr_handle)) {
1512                 rte_intr_callback_unregister(intr_handle,
1513                                              i40e_dev_interrupt_handler,
1514                                              (void *)dev);
1515                 /* configure and enable device interrupt */
1516                 i40e_pf_config_irq0(hw, FALSE);
1517                 i40e_pf_enable_irq0(hw);
1518
1519                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1520                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1521                                      " no intr multiplex\n");
1522         }
1523
1524         /* enable uio intr after callback register */
1525         rte_intr_enable(intr_handle);
1526
1527         return I40E_SUCCESS;
1528
1529 err_up:
1530         i40e_dev_switch_queues(pf, FALSE);
1531         i40e_dev_clear_queues(dev);
1532
1533         return ret;
1534 }
1535
1536 static void
1537 i40e_dev_stop(struct rte_eth_dev *dev)
1538 {
1539         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1540         struct i40e_vsi *main_vsi = pf->main_vsi;
1541         struct i40e_mirror_rule *p_mirror;
1542         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1543         int i;
1544
1545         /* Disable all queues */
1546         i40e_dev_switch_queues(pf, FALSE);
1547
1548         /* un-map queues with interrupt registers */
1549         i40e_vsi_disable_queues_intr(main_vsi);
1550         i40e_vsi_queues_unbind_intr(main_vsi);
1551
1552         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1553                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1554                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1555         }
1556
1557         if (pf->fdir.fdir_vsi) {
1558                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1559                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1560         }
1561         /* Clear all queues and release memory */
1562         i40e_dev_clear_queues(dev);
1563
1564         /* Set link down */
1565         i40e_dev_set_link_down(dev);
1566
1567         /* Remove all mirror rules */
1568         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1569                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1570                 rte_free(p_mirror);
1571         }
1572         pf->nb_mirror_rule = 0;
1573
1574         if (!rte_intr_allow_others(intr_handle))
1575                 /* resume to the default handler */
1576                 rte_intr_callback_register(intr_handle,
1577                                            i40e_dev_interrupt_handler,
1578                                            (void *)dev);
1579
1580         /* Clean datapath event and queue/vec mapping */
1581         rte_intr_efd_disable(intr_handle);
1582         if (intr_handle->intr_vec) {
1583                 rte_free(intr_handle->intr_vec);
1584                 intr_handle->intr_vec = NULL;
1585         }
1586 }
1587
1588 static void
1589 i40e_dev_close(struct rte_eth_dev *dev)
1590 {
1591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1593         uint32_t reg;
1594         int i;
1595
1596         PMD_INIT_FUNC_TRACE();
1597
1598         i40e_dev_stop(dev);
1599         hw->adapter_stopped = 1;
1600         i40e_dev_free_queues(dev);
1601
1602         /* Disable interrupt */
1603         i40e_pf_disable_irq0(hw);
1604         rte_intr_disable(&(dev->pci_dev->intr_handle));
1605
1606         /* shutdown and destroy the HMC */
1607         i40e_shutdown_lan_hmc(hw);
1608
1609         /* release all the existing VSIs and VEBs */
1610         i40e_fdir_teardown(pf);
1611         i40e_vsi_release(pf->main_vsi);
1612
1613         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1614                 i40e_vsi_release(pf->vmdq[i].vsi);
1615                 pf->vmdq[i].vsi = NULL;
1616         }
1617
1618         rte_free(pf->vmdq);
1619         pf->vmdq = NULL;
1620
1621         /* shutdown the adminq */
1622         i40e_aq_queue_shutdown(hw, true);
1623         i40e_shutdown_adminq(hw);
1624
1625         i40e_res_pool_destroy(&pf->qp_pool);
1626         i40e_res_pool_destroy(&pf->msix_pool);
1627
1628         /* force a PF reset to clean anything leftover */
1629         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1630         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1631                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1632         I40E_WRITE_FLUSH(hw);
1633 }
1634
1635 static void
1636 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1637 {
1638         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         struct i40e_vsi *vsi = pf->main_vsi;
1641         int status;
1642
1643         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1644                                                         true, NULL);
1645         if (status != I40E_SUCCESS)
1646                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1647
1648         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1649                                                         TRUE, NULL);
1650         if (status != I40E_SUCCESS)
1651                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1652
1653 }
1654
1655 static void
1656 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1657 {
1658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660         struct i40e_vsi *vsi = pf->main_vsi;
1661         int status;
1662
1663         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1664                                                         false, NULL);
1665         if (status != I40E_SUCCESS)
1666                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1667
1668         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1669                                                         false, NULL);
1670         if (status != I40E_SUCCESS)
1671                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1672 }
1673
1674 static void
1675 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1676 {
1677         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1679         struct i40e_vsi *vsi = pf->main_vsi;
1680         int ret;
1681
1682         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1683         if (ret != I40E_SUCCESS)
1684                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1685 }
1686
1687 static void
1688 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1689 {
1690         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692         struct i40e_vsi *vsi = pf->main_vsi;
1693         int ret;
1694
1695         if (dev->data->promiscuous == 1)
1696                 return; /* must remain in all_multicast mode */
1697
1698         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1699                                 vsi->seid, FALSE, NULL);
1700         if (ret != I40E_SUCCESS)
1701                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1702 }
1703
1704 /*
1705  * Set device link up.
1706  */
1707 static int
1708 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1709 {
1710         /* re-apply link speed setting */
1711         return i40e_apply_link_speed(dev);
1712 }
1713
1714 /*
1715  * Set device link down.
1716  */
1717 static int
1718 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1719 {
1720         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1721         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1722         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723
1724         return i40e_phy_conf_link(hw, abilities, speed);
1725 }
1726
1727 int
1728 i40e_dev_link_update(struct rte_eth_dev *dev,
1729                      int wait_to_complete)
1730 {
1731 #define CHECK_INTERVAL 100  /* 100ms */
1732 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1734         struct i40e_link_status link_status;
1735         struct rte_eth_link link, old;
1736         int status;
1737         unsigned rep_cnt = MAX_REPEAT_TIME;
1738
1739         memset(&link, 0, sizeof(link));
1740         memset(&old, 0, sizeof(old));
1741         memset(&link_status, 0, sizeof(link_status));
1742         rte_i40e_dev_atomic_read_link_status(dev, &old);
1743
1744         do {
1745                 /* Get link status information from hardware */
1746                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1747                 if (status != I40E_SUCCESS) {
1748                         link.link_speed = ETH_LINK_SPEED_100;
1749                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1750                         PMD_DRV_LOG(ERR, "Failed to get link info");
1751                         goto out;
1752                 }
1753
1754                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1755                 if (!wait_to_complete)
1756                         break;
1757
1758                 rte_delay_ms(CHECK_INTERVAL);
1759         } while (!link.link_status && rep_cnt--);
1760
1761         if (!link.link_status)
1762                 goto out;
1763
1764         /* i40e uses full duplex only */
1765         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1766
1767         /* Parse the link status */
1768         switch (link_status.link_speed) {
1769         case I40E_LINK_SPEED_100MB:
1770                 link.link_speed = ETH_LINK_SPEED_100;
1771                 break;
1772         case I40E_LINK_SPEED_1GB:
1773                 link.link_speed = ETH_LINK_SPEED_1000;
1774                 break;
1775         case I40E_LINK_SPEED_10GB:
1776                 link.link_speed = ETH_LINK_SPEED_10G;
1777                 break;
1778         case I40E_LINK_SPEED_20GB:
1779                 link.link_speed = ETH_LINK_SPEED_20G;
1780                 break;
1781         case I40E_LINK_SPEED_40GB:
1782                 link.link_speed = ETH_LINK_SPEED_40G;
1783                 break;
1784         default:
1785                 link.link_speed = ETH_LINK_SPEED_100;
1786                 break;
1787         }
1788
1789 out:
1790         rte_i40e_dev_atomic_write_link_status(dev, &link);
1791         if (link.link_status == old.link_status)
1792                 return -1;
1793
1794         return 0;
1795 }
1796
1797 /* Get all the statistics of a VSI */
1798 void
1799 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1800 {
1801         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1802         struct i40e_eth_stats *nes = &vsi->eth_stats;
1803         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1804         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1805
1806         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1807                             vsi->offset_loaded, &oes->rx_bytes,
1808                             &nes->rx_bytes);
1809         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1810                             vsi->offset_loaded, &oes->rx_unicast,
1811                             &nes->rx_unicast);
1812         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1813                             vsi->offset_loaded, &oes->rx_multicast,
1814                             &nes->rx_multicast);
1815         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1816                             vsi->offset_loaded, &oes->rx_broadcast,
1817                             &nes->rx_broadcast);
1818         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1819                             &oes->rx_discards, &nes->rx_discards);
1820         /* GLV_REPC not supported */
1821         /* GLV_RMPC not supported */
1822         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1823                             &oes->rx_unknown_protocol,
1824                             &nes->rx_unknown_protocol);
1825         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1826                             vsi->offset_loaded, &oes->tx_bytes,
1827                             &nes->tx_bytes);
1828         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1829                             vsi->offset_loaded, &oes->tx_unicast,
1830                             &nes->tx_unicast);
1831         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1832                             vsi->offset_loaded, &oes->tx_multicast,
1833                             &nes->tx_multicast);
1834         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1835                             vsi->offset_loaded,  &oes->tx_broadcast,
1836                             &nes->tx_broadcast);
1837         /* GLV_TDPC not supported */
1838         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1839                             &oes->tx_errors, &nes->tx_errors);
1840         vsi->offset_loaded = true;
1841
1842         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1843                     vsi->vsi_id);
1844         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1845         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1846         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1847         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1848         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1849         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1850                     nes->rx_unknown_protocol);
1851         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1852         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1853         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1854         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1855         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1856         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1857         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1858                     vsi->vsi_id);
1859 }
1860
1861 static void
1862 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1863 {
1864         unsigned int i;
1865         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1866         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1867
1868         /* Get statistics of struct i40e_eth_stats */
1869         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1870                             I40E_GLPRT_GORCL(hw->port),
1871                             pf->offset_loaded, &os->eth.rx_bytes,
1872                             &ns->eth.rx_bytes);
1873         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1874                             I40E_GLPRT_UPRCL(hw->port),
1875                             pf->offset_loaded, &os->eth.rx_unicast,
1876                             &ns->eth.rx_unicast);
1877         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1878                             I40E_GLPRT_MPRCL(hw->port),
1879                             pf->offset_loaded, &os->eth.rx_multicast,
1880                             &ns->eth.rx_multicast);
1881         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1882                             I40E_GLPRT_BPRCL(hw->port),
1883                             pf->offset_loaded, &os->eth.rx_broadcast,
1884                             &ns->eth.rx_broadcast);
1885         /* Workaround: CRC size should not be included in byte statistics,
1886          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1887          */
1888         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1889                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1890
1891         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1892                             pf->offset_loaded, &os->eth.rx_discards,
1893                             &ns->eth.rx_discards);
1894         /* GLPRT_REPC not supported */
1895         /* GLPRT_RMPC not supported */
1896         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1897                             pf->offset_loaded,
1898                             &os->eth.rx_unknown_protocol,
1899                             &ns->eth.rx_unknown_protocol);
1900         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1901                             I40E_GLPRT_GOTCL(hw->port),
1902                             pf->offset_loaded, &os->eth.tx_bytes,
1903                             &ns->eth.tx_bytes);
1904         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1905                             I40E_GLPRT_UPTCL(hw->port),
1906                             pf->offset_loaded, &os->eth.tx_unicast,
1907                             &ns->eth.tx_unicast);
1908         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1909                             I40E_GLPRT_MPTCL(hw->port),
1910                             pf->offset_loaded, &os->eth.tx_multicast,
1911                             &ns->eth.tx_multicast);
1912         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1913                             I40E_GLPRT_BPTCL(hw->port),
1914                             pf->offset_loaded, &os->eth.tx_broadcast,
1915                             &ns->eth.tx_broadcast);
1916         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1917                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1918         /* GLPRT_TEPC not supported */
1919
1920         /* additional port specific stats */
1921         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1922                             pf->offset_loaded, &os->tx_dropped_link_down,
1923                             &ns->tx_dropped_link_down);
1924         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1925                             pf->offset_loaded, &os->crc_errors,
1926                             &ns->crc_errors);
1927         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1928                             pf->offset_loaded, &os->illegal_bytes,
1929                             &ns->illegal_bytes);
1930         /* GLPRT_ERRBC not supported */
1931         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1932                             pf->offset_loaded, &os->mac_local_faults,
1933                             &ns->mac_local_faults);
1934         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1935                             pf->offset_loaded, &os->mac_remote_faults,
1936                             &ns->mac_remote_faults);
1937         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1938                             pf->offset_loaded, &os->rx_length_errors,
1939                             &ns->rx_length_errors);
1940         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1941                             pf->offset_loaded, &os->link_xon_rx,
1942                             &ns->link_xon_rx);
1943         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1944                             pf->offset_loaded, &os->link_xoff_rx,
1945                             &ns->link_xoff_rx);
1946         for (i = 0; i < 8; i++) {
1947                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1948                                     pf->offset_loaded,
1949                                     &os->priority_xon_rx[i],
1950                                     &ns->priority_xon_rx[i]);
1951                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1952                                     pf->offset_loaded,
1953                                     &os->priority_xoff_rx[i],
1954                                     &ns->priority_xoff_rx[i]);
1955         }
1956         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1957                             pf->offset_loaded, &os->link_xon_tx,
1958                             &ns->link_xon_tx);
1959         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1960                             pf->offset_loaded, &os->link_xoff_tx,
1961                             &ns->link_xoff_tx);
1962         for (i = 0; i < 8; i++) {
1963                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1964                                     pf->offset_loaded,
1965                                     &os->priority_xon_tx[i],
1966                                     &ns->priority_xon_tx[i]);
1967                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1968                                     pf->offset_loaded,
1969                                     &os->priority_xoff_tx[i],
1970                                     &ns->priority_xoff_tx[i]);
1971                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1972                                     pf->offset_loaded,
1973                                     &os->priority_xon_2_xoff[i],
1974                                     &ns->priority_xon_2_xoff[i]);
1975         }
1976         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1977                             I40E_GLPRT_PRC64L(hw->port),
1978                             pf->offset_loaded, &os->rx_size_64,
1979                             &ns->rx_size_64);
1980         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1981                             I40E_GLPRT_PRC127L(hw->port),
1982                             pf->offset_loaded, &os->rx_size_127,
1983                             &ns->rx_size_127);
1984         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1985                             I40E_GLPRT_PRC255L(hw->port),
1986                             pf->offset_loaded, &os->rx_size_255,
1987                             &ns->rx_size_255);
1988         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1989                             I40E_GLPRT_PRC511L(hw->port),
1990                             pf->offset_loaded, &os->rx_size_511,
1991                             &ns->rx_size_511);
1992         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1993                             I40E_GLPRT_PRC1023L(hw->port),
1994                             pf->offset_loaded, &os->rx_size_1023,
1995                             &ns->rx_size_1023);
1996         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1997                             I40E_GLPRT_PRC1522L(hw->port),
1998                             pf->offset_loaded, &os->rx_size_1522,
1999                             &ns->rx_size_1522);
2000         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2001                             I40E_GLPRT_PRC9522L(hw->port),
2002                             pf->offset_loaded, &os->rx_size_big,
2003                             &ns->rx_size_big);
2004         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2005                             pf->offset_loaded, &os->rx_undersize,
2006                             &ns->rx_undersize);
2007         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2008                             pf->offset_loaded, &os->rx_fragments,
2009                             &ns->rx_fragments);
2010         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2011                             pf->offset_loaded, &os->rx_oversize,
2012                             &ns->rx_oversize);
2013         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2014                             pf->offset_loaded, &os->rx_jabber,
2015                             &ns->rx_jabber);
2016         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2017                             I40E_GLPRT_PTC64L(hw->port),
2018                             pf->offset_loaded, &os->tx_size_64,
2019                             &ns->tx_size_64);
2020         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2021                             I40E_GLPRT_PTC127L(hw->port),
2022                             pf->offset_loaded, &os->tx_size_127,
2023                             &ns->tx_size_127);
2024         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2025                             I40E_GLPRT_PTC255L(hw->port),
2026                             pf->offset_loaded, &os->tx_size_255,
2027                             &ns->tx_size_255);
2028         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2029                             I40E_GLPRT_PTC511L(hw->port),
2030                             pf->offset_loaded, &os->tx_size_511,
2031                             &ns->tx_size_511);
2032         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2033                             I40E_GLPRT_PTC1023L(hw->port),
2034                             pf->offset_loaded, &os->tx_size_1023,
2035                             &ns->tx_size_1023);
2036         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2037                             I40E_GLPRT_PTC1522L(hw->port),
2038                             pf->offset_loaded, &os->tx_size_1522,
2039                             &ns->tx_size_1522);
2040         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2041                             I40E_GLPRT_PTC9522L(hw->port),
2042                             pf->offset_loaded, &os->tx_size_big,
2043                             &ns->tx_size_big);
2044         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2045                            pf->offset_loaded,
2046                            &os->fd_sb_match, &ns->fd_sb_match);
2047         /* GLPRT_MSPDC not supported */
2048         /* GLPRT_XEC not supported */
2049
2050         pf->offset_loaded = true;
2051
2052         if (pf->main_vsi)
2053                 i40e_update_vsi_stats(pf->main_vsi);
2054 }
2055
2056 /* Get all statistics of a port */
2057 static void
2058 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2059 {
2060         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2061         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2063         unsigned i;
2064
2065         /* call read registers - updates values, now write them to struct */
2066         i40e_read_stats_registers(pf, hw);
2067
2068         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2069                         pf->main_vsi->eth_stats.rx_multicast +
2070                         pf->main_vsi->eth_stats.rx_broadcast -
2071                         pf->main_vsi->eth_stats.rx_discards;
2072         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2073                         pf->main_vsi->eth_stats.tx_multicast +
2074                         pf->main_vsi->eth_stats.tx_broadcast;
2075         stats->ibytes   = ns->eth.rx_bytes;
2076         stats->obytes   = ns->eth.tx_bytes;
2077         stats->oerrors  = ns->eth.tx_errors +
2078                         pf->main_vsi->eth_stats.tx_errors;
2079         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2080
2081         /* Rx Errors */
2082         stats->imissed  = ns->eth.rx_discards +
2083                         pf->main_vsi->eth_stats.rx_discards;
2084         stats->ierrors  = ns->crc_errors +
2085                         ns->rx_length_errors + ns->rx_undersize +
2086                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2087                         stats->imissed;
2088
2089         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2090         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2091         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2092         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2093         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2094         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2095         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2096                     ns->eth.rx_unknown_protocol);
2097         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2098         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2099         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2100         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2101         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2102         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2103
2104         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2105                     ns->tx_dropped_link_down);
2106         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2107         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2108                     ns->illegal_bytes);
2109         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2110         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2111                     ns->mac_local_faults);
2112         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2113                     ns->mac_remote_faults);
2114         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2115                     ns->rx_length_errors);
2116         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2117         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2118         for (i = 0; i < 8; i++) {
2119                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2120                                 i, ns->priority_xon_rx[i]);
2121                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2122                                 i, ns->priority_xoff_rx[i]);
2123         }
2124         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2125         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2126         for (i = 0; i < 8; i++) {
2127                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2128                                 i, ns->priority_xon_tx[i]);
2129                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2130                                 i, ns->priority_xoff_tx[i]);
2131                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2132                                 i, ns->priority_xon_2_xoff[i]);
2133         }
2134         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2135         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2136         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2137         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2138         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2139         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2140         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2141         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2142         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2143         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2144         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2145         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2146         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2147         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2148         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2149         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2150         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2151         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2152         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2153                         ns->mac_short_packet_dropped);
2154         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2155                     ns->checksum_error);
2156         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2157         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2158 }
2159
2160 /* Reset the statistics */
2161 static void
2162 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2163 {
2164         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2165         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2166
2167         /* Mark PF and VSI stats to update the offset, aka "reset" */
2168         pf->offset_loaded = false;
2169         if (pf->main_vsi)
2170                 pf->main_vsi->offset_loaded = false;
2171
2172         /* read the stats, reading current register values into offset */
2173         i40e_read_stats_registers(pf, hw);
2174 }
2175
2176 static uint32_t
2177 i40e_xstats_calc_num(void)
2178 {
2179         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2180                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2181                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2182 }
2183
2184 static int
2185 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2186                     unsigned n)
2187 {
2188         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190         unsigned i, count, prio;
2191         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2192
2193         count = i40e_xstats_calc_num();
2194         if (n < count)
2195                 return count;
2196
2197         i40e_read_stats_registers(pf, hw);
2198
2199         if (xstats == NULL)
2200                 return 0;
2201
2202         count = 0;
2203
2204         /* Get stats from i40e_eth_stats struct */
2205         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2206                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2207                          "%s", rte_i40e_stats_strings[i].name);
2208                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2209                         rte_i40e_stats_strings[i].offset);
2210                 count++;
2211         }
2212
2213         /* Get individiual stats from i40e_hw_port struct */
2214         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2215                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2216                          "%s", rte_i40e_hw_port_strings[i].name);
2217                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2218                                 rte_i40e_hw_port_strings[i].offset);
2219                 count++;
2220         }
2221
2222         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2223                 for (prio = 0; prio < 8; prio++) {
2224                         snprintf(xstats[count].name,
2225                                  sizeof(xstats[count].name),
2226                                  "rx_priority%u_%s", prio,
2227                                  rte_i40e_rxq_prio_strings[i].name);
2228                         xstats[count].value =
2229                                 *(uint64_t *)(((char *)hw_stats) +
2230                                 rte_i40e_rxq_prio_strings[i].offset +
2231                                 (sizeof(uint64_t) * prio));
2232                         count++;
2233                 }
2234         }
2235
2236         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2237                 for (prio = 0; prio < 8; prio++) {
2238                         snprintf(xstats[count].name,
2239                                  sizeof(xstats[count].name),
2240                                  "tx_priority%u_%s", prio,
2241                                  rte_i40e_txq_prio_strings[i].name);
2242                         xstats[count].value =
2243                                 *(uint64_t *)(((char *)hw_stats) +
2244                                 rte_i40e_txq_prio_strings[i].offset +
2245                                 (sizeof(uint64_t) * prio));
2246                         count++;
2247                 }
2248         }
2249
2250         return count;
2251 }
2252
2253 static int
2254 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2255                                  __rte_unused uint16_t queue_id,
2256                                  __rte_unused uint8_t stat_idx,
2257                                  __rte_unused uint8_t is_rx)
2258 {
2259         PMD_INIT_FUNC_TRACE();
2260
2261         return -ENOSYS;
2262 }
2263
2264 static void
2265 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2266 {
2267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2268         struct i40e_vsi *vsi = pf->main_vsi;
2269
2270         dev_info->max_rx_queues = vsi->nb_qps;
2271         dev_info->max_tx_queues = vsi->nb_qps;
2272         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2273         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2274         dev_info->max_mac_addrs = vsi->max_macaddrs;
2275         dev_info->max_vfs = dev->pci_dev->max_vfs;
2276         dev_info->rx_offload_capa =
2277                 DEV_RX_OFFLOAD_VLAN_STRIP |
2278                 DEV_RX_OFFLOAD_QINQ_STRIP |
2279                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2280                 DEV_RX_OFFLOAD_UDP_CKSUM |
2281                 DEV_RX_OFFLOAD_TCP_CKSUM;
2282         dev_info->tx_offload_capa =
2283                 DEV_TX_OFFLOAD_VLAN_INSERT |
2284                 DEV_TX_OFFLOAD_QINQ_INSERT |
2285                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2286                 DEV_TX_OFFLOAD_UDP_CKSUM |
2287                 DEV_TX_OFFLOAD_TCP_CKSUM |
2288                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2289                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2290                 DEV_TX_OFFLOAD_TCP_TSO;
2291         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2292                                                 sizeof(uint32_t);
2293         dev_info->reta_size = pf->hash_lut_size;
2294         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2295
2296         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2297                 .rx_thresh = {
2298                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2299                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2300                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2301                 },
2302                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2303                 .rx_drop_en = 0,
2304         };
2305
2306         dev_info->default_txconf = (struct rte_eth_txconf) {
2307                 .tx_thresh = {
2308                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2309                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2310                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2311                 },
2312                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2313                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2314                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2315                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2316         };
2317
2318         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2319                 .nb_max = I40E_MAX_RING_DESC,
2320                 .nb_min = I40E_MIN_RING_DESC,
2321                 .nb_align = I40E_ALIGN_RING_DESC,
2322         };
2323
2324         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2325                 .nb_max = I40E_MAX_RING_DESC,
2326                 .nb_min = I40E_MIN_RING_DESC,
2327                 .nb_align = I40E_ALIGN_RING_DESC,
2328         };
2329
2330         if (pf->flags & I40E_FLAG_VMDQ) {
2331                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2332                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2333                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2334                                                 pf->max_nb_vmdq_vsi;
2335                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2336                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2337                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2338         }
2339 }
2340
2341 static int
2342 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2343 {
2344         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2345         struct i40e_vsi *vsi = pf->main_vsi;
2346         PMD_INIT_FUNC_TRACE();
2347
2348         if (on)
2349                 return i40e_vsi_add_vlan(vsi, vlan_id);
2350         else
2351                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2352 }
2353
2354 static int
2355 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2356                    enum rte_vlan_type vlan_type,
2357                    uint16_t tpid)
2358 {
2359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2360         uint64_t reg_r = 0, reg_w = 0;
2361         uint16_t reg_id = 0;
2362         int ret = 0;
2363
2364         switch (vlan_type) {
2365         case ETH_VLAN_TYPE_OUTER:
2366                 reg_id = 2;
2367                 break;
2368         case ETH_VLAN_TYPE_INNER:
2369                 reg_id = 3;
2370                 break;
2371         default:
2372                 ret = -EINVAL;
2373                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2374                 return ret;
2375         }
2376         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2377                                           &reg_r, NULL);
2378         if (ret != I40E_SUCCESS) {
2379                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2380                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2381                 ret = -EIO;
2382                 return ret;
2383         }
2384         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2385                     "0x%08"PRIx64"", reg_id, reg_r);
2386
2387         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2388         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2389         if (reg_r == reg_w) {
2390                 ret = 0;
2391                 PMD_DRV_LOG(DEBUG, "No need to write");
2392                 return ret;
2393         }
2394
2395         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2396                                            reg_w, NULL);
2397         if (ret != I40E_SUCCESS) {
2398                 ret = -EIO;
2399                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2400                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2401                 return ret;
2402         }
2403         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2404                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2405
2406         return ret;
2407 }
2408
2409 static void
2410 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2411 {
2412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2413         struct i40e_vsi *vsi = pf->main_vsi;
2414
2415         if (mask & ETH_VLAN_STRIP_MASK) {
2416                 /* Enable or disable VLAN stripping */
2417                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2418                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2419                 else
2420                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2421         }
2422
2423         if (mask & ETH_VLAN_EXTEND_MASK) {
2424                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2425                         i40e_vsi_config_double_vlan(vsi, TRUE);
2426                 else
2427                         i40e_vsi_config_double_vlan(vsi, FALSE);
2428         }
2429 }
2430
2431 static void
2432 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2433                           __rte_unused uint16_t queue,
2434                           __rte_unused int on)
2435 {
2436         PMD_INIT_FUNC_TRACE();
2437 }
2438
2439 static int
2440 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2441 {
2442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2443         struct i40e_vsi *vsi = pf->main_vsi;
2444         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2445         struct i40e_vsi_vlan_pvid_info info;
2446
2447         memset(&info, 0, sizeof(info));
2448         info.on = on;
2449         if (info.on)
2450                 info.config.pvid = pvid;
2451         else {
2452                 info.config.reject.tagged =
2453                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2454                 info.config.reject.untagged =
2455                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2456         }
2457
2458         return i40e_vsi_vlan_pvid_set(vsi, &info);
2459 }
2460
2461 static int
2462 i40e_dev_led_on(struct rte_eth_dev *dev)
2463 {
2464         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465         uint32_t mode = i40e_led_get(hw);
2466
2467         if (mode == 0)
2468                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2469
2470         return 0;
2471 }
2472
2473 static int
2474 i40e_dev_led_off(struct rte_eth_dev *dev)
2475 {
2476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         uint32_t mode = i40e_led_get(hw);
2478
2479         if (mode != 0)
2480                 i40e_led_set(hw, 0, false);
2481
2482         return 0;
2483 }
2484
2485 static int
2486 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2487 {
2488         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2490
2491         fc_conf->pause_time = pf->fc_conf.pause_time;
2492         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2493         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2494
2495          /* Return current mode according to actual setting*/
2496         switch (hw->fc.current_mode) {
2497         case I40E_FC_FULL:
2498                 fc_conf->mode = RTE_FC_FULL;
2499                 break;
2500         case I40E_FC_TX_PAUSE:
2501                 fc_conf->mode = RTE_FC_TX_PAUSE;
2502                 break;
2503         case I40E_FC_RX_PAUSE:
2504                 fc_conf->mode = RTE_FC_RX_PAUSE;
2505                 break;
2506         case I40E_FC_NONE:
2507         default:
2508                 fc_conf->mode = RTE_FC_NONE;
2509         };
2510
2511         return 0;
2512 }
2513
2514 static int
2515 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2516 {
2517         uint32_t mflcn_reg, fctrl_reg, reg;
2518         uint32_t max_high_water;
2519         uint8_t i, aq_failure;
2520         int err;
2521         struct i40e_hw *hw;
2522         struct i40e_pf *pf;
2523         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2524                 [RTE_FC_NONE] = I40E_FC_NONE,
2525                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2526                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2527                 [RTE_FC_FULL] = I40E_FC_FULL
2528         };
2529
2530         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2531
2532         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2533         if ((fc_conf->high_water > max_high_water) ||
2534                         (fc_conf->high_water < fc_conf->low_water)) {
2535                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2536                         "High_water must <= %d.", max_high_water);
2537                 return -EINVAL;
2538         }
2539
2540         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2542         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2543
2544         pf->fc_conf.pause_time = fc_conf->pause_time;
2545         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2546         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2547
2548         PMD_INIT_FUNC_TRACE();
2549
2550         /* All the link flow control related enable/disable register
2551          * configuration is handle by the F/W
2552          */
2553         err = i40e_set_fc(hw, &aq_failure, true);
2554         if (err < 0)
2555                 return -ENOSYS;
2556
2557         if (i40e_is_40G_device(hw->device_id)) {
2558                 /* Configure flow control refresh threshold,
2559                  * the value for stat_tx_pause_refresh_timer[8]
2560                  * is used for global pause operation.
2561                  */
2562
2563                 I40E_WRITE_REG(hw,
2564                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2565                                pf->fc_conf.pause_time);
2566
2567                 /* configure the timer value included in transmitted pause
2568                  * frame,
2569                  * the value for stat_tx_pause_quanta[8] is used for global
2570                  * pause operation
2571                  */
2572                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2573                                pf->fc_conf.pause_time);
2574
2575                 fctrl_reg = I40E_READ_REG(hw,
2576                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2577
2578                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2579                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2580                 else
2581                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2582
2583                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2584                                fctrl_reg);
2585         } else {
2586                 /* Configure pause time (2 TCs per register) */
2587                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2588                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2589                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2590
2591                 /* Configure flow control refresh threshold value */
2592                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2593                                pf->fc_conf.pause_time / 2);
2594
2595                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2596
2597                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2598                  *depending on configuration
2599                  */
2600                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2601                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2602                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2603                 } else {
2604                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2605                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2606                 }
2607
2608                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2609         }
2610
2611         /* config the water marker both based on the packets and bytes */
2612         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2613                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2614                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2615         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2616                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2617                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2618         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2619                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2620                        << I40E_KILOSHIFT);
2621         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2622                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2623                        << I40E_KILOSHIFT);
2624
2625         I40E_WRITE_FLUSH(hw);
2626
2627         return 0;
2628 }
2629
2630 static int
2631 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2632                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2633 {
2634         PMD_INIT_FUNC_TRACE();
2635
2636         return -ENOSYS;
2637 }
2638
2639 /* Add a MAC address, and update filters */
2640 static void
2641 i40e_macaddr_add(struct rte_eth_dev *dev,
2642                  struct ether_addr *mac_addr,
2643                  __rte_unused uint32_t index,
2644                  uint32_t pool)
2645 {
2646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2647         struct i40e_mac_filter_info mac_filter;
2648         struct i40e_vsi *vsi;
2649         int ret;
2650
2651         /* If VMDQ not enabled or configured, return */
2652         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2653                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2654                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2655                         pool);
2656                 return;
2657         }
2658
2659         if (pool > pf->nb_cfg_vmdq_vsi) {
2660                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2661                                 pool, pf->nb_cfg_vmdq_vsi);
2662                 return;
2663         }
2664
2665         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2666         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2667
2668         if (pool == 0)
2669                 vsi = pf->main_vsi;
2670         else
2671                 vsi = pf->vmdq[pool - 1].vsi;
2672
2673         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2674         if (ret != I40E_SUCCESS) {
2675                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2676                 return;
2677         }
2678 }
2679
2680 /* Remove a MAC address, and update filters */
2681 static void
2682 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2683 {
2684         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2685         struct i40e_vsi *vsi;
2686         struct rte_eth_dev_data *data = dev->data;
2687         struct ether_addr *macaddr;
2688         int ret;
2689         uint32_t i;
2690         uint64_t pool_sel;
2691
2692         macaddr = &(data->mac_addrs[index]);
2693
2694         pool_sel = dev->data->mac_pool_sel[index];
2695
2696         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2697                 if (pool_sel & (1ULL << i)) {
2698                         if (i == 0)
2699                                 vsi = pf->main_vsi;
2700                         else {
2701                                 /* No VMDQ pool enabled or configured */
2702                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2703                                         (i > pf->nb_cfg_vmdq_vsi)) {
2704                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2705                                                         "/configured");
2706                                         return;
2707                                 }
2708                                 vsi = pf->vmdq[i - 1].vsi;
2709                         }
2710                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2711
2712                         if (ret) {
2713                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2714                                 return;
2715                         }
2716                 }
2717         }
2718 }
2719
2720 /* Set perfect match or hash match of MAC and VLAN for a VF */
2721 static int
2722 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2723                  struct rte_eth_mac_filter *filter,
2724                  bool add)
2725 {
2726         struct i40e_hw *hw;
2727         struct i40e_mac_filter_info mac_filter;
2728         struct ether_addr old_mac;
2729         struct ether_addr *new_mac;
2730         struct i40e_pf_vf *vf = NULL;
2731         uint16_t vf_id;
2732         int ret;
2733
2734         if (pf == NULL) {
2735                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2736                 return -EINVAL;
2737         }
2738         hw = I40E_PF_TO_HW(pf);
2739
2740         if (filter == NULL) {
2741                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2742                 return -EINVAL;
2743         }
2744
2745         new_mac = &filter->mac_addr;
2746
2747         if (is_zero_ether_addr(new_mac)) {
2748                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2749                 return -EINVAL;
2750         }
2751
2752         vf_id = filter->dst_id;
2753
2754         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2755                 PMD_DRV_LOG(ERR, "Invalid argument.");
2756                 return -EINVAL;
2757         }
2758         vf = &pf->vfs[vf_id];
2759
2760         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2761                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2762                 return -EINVAL;
2763         }
2764
2765         if (add) {
2766                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2767                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2768                                 ETHER_ADDR_LEN);
2769                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2770                                  ETHER_ADDR_LEN);
2771
2772                 mac_filter.filter_type = filter->filter_type;
2773                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2774                 if (ret != I40E_SUCCESS) {
2775                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2776                         return -1;
2777                 }
2778                 ether_addr_copy(new_mac, &pf->dev_addr);
2779         } else {
2780                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2781                                 ETHER_ADDR_LEN);
2782                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2783                 if (ret != I40E_SUCCESS) {
2784                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2785                         return -1;
2786                 }
2787
2788                 /* Clear device address as it has been removed */
2789                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2790                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2791         }
2792
2793         return 0;
2794 }
2795
2796 /* MAC filter handle */
2797 static int
2798 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2799                 void *arg)
2800 {
2801         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2802         struct rte_eth_mac_filter *filter;
2803         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2804         int ret = I40E_NOT_SUPPORTED;
2805
2806         filter = (struct rte_eth_mac_filter *)(arg);
2807
2808         switch (filter_op) {
2809         case RTE_ETH_FILTER_NOP:
2810                 ret = I40E_SUCCESS;
2811                 break;
2812         case RTE_ETH_FILTER_ADD:
2813                 i40e_pf_disable_irq0(hw);
2814                 if (filter->is_vf)
2815                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2816                 i40e_pf_enable_irq0(hw);
2817                 break;
2818         case RTE_ETH_FILTER_DELETE:
2819                 i40e_pf_disable_irq0(hw);
2820                 if (filter->is_vf)
2821                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2822                 i40e_pf_enable_irq0(hw);
2823                 break;
2824         default:
2825                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2826                 ret = I40E_ERR_PARAM;
2827                 break;
2828         }
2829
2830         return ret;
2831 }
2832
2833 static int
2834 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2835 {
2836         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2837         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2838         int ret;
2839
2840         if (!lut)
2841                 return -EINVAL;
2842
2843         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2844                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2845                                           lut, lut_size);
2846                 if (ret) {
2847                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2848                         return ret;
2849                 }
2850         } else {
2851                 uint32_t *lut_dw = (uint32_t *)lut;
2852                 uint16_t i, lut_size_dw = lut_size / 4;
2853
2854                 for (i = 0; i < lut_size_dw; i++)
2855                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2856         }
2857
2858         return 0;
2859 }
2860
2861 static int
2862 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2863 {
2864         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2865         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2866         int ret;
2867
2868         if (!vsi || !lut)
2869                 return -EINVAL;
2870
2871         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2872                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2873                                           lut, lut_size);
2874                 if (ret) {
2875                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2876                         return ret;
2877                 }
2878         } else {
2879                 uint32_t *lut_dw = (uint32_t *)lut;
2880                 uint16_t i, lut_size_dw = lut_size / 4;
2881
2882                 for (i = 0; i < lut_size_dw; i++)
2883                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2884                 I40E_WRITE_FLUSH(hw);
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int
2891 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2892                          struct rte_eth_rss_reta_entry64 *reta_conf,
2893                          uint16_t reta_size)
2894 {
2895         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2896         uint16_t i, lut_size = pf->hash_lut_size;
2897         uint16_t idx, shift;
2898         uint8_t *lut;
2899         int ret;
2900
2901         if (reta_size != lut_size ||
2902                 reta_size > ETH_RSS_RETA_SIZE_512) {
2903                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2904                         "(%d) doesn't match the number hardware can supported "
2905                                         "(%d)\n", reta_size, lut_size);
2906                 return -EINVAL;
2907         }
2908
2909         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2910         if (!lut) {
2911                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2912                 return -ENOMEM;
2913         }
2914         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2915         if (ret)
2916                 goto out;
2917         for (i = 0; i < reta_size; i++) {
2918                 idx = i / RTE_RETA_GROUP_SIZE;
2919                 shift = i % RTE_RETA_GROUP_SIZE;
2920                 if (reta_conf[idx].mask & (1ULL << shift))
2921                         lut[i] = reta_conf[idx].reta[shift];
2922         }
2923         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2924
2925 out:
2926         rte_free(lut);
2927
2928         return ret;
2929 }
2930
2931 static int
2932 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2933                         struct rte_eth_rss_reta_entry64 *reta_conf,
2934                         uint16_t reta_size)
2935 {
2936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2937         uint16_t i, lut_size = pf->hash_lut_size;
2938         uint16_t idx, shift;
2939         uint8_t *lut;
2940         int ret;
2941
2942         if (reta_size != lut_size ||
2943                 reta_size > ETH_RSS_RETA_SIZE_512) {
2944                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2945                         "(%d) doesn't match the number hardware can supported "
2946                                         "(%d)\n", reta_size, lut_size);
2947                 return -EINVAL;
2948         }
2949
2950         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2951         if (!lut) {
2952                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2953                 return -ENOMEM;
2954         }
2955
2956         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2957         if (ret)
2958                 goto out;
2959         for (i = 0; i < reta_size; i++) {
2960                 idx = i / RTE_RETA_GROUP_SIZE;
2961                 shift = i % RTE_RETA_GROUP_SIZE;
2962                 if (reta_conf[idx].mask & (1ULL << shift))
2963                         reta_conf[idx].reta[shift] = lut[i];
2964         }
2965
2966 out:
2967         rte_free(lut);
2968
2969         return ret;
2970 }
2971
2972 /**
2973  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2974  * @hw:   pointer to the HW structure
2975  * @mem:  pointer to mem struct to fill out
2976  * @size: size of memory requested
2977  * @alignment: what to align the allocation to
2978  **/
2979 enum i40e_status_code
2980 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2981                         struct i40e_dma_mem *mem,
2982                         u64 size,
2983                         u32 alignment)
2984 {
2985         const struct rte_memzone *mz = NULL;
2986         char z_name[RTE_MEMZONE_NAMESIZE];
2987
2988         if (!mem)
2989                 return I40E_ERR_PARAM;
2990
2991         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2992         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2993                                          alignment, RTE_PGSIZE_2M);
2994         if (!mz)
2995                 return I40E_ERR_NO_MEMORY;
2996
2997         mem->size = size;
2998         mem->va = mz->addr;
2999         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3000         mem->zone = (const void *)mz;
3001         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3002                     "%"PRIu64, mz->name, mem->pa);
3003
3004         return I40E_SUCCESS;
3005 }
3006
3007 /**
3008  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3009  * @hw:   pointer to the HW structure
3010  * @mem:  ptr to mem struct to free
3011  **/
3012 enum i40e_status_code
3013 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3014                     struct i40e_dma_mem *mem)
3015 {
3016         if (!mem)
3017                 return I40E_ERR_PARAM;
3018
3019         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3020                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3021                     mem->pa);
3022         rte_memzone_free((const struct rte_memzone *)mem->zone);
3023         mem->zone = NULL;
3024         mem->va = NULL;
3025         mem->pa = (u64)0;
3026
3027         return I40E_SUCCESS;
3028 }
3029
3030 /**
3031  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3032  * @hw:   pointer to the HW structure
3033  * @mem:  pointer to mem struct to fill out
3034  * @size: size of memory requested
3035  **/
3036 enum i40e_status_code
3037 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3038                          struct i40e_virt_mem *mem,
3039                          u32 size)
3040 {
3041         if (!mem)
3042                 return I40E_ERR_PARAM;
3043
3044         mem->size = size;
3045         mem->va = rte_zmalloc("i40e", size, 0);
3046
3047         if (mem->va)
3048                 return I40E_SUCCESS;
3049         else
3050                 return I40E_ERR_NO_MEMORY;
3051 }
3052
3053 /**
3054  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3055  * @hw:   pointer to the HW structure
3056  * @mem:  pointer to mem struct to free
3057  **/
3058 enum i40e_status_code
3059 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3060                      struct i40e_virt_mem *mem)
3061 {
3062         if (!mem)
3063                 return I40E_ERR_PARAM;
3064
3065         rte_free(mem->va);
3066         mem->va = NULL;
3067
3068         return I40E_SUCCESS;
3069 }
3070
3071 void
3072 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3073 {
3074         rte_spinlock_init(&sp->spinlock);
3075 }
3076
3077 void
3078 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3079 {
3080         rte_spinlock_lock(&sp->spinlock);
3081 }
3082
3083 void
3084 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3085 {
3086         rte_spinlock_unlock(&sp->spinlock);
3087 }
3088
3089 void
3090 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3091 {
3092         return;
3093 }
3094
3095 /**
3096  * Get the hardware capabilities, which will be parsed
3097  * and saved into struct i40e_hw.
3098  */
3099 static int
3100 i40e_get_cap(struct i40e_hw *hw)
3101 {
3102         struct i40e_aqc_list_capabilities_element_resp *buf;
3103         uint16_t len, size = 0;
3104         int ret;
3105
3106         /* Calculate a huge enough buff for saving response data temporarily */
3107         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3108                                                 I40E_MAX_CAP_ELE_NUM;
3109         buf = rte_zmalloc("i40e", len, 0);
3110         if (!buf) {
3111                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3112                 return I40E_ERR_NO_MEMORY;
3113         }
3114
3115         /* Get, parse the capabilities and save it to hw */
3116         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3117                         i40e_aqc_opc_list_func_capabilities, NULL);
3118         if (ret != I40E_SUCCESS)
3119                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3120
3121         /* Free the temporary buffer after being used */
3122         rte_free(buf);
3123
3124         return ret;
3125 }
3126
3127 static int
3128 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3129 {
3130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3131         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3132         uint16_t qp_count = 0, vsi_count = 0;
3133
3134         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3135                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3136                 return -EINVAL;
3137         }
3138         /* Add the parameter init for LFC */
3139         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3140         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3141         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3142
3143         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3144         pf->max_num_vsi = hw->func_caps.num_vsis;
3145         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3146         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3147         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3148
3149         /* FDir queue/VSI allocation */
3150         pf->fdir_qp_offset = 0;
3151         if (hw->func_caps.fd) {
3152                 pf->flags |= I40E_FLAG_FDIR;
3153                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3154         } else {
3155                 pf->fdir_nb_qps = 0;
3156         }
3157         qp_count += pf->fdir_nb_qps;
3158         vsi_count += 1;
3159
3160         /* LAN queue/VSI allocation */
3161         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3162         if (!hw->func_caps.rss) {
3163                 pf->lan_nb_qps = 1;
3164         } else {
3165                 pf->flags |= I40E_FLAG_RSS;
3166                 if (hw->mac.type == I40E_MAC_X722)
3167                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3168                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3169         }
3170         qp_count += pf->lan_nb_qps;
3171         vsi_count += 1;
3172
3173         /* VF queue/VSI allocation */
3174         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3175         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3176                 pf->flags |= I40E_FLAG_SRIOV;
3177                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3178                 pf->vf_num = dev->pci_dev->max_vfs;
3179                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3180                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3181                             pf->vf_nb_qps * pf->vf_num);
3182         } else {
3183                 pf->vf_nb_qps = 0;
3184                 pf->vf_num = 0;
3185         }
3186         qp_count += pf->vf_nb_qps * pf->vf_num;
3187         vsi_count += pf->vf_num;
3188
3189         /* VMDq queue/VSI allocation */
3190         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3191         pf->vmdq_nb_qps = 0;
3192         pf->max_nb_vmdq_vsi = 0;
3193         if (hw->func_caps.vmdq) {
3194                 if (qp_count < hw->func_caps.num_tx_qp &&
3195                         vsi_count < hw->func_caps.num_vsis) {
3196                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3197                                 qp_count) / pf->vmdq_nb_qp_max;
3198
3199                         /* Limit the maximum number of VMDq vsi to the maximum
3200                          * ethdev can support
3201                          */
3202                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3203                                 hw->func_caps.num_vsis - vsi_count);
3204                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3205                                 ETH_64_POOLS);
3206                         if (pf->max_nb_vmdq_vsi) {
3207                                 pf->flags |= I40E_FLAG_VMDQ;
3208                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3209                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3210                                             "per VMDQ VSI, in total %u queues",
3211                                             pf->max_nb_vmdq_vsi,
3212                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3213                                             pf->max_nb_vmdq_vsi);
3214                         } else {
3215                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3216                                             "VMDq");
3217                         }
3218                 } else {
3219                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3220                 }
3221         }
3222         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3223         vsi_count += pf->max_nb_vmdq_vsi;
3224
3225         if (hw->func_caps.dcb)
3226                 pf->flags |= I40E_FLAG_DCB;
3227
3228         if (qp_count > hw->func_caps.num_tx_qp) {
3229                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3230                             "the hardware maximum %u", qp_count,
3231                             hw->func_caps.num_tx_qp);
3232                 return -EINVAL;
3233         }
3234         if (vsi_count > hw->func_caps.num_vsis) {
3235                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3236                             "the hardware maximum %u", vsi_count,
3237                             hw->func_caps.num_vsis);
3238                 return -EINVAL;
3239         }
3240
3241         return 0;
3242 }
3243
3244 static int
3245 i40e_pf_get_switch_config(struct i40e_pf *pf)
3246 {
3247         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3248         struct i40e_aqc_get_switch_config_resp *switch_config;
3249         struct i40e_aqc_switch_config_element_resp *element;
3250         uint16_t start_seid = 0, num_reported;
3251         int ret;
3252
3253         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3254                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3255         if (!switch_config) {
3256                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3257                 return -ENOMEM;
3258         }
3259
3260         /* Get the switch configurations */
3261         ret = i40e_aq_get_switch_config(hw, switch_config,
3262                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3263         if (ret != I40E_SUCCESS) {
3264                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3265                 goto fail;
3266         }
3267         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3268         if (num_reported != 1) { /* The number should be 1 */
3269                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3270                 goto fail;
3271         }
3272
3273         /* Parse the switch configuration elements */
3274         element = &(switch_config->element[0]);
3275         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3276                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3277                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3278         } else
3279                 PMD_DRV_LOG(INFO, "Unknown element type");
3280
3281 fail:
3282         rte_free(switch_config);
3283
3284         return ret;
3285 }
3286
3287 static int
3288 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3289                         uint32_t num)
3290 {
3291         struct pool_entry *entry;
3292
3293         if (pool == NULL || num == 0)
3294                 return -EINVAL;
3295
3296         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3297         if (entry == NULL) {
3298                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3299                 return -ENOMEM;
3300         }
3301
3302         /* queue heap initialize */
3303         pool->num_free = num;
3304         pool->num_alloc = 0;
3305         pool->base = base;
3306         LIST_INIT(&pool->alloc_list);
3307         LIST_INIT(&pool->free_list);
3308
3309         /* Initialize element  */
3310         entry->base = 0;
3311         entry->len = num;
3312
3313         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3314         return 0;
3315 }
3316
3317 static void
3318 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3319 {
3320         struct pool_entry *entry;
3321
3322         if (pool == NULL)
3323                 return;
3324
3325         LIST_FOREACH(entry, &pool->alloc_list, next) {
3326                 LIST_REMOVE(entry, next);
3327                 rte_free(entry);
3328         }
3329
3330         LIST_FOREACH(entry, &pool->free_list, next) {
3331                 LIST_REMOVE(entry, next);
3332                 rte_free(entry);
3333         }
3334
3335         pool->num_free = 0;
3336         pool->num_alloc = 0;
3337         pool->base = 0;
3338         LIST_INIT(&pool->alloc_list);
3339         LIST_INIT(&pool->free_list);
3340 }
3341
3342 static int
3343 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3344                        uint32_t base)
3345 {
3346         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3347         uint32_t pool_offset;
3348         int insert;
3349
3350         if (pool == NULL) {
3351                 PMD_DRV_LOG(ERR, "Invalid parameter");
3352                 return -EINVAL;
3353         }
3354
3355         pool_offset = base - pool->base;
3356         /* Lookup in alloc list */
3357         LIST_FOREACH(entry, &pool->alloc_list, next) {
3358                 if (entry->base == pool_offset) {
3359                         valid_entry = entry;
3360                         LIST_REMOVE(entry, next);
3361                         break;
3362                 }
3363         }
3364
3365         /* Not find, return */
3366         if (valid_entry == NULL) {
3367                 PMD_DRV_LOG(ERR, "Failed to find entry");
3368                 return -EINVAL;
3369         }
3370
3371         /**
3372          * Found it, move it to free list  and try to merge.
3373          * In order to make merge easier, always sort it by qbase.
3374          * Find adjacent prev and last entries.
3375          */
3376         prev = next = NULL;
3377         LIST_FOREACH(entry, &pool->free_list, next) {
3378                 if (entry->base > valid_entry->base) {
3379                         next = entry;
3380                         break;
3381                 }
3382                 prev = entry;
3383         }
3384
3385         insert = 0;
3386         /* Try to merge with next one*/
3387         if (next != NULL) {
3388                 /* Merge with next one */
3389                 if (valid_entry->base + valid_entry->len == next->base) {
3390                         next->base = valid_entry->base;
3391                         next->len += valid_entry->len;
3392                         rte_free(valid_entry);
3393                         valid_entry = next;
3394                         insert = 1;
3395                 }
3396         }
3397
3398         if (prev != NULL) {
3399                 /* Merge with previous one */
3400                 if (prev->base + prev->len == valid_entry->base) {
3401                         prev->len += valid_entry->len;
3402                         /* If it merge with next one, remove next node */
3403                         if (insert == 1) {
3404                                 LIST_REMOVE(valid_entry, next);
3405                                 rte_free(valid_entry);
3406                         } else {
3407                                 rte_free(valid_entry);
3408                                 insert = 1;
3409                         }
3410                 }
3411         }
3412
3413         /* Not find any entry to merge, insert */
3414         if (insert == 0) {
3415                 if (prev != NULL)
3416                         LIST_INSERT_AFTER(prev, valid_entry, next);
3417                 else if (next != NULL)
3418                         LIST_INSERT_BEFORE(next, valid_entry, next);
3419                 else /* It's empty list, insert to head */
3420                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3421         }
3422
3423         pool->num_free += valid_entry->len;
3424         pool->num_alloc -= valid_entry->len;
3425
3426         return 0;
3427 }
3428
3429 static int
3430 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3431                        uint16_t num)
3432 {
3433         struct pool_entry *entry, *valid_entry;
3434
3435         if (pool == NULL || num == 0) {
3436                 PMD_DRV_LOG(ERR, "Invalid parameter");
3437                 return -EINVAL;
3438         }
3439
3440         if (pool->num_free < num) {
3441                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3442                             num, pool->num_free);
3443                 return -ENOMEM;
3444         }
3445
3446         valid_entry = NULL;
3447         /* Lookup  in free list and find most fit one */
3448         LIST_FOREACH(entry, &pool->free_list, next) {
3449                 if (entry->len >= num) {
3450                         /* Find best one */
3451                         if (entry->len == num) {
3452                                 valid_entry = entry;
3453                                 break;
3454                         }
3455                         if (valid_entry == NULL || valid_entry->len > entry->len)
3456                                 valid_entry = entry;
3457                 }
3458         }
3459
3460         /* Not find one to satisfy the request, return */
3461         if (valid_entry == NULL) {
3462                 PMD_DRV_LOG(ERR, "No valid entry found");
3463                 return -ENOMEM;
3464         }
3465         /**
3466          * The entry have equal queue number as requested,
3467          * remove it from alloc_list.
3468          */
3469         if (valid_entry->len == num) {
3470                 LIST_REMOVE(valid_entry, next);
3471         } else {
3472                 /**
3473                  * The entry have more numbers than requested,
3474                  * create a new entry for alloc_list and minus its
3475                  * queue base and number in free_list.
3476                  */
3477                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3478                 if (entry == NULL) {
3479                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3480                                     "resource pool");
3481                         return -ENOMEM;
3482                 }
3483                 entry->base = valid_entry->base;
3484                 entry->len = num;
3485                 valid_entry->base += num;
3486                 valid_entry->len -= num;
3487                 valid_entry = entry;
3488         }
3489
3490         /* Insert it into alloc list, not sorted */
3491         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3492
3493         pool->num_free -= valid_entry->len;
3494         pool->num_alloc += valid_entry->len;
3495
3496         return valid_entry->base + pool->base;
3497 }
3498
3499 /**
3500  * bitmap_is_subset - Check whether src2 is subset of src1
3501  **/
3502 static inline int
3503 bitmap_is_subset(uint8_t src1, uint8_t src2)
3504 {
3505         return !((src1 ^ src2) & src2);
3506 }
3507
3508 static enum i40e_status_code
3509 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3510 {
3511         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3512
3513         /* If DCB is not supported, only default TC is supported */
3514         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3515                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3516                 return I40E_NOT_SUPPORTED;
3517         }
3518
3519         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3520                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3521                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3522                             enabled_tcmap);
3523                 return I40E_NOT_SUPPORTED;
3524         }
3525         return I40E_SUCCESS;
3526 }
3527
3528 int
3529 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3530                                 struct i40e_vsi_vlan_pvid_info *info)
3531 {
3532         struct i40e_hw *hw;
3533         struct i40e_vsi_context ctxt;
3534         uint8_t vlan_flags = 0;
3535         int ret;
3536
3537         if (vsi == NULL || info == NULL) {
3538                 PMD_DRV_LOG(ERR, "invalid parameters");
3539                 return I40E_ERR_PARAM;
3540         }
3541
3542         if (info->on) {
3543                 vsi->info.pvid = info->config.pvid;
3544                 /**
3545                  * If insert pvid is enabled, only tagged pkts are
3546                  * allowed to be sent out.
3547                  */
3548                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3549                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3550         } else {
3551                 vsi->info.pvid = 0;
3552                 if (info->config.reject.tagged == 0)
3553                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3554
3555                 if (info->config.reject.untagged == 0)
3556                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3557         }
3558         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3559                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3560         vsi->info.port_vlan_flags |= vlan_flags;
3561         vsi->info.valid_sections =
3562                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3563         memset(&ctxt, 0, sizeof(ctxt));
3564         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3565         ctxt.seid = vsi->seid;
3566
3567         hw = I40E_VSI_TO_HW(vsi);
3568         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3569         if (ret != I40E_SUCCESS)
3570                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3571
3572         return ret;
3573 }
3574
3575 static int
3576 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3577 {
3578         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3579         int i, ret;
3580         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3581
3582         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3583         if (ret != I40E_SUCCESS)
3584                 return ret;
3585
3586         if (!vsi->seid) {
3587                 PMD_DRV_LOG(ERR, "seid not valid");
3588                 return -EINVAL;
3589         }
3590
3591         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3592         tc_bw_data.tc_valid_bits = enabled_tcmap;
3593         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3594                 tc_bw_data.tc_bw_credits[i] =
3595                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3596
3597         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3598         if (ret != I40E_SUCCESS) {
3599                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3600                 return ret;
3601         }
3602
3603         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3604                                         sizeof(vsi->info.qs_handle));
3605         return I40E_SUCCESS;
3606 }
3607
3608 static enum i40e_status_code
3609 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3610                                  struct i40e_aqc_vsi_properties_data *info,
3611                                  uint8_t enabled_tcmap)
3612 {
3613         enum i40e_status_code ret;
3614         int i, total_tc = 0;
3615         uint16_t qpnum_per_tc, bsf, qp_idx;
3616
3617         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3618         if (ret != I40E_SUCCESS)
3619                 return ret;
3620
3621         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3622                 if (enabled_tcmap & (1 << i))
3623                         total_tc++;
3624         vsi->enabled_tc = enabled_tcmap;
3625
3626         /* Number of queues per enabled TC */
3627         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3628         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3629         bsf = rte_bsf32(qpnum_per_tc);
3630
3631         /* Adjust the queue number to actual queues that can be applied */
3632         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3633                 vsi->nb_qps = qpnum_per_tc * total_tc;
3634
3635         /**
3636          * Configure TC and queue mapping parameters, for enabled TC,
3637          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3638          * default queue will serve it.
3639          */
3640         qp_idx = 0;
3641         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3642                 if (vsi->enabled_tc & (1 << i)) {
3643                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3644                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3645                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3646                         qp_idx += qpnum_per_tc;
3647                 } else
3648                         info->tc_mapping[i] = 0;
3649         }
3650
3651         /* Associate queue number with VSI */
3652         if (vsi->type == I40E_VSI_SRIOV) {
3653                 info->mapping_flags |=
3654                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3655                 for (i = 0; i < vsi->nb_qps; i++)
3656                         info->queue_mapping[i] =
3657                                 rte_cpu_to_le_16(vsi->base_queue + i);
3658         } else {
3659                 info->mapping_flags |=
3660                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3661                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3662         }
3663         info->valid_sections |=
3664                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3665
3666         return I40E_SUCCESS;
3667 }
3668
3669 static int
3670 i40e_veb_release(struct i40e_veb *veb)
3671 {
3672         struct i40e_vsi *vsi;
3673         struct i40e_hw *hw;
3674
3675         if (veb == NULL || veb->associate_vsi == NULL)
3676                 return -EINVAL;
3677
3678         if (!TAILQ_EMPTY(&veb->head)) {
3679                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3680                 return -EACCES;
3681         }
3682
3683         vsi = veb->associate_vsi;
3684         hw = I40E_VSI_TO_HW(vsi);
3685
3686         vsi->uplink_seid = veb->uplink_seid;
3687         i40e_aq_delete_element(hw, veb->seid, NULL);
3688         rte_free(veb);
3689         vsi->veb = NULL;
3690         return I40E_SUCCESS;
3691 }
3692
3693 /* Setup a veb */
3694 static struct i40e_veb *
3695 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3696 {
3697         struct i40e_veb *veb;
3698         int ret;
3699         struct i40e_hw *hw;
3700
3701         if (NULL == pf || vsi == NULL) {
3702                 PMD_DRV_LOG(ERR, "veb setup failed, "
3703                             "associated VSI shouldn't null");
3704                 return NULL;
3705         }
3706         hw = I40E_PF_TO_HW(pf);
3707
3708         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3709         if (!veb) {
3710                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3711                 goto fail;
3712         }
3713
3714         veb->associate_vsi = vsi;
3715         TAILQ_INIT(&veb->head);
3716         veb->uplink_seid = vsi->uplink_seid;
3717
3718         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3719                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3720
3721         if (ret != I40E_SUCCESS) {
3722                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3723                             hw->aq.asq_last_status);
3724                 goto fail;
3725         }
3726
3727         /* get statistics index */
3728         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3729                                 &veb->stats_idx, NULL, NULL, NULL);
3730         if (ret != I40E_SUCCESS) {
3731                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3732                             hw->aq.asq_last_status);
3733                 goto fail;
3734         }
3735
3736         /* Get VEB bandwidth, to be implemented */
3737         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3738         vsi->uplink_seid = veb->seid;
3739
3740         return veb;
3741 fail:
3742         rte_free(veb);
3743         return NULL;
3744 }
3745
3746 int
3747 i40e_vsi_release(struct i40e_vsi *vsi)
3748 {
3749         struct i40e_pf *pf;
3750         struct i40e_hw *hw;
3751         struct i40e_vsi_list *vsi_list;
3752         int ret;
3753         struct i40e_mac_filter *f;
3754
3755         if (!vsi)
3756                 return I40E_SUCCESS;
3757
3758         pf = I40E_VSI_TO_PF(vsi);
3759         hw = I40E_VSI_TO_HW(vsi);
3760
3761         /* VSI has child to attach, release child first */
3762         if (vsi->veb) {
3763                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3764                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3765                                 return -1;
3766                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3767                 }
3768                 i40e_veb_release(vsi->veb);
3769         }
3770
3771         /* Remove all macvlan filters of the VSI */
3772         i40e_vsi_remove_all_macvlan_filter(vsi);
3773         TAILQ_FOREACH(f, &vsi->mac_list, next)
3774                 rte_free(f);
3775
3776         if (vsi->type != I40E_VSI_MAIN) {
3777                 /* Remove vsi from parent's sibling list */
3778                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3779                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3780                         return I40E_ERR_PARAM;
3781                 }
3782                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3783                                 &vsi->sib_vsi_list, list);
3784
3785                 /* Remove all switch element of the VSI */
3786                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3787                 if (ret != I40E_SUCCESS)
3788                         PMD_DRV_LOG(ERR, "Failed to delete element");
3789         }
3790         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3791
3792         if (vsi->type != I40E_VSI_SRIOV)
3793                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3794         rte_free(vsi);
3795
3796         return I40E_SUCCESS;
3797 }
3798
3799 static int
3800 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3801 {
3802         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3803         struct i40e_aqc_remove_macvlan_element_data def_filter;
3804         struct i40e_mac_filter_info filter;
3805         int ret;
3806
3807         if (vsi->type != I40E_VSI_MAIN)
3808                 return I40E_ERR_CONFIG;
3809         memset(&def_filter, 0, sizeof(def_filter));
3810         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3811                                         ETH_ADDR_LEN);
3812         def_filter.vlan_tag = 0;
3813         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3814                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3815         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3816         if (ret != I40E_SUCCESS) {
3817                 struct i40e_mac_filter *f;
3818                 struct ether_addr *mac;
3819
3820                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3821                             "macvlan filter");
3822                 /* It needs to add the permanent mac into mac list */
3823                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3824                 if (f == NULL) {
3825                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3826                         return I40E_ERR_NO_MEMORY;
3827                 }
3828                 mac = &f->mac_info.mac_addr;
3829                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3830                                 ETH_ADDR_LEN);
3831                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3832                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3833                 vsi->mac_num++;
3834
3835                 return ret;
3836         }
3837         (void)rte_memcpy(&filter.mac_addr,
3838                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3839         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3840         return i40e_vsi_add_mac(vsi, &filter);
3841 }
3842
3843 #define I40E_3_BIT_MASK     0x7
3844 /*
3845  * i40e_vsi_get_bw_config - Query VSI BW Information
3846  * @vsi: the VSI to be queried
3847  *
3848  * Returns 0 on success, negative value on failure
3849  */
3850 static enum i40e_status_code
3851 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3852 {
3853         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3854         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3855         struct i40e_hw *hw = &vsi->adapter->hw;
3856         i40e_status ret;
3857         int i;
3858         uint32_t bw_max;
3859
3860         memset(&bw_config, 0, sizeof(bw_config));
3861         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3862         if (ret != I40E_SUCCESS) {
3863                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3864                             hw->aq.asq_last_status);
3865                 return ret;
3866         }
3867
3868         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3869         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3870                                         &ets_sla_config, NULL);
3871         if (ret != I40E_SUCCESS) {
3872                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3873                             "configuration %u", hw->aq.asq_last_status);
3874                 return ret;
3875         }
3876
3877         /* store and print out BW info */
3878         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3879         vsi->bw_info.bw_max = bw_config.max_bw;
3880         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3881         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3882         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3883                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3884                      I40E_16_BIT_WIDTH);
3885         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3886                 vsi->bw_info.bw_ets_share_credits[i] =
3887                                 ets_sla_config.share_credits[i];
3888                 vsi->bw_info.bw_ets_credits[i] =
3889                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3890                 /* 4 bits per TC, 4th bit is reserved */
3891                 vsi->bw_info.bw_ets_max[i] =
3892                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3893                                   I40E_3_BIT_MASK);
3894                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3895                             vsi->bw_info.bw_ets_share_credits[i]);
3896                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3897                             vsi->bw_info.bw_ets_credits[i]);
3898                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3899                             vsi->bw_info.bw_ets_max[i]);
3900         }
3901
3902         return I40E_SUCCESS;
3903 }
3904
3905 /* Setup a VSI */
3906 struct i40e_vsi *
3907 i40e_vsi_setup(struct i40e_pf *pf,
3908                enum i40e_vsi_type type,
3909                struct i40e_vsi *uplink_vsi,
3910                uint16_t user_param)
3911 {
3912         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3913         struct i40e_vsi *vsi;
3914         struct i40e_mac_filter_info filter;
3915         int ret;
3916         struct i40e_vsi_context ctxt;
3917         struct ether_addr broadcast =
3918                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3919
3920         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3921                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3922                             "VSI link shouldn't be NULL");
3923                 return NULL;
3924         }
3925
3926         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3927                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3928                             "uplink VSI should be NULL");
3929                 return NULL;
3930         }
3931
3932         /* If uplink vsi didn't setup VEB, create one first */
3933         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3934                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3935
3936                 if (NULL == uplink_vsi->veb) {
3937                         PMD_DRV_LOG(ERR, "VEB setup failed");
3938                         return NULL;
3939                 }
3940         }
3941
3942         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3943         if (!vsi) {
3944                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3945                 return NULL;
3946         }
3947         TAILQ_INIT(&vsi->mac_list);
3948         vsi->type = type;
3949         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3950         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3951         vsi->parent_vsi = uplink_vsi;
3952         vsi->user_param = user_param;
3953         /* Allocate queues */
3954         switch (vsi->type) {
3955         case I40E_VSI_MAIN  :
3956                 vsi->nb_qps = pf->lan_nb_qps;
3957                 break;
3958         case I40E_VSI_SRIOV :
3959                 vsi->nb_qps = pf->vf_nb_qps;
3960                 break;
3961         case I40E_VSI_VMDQ2:
3962                 vsi->nb_qps = pf->vmdq_nb_qps;
3963                 break;
3964         case I40E_VSI_FDIR:
3965                 vsi->nb_qps = pf->fdir_nb_qps;
3966                 break;
3967         default:
3968                 goto fail_mem;
3969         }
3970         /*
3971          * The filter status descriptor is reported in rx queue 0,
3972          * while the tx queue for fdir filter programming has no
3973          * such constraints, can be non-zero queues.
3974          * To simplify it, choose FDIR vsi use queue 0 pair.
3975          * To make sure it will use queue 0 pair, queue allocation
3976          * need be done before this function is called
3977          */
3978         if (type != I40E_VSI_FDIR) {
3979                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3980                         if (ret < 0) {
3981                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3982                                                 vsi->seid, ret);
3983                                 goto fail_mem;
3984                         }
3985                         vsi->base_queue = ret;
3986         } else
3987                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3988
3989         /* VF has MSIX interrupt in VF range, don't allocate here */
3990         if (type == I40E_VSI_MAIN) {
3991                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3992                                           RTE_MIN(vsi->nb_qps,
3993                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3994                 if (ret < 0) {
3995                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3996                                     vsi->seid, ret);
3997                         goto fail_queue_alloc;
3998                 }
3999                 vsi->msix_intr = ret;
4000                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4001         } else if (type != I40E_VSI_SRIOV) {
4002                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4003                 if (ret < 0) {
4004                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4005                         goto fail_queue_alloc;
4006                 }
4007                 vsi->msix_intr = ret;
4008                 vsi->nb_msix = 1;
4009         } else {
4010                 vsi->msix_intr = 0;
4011                 vsi->nb_msix = 0;
4012         }
4013
4014         /* Add VSI */
4015         if (type == I40E_VSI_MAIN) {
4016                 /* For main VSI, no need to add since it's default one */
4017                 vsi->uplink_seid = pf->mac_seid;
4018                 vsi->seid = pf->main_vsi_seid;
4019                 /* Bind queues with specific MSIX interrupt */
4020                 /**
4021                  * Needs 2 interrupt at least, one for misc cause which will
4022                  * enabled from OS side, Another for queues binding the
4023                  * interrupt from device side only.
4024                  */
4025
4026                 /* Get default VSI parameters from hardware */
4027                 memset(&ctxt, 0, sizeof(ctxt));
4028                 ctxt.seid = vsi->seid;
4029                 ctxt.pf_num = hw->pf_id;
4030                 ctxt.uplink_seid = vsi->uplink_seid;
4031                 ctxt.vf_num = 0;
4032                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4033                 if (ret != I40E_SUCCESS) {
4034                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4035                         goto fail_msix_alloc;
4036                 }
4037                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4038                         sizeof(struct i40e_aqc_vsi_properties_data));
4039                 vsi->vsi_id = ctxt.vsi_number;
4040                 vsi->info.valid_sections = 0;
4041
4042                 /* Configure tc, enabled TC0 only */
4043                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4044                         I40E_SUCCESS) {
4045                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4046                         goto fail_msix_alloc;
4047                 }
4048
4049                 /* TC, queue mapping */
4050                 memset(&ctxt, 0, sizeof(ctxt));
4051                 vsi->info.valid_sections |=
4052                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4053                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4054                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4055                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4056                         sizeof(struct i40e_aqc_vsi_properties_data));
4057                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4058                                                 I40E_DEFAULT_TCMAP);
4059                 if (ret != I40E_SUCCESS) {
4060                         PMD_DRV_LOG(ERR, "Failed to configure "
4061                                     "TC queue mapping");
4062                         goto fail_msix_alloc;
4063                 }
4064                 ctxt.seid = vsi->seid;
4065                 ctxt.pf_num = hw->pf_id;
4066                 ctxt.uplink_seid = vsi->uplink_seid;
4067                 ctxt.vf_num = 0;
4068
4069                 /* Update VSI parameters */
4070                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4071                 if (ret != I40E_SUCCESS) {
4072                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4073                         goto fail_msix_alloc;
4074                 }
4075
4076                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4077                                                 sizeof(vsi->info.tc_mapping));
4078                 (void)rte_memcpy(&vsi->info.queue_mapping,
4079                                 &ctxt.info.queue_mapping,
4080                         sizeof(vsi->info.queue_mapping));
4081                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4082                 vsi->info.valid_sections = 0;
4083
4084                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4085                                 ETH_ADDR_LEN);
4086
4087                 /**
4088                  * Updating default filter settings are necessary to prevent
4089                  * reception of tagged packets.
4090                  * Some old firmware configurations load a default macvlan
4091                  * filter which accepts both tagged and untagged packets.
4092                  * The updating is to use a normal filter instead if needed.
4093                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4094                  * The firmware with correct configurations load the default
4095                  * macvlan filter which is expected and cannot be removed.
4096                  */
4097                 i40e_update_default_filter_setting(vsi);
4098                 i40e_config_qinq(hw, vsi);
4099         } else if (type == I40E_VSI_SRIOV) {
4100                 memset(&ctxt, 0, sizeof(ctxt));
4101                 /**
4102                  * For other VSI, the uplink_seid equals to uplink VSI's
4103                  * uplink_seid since they share same VEB
4104                  */
4105                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4106                 ctxt.pf_num = hw->pf_id;
4107                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4108                 ctxt.uplink_seid = vsi->uplink_seid;
4109                 ctxt.connection_type = 0x1;
4110                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4111
4112                 /**
4113                  * Do not configure switch ID to enable VEB switch by
4114                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4115                  * if the source mac address of packet sent from VF is not
4116                  * listed in the VEB's mac table, the VEB will switch the
4117                  * packet back to the VF. Need to enable it when HW issue
4118                  * is fixed.
4119                  */
4120
4121                 /* Configure port/vlan */
4122                 ctxt.info.valid_sections |=
4123                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4124                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4125                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4126                                                 I40E_DEFAULT_TCMAP);
4127                 if (ret != I40E_SUCCESS) {
4128                         PMD_DRV_LOG(ERR, "Failed to configure "
4129                                     "TC queue mapping");
4130                         goto fail_msix_alloc;
4131                 }
4132                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4133                 ctxt.info.valid_sections |=
4134                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4135                 /**
4136                  * Since VSI is not created yet, only configure parameter,
4137                  * will add vsi below.
4138                  */
4139
4140                 i40e_config_qinq(hw, vsi);
4141         } else if (type == I40E_VSI_VMDQ2) {
4142                 memset(&ctxt, 0, sizeof(ctxt));
4143                 /*
4144                  * For other VSI, the uplink_seid equals to uplink VSI's
4145                  * uplink_seid since they share same VEB
4146                  */
4147                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4148                 ctxt.pf_num = hw->pf_id;
4149                 ctxt.vf_num = 0;
4150                 ctxt.uplink_seid = vsi->uplink_seid;
4151                 ctxt.connection_type = 0x1;
4152                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4153
4154                 ctxt.info.valid_sections |=
4155                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4156                 /* user_param carries flag to enable loop back */
4157                 if (user_param) {
4158                         ctxt.info.switch_id =
4159                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4160                         ctxt.info.switch_id |=
4161                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4162                 }
4163
4164                 /* Configure port/vlan */
4165                 ctxt.info.valid_sections |=
4166                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4167                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4168                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4169                                                 I40E_DEFAULT_TCMAP);
4170                 if (ret != I40E_SUCCESS) {
4171                         PMD_DRV_LOG(ERR, "Failed to configure "
4172                                         "TC queue mapping");
4173                         goto fail_msix_alloc;
4174                 }
4175                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4176                 ctxt.info.valid_sections |=
4177                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4178         } else if (type == I40E_VSI_FDIR) {
4179                 memset(&ctxt, 0, sizeof(ctxt));
4180                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4181                 ctxt.pf_num = hw->pf_id;
4182                 ctxt.vf_num = 0;
4183                 ctxt.uplink_seid = vsi->uplink_seid;
4184                 ctxt.connection_type = 0x1;     /* regular data port */
4185                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4186                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4187                                                 I40E_DEFAULT_TCMAP);
4188                 if (ret != I40E_SUCCESS) {
4189                         PMD_DRV_LOG(ERR, "Failed to configure "
4190                                         "TC queue mapping.");
4191                         goto fail_msix_alloc;
4192                 }
4193                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4194                 ctxt.info.valid_sections |=
4195                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4196         } else {
4197                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4198                 goto fail_msix_alloc;
4199         }
4200
4201         if (vsi->type != I40E_VSI_MAIN) {
4202                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4203                 if (ret != I40E_SUCCESS) {
4204                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4205                                     hw->aq.asq_last_status);
4206                         goto fail_msix_alloc;
4207                 }
4208                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4209                 vsi->info.valid_sections = 0;
4210                 vsi->seid = ctxt.seid;
4211                 vsi->vsi_id = ctxt.vsi_number;
4212                 vsi->sib_vsi_list.vsi = vsi;
4213                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4214                                 &vsi->sib_vsi_list, list);
4215         }
4216
4217         /* MAC/VLAN configuration */
4218         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4219         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4220
4221         ret = i40e_vsi_add_mac(vsi, &filter);
4222         if (ret != I40E_SUCCESS) {
4223                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4224                 goto fail_msix_alloc;
4225         }
4226
4227         /* Get VSI BW information */
4228         i40e_vsi_get_bw_config(vsi);
4229         return vsi;
4230 fail_msix_alloc:
4231         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4232 fail_queue_alloc:
4233         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4234 fail_mem:
4235         rte_free(vsi);
4236         return NULL;
4237 }
4238
4239 /* Configure vlan stripping on or off */
4240 int
4241 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4242 {
4243         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4244         struct i40e_vsi_context ctxt;
4245         uint8_t vlan_flags;
4246         int ret = I40E_SUCCESS;
4247
4248         /* Check if it has been already on or off */
4249         if (vsi->info.valid_sections &
4250                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4251                 if (on) {
4252                         if ((vsi->info.port_vlan_flags &
4253                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4254                                 return 0; /* already on */
4255                 } else {
4256                         if ((vsi->info.port_vlan_flags &
4257                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4258                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4259                                 return 0; /* already off */
4260                 }
4261         }
4262
4263         if (on)
4264                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4265         else
4266                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4267         vsi->info.valid_sections =
4268                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4269         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4270         vsi->info.port_vlan_flags |= vlan_flags;
4271         ctxt.seid = vsi->seid;
4272         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4273         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4274         if (ret)
4275                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4276                             on ? "enable" : "disable");
4277
4278         return ret;
4279 }
4280
4281 static int
4282 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4283 {
4284         struct rte_eth_dev_data *data = dev->data;
4285         int ret;
4286
4287         /* Apply vlan offload setting */
4288         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4289
4290         /* Apply double-vlan setting, not implemented yet */
4291
4292         /* Apply pvid setting */
4293         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4294                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4295         if (ret)
4296                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4297
4298         return ret;
4299 }
4300
4301 static int
4302 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4303 {
4304         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4305
4306         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4307 }
4308
4309 static int
4310 i40e_update_flow_control(struct i40e_hw *hw)
4311 {
4312 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4313         struct i40e_link_status link_status;
4314         uint32_t rxfc = 0, txfc = 0, reg;
4315         uint8_t an_info;
4316         int ret;
4317
4318         memset(&link_status, 0, sizeof(link_status));
4319         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4320         if (ret != I40E_SUCCESS) {
4321                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4322                 goto write_reg; /* Disable flow control */
4323         }
4324
4325         an_info = hw->phy.link_info.an_info;
4326         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4327                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4328                 ret = I40E_ERR_NOT_READY;
4329                 goto write_reg; /* Disable flow control */
4330         }
4331         /**
4332          * If link auto negotiation is enabled, flow control needs to
4333          * be configured according to it
4334          */
4335         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4336         case I40E_LINK_PAUSE_RXTX:
4337                 rxfc = 1;
4338                 txfc = 1;
4339                 hw->fc.current_mode = I40E_FC_FULL;
4340                 break;
4341         case I40E_AQ_LINK_PAUSE_RX:
4342                 rxfc = 1;
4343                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4344                 break;
4345         case I40E_AQ_LINK_PAUSE_TX:
4346                 txfc = 1;
4347                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4348                 break;
4349         default:
4350                 hw->fc.current_mode = I40E_FC_NONE;
4351                 break;
4352         }
4353
4354 write_reg:
4355         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4356                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4357         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4358         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4359         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4360         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4361
4362         return ret;
4363 }
4364
4365 /* PF setup */
4366 static int
4367 i40e_pf_setup(struct i40e_pf *pf)
4368 {
4369         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4370         struct i40e_filter_control_settings settings;
4371         struct i40e_vsi *vsi;
4372         int ret;
4373
4374         /* Clear all stats counters */
4375         pf->offset_loaded = FALSE;
4376         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4377         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4378
4379         ret = i40e_pf_get_switch_config(pf);
4380         if (ret != I40E_SUCCESS) {
4381                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4382                 return ret;
4383         }
4384         if (pf->flags & I40E_FLAG_FDIR) {
4385                 /* make queue allocated first, let FDIR use queue pair 0*/
4386                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4387                 if (ret != I40E_FDIR_QUEUE_ID) {
4388                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4389                                     " ret =%d", ret);
4390                         pf->flags &= ~I40E_FLAG_FDIR;
4391                 }
4392         }
4393         /*  main VSI setup */
4394         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4395         if (!vsi) {
4396                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4397                 return I40E_ERR_NOT_READY;
4398         }
4399         pf->main_vsi = vsi;
4400
4401         /* Configure filter control */
4402         memset(&settings, 0, sizeof(settings));
4403         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4404                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4405         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4406                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4407         else {
4408                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4409                                                 hw->func_caps.rss_table_size);
4410                 return I40E_ERR_PARAM;
4411         }
4412         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4413                         "size: %u\n", hw->func_caps.rss_table_size);
4414         pf->hash_lut_size = hw->func_caps.rss_table_size;
4415
4416         /* Enable ethtype and macvlan filters */
4417         settings.enable_ethtype = TRUE;
4418         settings.enable_macvlan = TRUE;
4419         ret = i40e_set_filter_control(hw, &settings);
4420         if (ret)
4421                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4422                                                                 ret);
4423
4424         /* Update flow control according to the auto negotiation */
4425         i40e_update_flow_control(hw);
4426
4427         return I40E_SUCCESS;
4428 }
4429
4430 int
4431 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4432 {
4433         uint32_t reg;
4434         uint16_t j;
4435
4436         /**
4437          * Set or clear TX Queue Disable flags,
4438          * which is required by hardware.
4439          */
4440         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4441         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4442
4443         /* Wait until the request is finished */
4444         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4445                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4446                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4447                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4448                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4449                                                         & 0x1))) {
4450                         break;
4451                 }
4452         }
4453         if (on) {
4454                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4455                         return I40E_SUCCESS; /* already on, skip next steps */
4456
4457                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4458                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4459         } else {
4460                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4461                         return I40E_SUCCESS; /* already off, skip next steps */
4462                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4463         }
4464         /* Write the register */
4465         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4466         /* Check the result */
4467         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4468                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4469                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4470                 if (on) {
4471                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4472                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4473                                 break;
4474                 } else {
4475                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4476                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4477                                 break;
4478                 }
4479         }
4480         /* Check if it is timeout */
4481         if (j >= I40E_CHK_Q_ENA_COUNT) {
4482                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4483                             (on ? "enable" : "disable"), q_idx);
4484                 return I40E_ERR_TIMEOUT;
4485         }
4486
4487         return I40E_SUCCESS;
4488 }
4489
4490 /* Swith on or off the tx queues */
4491 static int
4492 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4493 {
4494         struct rte_eth_dev_data *dev_data = pf->dev_data;
4495         struct i40e_tx_queue *txq;
4496         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4497         uint16_t i;
4498         int ret;
4499
4500         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4501                 txq = dev_data->tx_queues[i];
4502                 /* Don't operate the queue if not configured or
4503                  * if starting only per queue */
4504                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4505                         continue;
4506                 if (on)
4507                         ret = i40e_dev_tx_queue_start(dev, i);
4508                 else
4509                         ret = i40e_dev_tx_queue_stop(dev, i);
4510                 if ( ret != I40E_SUCCESS)
4511                         return ret;
4512         }
4513
4514         return I40E_SUCCESS;
4515 }
4516
4517 int
4518 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4519 {
4520         uint32_t reg;
4521         uint16_t j;
4522
4523         /* Wait until the request is finished */
4524         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4525                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4526                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4527                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4528                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4529                         break;
4530         }
4531
4532         if (on) {
4533                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4534                         return I40E_SUCCESS; /* Already on, skip next steps */
4535                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4536         } else {
4537                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4538                         return I40E_SUCCESS; /* Already off, skip next steps */
4539                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4540         }
4541
4542         /* Write the register */
4543         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4544         /* Check the result */
4545         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4546                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4547                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4548                 if (on) {
4549                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4550                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4551                                 break;
4552                 } else {
4553                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4554                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4555                                 break;
4556                 }
4557         }
4558
4559         /* Check if it is timeout */
4560         if (j >= I40E_CHK_Q_ENA_COUNT) {
4561                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4562                             (on ? "enable" : "disable"), q_idx);
4563                 return I40E_ERR_TIMEOUT;
4564         }
4565
4566         return I40E_SUCCESS;
4567 }
4568 /* Switch on or off the rx queues */
4569 static int
4570 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4571 {
4572         struct rte_eth_dev_data *dev_data = pf->dev_data;
4573         struct i40e_rx_queue *rxq;
4574         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4575         uint16_t i;
4576         int ret;
4577
4578         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4579                 rxq = dev_data->rx_queues[i];
4580                 /* Don't operate the queue if not configured or
4581                  * if starting only per queue */
4582                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4583                         continue;
4584                 if (on)
4585                         ret = i40e_dev_rx_queue_start(dev, i);
4586                 else
4587                         ret = i40e_dev_rx_queue_stop(dev, i);
4588                 if (ret != I40E_SUCCESS)
4589                         return ret;
4590         }
4591
4592         return I40E_SUCCESS;
4593 }
4594
4595 /* Switch on or off all the rx/tx queues */
4596 int
4597 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4598 {
4599         int ret;
4600
4601         if (on) {
4602                 /* enable rx queues before enabling tx queues */
4603                 ret = i40e_dev_switch_rx_queues(pf, on);
4604                 if (ret) {
4605                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4606                         return ret;
4607                 }
4608                 ret = i40e_dev_switch_tx_queues(pf, on);
4609         } else {
4610                 /* Stop tx queues before stopping rx queues */
4611                 ret = i40e_dev_switch_tx_queues(pf, on);
4612                 if (ret) {
4613                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4614                         return ret;
4615                 }
4616                 ret = i40e_dev_switch_rx_queues(pf, on);
4617         }
4618
4619         return ret;
4620 }
4621
4622 /* Initialize VSI for TX */
4623 static int
4624 i40e_dev_tx_init(struct i40e_pf *pf)
4625 {
4626         struct rte_eth_dev_data *data = pf->dev_data;
4627         uint16_t i;
4628         uint32_t ret = I40E_SUCCESS;
4629         struct i40e_tx_queue *txq;
4630
4631         for (i = 0; i < data->nb_tx_queues; i++) {
4632                 txq = data->tx_queues[i];
4633                 if (!txq || !txq->q_set)
4634                         continue;
4635                 ret = i40e_tx_queue_init(txq);
4636                 if (ret != I40E_SUCCESS)
4637                         break;
4638         }
4639         if (ret == I40E_SUCCESS)
4640                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4641                                      ->eth_dev);
4642
4643         return ret;
4644 }
4645
4646 /* Initialize VSI for RX */
4647 static int
4648 i40e_dev_rx_init(struct i40e_pf *pf)
4649 {
4650         struct rte_eth_dev_data *data = pf->dev_data;
4651         int ret = I40E_SUCCESS;
4652         uint16_t i;
4653         struct i40e_rx_queue *rxq;
4654
4655         i40e_pf_config_mq_rx(pf);
4656         for (i = 0; i < data->nb_rx_queues; i++) {
4657                 rxq = data->rx_queues[i];
4658                 if (!rxq || !rxq->q_set)
4659                         continue;
4660
4661                 ret = i40e_rx_queue_init(rxq);
4662                 if (ret != I40E_SUCCESS) {
4663                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4664                                     "initialization");
4665                         break;
4666                 }
4667         }
4668         if (ret == I40E_SUCCESS)
4669                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4670                                      ->eth_dev);
4671
4672         return ret;
4673 }
4674
4675 static int
4676 i40e_dev_rxtx_init(struct i40e_pf *pf)
4677 {
4678         int err;
4679
4680         err = i40e_dev_tx_init(pf);
4681         if (err) {
4682                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4683                 return err;
4684         }
4685         err = i40e_dev_rx_init(pf);
4686         if (err) {
4687                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4688                 return err;
4689         }
4690
4691         return err;
4692 }
4693
4694 static int
4695 i40e_vmdq_setup(struct rte_eth_dev *dev)
4696 {
4697         struct rte_eth_conf *conf = &dev->data->dev_conf;
4698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4699         int i, err, conf_vsis, j, loop;
4700         struct i40e_vsi *vsi;
4701         struct i40e_vmdq_info *vmdq_info;
4702         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4703         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4704
4705         /*
4706          * Disable interrupt to avoid message from VF. Furthermore, it will
4707          * avoid race condition in VSI creation/destroy.
4708          */
4709         i40e_pf_disable_irq0(hw);
4710
4711         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4712                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4713                 return -ENOTSUP;
4714         }
4715
4716         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4717         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4718                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4719                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4720                         pf->max_nb_vmdq_vsi);
4721                 return -ENOTSUP;
4722         }
4723
4724         if (pf->vmdq != NULL) {
4725                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4726                 return 0;
4727         }
4728
4729         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4730                                 sizeof(*vmdq_info) * conf_vsis, 0);
4731
4732         if (pf->vmdq == NULL) {
4733                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4734                 return -ENOMEM;
4735         }
4736
4737         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4738
4739         /* Create VMDQ VSI */
4740         for (i = 0; i < conf_vsis; i++) {
4741                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4742                                 vmdq_conf->enable_loop_back);
4743                 if (vsi == NULL) {
4744                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4745                         err = -1;
4746                         goto err_vsi_setup;
4747                 }
4748                 vmdq_info = &pf->vmdq[i];
4749                 vmdq_info->pf = pf;
4750                 vmdq_info->vsi = vsi;
4751         }
4752         pf->nb_cfg_vmdq_vsi = conf_vsis;
4753
4754         /* Configure Vlan */
4755         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4756         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4757                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4758                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4759                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4760                                         vmdq_conf->pool_map[i].vlan_id, j);
4761
4762                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4763                                                 vmdq_conf->pool_map[i].vlan_id);
4764                                 if (err) {
4765                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4766                                         err = -1;
4767                                         goto err_vsi_setup;
4768                                 }
4769                         }
4770                 }
4771         }
4772
4773         i40e_pf_enable_irq0(hw);
4774
4775         return 0;
4776
4777 err_vsi_setup:
4778         for (i = 0; i < conf_vsis; i++)
4779                 if (pf->vmdq[i].vsi == NULL)
4780                         break;
4781                 else
4782                         i40e_vsi_release(pf->vmdq[i].vsi);
4783
4784         rte_free(pf->vmdq);
4785         pf->vmdq = NULL;
4786         i40e_pf_enable_irq0(hw);
4787         return err;
4788 }
4789
4790 static void
4791 i40e_stat_update_32(struct i40e_hw *hw,
4792                    uint32_t reg,
4793                    bool offset_loaded,
4794                    uint64_t *offset,
4795                    uint64_t *stat)
4796 {
4797         uint64_t new_data;
4798
4799         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4800         if (!offset_loaded)
4801                 *offset = new_data;
4802
4803         if (new_data >= *offset)
4804                 *stat = (uint64_t)(new_data - *offset);
4805         else
4806                 *stat = (uint64_t)((new_data +
4807                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4808 }
4809
4810 static void
4811 i40e_stat_update_48(struct i40e_hw *hw,
4812                    uint32_t hireg,
4813                    uint32_t loreg,
4814                    bool offset_loaded,
4815                    uint64_t *offset,
4816                    uint64_t *stat)
4817 {
4818         uint64_t new_data;
4819
4820         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4821         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4822                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4823
4824         if (!offset_loaded)
4825                 *offset = new_data;
4826
4827         if (new_data >= *offset)
4828                 *stat = new_data - *offset;
4829         else
4830                 *stat = (uint64_t)((new_data +
4831                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4832
4833         *stat &= I40E_48_BIT_MASK;
4834 }
4835
4836 /* Disable IRQ0 */
4837 void
4838 i40e_pf_disable_irq0(struct i40e_hw *hw)
4839 {
4840         /* Disable all interrupt types */
4841         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4842         I40E_WRITE_FLUSH(hw);
4843 }
4844
4845 /* Enable IRQ0 */
4846 void
4847 i40e_pf_enable_irq0(struct i40e_hw *hw)
4848 {
4849         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4850                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4851                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4852                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4853         I40E_WRITE_FLUSH(hw);
4854 }
4855
4856 static void
4857 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4858 {
4859         /* read pending request and disable first */
4860         i40e_pf_disable_irq0(hw);
4861         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4862         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4863                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4864
4865         if (no_queue)
4866                 /* Link no queues with irq0 */
4867                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4868                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4869 }
4870
4871 static void
4872 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4873 {
4874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4875         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4876         int i;
4877         uint16_t abs_vf_id;
4878         uint32_t index, offset, val;
4879
4880         if (!pf->vfs)
4881                 return;
4882         /**
4883          * Try to find which VF trigger a reset, use absolute VF id to access
4884          * since the reg is global register.
4885          */
4886         for (i = 0; i < pf->vf_num; i++) {
4887                 abs_vf_id = hw->func_caps.vf_base_id + i;
4888                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4889                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4890                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4891                 /* VFR event occured */
4892                 if (val & (0x1 << offset)) {
4893                         int ret;
4894
4895                         /* Clear the event first */
4896                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4897                                                         (0x1 << offset));
4898                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4899                         /**
4900                          * Only notify a VF reset event occured,
4901                          * don't trigger another SW reset
4902                          */
4903                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4904                         if (ret != I40E_SUCCESS)
4905                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4906                 }
4907         }
4908 }
4909
4910 static void
4911 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4912 {
4913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4914         struct i40e_arq_event_info info;
4915         uint16_t pending, opcode;
4916         int ret;
4917
4918         info.buf_len = I40E_AQ_BUF_SZ;
4919         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4920         if (!info.msg_buf) {
4921                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4922                 return;
4923         }
4924
4925         pending = 1;
4926         while (pending) {
4927                 ret = i40e_clean_arq_element(hw, &info, &pending);
4928
4929                 if (ret != I40E_SUCCESS) {
4930                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4931                                     "aq_err: %u", hw->aq.asq_last_status);
4932                         break;
4933                 }
4934                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4935
4936                 switch (opcode) {
4937                 case i40e_aqc_opc_send_msg_to_pf:
4938                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4939                         i40e_pf_host_handle_vf_msg(dev,
4940                                         rte_le_to_cpu_16(info.desc.retval),
4941                                         rte_le_to_cpu_32(info.desc.cookie_high),
4942                                         rte_le_to_cpu_32(info.desc.cookie_low),
4943                                         info.msg_buf,
4944                                         info.msg_len);
4945                         break;
4946                 default:
4947                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4948                                     opcode);
4949                         break;
4950                 }
4951         }
4952         rte_free(info.msg_buf);
4953 }
4954
4955 /*
4956  * Interrupt handler is registered as the alarm callback for handling LSC
4957  * interrupt in a definite of time, in order to wait the NIC into a stable
4958  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4959  * no need for link down interrupt.
4960  */
4961 static void
4962 i40e_dev_interrupt_delayed_handler(void *param)
4963 {
4964         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4966         uint32_t icr0;
4967
4968         /* read interrupt causes again */
4969         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4970
4971 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4972         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4973                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4974         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4975                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4976         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4977                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4978         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4979                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4980         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4981                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4982                                                                 "state\n");
4983         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4984                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4985         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4986                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4987 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4988
4989         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4990                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4991                 i40e_dev_handle_vfr_event(dev);
4992         }
4993         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4994                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4995                 i40e_dev_handle_aq_msg(dev);
4996         }
4997
4998         /* handle the link up interrupt in an alarm callback */
4999         i40e_dev_link_update(dev, 0);
5000         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5001
5002         i40e_pf_enable_irq0(hw);
5003         rte_intr_enable(&(dev->pci_dev->intr_handle));
5004 }
5005
5006 /**
5007  * Interrupt handler triggered by NIC  for handling
5008  * specific interrupt.
5009  *
5010  * @param handle
5011  *  Pointer to interrupt handle.
5012  * @param param
5013  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5014  *
5015  * @return
5016  *  void
5017  */
5018 static void
5019 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5020                            void *param)
5021 {
5022         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5023         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5024         uint32_t icr0;
5025
5026         /* Disable interrupt */
5027         i40e_pf_disable_irq0(hw);
5028
5029         /* read out interrupt causes */
5030         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5031
5032         /* No interrupt event indicated */
5033         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5034                 PMD_DRV_LOG(INFO, "No interrupt event");
5035                 goto done;
5036         }
5037 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5038         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5039                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5040         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5041                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5042         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5043                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5044         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5045                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5046         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5047                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5048         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5049                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5050         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5051                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5052 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5053
5054         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5055                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5056                 i40e_dev_handle_vfr_event(dev);
5057         }
5058         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5059                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5060                 i40e_dev_handle_aq_msg(dev);
5061         }
5062
5063         /* Link Status Change interrupt */
5064         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5065 #define I40E_US_PER_SECOND 1000000
5066                 struct rte_eth_link link;
5067
5068                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5069                 memset(&link, 0, sizeof(link));
5070                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5071                 i40e_dev_link_update(dev, 0);
5072
5073                 /*
5074                  * For link up interrupt, it needs to wait 1 second to let the
5075                  * hardware be a stable state. Otherwise several consecutive
5076                  * interrupts can be observed.
5077                  * For link down interrupt, no need to wait.
5078                  */
5079                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5080                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5081                         return;
5082                 else
5083                         _rte_eth_dev_callback_process(dev,
5084                                 RTE_ETH_EVENT_INTR_LSC);
5085         }
5086
5087 done:
5088         /* Enable interrupt */
5089         i40e_pf_enable_irq0(hw);
5090         rte_intr_enable(&(dev->pci_dev->intr_handle));
5091 }
5092
5093 static int
5094 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5095                          struct i40e_macvlan_filter *filter,
5096                          int total)
5097 {
5098         int ele_num, ele_buff_size;
5099         int num, actual_num, i;
5100         uint16_t flags;
5101         int ret = I40E_SUCCESS;
5102         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5103         struct i40e_aqc_add_macvlan_element_data *req_list;
5104
5105         if (filter == NULL  || total == 0)
5106                 return I40E_ERR_PARAM;
5107         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5108         ele_buff_size = hw->aq.asq_buf_size;
5109
5110         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5111         if (req_list == NULL) {
5112                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5113                 return I40E_ERR_NO_MEMORY;
5114         }
5115
5116         num = 0;
5117         do {
5118                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5119                 memset(req_list, 0, ele_buff_size);
5120
5121                 for (i = 0; i < actual_num; i++) {
5122                         (void)rte_memcpy(req_list[i].mac_addr,
5123                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5124                         req_list[i].vlan_tag =
5125                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5126
5127                         switch (filter[num + i].filter_type) {
5128                         case RTE_MAC_PERFECT_MATCH:
5129                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5130                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5131                                 break;
5132                         case RTE_MACVLAN_PERFECT_MATCH:
5133                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5134                                 break;
5135                         case RTE_MAC_HASH_MATCH:
5136                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5137                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5138                                 break;
5139                         case RTE_MACVLAN_HASH_MATCH:
5140                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5141                                 break;
5142                         default:
5143                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5144                                 ret = I40E_ERR_PARAM;
5145                                 goto DONE;
5146                         }
5147
5148                         req_list[i].queue_number = 0;
5149
5150                         req_list[i].flags = rte_cpu_to_le_16(flags);
5151                 }
5152
5153                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5154                                                 actual_num, NULL);
5155                 if (ret != I40E_SUCCESS) {
5156                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5157                         goto DONE;
5158                 }
5159                 num += actual_num;
5160         } while (num < total);
5161
5162 DONE:
5163         rte_free(req_list);
5164         return ret;
5165 }
5166
5167 static int
5168 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5169                             struct i40e_macvlan_filter *filter,
5170                             int total)
5171 {
5172         int ele_num, ele_buff_size;
5173         int num, actual_num, i;
5174         uint16_t flags;
5175         int ret = I40E_SUCCESS;
5176         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5177         struct i40e_aqc_remove_macvlan_element_data *req_list;
5178
5179         if (filter == NULL  || total == 0)
5180                 return I40E_ERR_PARAM;
5181
5182         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5183         ele_buff_size = hw->aq.asq_buf_size;
5184
5185         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5186         if (req_list == NULL) {
5187                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5188                 return I40E_ERR_NO_MEMORY;
5189         }
5190
5191         num = 0;
5192         do {
5193                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5194                 memset(req_list, 0, ele_buff_size);
5195
5196                 for (i = 0; i < actual_num; i++) {
5197                         (void)rte_memcpy(req_list[i].mac_addr,
5198                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5199                         req_list[i].vlan_tag =
5200                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5201
5202                         switch (filter[num + i].filter_type) {
5203                         case RTE_MAC_PERFECT_MATCH:
5204                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5205                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5206                                 break;
5207                         case RTE_MACVLAN_PERFECT_MATCH:
5208                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5209                                 break;
5210                         case RTE_MAC_HASH_MATCH:
5211                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5212                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5213                                 break;
5214                         case RTE_MACVLAN_HASH_MATCH:
5215                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5216                                 break;
5217                         default:
5218                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5219                                 ret = I40E_ERR_PARAM;
5220                                 goto DONE;
5221                         }
5222                         req_list[i].flags = rte_cpu_to_le_16(flags);
5223                 }
5224
5225                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5226                                                 actual_num, NULL);
5227                 if (ret != I40E_SUCCESS) {
5228                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5229                         goto DONE;
5230                 }
5231                 num += actual_num;
5232         } while (num < total);
5233
5234 DONE:
5235         rte_free(req_list);
5236         return ret;
5237 }
5238
5239 /* Find out specific MAC filter */
5240 static struct i40e_mac_filter *
5241 i40e_find_mac_filter(struct i40e_vsi *vsi,
5242                          struct ether_addr *macaddr)
5243 {
5244         struct i40e_mac_filter *f;
5245
5246         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5247                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5248                         return f;
5249         }
5250
5251         return NULL;
5252 }
5253
5254 static bool
5255 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5256                          uint16_t vlan_id)
5257 {
5258         uint32_t vid_idx, vid_bit;
5259
5260         if (vlan_id > ETH_VLAN_ID_MAX)
5261                 return 0;
5262
5263         vid_idx = I40E_VFTA_IDX(vlan_id);
5264         vid_bit = I40E_VFTA_BIT(vlan_id);
5265
5266         if (vsi->vfta[vid_idx] & vid_bit)
5267                 return 1;
5268         else
5269                 return 0;
5270 }
5271
5272 static void
5273 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5274                          uint16_t vlan_id, bool on)
5275 {
5276         uint32_t vid_idx, vid_bit;
5277
5278         if (vlan_id > ETH_VLAN_ID_MAX)
5279                 return;
5280
5281         vid_idx = I40E_VFTA_IDX(vlan_id);
5282         vid_bit = I40E_VFTA_BIT(vlan_id);
5283
5284         if (on)
5285                 vsi->vfta[vid_idx] |= vid_bit;
5286         else
5287                 vsi->vfta[vid_idx] &= ~vid_bit;
5288 }
5289
5290 /**
5291  * Find all vlan options for specific mac addr,
5292  * return with actual vlan found.
5293  */
5294 static inline int
5295 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5296                            struct i40e_macvlan_filter *mv_f,
5297                            int num, struct ether_addr *addr)
5298 {
5299         int i;
5300         uint32_t j, k;
5301
5302         /**
5303          * Not to use i40e_find_vlan_filter to decrease the loop time,
5304          * although the code looks complex.
5305           */
5306         if (num < vsi->vlan_num)
5307                 return I40E_ERR_PARAM;
5308
5309         i = 0;
5310         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5311                 if (vsi->vfta[j]) {
5312                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5313                                 if (vsi->vfta[j] & (1 << k)) {
5314                                         if (i > num - 1) {
5315                                                 PMD_DRV_LOG(ERR, "vlan number "
5316                                                             "not match");
5317                                                 return I40E_ERR_PARAM;
5318                                         }
5319                                         (void)rte_memcpy(&mv_f[i].macaddr,
5320                                                         addr, ETH_ADDR_LEN);
5321                                         mv_f[i].vlan_id =
5322                                                 j * I40E_UINT32_BIT_SIZE + k;
5323                                         i++;
5324                                 }
5325                         }
5326                 }
5327         }
5328         return I40E_SUCCESS;
5329 }
5330
5331 static inline int
5332 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5333                            struct i40e_macvlan_filter *mv_f,
5334                            int num,
5335                            uint16_t vlan)
5336 {
5337         int i = 0;
5338         struct i40e_mac_filter *f;
5339
5340         if (num < vsi->mac_num)
5341                 return I40E_ERR_PARAM;
5342
5343         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5344                 if (i > num - 1) {
5345                         PMD_DRV_LOG(ERR, "buffer number not match");
5346                         return I40E_ERR_PARAM;
5347                 }
5348                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5349                                 ETH_ADDR_LEN);
5350                 mv_f[i].vlan_id = vlan;
5351                 mv_f[i].filter_type = f->mac_info.filter_type;
5352                 i++;
5353         }
5354
5355         return I40E_SUCCESS;
5356 }
5357
5358 static int
5359 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5360 {
5361         int i, num;
5362         struct i40e_mac_filter *f;
5363         struct i40e_macvlan_filter *mv_f;
5364         int ret = I40E_SUCCESS;
5365
5366         if (vsi == NULL || vsi->mac_num == 0)
5367                 return I40E_ERR_PARAM;
5368
5369         /* Case that no vlan is set */
5370         if (vsi->vlan_num == 0)
5371                 num = vsi->mac_num;
5372         else
5373                 num = vsi->mac_num * vsi->vlan_num;
5374
5375         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5376         if (mv_f == NULL) {
5377                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5378                 return I40E_ERR_NO_MEMORY;
5379         }
5380
5381         i = 0;
5382         if (vsi->vlan_num == 0) {
5383                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5384                         (void)rte_memcpy(&mv_f[i].macaddr,
5385                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5386                         mv_f[i].vlan_id = 0;
5387                         i++;
5388                 }
5389         } else {
5390                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5391                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5392                                         vsi->vlan_num, &f->mac_info.mac_addr);
5393                         if (ret != I40E_SUCCESS)
5394                                 goto DONE;
5395                         i += vsi->vlan_num;
5396                 }
5397         }
5398
5399         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5400 DONE:
5401         rte_free(mv_f);
5402
5403         return ret;
5404 }
5405
5406 int
5407 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5408 {
5409         struct i40e_macvlan_filter *mv_f;
5410         int mac_num;
5411         int ret = I40E_SUCCESS;
5412
5413         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5414                 return I40E_ERR_PARAM;
5415
5416         /* If it's already set, just return */
5417         if (i40e_find_vlan_filter(vsi,vlan))
5418                 return I40E_SUCCESS;
5419
5420         mac_num = vsi->mac_num;
5421
5422         if (mac_num == 0) {
5423                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5424                 return I40E_ERR_PARAM;
5425         }
5426
5427         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5428
5429         if (mv_f == NULL) {
5430                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5431                 return I40E_ERR_NO_MEMORY;
5432         }
5433
5434         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5435
5436         if (ret != I40E_SUCCESS)
5437                 goto DONE;
5438
5439         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5440
5441         if (ret != I40E_SUCCESS)
5442                 goto DONE;
5443
5444         i40e_set_vlan_filter(vsi, vlan, 1);
5445
5446         vsi->vlan_num++;
5447         ret = I40E_SUCCESS;
5448 DONE:
5449         rte_free(mv_f);
5450         return ret;
5451 }
5452
5453 int
5454 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5455 {
5456         struct i40e_macvlan_filter *mv_f;
5457         int mac_num;
5458         int ret = I40E_SUCCESS;
5459
5460         /**
5461          * Vlan 0 is the generic filter for untagged packets
5462          * and can't be removed.
5463          */
5464         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5465                 return I40E_ERR_PARAM;
5466
5467         /* If can't find it, just return */
5468         if (!i40e_find_vlan_filter(vsi, vlan))
5469                 return I40E_ERR_PARAM;
5470
5471         mac_num = vsi->mac_num;
5472
5473         if (mac_num == 0) {
5474                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5475                 return I40E_ERR_PARAM;
5476         }
5477
5478         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5479
5480         if (mv_f == NULL) {
5481                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5482                 return I40E_ERR_NO_MEMORY;
5483         }
5484
5485         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5486
5487         if (ret != I40E_SUCCESS)
5488                 goto DONE;
5489
5490         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5491
5492         if (ret != I40E_SUCCESS)
5493                 goto DONE;
5494
5495         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5496         if (vsi->vlan_num == 1) {
5497                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5498                 if (ret != I40E_SUCCESS)
5499                         goto DONE;
5500
5501                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5502                 if (ret != I40E_SUCCESS)
5503                         goto DONE;
5504         }
5505
5506         i40e_set_vlan_filter(vsi, vlan, 0);
5507
5508         vsi->vlan_num--;
5509         ret = I40E_SUCCESS;
5510 DONE:
5511         rte_free(mv_f);
5512         return ret;
5513 }
5514
5515 int
5516 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5517 {
5518         struct i40e_mac_filter *f;
5519         struct i40e_macvlan_filter *mv_f;
5520         int i, vlan_num = 0;
5521         int ret = I40E_SUCCESS;
5522
5523         /* If it's add and we've config it, return */
5524         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5525         if (f != NULL)
5526                 return I40E_SUCCESS;
5527         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5528                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5529
5530                 /**
5531                  * If vlan_num is 0, that's the first time to add mac,
5532                  * set mask for vlan_id 0.
5533                  */
5534                 if (vsi->vlan_num == 0) {
5535                         i40e_set_vlan_filter(vsi, 0, 1);
5536                         vsi->vlan_num = 1;
5537                 }
5538                 vlan_num = vsi->vlan_num;
5539         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5540                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5541                 vlan_num = 1;
5542
5543         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5544         if (mv_f == NULL) {
5545                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5546                 return I40E_ERR_NO_MEMORY;
5547         }
5548
5549         for (i = 0; i < vlan_num; i++) {
5550                 mv_f[i].filter_type = mac_filter->filter_type;
5551                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5552                                 ETH_ADDR_LEN);
5553         }
5554
5555         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5556                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5557                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5558                                         &mac_filter->mac_addr);
5559                 if (ret != I40E_SUCCESS)
5560                         goto DONE;
5561         }
5562
5563         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5564         if (ret != I40E_SUCCESS)
5565                 goto DONE;
5566
5567         /* Add the mac addr into mac list */
5568         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5569         if (f == NULL) {
5570                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5571                 ret = I40E_ERR_NO_MEMORY;
5572                 goto DONE;
5573         }
5574         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5575                         ETH_ADDR_LEN);
5576         f->mac_info.filter_type = mac_filter->filter_type;
5577         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5578         vsi->mac_num++;
5579
5580         ret = I40E_SUCCESS;
5581 DONE:
5582         rte_free(mv_f);
5583
5584         return ret;
5585 }
5586
5587 int
5588 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5589 {
5590         struct i40e_mac_filter *f;
5591         struct i40e_macvlan_filter *mv_f;
5592         int i, vlan_num;
5593         enum rte_mac_filter_type filter_type;
5594         int ret = I40E_SUCCESS;
5595
5596         /* Can't find it, return an error */
5597         f = i40e_find_mac_filter(vsi, addr);
5598         if (f == NULL)
5599                 return I40E_ERR_PARAM;
5600
5601         vlan_num = vsi->vlan_num;
5602         filter_type = f->mac_info.filter_type;
5603         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5604                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5605                 if (vlan_num == 0) {
5606                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5607                         return I40E_ERR_PARAM;
5608                 }
5609         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5610                         filter_type == RTE_MAC_HASH_MATCH)
5611                 vlan_num = 1;
5612
5613         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5614         if (mv_f == NULL) {
5615                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5616                 return I40E_ERR_NO_MEMORY;
5617         }
5618
5619         for (i = 0; i < vlan_num; i++) {
5620                 mv_f[i].filter_type = filter_type;
5621                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5622                                 ETH_ADDR_LEN);
5623         }
5624         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5625                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5626                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5627                 if (ret != I40E_SUCCESS)
5628                         goto DONE;
5629         }
5630
5631         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5632         if (ret != I40E_SUCCESS)
5633                 goto DONE;
5634
5635         /* Remove the mac addr into mac list */
5636         TAILQ_REMOVE(&vsi->mac_list, f, next);
5637         rte_free(f);
5638         vsi->mac_num--;
5639
5640         ret = I40E_SUCCESS;
5641 DONE:
5642         rte_free(mv_f);
5643         return ret;
5644 }
5645
5646 /* Configure hash enable flags for RSS */
5647 uint64_t
5648 i40e_config_hena(uint64_t flags)
5649 {
5650         uint64_t hena = 0;
5651
5652         if (!flags)
5653                 return hena;
5654
5655         if (flags & ETH_RSS_FRAG_IPV4)
5656                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5657         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5658                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5659         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5660                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5661         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5662                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5663         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5664                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5665         if (flags & ETH_RSS_FRAG_IPV6)
5666                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5667         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5668                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5669         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5670                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5671         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5672                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5673         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5674                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5675         if (flags & ETH_RSS_L2_PAYLOAD)
5676                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5677
5678         return hena;
5679 }
5680
5681 /* Parse the hash enable flags */
5682 uint64_t
5683 i40e_parse_hena(uint64_t flags)
5684 {
5685         uint64_t rss_hf = 0;
5686
5687         if (!flags)
5688                 return rss_hf;
5689         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5690                 rss_hf |= ETH_RSS_FRAG_IPV4;
5691         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5692                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5693         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5694                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5695         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5696                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5697         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5698                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5699         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5700                 rss_hf |= ETH_RSS_FRAG_IPV6;
5701         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5702                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5703         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5704                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5705         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5706                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5707         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5708                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5709         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5710                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5711
5712         return rss_hf;
5713 }
5714
5715 /* Disable RSS */
5716 static void
5717 i40e_pf_disable_rss(struct i40e_pf *pf)
5718 {
5719         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5720         uint64_t hena;
5721
5722         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5723         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5724         hena &= ~I40E_RSS_HENA_ALL;
5725         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5726         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5727         I40E_WRITE_FLUSH(hw);
5728 }
5729
5730 static int
5731 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5732 {
5733         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5734         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5735         int ret = 0;
5736
5737         if (!key || key_len == 0) {
5738                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5739                 return 0;
5740         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5741                 sizeof(uint32_t)) {
5742                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5743                 return -EINVAL;
5744         }
5745
5746         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5747                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5748                         (struct i40e_aqc_get_set_rss_key_data *)key;
5749
5750                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5751                 if (ret)
5752                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5753                                      "via AQ");
5754         } else {
5755                 uint32_t *hash_key = (uint32_t *)key;
5756                 uint16_t i;
5757
5758                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5759                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5760                 I40E_WRITE_FLUSH(hw);
5761         }
5762
5763         return ret;
5764 }
5765
5766 static int
5767 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5768 {
5769         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5770         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5771         int ret;
5772
5773         if (!key || !key_len)
5774                 return -EINVAL;
5775
5776         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5777                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5778                         (struct i40e_aqc_get_set_rss_key_data *)key);
5779                 if (ret) {
5780                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5781                         return ret;
5782                 }
5783         } else {
5784                 uint32_t *key_dw = (uint32_t *)key;
5785                 uint16_t i;
5786
5787                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5788                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5789         }
5790         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5791
5792         return 0;
5793 }
5794
5795 static int
5796 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5797 {
5798         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5799         uint64_t rss_hf;
5800         uint64_t hena;
5801         int ret;
5802
5803         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5804                                rss_conf->rss_key_len);
5805         if (ret)
5806                 return ret;
5807
5808         rss_hf = rss_conf->rss_hf;
5809         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5810         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5811         hena &= ~I40E_RSS_HENA_ALL;
5812         hena |= i40e_config_hena(rss_hf);
5813         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5814         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5815         I40E_WRITE_FLUSH(hw);
5816
5817         return 0;
5818 }
5819
5820 static int
5821 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5822                          struct rte_eth_rss_conf *rss_conf)
5823 {
5824         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5825         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5826         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5827         uint64_t hena;
5828
5829         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5830         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5831         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5832                 if (rss_hf != 0) /* Enable RSS */
5833                         return -EINVAL;
5834                 return 0; /* Nothing to do */
5835         }
5836         /* RSS enabled */
5837         if (rss_hf == 0) /* Disable RSS */
5838                 return -EINVAL;
5839
5840         return i40e_hw_rss_hash_set(pf, rss_conf);
5841 }
5842
5843 static int
5844 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5845                            struct rte_eth_rss_conf *rss_conf)
5846 {
5847         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5849         uint64_t hena;
5850
5851         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5852                          &rss_conf->rss_key_len);
5853
5854         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5855         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5856         rss_conf->rss_hf = i40e_parse_hena(hena);
5857
5858         return 0;
5859 }
5860
5861 static int
5862 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5863 {
5864         switch (filter_type) {
5865         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5866                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5867                 break;
5868         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5869                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5870                 break;
5871         case RTE_TUNNEL_FILTER_IMAC_TENID:
5872                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5873                 break;
5874         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5875                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5876                 break;
5877         case ETH_TUNNEL_FILTER_IMAC:
5878                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5879                 break;
5880         default:
5881                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5882                 return -EINVAL;
5883         }
5884
5885         return 0;
5886 }
5887
5888 static int
5889 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5890                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5891                         uint8_t add)
5892 {
5893         uint16_t ip_type;
5894         uint8_t tun_type = 0;
5895         int val, ret = 0;
5896         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5897         struct i40e_vsi *vsi = pf->main_vsi;
5898         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5899         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5900
5901         cld_filter = rte_zmalloc("tunnel_filter",
5902                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5903                 0);
5904
5905         if (NULL == cld_filter) {
5906                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5907                 return -EINVAL;
5908         }
5909         pfilter = cld_filter;
5910
5911         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5912                         sizeof(struct ether_addr));
5913         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5914                         sizeof(struct ether_addr));
5915
5916         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5917         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5918                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5919                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5920                                 &tunnel_filter->ip_addr,
5921                                 sizeof(pfilter->ipaddr.v4.data));
5922         } else {
5923                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5924                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5925                                 &tunnel_filter->ip_addr,
5926                                 sizeof(pfilter->ipaddr.v6.data));
5927         }
5928
5929         /* check tunneled type */
5930         switch (tunnel_filter->tunnel_type) {
5931         case RTE_TUNNEL_TYPE_VXLAN:
5932                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5933                 break;
5934         case RTE_TUNNEL_TYPE_NVGRE:
5935                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5936                 break;
5937         default:
5938                 /* Other tunnel types is not supported. */
5939                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5940                 rte_free(cld_filter);
5941                 return -EINVAL;
5942         }
5943
5944         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5945                                                 &pfilter->flags);
5946         if (val < 0) {
5947                 rte_free(cld_filter);
5948                 return -EINVAL;
5949         }
5950
5951         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5952                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5953         pfilter->tenant_id = tunnel_filter->tenant_id;
5954         pfilter->queue_number = tunnel_filter->queue_id;
5955
5956         if (add)
5957                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5958         else
5959                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5960                                                 cld_filter, 1);
5961
5962         rte_free(cld_filter);
5963         return ret;
5964 }
5965
5966 static int
5967 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5968 {
5969         uint8_t i;
5970
5971         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5972                 if (pf->vxlan_ports[i] == port)
5973                         return i;
5974         }
5975
5976         return -1;
5977 }
5978
5979 static int
5980 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5981 {
5982         int  idx, ret;
5983         uint8_t filter_idx;
5984         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5985
5986         idx = i40e_get_vxlan_port_idx(pf, port);
5987
5988         /* Check if port already exists */
5989         if (idx >= 0) {
5990                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5991                 return -EINVAL;
5992         }
5993
5994         /* Now check if there is space to add the new port */
5995         idx = i40e_get_vxlan_port_idx(pf, 0);
5996         if (idx < 0) {
5997                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5998                         "not adding port %d", port);
5999                 return -ENOSPC;
6000         }
6001
6002         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6003                                         &filter_idx, NULL);
6004         if (ret < 0) {
6005                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6006                 return -1;
6007         }
6008
6009         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6010                          port,  filter_idx);
6011
6012         /* New port: add it and mark its index in the bitmap */
6013         pf->vxlan_ports[idx] = port;
6014         pf->vxlan_bitmap |= (1 << idx);
6015
6016         if (!(pf->flags & I40E_FLAG_VXLAN))
6017                 pf->flags |= I40E_FLAG_VXLAN;
6018
6019         return 0;
6020 }
6021
6022 static int
6023 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6024 {
6025         int idx;
6026         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6027
6028         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6029                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6030                 return -EINVAL;
6031         }
6032
6033         idx = i40e_get_vxlan_port_idx(pf, port);
6034
6035         if (idx < 0) {
6036                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6037                 return -EINVAL;
6038         }
6039
6040         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6041                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6042                 return -1;
6043         }
6044
6045         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6046                         port, idx);
6047
6048         pf->vxlan_ports[idx] = 0;
6049         pf->vxlan_bitmap &= ~(1 << idx);
6050
6051         if (!pf->vxlan_bitmap)
6052                 pf->flags &= ~I40E_FLAG_VXLAN;
6053
6054         return 0;
6055 }
6056
6057 /* Add UDP tunneling port */
6058 static int
6059 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
6060                         struct rte_eth_udp_tunnel *udp_tunnel)
6061 {
6062         int ret = 0;
6063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6064
6065         if (udp_tunnel == NULL)
6066                 return -EINVAL;
6067
6068         switch (udp_tunnel->prot_type) {
6069         case RTE_TUNNEL_TYPE_VXLAN:
6070                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6071                 break;
6072
6073         case RTE_TUNNEL_TYPE_GENEVE:
6074         case RTE_TUNNEL_TYPE_TEREDO:
6075                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6076                 ret = -1;
6077                 break;
6078
6079         default:
6080                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6081                 ret = -1;
6082                 break;
6083         }
6084
6085         return ret;
6086 }
6087
6088 /* Remove UDP tunneling port */
6089 static int
6090 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6091                         struct rte_eth_udp_tunnel *udp_tunnel)
6092 {
6093         int ret = 0;
6094         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6095
6096         if (udp_tunnel == NULL)
6097                 return -EINVAL;
6098
6099         switch (udp_tunnel->prot_type) {
6100         case RTE_TUNNEL_TYPE_VXLAN:
6101                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6102                 break;
6103         case RTE_TUNNEL_TYPE_GENEVE:
6104         case RTE_TUNNEL_TYPE_TEREDO:
6105                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6106                 ret = -1;
6107                 break;
6108         default:
6109                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6110                 ret = -1;
6111                 break;
6112         }
6113
6114         return ret;
6115 }
6116
6117 /* Calculate the maximum number of contiguous PF queues that are configured */
6118 static int
6119 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6120 {
6121         struct rte_eth_dev_data *data = pf->dev_data;
6122         int i, num;
6123         struct i40e_rx_queue *rxq;
6124
6125         num = 0;
6126         for (i = 0; i < pf->lan_nb_qps; i++) {
6127                 rxq = data->rx_queues[i];
6128                 if (rxq && rxq->q_set)
6129                         num++;
6130                 else
6131                         break;
6132         }
6133
6134         return num;
6135 }
6136
6137 /* Configure RSS */
6138 static int
6139 i40e_pf_config_rss(struct i40e_pf *pf)
6140 {
6141         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6142         struct rte_eth_rss_conf rss_conf;
6143         uint32_t i, lut = 0;
6144         uint16_t j, num;
6145
6146         /*
6147          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6148          * It's necessary to calulate the actual PF queues that are configured.
6149          */
6150         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6151                 num = i40e_pf_calc_configured_queues_num(pf);
6152         else
6153                 num = pf->dev_data->nb_rx_queues;
6154
6155         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6156         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6157                         num);
6158
6159         if (num == 0) {
6160                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6161                 return -ENOTSUP;
6162         }
6163
6164         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6165                 if (j == num)
6166                         j = 0;
6167                 lut = (lut << 8) | (j & ((0x1 <<
6168                         hw->func_caps.rss_table_entry_width) - 1));
6169                 if ((i & 3) == 3)
6170                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6171         }
6172
6173         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6174         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6175                 i40e_pf_disable_rss(pf);
6176                 return 0;
6177         }
6178         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6179                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6180                 /* Random default keys */
6181                 static uint32_t rss_key_default[] = {0x6b793944,
6182                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6183                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6184                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6185
6186                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6187                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6188                                                         sizeof(uint32_t);
6189         }
6190
6191         return i40e_hw_rss_hash_set(pf, &rss_conf);
6192 }
6193
6194 static int
6195 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6196                                struct rte_eth_tunnel_filter_conf *filter)
6197 {
6198         if (pf == NULL || filter == NULL) {
6199                 PMD_DRV_LOG(ERR, "Invalid parameter");
6200                 return -EINVAL;
6201         }
6202
6203         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6204                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6205                 return -EINVAL;
6206         }
6207
6208         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6209                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6210                 return -EINVAL;
6211         }
6212
6213         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6214                 (is_zero_ether_addr(filter->outer_mac))) {
6215                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6216                 return -EINVAL;
6217         }
6218
6219         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6220                 (is_zero_ether_addr(filter->inner_mac))) {
6221                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6222                 return -EINVAL;
6223         }
6224
6225         return 0;
6226 }
6227
6228 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6229 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6230 static int
6231 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6232 {
6233         uint32_t val, reg;
6234         int ret = -EINVAL;
6235
6236         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6237         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6238
6239         if (len == 3) {
6240                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6241         } else if (len == 4) {
6242                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6243         } else {
6244                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6245                 return ret;
6246         }
6247
6248         if (reg != val) {
6249                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6250                                                    reg, NULL);
6251                 if (ret != 0)
6252                         return ret;
6253         } else {
6254                 ret = 0;
6255         }
6256         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6257                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6258
6259         return ret;
6260 }
6261
6262 static int
6263 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6264 {
6265         int ret = -EINVAL;
6266
6267         if (!hw || !cfg)
6268                 return -EINVAL;
6269
6270         switch (cfg->cfg_type) {
6271         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6272                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6273                 break;
6274         default:
6275                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6276                 break;
6277         }
6278
6279         return ret;
6280 }
6281
6282 static int
6283 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6284                                enum rte_filter_op filter_op,
6285                                void *arg)
6286 {
6287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6288         int ret = I40E_ERR_PARAM;
6289
6290         switch (filter_op) {
6291         case RTE_ETH_FILTER_SET:
6292                 ret = i40e_dev_global_config_set(hw,
6293                         (struct rte_eth_global_cfg *)arg);
6294                 break;
6295         default:
6296                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6297                 break;
6298         }
6299
6300         return ret;
6301 }
6302
6303 static int
6304 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6305                           enum rte_filter_op filter_op,
6306                           void *arg)
6307 {
6308         struct rte_eth_tunnel_filter_conf *filter;
6309         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6310         int ret = I40E_SUCCESS;
6311
6312         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6313
6314         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6315                 return I40E_ERR_PARAM;
6316
6317         switch (filter_op) {
6318         case RTE_ETH_FILTER_NOP:
6319                 if (!(pf->flags & I40E_FLAG_VXLAN))
6320                         ret = I40E_NOT_SUPPORTED;
6321                 break;
6322         case RTE_ETH_FILTER_ADD:
6323                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6324                 break;
6325         case RTE_ETH_FILTER_DELETE:
6326                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6327                 break;
6328         default:
6329                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6330                 ret = I40E_ERR_PARAM;
6331                 break;
6332         }
6333
6334         return ret;
6335 }
6336
6337 static int
6338 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6339 {
6340         int ret = 0;
6341         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6342
6343         /* RSS setup */
6344         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6345                 ret = i40e_pf_config_rss(pf);
6346         else
6347                 i40e_pf_disable_rss(pf);
6348
6349         return ret;
6350 }
6351
6352 /* Get the symmetric hash enable configurations per port */
6353 static void
6354 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6355 {
6356         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6357
6358         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6359 }
6360
6361 /* Set the symmetric hash enable configurations per port */
6362 static void
6363 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6364 {
6365         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6366
6367         if (enable > 0) {
6368                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6369                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6370                                                         "been enabled");
6371                         return;
6372                 }
6373                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6374         } else {
6375                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6376                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6377                                                         "been disabled");
6378                         return;
6379                 }
6380                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6381         }
6382         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6383         I40E_WRITE_FLUSH(hw);
6384 }
6385
6386 /*
6387  * Get global configurations of hash function type and symmetric hash enable
6388  * per flow type (pctype). Note that global configuration means it affects all
6389  * the ports on the same NIC.
6390  */
6391 static int
6392 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6393                                    struct rte_eth_hash_global_conf *g_cfg)
6394 {
6395         uint32_t reg, mask = I40E_FLOW_TYPES;
6396         uint16_t i;
6397         enum i40e_filter_pctype pctype;
6398
6399         memset(g_cfg, 0, sizeof(*g_cfg));
6400         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6401         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6402                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6403         else
6404                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6405         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6406                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6407
6408         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6409                 if (!(mask & (1UL << i)))
6410                         continue;
6411                 mask &= ~(1UL << i);
6412                 /* Bit set indicats the coresponding flow type is supported */
6413                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6414                 pctype = i40e_flowtype_to_pctype(i);
6415                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6416                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6417                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6418         }
6419
6420         return 0;
6421 }
6422
6423 static int
6424 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6425 {
6426         uint32_t i;
6427         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6428
6429         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6430                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6431                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6432                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6433                                                 g_cfg->hash_func);
6434                 return -EINVAL;
6435         }
6436
6437         /*
6438          * As i40e supports less than 32 flow types, only first 32 bits need to
6439          * be checked.
6440          */
6441         mask0 = g_cfg->valid_bit_mask[0];
6442         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6443                 if (i == 0) {
6444                         /* Check if any unsupported flow type configured */
6445                         if ((mask0 | i40e_mask) ^ i40e_mask)
6446                                 goto mask_err;
6447                 } else {
6448                         if (g_cfg->valid_bit_mask[i])
6449                                 goto mask_err;
6450                 }
6451         }
6452
6453         return 0;
6454
6455 mask_err:
6456         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6457
6458         return -EINVAL;
6459 }
6460
6461 /*
6462  * Set global configurations of hash function type and symmetric hash enable
6463  * per flow type (pctype). Note any modifying global configuration will affect
6464  * all the ports on the same NIC.
6465  */
6466 static int
6467 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6468                                    struct rte_eth_hash_global_conf *g_cfg)
6469 {
6470         int ret;
6471         uint16_t i;
6472         uint32_t reg;
6473         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6474         enum i40e_filter_pctype pctype;
6475
6476         /* Check the input parameters */
6477         ret = i40e_hash_global_config_check(g_cfg);
6478         if (ret < 0)
6479                 return ret;
6480
6481         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6482                 if (!(mask0 & (1UL << i)))
6483                         continue;
6484                 mask0 &= ~(1UL << i);
6485                 pctype = i40e_flowtype_to_pctype(i);
6486                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6487                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6488                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6489         }
6490
6491         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6492         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6493                 /* Toeplitz */
6494                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6495                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6496                                                                 "Toeplitz");
6497                         goto out;
6498                 }
6499                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6500         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6501                 /* Simple XOR */
6502                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6503                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6504                                                         "Simple XOR");
6505                         goto out;
6506                 }
6507                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6508         } else
6509                 /* Use the default, and keep it as it is */
6510                 goto out;
6511
6512         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6513
6514 out:
6515         I40E_WRITE_FLUSH(hw);
6516
6517         return 0;
6518 }
6519
6520 /**
6521  * Valid input sets for hash and flow director filters per PCTYPE
6522  */
6523 static uint64_t
6524 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6525                 enum rte_filter_type filter)
6526 {
6527         uint64_t valid;
6528
6529         static const uint64_t valid_hash_inset_table[] = {
6530                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6531                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6532                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6533                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6534                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6535                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6536                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6537                         I40E_INSET_FLEX_PAYLOAD,
6538                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6539                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6540                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6541                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6542                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6543                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6544                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6545                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6546                         I40E_INSET_FLEX_PAYLOAD,
6547                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6548                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6549                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6550                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6551                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6552                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6553                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6554                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6555                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6556                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6557                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6558                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6559                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6560                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6561                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6562                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6563                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6564                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6565                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6566                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6567                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6568                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6569                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6570                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6571                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6572                         I40E_INSET_FLEX_PAYLOAD,
6573                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6574                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6575                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6576                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6577                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6578                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6579                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6580                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6581                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6582                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6583                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6584                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6585                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6586                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6587                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6588                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6589                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6590                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6591                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6592                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6593                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6594                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6595                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6596                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6597                         I40E_INSET_FLEX_PAYLOAD,
6598                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6599                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6600                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6601                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6602                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6603                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6604                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6605                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6606                         I40E_INSET_FLEX_PAYLOAD,
6607                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6608                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6609                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6610                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6611                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6612                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6613                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6614                         I40E_INSET_FLEX_PAYLOAD,
6615                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6616                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6617                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6618                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6619                         I40E_INSET_FLEX_PAYLOAD,
6620         };
6621
6622         /**
6623          * Flow director supports only fields defined in
6624          * union rte_eth_fdir_flow.
6625          */
6626         static const uint64_t valid_fdir_inset_table[] = {
6627                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6628                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6629                 I40E_INSET_FLEX_PAYLOAD,
6630                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6631                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6632                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6633                 I40E_INSET_FLEX_PAYLOAD,
6634                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6635                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6636                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6637                 I40E_INSET_FLEX_PAYLOAD,
6638                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6639                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6640                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6641                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6642                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6643                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6644                 I40E_INSET_FLEX_PAYLOAD,
6645                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6646                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6647                 I40E_INSET_FLEX_PAYLOAD,
6648                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6649                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6650                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6651                 I40E_INSET_FLEX_PAYLOAD,
6652                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6653                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6654                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6655                 I40E_INSET_FLEX_PAYLOAD,
6656                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6657                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6658                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6659                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6660                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6661                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6662                 I40E_INSET_FLEX_PAYLOAD,
6663                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6664                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6665         };
6666
6667         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6668                 return 0;
6669         if (filter == RTE_ETH_FILTER_HASH)
6670                 valid = valid_hash_inset_table[pctype];
6671         else
6672                 valid = valid_fdir_inset_table[pctype];
6673
6674         return valid;
6675 }
6676
6677 /**
6678  * Validate if the input set is allowed for a specific PCTYPE
6679  */
6680 static int
6681 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6682                 enum rte_filter_type filter, uint64_t inset)
6683 {
6684         uint64_t valid;
6685
6686         valid = i40e_get_valid_input_set(pctype, filter);
6687         if (inset & (~valid))
6688                 return -EINVAL;
6689
6690         return 0;
6691 }
6692
6693 /* default input set fields combination per pctype */
6694 static uint64_t
6695 i40e_get_default_input_set(uint16_t pctype)
6696 {
6697         static const uint64_t default_inset_table[] = {
6698                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6699                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6700                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6701                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6702                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6703                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6704                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6705                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6706                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6707                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6708                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6709                         I40E_INSET_SCTP_VT,
6710                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6711                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6712                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6713                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6714                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6715                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6716                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6717                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6718                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6719                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6720                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6721                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6722                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6723                         I40E_INSET_SCTP_VT,
6724                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6725                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6726                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6727                         I40E_INSET_LAST_ETHER_TYPE,
6728         };
6729
6730         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6731                 return 0;
6732
6733         return default_inset_table[pctype];
6734 }
6735
6736 /**
6737  * Parse the input set from index to logical bit masks
6738  */
6739 static int
6740 i40e_parse_input_set(uint64_t *inset,
6741                      enum i40e_filter_pctype pctype,
6742                      enum rte_eth_input_set_field *field,
6743                      uint16_t size)
6744 {
6745         uint16_t i, j;
6746         int ret = -EINVAL;
6747
6748         static const struct {
6749                 enum rte_eth_input_set_field field;
6750                 uint64_t inset;
6751         } inset_convert_table[] = {
6752                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6753                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6754                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6755                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6756                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6757                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6758                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6759                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6760                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6761                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6762                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6763                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6764                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6765                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6766                         I40E_INSET_IPV6_NEXT_HDR},
6767                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6768                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6769                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6770                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6771                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6772                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6773                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6774                         I40E_INSET_SCTP_VT},
6775                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6776                         I40E_INSET_TUNNEL_DMAC},
6777                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6778                         I40E_INSET_VLAN_TUNNEL},
6779                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6780                         I40E_INSET_TUNNEL_ID},
6781                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6782                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6783                         I40E_INSET_FLEX_PAYLOAD_W1},
6784                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6785                         I40E_INSET_FLEX_PAYLOAD_W2},
6786                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6787                         I40E_INSET_FLEX_PAYLOAD_W3},
6788                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6789                         I40E_INSET_FLEX_PAYLOAD_W4},
6790                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6791                         I40E_INSET_FLEX_PAYLOAD_W5},
6792                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6793                         I40E_INSET_FLEX_PAYLOAD_W6},
6794                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6795                         I40E_INSET_FLEX_PAYLOAD_W7},
6796                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6797                         I40E_INSET_FLEX_PAYLOAD_W8},
6798         };
6799
6800         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6801                 return ret;
6802
6803         /* Only one item allowed for default or all */
6804         if (size == 1) {
6805                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6806                         *inset = i40e_get_default_input_set(pctype);
6807                         return 0;
6808                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6809                         *inset = I40E_INSET_NONE;
6810                         return 0;
6811                 }
6812         }
6813
6814         for (i = 0, *inset = 0; i < size; i++) {
6815                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6816                         if (field[i] == inset_convert_table[j].field) {
6817                                 *inset |= inset_convert_table[j].inset;
6818                                 break;
6819                         }
6820                 }
6821
6822                 /* It contains unsupported input set, return immediately */
6823                 if (j == RTE_DIM(inset_convert_table))
6824                         return ret;
6825         }
6826
6827         return 0;
6828 }
6829
6830 /**
6831  * Translate the input set from bit masks to register aware bit masks
6832  * and vice versa
6833  */
6834 static uint64_t
6835 i40e_translate_input_set_reg(uint64_t input)
6836 {
6837         uint64_t val = 0;
6838         uint16_t i;
6839
6840         static const struct {
6841                 uint64_t inset;
6842                 uint64_t inset_reg;
6843         } inset_map[] = {
6844                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6845                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6846                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6847                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6848                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6849                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6850                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6851                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6852                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6853                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6854                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6855                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6856                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6857                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6858                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6859                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6860                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6861                 {I40E_INSET_TUNNEL_DMAC,
6862                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6863                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6864                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6865                 {I40E_INSET_TUNNEL_SRC_PORT,
6866                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6867                 {I40E_INSET_TUNNEL_DST_PORT,
6868                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6869                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6870                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6871                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6872                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6873                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6874                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6875                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6876                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6877                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6878         };
6879
6880         if (input == 0)
6881                 return val;
6882
6883         /* Translate input set to register aware inset */
6884         for (i = 0; i < RTE_DIM(inset_map); i++) {
6885                 if (input & inset_map[i].inset)
6886                         val |= inset_map[i].inset_reg;
6887         }
6888
6889         return val;
6890 }
6891
6892 static uint8_t
6893 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6894 {
6895         uint8_t i, idx = 0;
6896
6897         static const struct {
6898                 uint64_t inset;
6899                 uint32_t mask;
6900         } inset_mask_map[] = {
6901                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6902                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6903                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6904                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6905         };
6906
6907         if (!inset || !mask || !nb_elem)
6908                 return 0;
6909
6910         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6911                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6912                         mask[i] = 0;
6913                 return I40E_INSET_MASK_NUM_REG;
6914         }
6915
6916         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6917                 if (idx >= nb_elem)
6918                         break;
6919                 if (inset & inset_mask_map[i].inset) {
6920                         mask[idx] = inset_mask_map[i].mask;
6921                         idx++;
6922                 }
6923         }
6924
6925         return idx;
6926 }
6927
6928 static uint64_t
6929 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6930                             enum i40e_filter_pctype pctype)
6931 {
6932         uint64_t reg = 0;
6933
6934         if (filter == RTE_ETH_FILTER_HASH) {
6935                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6936                 reg <<= I40E_32_BIT_WIDTH;
6937                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6938         } else if (filter == RTE_ETH_FILTER_FDIR) {
6939                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6940                 reg <<= I40E_32_BIT_WIDTH;
6941                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6942         }
6943
6944         return reg;
6945 }
6946
6947 static void
6948 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6949 {
6950         uint32_t reg = I40E_READ_REG(hw, addr);
6951
6952         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6953         if (reg != val)
6954                 I40E_WRITE_REG(hw, addr, val);
6955         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6956                     (uint32_t)I40E_READ_REG(hw, addr));
6957 }
6958
6959 static int
6960 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6961                          enum i40e_filter_pctype pctype,
6962                          enum rte_filter_input_set_op op,
6963                          uint32_t *mask_reg,
6964                          uint8_t num)
6965 {
6966         uint32_t reg;
6967         uint8_t i;
6968
6969         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6970                 return -EINVAL;
6971
6972         if (op == RTE_ETH_INPUT_SET_SELECT) {
6973                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6974                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6975                                              0);
6976                         if (i >= num)
6977                                 continue;
6978                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6979                                              mask_reg[i]);
6980                 }
6981         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6982                 uint8_t j, count = 0;
6983
6984                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6985                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6986                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6987                                 count++;
6988                 }
6989                 if (count + num > I40E_INSET_MASK_NUM_REG)
6990                         return -EINVAL;
6991
6992                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6993                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6994                                              mask_reg[j]);
6995         }
6996
6997         return 0;
6998 }
6999
7000 static int
7001 i40e_set_fd_inset_mask(struct i40e_hw *hw,
7002                        enum i40e_filter_pctype pctype,
7003                        enum rte_filter_input_set_op op,
7004                        uint32_t *mask_reg,
7005                        uint8_t num)
7006 {
7007         uint32_t reg;
7008         uint8_t i;
7009
7010         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7011                 return -EINVAL;
7012
7013         if (op == RTE_ETH_INPUT_SET_SELECT) {
7014                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7015                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7016                                              0);
7017                         if (i >= num)
7018                                 continue;
7019                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7020                                              mask_reg[i]);
7021                 }
7022         } else if (op == RTE_ETH_INPUT_SET_ADD) {
7023                 uint8_t j, count = 0;
7024
7025                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7026                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
7027                         if (reg & I40E_GLQF_FD_MSK_FIELD)
7028                                 count++;
7029                 }
7030                 if (count + num > I40E_INSET_MASK_NUM_REG)
7031                         return -EINVAL;
7032
7033                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7034                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7035                                              mask_reg[j]);
7036         }
7037
7038         return 0;
7039 }
7040
7041 int
7042 i40e_filter_inset_select(struct i40e_hw *hw,
7043                          struct rte_eth_input_set_conf *conf,
7044                          enum rte_filter_type filter)
7045 {
7046         enum i40e_filter_pctype pctype;
7047         uint64_t inset_reg = 0, input_set;
7048         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
7049         uint8_t num;
7050         int ret;
7051
7052         if (!hw || !conf) {
7053                 PMD_DRV_LOG(ERR, "Invalid pointer");
7054                 return -EFAULT;
7055         }
7056
7057         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7058         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7059                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7060                             conf->flow_type);
7061                 return -EINVAL;
7062         }
7063         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
7064                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7065                 return -EINVAL;
7066         }
7067
7068         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7069                                    conf->inset_size);
7070         if (ret) {
7071                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7072                 return -EINVAL;
7073         }
7074         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
7075                 PMD_DRV_LOG(ERR, "Invalid input set");
7076                 return -EINVAL;
7077         }
7078
7079         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7080                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7081         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7082                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7083                 return -EINVAL;
7084         }
7085         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7086                                            I40E_INSET_MASK_NUM_REG);
7087         inset_reg |= i40e_translate_input_set_reg(input_set);
7088
7089         if (filter == RTE_ETH_FILTER_HASH) {
7090                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7091                                                num);
7092                 if (ret)
7093                         return -EINVAL;
7094
7095                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7096                                       (uint32_t)(inset_reg & UINT32_MAX));
7097                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7098                                      (uint32_t)((inset_reg >>
7099                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7100         } else if (filter == RTE_ETH_FILTER_FDIR) {
7101                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7102                                              num);
7103                 if (ret)
7104                         return -EINVAL;
7105
7106                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7107                                       (uint32_t)(inset_reg & UINT32_MAX));
7108                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7109                                      (uint32_t)((inset_reg >>
7110                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7111         } else {
7112                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7113                 return -EINVAL;
7114         }
7115         I40E_WRITE_FLUSH(hw);
7116
7117         return 0;
7118 }
7119
7120 static int
7121 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7122 {
7123         int ret = 0;
7124
7125         if (!hw || !info) {
7126                 PMD_DRV_LOG(ERR, "Invalid pointer");
7127                 return -EFAULT;
7128         }
7129
7130         switch (info->info_type) {
7131         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7132                 i40e_get_symmetric_hash_enable_per_port(hw,
7133                                         &(info->info.enable));
7134                 break;
7135         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7136                 ret = i40e_get_hash_filter_global_config(hw,
7137                                 &(info->info.global_conf));
7138                 break;
7139         default:
7140                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7141                                                         info->info_type);
7142                 ret = -EINVAL;
7143                 break;
7144         }
7145
7146         return ret;
7147 }
7148
7149 static int
7150 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7151 {
7152         int ret = 0;
7153
7154         if (!hw || !info) {
7155                 PMD_DRV_LOG(ERR, "Invalid pointer");
7156                 return -EFAULT;
7157         }
7158
7159         switch (info->info_type) {
7160         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7161                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7162                 break;
7163         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7164                 ret = i40e_set_hash_filter_global_config(hw,
7165                                 &(info->info.global_conf));
7166                 break;
7167         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7168                 ret = i40e_filter_inset_select(hw,
7169                                                &(info->info.input_set_conf),
7170                                                RTE_ETH_FILTER_HASH);
7171                 break;
7172
7173         default:
7174                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7175                                                         info->info_type);
7176                 ret = -EINVAL;
7177                 break;
7178         }
7179
7180         return ret;
7181 }
7182
7183 /* Operations for hash function */
7184 static int
7185 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7186                       enum rte_filter_op filter_op,
7187                       void *arg)
7188 {
7189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7190         int ret = 0;
7191
7192         switch (filter_op) {
7193         case RTE_ETH_FILTER_NOP:
7194                 break;
7195         case RTE_ETH_FILTER_GET:
7196                 ret = i40e_hash_filter_get(hw,
7197                         (struct rte_eth_hash_filter_info *)arg);
7198                 break;
7199         case RTE_ETH_FILTER_SET:
7200                 ret = i40e_hash_filter_set(hw,
7201                         (struct rte_eth_hash_filter_info *)arg);
7202                 break;
7203         default:
7204                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7205                                                                 filter_op);
7206                 ret = -ENOTSUP;
7207                 break;
7208         }
7209
7210         return ret;
7211 }
7212
7213 /*
7214  * Configure ethertype filter, which can director packet by filtering
7215  * with mac address and ether_type or only ether_type
7216  */
7217 static int
7218 i40e_ethertype_filter_set(struct i40e_pf *pf,
7219                         struct rte_eth_ethertype_filter *filter,
7220                         bool add)
7221 {
7222         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7223         struct i40e_control_filter_stats stats;
7224         uint16_t flags = 0;
7225         int ret;
7226
7227         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7228                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7229                 return -EINVAL;
7230         }
7231         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7232                 filter->ether_type == ETHER_TYPE_IPv6) {
7233                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7234                         " control packet filter.", filter->ether_type);
7235                 return -EINVAL;
7236         }
7237         if (filter->ether_type == ETHER_TYPE_VLAN)
7238                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7239                         " not supported.");
7240
7241         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7242                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7243         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7244                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7245         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7246
7247         memset(&stats, 0, sizeof(stats));
7248         ret = i40e_aq_add_rem_control_packet_filter(hw,
7249                         filter->mac_addr.addr_bytes,
7250                         filter->ether_type, flags,
7251                         pf->main_vsi->seid,
7252                         filter->queue, add, &stats, NULL);
7253
7254         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7255                          " mac_etype_used = %u, etype_used = %u,"
7256                          " mac_etype_free = %u, etype_free = %u\n",
7257                          ret, stats.mac_etype_used, stats.etype_used,
7258                          stats.mac_etype_free, stats.etype_free);
7259         if (ret < 0)
7260                 return -ENOSYS;
7261         return 0;
7262 }
7263
7264 /*
7265  * Handle operations for ethertype filter.
7266  */
7267 static int
7268 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7269                                 enum rte_filter_op filter_op,
7270                                 void *arg)
7271 {
7272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7273         int ret = 0;
7274
7275         if (filter_op == RTE_ETH_FILTER_NOP)
7276                 return ret;
7277
7278         if (arg == NULL) {
7279                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7280                             filter_op);
7281                 return -EINVAL;
7282         }
7283
7284         switch (filter_op) {
7285         case RTE_ETH_FILTER_ADD:
7286                 ret = i40e_ethertype_filter_set(pf,
7287                         (struct rte_eth_ethertype_filter *)arg,
7288                         TRUE);
7289                 break;
7290         case RTE_ETH_FILTER_DELETE:
7291                 ret = i40e_ethertype_filter_set(pf,
7292                         (struct rte_eth_ethertype_filter *)arg,
7293                         FALSE);
7294                 break;
7295         default:
7296                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7297                 ret = -ENOSYS;
7298                 break;
7299         }
7300         return ret;
7301 }
7302
7303 static int
7304 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7305                      enum rte_filter_type filter_type,
7306                      enum rte_filter_op filter_op,
7307                      void *arg)
7308 {
7309         int ret = 0;
7310
7311         if (dev == NULL)
7312                 return -EINVAL;
7313
7314         switch (filter_type) {
7315         case RTE_ETH_FILTER_NONE:
7316                 /* For global configuration */
7317                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7318                 break;
7319         case RTE_ETH_FILTER_HASH:
7320                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7321                 break;
7322         case RTE_ETH_FILTER_MACVLAN:
7323                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7324                 break;
7325         case RTE_ETH_FILTER_ETHERTYPE:
7326                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7327                 break;
7328         case RTE_ETH_FILTER_TUNNEL:
7329                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7330                 break;
7331         case RTE_ETH_FILTER_FDIR:
7332                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7333                 break;
7334         default:
7335                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7336                                                         filter_type);
7337                 ret = -EINVAL;
7338                 break;
7339         }
7340
7341         return ret;
7342 }
7343
7344 /*
7345  * Check and enable Extended Tag.
7346  * Enabling Extended Tag is important for 40G performance.
7347  */
7348 static void
7349 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7350 {
7351         uint32_t buf = 0;
7352         int ret;
7353
7354         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7355                                       PCI_DEV_CAP_REG);
7356         if (ret < 0) {
7357                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7358                             PCI_DEV_CAP_REG);
7359                 return;
7360         }
7361         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7362                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7363                 return;
7364         }
7365
7366         buf = 0;
7367         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7368                                       PCI_DEV_CTRL_REG);
7369         if (ret < 0) {
7370                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7371                             PCI_DEV_CTRL_REG);
7372                 return;
7373         }
7374         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7375                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7376                 return;
7377         }
7378         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7379         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7380                                        PCI_DEV_CTRL_REG);
7381         if (ret < 0) {
7382                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7383                             PCI_DEV_CTRL_REG);
7384                 return;
7385         }
7386 }
7387
7388 /*
7389  * As some registers wouldn't be reset unless a global hardware reset,
7390  * hardware initialization is needed to put those registers into an
7391  * expected initial state.
7392  */
7393 static void
7394 i40e_hw_init(struct rte_eth_dev *dev)
7395 {
7396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7397
7398         i40e_enable_extended_tag(dev);
7399
7400         /* clear the PF Queue Filter control register */
7401         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7402
7403         /* Disable symmetric hash per port */
7404         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7405 }
7406
7407 enum i40e_filter_pctype
7408 i40e_flowtype_to_pctype(uint16_t flow_type)
7409 {
7410         static const enum i40e_filter_pctype pctype_table[] = {
7411                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7412                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7413                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7414                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7415                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7416                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7417                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7418                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7419                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7420                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7421                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7422                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7423                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7424                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7425                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7426                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7427                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7428                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7429                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7430         };
7431
7432         return pctype_table[flow_type];
7433 }
7434
7435 uint16_t
7436 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7437 {
7438         static const uint16_t flowtype_table[] = {
7439                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7440                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7441                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7442                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7443                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7444                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7445                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7446                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7447                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7448                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7449                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7450                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7451                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7452                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7453                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7454                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7455                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7456                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7457                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7458         };
7459
7460         return flowtype_table[pctype];
7461 }
7462
7463 /*
7464  * On X710, performance number is far from the expectation on recent firmware
7465  * versions; on XL710, performance number is also far from the expectation on
7466  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7467  * mode is enabled and port MAC address is equal to the packet destination MAC
7468  * address. The fix for this issue may not be integrated in the following
7469  * firmware version. So the workaround in software driver is needed. It needs
7470  * to modify the initial values of 3 internal only registers for both X710 and
7471  * XL710. Note that the values for X710 or XL710 could be different, and the
7472  * workaround can be removed when it is fixed in firmware in the future.
7473  */
7474
7475 /* For both X710 and XL710 */
7476 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7477 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7478
7479 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7480 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7481
7482 /* For X710 */
7483 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7484 /* For XL710 */
7485 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7486 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7487
7488 static void
7489 i40e_configure_registers(struct i40e_hw *hw)
7490 {
7491         static struct {
7492                 uint32_t addr;
7493                 uint64_t val;
7494         } reg_table[] = {
7495                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7496                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7497                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7498         };
7499         uint64_t reg;
7500         uint32_t i;
7501         int ret;
7502
7503         for (i = 0; i < RTE_DIM(reg_table); i++) {
7504                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7505                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7506                                 reg_table[i].val =
7507                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7508                         else /* For X710 */
7509                                 reg_table[i].val =
7510                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7511                 }
7512
7513                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7514                                                         &reg, NULL);
7515                 if (ret < 0) {
7516                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7517                                                         reg_table[i].addr);
7518                         break;
7519                 }
7520                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7521                                                 reg_table[i].addr, reg);
7522                 if (reg == reg_table[i].val)
7523                         continue;
7524
7525                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7526                                                 reg_table[i].val, NULL);
7527                 if (ret < 0) {
7528                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7529                                 "address of 0x%"PRIx32, reg_table[i].val,
7530                                                         reg_table[i].addr);
7531                         break;
7532                 }
7533                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7534                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7535         }
7536 }
7537
7538 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7539 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7540 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7541 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7542 static int
7543 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7544 {
7545         uint32_t reg;
7546         int ret;
7547
7548         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7549                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7550                 return -EINVAL;
7551         }
7552
7553         /* Configure for double VLAN RX stripping */
7554         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7555         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7556                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7557                 ret = i40e_aq_debug_write_register(hw,
7558                                                    I40E_VSI_TSR(vsi->vsi_id),
7559                                                    reg, NULL);
7560                 if (ret < 0) {
7561                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7562                                     vsi->vsi_id);
7563                         return I40E_ERR_CONFIG;
7564                 }
7565         }
7566
7567         /* Configure for double VLAN TX insertion */
7568         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7569         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7570                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7571                 ret = i40e_aq_debug_write_register(hw,
7572                                                    I40E_VSI_L2TAGSTXVALID(
7573                                                    vsi->vsi_id), reg, NULL);
7574                 if (ret < 0) {
7575                         PMD_DRV_LOG(ERR, "Failed to update "
7576                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7577                         return I40E_ERR_CONFIG;
7578                 }
7579         }
7580
7581         return 0;
7582 }
7583
7584 /**
7585  * i40e_aq_add_mirror_rule
7586  * @hw: pointer to the hardware structure
7587  * @seid: VEB seid to add mirror rule to
7588  * @dst_id: destination vsi seid
7589  * @entries: Buffer which contains the entities to be mirrored
7590  * @count: number of entities contained in the buffer
7591  * @rule_id:the rule_id of the rule to be added
7592  *
7593  * Add a mirror rule for a given veb.
7594  *
7595  **/
7596 static enum i40e_status_code
7597 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7598                         uint16_t seid, uint16_t dst_id,
7599                         uint16_t rule_type, uint16_t *entries,
7600                         uint16_t count, uint16_t *rule_id)
7601 {
7602         struct i40e_aq_desc desc;
7603         struct i40e_aqc_add_delete_mirror_rule cmd;
7604         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7605                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7606                 &desc.params.raw;
7607         uint16_t buff_len;
7608         enum i40e_status_code status;
7609
7610         i40e_fill_default_direct_cmd_desc(&desc,
7611                                           i40e_aqc_opc_add_mirror_rule);
7612         memset(&cmd, 0, sizeof(cmd));
7613
7614         buff_len = sizeof(uint16_t) * count;
7615         desc.datalen = rte_cpu_to_le_16(buff_len);
7616         if (buff_len > 0)
7617                 desc.flags |= rte_cpu_to_le_16(
7618                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7619         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7620                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7621         cmd.num_entries = rte_cpu_to_le_16(count);
7622         cmd.seid = rte_cpu_to_le_16(seid);
7623         cmd.destination = rte_cpu_to_le_16(dst_id);
7624
7625         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7626         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7627         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7628                          "rule_id = %u"
7629                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7630                          hw->aq.asq_last_status, resp->rule_id,
7631                          resp->mirror_rules_used, resp->mirror_rules_free);
7632         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7633
7634         return status;
7635 }
7636
7637 /**
7638  * i40e_aq_del_mirror_rule
7639  * @hw: pointer to the hardware structure
7640  * @seid: VEB seid to add mirror rule to
7641  * @entries: Buffer which contains the entities to be mirrored
7642  * @count: number of entities contained in the buffer
7643  * @rule_id:the rule_id of the rule to be delete
7644  *
7645  * Delete a mirror rule for a given veb.
7646  *
7647  **/
7648 static enum i40e_status_code
7649 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7650                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7651                 uint16_t count, uint16_t rule_id)
7652 {
7653         struct i40e_aq_desc desc;
7654         struct i40e_aqc_add_delete_mirror_rule cmd;
7655         uint16_t buff_len = 0;
7656         enum i40e_status_code status;
7657         void *buff = NULL;
7658
7659         i40e_fill_default_direct_cmd_desc(&desc,
7660                                           i40e_aqc_opc_delete_mirror_rule);
7661         memset(&cmd, 0, sizeof(cmd));
7662         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7663                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7664                                                           I40E_AQ_FLAG_RD));
7665                 cmd.num_entries = count;
7666                 buff_len = sizeof(uint16_t) * count;
7667                 desc.datalen = rte_cpu_to_le_16(buff_len);
7668                 buff = (void *)entries;
7669         } else
7670                 /* rule id is filled in destination field for deleting mirror rule */
7671                 cmd.destination = rte_cpu_to_le_16(rule_id);
7672
7673         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7674                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7675         cmd.seid = rte_cpu_to_le_16(seid);
7676
7677         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7678         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7679
7680         return status;
7681 }
7682
7683 /**
7684  * i40e_mirror_rule_set
7685  * @dev: pointer to the hardware structure
7686  * @mirror_conf: mirror rule info
7687  * @sw_id: mirror rule's sw_id
7688  * @on: enable/disable
7689  *
7690  * set a mirror rule.
7691  *
7692  **/
7693 static int
7694 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7695                         struct rte_eth_mirror_conf *mirror_conf,
7696                         uint8_t sw_id, uint8_t on)
7697 {
7698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7699         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7700         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7701         struct i40e_mirror_rule *parent = NULL;
7702         uint16_t seid, dst_seid, rule_id;
7703         uint16_t i, j = 0;
7704         int ret;
7705
7706         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7707
7708         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7709                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7710                         " without veb or vfs.");
7711                 return -ENOSYS;
7712         }
7713         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7714                 PMD_DRV_LOG(ERR, "mirror table is full.");
7715                 return -ENOSPC;
7716         }
7717         if (mirror_conf->dst_pool > pf->vf_num) {
7718                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7719                                  mirror_conf->dst_pool);
7720                 return -EINVAL;
7721         }
7722
7723         seid = pf->main_vsi->veb->seid;
7724
7725         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7726                 if (sw_id <= it->index) {
7727                         mirr_rule = it;
7728                         break;
7729                 }
7730                 parent = it;
7731         }
7732         if (mirr_rule && sw_id == mirr_rule->index) {
7733                 if (on) {
7734                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7735                         return -EEXIST;
7736                 } else {
7737                         ret = i40e_aq_del_mirror_rule(hw, seid,
7738                                         mirr_rule->rule_type,
7739                                         mirr_rule->entries,
7740                                         mirr_rule->num_entries, mirr_rule->id);
7741                         if (ret < 0) {
7742                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7743                                                    " ret = %d, aq_err = %d.",
7744                                                    ret, hw->aq.asq_last_status);
7745                                 return -ENOSYS;
7746                         }
7747                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7748                         rte_free(mirr_rule);
7749                         pf->nb_mirror_rule--;
7750                         return 0;
7751                 }
7752         } else if (!on) {
7753                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7754                 return -ENOENT;
7755         }
7756
7757         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7758                                 sizeof(struct i40e_mirror_rule) , 0);
7759         if (!mirr_rule) {
7760                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7761                 return I40E_ERR_NO_MEMORY;
7762         }
7763         switch (mirror_conf->rule_type) {
7764         case ETH_MIRROR_VLAN:
7765                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7766                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7767                                 mirr_rule->entries[j] =
7768                                         mirror_conf->vlan.vlan_id[i];
7769                                 j++;
7770                         }
7771                 }
7772                 if (j == 0) {
7773                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7774                         rte_free(mirr_rule);
7775                         return -EINVAL;
7776                 }
7777                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7778                 break;
7779         case ETH_MIRROR_VIRTUAL_POOL_UP:
7780         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7781                 /* check if the specified pool bit is out of range */
7782                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7783                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7784                         rte_free(mirr_rule);
7785                         return -EINVAL;
7786                 }
7787                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7788                         if (mirror_conf->pool_mask & (1ULL << i)) {
7789                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7790                                 j++;
7791                         }
7792                 }
7793                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7794                         /* add pf vsi to entries */
7795                         mirr_rule->entries[j] = pf->main_vsi_seid;
7796                         j++;
7797                 }
7798                 if (j == 0) {
7799                         PMD_DRV_LOG(ERR, "pool is not specified.");
7800                         rte_free(mirr_rule);
7801                         return -EINVAL;
7802                 }
7803                 /* egress and ingress in aq commands means from switch but not port */
7804                 mirr_rule->rule_type =
7805                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7806                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7807                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7808                 break;
7809         case ETH_MIRROR_UPLINK_PORT:
7810                 /* egress and ingress in aq commands means from switch but not port*/
7811                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7812                 break;
7813         case ETH_MIRROR_DOWNLINK_PORT:
7814                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7815                 break;
7816         default:
7817                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7818                         mirror_conf->rule_type);
7819                 rte_free(mirr_rule);
7820                 return -EINVAL;
7821         }
7822
7823         /* If the dst_pool is equal to vf_num, consider it as PF */
7824         if (mirror_conf->dst_pool == pf->vf_num)
7825                 dst_seid = pf->main_vsi_seid;
7826         else
7827                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7828
7829         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7830                                       mirr_rule->rule_type, mirr_rule->entries,
7831                                       j, &rule_id);
7832         if (ret < 0) {
7833                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7834                                    " ret = %d, aq_err = %d.",
7835                                    ret, hw->aq.asq_last_status);
7836                 rte_free(mirr_rule);
7837                 return -ENOSYS;
7838         }
7839
7840         mirr_rule->index = sw_id;
7841         mirr_rule->num_entries = j;
7842         mirr_rule->id = rule_id;
7843         mirr_rule->dst_vsi_seid = dst_seid;
7844
7845         if (parent)
7846                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7847         else
7848                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7849
7850         pf->nb_mirror_rule++;
7851         return 0;
7852 }
7853
7854 /**
7855  * i40e_mirror_rule_reset
7856  * @dev: pointer to the device
7857  * @sw_id: mirror rule's sw_id
7858  *
7859  * reset a mirror rule.
7860  *
7861  **/
7862 static int
7863 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7864 {
7865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7867         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7868         uint16_t seid;
7869         int ret;
7870
7871         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7872
7873         seid = pf->main_vsi->veb->seid;
7874
7875         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7876                 if (sw_id == it->index) {
7877                         mirr_rule = it;
7878                         break;
7879                 }
7880         }
7881         if (mirr_rule) {
7882                 ret = i40e_aq_del_mirror_rule(hw, seid,
7883                                 mirr_rule->rule_type,
7884                                 mirr_rule->entries,
7885                                 mirr_rule->num_entries, mirr_rule->id);
7886                 if (ret < 0) {
7887                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7888                                            " status = %d, aq_err = %d.",
7889                                            ret, hw->aq.asq_last_status);
7890                         return -ENOSYS;
7891                 }
7892                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7893                 rte_free(mirr_rule);
7894                 pf->nb_mirror_rule--;
7895         } else {
7896                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7897                 return -ENOENT;
7898         }
7899         return 0;
7900 }
7901
7902 static uint64_t
7903 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
7904 {
7905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7906         uint64_t systim_cycles;
7907
7908         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
7909         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
7910                         << 32;
7911
7912         return systim_cycles;
7913 }
7914
7915 static uint64_t
7916 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
7917 {
7918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7919         uint64_t rx_tstamp;
7920
7921         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7922         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
7923                         << 32;
7924
7925         return rx_tstamp;
7926 }
7927
7928 static uint64_t
7929 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7930 {
7931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7932         uint64_t tx_tstamp;
7933
7934         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7935         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
7936                         << 32;
7937
7938         return tx_tstamp;
7939 }
7940
7941 static void
7942 i40e_start_timecounters(struct rte_eth_dev *dev)
7943 {
7944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7945         struct i40e_adapter *adapter =
7946                         (struct i40e_adapter *)dev->data->dev_private;
7947         struct rte_eth_link link;
7948         uint32_t tsync_inc_l;
7949         uint32_t tsync_inc_h;
7950
7951         /* Get current link speed. */
7952         memset(&link, 0, sizeof(link));
7953         i40e_dev_link_update(dev, 1);
7954         rte_i40e_dev_atomic_read_link_status(dev, &link);
7955
7956         switch (link.link_speed) {
7957         case ETH_LINK_SPEED_40G:
7958                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7959                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7960                 break;
7961         case ETH_LINK_SPEED_10G:
7962                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7963                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7964                 break;
7965         case ETH_LINK_SPEED_1000:
7966                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7967                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7968                 break;
7969         default:
7970                 tsync_inc_l = 0x0;
7971                 tsync_inc_h = 0x0;
7972         }
7973
7974         /* Set the timesync increment value. */
7975         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7976         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7977
7978         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7979         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7980         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7981
7982         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7983         adapter->systime_tc.cc_shift = 0;
7984         adapter->systime_tc.nsec_mask = 0;
7985
7986         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7987         adapter->rx_tstamp_tc.cc_shift = 0;
7988         adapter->rx_tstamp_tc.nsec_mask = 0;
7989
7990         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7991         adapter->tx_tstamp_tc.cc_shift = 0;
7992         adapter->tx_tstamp_tc.nsec_mask = 0;
7993 }
7994
7995 static int
7996 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7997 {
7998         struct i40e_adapter *adapter =
7999                         (struct i40e_adapter *)dev->data->dev_private;
8000
8001         adapter->systime_tc.nsec += delta;
8002         adapter->rx_tstamp_tc.nsec += delta;
8003         adapter->tx_tstamp_tc.nsec += delta;
8004
8005         return 0;
8006 }
8007
8008 static int
8009 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8010 {
8011         uint64_t ns;
8012         struct i40e_adapter *adapter =
8013                         (struct i40e_adapter *)dev->data->dev_private;
8014
8015         ns = rte_timespec_to_ns(ts);
8016
8017         /* Set the timecounters to a new value. */
8018         adapter->systime_tc.nsec = ns;
8019         adapter->rx_tstamp_tc.nsec = ns;
8020         adapter->tx_tstamp_tc.nsec = ns;
8021
8022         return 0;
8023 }
8024
8025 static int
8026 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8027 {
8028         uint64_t ns, systime_cycles;
8029         struct i40e_adapter *adapter =
8030                         (struct i40e_adapter *)dev->data->dev_private;
8031
8032         systime_cycles = i40e_read_systime_cyclecounter(dev);
8033         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8034         *ts = rte_ns_to_timespec(ns);
8035
8036         return 0;
8037 }
8038
8039 static int
8040 i40e_timesync_enable(struct rte_eth_dev *dev)
8041 {
8042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8043         uint32_t tsync_ctl_l;
8044         uint32_t tsync_ctl_h;
8045
8046         /* Stop the timesync system time. */
8047         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8048         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8049         /* Reset the timesync system time value. */
8050         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8051         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8052
8053         i40e_start_timecounters(dev);
8054
8055         /* Clear timesync registers. */
8056         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8057         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8058         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8059         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8060         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8061         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8062
8063         /* Enable timestamping of PTP packets. */
8064         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8065         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8066
8067         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8068         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8069         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8070
8071         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8072         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8073
8074         return 0;
8075 }
8076
8077 static int
8078 i40e_timesync_disable(struct rte_eth_dev *dev)
8079 {
8080         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8081         uint32_t tsync_ctl_l;
8082         uint32_t tsync_ctl_h;
8083
8084         /* Disable timestamping of transmitted PTP packets. */
8085         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8086         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8087
8088         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8089         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8090
8091         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8092         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8093
8094         /* Reset the timesync increment value. */
8095         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8096         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8097
8098         return 0;
8099 }
8100
8101 static int
8102 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8103                                 struct timespec *timestamp, uint32_t flags)
8104 {
8105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8106         struct i40e_adapter *adapter =
8107                 (struct i40e_adapter *)dev->data->dev_private;
8108
8109         uint32_t sync_status;
8110         uint32_t index = flags & 0x03;
8111         uint64_t rx_tstamp_cycles;
8112         uint64_t ns;
8113
8114         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8115         if ((sync_status & (1 << index)) == 0)
8116                 return -EINVAL;
8117
8118         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8119         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8120         *timestamp = rte_ns_to_timespec(ns);
8121
8122         return 0;
8123 }
8124
8125 static int
8126 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8127                                 struct timespec *timestamp)
8128 {
8129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8130         struct i40e_adapter *adapter =
8131                 (struct i40e_adapter *)dev->data->dev_private;
8132
8133         uint32_t sync_status;
8134         uint64_t tx_tstamp_cycles;
8135         uint64_t ns;
8136
8137         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8138         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8139                 return -EINVAL;
8140
8141         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8142         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8143         *timestamp = rte_ns_to_timespec(ns);
8144
8145         return 0;
8146 }
8147
8148 /*
8149  * i40e_parse_dcb_configure - parse dcb configure from user
8150  * @dev: the device being configured
8151  * @dcb_cfg: pointer of the result of parse
8152  * @*tc_map: bit map of enabled traffic classes
8153  *
8154  * Returns 0 on success, negative value on failure
8155  */
8156 static int
8157 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8158                          struct i40e_dcbx_config *dcb_cfg,
8159                          uint8_t *tc_map)
8160 {
8161         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8162         uint8_t i, tc_bw, bw_lf;
8163
8164         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8165
8166         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8167         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8168                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8169                 return -EINVAL;
8170         }
8171
8172         /* assume each tc has the same bw */
8173         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8174         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8175                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8176         /* to ensure the sum of tcbw is equal to 100 */
8177         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8178         for (i = 0; i < bw_lf; i++)
8179                 dcb_cfg->etscfg.tcbwtable[i]++;
8180
8181         /* assume each tc has the same Transmission Selection Algorithm */
8182         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8183                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8184
8185         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8186                 dcb_cfg->etscfg.prioritytable[i] =
8187                                 dcb_rx_conf->dcb_tc[i];
8188
8189         /* FW needs one App to configure HW */
8190         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8191         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8192         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8193         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8194
8195         if (dcb_rx_conf->nb_tcs == 0)
8196                 *tc_map = 1; /* tc0 only */
8197         else
8198                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8199
8200         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8201                 dcb_cfg->pfc.willing = 0;
8202                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8203                 dcb_cfg->pfc.pfcenable = *tc_map;
8204         }
8205         return 0;
8206 }
8207
8208
8209 static enum i40e_status_code
8210 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8211                               struct i40e_aqc_vsi_properties_data *info,
8212                               uint8_t enabled_tcmap)
8213 {
8214         enum i40e_status_code ret;
8215         int i, total_tc = 0;
8216         uint16_t qpnum_per_tc, bsf, qp_idx;
8217         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8218
8219         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8220         if (ret != I40E_SUCCESS)
8221                 return ret;
8222
8223         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8224                 if (enabled_tcmap & (1 << i))
8225                         total_tc++;
8226         }
8227         if (total_tc == 0)
8228                 total_tc = 1;
8229         vsi->enabled_tc = enabled_tcmap;
8230
8231         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8232         /* Number of queues per enabled TC */
8233         if (qpnum_per_tc == 0) {
8234                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8235                 return I40E_ERR_INVALID_QP_ID;
8236         }
8237         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8238                                 I40E_MAX_Q_PER_TC);
8239         bsf = rte_bsf32(qpnum_per_tc);
8240
8241         /**
8242          * Configure TC and queue mapping parameters, for enabled TC,
8243          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8244          * default queue will serve it.
8245          */
8246         qp_idx = 0;
8247         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8248                 if (vsi->enabled_tc & (1 << i)) {
8249                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8250                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8251                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8252                         qp_idx += qpnum_per_tc;
8253                 } else
8254                         info->tc_mapping[i] = 0;
8255         }
8256
8257         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8258         if (vsi->type == I40E_VSI_SRIOV) {
8259                 info->mapping_flags |=
8260                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8261                 for (i = 0; i < vsi->nb_qps; i++)
8262                         info->queue_mapping[i] =
8263                                 rte_cpu_to_le_16(vsi->base_queue + i);
8264         } else {
8265                 info->mapping_flags |=
8266                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8267                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8268         }
8269         info->valid_sections |=
8270                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8271
8272         return I40E_SUCCESS;
8273 }
8274
8275 /*
8276  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8277  * @vsi: VSI to be configured
8278  * @tc_map: enabled TC bitmap
8279  *
8280  * Returns 0 on success, negative value on failure
8281  */
8282 static enum i40e_status_code
8283 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8284 {
8285         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8286         struct i40e_vsi_context ctxt;
8287         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8288         enum i40e_status_code ret = I40E_SUCCESS;
8289         int i;
8290
8291         /* Check if enabled_tc is same as existing or new TCs */
8292         if (vsi->enabled_tc == tc_map)
8293                 return ret;
8294
8295         /* configure tc bandwidth */
8296         memset(&bw_data, 0, sizeof(bw_data));
8297         bw_data.tc_valid_bits = tc_map;
8298         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8299         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8300                 if (tc_map & BIT_ULL(i))
8301                         bw_data.tc_bw_credits[i] = 1;
8302         }
8303         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8304         if (ret) {
8305                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8306                         " per TC failed = %d",
8307                         hw->aq.asq_last_status);
8308                 goto out;
8309         }
8310         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8311                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8312
8313         /* Update Queue Pairs Mapping for currently enabled UPs */
8314         ctxt.seid = vsi->seid;
8315         ctxt.pf_num = hw->pf_id;
8316         ctxt.vf_num = 0;
8317         ctxt.uplink_seid = vsi->uplink_seid;
8318         ctxt.info = vsi->info;
8319         i40e_get_cap(hw);
8320         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8321         if (ret)
8322                 goto out;
8323
8324         /* Update the VSI after updating the VSI queue-mapping information */
8325         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8326         if (ret) {
8327                 PMD_INIT_LOG(ERR, "Failed to configure "
8328                             "TC queue mapping = %d",
8329                             hw->aq.asq_last_status);
8330                 goto out;
8331         }
8332         /* update the local VSI info with updated queue map */
8333         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8334                                         sizeof(vsi->info.tc_mapping));
8335         (void)rte_memcpy(&vsi->info.queue_mapping,
8336                         &ctxt.info.queue_mapping,
8337                 sizeof(vsi->info.queue_mapping));
8338         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8339         vsi->info.valid_sections = 0;
8340
8341         /* query and update current VSI BW information */
8342         ret = i40e_vsi_get_bw_config(vsi);
8343         if (ret) {
8344                 PMD_INIT_LOG(ERR,
8345                          "Failed updating vsi bw info, err %s aq_err %s",
8346                          i40e_stat_str(hw, ret),
8347                          i40e_aq_str(hw, hw->aq.asq_last_status));
8348                 goto out;
8349         }
8350
8351         vsi->enabled_tc = tc_map;
8352
8353 out:
8354         return ret;
8355 }
8356
8357 /*
8358  * i40e_dcb_hw_configure - program the dcb setting to hw
8359  * @pf: pf the configuration is taken on
8360  * @new_cfg: new configuration
8361  * @tc_map: enabled TC bitmap
8362  *
8363  * Returns 0 on success, negative value on failure
8364  */
8365 static enum i40e_status_code
8366 i40e_dcb_hw_configure(struct i40e_pf *pf,
8367                       struct i40e_dcbx_config *new_cfg,
8368                       uint8_t tc_map)
8369 {
8370         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8371         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8372         struct i40e_vsi *main_vsi = pf->main_vsi;
8373         struct i40e_vsi_list *vsi_list;
8374         enum i40e_status_code ret;
8375         int i;
8376         uint32_t val;
8377
8378         /* Use the FW API if FW > v4.4*/
8379         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8380               (hw->aq.fw_maj_ver >= 5))) {
8381                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8382                                   " to configure DCB");
8383                 return I40E_ERR_FIRMWARE_API_VERSION;
8384         }
8385
8386         /* Check if need reconfiguration */
8387         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8388                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8389                 return I40E_SUCCESS;
8390         }
8391
8392         /* Copy the new config to the current config */
8393         *old_cfg = *new_cfg;
8394         old_cfg->etsrec = old_cfg->etscfg;
8395         ret = i40e_set_dcb_config(hw);
8396         if (ret) {
8397                 PMD_INIT_LOG(ERR,
8398                          "Set DCB Config failed, err %s aq_err %s\n",
8399                          i40e_stat_str(hw, ret),
8400                          i40e_aq_str(hw, hw->aq.asq_last_status));
8401                 return ret;
8402         }
8403         /* set receive Arbiter to RR mode and ETS scheme by default */
8404         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8405                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8406                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8407                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8408                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8409                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8410                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8411                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8412                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8413                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8414                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8415                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8416                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8417         }
8418         /* get local mib to check whether it is configured correctly */
8419         /* IEEE mode */
8420         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8421         /* Get Local DCB Config */
8422         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8423                                      &hw->local_dcbx_config);
8424
8425         /* Update each VSI */
8426         i40e_vsi_config_tc(main_vsi, tc_map);
8427         if (main_vsi->veb) {
8428                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8429                         /* Beside main VSI, only enable default
8430                          * TC for other VSIs
8431                          */
8432                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8433                                                 I40E_DEFAULT_TCMAP);
8434                         if (ret)
8435                                 PMD_INIT_LOG(WARNING,
8436                                          "Failed configuring TC for VSI seid=%d\n",
8437                                          vsi_list->vsi->seid);
8438                         /* continue */
8439                 }
8440         }
8441         return I40E_SUCCESS;
8442 }
8443
8444 /*
8445  * i40e_dcb_init_configure - initial dcb config
8446  * @dev: device being configured
8447  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8448  *
8449  * Returns 0 on success, negative value on failure
8450  */
8451 static int
8452 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8453 {
8454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8455         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8456         int ret = 0;
8457
8458         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8459                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8460                 return -ENOTSUP;
8461         }
8462
8463         /* DCB initialization:
8464          * Update DCB configuration from the Firmware and configure
8465          * LLDP MIB change event.
8466          */
8467         if (sw_dcb == TRUE) {
8468                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8469                 if (ret != I40E_SUCCESS)
8470                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8471
8472                 ret = i40e_init_dcb(hw);
8473                 /* if sw_dcb, lldp agent is stopped, the return from
8474                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8475                  * adminq status.
8476                  */
8477                 if (ret != I40E_SUCCESS &&
8478                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8479                         memset(&hw->local_dcbx_config, 0,
8480                                 sizeof(struct i40e_dcbx_config));
8481                         /* set dcb default configuration */
8482                         hw->local_dcbx_config.etscfg.willing = 0;
8483                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8484                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8485                         hw->local_dcbx_config.etscfg.tsatable[0] =
8486                                                 I40E_IEEE_TSA_ETS;
8487                         hw->local_dcbx_config.etsrec =
8488                                 hw->local_dcbx_config.etscfg;
8489                         hw->local_dcbx_config.pfc.willing = 0;
8490                         hw->local_dcbx_config.pfc.pfccap =
8491                                                 I40E_MAX_TRAFFIC_CLASS;
8492                         /* FW needs one App to configure HW */
8493                         hw->local_dcbx_config.numapps = 1;
8494                         hw->local_dcbx_config.app[0].selector =
8495                                                 I40E_APP_SEL_ETHTYPE;
8496                         hw->local_dcbx_config.app[0].priority = 3;
8497                         hw->local_dcbx_config.app[0].protocolid =
8498                                                 I40E_APP_PROTOID_FCOE;
8499                         ret = i40e_set_dcb_config(hw);
8500                         if (ret) {
8501                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8502                                         " err = %d, aq_err = %d.", ret,
8503                                           hw->aq.asq_last_status);
8504                                 return -ENOSYS;
8505                         }
8506                 } else {
8507                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8508                                           " aq_err = %d.", ret,
8509                                           hw->aq.asq_last_status);
8510                         return -ENOTSUP;
8511                 }
8512         } else {
8513                 ret = i40e_aq_start_lldp(hw, NULL);
8514                 if (ret != I40E_SUCCESS)
8515                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8516
8517                 ret = i40e_init_dcb(hw);
8518                 if (!ret) {
8519                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8520                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8521                                                   " DCBX offload.");
8522                                 return -ENOTSUP;
8523                         }
8524                 } else {
8525                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8526                                           " aq_err = %d.", ret,
8527                                           hw->aq.asq_last_status);
8528                         return -ENOTSUP;
8529                 }
8530         }
8531         return 0;
8532 }
8533
8534 /*
8535  * i40e_dcb_setup - setup dcb related config
8536  * @dev: device being configured
8537  *
8538  * Returns 0 on success, negative value on failure
8539  */
8540 static int
8541 i40e_dcb_setup(struct rte_eth_dev *dev)
8542 {
8543         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8544         struct i40e_dcbx_config dcb_cfg;
8545         uint8_t tc_map = 0;
8546         int ret = 0;
8547
8548         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8549                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8550                 return -ENOTSUP;
8551         }
8552
8553         if (pf->vf_num != 0 ||
8554             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8555                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8556
8557         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8558         if (ret) {
8559                 PMD_INIT_LOG(ERR, "invalid dcb config");
8560                 return -EINVAL;
8561         }
8562         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8563         if (ret) {
8564                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8565                 return -ENOSYS;
8566         }
8567
8568         return 0;
8569 }
8570
8571 static int
8572 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8573                       struct rte_eth_dcb_info *dcb_info)
8574 {
8575         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8576         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8577         struct i40e_vsi *vsi = pf->main_vsi;
8578         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8579         uint16_t bsf, tc_mapping;
8580         int i;
8581
8582         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8583                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8584         else
8585                 dcb_info->nb_tcs = 1;
8586         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8587                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8588         for (i = 0; i < dcb_info->nb_tcs; i++)
8589                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8590
8591         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8592                 if (vsi->enabled_tc & (1 << i)) {
8593                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8594                         /* only main vsi support multi TCs */
8595                         dcb_info->tc_queue.tc_rxq[0][i].base =
8596                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8597                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8598                         dcb_info->tc_queue.tc_txq[0][i].base =
8599                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8600                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8601                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8602                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8603                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8604                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8605                 }
8606         }
8607
8608         return 0;
8609 }
8610
8611 static int
8612 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8613 {
8614         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8616         uint16_t interval =
8617                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8618         uint16_t msix_intr;
8619
8620         msix_intr = intr_handle->intr_vec[queue_id];
8621         if (msix_intr == I40E_MISC_VEC_ID)
8622                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8623                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8624                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8625                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8626                                (interval <<
8627                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8628         else
8629                 I40E_WRITE_REG(hw,
8630                                I40E_PFINT_DYN_CTLN(msix_intr -
8631                                                    I40E_RX_VEC_START),
8632                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8633                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8634                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8635                                (interval <<
8636                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8637
8638         I40E_WRITE_FLUSH(hw);
8639         rte_intr_enable(&dev->pci_dev->intr_handle);
8640
8641         return 0;
8642 }
8643
8644 static int
8645 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8646 {
8647         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8648         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8649         uint16_t msix_intr;
8650
8651         msix_intr = intr_handle->intr_vec[queue_id];
8652         if (msix_intr == I40E_MISC_VEC_ID)
8653                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8654         else
8655                 I40E_WRITE_REG(hw,
8656                                I40E_PFINT_DYN_CTLN(msix_intr -
8657                                                    I40E_RX_VEC_START),
8658                                0);
8659         I40E_WRITE_FLUSH(hw);
8660
8661         return 0;
8662 }