drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Flow control default high water */
  99 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 100
 101 /* Flow control default low water */
 102 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 257 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 259 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 260 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_stats *stats);
 262 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 263                                struct rte_eth_xstat *xstats, unsigned n);
 264 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 265                                      struct rte_eth_xstat_name *xstats_names,
 266                                      unsigned limit);
 267 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 268 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id,
 270                                             uint8_t stat_idx,
 271                                             uint8_t is_rx);
 272 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 273                                 char *fw_version, size_t fw_size);
 274 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 275                               struct rte_eth_dev_info *dev_info);
 276 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 277                                 uint16_t vlan_id,
 278                                 int on);
 279 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 280                               enum rte_vlan_type vlan_type,
 281                               uint16_t tpid);
 282 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 283 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 284                                       uint16_t queue,
 285                                       int on);
 286 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 287 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 288 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 289 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 292                               struct rte_eth_fc_conf *fc_conf);
 293 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 294                                        struct rte_eth_pfc_conf *pfc_conf);
 295 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 296                             struct ether_addr *mac_addr,
 297                             uint32_t index,
 298                             uint32_t pool);
 299 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 300 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 301                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                     uint16_t reta_size);
 303 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 304                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 305                                    uint16_t reta_size);
 306
 307 static int i40e_get_cap(struct i40e_hw *hw);
 308 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 309 static int i40e_pf_setup(struct i40e_pf *pf);
 310 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 311 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 312 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 313 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 314 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 315                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 316 static void i40e_stat_update_48(struct i40e_hw *hw,
 317                                uint32_t hireg,
 318                                uint32_t loreg,
 319                                bool offset_loaded,
 320                                uint64_t *offset,
 321                                uint64_t *stat);
 322 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 323 static void i40e_dev_interrupt_handler(void *param);
 324 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 325                                 uint32_t base, uint32_t num);
 326 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 327 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 328                         uint32_t base);
 329 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 330                         uint16_t num);
 331 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 332 static int i40e_veb_release(struct i40e_veb *veb);
 333 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 334                                                 struct i40e_vsi *vsi);
 335 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 336 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 337 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 338                                              struct i40e_macvlan_filter *mv_f,
 339                                              int num,
 340                                              uint16_t vlan);
 341 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 342 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 343                                     struct rte_eth_rss_conf *rss_conf);
 344 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 345                                       struct rte_eth_rss_conf *rss_conf);
 346 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 347                                         struct rte_eth_udp_tunnel *udp_tunnel);
 348 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 349                                         struct rte_eth_udp_tunnel *udp_tunnel);
 350 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 351 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 352                                 enum rte_filter_op filter_op,
 353                                 void *arg);
 354 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 355                                 enum rte_filter_type filter_type,
 356                                 enum rte_filter_op filter_op,
 357                                 void *arg);
 358 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 359                                   struct rte_eth_dcb_info *dcb_info);
 360 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 361 static void i40e_configure_registers(struct i40e_hw *hw);
 362 static void i40e_hw_init(struct rte_eth_dev *dev);
 363 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 364 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 365                         struct rte_eth_mirror_conf *mirror_conf,
 366                         uint8_t sw_id, uint8_t on);
 367 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 368
 369 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 371 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 372                                            struct timespec *timestamp,
 373                                            uint32_t flags);
 374 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp);
 376 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 377
 378 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 379
 380 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 381                                    struct timespec *timestamp);
 382 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 383                                     const struct timespec *timestamp);
 384
 385 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 386                                          uint16_t queue_id);
 387 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 388                                           uint16_t queue_id);
 389
 390 static int i40e_get_regs(struct rte_eth_dev *dev,
 391                          struct rte_dev_reg_info *regs);
 392
 393 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 394
 395 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 396                            struct rte_dev_eeprom_info *eeprom);
 397
 398 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 399                                       struct ether_addr *mac_addr);
 400
 401 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 402
 403 static int i40e_ethertype_filter_convert(
 404         const struct rte_eth_ethertype_filter *input,
 405         struct i40e_ethertype_filter *filter);
 406 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 407                                    struct i40e_ethertype_filter *filter);
 408
 409 static int i40e_tunnel_filter_convert(
 410         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 411         struct i40e_tunnel_filter *tunnel_filter);
 412 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 413                                 struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 415
 416 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 417 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 418 static void i40e_filter_restore(struct i40e_pf *pf);
 419 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 420
 421 int i40e_logtype_init;
 422 int i40e_logtype_driver;
 423
 424 static const struct rte_pci_id pci_id_i40e_map[] = {
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 445         { .vendor_id = 0, /* sentinel */ },
 446 };
 447
 448 static const struct eth_dev_ops i40e_eth_dev_ops = {
 449         .dev_configure                = i40e_dev_configure,
 450         .dev_start                    = i40e_dev_start,
 451         .dev_stop                     = i40e_dev_stop,
 452         .dev_close                    = i40e_dev_close,
 453         .dev_reset                    = i40e_dev_reset,
 454         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 455         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 456         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 457         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 458         .dev_set_link_up              = i40e_dev_set_link_up,
 459         .dev_set_link_down            = i40e_dev_set_link_down,
 460         .link_update                  = i40e_dev_link_update,
 461         .stats_get                    = i40e_dev_stats_get,
 462         .xstats_get                   = i40e_dev_xstats_get,
 463         .xstats_get_names             = i40e_dev_xstats_get_names,
 464         .stats_reset                  = i40e_dev_stats_reset,
 465         .xstats_reset                 = i40e_dev_stats_reset,
 466         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 467         .fw_version_get               = i40e_fw_version_get,
 468         .dev_infos_get                = i40e_dev_info_get,
 469         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 470         .vlan_filter_set              = i40e_vlan_filter_set,
 471         .vlan_tpid_set                = i40e_vlan_tpid_set,
 472         .vlan_offload_set             = i40e_vlan_offload_set,
 473         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 474         .vlan_pvid_set                = i40e_vlan_pvid_set,
 475         .rx_queue_start               = i40e_dev_rx_queue_start,
 476         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 477         .tx_queue_start               = i40e_dev_tx_queue_start,
 478         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 479         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 480         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 482         .rx_queue_release             = i40e_dev_rx_queue_release,
 483         .rx_queue_count               = i40e_dev_rx_queue_count,
 484         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 485         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 486         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 487         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 488         .tx_queue_release             = i40e_dev_tx_queue_release,
 489         .dev_led_on                   = i40e_dev_led_on,
 490         .dev_led_off                  = i40e_dev_led_off,
 491         .flow_ctrl_get                = i40e_flow_ctrl_get,
 492         .flow_ctrl_set                = i40e_flow_ctrl_set,
 493         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 494         .mac_addr_add                 = i40e_macaddr_add,
 495         .mac_addr_remove              = i40e_macaddr_remove,
 496         .reta_update                  = i40e_dev_rss_reta_update,
 497         .reta_query                   = i40e_dev_rss_reta_query,
 498         .rss_hash_update              = i40e_dev_rss_hash_update,
 499         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 500         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 501         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 502         .filter_ctrl                  = i40e_dev_filter_ctrl,
 503         .rxq_info_get                 = i40e_rxq_info_get,
 504         .txq_info_get                 = i40e_txq_info_get,
 505         .mirror_rule_set              = i40e_mirror_rule_set,
 506         .mirror_rule_reset            = i40e_mirror_rule_reset,
 507         .timesync_enable              = i40e_timesync_enable,
 508         .timesync_disable             = i40e_timesync_disable,
 509         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 510         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 511         .get_dcb_info                 = i40e_dev_get_dcb_info,
 512         .timesync_adjust_time         = i40e_timesync_adjust_time,
 513         .timesync_read_time           = i40e_timesync_read_time,
 514         .timesync_write_time          = i40e_timesync_write_time,
 515         .get_reg                      = i40e_get_regs,
 516         .get_eeprom_length            = i40e_get_eeprom_length,
 517         .get_eeprom                   = i40e_get_eeprom,
 518         .mac_addr_set                 = i40e_set_default_mac_addr,
 519         .mtu_set                      = i40e_dev_mtu_set,
 520         .tm_ops_get                   = i40e_tm_ops_get,
 521 };
 522
 523 /* store statistics names and its offset in stats structure */
 524 struct rte_i40e_xstats_name_off {
 525         char name[RTE_ETH_XSTATS_NAME_SIZE];
 526         unsigned offset;
 527 };
 528
 529 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 530         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 531         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 532         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 533         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 534         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 535                 rx_unknown_protocol)},
 536         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 537         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 538         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 539         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 540 };
 541
 542 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 543                 sizeof(rte_i40e_stats_strings[0]))
 544
 545 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 546         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 547                 tx_dropped_link_down)},
 548         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 549         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 550                 illegal_bytes)},
 551         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 552         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_local_faults)},
 554         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_remote_faults)},
 556         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_length_errors)},
 558         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 559         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 560         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 561         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 562         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 563         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_127)},
 565         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_255)},
 567         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_511)},
 569         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1023)},
 571         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1522)},
 573         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_big)},
 575         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_undersize)},
 577         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_oversize)},
 579         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 580                 mac_short_packet_dropped)},
 581         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_fragments)},
 583         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 584         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 585         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_127)},
 587         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_255)},
 589         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_511)},
 591         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1023)},
 593         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1522)},
 595         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_big)},
 597         {"rx_flow_director_atr_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 599         {"rx_flow_director_sb_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 601         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_status)},
 603         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_status)},
 605         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 tx_lpi_count)},
 607         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 rx_lpi_count)},
 609 };
 610
 611 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 612                 sizeof(rte_i40e_hw_port_strings[0]))
 613
 614 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 615         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xon_rx)},
 617         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xoff_rx)},
 619 };
 620
 621 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 622                 sizeof(rte_i40e_rxq_prio_strings[0]))
 623
 624 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 625         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_tx)},
 627         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xoff_tx)},
 629         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xon_2_xoff)},
 631 };
 632
 633 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 634                 sizeof(rte_i40e_txq_prio_strings[0]))
 635
 636 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 637         struct rte_pci_device *pci_dev)
 638 {
 639         return rte_eth_dev_pci_generic_probe(pci_dev,
 640                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 641 }
 642
 643 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 644 {
 645         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 646 }
 647
 648 static struct rte_pci_driver rte_i40e_pmd = {
 649         .id_table = pci_id_i40e_map,
 650         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 651         .probe = eth_i40e_pci_probe,
 652         .remove = eth_i40e_pci_remove,
 653 };
 654
 655 static inline int
 656 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 657                                      struct rte_eth_link *link)
 658 {
 659         struct rte_eth_link *dst = link;
 660         struct rte_eth_link *src = &(dev->data->dev_link);
 661
 662         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 663                                         *(uint64_t *)src) == 0)
 664                 return -1;
 665
 666         return 0;
 667 }
 668
 669 static inline int
 670 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 671                                       struct rte_eth_link *link)
 672 {
 673         struct rte_eth_link *dst = &(dev->data->dev_link);
 674         struct rte_eth_link *src = link;
 675
 676         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 677                                         *(uint64_t *)src) == 0)
 678                 return -1;
 679
 680         return 0;
 681 }
 682
 683 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 684 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 685 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 686
 687 #ifndef I40E_GLQF_ORT
 688 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 689 #endif
 690 #ifndef I40E_GLQF_PIT
 691 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 692 #endif
 693 #ifndef I40E_GLQF_L3_MAP
 694 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 695 #endif
 696
 697 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 698 {
 699         /*
 700          * Initialize registers for flexible payload, which should be set by NVM.
 701          * This should be removed from code once it is fixed in NVM.
 702          */
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 713         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 714         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 715
 716         /* Initialize registers for parsing packet type of QinQ */
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 718         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 719 }
 720
 721 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 722
 723 /*
 724  * Add a ethertype filter to drop all flow control frames transmitted
 725  * from VSIs.
 726 */
 727 static void
 728 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 729 {
 730         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 731         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 732                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 733                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 734         int ret;
 735
 736         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 737                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 738                                 pf->main_vsi_seid, 0,
 739                                 TRUE, NULL, NULL);
 740         if (ret)
 741                 PMD_INIT_LOG(ERR,
 742                         "Failed to add filter to drop flow control frames from VSIs.");
 743 }
 744
 745 static int
 746 floating_veb_list_handler(__rte_unused const char *key,
 747                           const char *floating_veb_value,
 748                           void *opaque)
 749 {
 750         int idx = 0;
 751         unsigned int count = 0;
 752         char *end = NULL;
 753         int min, max;
 754         bool *vf_floating_veb = opaque;
 755
 756         while (isblank(*floating_veb_value))
 757                 floating_veb_value++;
 758
 759         /* Reset floating VEB configuration for VFs */
 760         for (idx = 0; idx < I40E_MAX_VF; idx++)
 761                 vf_floating_veb[idx] = false;
 762
 763         min = I40E_MAX_VF;
 764         do {
 765                 while (isblank(*floating_veb_value))
 766                         floating_veb_value++;
 767                 if (*floating_veb_value == '\0')
 768                         return -1;
 769                 errno = 0;
 770                 idx = strtoul(floating_veb_value, &end, 10);
 771                 if (errno || end == NULL)
 772                         return -1;
 773                 while (isblank(*end))
 774                         end++;
 775                 if (*end == '-') {
 776                         min = idx;
 777                 } else if ((*end == ';') || (*end == '\0')) {
 778                         max = idx;
 779                         if (min == I40E_MAX_VF)
 780                                 min = idx;
 781                         if (max >= I40E_MAX_VF)
 782                                 max = I40E_MAX_VF - 1;
 783                         for (idx = min; idx <= max; idx++) {
 784                                 vf_floating_veb[idx] = true;
 785                                 count++;
 786                         }
 787                         min = I40E_MAX_VF;
 788                 } else {
 789                         return -1;
 790                 }
 791                 floating_veb_value = end + 1;
 792         } while (*end != '\0');
 793
 794         if (count == 0)
 795                 return -1;
 796
 797         return 0;
 798 }
 799
 800 static void
 801 config_vf_floating_veb(struct rte_devargs *devargs,
 802                        uint16_t floating_veb,
 803                        bool *vf_floating_veb)
 804 {
 805         struct rte_kvargs *kvlist;
 806         int i;
 807         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 808
 809         if (!floating_veb)
 810                 return;
 811         /* All the VFs attach to the floating VEB by default
 812          * when the floating VEB is enabled.
 813          */
 814         for (i = 0; i < I40E_MAX_VF; i++)
 815                 vf_floating_veb[i] = true;
 816
 817         if (devargs == NULL)
 818                 return;
 819
 820         kvlist = rte_kvargs_parse(devargs->args, NULL);
 821         if (kvlist == NULL)
 822                 return;
 823
 824         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 825                 rte_kvargs_free(kvlist);
 826                 return;
 827         }
 828         /* When the floating_veb_list parameter exists, all the VFs
 829          * will attach to the legacy VEB firstly, then configure VFs
 830          * to the floating VEB according to the floating_veb_list.
 831          */
 832         if (rte_kvargs_process(kvlist, floating_veb_list,
 833                                floating_veb_list_handler,
 834                                vf_floating_veb) < 0) {
 835                 rte_kvargs_free(kvlist);
 836                 return;
 837         }
 838         rte_kvargs_free(kvlist);
 839 }
 840
 841 static int
 842 i40e_check_floating_handler(__rte_unused const char *key,
 843                             const char *value,
 844                             __rte_unused void *opaque)
 845 {
 846         if (strcmp(value, "1"))
 847                 return -1;
 848
 849         return 0;
 850 }
 851
 852 static int
 853 is_floating_veb_supported(struct rte_devargs *devargs)
 854 {
 855         struct rte_kvargs *kvlist;
 856         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 857
 858         if (devargs == NULL)
 859                 return 0;
 860
 861         kvlist = rte_kvargs_parse(devargs->args, NULL);
 862         if (kvlist == NULL)
 863                 return 0;
 864
 865         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 866                 rte_kvargs_free(kvlist);
 867                 return 0;
 868         }
 869         /* Floating VEB is enabled when there's key-value:
 870          * enable_floating_veb=1
 871          */
 872         if (rte_kvargs_process(kvlist, floating_veb_key,
 873                                i40e_check_floating_handler, NULL) < 0) {
 874                 rte_kvargs_free(kvlist);
 875                 return 0;
 876         }
 877         rte_kvargs_free(kvlist);
 878
 879         return 1;
 880 }
 881
 882 static void
 883 config_floating_veb(struct rte_eth_dev *dev)
 884 {
 885         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 886         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 888
 889         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 890
 891         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 892                 pf->floating_veb =
 893                         is_floating_veb_supported(pci_dev->device.devargs);
 894                 config_vf_floating_veb(pci_dev->device.devargs,
 895                                        pf->floating_veb,
 896                                        pf->floating_veb_list);
 897         } else {
 898                 pf->floating_veb = false;
 899         }
 900 }
 901
 902 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 903 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 904
 905 static int
 906 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 907 {
 908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 909         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 910         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 911         int ret;
 912
 913         struct rte_hash_parameters ethertype_hash_params = {
 914                 .name = ethertype_hash_name,
 915                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 916                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 917                 .hash_func = rte_hash_crc,
 918                 .hash_func_init_val = 0,
 919                 .socket_id = rte_socket_id(),
 920         };
 921
 922         /* Initialize ethertype filter rule list and hash */
 923         TAILQ_INIT(&ethertype_rule->ethertype_list);
 924         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 925                  "ethertype_%s", dev->device->name);
 926         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 927         if (!ethertype_rule->hash_table) {
 928                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 929                 return -EINVAL;
 930         }
 931         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 932                                        sizeof(struct i40e_ethertype_filter *) *
 933                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 934                                        0);
 935         if (!ethertype_rule->hash_map) {
 936                 PMD_INIT_LOG(ERR,
 937                              "Failed to allocate memory for ethertype hash map!");
 938                 ret = -ENOMEM;
 939                 goto err_ethertype_hash_map_alloc;
 940         }
 941
 942         return 0;
 943
 944 err_ethertype_hash_map_alloc:
 945         rte_hash_free(ethertype_rule->hash_table);
 946
 947         return ret;
 948 }
 949
 950 static int
 951 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 952 {
 953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 954         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 955         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 956         int ret;
 957
 958         struct rte_hash_parameters tunnel_hash_params = {
 959                 .name = tunnel_hash_name,
 960                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 961                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 962                 .hash_func = rte_hash_crc,
 963                 .hash_func_init_val = 0,
 964                 .socket_id = rte_socket_id(),
 965         };
 966
 967         /* Initialize tunnel filter rule list and hash */
 968         TAILQ_INIT(&tunnel_rule->tunnel_list);
 969         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 970                  "tunnel_%s", dev->device->name);
 971         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 972         if (!tunnel_rule->hash_table) {
 973                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 974                 return -EINVAL;
 975         }
 976         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 977                                     sizeof(struct i40e_tunnel_filter *) *
 978                                     I40E_MAX_TUNNEL_FILTER_NUM,
 979                                     0);
 980         if (!tunnel_rule->hash_map) {
 981                 PMD_INIT_LOG(ERR,
 982                              "Failed to allocate memory for tunnel hash map!");
 983                 ret = -ENOMEM;
 984                 goto err_tunnel_hash_map_alloc;
 985         }
 986
 987         return 0;
 988
 989 err_tunnel_hash_map_alloc:
 990         rte_hash_free(tunnel_rule->hash_table);
 991
 992         return ret;
 993 }
 994
 995 static int
 996 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct i40e_fdir_info *fdir_info = &pf->fdir;
1000         char fdir_hash_name[RTE_HASH_NAMESIZE];
1001         int ret;
1002
1003         struct rte_hash_parameters fdir_hash_params = {
1004                 .name = fdir_hash_name,
1005                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1006                 .key_len = sizeof(struct rte_eth_fdir_input),
1007                 .hash_func = rte_hash_crc,
1008                 .hash_func_init_val = 0,
1009                 .socket_id = rte_socket_id(),
1010         };
1011
1012         /* Initialize flow director filter rule list and hash */
1013         TAILQ_INIT(&fdir_info->fdir_list);
1014         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1015                  "fdir_%s", dev->device->name);
1016         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1017         if (!fdir_info->hash_table) {
1018                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1019                 return -EINVAL;
1020         }
1021         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1022                                           sizeof(struct i40e_fdir_filter *) *
1023                                           I40E_MAX_FDIR_FILTER_NUM,
1024                                           0);
1025         if (!fdir_info->hash_map) {
1026                 PMD_INIT_LOG(ERR,
1027                              "Failed to allocate memory for fdir hash map!");
1028                 ret = -ENOMEM;
1029                 goto err_fdir_hash_map_alloc;
1030         }
1031         return 0;
1032
1033 err_fdir_hash_map_alloc:
1034         rte_hash_free(fdir_info->hash_table);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 eth_i40e_dev_init(struct rte_eth_dev *dev)
1041 {
1042         struct rte_pci_device *pci_dev;
1043         struct rte_intr_handle *intr_handle;
1044         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1045         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046         struct i40e_vsi *vsi;
1047         int ret;
1048         uint32_t len;
1049         uint8_t aq_fail = 0;
1050
1051         PMD_INIT_FUNC_TRACE();
1052
1053         dev->dev_ops = &i40e_eth_dev_ops;
1054         dev->rx_pkt_burst = i40e_recv_pkts;
1055         dev->tx_pkt_burst = i40e_xmit_pkts;
1056         dev->tx_pkt_prepare = i40e_prep_pkts;
1057
1058         /* for secondary processes, we don't initialise any further as primary
1059          * has already done this work. Only check we don't need a different
1060          * RX function */
1061         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1062                 i40e_set_rx_function(dev);
1063                 i40e_set_tx_function(dev);
1064                 return 0;
1065         }
1066         i40e_set_default_ptype_table(dev);
1067         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1068         intr_handle = &pci_dev->intr_handle;
1069
1070         rte_eth_copy_pci_info(dev, pci_dev);
1071         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1072
1073         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1074         pf->adapter->eth_dev = dev;
1075         pf->dev_data = dev->data;
1076
1077         hw->back = I40E_PF_TO_ADAPTER(pf);
1078         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1079         if (!hw->hw_addr) {
1080                 PMD_INIT_LOG(ERR,
1081                         "Hardware is not available, as address is NULL");
1082                 return -ENODEV;
1083         }
1084
1085         hw->vendor_id = pci_dev->id.vendor_id;
1086         hw->device_id = pci_dev->id.device_id;
1087         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1088         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1089         hw->bus.device = pci_dev->addr.devid;
1090         hw->bus.func = pci_dev->addr.function;
1091         hw->adapter_stopped = 0;
1092
1093         /* Make sure all is clean before doing PF reset */
1094         i40e_clear_hw(hw);
1095
1096         /* Initialize the hardware */
1097         i40e_hw_init(dev);
1098
1099         /* Reset here to make sure all is clean for each PF */
1100         ret = i40e_pf_reset(hw);
1101         if (ret) {
1102                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103                 return ret;
1104         }
1105
1106         /* Initialize the shared code (base driver) */
1107         ret = i40e_init_shared_code(hw);
1108         if (ret) {
1109                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1110                 return ret;
1111         }
1112
1113         /*
1114          * To work around the NVM issue, initialize registers
1115          * for flexible payload and packet type of QinQ by
1116          * software. It should be removed once issues are fixed
1117          * in NVM.
1118          */
1119         i40e_GLQF_reg_init(hw);
1120
1121         /* Initialize the input set for filters (hash and fd) to default value */
1122         i40e_filter_input_set_init(pf);
1123
1124         /* Initialize the parameters for adminq */
1125         i40e_init_adminq_parameter(hw);
1126         ret = i40e_init_adminq(hw);
1127         if (ret != I40E_SUCCESS) {
1128                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1129                 return -EIO;
1130         }
1131         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1132                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1133                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1134                      ((hw->nvm.version >> 12) & 0xf),
1135                      ((hw->nvm.version >> 4) & 0xff),
1136                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1137
1138         /* initialise the L3_MAP register */
1139         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1140                                    0x00000028,  NULL);
1141         if (ret)
1142                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1143
1144         /* Need the special FW version to support floating VEB */
1145         config_floating_veb(dev);
1146         /* Clear PXE mode */
1147         i40e_clear_pxe_mode(hw);
1148         i40e_dev_sync_phy_type(hw);
1149
1150         /*
1151          * On X710, performance number is far from the expectation on recent
1152          * firmware versions. The fix for this issue may not be integrated in
1153          * the following firmware version. So the workaround in software driver
1154          * is needed. It needs to modify the initial values of 3 internal only
1155          * registers. Note that the workaround can be removed when it is fixed
1156          * in firmware in the future.
1157          */
1158         i40e_configure_registers(hw);
1159
1160         /* Get hw capabilities */
1161         ret = i40e_get_cap(hw);
1162         if (ret != I40E_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164                 goto err_get_capabilities;
1165         }
1166
1167         /* Initialize parameters for PF */
1168         ret = i40e_pf_parameter_init(dev);
1169         if (ret != 0) {
1170                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171                 goto err_parameter_init;
1172         }
1173
1174         /* Initialize the queue management */
1175         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1176         if (ret < 0) {
1177                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178                 goto err_qp_pool_init;
1179         }
1180         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181                                 hw->func_caps.num_msix_vectors - 1);
1182         if (ret < 0) {
1183                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184                 goto err_msix_pool_init;
1185         }
1186
1187         /* Initialize lan hmc */
1188         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189                                 hw->func_caps.num_rx_qp, 0, 0);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192                 goto err_init_lan_hmc;
1193         }
1194
1195         /* Configure lan hmc */
1196         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197         if (ret != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199                 goto err_configure_lan_hmc;
1200         }
1201
1202         /* Get and check the mac address */
1203         i40e_get_mac_addr(hw, hw->mac.addr);
1204         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205                 PMD_INIT_LOG(ERR, "mac address is not valid");
1206                 ret = -EIO;
1207                 goto err_get_mac_addr;
1208         }
1209         /* Copy the permanent MAC address */
1210         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211                         (struct ether_addr *) hw->mac.perm_addr);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* Set the global registers with default ether type value */
1218         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219         if (ret != I40E_SUCCESS) {
1220                 PMD_INIT_LOG(ERR,
1221                         "Failed to set the default outer VLAN ether type");
1222                 goto err_setup_pf_switch;
1223         }
1224
1225         /* PF setup, which includes VSI setup */
1226         ret = i40e_pf_setup(pf);
1227         if (ret) {
1228                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229                 goto err_setup_pf_switch;
1230         }
1231
1232         /* reset all stats of the device, including pf and main vsi */
1233         i40e_dev_stats_reset(dev);
1234
1235         vsi = pf->main_vsi;
1236
1237         /* Disable double vlan by default */
1238         i40e_vsi_config_double_vlan(vsi, FALSE);
1239
1240         /* Disable S-TAG identification when floating_veb is disabled */
1241         if (!pf->floating_veb) {
1242                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1246                 }
1247         }
1248
1249         if (!vsi->max_macaddrs)
1250                 len = ETHER_ADDR_LEN;
1251         else
1252                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1253
1254         /* Should be after VSI initialized */
1255         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256         if (!dev->data->mac_addrs) {
1257                 PMD_INIT_LOG(ERR,
1258                         "Failed to allocated memory for storing mac address");
1259                 goto err_mac_alloc;
1260         }
1261         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262                                         &dev->data->mac_addrs[0]);
1263
1264         /* Init dcb to sw mode by default */
1265         ret = i40e_dcb_init_configure(dev, TRUE);
1266         if (ret != I40E_SUCCESS) {
1267                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268                 pf->flags &= ~I40E_FLAG_DCB;
1269         }
1270         /* Update HW struct after DCB configuration */
1271         i40e_get_cap(hw);
1272
1273         /* initialize pf host driver to setup SRIOV resource if applicable */
1274         i40e_pf_host_init(dev);
1275
1276         /* register callback func to eal lib */
1277         rte_intr_callback_register(intr_handle,
1278                                    i40e_dev_interrupt_handler, dev);
1279
1280         /* configure and enable device interrupt */
1281         i40e_pf_config_irq0(hw, TRUE);
1282         i40e_pf_enable_irq0(hw);
1283
1284         /* enable uio intr after callback register */
1285         rte_intr_enable(intr_handle);
1286         /*
1287          * Add an ethertype filter to drop all flow control frames transmitted
1288          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1289          * frames to wire.
1290          */
1291         i40e_add_tx_flow_control_drop_filter(pf);
1292
1293         /* Set the max frame size to 0x2600 by default,
1294          * in case other drivers changed the default value.
1295          */
1296         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1297
1298         /* initialize mirror rule list */
1299         TAILQ_INIT(&pf->mirror_list);
1300
1301         /* initialize Traffic Manager configuration */
1302         i40e_tm_conf_init(dev);
1303
1304         ret = i40e_init_ethtype_filter_list(dev);
1305         if (ret < 0)
1306                 goto err_init_ethtype_filter_list;
1307         ret = i40e_init_tunnel_filter_list(dev);
1308         if (ret < 0)
1309                 goto err_init_tunnel_filter_list;
1310         ret = i40e_init_fdir_filter_list(dev);
1311         if (ret < 0)
1312                 goto err_init_fdir_filter_list;
1313
1314         return 0;
1315
1316 err_init_fdir_filter_list:
1317         rte_free(pf->tunnel.hash_table);
1318         rte_free(pf->tunnel.hash_map);
1319 err_init_tunnel_filter_list:
1320         rte_free(pf->ethertype.hash_table);
1321         rte_free(pf->ethertype.hash_map);
1322 err_init_ethtype_filter_list:
1323         rte_free(dev->data->mac_addrs);
1324 err_mac_alloc:
1325         i40e_vsi_release(pf->main_vsi);
1326 err_setup_pf_switch:
1327 err_get_mac_addr:
1328 err_configure_lan_hmc:
1329         (void)i40e_shutdown_lan_hmc(hw);
1330 err_init_lan_hmc:
1331         i40e_res_pool_destroy(&pf->msix_pool);
1332 err_msix_pool_init:
1333         i40e_res_pool_destroy(&pf->qp_pool);
1334 err_qp_pool_init:
1335 err_parameter_init:
1336 err_get_capabilities:
1337         (void)i40e_shutdown_adminq(hw);
1338
1339         return ret;
1340 }
1341
1342 static void
1343 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1344 {
1345         struct i40e_ethertype_filter *p_ethertype;
1346         struct i40e_ethertype_rule *ethertype_rule;
1347
1348         ethertype_rule = &pf->ethertype;
1349         /* Remove all ethertype filter rules and hash */
1350         if (ethertype_rule->hash_map)
1351                 rte_free(ethertype_rule->hash_map);
1352         if (ethertype_rule->hash_table)
1353                 rte_hash_free(ethertype_rule->hash_table);
1354
1355         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1356                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1357                              p_ethertype, rules);
1358                 rte_free(p_ethertype);
1359         }
1360 }
1361
1362 static void
1363 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1364 {
1365         struct i40e_tunnel_filter *p_tunnel;
1366         struct i40e_tunnel_rule *tunnel_rule;
1367
1368         tunnel_rule = &pf->tunnel;
1369         /* Remove all tunnel director rules and hash */
1370         if (tunnel_rule->hash_map)
1371                 rte_free(tunnel_rule->hash_map);
1372         if (tunnel_rule->hash_table)
1373                 rte_hash_free(tunnel_rule->hash_table);
1374
1375         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1376                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1377                 rte_free(p_tunnel);
1378         }
1379 }
1380
1381 static void
1382 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1383 {
1384         struct i40e_fdir_filter *p_fdir;
1385         struct i40e_fdir_info *fdir_info;
1386
1387         fdir_info = &pf->fdir;
1388         /* Remove all flow director rules and hash */
1389         if (fdir_info->hash_map)
1390                 rte_free(fdir_info->hash_map);
1391         if (fdir_info->hash_table)
1392                 rte_hash_free(fdir_info->hash_table);
1393
1394         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1395                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1396                 rte_free(p_fdir);
1397         }
1398 }
1399
1400 static int
1401 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1402 {
1403         struct i40e_pf *pf;
1404         struct rte_pci_device *pci_dev;
1405         struct rte_intr_handle *intr_handle;
1406         struct i40e_hw *hw;
1407         struct i40e_filter_control_settings settings;
1408         struct rte_flow *p_flow;
1409         int ret;
1410         uint8_t aq_fail = 0;
1411
1412         PMD_INIT_FUNC_TRACE();
1413
1414         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1415                 return 0;
1416
1417         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1418         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1420         intr_handle = &pci_dev->intr_handle;
1421
1422         if (hw->adapter_stopped == 0)
1423                 i40e_dev_close(dev);
1424
1425         dev->dev_ops = NULL;
1426         dev->rx_pkt_burst = NULL;
1427         dev->tx_pkt_burst = NULL;
1428
1429         /* Clear PXE mode */
1430         i40e_clear_pxe_mode(hw);
1431
1432         /* Unconfigure filter control */
1433         memset(&settings, 0, sizeof(settings));
1434         ret = i40e_set_filter_control(hw, &settings);
1435         if (ret)
1436                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1437                                         ret);
1438
1439         /* Disable flow control */
1440         hw->fc.requested_mode = I40E_FC_NONE;
1441         i40e_set_fc(hw, &aq_fail, TRUE);
1442
1443         /* uninitialize pf host driver */
1444         i40e_pf_host_uninit(dev);
1445
1446         rte_free(dev->data->mac_addrs);
1447         dev->data->mac_addrs = NULL;
1448
1449         /* disable uio intr before callback unregister */
1450         rte_intr_disable(intr_handle);
1451
1452         /* register callback func to eal lib */
1453         rte_intr_callback_unregister(intr_handle,
1454                                      i40e_dev_interrupt_handler, dev);
1455
1456         i40e_rm_ethtype_filter_list(pf);
1457         i40e_rm_tunnel_filter_list(pf);
1458         i40e_rm_fdir_filter_list(pf);
1459
1460         /* Remove all flows */
1461         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1462                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1463                 rte_free(p_flow);
1464         }
1465
1466         /* Remove all Traffic Manager configuration */
1467         i40e_tm_conf_uninit(dev);
1468
1469         return 0;
1470 }
1471
1472 static int
1473 i40e_dev_configure(struct rte_eth_dev *dev)
1474 {
1475         struct i40e_adapter *ad =
1476                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1480         int i, ret;
1481
1482         ret = i40e_dev_sync_phy_type(hw);
1483         if (ret)
1484                 return ret;
1485
1486         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1487          * bulk allocation or vector Rx preconditions we will reset it.
1488          */
1489         ad->rx_bulk_alloc_allowed = true;
1490         ad->rx_vec_allowed = true;
1491         ad->tx_simple_allowed = true;
1492         ad->tx_vec_allowed = true;
1493
1494         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1495                 ret = i40e_fdir_setup(pf);
1496                 if (ret != I40E_SUCCESS) {
1497                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1498                         return -ENOTSUP;
1499                 }
1500                 ret = i40e_fdir_configure(dev);
1501                 if (ret < 0) {
1502                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1503                         goto err;
1504                 }
1505         } else
1506                 i40e_fdir_teardown(pf);
1507
1508         ret = i40e_dev_init_vlan(dev);
1509         if (ret < 0)
1510                 goto err;
1511
1512         /* VMDQ setup.
1513          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1514          *  RSS setting have different requirements.
1515          *  General PMD driver call sequence are NIC init, configure,
1516          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1517          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1518          *  applicable. So, VMDQ setting has to be done before
1519          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1520          *  For RSS setting, it will try to calculate actual configured RX queue
1521          *  number, which will be available after rx_queue_setup(). dev_start()
1522          *  function is good to place RSS setup.
1523          */
1524         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1525                 ret = i40e_vmdq_setup(dev);
1526                 if (ret)
1527                         goto err;
1528         }
1529
1530         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1531                 ret = i40e_dcb_setup(dev);
1532                 if (ret) {
1533                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1534                         goto err_dcb;
1535                 }
1536         }
1537
1538         TAILQ_INIT(&pf->flow_list);
1539
1540         return 0;
1541
1542 err_dcb:
1543         /* need to release vmdq resource if exists */
1544         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1545                 i40e_vsi_release(pf->vmdq[i].vsi);
1546                 pf->vmdq[i].vsi = NULL;
1547         }
1548         rte_free(pf->vmdq);
1549         pf->vmdq = NULL;
1550 err:
1551         /* need to release fdir resource if exists */
1552         i40e_fdir_teardown(pf);
1553         return ret;
1554 }
1555
1556 void
1557 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1558 {
1559         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1560         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1561         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1562         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1563         uint16_t msix_vect = vsi->msix_intr;
1564         uint16_t i;
1565
1566         for (i = 0; i < vsi->nb_qps; i++) {
1567                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1568                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1569                 rte_wmb();
1570         }
1571
1572         if (vsi->type != I40E_VSI_SRIOV) {
1573                 if (!rte_intr_allow_others(intr_handle)) {
1574                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1575                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1576                         I40E_WRITE_REG(hw,
1577                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1578                                        0);
1579                 } else {
1580                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1581                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1582                         I40E_WRITE_REG(hw,
1583                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1584                                                        msix_vect - 1), 0);
1585                 }
1586         } else {
1587                 uint32_t reg;
1588                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1589                         vsi->user_param + (msix_vect - 1);
1590
1591                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1592                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1593         }
1594         I40E_WRITE_FLUSH(hw);
1595 }
1596
1597 static void
1598 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1599                        int base_queue, int nb_queue)
1600 {
1601         int i;
1602         uint32_t val;
1603         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1604
1605         /* Bind all RX queues to allocated MSIX interrupt */
1606         for (i = 0; i < nb_queue; i++) {
1607                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1608                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1609                         ((base_queue + i + 1) <<
1610                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1611                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1612                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1613
1614                 if (i == nb_queue - 1)
1615                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1616                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1617         }
1618
1619         /* Write first RX queue to Link list register as the head element */
1620         if (vsi->type != I40E_VSI_SRIOV) {
1621                 uint16_t interval =
1622                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1623
1624                 if (msix_vect == I40E_MISC_VEC_ID) {
1625                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1626                                        (base_queue <<
1627                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1628                                        (0x0 <<
1629                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1630                         I40E_WRITE_REG(hw,
1631                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1632                                        interval);
1633                 } else {
1634                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1635                                        (base_queue <<
1636                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1637                                        (0x0 <<
1638                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1639                         I40E_WRITE_REG(hw,
1640                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1641                                                        msix_vect - 1),
1642                                        interval);
1643                 }
1644         } else {
1645                 uint32_t reg;
1646
1647                 if (msix_vect == I40E_MISC_VEC_ID) {
1648                         I40E_WRITE_REG(hw,
1649                                        I40E_VPINT_LNKLST0(vsi->user_param),
1650                                        (base_queue <<
1651                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1652                                        (0x0 <<
1653                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1654                 } else {
1655                         /* num_msix_vectors_vf needs to minus irq0 */
1656                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1657                                 vsi->user_param + (msix_vect - 1);
1658
1659                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1660                                        (base_queue <<
1661                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1662                                        (0x0 <<
1663                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1664                 }
1665         }
1666
1667         I40E_WRITE_FLUSH(hw);
1668 }
1669
1670 void
1671 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1672 {
1673         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1674         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1675         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1676         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1677         uint16_t msix_vect = vsi->msix_intr;
1678         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1679         uint16_t queue_idx = 0;
1680         int record = 0;
1681         uint32_t val;
1682         int i;
1683
1684         for (i = 0; i < vsi->nb_qps; i++) {
1685                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1686                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1687         }
1688
1689         /* INTENA flag is not auto-cleared for interrupt */
1690         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1691         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1692                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1693                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1694         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1695
1696         /* VF bind interrupt */
1697         if (vsi->type == I40E_VSI_SRIOV) {
1698                 __vsi_queues_bind_intr(vsi, msix_vect,
1699                                        vsi->base_queue, vsi->nb_qps);
1700                 return;
1701         }
1702
1703         /* PF & VMDq bind interrupt */
1704         if (rte_intr_dp_is_en(intr_handle)) {
1705                 if (vsi->type == I40E_VSI_MAIN) {
1706                         queue_idx = 0;
1707                         record = 1;
1708                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1709                         struct i40e_vsi *main_vsi =
1710                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1711                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1712                         record = 1;
1713                 }
1714         }
1715
1716         for (i = 0; i < vsi->nb_used_qps; i++) {
1717                 if (nb_msix <= 1) {
1718                         if (!rte_intr_allow_others(intr_handle))
1719                                 /* allow to share MISC_VEC_ID */
1720                                 msix_vect = I40E_MISC_VEC_ID;
1721
1722                         /* no enough msix_vect, map all to one */
1723                         __vsi_queues_bind_intr(vsi, msix_vect,
1724                                                vsi->base_queue + i,
1725                                                vsi->nb_used_qps - i);
1726                         for (; !!record && i < vsi->nb_used_qps; i++)
1727                                 intr_handle->intr_vec[queue_idx + i] =
1728                                         msix_vect;
1729                         break;
1730                 }
1731                 /* 1:1 queue/msix_vect mapping */
1732                 __vsi_queues_bind_intr(vsi, msix_vect,
1733                                        vsi->base_queue + i, 1);
1734                 if (!!record)
1735                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1736
1737                 msix_vect++;
1738                 nb_msix--;
1739         }
1740 }
1741
1742 static void
1743 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1744 {
1745         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1746         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1747         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1748         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1749         uint16_t interval = i40e_calc_itr_interval(\
1750                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1751         uint16_t msix_intr, i;
1752
1753         if (rte_intr_allow_others(intr_handle))
1754                 for (i = 0; i < vsi->nb_msix; i++) {
1755                         msix_intr = vsi->msix_intr + i;
1756                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1757                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1758                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1759                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1760                                 (interval <<
1761                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1762                 }
1763         else
1764                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1765                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1766                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1767                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1768                                (interval <<
1769                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1770
1771         I40E_WRITE_FLUSH(hw);
1772 }
1773
1774 static void
1775 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1776 {
1777         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1778         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1779         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1780         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1781         uint16_t msix_intr, i;
1782
1783         if (rte_intr_allow_others(intr_handle))
1784                 for (i = 0; i < vsi->nb_msix; i++) {
1785                         msix_intr = vsi->msix_intr + i;
1786                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1787                                        0);
1788                 }
1789         else
1790                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1791
1792         I40E_WRITE_FLUSH(hw);
1793 }
1794
1795 static inline uint8_t
1796 i40e_parse_link_speeds(uint16_t link_speeds)
1797 {
1798         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1799
1800         if (link_speeds & ETH_LINK_SPEED_40G)
1801                 link_speed |= I40E_LINK_SPEED_40GB;
1802         if (link_speeds & ETH_LINK_SPEED_25G)
1803                 link_speed |= I40E_LINK_SPEED_25GB;
1804         if (link_speeds & ETH_LINK_SPEED_20G)
1805                 link_speed |= I40E_LINK_SPEED_20GB;
1806         if (link_speeds & ETH_LINK_SPEED_10G)
1807                 link_speed |= I40E_LINK_SPEED_10GB;
1808         if (link_speeds & ETH_LINK_SPEED_1G)
1809                 link_speed |= I40E_LINK_SPEED_1GB;
1810         if (link_speeds & ETH_LINK_SPEED_100M)
1811                 link_speed |= I40E_LINK_SPEED_100MB;
1812
1813         return link_speed;
1814 }
1815
1816 static int
1817 i40e_phy_conf_link(struct i40e_hw *hw,
1818                    uint8_t abilities,
1819                    uint8_t force_speed,
1820                    bool is_up)
1821 {
1822         enum i40e_status_code status;
1823         struct i40e_aq_get_phy_abilities_resp phy_ab;
1824         struct i40e_aq_set_phy_config phy_conf;
1825         enum i40e_aq_phy_type cnt;
1826         uint32_t phy_type_mask = 0;
1827
1828         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1829                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1830                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1831                         I40E_AQ_PHY_FLAG_LOW_POWER;
1832         const uint8_t advt = I40E_LINK_SPEED_40GB |
1833                         I40E_LINK_SPEED_25GB |
1834                         I40E_LINK_SPEED_10GB |
1835                         I40E_LINK_SPEED_1GB |
1836                         I40E_LINK_SPEED_100MB;
1837         int ret = -ENOTSUP;
1838
1839
1840         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1841                                               NULL);
1842         if (status)
1843                 return ret;
1844
1845         /* If link already up, no need to set up again */
1846         if (is_up && phy_ab.phy_type != 0)
1847                 return I40E_SUCCESS;
1848
1849         memset(&phy_conf, 0, sizeof(phy_conf));
1850
1851         /* bits 0-2 use the values from get_phy_abilities_resp */
1852         abilities &= ~mask;
1853         abilities |= phy_ab.abilities & mask;
1854
1855         /* update ablities and speed */
1856         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1857                 phy_conf.link_speed = advt;
1858         else
1859                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1860
1861         phy_conf.abilities = abilities;
1862
1863
1864
1865         /* To enable link, phy_type mask needs to include each type */
1866         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1867                 phy_type_mask |= 1 << cnt;
1868
1869         /* use get_phy_abilities_resp value for the rest */
1870         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1871         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1872                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1873                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1874         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1875         phy_conf.eee_capability = phy_ab.eee_capability;
1876         phy_conf.eeer = phy_ab.eeer_val;
1877         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1878
1879         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1880                     phy_ab.abilities, phy_ab.link_speed);
1881         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1882                     phy_conf.abilities, phy_conf.link_speed);
1883
1884         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1885         if (status)
1886                 return ret;
1887
1888         return I40E_SUCCESS;
1889 }
1890
1891 static int
1892 i40e_apply_link_speed(struct rte_eth_dev *dev)
1893 {
1894         uint8_t speed;
1895         uint8_t abilities = 0;
1896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897         struct rte_eth_conf *conf = &dev->data->dev_conf;
1898
1899         speed = i40e_parse_link_speeds(conf->link_speeds);
1900         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1901         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1902                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1903         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1904
1905         return i40e_phy_conf_link(hw, abilities, speed, true);
1906 }
1907
1908 static int
1909 i40e_dev_start(struct rte_eth_dev *dev)
1910 {
1911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         struct i40e_vsi *main_vsi = pf->main_vsi;
1914         int ret, i;
1915         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1916         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1917         uint32_t intr_vector = 0;
1918         struct i40e_vsi *vsi;
1919
1920         hw->adapter_stopped = 0;
1921
1922         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1923                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1924                              dev->data->port_id);
1925                 return -EINVAL;
1926         }
1927
1928         rte_intr_disable(intr_handle);
1929
1930         if ((rte_intr_cap_multiple(intr_handle) ||
1931              !RTE_ETH_DEV_SRIOV(dev).active) &&
1932             dev->data->dev_conf.intr_conf.rxq != 0) {
1933                 intr_vector = dev->data->nb_rx_queues;
1934                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1935                 if (ret)
1936                         return ret;
1937         }
1938
1939         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1940                 intr_handle->intr_vec =
1941                         rte_zmalloc("intr_vec",
1942                                     dev->data->nb_rx_queues * sizeof(int),
1943                                     0);
1944                 if (!intr_handle->intr_vec) {
1945                         PMD_INIT_LOG(ERR,
1946                                 "Failed to allocate %d rx_queues intr_vec",
1947                                 dev->data->nb_rx_queues);
1948                         return -ENOMEM;
1949                 }
1950         }
1951
1952         /* Initialize VSI */
1953         ret = i40e_dev_rxtx_init(pf);
1954         if (ret != I40E_SUCCESS) {
1955                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1956                 goto err_up;
1957         }
1958
1959         /* Map queues with MSIX interrupt */
1960         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1961                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1962         i40e_vsi_queues_bind_intr(main_vsi);
1963         i40e_vsi_enable_queues_intr(main_vsi);
1964
1965         /* Map VMDQ VSI queues with MSIX interrupt */
1966         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1967                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1968                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1969                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1970         }
1971
1972         /* enable FDIR MSIX interrupt */
1973         if (pf->fdir.fdir_vsi) {
1974                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1975                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1976         }
1977
1978         /* Enable all queues which have been configured */
1979         ret = i40e_dev_switch_queues(pf, TRUE);
1980         if (ret != I40E_SUCCESS) {
1981                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1982                 goto err_up;
1983         }
1984
1985         /* Enable receiving broadcast packets */
1986         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1987         if (ret != I40E_SUCCESS)
1988                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1989
1990         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1991                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1992                                                 true, NULL);
1993                 if (ret != I40E_SUCCESS)
1994                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1995         }
1996
1997         /* Enable the VLAN promiscuous mode. */
1998         if (pf->vfs) {
1999                 for (i = 0; i < pf->vf_num; i++) {
2000                         vsi = pf->vfs[i].vsi;
2001                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2002                                                      true, NULL);
2003                 }
2004         }
2005
2006         /* Apply link configure */
2007         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2008                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2009                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2010                                 ETH_LINK_SPEED_40G)) {
2011                 PMD_DRV_LOG(ERR, "Invalid link setting");
2012                 goto err_up;
2013         }
2014         ret = i40e_apply_link_speed(dev);
2015         if (I40E_SUCCESS != ret) {
2016                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2017                 goto err_up;
2018         }
2019
2020         if (!rte_intr_allow_others(intr_handle)) {
2021                 rte_intr_callback_unregister(intr_handle,
2022                                              i40e_dev_interrupt_handler,
2023                                              (void *)dev);
2024                 /* configure and enable device interrupt */
2025                 i40e_pf_config_irq0(hw, FALSE);
2026                 i40e_pf_enable_irq0(hw);
2027
2028                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2029                         PMD_INIT_LOG(INFO,
2030                                 "lsc won't enable because of no intr multiplex");
2031         } else {
2032                 ret = i40e_aq_set_phy_int_mask(hw,
2033                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2034                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2035                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2036                 if (ret != I40E_SUCCESS)
2037                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2038
2039                 /* Call get_link_info aq commond to enable/disable LSE */
2040                 i40e_dev_link_update(dev, 0);
2041         }
2042
2043         /* enable uio intr after callback register */
2044         rte_intr_enable(intr_handle);
2045
2046         i40e_filter_restore(pf);
2047
2048         if (pf->tm_conf.root && !pf->tm_conf.committed)
2049                 PMD_DRV_LOG(WARNING,
2050                             "please call hierarchy_commit() "
2051                             "before starting the port");
2052
2053         return I40E_SUCCESS;
2054
2055 err_up:
2056         i40e_dev_switch_queues(pf, FALSE);
2057         i40e_dev_clear_queues(dev);
2058
2059         return ret;
2060 }
2061
2062 static void
2063 i40e_dev_stop(struct rte_eth_dev *dev)
2064 {
2065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         struct i40e_vsi *main_vsi = pf->main_vsi;
2068         struct i40e_mirror_rule *p_mirror;
2069         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2070         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2071         int i;
2072
2073         if (hw->adapter_stopped == 1)
2074                 return;
2075         /* Disable all queues */
2076         i40e_dev_switch_queues(pf, FALSE);
2077
2078         /* un-map queues with interrupt registers */
2079         i40e_vsi_disable_queues_intr(main_vsi);
2080         i40e_vsi_queues_unbind_intr(main_vsi);
2081
2082         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2083                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2084                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2085         }
2086
2087         if (pf->fdir.fdir_vsi) {
2088                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2089                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2090         }
2091         /* Clear all queues and release memory */
2092         i40e_dev_clear_queues(dev);
2093
2094         /* Set link down */
2095         i40e_dev_set_link_down(dev);
2096
2097         /* Remove all mirror rules */
2098         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2099                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2100                 rte_free(p_mirror);
2101         }
2102         pf->nb_mirror_rule = 0;
2103
2104         if (!rte_intr_allow_others(intr_handle))
2105                 /* resume to the default handler */
2106                 rte_intr_callback_register(intr_handle,
2107                                            i40e_dev_interrupt_handler,
2108                                            (void *)dev);
2109
2110         /* Clean datapath event and queue/vec mapping */
2111         rte_intr_efd_disable(intr_handle);
2112         if (intr_handle->intr_vec) {
2113                 rte_free(intr_handle->intr_vec);
2114                 intr_handle->intr_vec = NULL;
2115         }
2116
2117         /* reset hierarchy commit */
2118         pf->tm_conf.committed = false;
2119
2120         hw->adapter_stopped = 1;
2121 }
2122
2123 static void
2124 i40e_dev_close(struct rte_eth_dev *dev)
2125 {
2126         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2127         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2128         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2129         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2130         uint32_t reg;
2131         int i;
2132
2133         PMD_INIT_FUNC_TRACE();
2134
2135         i40e_dev_stop(dev);
2136         i40e_dev_free_queues(dev);
2137
2138         /* Disable interrupt */
2139         i40e_pf_disable_irq0(hw);
2140         rte_intr_disable(intr_handle);
2141
2142         /* shutdown and destroy the HMC */
2143         i40e_shutdown_lan_hmc(hw);
2144
2145         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2146                 i40e_vsi_release(pf->vmdq[i].vsi);
2147                 pf->vmdq[i].vsi = NULL;
2148         }
2149         rte_free(pf->vmdq);
2150         pf->vmdq = NULL;
2151
2152         /* release all the existing VSIs and VEBs */
2153         i40e_fdir_teardown(pf);
2154         i40e_vsi_release(pf->main_vsi);
2155
2156         /* shutdown the adminq */
2157         i40e_aq_queue_shutdown(hw, true);
2158         i40e_shutdown_adminq(hw);
2159
2160         i40e_res_pool_destroy(&pf->qp_pool);
2161         i40e_res_pool_destroy(&pf->msix_pool);
2162
2163         /* force a PF reset to clean anything leftover */
2164         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2165         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2166                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2167         I40E_WRITE_FLUSH(hw);
2168 }
2169
2170 /*
2171  * Reset PF device only to re-initialize resources in PMD layer
2172  */
2173 static int
2174 i40e_dev_reset(struct rte_eth_dev *dev)
2175 {
2176         int ret;
2177
2178         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2179          * its VF to make them align with it. The detailed notification
2180          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2181          * To avoid unexpected behavior in VF, currently reset of PF with
2182          * SR-IOV activation is not supported. It might be supported later.
2183          */
2184         if (dev->data->sriov.active)
2185                 return -ENOTSUP;
2186
2187         ret = eth_i40e_dev_uninit(dev);
2188         if (ret)
2189                 return ret;
2190
2191         ret = eth_i40e_dev_init(dev);
2192
2193         return ret;
2194 }
2195
2196 static void
2197 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2198 {
2199         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2200         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201         struct i40e_vsi *vsi = pf->main_vsi;
2202         int status;
2203
2204         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2205                                                      true, NULL, true);
2206         if (status != I40E_SUCCESS)
2207                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2208
2209         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2210                                                         TRUE, NULL);
2211         if (status != I40E_SUCCESS)
2212                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2213
2214 }
2215
2216 static void
2217 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2218 {
2219         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2220         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221         struct i40e_vsi *vsi = pf->main_vsi;
2222         int status;
2223
2224         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2225                                                      false, NULL, true);
2226         if (status != I40E_SUCCESS)
2227                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2228
2229         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2230                                                         false, NULL);
2231         if (status != I40E_SUCCESS)
2232                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2233 }
2234
2235 static void
2236 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2237 {
2238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct i40e_vsi *vsi = pf->main_vsi;
2241         int ret;
2242
2243         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2244         if (ret != I40E_SUCCESS)
2245                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2246 }
2247
2248 static void
2249 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2250 {
2251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253         struct i40e_vsi *vsi = pf->main_vsi;
2254         int ret;
2255
2256         if (dev->data->promiscuous == 1)
2257                 return; /* must remain in all_multicast mode */
2258
2259         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2260                                 vsi->seid, FALSE, NULL);
2261         if (ret != I40E_SUCCESS)
2262                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2263 }
2264
2265 /*
2266  * Set device link up.
2267  */
2268 static int
2269 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2270 {
2271         /* re-apply link speed setting */
2272         return i40e_apply_link_speed(dev);
2273 }
2274
2275 /*
2276  * Set device link down.
2277  */
2278 static int
2279 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2280 {
2281         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2282         uint8_t abilities = 0;
2283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2284
2285         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2286         return i40e_phy_conf_link(hw, abilities, speed, false);
2287 }
2288
2289 int
2290 i40e_dev_link_update(struct rte_eth_dev *dev,
2291                      int wait_to_complete)
2292 {
2293 #define CHECK_INTERVAL 100  /* 100ms */
2294 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2295         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296         struct i40e_link_status link_status;
2297         struct rte_eth_link link, old;
2298         int status;
2299         unsigned rep_cnt = MAX_REPEAT_TIME;
2300         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2301
2302         memset(&link, 0, sizeof(link));
2303         memset(&old, 0, sizeof(old));
2304         memset(&link_status, 0, sizeof(link_status));
2305         rte_i40e_dev_atomic_read_link_status(dev, &old);
2306
2307         do {
2308                 /* Get link status information from hardware */
2309                 status = i40e_aq_get_link_info(hw, enable_lse,
2310                                                 &link_status, NULL);
2311                 if (status != I40E_SUCCESS) {
2312                         link.link_speed = ETH_SPEED_NUM_100M;
2313                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2314                         PMD_DRV_LOG(ERR, "Failed to get link info");
2315                         goto out;
2316                 }
2317
2318                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2319                 if (!wait_to_complete || link.link_status)
2320                         break;
2321
2322                 rte_delay_ms(CHECK_INTERVAL);
2323         } while (--rep_cnt);
2324
2325         if (!link.link_status)
2326                 goto out;
2327
2328         /* i40e uses full duplex only */
2329         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2330
2331         /* Parse the link status */
2332         switch (link_status.link_speed) {
2333         case I40E_LINK_SPEED_100MB:
2334                 link.link_speed = ETH_SPEED_NUM_100M;
2335                 break;
2336         case I40E_LINK_SPEED_1GB:
2337                 link.link_speed = ETH_SPEED_NUM_1G;
2338                 break;
2339         case I40E_LINK_SPEED_10GB:
2340                 link.link_speed = ETH_SPEED_NUM_10G;
2341                 break;
2342         case I40E_LINK_SPEED_20GB:
2343                 link.link_speed = ETH_SPEED_NUM_20G;
2344                 break;
2345         case I40E_LINK_SPEED_25GB:
2346                 link.link_speed = ETH_SPEED_NUM_25G;
2347                 break;
2348         case I40E_LINK_SPEED_40GB:
2349                 link.link_speed = ETH_SPEED_NUM_40G;
2350                 break;
2351         default:
2352                 link.link_speed = ETH_SPEED_NUM_100M;
2353                 break;
2354         }
2355
2356         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2357                         ETH_LINK_SPEED_FIXED);
2358
2359 out:
2360         rte_i40e_dev_atomic_write_link_status(dev, &link);
2361         if (link.link_status == old.link_status)
2362                 return -1;
2363
2364         i40e_notify_all_vfs_link_status(dev);
2365
2366         return 0;
2367 }
2368
2369 /* Get all the statistics of a VSI */
2370 void
2371 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2372 {
2373         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2374         struct i40e_eth_stats *nes = &vsi->eth_stats;
2375         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2376         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2377
2378         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2379                             vsi->offset_loaded, &oes->rx_bytes,
2380                             &nes->rx_bytes);
2381         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2382                             vsi->offset_loaded, &oes->rx_unicast,
2383                             &nes->rx_unicast);
2384         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2385                             vsi->offset_loaded, &oes->rx_multicast,
2386                             &nes->rx_multicast);
2387         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2388                             vsi->offset_loaded, &oes->rx_broadcast,
2389                             &nes->rx_broadcast);
2390         /* exclude CRC bytes */
2391         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2392                 nes->rx_broadcast) * ETHER_CRC_LEN;
2393
2394         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2395                             &oes->rx_discards, &nes->rx_discards);
2396         /* GLV_REPC not supported */
2397         /* GLV_RMPC not supported */
2398         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2399                             &oes->rx_unknown_protocol,
2400                             &nes->rx_unknown_protocol);
2401         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2402                             vsi->offset_loaded, &oes->tx_bytes,
2403                             &nes->tx_bytes);
2404         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2405                             vsi->offset_loaded, &oes->tx_unicast,
2406                             &nes->tx_unicast);
2407         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2408                             vsi->offset_loaded, &oes->tx_multicast,
2409                             &nes->tx_multicast);
2410         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2411                             vsi->offset_loaded,  &oes->tx_broadcast,
2412                             &nes->tx_broadcast);
2413         /* GLV_TDPC not supported */
2414         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2415                             &oes->tx_errors, &nes->tx_errors);
2416         vsi->offset_loaded = true;
2417
2418         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2419                     vsi->vsi_id);
2420         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2421         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2422         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2423         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2424         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2425         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2426                     nes->rx_unknown_protocol);
2427         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2428         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2429         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2430         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2431         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2432         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2433         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2434                     vsi->vsi_id);
2435 }
2436
2437 static void
2438 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2439 {
2440         unsigned int i;
2441         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2442         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2443
2444         /* Get rx/tx bytes of internal transfer packets */
2445         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2446                         I40E_GLV_GORCL(hw->port),
2447                         pf->offset_loaded,
2448                         &pf->internal_stats_offset.rx_bytes,
2449                         &pf->internal_stats.rx_bytes);
2450
2451         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2452                         I40E_GLV_GOTCL(hw->port),
2453                         pf->offset_loaded,
2454                         &pf->internal_stats_offset.tx_bytes,
2455                         &pf->internal_stats.tx_bytes);
2456         /* Get total internal rx packet count */
2457         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2458                             I40E_GLV_UPRCL(hw->port),
2459                             pf->offset_loaded,
2460                             &pf->internal_stats_offset.rx_unicast,
2461                             &pf->internal_stats.rx_unicast);
2462         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2463                             I40E_GLV_MPRCL(hw->port),
2464                             pf->offset_loaded,
2465                             &pf->internal_stats_offset.rx_multicast,
2466                             &pf->internal_stats.rx_multicast);
2467         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2468                             I40E_GLV_BPRCL(hw->port),
2469                             pf->offset_loaded,
2470                             &pf->internal_stats_offset.rx_broadcast,
2471                             &pf->internal_stats.rx_broadcast);
2472
2473         /* exclude CRC size */
2474         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2475                 pf->internal_stats.rx_multicast +
2476                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2477
2478         /* Get statistics of struct i40e_eth_stats */
2479         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2480                             I40E_GLPRT_GORCL(hw->port),
2481                             pf->offset_loaded, &os->eth.rx_bytes,
2482                             &ns->eth.rx_bytes);
2483         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2484                             I40E_GLPRT_UPRCL(hw->port),
2485                             pf->offset_loaded, &os->eth.rx_unicast,
2486                             &ns->eth.rx_unicast);
2487         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2488                             I40E_GLPRT_MPRCL(hw->port),
2489                             pf->offset_loaded, &os->eth.rx_multicast,
2490                             &ns->eth.rx_multicast);
2491         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2492                             I40E_GLPRT_BPRCL(hw->port),
2493                             pf->offset_loaded, &os->eth.rx_broadcast,
2494                             &ns->eth.rx_broadcast);
2495         /* Workaround: CRC size should not be included in byte statistics,
2496          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2497          */
2498         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2499                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2500
2501         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2502          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2503          * value.
2504          */
2505         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2506                 ns->eth.rx_bytes = 0;
2507         /* exlude internal rx bytes */
2508         else
2509                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2510
2511         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2512                             pf->offset_loaded, &os->eth.rx_discards,
2513                             &ns->eth.rx_discards);
2514         /* GLPRT_REPC not supported */
2515         /* GLPRT_RMPC not supported */
2516         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2517                             pf->offset_loaded,
2518                             &os->eth.rx_unknown_protocol,
2519                             &ns->eth.rx_unknown_protocol);
2520         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2521                             I40E_GLPRT_GOTCL(hw->port),
2522                             pf->offset_loaded, &os->eth.tx_bytes,
2523                             &ns->eth.tx_bytes);
2524         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2525                             I40E_GLPRT_UPTCL(hw->port),
2526                             pf->offset_loaded, &os->eth.tx_unicast,
2527                             &ns->eth.tx_unicast);
2528         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2529                             I40E_GLPRT_MPTCL(hw->port),
2530                             pf->offset_loaded, &os->eth.tx_multicast,
2531                             &ns->eth.tx_multicast);
2532         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2533                             I40E_GLPRT_BPTCL(hw->port),
2534                             pf->offset_loaded, &os->eth.tx_broadcast,
2535                             &ns->eth.tx_broadcast);
2536         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2537                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2538
2539         /* exclude internal tx bytes */
2540         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2541                 ns->eth.tx_bytes = 0;
2542         else
2543                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2544
2545         /* GLPRT_TEPC not supported */
2546
2547         /* additional port specific stats */
2548         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2549                             pf->offset_loaded, &os->tx_dropped_link_down,
2550                             &ns->tx_dropped_link_down);
2551         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2552                             pf->offset_loaded, &os->crc_errors,
2553                             &ns->crc_errors);
2554         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2555                             pf->offset_loaded, &os->illegal_bytes,
2556                             &ns->illegal_bytes);
2557         /* GLPRT_ERRBC not supported */
2558         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2559                             pf->offset_loaded, &os->mac_local_faults,
2560                             &ns->mac_local_faults);
2561         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2562                             pf->offset_loaded, &os->mac_remote_faults,
2563                             &ns->mac_remote_faults);
2564         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2565                             pf->offset_loaded, &os->rx_length_errors,
2566                             &ns->rx_length_errors);
2567         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2568                             pf->offset_loaded, &os->link_xon_rx,
2569                             &ns->link_xon_rx);
2570         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2571                             pf->offset_loaded, &os->link_xoff_rx,
2572                             &ns->link_xoff_rx);
2573         for (i = 0; i < 8; i++) {
2574                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2575                                     pf->offset_loaded,
2576                                     &os->priority_xon_rx[i],
2577                                     &ns->priority_xon_rx[i]);
2578                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2579                                     pf->offset_loaded,
2580                                     &os->priority_xoff_rx[i],
2581                                     &ns->priority_xoff_rx[i]);
2582         }
2583         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2584                             pf->offset_loaded, &os->link_xon_tx,
2585                             &ns->link_xon_tx);
2586         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2587                             pf->offset_loaded, &os->link_xoff_tx,
2588                             &ns->link_xoff_tx);
2589         for (i = 0; i < 8; i++) {
2590                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2591                                     pf->offset_loaded,
2592                                     &os->priority_xon_tx[i],
2593                                     &ns->priority_xon_tx[i]);
2594                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2595                                     pf->offset_loaded,
2596                                     &os->priority_xoff_tx[i],
2597                                     &ns->priority_xoff_tx[i]);
2598                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2599                                     pf->offset_loaded,
2600                                     &os->priority_xon_2_xoff[i],
2601                                     &ns->priority_xon_2_xoff[i]);
2602         }
2603         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2604                             I40E_GLPRT_PRC64L(hw->port),
2605                             pf->offset_loaded, &os->rx_size_64,
2606                             &ns->rx_size_64);
2607         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2608                             I40E_GLPRT_PRC127L(hw->port),
2609                             pf->offset_loaded, &os->rx_size_127,
2610                             &ns->rx_size_127);
2611         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2612                             I40E_GLPRT_PRC255L(hw->port),
2613                             pf->offset_loaded, &os->rx_size_255,
2614                             &ns->rx_size_255);
2615         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2616                             I40E_GLPRT_PRC511L(hw->port),
2617                             pf->offset_loaded, &os->rx_size_511,
2618                             &ns->rx_size_511);
2619         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2620                             I40E_GLPRT_PRC1023L(hw->port),
2621                             pf->offset_loaded, &os->rx_size_1023,
2622                             &ns->rx_size_1023);
2623         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2624                             I40E_GLPRT_PRC1522L(hw->port),
2625                             pf->offset_loaded, &os->rx_size_1522,
2626                             &ns->rx_size_1522);
2627         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2628                             I40E_GLPRT_PRC9522L(hw->port),
2629                             pf->offset_loaded, &os->rx_size_big,
2630                             &ns->rx_size_big);
2631         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2632                             pf->offset_loaded, &os->rx_undersize,
2633                             &ns->rx_undersize);
2634         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2635                             pf->offset_loaded, &os->rx_fragments,
2636                             &ns->rx_fragments);
2637         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2638                             pf->offset_loaded, &os->rx_oversize,
2639                             &ns->rx_oversize);
2640         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2641                             pf->offset_loaded, &os->rx_jabber,
2642                             &ns->rx_jabber);
2643         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2644                             I40E_GLPRT_PTC64L(hw->port),
2645                             pf->offset_loaded, &os->tx_size_64,
2646                             &ns->tx_size_64);
2647         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2648                             I40E_GLPRT_PTC127L(hw->port),
2649                             pf->offset_loaded, &os->tx_size_127,
2650                             &ns->tx_size_127);
2651         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2652                             I40E_GLPRT_PTC255L(hw->port),
2653                             pf->offset_loaded, &os->tx_size_255,
2654                             &ns->tx_size_255);
2655         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2656                             I40E_GLPRT_PTC511L(hw->port),
2657                             pf->offset_loaded, &os->tx_size_511,
2658                             &ns->tx_size_511);
2659         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2660                             I40E_GLPRT_PTC1023L(hw->port),
2661                             pf->offset_loaded, &os->tx_size_1023,
2662                             &ns->tx_size_1023);
2663         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2664                             I40E_GLPRT_PTC1522L(hw->port),
2665                             pf->offset_loaded, &os->tx_size_1522,
2666                             &ns->tx_size_1522);
2667         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2668                             I40E_GLPRT_PTC9522L(hw->port),
2669                             pf->offset_loaded, &os->tx_size_big,
2670                             &ns->tx_size_big);
2671         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2672                            pf->offset_loaded,
2673                            &os->fd_sb_match, &ns->fd_sb_match);
2674         /* GLPRT_MSPDC not supported */
2675         /* GLPRT_XEC not supported */
2676
2677         pf->offset_loaded = true;
2678
2679         if (pf->main_vsi)
2680                 i40e_update_vsi_stats(pf->main_vsi);
2681 }
2682
2683 /* Get all statistics of a port */
2684 static void
2685 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2686 {
2687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2690         unsigned i;
2691
2692         /* call read registers - updates values, now write them to struct */
2693         i40e_read_stats_registers(pf, hw);
2694
2695         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2696                         pf->main_vsi->eth_stats.rx_multicast +
2697                         pf->main_vsi->eth_stats.rx_broadcast -
2698                         pf->main_vsi->eth_stats.rx_discards;
2699         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2700                         pf->main_vsi->eth_stats.tx_multicast +
2701                         pf->main_vsi->eth_stats.tx_broadcast;
2702         stats->ibytes   = ns->eth.rx_bytes;
2703         stats->obytes   = ns->eth.tx_bytes;
2704         stats->oerrors  = ns->eth.tx_errors +
2705                         pf->main_vsi->eth_stats.tx_errors;
2706
2707         /* Rx Errors */
2708         stats->imissed  = ns->eth.rx_discards +
2709                         pf->main_vsi->eth_stats.rx_discards;
2710         stats->ierrors  = ns->crc_errors +
2711                         ns->rx_length_errors + ns->rx_undersize +
2712                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2713
2714         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2715         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2716         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2717         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2718         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2719         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2720         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2721                     ns->eth.rx_unknown_protocol);
2722         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2723         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2724         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2725         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2726         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2727         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2728
2729         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2730                     ns->tx_dropped_link_down);
2731         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2732         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2733                     ns->illegal_bytes);
2734         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2735         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2736                     ns->mac_local_faults);
2737         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2738                     ns->mac_remote_faults);
2739         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2740                     ns->rx_length_errors);
2741         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2742         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2743         for (i = 0; i < 8; i++) {
2744                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2745                                 i, ns->priority_xon_rx[i]);
2746                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2747                                 i, ns->priority_xoff_rx[i]);
2748         }
2749         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2750         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2751         for (i = 0; i < 8; i++) {
2752                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2753                                 i, ns->priority_xon_tx[i]);
2754                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2755                                 i, ns->priority_xoff_tx[i]);
2756                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2757                                 i, ns->priority_xon_2_xoff[i]);
2758         }
2759         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2760         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2761         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2762         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2763         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2764         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2765         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2766         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2767         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2768         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2769         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2770         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2771         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2772         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2773         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2774         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2775         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2776         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2777         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2778                         ns->mac_short_packet_dropped);
2779         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2780                     ns->checksum_error);
2781         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2782         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2783 }
2784
2785 /* Reset the statistics */
2786 static void
2787 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2788 {
2789         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791
2792         /* Mark PF and VSI stats to update the offset, aka "reset" */
2793         pf->offset_loaded = false;
2794         if (pf->main_vsi)
2795                 pf->main_vsi->offset_loaded = false;
2796
2797         /* read the stats, reading current register values into offset */
2798         i40e_read_stats_registers(pf, hw);
2799 }
2800
2801 static uint32_t
2802 i40e_xstats_calc_num(void)
2803 {
2804         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2805                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2806                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2807 }
2808
2809 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2810                                      struct rte_eth_xstat_name *xstats_names,
2811                                      __rte_unused unsigned limit)
2812 {
2813         unsigned count = 0;
2814         unsigned i, prio;
2815
2816         if (xstats_names == NULL)
2817                 return i40e_xstats_calc_num();
2818
2819         /* Note: limit checked in rte_eth_xstats_names() */
2820
2821         /* Get stats from i40e_eth_stats struct */
2822         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2823                 snprintf(xstats_names[count].name,
2824                          sizeof(xstats_names[count].name),
2825                          "%s", rte_i40e_stats_strings[i].name);
2826                 count++;
2827         }
2828
2829         /* Get individiual stats from i40e_hw_port struct */
2830         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2831                 snprintf(xstats_names[count].name,
2832                         sizeof(xstats_names[count].name),
2833                          "%s", rte_i40e_hw_port_strings[i].name);
2834                 count++;
2835         }
2836
2837         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2838                 for (prio = 0; prio < 8; prio++) {
2839                         snprintf(xstats_names[count].name,
2840                                  sizeof(xstats_names[count].name),
2841                                  "rx_priority%u_%s", prio,
2842                                  rte_i40e_rxq_prio_strings[i].name);
2843                         count++;
2844                 }
2845         }
2846
2847         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2848                 for (prio = 0; prio < 8; prio++) {
2849                         snprintf(xstats_names[count].name,
2850                                  sizeof(xstats_names[count].name),
2851                                  "tx_priority%u_%s", prio,
2852                                  rte_i40e_txq_prio_strings[i].name);
2853                         count++;
2854                 }
2855         }
2856         return count;
2857 }
2858
2859 static int
2860 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2861                     unsigned n)
2862 {
2863         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         unsigned i, count, prio;
2866         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2867
2868         count = i40e_xstats_calc_num();
2869         if (n < count)
2870                 return count;
2871
2872         i40e_read_stats_registers(pf, hw);
2873
2874         if (xstats == NULL)
2875                 return 0;
2876
2877         count = 0;
2878
2879         /* Get stats from i40e_eth_stats struct */
2880         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2881                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2882                         rte_i40e_stats_strings[i].offset);
2883                 xstats[count].id = count;
2884                 count++;
2885         }
2886
2887         /* Get individiual stats from i40e_hw_port struct */
2888         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2889                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2890                         rte_i40e_hw_port_strings[i].offset);
2891                 xstats[count].id = count;
2892                 count++;
2893         }
2894
2895         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2896                 for (prio = 0; prio < 8; prio++) {
2897                         xstats[count].value =
2898                                 *(uint64_t *)(((char *)hw_stats) +
2899                                 rte_i40e_rxq_prio_strings[i].offset +
2900                                 (sizeof(uint64_t) * prio));
2901                         xstats[count].id = count;
2902                         count++;
2903                 }
2904         }
2905
2906         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2907                 for (prio = 0; prio < 8; prio++) {
2908                         xstats[count].value =
2909                                 *(uint64_t *)(((char *)hw_stats) +
2910                                 rte_i40e_txq_prio_strings[i].offset +
2911                                 (sizeof(uint64_t) * prio));
2912                         xstats[count].id = count;
2913                         count++;
2914                 }
2915         }
2916
2917         return count;
2918 }
2919
2920 static int
2921 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2922                                  __rte_unused uint16_t queue_id,
2923                                  __rte_unused uint8_t stat_idx,
2924                                  __rte_unused uint8_t is_rx)
2925 {
2926         PMD_INIT_FUNC_TRACE();
2927
2928         return -ENOSYS;
2929 }
2930
2931 static int
2932 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2933 {
2934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935         u32 full_ver;
2936         u8 ver, patch;
2937         u16 build;
2938         int ret;
2939
2940         full_ver = hw->nvm.oem_ver;
2941         ver = (u8)(full_ver >> 24);
2942         build = (u16)((full_ver >> 8) & 0xffff);
2943         patch = (u8)(full_ver & 0xff);
2944
2945         ret = snprintf(fw_version, fw_size,
2946                  "%d.%d%d 0x%08x %d.%d.%d",
2947                  ((hw->nvm.version >> 12) & 0xf),
2948                  ((hw->nvm.version >> 4) & 0xff),
2949                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2950                  ver, build, patch);
2951
2952         ret += 1; /* add the size of '\0' */
2953         if (fw_size < (u32)ret)
2954                 return ret;
2955         else
2956                 return 0;
2957 }
2958
2959 static void
2960 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2961 {
2962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         struct i40e_vsi *vsi = pf->main_vsi;
2965         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2966
2967         dev_info->pci_dev = pci_dev;
2968         dev_info->max_rx_queues = vsi->nb_qps;
2969         dev_info->max_tx_queues = vsi->nb_qps;
2970         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2971         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2972         dev_info->max_mac_addrs = vsi->max_macaddrs;
2973         dev_info->max_vfs = pci_dev->max_vfs;
2974         dev_info->rx_offload_capa =
2975                 DEV_RX_OFFLOAD_VLAN_STRIP |
2976                 DEV_RX_OFFLOAD_QINQ_STRIP |
2977                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2978                 DEV_RX_OFFLOAD_UDP_CKSUM |
2979                 DEV_RX_OFFLOAD_TCP_CKSUM;
2980         dev_info->tx_offload_capa =
2981                 DEV_TX_OFFLOAD_VLAN_INSERT |
2982                 DEV_TX_OFFLOAD_QINQ_INSERT |
2983                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2984                 DEV_TX_OFFLOAD_UDP_CKSUM |
2985                 DEV_TX_OFFLOAD_TCP_CKSUM |
2986                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2987                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2988                 DEV_TX_OFFLOAD_TCP_TSO |
2989                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2990                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2991                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2992                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2993         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2994                                                 sizeof(uint32_t);
2995         dev_info->reta_size = pf->hash_lut_size;
2996         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2997
2998         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2999                 .rx_thresh = {
3000                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3001                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3002                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3003                 },
3004                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3005                 .rx_drop_en = 0,
3006         };
3007
3008         dev_info->default_txconf = (struct rte_eth_txconf) {
3009                 .tx_thresh = {
3010                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3011                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3012                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3013                 },
3014                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3015                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3016                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3017                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3018         };
3019
3020         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3021                 .nb_max = I40E_MAX_RING_DESC,
3022                 .nb_min = I40E_MIN_RING_DESC,
3023                 .nb_align = I40E_ALIGN_RING_DESC,
3024         };
3025
3026         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3027                 .nb_max = I40E_MAX_RING_DESC,
3028                 .nb_min = I40E_MIN_RING_DESC,
3029                 .nb_align = I40E_ALIGN_RING_DESC,
3030                 .nb_seg_max = I40E_TX_MAX_SEG,
3031                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3032         };
3033
3034         if (pf->flags & I40E_FLAG_VMDQ) {
3035                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3036                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3037                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3038                                                 pf->max_nb_vmdq_vsi;
3039                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3040                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3041                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3042         }
3043
3044         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3045                 /* For XL710 */
3046                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3047         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3048                 /* For XXV710 */
3049                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3050         else
3051                 /* For X710 */
3052                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3053 }
3054
3055 static int
3056 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3057 {
3058         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3059         struct i40e_vsi *vsi = pf->main_vsi;
3060         PMD_INIT_FUNC_TRACE();
3061
3062         if (on)
3063                 return i40e_vsi_add_vlan(vsi, vlan_id);
3064         else
3065                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3066 }
3067
3068 static int
3069 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3070                                 enum rte_vlan_type vlan_type,
3071                                 uint16_t tpid, int qinq)
3072 {
3073         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         uint64_t reg_r = 0;
3075         uint64_t reg_w = 0;
3076         uint16_t reg_id = 3;
3077         int ret;
3078
3079         if (qinq) {
3080                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3081                         reg_id = 2;
3082         }
3083
3084         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3085                                           &reg_r, NULL);
3086         if (ret != I40E_SUCCESS) {
3087                 PMD_DRV_LOG(ERR,
3088                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3089                            reg_id);
3090                 return -EIO;
3091         }
3092         PMD_DRV_LOG(DEBUG,
3093                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3094                     reg_id, reg_r);
3095
3096         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3097         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3098         if (reg_r == reg_w) {
3099                 PMD_DRV_LOG(DEBUG, "No need to write");
3100                 return 0;
3101         }
3102
3103         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3104                                            reg_w, NULL);
3105         if (ret != I40E_SUCCESS) {
3106                 PMD_DRV_LOG(ERR,
3107                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3108                             reg_id);
3109                 return -EIO;
3110         }
3111         PMD_DRV_LOG(DEBUG,
3112                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3113                     reg_w, reg_id);
3114
3115         return 0;
3116 }
3117
3118 static int
3119 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3120                    enum rte_vlan_type vlan_type,
3121                    uint16_t tpid)
3122 {
3123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3125         int ret = 0;
3126
3127         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3128              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3129             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3130                 PMD_DRV_LOG(ERR,
3131                             "Unsupported vlan type.");
3132                 return -EINVAL;
3133         }
3134         /* 802.1ad frames ability is added in NVM API 1.7*/
3135         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3136                 if (qinq) {
3137                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3138                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3139                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3140                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3141                 } else {
3142                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3143                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3144                 }
3145                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3146                 if (ret != I40E_SUCCESS) {
3147                         PMD_DRV_LOG(ERR,
3148                                     "Set switch config failed aq_err: %d",
3149                                     hw->aq.asq_last_status);
3150                         ret = -EIO;
3151                 }
3152         } else
3153                 /* If NVM API < 1.7, keep the register setting */
3154                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3155                                                       tpid, qinq);
3156
3157         return ret;
3158 }
3159
3160 static void
3161 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3162 {
3163         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3164         struct i40e_vsi *vsi = pf->main_vsi;
3165
3166         if (mask & ETH_VLAN_FILTER_MASK) {
3167                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3168                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3169                 else
3170                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3171         }
3172
3173         if (mask & ETH_VLAN_STRIP_MASK) {
3174                 /* Enable or disable VLAN stripping */
3175                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3176                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3177                 else
3178                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3179         }
3180
3181         if (mask & ETH_VLAN_EXTEND_MASK) {
3182                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3183                         i40e_vsi_config_double_vlan(vsi, TRUE);
3184                         /* Set global registers with default ethertype. */
3185                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3186                                            ETHER_TYPE_VLAN);
3187                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3188                                            ETHER_TYPE_VLAN);
3189                 }
3190                 else
3191                         i40e_vsi_config_double_vlan(vsi, FALSE);
3192         }
3193 }
3194
3195 static void
3196 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3197                           __rte_unused uint16_t queue,
3198                           __rte_unused int on)
3199 {
3200         PMD_INIT_FUNC_TRACE();
3201 }
3202
3203 static int
3204 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3205 {
3206         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3207         struct i40e_vsi *vsi = pf->main_vsi;
3208         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3209         struct i40e_vsi_vlan_pvid_info info;
3210
3211         memset(&info, 0, sizeof(info));
3212         info.on = on;
3213         if (info.on)
3214                 info.config.pvid = pvid;
3215         else {
3216                 info.config.reject.tagged =
3217                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3218                 info.config.reject.untagged =
3219                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3220         }
3221
3222         return i40e_vsi_vlan_pvid_set(vsi, &info);
3223 }
3224
3225 static int
3226 i40e_dev_led_on(struct rte_eth_dev *dev)
3227 {
3228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229         uint32_t mode = i40e_led_get(hw);
3230
3231         if (mode == 0)
3232                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3233
3234         return 0;
3235 }
3236
3237 static int
3238 i40e_dev_led_off(struct rte_eth_dev *dev)
3239 {
3240         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3241         uint32_t mode = i40e_led_get(hw);
3242
3243         if (mode != 0)
3244                 i40e_led_set(hw, 0, false);
3245
3246         return 0;
3247 }
3248
3249 static int
3250 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3251 {
3252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3254
3255         fc_conf->pause_time = pf->fc_conf.pause_time;
3256
3257         /* read out from register, in case they are modified by other port */
3258         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3259                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3260         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3261                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3262
3263         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3264         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3265
3266          /* Return current mode according to actual setting*/
3267         switch (hw->fc.current_mode) {
3268         case I40E_FC_FULL:
3269                 fc_conf->mode = RTE_FC_FULL;
3270                 break;
3271         case I40E_FC_TX_PAUSE:
3272                 fc_conf->mode = RTE_FC_TX_PAUSE;
3273                 break;
3274         case I40E_FC_RX_PAUSE:
3275                 fc_conf->mode = RTE_FC_RX_PAUSE;
3276                 break;
3277         case I40E_FC_NONE:
3278         default:
3279                 fc_conf->mode = RTE_FC_NONE;
3280         };
3281
3282         return 0;
3283 }
3284
3285 static int
3286 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3287 {
3288         uint32_t mflcn_reg, fctrl_reg, reg;
3289         uint32_t max_high_water;
3290         uint8_t i, aq_failure;
3291         int err;
3292         struct i40e_hw *hw;
3293         struct i40e_pf *pf;
3294         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3295                 [RTE_FC_NONE] = I40E_FC_NONE,
3296                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3297                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3298                 [RTE_FC_FULL] = I40E_FC_FULL
3299         };
3300
3301         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3302
3303         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3304         if ((fc_conf->high_water > max_high_water) ||
3305                         (fc_conf->high_water < fc_conf->low_water)) {
3306                 PMD_INIT_LOG(ERR,
3307                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3308                         max_high_water);
3309                 return -EINVAL;
3310         }
3311
3312         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3314         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3315
3316         pf->fc_conf.pause_time = fc_conf->pause_time;
3317         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3318         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3319
3320         PMD_INIT_FUNC_TRACE();
3321
3322         /* All the link flow control related enable/disable register
3323          * configuration is handle by the F/W
3324          */
3325         err = i40e_set_fc(hw, &aq_failure, true);
3326         if (err < 0)
3327                 return -ENOSYS;
3328
3329         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3330                 /* Configure flow control refresh threshold,
3331                  * the value for stat_tx_pause_refresh_timer[8]
3332                  * is used for global pause operation.
3333                  */
3334
3335                 I40E_WRITE_REG(hw,
3336                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3337                                pf->fc_conf.pause_time);
3338
3339                 /* configure the timer value included in transmitted pause
3340                  * frame,
3341                  * the value for stat_tx_pause_quanta[8] is used for global
3342                  * pause operation
3343                  */
3344                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3345                                pf->fc_conf.pause_time);
3346
3347                 fctrl_reg = I40E_READ_REG(hw,
3348                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3349
3350                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3351                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3352                 else
3353                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3354
3355                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3356                                fctrl_reg);
3357         } else {
3358                 /* Configure pause time (2 TCs per register) */
3359                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3360                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3361                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3362
3363                 /* Configure flow control refresh threshold value */
3364                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3365                                pf->fc_conf.pause_time / 2);
3366
3367                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3368
3369                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3370                  *depending on configuration
3371                  */
3372                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3373                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3374                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3375                 } else {
3376                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3377                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3378                 }
3379
3380                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3381         }
3382
3383         /* config the water marker both based on the packets and bytes */
3384         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3385                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3386                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3387         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3388                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3389                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3390         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3391                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3392                        << I40E_KILOSHIFT);
3393         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3394                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3395                        << I40E_KILOSHIFT);
3396
3397         I40E_WRITE_FLUSH(hw);
3398
3399         return 0;
3400 }
3401
3402 static int
3403 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3404                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3405 {
3406         PMD_INIT_FUNC_TRACE();
3407
3408         return -ENOSYS;
3409 }
3410
3411 /* Add a MAC address, and update filters */
3412 static int
3413 i40e_macaddr_add(struct rte_eth_dev *dev,
3414                  struct ether_addr *mac_addr,
3415                  __rte_unused uint32_t index,
3416                  uint32_t pool)
3417 {
3418         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3419         struct i40e_mac_filter_info mac_filter;
3420         struct i40e_vsi *vsi;
3421         int ret;
3422
3423         /* If VMDQ not enabled or configured, return */
3424         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3425                           !pf->nb_cfg_vmdq_vsi)) {
3426                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3427                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3428                         pool);
3429                 return -ENOTSUP;
3430         }
3431
3432         if (pool > pf->nb_cfg_vmdq_vsi) {
3433                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3434                                 pool, pf->nb_cfg_vmdq_vsi);
3435                 return -EINVAL;
3436         }
3437
3438         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3439         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3440                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3441         else
3442                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3443
3444         if (pool == 0)
3445                 vsi = pf->main_vsi;
3446         else
3447                 vsi = pf->vmdq[pool - 1].vsi;
3448
3449         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3450         if (ret != I40E_SUCCESS) {
3451                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3452                 return -ENODEV;
3453         }
3454         return 0;
3455 }
3456
3457 /* Remove a MAC address, and update filters */
3458 static void
3459 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3460 {
3461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3462         struct i40e_vsi *vsi;
3463         struct rte_eth_dev_data *data = dev->data;
3464         struct ether_addr *macaddr;
3465         int ret;
3466         uint32_t i;
3467         uint64_t pool_sel;
3468
3469         macaddr = &(data->mac_addrs[index]);
3470
3471         pool_sel = dev->data->mac_pool_sel[index];
3472
3473         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3474                 if (pool_sel & (1ULL << i)) {
3475                         if (i == 0)
3476                                 vsi = pf->main_vsi;
3477                         else {
3478                                 /* No VMDQ pool enabled or configured */
3479                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3480                                         (i > pf->nb_cfg_vmdq_vsi)) {
3481                                         PMD_DRV_LOG(ERR,
3482                                                 "No VMDQ pool enabled/configured");
3483                                         return;
3484                                 }
3485                                 vsi = pf->vmdq[i - 1].vsi;
3486                         }
3487                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3488
3489                         if (ret) {
3490                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3491                                 return;
3492                         }
3493                 }
3494         }
3495 }
3496
3497 /* Set perfect match or hash match of MAC and VLAN for a VF */
3498 static int
3499 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3500                  struct rte_eth_mac_filter *filter,
3501                  bool add)
3502 {
3503         struct i40e_hw *hw;
3504         struct i40e_mac_filter_info mac_filter;
3505         struct ether_addr old_mac;
3506         struct ether_addr *new_mac;
3507         struct i40e_pf_vf *vf = NULL;
3508         uint16_t vf_id;
3509         int ret;
3510
3511         if (pf == NULL) {
3512                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3513                 return -EINVAL;
3514         }
3515         hw = I40E_PF_TO_HW(pf);
3516
3517         if (filter == NULL) {
3518                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3519                 return -EINVAL;
3520         }
3521
3522         new_mac = &filter->mac_addr;
3523
3524         if (is_zero_ether_addr(new_mac)) {
3525                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3526                 return -EINVAL;
3527         }
3528
3529         vf_id = filter->dst_id;
3530
3531         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3532                 PMD_DRV_LOG(ERR, "Invalid argument.");
3533                 return -EINVAL;
3534         }
3535         vf = &pf->vfs[vf_id];
3536
3537         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3538                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3539                 return -EINVAL;
3540         }
3541
3542         if (add) {
3543                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3544                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3545                                 ETHER_ADDR_LEN);
3546                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3547                                  ETHER_ADDR_LEN);
3548
3549                 mac_filter.filter_type = filter->filter_type;
3550                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3551                 if (ret != I40E_SUCCESS) {
3552                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3553                         return -1;
3554                 }
3555                 ether_addr_copy(new_mac, &pf->dev_addr);
3556         } else {
3557                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3558                                 ETHER_ADDR_LEN);
3559                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3560                 if (ret != I40E_SUCCESS) {
3561                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3562                         return -1;
3563                 }
3564
3565                 /* Clear device address as it has been removed */
3566                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3567                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3568         }
3569
3570         return 0;
3571 }
3572
3573 /* MAC filter handle */
3574 static int
3575 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3576                 void *arg)
3577 {
3578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3579         struct rte_eth_mac_filter *filter;
3580         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3581         int ret = I40E_NOT_SUPPORTED;
3582
3583         filter = (struct rte_eth_mac_filter *)(arg);
3584
3585         switch (filter_op) {
3586         case RTE_ETH_FILTER_NOP:
3587                 ret = I40E_SUCCESS;
3588                 break;
3589         case RTE_ETH_FILTER_ADD:
3590                 i40e_pf_disable_irq0(hw);
3591                 if (filter->is_vf)
3592                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3593                 i40e_pf_enable_irq0(hw);
3594                 break;
3595         case RTE_ETH_FILTER_DELETE:
3596                 i40e_pf_disable_irq0(hw);
3597                 if (filter->is_vf)
3598                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3599                 i40e_pf_enable_irq0(hw);
3600                 break;
3601         default:
3602                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3603                 ret = I40E_ERR_PARAM;
3604                 break;
3605         }
3606
3607         return ret;
3608 }
3609
3610 static int
3611 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3612 {
3613         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3614         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3615         int ret;
3616
3617         if (!lut)
3618                 return -EINVAL;
3619
3620         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3621                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3622                                           lut, lut_size);
3623                 if (ret) {
3624                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3625                         return ret;
3626                 }
3627         } else {
3628                 uint32_t *lut_dw = (uint32_t *)lut;
3629                 uint16_t i, lut_size_dw = lut_size / 4;
3630
3631                 for (i = 0; i < lut_size_dw; i++)
3632                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3633         }
3634
3635         return 0;
3636 }
3637
3638 static int
3639 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3640 {
3641         struct i40e_pf *pf;
3642         struct i40e_hw *hw;
3643         int ret;
3644
3645         if (!vsi || !lut)
3646                 return -EINVAL;
3647
3648         pf = I40E_VSI_TO_PF(vsi);
3649         hw = I40E_VSI_TO_HW(vsi);
3650
3651         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3652                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3653                                           lut, lut_size);
3654                 if (ret) {
3655                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3656                         return ret;
3657                 }
3658         } else {
3659                 uint32_t *lut_dw = (uint32_t *)lut;
3660                 uint16_t i, lut_size_dw = lut_size / 4;
3661
3662                 for (i = 0; i < lut_size_dw; i++)
3663                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3664                 I40E_WRITE_FLUSH(hw);
3665         }
3666
3667         return 0;
3668 }
3669
3670 static int
3671 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3672                          struct rte_eth_rss_reta_entry64 *reta_conf,
3673                          uint16_t reta_size)
3674 {
3675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3676         uint16_t i, lut_size = pf->hash_lut_size;
3677         uint16_t idx, shift;
3678         uint8_t *lut;
3679         int ret;
3680
3681         if (reta_size != lut_size ||
3682                 reta_size > ETH_RSS_RETA_SIZE_512) {
3683                 PMD_DRV_LOG(ERR,
3684                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3685                         reta_size, lut_size);
3686                 return -EINVAL;
3687         }
3688
3689         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3690         if (!lut) {
3691                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3692                 return -ENOMEM;
3693         }
3694         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3695         if (ret)
3696                 goto out;
3697         for (i = 0; i < reta_size; i++) {
3698                 idx = i / RTE_RETA_GROUP_SIZE;
3699                 shift = i % RTE_RETA_GROUP_SIZE;
3700                 if (reta_conf[idx].mask & (1ULL << shift))
3701                         lut[i] = reta_conf[idx].reta[shift];
3702         }
3703         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3704
3705 out:
3706         rte_free(lut);
3707
3708         return ret;
3709 }
3710
3711 static int
3712 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3713                         struct rte_eth_rss_reta_entry64 *reta_conf,
3714                         uint16_t reta_size)
3715 {
3716         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3717         uint16_t i, lut_size = pf->hash_lut_size;
3718         uint16_t idx, shift;
3719         uint8_t *lut;
3720         int ret;
3721
3722         if (reta_size != lut_size ||
3723                 reta_size > ETH_RSS_RETA_SIZE_512) {
3724                 PMD_DRV_LOG(ERR,
3725                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3726                         reta_size, lut_size);
3727                 return -EINVAL;
3728         }
3729
3730         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3731         if (!lut) {
3732                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3733                 return -ENOMEM;
3734         }
3735
3736         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3737         if (ret)
3738                 goto out;
3739         for (i = 0; i < reta_size; i++) {
3740                 idx = i / RTE_RETA_GROUP_SIZE;
3741                 shift = i % RTE_RETA_GROUP_SIZE;
3742                 if (reta_conf[idx].mask & (1ULL << shift))
3743                         reta_conf[idx].reta[shift] = lut[i];
3744         }
3745
3746 out:
3747         rte_free(lut);
3748
3749         return ret;
3750 }
3751
3752 /**
3753  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3754  * @hw:   pointer to the HW structure
3755  * @mem:  pointer to mem struct to fill out
3756  * @size: size of memory requested
3757  * @alignment: what to align the allocation to
3758  **/
3759 enum i40e_status_code
3760 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3761                         struct i40e_dma_mem *mem,
3762                         u64 size,
3763                         u32 alignment)
3764 {
3765         const struct rte_memzone *mz = NULL;
3766         char z_name[RTE_MEMZONE_NAMESIZE];
3767
3768         if (!mem)
3769                 return I40E_ERR_PARAM;
3770
3771         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3772         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3773                                          alignment, RTE_PGSIZE_2M);
3774         if (!mz)
3775                 return I40E_ERR_NO_MEMORY;
3776
3777         mem->size = size;
3778         mem->va = mz->addr;
3779         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3780         mem->zone = (const void *)mz;
3781         PMD_DRV_LOG(DEBUG,
3782                 "memzone %s allocated with physical address: %"PRIu64,
3783                 mz->name, mem->pa);
3784
3785         return I40E_SUCCESS;
3786 }
3787
3788 /**
3789  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3790  * @hw:   pointer to the HW structure
3791  * @mem:  ptr to mem struct to free
3792  **/
3793 enum i40e_status_code
3794 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3795                     struct i40e_dma_mem *mem)
3796 {
3797         if (!mem)
3798                 return I40E_ERR_PARAM;
3799
3800         PMD_DRV_LOG(DEBUG,
3801                 "memzone %s to be freed with physical address: %"PRIu64,
3802                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3803         rte_memzone_free((const struct rte_memzone *)mem->zone);
3804         mem->zone = NULL;
3805         mem->va = NULL;
3806         mem->pa = (u64)0;
3807
3808         return I40E_SUCCESS;
3809 }
3810
3811 /**
3812  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3813  * @hw:   pointer to the HW structure
3814  * @mem:  pointer to mem struct to fill out
3815  * @size: size of memory requested
3816  **/
3817 enum i40e_status_code
3818 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3819                          struct i40e_virt_mem *mem,
3820                          u32 size)
3821 {
3822         if (!mem)
3823                 return I40E_ERR_PARAM;
3824
3825         mem->size = size;
3826         mem->va = rte_zmalloc("i40e", size, 0);
3827
3828         if (mem->va)
3829                 return I40E_SUCCESS;
3830         else
3831                 return I40E_ERR_NO_MEMORY;
3832 }
3833
3834 /**
3835  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3836  * @hw:   pointer to the HW structure
3837  * @mem:  pointer to mem struct to free
3838  **/
3839 enum i40e_status_code
3840 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3841                      struct i40e_virt_mem *mem)
3842 {
3843         if (!mem)
3844                 return I40E_ERR_PARAM;
3845
3846         rte_free(mem->va);
3847         mem->va = NULL;
3848
3849         return I40E_SUCCESS;
3850 }
3851
3852 void
3853 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3854 {
3855         rte_spinlock_init(&sp->spinlock);
3856 }
3857
3858 void
3859 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3860 {
3861         rte_spinlock_lock(&sp->spinlock);
3862 }
3863
3864 void
3865 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3866 {
3867         rte_spinlock_unlock(&sp->spinlock);
3868 }
3869
3870 void
3871 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3872 {
3873         return;
3874 }
3875
3876 /**
3877  * Get the hardware capabilities, which will be parsed
3878  * and saved into struct i40e_hw.
3879  */
3880 static int
3881 i40e_get_cap(struct i40e_hw *hw)
3882 {
3883         struct i40e_aqc_list_capabilities_element_resp *buf;
3884         uint16_t len, size = 0;
3885         int ret;
3886
3887         /* Calculate a huge enough buff for saving response data temporarily */
3888         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3889                                                 I40E_MAX_CAP_ELE_NUM;
3890         buf = rte_zmalloc("i40e", len, 0);
3891         if (!buf) {
3892                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3893                 return I40E_ERR_NO_MEMORY;
3894         }
3895
3896         /* Get, parse the capabilities and save it to hw */
3897         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3898                         i40e_aqc_opc_list_func_capabilities, NULL);
3899         if (ret != I40E_SUCCESS)
3900                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3901
3902         /* Free the temporary buffer after being used */
3903         rte_free(buf);
3904
3905         return ret;
3906 }
3907
3908 static int
3909 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3910 {
3911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3912         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3913         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3914         uint16_t qp_count = 0, vsi_count = 0;
3915
3916         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3917                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3918                 return -EINVAL;
3919         }
3920         /* Add the parameter init for LFC */
3921         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3922         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3923         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3924
3925         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3926         pf->max_num_vsi = hw->func_caps.num_vsis;
3927         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3928         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3929         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3930
3931         /* FDir queue/VSI allocation */
3932         pf->fdir_qp_offset = 0;
3933         if (hw->func_caps.fd) {
3934                 pf->flags |= I40E_FLAG_FDIR;
3935                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3936         } else {
3937                 pf->fdir_nb_qps = 0;
3938         }
3939         qp_count += pf->fdir_nb_qps;
3940         vsi_count += 1;
3941
3942         /* LAN queue/VSI allocation */
3943         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3944         if (!hw->func_caps.rss) {
3945                 pf->lan_nb_qps = 1;
3946         } else {
3947                 pf->flags |= I40E_FLAG_RSS;
3948                 if (hw->mac.type == I40E_MAC_X722)
3949                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3950                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3951         }
3952         qp_count += pf->lan_nb_qps;
3953         vsi_count += 1;
3954
3955         /* VF queue/VSI allocation */
3956         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3957         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3958                 pf->flags |= I40E_FLAG_SRIOV;
3959                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3960                 pf->vf_num = pci_dev->max_vfs;
3961                 PMD_DRV_LOG(DEBUG,
3962                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3963                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3964         } else {
3965                 pf->vf_nb_qps = 0;
3966                 pf->vf_num = 0;
3967         }
3968         qp_count += pf->vf_nb_qps * pf->vf_num;
3969         vsi_count += pf->vf_num;
3970
3971         /* VMDq queue/VSI allocation */
3972         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3973         pf->vmdq_nb_qps = 0;
3974         pf->max_nb_vmdq_vsi = 0;
3975         if (hw->func_caps.vmdq) {
3976                 if (qp_count < hw->func_caps.num_tx_qp &&
3977                         vsi_count < hw->func_caps.num_vsis) {
3978                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3979                                 qp_count) / pf->vmdq_nb_qp_max;
3980
3981                         /* Limit the maximum number of VMDq vsi to the maximum
3982                          * ethdev can support
3983                          */
3984                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3985                                 hw->func_caps.num_vsis - vsi_count);
3986                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3987                                 ETH_64_POOLS);
3988                         if (pf->max_nb_vmdq_vsi) {
3989                                 pf->flags |= I40E_FLAG_VMDQ;
3990                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3991                                 PMD_DRV_LOG(DEBUG,
3992                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3993                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3994                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3995                         } else {
3996                                 PMD_DRV_LOG(INFO,
3997                                         "No enough queues left for VMDq");
3998                         }
3999                 } else {
4000                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4001                 }
4002         }
4003         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4004         vsi_count += pf->max_nb_vmdq_vsi;
4005
4006         if (hw->func_caps.dcb)
4007                 pf->flags |= I40E_FLAG_DCB;
4008
4009         if (qp_count > hw->func_caps.num_tx_qp) {
4010                 PMD_DRV_LOG(ERR,
4011                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4012                         qp_count, hw->func_caps.num_tx_qp);
4013                 return -EINVAL;
4014         }
4015         if (vsi_count > hw->func_caps.num_vsis) {
4016                 PMD_DRV_LOG(ERR,
4017                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4018                         vsi_count, hw->func_caps.num_vsis);
4019                 return -EINVAL;
4020         }
4021
4022         return 0;
4023 }
4024
4025 static int
4026 i40e_pf_get_switch_config(struct i40e_pf *pf)
4027 {
4028         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4029         struct i40e_aqc_get_switch_config_resp *switch_config;
4030         struct i40e_aqc_switch_config_element_resp *element;
4031         uint16_t start_seid = 0, num_reported;
4032         int ret;
4033
4034         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4035                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4036         if (!switch_config) {
4037                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4038                 return -ENOMEM;
4039         }
4040
4041         /* Get the switch configurations */
4042         ret = i40e_aq_get_switch_config(hw, switch_config,
4043                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4044         if (ret != I40E_SUCCESS) {
4045                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4046                 goto fail;
4047         }
4048         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4049         if (num_reported != 1) { /* The number should be 1 */
4050                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4051                 goto fail;
4052         }
4053
4054         /* Parse the switch configuration elements */
4055         element = &(switch_config->element[0]);
4056         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4057                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4058                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4059         } else
4060                 PMD_DRV_LOG(INFO, "Unknown element type");
4061
4062 fail:
4063         rte_free(switch_config);
4064
4065         return ret;
4066 }
4067
4068 static int
4069 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4070                         uint32_t num)
4071 {
4072         struct pool_entry *entry;
4073
4074         if (pool == NULL || num == 0)
4075                 return -EINVAL;
4076
4077         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4078         if (entry == NULL) {
4079                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4080                 return -ENOMEM;
4081         }
4082
4083         /* queue heap initialize */
4084         pool->num_free = num;
4085         pool->num_alloc = 0;
4086         pool->base = base;
4087         LIST_INIT(&pool->alloc_list);
4088         LIST_INIT(&pool->free_list);
4089
4090         /* Initialize element  */
4091         entry->base = 0;
4092         entry->len = num;
4093
4094         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4095         return 0;
4096 }
4097
4098 static void
4099 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4100 {
4101         struct pool_entry *entry, *next_entry;
4102
4103         if (pool == NULL)
4104                 return;
4105
4106         for (entry = LIST_FIRST(&pool->alloc_list);
4107                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4108                         entry = next_entry) {
4109                 LIST_REMOVE(entry, next);
4110                 rte_free(entry);
4111         }
4112
4113         for (entry = LIST_FIRST(&pool->free_list);
4114                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4115                         entry = next_entry) {
4116                 LIST_REMOVE(entry, next);
4117                 rte_free(entry);
4118         }
4119
4120         pool->num_free = 0;
4121         pool->num_alloc = 0;
4122         pool->base = 0;
4123         LIST_INIT(&pool->alloc_list);
4124         LIST_INIT(&pool->free_list);
4125 }
4126
4127 static int
4128 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4129                        uint32_t base)
4130 {
4131         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4132         uint32_t pool_offset;
4133         int insert;
4134
4135         if (pool == NULL) {
4136                 PMD_DRV_LOG(ERR, "Invalid parameter");
4137                 return -EINVAL;
4138         }
4139
4140         pool_offset = base - pool->base;
4141         /* Lookup in alloc list */
4142         LIST_FOREACH(entry, &pool->alloc_list, next) {
4143                 if (entry->base == pool_offset) {
4144                         valid_entry = entry;
4145                         LIST_REMOVE(entry, next);
4146                         break;
4147                 }
4148         }
4149
4150         /* Not find, return */
4151         if (valid_entry == NULL) {
4152                 PMD_DRV_LOG(ERR, "Failed to find entry");
4153                 return -EINVAL;
4154         }
4155
4156         /**
4157          * Found it, move it to free list  and try to merge.
4158          * In order to make merge easier, always sort it by qbase.
4159          * Find adjacent prev and last entries.
4160          */
4161         prev = next = NULL;
4162         LIST_FOREACH(entry, &pool->free_list, next) {
4163                 if (entry->base > valid_entry->base) {
4164                         next = entry;
4165                         break;
4166                 }
4167                 prev = entry;
4168         }
4169
4170         insert = 0;
4171         /* Try to merge with next one*/
4172         if (next != NULL) {
4173                 /* Merge with next one */
4174                 if (valid_entry->base + valid_entry->len == next->base) {
4175                         next->base = valid_entry->base;
4176                         next->len += valid_entry->len;
4177                         rte_free(valid_entry);
4178                         valid_entry = next;
4179                         insert = 1;
4180                 }
4181         }
4182
4183         if (prev != NULL) {
4184                 /* Merge with previous one */
4185                 if (prev->base + prev->len == valid_entry->base) {
4186                         prev->len += valid_entry->len;
4187                         /* If it merge with next one, remove next node */
4188                         if (insert == 1) {
4189                                 LIST_REMOVE(valid_entry, next);
4190                                 rte_free(valid_entry);
4191                         } else {
4192                                 rte_free(valid_entry);
4193                                 insert = 1;
4194                         }
4195                 }
4196         }
4197
4198         /* Not find any entry to merge, insert */
4199         if (insert == 0) {
4200                 if (prev != NULL)
4201                         LIST_INSERT_AFTER(prev, valid_entry, next);
4202                 else if (next != NULL)
4203                         LIST_INSERT_BEFORE(next, valid_entry, next);
4204                 else /* It's empty list, insert to head */
4205                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4206         }
4207
4208         pool->num_free += valid_entry->len;
4209         pool->num_alloc -= valid_entry->len;
4210
4211         return 0;
4212 }
4213
4214 static int
4215 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4216                        uint16_t num)
4217 {
4218         struct pool_entry *entry, *valid_entry;
4219
4220         if (pool == NULL || num == 0) {
4221                 PMD_DRV_LOG(ERR, "Invalid parameter");
4222                 return -EINVAL;
4223         }
4224
4225         if (pool->num_free < num) {
4226                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4227                             num, pool->num_free);
4228                 return -ENOMEM;
4229         }
4230
4231         valid_entry = NULL;
4232         /* Lookup  in free list and find most fit one */
4233         LIST_FOREACH(entry, &pool->free_list, next) {
4234                 if (entry->len >= num) {
4235                         /* Find best one */
4236                         if (entry->len == num) {
4237                                 valid_entry = entry;
4238                                 break;
4239                         }
4240                         if (valid_entry == NULL || valid_entry->len > entry->len)
4241                                 valid_entry = entry;
4242                 }
4243         }
4244
4245         /* Not find one to satisfy the request, return */
4246         if (valid_entry == NULL) {
4247                 PMD_DRV_LOG(ERR, "No valid entry found");
4248                 return -ENOMEM;
4249         }
4250         /**
4251          * The entry have equal queue number as requested,
4252          * remove it from alloc_list.
4253          */
4254         if (valid_entry->len == num) {
4255                 LIST_REMOVE(valid_entry, next);
4256         } else {
4257                 /**
4258                  * The entry have more numbers than requested,
4259                  * create a new entry for alloc_list and minus its
4260                  * queue base and number in free_list.
4261                  */
4262                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4263                 if (entry == NULL) {
4264                         PMD_DRV_LOG(ERR,
4265                                 "Failed to allocate memory for resource pool");
4266                         return -ENOMEM;
4267                 }
4268                 entry->base = valid_entry->base;
4269                 entry->len = num;
4270                 valid_entry->base += num;
4271                 valid_entry->len -= num;
4272                 valid_entry = entry;
4273         }
4274
4275         /* Insert it into alloc list, not sorted */
4276         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4277
4278         pool->num_free -= valid_entry->len;
4279         pool->num_alloc += valid_entry->len;
4280
4281         return valid_entry->base + pool->base;
4282 }
4283
4284 /**
4285  * bitmap_is_subset - Check whether src2 is subset of src1
4286  **/
4287 static inline int
4288 bitmap_is_subset(uint8_t src1, uint8_t src2)
4289 {
4290         return !((src1 ^ src2) & src2);
4291 }
4292
4293 static enum i40e_status_code
4294 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4295 {
4296         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4297
4298         /* If DCB is not supported, only default TC is supported */
4299         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4300                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4301                 return I40E_NOT_SUPPORTED;
4302         }
4303
4304         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4305                 PMD_DRV_LOG(ERR,
4306                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4307                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4308                 return I40E_NOT_SUPPORTED;
4309         }
4310         return I40E_SUCCESS;
4311 }
4312
4313 int
4314 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4315                                 struct i40e_vsi_vlan_pvid_info *info)
4316 {
4317         struct i40e_hw *hw;
4318         struct i40e_vsi_context ctxt;
4319         uint8_t vlan_flags = 0;
4320         int ret;
4321
4322         if (vsi == NULL || info == NULL) {
4323                 PMD_DRV_LOG(ERR, "invalid parameters");
4324                 return I40E_ERR_PARAM;
4325         }
4326
4327         if (info->on) {
4328                 vsi->info.pvid = info->config.pvid;
4329                 /**
4330                  * If insert pvid is enabled, only tagged pkts are
4331                  * allowed to be sent out.
4332                  */
4333                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4334                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4335         } else {
4336                 vsi->info.pvid = 0;
4337                 if (info->config.reject.tagged == 0)
4338                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4339
4340                 if (info->config.reject.untagged == 0)
4341                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4342         }
4343         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4344                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4345         vsi->info.port_vlan_flags |= vlan_flags;
4346         vsi->info.valid_sections =
4347                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4348         memset(&ctxt, 0, sizeof(ctxt));
4349         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4350         ctxt.seid = vsi->seid;
4351
4352         hw = I40E_VSI_TO_HW(vsi);
4353         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4354         if (ret != I40E_SUCCESS)
4355                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4356
4357         return ret;
4358 }
4359
4360 static int
4361 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4362 {
4363         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4364         int i, ret;
4365         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4366
4367         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4368         if (ret != I40E_SUCCESS)
4369                 return ret;
4370
4371         if (!vsi->seid) {
4372                 PMD_DRV_LOG(ERR, "seid not valid");
4373                 return -EINVAL;
4374         }
4375
4376         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4377         tc_bw_data.tc_valid_bits = enabled_tcmap;
4378         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4379                 tc_bw_data.tc_bw_credits[i] =
4380                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4381
4382         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4383         if (ret != I40E_SUCCESS) {
4384                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4385                 return ret;
4386         }
4387
4388         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4389                                         sizeof(vsi->info.qs_handle));
4390         return I40E_SUCCESS;
4391 }
4392
4393 static enum i40e_status_code
4394 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4395                                  struct i40e_aqc_vsi_properties_data *info,
4396                                  uint8_t enabled_tcmap)
4397 {
4398         enum i40e_status_code ret;
4399         int i, total_tc = 0;
4400         uint16_t qpnum_per_tc, bsf, qp_idx;
4401
4402         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4403         if (ret != I40E_SUCCESS)
4404                 return ret;
4405
4406         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4407                 if (enabled_tcmap & (1 << i))
4408                         total_tc++;
4409         if (total_tc == 0)
4410                 total_tc = 1;
4411         vsi->enabled_tc = enabled_tcmap;
4412
4413         /* Number of queues per enabled TC */
4414         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4415         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4416         bsf = rte_bsf32(qpnum_per_tc);
4417
4418         /* Adjust the queue number to actual queues that can be applied */
4419         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4420                 vsi->nb_qps = qpnum_per_tc * total_tc;
4421
4422         /**
4423          * Configure TC and queue mapping parameters, for enabled TC,
4424          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4425          * default queue will serve it.
4426          */
4427         qp_idx = 0;
4428         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4429                 if (vsi->enabled_tc & (1 << i)) {
4430                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4431                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4432                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4433                         qp_idx += qpnum_per_tc;
4434                 } else
4435                         info->tc_mapping[i] = 0;
4436         }
4437
4438         /* Associate queue number with VSI */
4439         if (vsi->type == I40E_VSI_SRIOV) {
4440                 info->mapping_flags |=
4441                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4442                 for (i = 0; i < vsi->nb_qps; i++)
4443                         info->queue_mapping[i] =
4444                                 rte_cpu_to_le_16(vsi->base_queue + i);
4445         } else {
4446                 info->mapping_flags |=
4447                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4448                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4449         }
4450         info->valid_sections |=
4451                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4452
4453         return I40E_SUCCESS;
4454 }
4455
4456 static int
4457 i40e_veb_release(struct i40e_veb *veb)
4458 {
4459         struct i40e_vsi *vsi;
4460         struct i40e_hw *hw;
4461
4462         if (veb == NULL)
4463                 return -EINVAL;
4464
4465         if (!TAILQ_EMPTY(&veb->head)) {
4466                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4467                 return -EACCES;
4468         }
4469         /* associate_vsi field is NULL for floating VEB */
4470         if (veb->associate_vsi != NULL) {
4471                 vsi = veb->associate_vsi;
4472                 hw = I40E_VSI_TO_HW(vsi);
4473
4474                 vsi->uplink_seid = veb->uplink_seid;
4475                 vsi->veb = NULL;
4476         } else {
4477                 veb->associate_pf->main_vsi->floating_veb = NULL;
4478                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4479         }
4480
4481         i40e_aq_delete_element(hw, veb->seid, NULL);
4482         rte_free(veb);
4483         return I40E_SUCCESS;
4484 }
4485
4486 /* Setup a veb */
4487 static struct i40e_veb *
4488 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4489 {
4490         struct i40e_veb *veb;
4491         int ret;
4492         struct i40e_hw *hw;
4493
4494         if (pf == NULL) {
4495                 PMD_DRV_LOG(ERR,
4496                             "veb setup failed, associated PF shouldn't null");
4497                 return NULL;
4498         }
4499         hw = I40E_PF_TO_HW(pf);
4500
4501         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4502         if (!veb) {
4503                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4504                 goto fail;
4505         }
4506
4507         veb->associate_vsi = vsi;
4508         veb->associate_pf = pf;
4509         TAILQ_INIT(&veb->head);
4510         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4511
4512         /* create floating veb if vsi is NULL */
4513         if (vsi != NULL) {
4514                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4515                                       I40E_DEFAULT_TCMAP, false,
4516                                       &veb->seid, false, NULL);
4517         } else {
4518                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4519                                       true, &veb->seid, false, NULL);
4520         }
4521
4522         if (ret != I40E_SUCCESS) {
4523                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4524                             hw->aq.asq_last_status);
4525                 goto fail;
4526         }
4527         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4528
4529         /* get statistics index */
4530         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4531                                 &veb->stats_idx, NULL, NULL, NULL);
4532         if (ret != I40E_SUCCESS) {
4533                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4534                             hw->aq.asq_last_status);
4535                 goto fail;
4536         }
4537         /* Get VEB bandwidth, to be implemented */
4538         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4539         if (vsi)
4540                 vsi->uplink_seid = veb->seid;
4541
4542         return veb;
4543 fail:
4544         rte_free(veb);
4545         return NULL;
4546 }
4547
4548 int
4549 i40e_vsi_release(struct i40e_vsi *vsi)
4550 {
4551         struct i40e_pf *pf;
4552         struct i40e_hw *hw;
4553         struct i40e_vsi_list *vsi_list;
4554         void *temp;
4555         int ret;
4556         struct i40e_mac_filter *f;
4557         uint16_t user_param;
4558
4559         if (!vsi)
4560                 return I40E_SUCCESS;
4561
4562         if (!vsi->adapter)
4563                 return -EFAULT;
4564
4565         user_param = vsi->user_param;
4566
4567         pf = I40E_VSI_TO_PF(vsi);
4568         hw = I40E_VSI_TO_HW(vsi);
4569
4570         /* VSI has child to attach, release child first */
4571         if (vsi->veb) {
4572                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4573                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4574                                 return -1;
4575                 }
4576                 i40e_veb_release(vsi->veb);
4577         }
4578
4579         if (vsi->floating_veb) {
4580                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4581                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4582                                 return -1;
4583                 }
4584         }
4585
4586         /* Remove all macvlan filters of the VSI */
4587         i40e_vsi_remove_all_macvlan_filter(vsi);
4588         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4589                 rte_free(f);
4590
4591         if (vsi->type != I40E_VSI_MAIN &&
4592             ((vsi->type != I40E_VSI_SRIOV) ||
4593             !pf->floating_veb_list[user_param])) {
4594                 /* Remove vsi from parent's sibling list */
4595                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4596                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4597                         return I40E_ERR_PARAM;
4598                 }
4599                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4600                                 &vsi->sib_vsi_list, list);
4601
4602                 /* Remove all switch element of the VSI */
4603                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4604                 if (ret != I40E_SUCCESS)
4605                         PMD_DRV_LOG(ERR, "Failed to delete element");
4606         }
4607
4608         if ((vsi->type == I40E_VSI_SRIOV) &&
4609             pf->floating_veb_list[user_param]) {
4610                 /* Remove vsi from parent's sibling list */
4611                 if (vsi->parent_vsi == NULL ||
4612                     vsi->parent_vsi->floating_veb == NULL) {
4613                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4614                         return I40E_ERR_PARAM;
4615                 }
4616                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4617                              &vsi->sib_vsi_list, list);
4618
4619                 /* Remove all switch element of the VSI */
4620                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4621                 if (ret != I40E_SUCCESS)
4622                         PMD_DRV_LOG(ERR, "Failed to delete element");
4623         }
4624
4625         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4626
4627         if (vsi->type != I40E_VSI_SRIOV)
4628                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4629         rte_free(vsi);
4630
4631         return I40E_SUCCESS;
4632 }
4633
4634 static int
4635 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4636 {
4637         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4638         struct i40e_aqc_remove_macvlan_element_data def_filter;
4639         struct i40e_mac_filter_info filter;
4640         int ret;
4641
4642         if (vsi->type != I40E_VSI_MAIN)
4643                 return I40E_ERR_CONFIG;
4644         memset(&def_filter, 0, sizeof(def_filter));
4645         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4646                                         ETH_ADDR_LEN);
4647         def_filter.vlan_tag = 0;
4648         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4649                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4650         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4651         if (ret != I40E_SUCCESS) {
4652                 struct i40e_mac_filter *f;
4653                 struct ether_addr *mac;
4654
4655                 PMD_DRV_LOG(DEBUG,
4656                             "Cannot remove the default macvlan filter");
4657                 /* It needs to add the permanent mac into mac list */
4658                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4659                 if (f == NULL) {
4660                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4661                         return I40E_ERR_NO_MEMORY;
4662                 }
4663                 mac = &f->mac_info.mac_addr;
4664                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4665                                 ETH_ADDR_LEN);
4666                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4667                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4668                 vsi->mac_num++;
4669
4670                 return ret;
4671         }
4672         (void)rte_memcpy(&filter.mac_addr,
4673                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4674         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4675         return i40e_vsi_add_mac(vsi, &filter);
4676 }
4677
4678 /*
4679  * i40e_vsi_get_bw_config - Query VSI BW Information
4680  * @vsi: the VSI to be queried
4681  *
4682  * Returns 0 on success, negative value on failure
4683  */
4684 static enum i40e_status_code
4685 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4686 {
4687         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4688         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4689         struct i40e_hw *hw = &vsi->adapter->hw;
4690         i40e_status ret;
4691         int i;
4692         uint32_t bw_max;
4693
4694         memset(&bw_config, 0, sizeof(bw_config));
4695         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4696         if (ret != I40E_SUCCESS) {
4697                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4698                             hw->aq.asq_last_status);
4699                 return ret;
4700         }
4701
4702         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4703         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4704                                         &ets_sla_config, NULL);
4705         if (ret != I40E_SUCCESS) {
4706                 PMD_DRV_LOG(ERR,
4707                         "VSI failed to get TC bandwdith configuration %u",
4708                         hw->aq.asq_last_status);
4709                 return ret;
4710         }
4711
4712         /* store and print out BW info */
4713         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4714         vsi->bw_info.bw_max = bw_config.max_bw;
4715         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4716         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4717         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4718                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4719                      I40E_16_BIT_WIDTH);
4720         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4721                 vsi->bw_info.bw_ets_share_credits[i] =
4722                                 ets_sla_config.share_credits[i];
4723                 vsi->bw_info.bw_ets_credits[i] =
4724                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4725                 /* 4 bits per TC, 4th bit is reserved */
4726                 vsi->bw_info.bw_ets_max[i] =
4727                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4728                                   RTE_LEN2MASK(3, uint8_t));
4729                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4730                             vsi->bw_info.bw_ets_share_credits[i]);
4731                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4732                             vsi->bw_info.bw_ets_credits[i]);
4733                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4734                             vsi->bw_info.bw_ets_max[i]);
4735         }
4736
4737         return I40E_SUCCESS;
4738 }
4739
4740 /* i40e_enable_pf_lb
4741  * @pf: pointer to the pf structure
4742  *
4743  * allow loopback on pf
4744  */
4745 static inline void
4746 i40e_enable_pf_lb(struct i40e_pf *pf)
4747 {
4748         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4749         struct i40e_vsi_context ctxt;
4750         int ret;
4751
4752         /* Use the FW API if FW >= v5.0 */
4753         if (hw->aq.fw_maj_ver < 5) {
4754                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4755                 return;
4756         }
4757
4758         memset(&ctxt, 0, sizeof(ctxt));
4759         ctxt.seid = pf->main_vsi_seid;
4760         ctxt.pf_num = hw->pf_id;
4761         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4762         if (ret) {
4763                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4764                             ret, hw->aq.asq_last_status);
4765                 return;
4766         }
4767         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4768         ctxt.info.valid_sections =
4769                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4770         ctxt.info.switch_id |=
4771                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4772
4773         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4774         if (ret)
4775                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4776                             hw->aq.asq_last_status);
4777 }
4778
4779 /* Setup a VSI */
4780 struct i40e_vsi *
4781 i40e_vsi_setup(struct i40e_pf *pf,
4782                enum i40e_vsi_type type,
4783                struct i40e_vsi *uplink_vsi,
4784                uint16_t user_param)
4785 {
4786         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4787         struct i40e_vsi *vsi;
4788         struct i40e_mac_filter_info filter;
4789         int ret;
4790         struct i40e_vsi_context ctxt;
4791         struct ether_addr broadcast =
4792                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4793
4794         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4795             uplink_vsi == NULL) {
4796                 PMD_DRV_LOG(ERR,
4797                         "VSI setup failed, VSI link shouldn't be NULL");
4798                 return NULL;
4799         }
4800
4801         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4802                 PMD_DRV_LOG(ERR,
4803                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4804                 return NULL;
4805         }
4806
4807         /* two situations
4808          * 1.type is not MAIN and uplink vsi is not NULL
4809          * If uplink vsi didn't setup VEB, create one first under veb field
4810          * 2.type is SRIOV and the uplink is NULL
4811          * If floating VEB is NULL, create one veb under floating veb field
4812          */
4813
4814         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4815             uplink_vsi->veb == NULL) {
4816                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4817
4818                 if (uplink_vsi->veb == NULL) {
4819                         PMD_DRV_LOG(ERR, "VEB setup failed");
4820                         return NULL;
4821                 }
4822                 /* set ALLOWLOOPBACk on pf, when veb is created */
4823                 i40e_enable_pf_lb(pf);
4824         }
4825
4826         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4827             pf->main_vsi->floating_veb == NULL) {
4828                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4829
4830                 if (pf->main_vsi->floating_veb == NULL) {
4831                         PMD_DRV_LOG(ERR, "VEB setup failed");
4832                         return NULL;
4833                 }
4834         }
4835
4836         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4837         if (!vsi) {
4838                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4839                 return NULL;
4840         }
4841         TAILQ_INIT(&vsi->mac_list);
4842         vsi->type = type;
4843         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4844         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4845         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4846         vsi->user_param = user_param;
4847         vsi->vlan_anti_spoof_on = 0;
4848         vsi->vlan_filter_on = 0;
4849         /* Allocate queues */
4850         switch (vsi->type) {
4851         case I40E_VSI_MAIN  :
4852                 vsi->nb_qps = pf->lan_nb_qps;
4853                 break;
4854         case I40E_VSI_SRIOV :
4855                 vsi->nb_qps = pf->vf_nb_qps;
4856                 break;
4857         case I40E_VSI_VMDQ2:
4858                 vsi->nb_qps = pf->vmdq_nb_qps;
4859                 break;
4860         case I40E_VSI_FDIR:
4861                 vsi->nb_qps = pf->fdir_nb_qps;
4862                 break;
4863         default:
4864                 goto fail_mem;
4865         }
4866         /*
4867          * The filter status descriptor is reported in rx queue 0,
4868          * while the tx queue for fdir filter programming has no
4869          * such constraints, can be non-zero queues.
4870          * To simplify it, choose FDIR vsi use queue 0 pair.
4871          * To make sure it will use queue 0 pair, queue allocation
4872          * need be done before this function is called
4873          */
4874         if (type != I40E_VSI_FDIR) {
4875                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4876                         if (ret < 0) {
4877                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4878                                                 vsi->seid, ret);
4879                                 goto fail_mem;
4880                         }
4881                         vsi->base_queue = ret;
4882         } else
4883                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4884
4885         /* VF has MSIX interrupt in VF range, don't allocate here */
4886         if (type == I40E_VSI_MAIN) {
4887                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4888                                           RTE_MIN(vsi->nb_qps,
4889                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4890                 if (ret < 0) {
4891                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4892                                     vsi->seid, ret);
4893                         goto fail_queue_alloc;
4894                 }
4895                 vsi->msix_intr = ret;
4896                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4897         } else if (type != I40E_VSI_SRIOV) {
4898                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4899                 if (ret < 0) {
4900                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4901                         goto fail_queue_alloc;
4902                 }
4903                 vsi->msix_intr = ret;
4904                 vsi->nb_msix = 1;
4905         } else {
4906                 vsi->msix_intr = 0;
4907                 vsi->nb_msix = 0;
4908         }
4909
4910         /* Add VSI */
4911         if (type == I40E_VSI_MAIN) {
4912                 /* For main VSI, no need to add since it's default one */
4913                 vsi->uplink_seid = pf->mac_seid;
4914                 vsi->seid = pf->main_vsi_seid;
4915                 /* Bind queues with specific MSIX interrupt */
4916                 /**
4917                  * Needs 2 interrupt at least, one for misc cause which will
4918                  * enabled from OS side, Another for queues binding the
4919                  * interrupt from device side only.
4920                  */
4921
4922                 /* Get default VSI parameters from hardware */
4923                 memset(&ctxt, 0, sizeof(ctxt));
4924                 ctxt.seid = vsi->seid;
4925                 ctxt.pf_num = hw->pf_id;
4926                 ctxt.uplink_seid = vsi->uplink_seid;
4927                 ctxt.vf_num = 0;
4928                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4929                 if (ret != I40E_SUCCESS) {
4930                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4931                         goto fail_msix_alloc;
4932                 }
4933                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4934                         sizeof(struct i40e_aqc_vsi_properties_data));
4935                 vsi->vsi_id = ctxt.vsi_number;
4936                 vsi->info.valid_sections = 0;
4937
4938                 /* Configure tc, enabled TC0 only */
4939                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4940                         I40E_SUCCESS) {
4941                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4942                         goto fail_msix_alloc;
4943                 }
4944
4945                 /* TC, queue mapping */
4946                 memset(&ctxt, 0, sizeof(ctxt));
4947                 vsi->info.valid_sections |=
4948                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4949                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4950                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4951                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4952                         sizeof(struct i40e_aqc_vsi_properties_data));
4953                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4954                                                 I40E_DEFAULT_TCMAP);
4955                 if (ret != I40E_SUCCESS) {
4956                         PMD_DRV_LOG(ERR,
4957                                 "Failed to configure TC queue mapping");
4958                         goto fail_msix_alloc;
4959                 }
4960                 ctxt.seid = vsi->seid;
4961                 ctxt.pf_num = hw->pf_id;
4962                 ctxt.uplink_seid = vsi->uplink_seid;
4963                 ctxt.vf_num = 0;
4964
4965                 /* Update VSI parameters */
4966                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4967                 if (ret != I40E_SUCCESS) {
4968                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4969                         goto fail_msix_alloc;
4970                 }
4971
4972                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4973                                                 sizeof(vsi->info.tc_mapping));
4974                 (void)rte_memcpy(&vsi->info.queue_mapping,
4975                                 &ctxt.info.queue_mapping,
4976                         sizeof(vsi->info.queue_mapping));
4977                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4978                 vsi->info.valid_sections = 0;
4979
4980                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4981                                 ETH_ADDR_LEN);
4982
4983                 /**
4984                  * Updating default filter settings are necessary to prevent
4985                  * reception of tagged packets.
4986                  * Some old firmware configurations load a default macvlan
4987                  * filter which accepts both tagged and untagged packets.
4988                  * The updating is to use a normal filter instead if needed.
4989                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4990                  * The firmware with correct configurations load the default
4991                  * macvlan filter which is expected and cannot be removed.
4992                  */
4993                 i40e_update_default_filter_setting(vsi);
4994                 i40e_config_qinq(hw, vsi);
4995         } else if (type == I40E_VSI_SRIOV) {
4996                 memset(&ctxt, 0, sizeof(ctxt));
4997                 /**
4998                  * For other VSI, the uplink_seid equals to uplink VSI's
4999                  * uplink_seid since they share same VEB
5000                  */
5001                 if (uplink_vsi == NULL)
5002                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5003                 else
5004                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5005                 ctxt.pf_num = hw->pf_id;
5006                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5007                 ctxt.uplink_seid = vsi->uplink_seid;
5008                 ctxt.connection_type = 0x1;
5009                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5010
5011                 /* Use the VEB configuration if FW >= v5.0 */
5012                 if (hw->aq.fw_maj_ver >= 5) {
5013                         /* Configure switch ID */
5014                         ctxt.info.valid_sections |=
5015                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5016                         ctxt.info.switch_id =
5017                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5018                 }
5019
5020                 /* Configure port/vlan */
5021                 ctxt.info.valid_sections |=
5022                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5023                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5024                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5025                                                 hw->func_caps.enabled_tcmap);
5026                 if (ret != I40E_SUCCESS) {
5027                         PMD_DRV_LOG(ERR,
5028                                 "Failed to configure TC queue mapping");
5029                         goto fail_msix_alloc;
5030                 }
5031
5032                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5033                 ctxt.info.valid_sections |=
5034                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5035                 /**
5036                  * Since VSI is not created yet, only configure parameter,
5037                  * will add vsi below.
5038                  */
5039
5040                 i40e_config_qinq(hw, vsi);
5041         } else if (type == I40E_VSI_VMDQ2) {
5042                 memset(&ctxt, 0, sizeof(ctxt));
5043                 /*
5044                  * For other VSI, the uplink_seid equals to uplink VSI's
5045                  * uplink_seid since they share same VEB
5046                  */
5047                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5048                 ctxt.pf_num = hw->pf_id;
5049                 ctxt.vf_num = 0;
5050                 ctxt.uplink_seid = vsi->uplink_seid;
5051                 ctxt.connection_type = 0x1;
5052                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5053
5054                 ctxt.info.valid_sections |=
5055                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5056                 /* user_param carries flag to enable loop back */
5057                 if (user_param) {
5058                         ctxt.info.switch_id =
5059                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5060                         ctxt.info.switch_id |=
5061                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5062                 }
5063
5064                 /* Configure port/vlan */
5065                 ctxt.info.valid_sections |=
5066                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5067                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5068                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5069                                                 I40E_DEFAULT_TCMAP);
5070                 if (ret != I40E_SUCCESS) {
5071                         PMD_DRV_LOG(ERR,
5072                                 "Failed to configure TC queue mapping");
5073                         goto fail_msix_alloc;
5074                 }
5075                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5076                 ctxt.info.valid_sections |=
5077                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5078         } else if (type == I40E_VSI_FDIR) {
5079                 memset(&ctxt, 0, sizeof(ctxt));
5080                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5081                 ctxt.pf_num = hw->pf_id;
5082                 ctxt.vf_num = 0;
5083                 ctxt.uplink_seid = vsi->uplink_seid;
5084                 ctxt.connection_type = 0x1;     /* regular data port */
5085                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5086                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5087                                                 I40E_DEFAULT_TCMAP);
5088                 if (ret != I40E_SUCCESS) {
5089                         PMD_DRV_LOG(ERR,
5090                                 "Failed to configure TC queue mapping.");
5091                         goto fail_msix_alloc;
5092                 }
5093                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5094                 ctxt.info.valid_sections |=
5095                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5096         } else {
5097                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5098                 goto fail_msix_alloc;
5099         }
5100
5101         if (vsi->type != I40E_VSI_MAIN) {
5102                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5103                 if (ret != I40E_SUCCESS) {
5104                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5105                                     hw->aq.asq_last_status);
5106                         goto fail_msix_alloc;
5107                 }
5108                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5109                 vsi->info.valid_sections = 0;
5110                 vsi->seid = ctxt.seid;
5111                 vsi->vsi_id = ctxt.vsi_number;
5112                 vsi->sib_vsi_list.vsi = vsi;
5113                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5114                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5115                                           &vsi->sib_vsi_list, list);
5116                 } else {
5117                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5118                                           &vsi->sib_vsi_list, list);
5119                 }
5120         }
5121
5122         /* MAC/VLAN configuration */
5123         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5124         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5125
5126         ret = i40e_vsi_add_mac(vsi, &filter);
5127         if (ret != I40E_SUCCESS) {
5128                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5129                 goto fail_msix_alloc;
5130         }
5131
5132         /* Get VSI BW information */
5133         i40e_vsi_get_bw_config(vsi);
5134         return vsi;
5135 fail_msix_alloc:
5136         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5137 fail_queue_alloc:
5138         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5139 fail_mem:
5140         rte_free(vsi);
5141         return NULL;
5142 }
5143
5144 /* Configure vlan filter on or off */
5145 int
5146 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5147 {
5148         int i, num;
5149         struct i40e_mac_filter *f;
5150         void *temp;
5151         struct i40e_mac_filter_info *mac_filter;
5152         enum rte_mac_filter_type desired_filter;
5153         int ret = I40E_SUCCESS;
5154
5155         if (on) {
5156                 /* Filter to match MAC and VLAN */
5157                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5158         } else {
5159                 /* Filter to match only MAC */
5160                 desired_filter = RTE_MAC_PERFECT_MATCH;
5161         }
5162
5163         num = vsi->mac_num;
5164
5165         mac_filter = rte_zmalloc("mac_filter_info_data",
5166                                  num * sizeof(*mac_filter), 0);
5167         if (mac_filter == NULL) {
5168                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5169                 return I40E_ERR_NO_MEMORY;
5170         }
5171
5172         i = 0;
5173
5174         /* Remove all existing mac */
5175         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5176                 mac_filter[i] = f->mac_info;
5177                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5178                 if (ret) {
5179                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5180                                     on ? "enable" : "disable");
5181                         goto DONE;
5182                 }
5183                 i++;
5184         }
5185
5186         /* Override with new filter */
5187         for (i = 0; i < num; i++) {
5188                 mac_filter[i].filter_type = desired_filter;
5189                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5190                 if (ret) {
5191                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5192                                     on ? "enable" : "disable");
5193                         goto DONE;
5194                 }
5195         }
5196
5197 DONE:
5198         rte_free(mac_filter);
5199         return ret;
5200 }
5201
5202 /* Configure vlan stripping on or off */
5203 int
5204 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5205 {
5206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5207         struct i40e_vsi_context ctxt;
5208         uint8_t vlan_flags;
5209         int ret = I40E_SUCCESS;
5210
5211         /* Check if it has been already on or off */
5212         if (vsi->info.valid_sections &
5213                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5214                 if (on) {
5215                         if ((vsi->info.port_vlan_flags &
5216                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5217                                 return 0; /* already on */
5218                 } else {
5219                         if ((vsi->info.port_vlan_flags &
5220                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5221                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5222                                 return 0; /* already off */
5223                 }
5224         }
5225
5226         if (on)
5227                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5228         else
5229                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5230         vsi->info.valid_sections =
5231                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5232         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5233         vsi->info.port_vlan_flags |= vlan_flags;
5234         ctxt.seid = vsi->seid;
5235         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5236         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5237         if (ret)
5238                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5239                             on ? "enable" : "disable");
5240
5241         return ret;
5242 }
5243
5244 static int
5245 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5246 {
5247         struct rte_eth_dev_data *data = dev->data;
5248         int ret;
5249         int mask = 0;
5250
5251         /* Apply vlan offload setting */
5252         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5253         i40e_vlan_offload_set(dev, mask);
5254
5255         /* Apply double-vlan setting, not implemented yet */
5256
5257         /* Apply pvid setting */
5258         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5259                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5260         if (ret)
5261                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5262
5263         return ret;
5264 }
5265
5266 static int
5267 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5268 {
5269         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5270
5271         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5272 }
5273
5274 static int
5275 i40e_update_flow_control(struct i40e_hw *hw)
5276 {
5277 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5278         struct i40e_link_status link_status;
5279         uint32_t rxfc = 0, txfc = 0, reg;
5280         uint8_t an_info;
5281         int ret;
5282
5283         memset(&link_status, 0, sizeof(link_status));
5284         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5285         if (ret != I40E_SUCCESS) {
5286                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5287                 goto write_reg; /* Disable flow control */
5288         }
5289
5290         an_info = hw->phy.link_info.an_info;
5291         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5292                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5293                 ret = I40E_ERR_NOT_READY;
5294                 goto write_reg; /* Disable flow control */
5295         }
5296         /**
5297          * If link auto negotiation is enabled, flow control needs to
5298          * be configured according to it
5299          */
5300         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5301         case I40E_LINK_PAUSE_RXTX:
5302                 rxfc = 1;
5303                 txfc = 1;
5304                 hw->fc.current_mode = I40E_FC_FULL;
5305                 break;
5306         case I40E_AQ_LINK_PAUSE_RX:
5307                 rxfc = 1;
5308                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5309                 break;
5310         case I40E_AQ_LINK_PAUSE_TX:
5311                 txfc = 1;
5312                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5313                 break;
5314         default:
5315                 hw->fc.current_mode = I40E_FC_NONE;
5316                 break;
5317         }
5318
5319 write_reg:
5320         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5321                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5322         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5323         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5324         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5325         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5326
5327         return ret;
5328 }
5329
5330 /* PF setup */
5331 static int
5332 i40e_pf_setup(struct i40e_pf *pf)
5333 {
5334         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5335         struct i40e_filter_control_settings settings;
5336         struct i40e_vsi *vsi;
5337         int ret;
5338
5339         /* Clear all stats counters */
5340         pf->offset_loaded = FALSE;
5341         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5342         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5343         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5344         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5345
5346         ret = i40e_pf_get_switch_config(pf);
5347         if (ret != I40E_SUCCESS) {
5348                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5349                 return ret;
5350         }
5351         if (pf->flags & I40E_FLAG_FDIR) {
5352                 /* make queue allocated first, let FDIR use queue pair 0*/
5353                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5354                 if (ret != I40E_FDIR_QUEUE_ID) {
5355                         PMD_DRV_LOG(ERR,
5356                                 "queue allocation fails for FDIR: ret =%d",
5357                                 ret);
5358                         pf->flags &= ~I40E_FLAG_FDIR;
5359                 }
5360         }
5361         /*  main VSI setup */
5362         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5363         if (!vsi) {
5364                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5365                 return I40E_ERR_NOT_READY;
5366         }
5367         pf->main_vsi = vsi;
5368
5369         /* Configure filter control */
5370         memset(&settings, 0, sizeof(settings));
5371         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5372                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5373         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5374                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5375         else {
5376                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5377                         hw->func_caps.rss_table_size);
5378                 return I40E_ERR_PARAM;
5379         }
5380         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5381                 hw->func_caps.rss_table_size);
5382         pf->hash_lut_size = hw->func_caps.rss_table_size;
5383
5384         /* Enable ethtype and macvlan filters */
5385         settings.enable_ethtype = TRUE;
5386         settings.enable_macvlan = TRUE;
5387         ret = i40e_set_filter_control(hw, &settings);
5388         if (ret)
5389                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5390                                                                 ret);
5391
5392         /* Update flow control according to the auto negotiation */
5393         i40e_update_flow_control(hw);
5394
5395         return I40E_SUCCESS;
5396 }
5397
5398 int
5399 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5400 {
5401         uint32_t reg;
5402         uint16_t j;
5403
5404         /**
5405          * Set or clear TX Queue Disable flags,
5406          * which is required by hardware.
5407          */
5408         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5409         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5410
5411         /* Wait until the request is finished */
5412         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5413                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5414                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5415                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5416                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5417                                                         & 0x1))) {
5418                         break;
5419                 }
5420         }
5421         if (on) {
5422                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5423                         return I40E_SUCCESS; /* already on, skip next steps */
5424
5425                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5426                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5427         } else {
5428                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5429                         return I40E_SUCCESS; /* already off, skip next steps */
5430                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5431         }
5432         /* Write the register */
5433         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5434         /* Check the result */
5435         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5436                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5437                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5438                 if (on) {
5439                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5440                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5441                                 break;
5442                 } else {
5443                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5444                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5445                                 break;
5446                 }
5447         }
5448         /* Check if it is timeout */
5449         if (j >= I40E_CHK_Q_ENA_COUNT) {
5450                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5451                             (on ? "enable" : "disable"), q_idx);
5452                 return I40E_ERR_TIMEOUT;
5453         }
5454
5455         return I40E_SUCCESS;
5456 }
5457
5458 /* Swith on or off the tx queues */
5459 static int
5460 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5461 {
5462         struct rte_eth_dev_data *dev_data = pf->dev_data;
5463         struct i40e_tx_queue *txq;
5464         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5465         uint16_t i;
5466         int ret;
5467
5468         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5469                 txq = dev_data->tx_queues[i];
5470                 /* Don't operate the queue if not configured or
5471                  * if starting only per queue */
5472                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5473                         continue;
5474                 if (on)
5475                         ret = i40e_dev_tx_queue_start(dev, i);
5476                 else
5477                         ret = i40e_dev_tx_queue_stop(dev, i);
5478                 if ( ret != I40E_SUCCESS)
5479                         return ret;
5480         }
5481
5482         return I40E_SUCCESS;
5483 }
5484
5485 int
5486 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5487 {
5488         uint32_t reg;
5489         uint16_t j;
5490
5491         /* Wait until the request is finished */
5492         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5493                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5494                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5495                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5496                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5497                         break;
5498         }
5499
5500         if (on) {
5501                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5502                         return I40E_SUCCESS; /* Already on, skip next steps */
5503                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5504         } else {
5505                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5506                         return I40E_SUCCESS; /* Already off, skip next steps */
5507                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5508         }
5509
5510         /* Write the register */
5511         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5512         /* Check the result */
5513         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5514                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5515                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5516                 if (on) {
5517                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5518                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5519                                 break;
5520                 } else {
5521                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5522                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5523                                 break;
5524                 }
5525         }
5526
5527         /* Check if it is timeout */
5528         if (j >= I40E_CHK_Q_ENA_COUNT) {
5529                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5530                             (on ? "enable" : "disable"), q_idx);
5531                 return I40E_ERR_TIMEOUT;
5532         }
5533
5534         return I40E_SUCCESS;
5535 }
5536 /* Switch on or off the rx queues */
5537 static int
5538 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5539 {
5540         struct rte_eth_dev_data *dev_data = pf->dev_data;
5541         struct i40e_rx_queue *rxq;
5542         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5543         uint16_t i;
5544         int ret;
5545
5546         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5547                 rxq = dev_data->rx_queues[i];
5548                 /* Don't operate the queue if not configured or
5549                  * if starting only per queue */
5550                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5551                         continue;
5552                 if (on)
5553                         ret = i40e_dev_rx_queue_start(dev, i);
5554                 else
5555                         ret = i40e_dev_rx_queue_stop(dev, i);
5556                 if (ret != I40E_SUCCESS)
5557                         return ret;
5558         }
5559
5560         return I40E_SUCCESS;
5561 }
5562
5563 /* Switch on or off all the rx/tx queues */
5564 int
5565 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5566 {
5567         int ret;
5568
5569         if (on) {
5570                 /* enable rx queues before enabling tx queues */
5571                 ret = i40e_dev_switch_rx_queues(pf, on);
5572                 if (ret) {
5573                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5574                         return ret;
5575                 }
5576                 ret = i40e_dev_switch_tx_queues(pf, on);
5577         } else {
5578                 /* Stop tx queues before stopping rx queues */
5579                 ret = i40e_dev_switch_tx_queues(pf, on);
5580                 if (ret) {
5581                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5582                         return ret;
5583                 }
5584                 ret = i40e_dev_switch_rx_queues(pf, on);
5585         }
5586
5587         return ret;
5588 }
5589
5590 /* Initialize VSI for TX */
5591 static int
5592 i40e_dev_tx_init(struct i40e_pf *pf)
5593 {
5594         struct rte_eth_dev_data *data = pf->dev_data;
5595         uint16_t i;
5596         uint32_t ret = I40E_SUCCESS;
5597         struct i40e_tx_queue *txq;
5598
5599         for (i = 0; i < data->nb_tx_queues; i++) {
5600                 txq = data->tx_queues[i];
5601                 if (!txq || !txq->q_set)
5602                         continue;
5603                 ret = i40e_tx_queue_init(txq);
5604                 if (ret != I40E_SUCCESS)
5605                         break;
5606         }
5607         if (ret == I40E_SUCCESS)
5608                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5609                                      ->eth_dev);
5610
5611         return ret;
5612 }
5613
5614 /* Initialize VSI for RX */
5615 static int
5616 i40e_dev_rx_init(struct i40e_pf *pf)
5617 {
5618         struct rte_eth_dev_data *data = pf->dev_data;
5619         int ret = I40E_SUCCESS;
5620         uint16_t i;
5621         struct i40e_rx_queue *rxq;
5622
5623         i40e_pf_config_mq_rx(pf);
5624         for (i = 0; i < data->nb_rx_queues; i++) {
5625                 rxq = data->rx_queues[i];
5626                 if (!rxq || !rxq->q_set)
5627                         continue;
5628
5629                 ret = i40e_rx_queue_init(rxq);
5630                 if (ret != I40E_SUCCESS) {
5631                         PMD_DRV_LOG(ERR,
5632                                 "Failed to do RX queue initialization");
5633                         break;
5634                 }
5635         }
5636         if (ret == I40E_SUCCESS)
5637                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5638                                      ->eth_dev);
5639
5640         return ret;
5641 }
5642
5643 static int
5644 i40e_dev_rxtx_init(struct i40e_pf *pf)
5645 {
5646         int err;
5647
5648         err = i40e_dev_tx_init(pf);
5649         if (err) {
5650                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5651                 return err;
5652         }
5653         err = i40e_dev_rx_init(pf);
5654         if (err) {
5655                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5656                 return err;
5657         }
5658
5659         return err;
5660 }
5661
5662 static int
5663 i40e_vmdq_setup(struct rte_eth_dev *dev)
5664 {
5665         struct rte_eth_conf *conf = &dev->data->dev_conf;
5666         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5667         int i, err, conf_vsis, j, loop;
5668         struct i40e_vsi *vsi;
5669         struct i40e_vmdq_info *vmdq_info;
5670         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5671         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5672
5673         /*
5674          * Disable interrupt to avoid message from VF. Furthermore, it will
5675          * avoid race condition in VSI creation/destroy.
5676          */
5677         i40e_pf_disable_irq0(hw);
5678
5679         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5680                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5681                 return -ENOTSUP;
5682         }
5683
5684         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5685         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5686                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5687                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5688                         pf->max_nb_vmdq_vsi);
5689                 return -ENOTSUP;
5690         }
5691
5692         if (pf->vmdq != NULL) {
5693                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5694                 return 0;
5695         }
5696
5697         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5698                                 sizeof(*vmdq_info) * conf_vsis, 0);
5699
5700         if (pf->vmdq == NULL) {
5701                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5702                 return -ENOMEM;
5703         }
5704
5705         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5706
5707         /* Create VMDQ VSI */
5708         for (i = 0; i < conf_vsis; i++) {
5709                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5710                                 vmdq_conf->enable_loop_back);
5711                 if (vsi == NULL) {
5712                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5713                         err = -1;
5714                         goto err_vsi_setup;
5715                 }
5716                 vmdq_info = &pf->vmdq[i];
5717                 vmdq_info->pf = pf;
5718                 vmdq_info->vsi = vsi;
5719         }
5720         pf->nb_cfg_vmdq_vsi = conf_vsis;
5721
5722         /* Configure Vlan */
5723         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5724         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5725                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5726                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5727                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5728                                         vmdq_conf->pool_map[i].vlan_id, j);
5729
5730                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5731                                                 vmdq_conf->pool_map[i].vlan_id);
5732                                 if (err) {
5733                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5734                                         err = -1;
5735                                         goto err_vsi_setup;
5736                                 }
5737                         }
5738                 }
5739         }
5740
5741         i40e_pf_enable_irq0(hw);
5742
5743         return 0;
5744
5745 err_vsi_setup:
5746         for (i = 0; i < conf_vsis; i++)
5747                 if (pf->vmdq[i].vsi == NULL)
5748                         break;
5749                 else
5750                         i40e_vsi_release(pf->vmdq[i].vsi);
5751
5752         rte_free(pf->vmdq);
5753         pf->vmdq = NULL;
5754         i40e_pf_enable_irq0(hw);
5755         return err;
5756 }
5757
5758 static void
5759 i40e_stat_update_32(struct i40e_hw *hw,
5760                    uint32_t reg,
5761                    bool offset_loaded,
5762                    uint64_t *offset,
5763                    uint64_t *stat)
5764 {
5765         uint64_t new_data;
5766
5767         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5768         if (!offset_loaded)
5769                 *offset = new_data;
5770
5771         if (new_data >= *offset)
5772                 *stat = (uint64_t)(new_data - *offset);
5773         else
5774                 *stat = (uint64_t)((new_data +
5775                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5776 }
5777
5778 static void
5779 i40e_stat_update_48(struct i40e_hw *hw,
5780                    uint32_t hireg,
5781                    uint32_t loreg,
5782                    bool offset_loaded,
5783                    uint64_t *offset,
5784                    uint64_t *stat)
5785 {
5786         uint64_t new_data;
5787
5788         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5789         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5790                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5791
5792         if (!offset_loaded)
5793                 *offset = new_data;
5794
5795         if (new_data >= *offset)
5796                 *stat = new_data - *offset;
5797         else
5798                 *stat = (uint64_t)((new_data +
5799                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5800
5801         *stat &= I40E_48_BIT_MASK;
5802 }
5803
5804 /* Disable IRQ0 */
5805 void
5806 i40e_pf_disable_irq0(struct i40e_hw *hw)
5807 {
5808         /* Disable all interrupt types */
5809         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5810         I40E_WRITE_FLUSH(hw);
5811 }
5812
5813 /* Enable IRQ0 */
5814 void
5815 i40e_pf_enable_irq0(struct i40e_hw *hw)
5816 {
5817         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5818                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5819                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5820                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5821         I40E_WRITE_FLUSH(hw);
5822 }
5823
5824 static void
5825 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5826 {
5827         /* read pending request and disable first */
5828         i40e_pf_disable_irq0(hw);
5829         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5830         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5831                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5832
5833         if (no_queue)
5834                 /* Link no queues with irq0 */
5835                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5836                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5837 }
5838
5839 static void
5840 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5841 {
5842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5843         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5844         int i;
5845         uint16_t abs_vf_id;
5846         uint32_t index, offset, val;
5847
5848         if (!pf->vfs)
5849                 return;
5850         /**
5851          * Try to find which VF trigger a reset, use absolute VF id to access
5852          * since the reg is global register.
5853          */
5854         for (i = 0; i < pf->vf_num; i++) {
5855                 abs_vf_id = hw->func_caps.vf_base_id + i;
5856                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5857                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5858                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5859                 /* VFR event occurred */
5860                 if (val & (0x1 << offset)) {
5861                         int ret;
5862
5863                         /* Clear the event first */
5864                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5865                                                         (0x1 << offset));
5866                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5867                         /**
5868                          * Only notify a VF reset event occurred,
5869                          * don't trigger another SW reset
5870                          */
5871                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5872                         if (ret != I40E_SUCCESS)
5873                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5874                 }
5875         }
5876 }
5877
5878 static void
5879 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5880 {
5881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5882         int i;
5883
5884         for (i = 0; i < pf->vf_num; i++)
5885                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5886 }
5887
5888 static void
5889 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5890 {
5891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5892         struct i40e_arq_event_info info;
5893         uint16_t pending, opcode;
5894         int ret;
5895
5896         info.buf_len = I40E_AQ_BUF_SZ;
5897         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5898         if (!info.msg_buf) {
5899                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5900                 return;
5901         }
5902
5903         pending = 1;
5904         while (pending) {
5905                 ret = i40e_clean_arq_element(hw, &info, &pending);
5906
5907                 if (ret != I40E_SUCCESS) {
5908                         PMD_DRV_LOG(INFO,
5909                                 "Failed to read msg from AdminQ, aq_err: %u",
5910                                 hw->aq.asq_last_status);
5911                         break;
5912                 }
5913                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5914
5915                 switch (opcode) {
5916                 case i40e_aqc_opc_send_msg_to_pf:
5917                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5918                         i40e_pf_host_handle_vf_msg(dev,
5919                                         rte_le_to_cpu_16(info.desc.retval),
5920                                         rte_le_to_cpu_32(info.desc.cookie_high),
5921                                         rte_le_to_cpu_32(info.desc.cookie_low),
5922                                         info.msg_buf,
5923                                         info.msg_len);
5924                         break;
5925                 case i40e_aqc_opc_get_link_status:
5926                         ret = i40e_dev_link_update(dev, 0);
5927                         if (!ret)
5928                                 _rte_eth_dev_callback_process(dev,
5929                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5930                         break;
5931                 default:
5932                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5933                                     opcode);
5934                         break;
5935                 }
5936         }
5937         rte_free(info.msg_buf);
5938 }
5939
5940 /**
5941  * Interrupt handler triggered by NIC  for handling
5942  * specific interrupt.
5943  *
5944  * @param handle
5945  *  Pointer to interrupt handle.
5946  * @param param
5947  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5948  *
5949  * @return
5950  *  void
5951  */
5952 static void
5953 i40e_dev_interrupt_handler(void *param)
5954 {
5955         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5956         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5957         uint32_t icr0;
5958
5959         /* Disable interrupt */
5960         i40e_pf_disable_irq0(hw);
5961
5962         /* read out interrupt causes */
5963         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5964
5965         /* No interrupt event indicated */
5966         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5967                 PMD_DRV_LOG(INFO, "No interrupt event");
5968                 goto done;
5969         }
5970         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5971                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5972         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5973                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5974         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5975                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5976         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5977                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5978         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5979                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5980         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5981                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5982         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5983                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5984
5985         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5986                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5987                 i40e_dev_handle_vfr_event(dev);
5988         }
5989         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5990                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5991                 i40e_dev_handle_aq_msg(dev);
5992         }
5993
5994 done:
5995         /* Enable interrupt */
5996         i40e_pf_enable_irq0(hw);
5997         rte_intr_enable(dev->intr_handle);
5998 }
5999
6000 int
6001 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6002                          struct i40e_macvlan_filter *filter,
6003                          int total)
6004 {
6005         int ele_num, ele_buff_size;
6006         int num, actual_num, i;
6007         uint16_t flags;
6008         int ret = I40E_SUCCESS;
6009         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6010         struct i40e_aqc_add_macvlan_element_data *req_list;
6011
6012         if (filter == NULL  || total == 0)
6013                 return I40E_ERR_PARAM;
6014         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6015         ele_buff_size = hw->aq.asq_buf_size;
6016
6017         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6018         if (req_list == NULL) {
6019                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6020                 return I40E_ERR_NO_MEMORY;
6021         }
6022
6023         num = 0;
6024         do {
6025                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6026                 memset(req_list, 0, ele_buff_size);
6027
6028                 for (i = 0; i < actual_num; i++) {
6029                         (void)rte_memcpy(req_list[i].mac_addr,
6030                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6031                         req_list[i].vlan_tag =
6032                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6033
6034                         switch (filter[num + i].filter_type) {
6035                         case RTE_MAC_PERFECT_MATCH:
6036                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6037                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6038                                 break;
6039                         case RTE_MACVLAN_PERFECT_MATCH:
6040                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6041                                 break;
6042                         case RTE_MAC_HASH_MATCH:
6043                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6044                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6045                                 break;
6046                         case RTE_MACVLAN_HASH_MATCH:
6047                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6048                                 break;
6049                         default:
6050                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6051                                 ret = I40E_ERR_PARAM;
6052                                 goto DONE;
6053                         }
6054
6055                         req_list[i].queue_number = 0;
6056
6057                         req_list[i].flags = rte_cpu_to_le_16(flags);
6058                 }
6059
6060                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6061                                                 actual_num, NULL);
6062                 if (ret != I40E_SUCCESS) {
6063                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6064                         goto DONE;
6065                 }
6066                 num += actual_num;
6067         } while (num < total);
6068
6069 DONE:
6070         rte_free(req_list);
6071         return ret;
6072 }
6073
6074 int
6075 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6076                             struct i40e_macvlan_filter *filter,
6077                             int total)
6078 {
6079         int ele_num, ele_buff_size;
6080         int num, actual_num, i;
6081         uint16_t flags;
6082         int ret = I40E_SUCCESS;
6083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6084         struct i40e_aqc_remove_macvlan_element_data *req_list;
6085
6086         if (filter == NULL  || total == 0)
6087                 return I40E_ERR_PARAM;
6088
6089         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6090         ele_buff_size = hw->aq.asq_buf_size;
6091
6092         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6093         if (req_list == NULL) {
6094                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6095                 return I40E_ERR_NO_MEMORY;
6096         }
6097
6098         num = 0;
6099         do {
6100                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6101                 memset(req_list, 0, ele_buff_size);
6102
6103                 for (i = 0; i < actual_num; i++) {
6104                         (void)rte_memcpy(req_list[i].mac_addr,
6105                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6106                         req_list[i].vlan_tag =
6107                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6108
6109                         switch (filter[num + i].filter_type) {
6110                         case RTE_MAC_PERFECT_MATCH:
6111                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6112                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6113                                 break;
6114                         case RTE_MACVLAN_PERFECT_MATCH:
6115                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6116                                 break;
6117                         case RTE_MAC_HASH_MATCH:
6118                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6119                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6120                                 break;
6121                         case RTE_MACVLAN_HASH_MATCH:
6122                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6123                                 break;
6124                         default:
6125                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6126                                 ret = I40E_ERR_PARAM;
6127                                 goto DONE;
6128                         }
6129                         req_list[i].flags = rte_cpu_to_le_16(flags);
6130                 }
6131
6132                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6133                                                 actual_num, NULL);
6134                 if (ret != I40E_SUCCESS) {
6135                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6136                         goto DONE;
6137                 }
6138                 num += actual_num;
6139         } while (num < total);
6140
6141 DONE:
6142         rte_free(req_list);
6143         return ret;
6144 }
6145
6146 /* Find out specific MAC filter */
6147 static struct i40e_mac_filter *
6148 i40e_find_mac_filter(struct i40e_vsi *vsi,
6149                          struct ether_addr *macaddr)
6150 {
6151         struct i40e_mac_filter *f;
6152
6153         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6154                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6155                         return f;
6156         }
6157
6158         return NULL;
6159 }
6160
6161 static bool
6162 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6163                          uint16_t vlan_id)
6164 {
6165         uint32_t vid_idx, vid_bit;
6166
6167         if (vlan_id > ETH_VLAN_ID_MAX)
6168                 return 0;
6169
6170         vid_idx = I40E_VFTA_IDX(vlan_id);
6171         vid_bit = I40E_VFTA_BIT(vlan_id);
6172
6173         if (vsi->vfta[vid_idx] & vid_bit)
6174                 return 1;
6175         else
6176                 return 0;
6177 }
6178
6179 static void
6180 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6181                        uint16_t vlan_id, bool on)
6182 {
6183         uint32_t vid_idx, vid_bit;
6184
6185         vid_idx = I40E_VFTA_IDX(vlan_id);
6186         vid_bit = I40E_VFTA_BIT(vlan_id);
6187
6188         if (on)
6189                 vsi->vfta[vid_idx] |= vid_bit;
6190         else
6191                 vsi->vfta[vid_idx] &= ~vid_bit;
6192 }
6193
6194 void
6195 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6196                      uint16_t vlan_id, bool on)
6197 {
6198         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6199         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6200         int ret;
6201
6202         if (vlan_id > ETH_VLAN_ID_MAX)
6203                 return;
6204
6205         i40e_store_vlan_filter(vsi, vlan_id, on);
6206
6207         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6208                 return;
6209
6210         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6211
6212         if (on) {
6213                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6214                                        &vlan_data, 1, NULL);
6215                 if (ret != I40E_SUCCESS)
6216                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6217         } else {
6218                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6219                                           &vlan_data, 1, NULL);
6220                 if (ret != I40E_SUCCESS)
6221                         PMD_DRV_LOG(ERR,
6222                                     "Failed to remove vlan filter");
6223         }
6224 }
6225
6226 /**
6227  * Find all vlan options for specific mac addr,
6228  * return with actual vlan found.
6229  */
6230 int
6231 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6232                            struct i40e_macvlan_filter *mv_f,
6233                            int num, struct ether_addr *addr)
6234 {
6235         int i;
6236         uint32_t j, k;
6237
6238         /**
6239          * Not to use i40e_find_vlan_filter to decrease the loop time,
6240          * although the code looks complex.
6241           */
6242         if (num < vsi->vlan_num)
6243                 return I40E_ERR_PARAM;
6244
6245         i = 0;
6246         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6247                 if (vsi->vfta[j]) {
6248                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6249                                 if (vsi->vfta[j] & (1 << k)) {
6250                                         if (i > num - 1) {
6251                                                 PMD_DRV_LOG(ERR,
6252                                                         "vlan number doesn't match");
6253                                                 return I40E_ERR_PARAM;
6254                                         }
6255                                         (void)rte_memcpy(&mv_f[i].macaddr,
6256                                                         addr, ETH_ADDR_LEN);
6257                                         mv_f[i].vlan_id =
6258                                                 j * I40E_UINT32_BIT_SIZE + k;
6259                                         i++;
6260                                 }
6261                         }
6262                 }
6263         }
6264         return I40E_SUCCESS;
6265 }
6266
6267 static inline int
6268 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6269                            struct i40e_macvlan_filter *mv_f,
6270                            int num,
6271                            uint16_t vlan)
6272 {
6273         int i = 0;
6274         struct i40e_mac_filter *f;
6275
6276         if (num < vsi->mac_num)
6277                 return I40E_ERR_PARAM;
6278
6279         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6280                 if (i > num - 1) {
6281                         PMD_DRV_LOG(ERR, "buffer number not match");
6282                         return I40E_ERR_PARAM;
6283                 }
6284                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6285                                 ETH_ADDR_LEN);
6286                 mv_f[i].vlan_id = vlan;
6287                 mv_f[i].filter_type = f->mac_info.filter_type;
6288                 i++;
6289         }
6290
6291         return I40E_SUCCESS;
6292 }
6293
6294 static int
6295 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6296 {
6297         int i, j, num;
6298         struct i40e_mac_filter *f;
6299         struct i40e_macvlan_filter *mv_f;
6300         int ret = I40E_SUCCESS;
6301
6302         if (vsi == NULL || vsi->mac_num == 0)
6303                 return I40E_ERR_PARAM;
6304
6305         /* Case that no vlan is set */
6306         if (vsi->vlan_num == 0)
6307                 num = vsi->mac_num;
6308         else
6309                 num = vsi->mac_num * vsi->vlan_num;
6310
6311         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6312         if (mv_f == NULL) {
6313                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6314                 return I40E_ERR_NO_MEMORY;
6315         }
6316
6317         i = 0;
6318         if (vsi->vlan_num == 0) {
6319                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6320                         (void)rte_memcpy(&mv_f[i].macaddr,
6321                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6322                         mv_f[i].filter_type = f->mac_info.filter_type;
6323                         mv_f[i].vlan_id = 0;
6324                         i++;
6325                 }
6326         } else {
6327                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6328                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6329                                         vsi->vlan_num, &f->mac_info.mac_addr);
6330                         if (ret != I40E_SUCCESS)
6331                                 goto DONE;
6332                         for (j = i; j < i + vsi->vlan_num; j++)
6333                                 mv_f[j].filter_type = f->mac_info.filter_type;
6334                         i += vsi->vlan_num;
6335                 }
6336         }
6337
6338         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6339 DONE:
6340         rte_free(mv_f);
6341
6342         return ret;
6343 }
6344
6345 int
6346 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6347 {
6348         struct i40e_macvlan_filter *mv_f;
6349         int mac_num;
6350         int ret = I40E_SUCCESS;
6351
6352         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6353                 return I40E_ERR_PARAM;
6354
6355         /* If it's already set, just return */
6356         if (i40e_find_vlan_filter(vsi,vlan))
6357                 return I40E_SUCCESS;
6358
6359         mac_num = vsi->mac_num;
6360
6361         if (mac_num == 0) {
6362                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6363                 return I40E_ERR_PARAM;
6364         }
6365
6366         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6367
6368         if (mv_f == NULL) {
6369                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6370                 return I40E_ERR_NO_MEMORY;
6371         }
6372
6373         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6374
6375         if (ret != I40E_SUCCESS)
6376                 goto DONE;
6377
6378         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6379
6380         if (ret != I40E_SUCCESS)
6381                 goto DONE;
6382
6383         i40e_set_vlan_filter(vsi, vlan, 1);
6384
6385         vsi->vlan_num++;
6386         ret = I40E_SUCCESS;
6387 DONE:
6388         rte_free(mv_f);
6389         return ret;
6390 }
6391
6392 int
6393 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6394 {
6395         struct i40e_macvlan_filter *mv_f;
6396         int mac_num;
6397         int ret = I40E_SUCCESS;
6398
6399         /**
6400          * Vlan 0 is the generic filter for untagged packets
6401          * and can't be removed.
6402          */
6403         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6404                 return I40E_ERR_PARAM;
6405
6406         /* If can't find it, just return */
6407         if (!i40e_find_vlan_filter(vsi, vlan))
6408                 return I40E_ERR_PARAM;
6409
6410         mac_num = vsi->mac_num;
6411
6412         if (mac_num == 0) {
6413                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6414                 return I40E_ERR_PARAM;
6415         }
6416
6417         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6418
6419         if (mv_f == NULL) {
6420                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6421                 return I40E_ERR_NO_MEMORY;
6422         }
6423
6424         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6425
6426         if (ret != I40E_SUCCESS)
6427                 goto DONE;
6428
6429         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6430
6431         if (ret != I40E_SUCCESS)
6432                 goto DONE;
6433
6434         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6435         if (vsi->vlan_num == 1) {
6436                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6437                 if (ret != I40E_SUCCESS)
6438                         goto DONE;
6439
6440                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6441                 if (ret != I40E_SUCCESS)
6442                         goto DONE;
6443         }
6444
6445         i40e_set_vlan_filter(vsi, vlan, 0);
6446
6447         vsi->vlan_num--;
6448         ret = I40E_SUCCESS;
6449 DONE:
6450         rte_free(mv_f);
6451         return ret;
6452 }
6453
6454 int
6455 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6456 {
6457         struct i40e_mac_filter *f;
6458         struct i40e_macvlan_filter *mv_f;
6459         int i, vlan_num = 0;
6460         int ret = I40E_SUCCESS;
6461
6462         /* If it's add and we've config it, return */
6463         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6464         if (f != NULL)
6465                 return I40E_SUCCESS;
6466         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6467                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6468
6469                 /**
6470                  * If vlan_num is 0, that's the first time to add mac,
6471                  * set mask for vlan_id 0.
6472                  */
6473                 if (vsi->vlan_num == 0) {
6474                         i40e_set_vlan_filter(vsi, 0, 1);
6475                         vsi->vlan_num = 1;
6476                 }
6477                 vlan_num = vsi->vlan_num;
6478         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6479                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6480                 vlan_num = 1;
6481
6482         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6483         if (mv_f == NULL) {
6484                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6485                 return I40E_ERR_NO_MEMORY;
6486         }
6487
6488         for (i = 0; i < vlan_num; i++) {
6489                 mv_f[i].filter_type = mac_filter->filter_type;
6490                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6491                                 ETH_ADDR_LEN);
6492         }
6493
6494         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6495                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6496                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6497                                         &mac_filter->mac_addr);
6498                 if (ret != I40E_SUCCESS)
6499                         goto DONE;
6500         }
6501
6502         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6503         if (ret != I40E_SUCCESS)
6504                 goto DONE;
6505
6506         /* Add the mac addr into mac list */
6507         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6508         if (f == NULL) {
6509                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6510                 ret = I40E_ERR_NO_MEMORY;
6511                 goto DONE;
6512         }
6513         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6514                         ETH_ADDR_LEN);
6515         f->mac_info.filter_type = mac_filter->filter_type;
6516         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6517         vsi->mac_num++;
6518
6519         ret = I40E_SUCCESS;
6520 DONE:
6521         rte_free(mv_f);
6522
6523         return ret;
6524 }
6525
6526 int
6527 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6528 {
6529         struct i40e_mac_filter *f;
6530         struct i40e_macvlan_filter *mv_f;
6531         int i, vlan_num;
6532         enum rte_mac_filter_type filter_type;
6533         int ret = I40E_SUCCESS;
6534
6535         /* Can't find it, return an error */
6536         f = i40e_find_mac_filter(vsi, addr);
6537         if (f == NULL)
6538                 return I40E_ERR_PARAM;
6539
6540         vlan_num = vsi->vlan_num;
6541         filter_type = f->mac_info.filter_type;
6542         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6543                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6544                 if (vlan_num == 0) {
6545                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6546                         return I40E_ERR_PARAM;
6547                 }
6548         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6549                         filter_type == RTE_MAC_HASH_MATCH)
6550                 vlan_num = 1;
6551
6552         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6553         if (mv_f == NULL) {
6554                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6555                 return I40E_ERR_NO_MEMORY;
6556         }
6557
6558         for (i = 0; i < vlan_num; i++) {
6559                 mv_f[i].filter_type = filter_type;
6560                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6561                                 ETH_ADDR_LEN);
6562         }
6563         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6564                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6565                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6566                 if (ret != I40E_SUCCESS)
6567                         goto DONE;
6568         }
6569
6570         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6571         if (ret != I40E_SUCCESS)
6572                 goto DONE;
6573
6574         /* Remove the mac addr into mac list */
6575         TAILQ_REMOVE(&vsi->mac_list, f, next);
6576         rte_free(f);
6577         vsi->mac_num--;
6578
6579         ret = I40E_SUCCESS;
6580 DONE:
6581         rte_free(mv_f);
6582         return ret;
6583 }
6584
6585 /* Configure hash enable flags for RSS */
6586 uint64_t
6587 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6588 {
6589         uint64_t hena = 0;
6590
6591         if (!flags)
6592                 return hena;
6593
6594         if (flags & ETH_RSS_FRAG_IPV4)
6595                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6596         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6597                 if (type == I40E_MAC_X722) {
6598                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6599                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6600                 } else
6601                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6602         }
6603         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6604                 if (type == I40E_MAC_X722) {
6605                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6606                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6607                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6608                 } else
6609                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6610         }
6611         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6612                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6613         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6614                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6615         if (flags & ETH_RSS_FRAG_IPV6)
6616                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6617         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6618                 if (type == I40E_MAC_X722) {
6619                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6620                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6621                 } else
6622                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6623         }
6624         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6625                 if (type == I40E_MAC_X722) {
6626                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6627                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6628                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6629                 } else
6630                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6631         }
6632         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6633                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6634         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6635                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6636         if (flags & ETH_RSS_L2_PAYLOAD)
6637                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6638
6639         return hena;
6640 }
6641
6642 /* Parse the hash enable flags */
6643 uint64_t
6644 i40e_parse_hena(uint64_t flags)
6645 {
6646         uint64_t rss_hf = 0;
6647
6648         if (!flags)
6649                 return rss_hf;
6650         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6651                 rss_hf |= ETH_RSS_FRAG_IPV4;
6652         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6653                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6654         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6655                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6656         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6657                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6658         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6659                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6660         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6661                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6662         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6663                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6664         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6665                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6666         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6667                 rss_hf |= ETH_RSS_FRAG_IPV6;
6668         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6669                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6670         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6671                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6672         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6673                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6674         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6675                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6676         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6677                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6678         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6679                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6680         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6681                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6682         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6683                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6684
6685         return rss_hf;
6686 }
6687
6688 /* Disable RSS */
6689 static void
6690 i40e_pf_disable_rss(struct i40e_pf *pf)
6691 {
6692         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6693         uint64_t hena;
6694
6695         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6696         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6697         if (hw->mac.type == I40E_MAC_X722)
6698                 hena &= ~I40E_RSS_HENA_ALL_X722;
6699         else
6700                 hena &= ~I40E_RSS_HENA_ALL;
6701         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6702         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6703         I40E_WRITE_FLUSH(hw);
6704 }
6705
6706 static int
6707 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6708 {
6709         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6710         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6711         int ret = 0;
6712
6713         if (!key || key_len == 0) {
6714                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6715                 return 0;
6716         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6717                 sizeof(uint32_t)) {
6718                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6719                 return -EINVAL;
6720         }
6721
6722         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6723                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6724                         (struct i40e_aqc_get_set_rss_key_data *)key;
6725
6726                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6727                 if (ret)
6728                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6729         } else {
6730                 uint32_t *hash_key = (uint32_t *)key;
6731                 uint16_t i;
6732
6733                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6734                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6735                 I40E_WRITE_FLUSH(hw);
6736         }
6737
6738         return ret;
6739 }
6740
6741 static int
6742 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6743 {
6744         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6745         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6746         int ret;
6747
6748         if (!key || !key_len)
6749                 return -EINVAL;
6750
6751         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6752                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6753                         (struct i40e_aqc_get_set_rss_key_data *)key);
6754                 if (ret) {
6755                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6756                         return ret;
6757                 }
6758         } else {
6759                 uint32_t *key_dw = (uint32_t *)key;
6760                 uint16_t i;
6761
6762                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6763                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6764         }
6765         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6766
6767         return 0;
6768 }
6769
6770 static int
6771 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6772 {
6773         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6774         uint64_t rss_hf;
6775         uint64_t hena;
6776         int ret;
6777
6778         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6779                                rss_conf->rss_key_len);
6780         if (ret)
6781                 return ret;
6782
6783         rss_hf = rss_conf->rss_hf;
6784         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6785         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6786         if (hw->mac.type == I40E_MAC_X722)
6787                 hena &= ~I40E_RSS_HENA_ALL_X722;
6788         else
6789                 hena &= ~I40E_RSS_HENA_ALL;
6790         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6791         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6792         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6793         I40E_WRITE_FLUSH(hw);
6794
6795         return 0;
6796 }
6797
6798 static int
6799 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6800                          struct rte_eth_rss_conf *rss_conf)
6801 {
6802         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6803         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6804         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6805         uint64_t hena;
6806
6807         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6808         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6809         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6810                  ? I40E_RSS_HENA_ALL_X722
6811                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6812                 if (rss_hf != 0) /* Enable RSS */
6813                         return -EINVAL;
6814                 return 0; /* Nothing to do */
6815         }
6816         /* RSS enabled */
6817         if (rss_hf == 0) /* Disable RSS */
6818                 return -EINVAL;
6819
6820         return i40e_hw_rss_hash_set(pf, rss_conf);
6821 }
6822
6823 static int
6824 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6825                            struct rte_eth_rss_conf *rss_conf)
6826 {
6827         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6829         uint64_t hena;
6830
6831         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6832                          &rss_conf->rss_key_len);
6833
6834         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6835         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6836         rss_conf->rss_hf = i40e_parse_hena(hena);
6837
6838         return 0;
6839 }
6840
6841 static int
6842 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6843 {
6844         switch (filter_type) {
6845         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6846                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6847                 break;
6848         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6849                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6850                 break;
6851         case RTE_TUNNEL_FILTER_IMAC_TENID:
6852                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6853                 break;
6854         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6855                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6856                 break;
6857         case ETH_TUNNEL_FILTER_IMAC:
6858                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6859                 break;
6860         case ETH_TUNNEL_FILTER_OIP:
6861                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6862                 break;
6863         case ETH_TUNNEL_FILTER_IIP:
6864                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6865                 break;
6866         default:
6867                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6868                 return -EINVAL;
6869         }
6870
6871         return 0;
6872 }
6873
6874 /* Convert tunnel filter structure */
6875 static int
6876 i40e_tunnel_filter_convert(
6877         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6878         struct i40e_tunnel_filter *tunnel_filter)
6879 {
6880         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6881                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6882         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6883                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6884         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6885         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6886              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6887             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6888                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6889         else
6890                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6891         tunnel_filter->input.flags = cld_filter->element.flags;
6892         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6893         tunnel_filter->queue = cld_filter->element.queue_number;
6894         rte_memcpy(tunnel_filter->input.general_fields,
6895                    cld_filter->general_fields,
6896                    sizeof(cld_filter->general_fields));
6897
6898         return 0;
6899 }
6900
6901 /* Check if there exists the tunnel filter */
6902 struct i40e_tunnel_filter *
6903 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6904                              const struct i40e_tunnel_filter_input *input)
6905 {
6906         int ret;
6907
6908         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6909         if (ret < 0)
6910                 return NULL;
6911
6912         return tunnel_rule->hash_map[ret];
6913 }
6914
6915 /* Add a tunnel filter into the SW list */
6916 static int
6917 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6918                              struct i40e_tunnel_filter *tunnel_filter)
6919 {
6920         struct i40e_tunnel_rule *rule = &pf->tunnel;
6921         int ret;
6922
6923         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6924         if (ret < 0) {
6925                 PMD_DRV_LOG(ERR,
6926                             "Failed to insert tunnel filter to hash table %d!",
6927                             ret);
6928                 return ret;
6929         }
6930         rule->hash_map[ret] = tunnel_filter;
6931
6932         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6933
6934         return 0;
6935 }
6936
6937 /* Delete a tunnel filter from the SW list */
6938 int
6939 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6940                           struct i40e_tunnel_filter_input *input)
6941 {
6942         struct i40e_tunnel_rule *rule = &pf->tunnel;
6943         struct i40e_tunnel_filter *tunnel_filter;
6944         int ret;
6945
6946         ret = rte_hash_del_key(rule->hash_table, input);
6947         if (ret < 0) {
6948                 PMD_DRV_LOG(ERR,
6949                             "Failed to delete tunnel filter to hash table %d!",
6950                             ret);
6951                 return ret;
6952         }
6953         tunnel_filter = rule->hash_map[ret];
6954         rule->hash_map[ret] = NULL;
6955
6956         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6957         rte_free(tunnel_filter);
6958
6959         return 0;
6960 }
6961
6962 int
6963 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6964                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6965                         uint8_t add)
6966 {
6967         uint16_t ip_type;
6968         uint32_t ipv4_addr;
6969         uint8_t i, tun_type = 0;
6970         /* internal varialbe to convert ipv6 byte order */
6971         uint32_t convert_ipv6[4];
6972         int val, ret = 0;
6973         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6974         struct i40e_vsi *vsi = pf->main_vsi;
6975         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6976         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6977         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6978         struct i40e_tunnel_filter *tunnel, *node;
6979         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6980
6981         cld_filter = rte_zmalloc("tunnel_filter",
6982                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6983         0);
6984
6985         if (NULL == cld_filter) {
6986                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6987                 return -ENOMEM;
6988         }
6989         pfilter = cld_filter;
6990
6991         ether_addr_copy(&tunnel_filter->outer_mac,
6992                         (struct ether_addr *)&pfilter->element.outer_mac);
6993         ether_addr_copy(&tunnel_filter->inner_mac,
6994                         (struct ether_addr *)&pfilter->element.inner_mac);
6995
6996         pfilter->element.inner_vlan =
6997                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6998         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6999                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7000                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7001                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7002                                 &rte_cpu_to_le_32(ipv4_addr),
7003                                 sizeof(pfilter->element.ipaddr.v4.data));
7004         } else {
7005                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7006                 for (i = 0; i < 4; i++) {
7007                         convert_ipv6[i] =
7008                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7009                 }
7010                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7011                            &convert_ipv6,
7012                            sizeof(pfilter->element.ipaddr.v6.data));
7013         }
7014
7015         /* check tunneled type */
7016         switch (tunnel_filter->tunnel_type) {
7017         case RTE_TUNNEL_TYPE_VXLAN:
7018                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7019                 break;
7020         case RTE_TUNNEL_TYPE_NVGRE:
7021                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7022                 break;
7023         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7024                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7025                 break;
7026         default:
7027                 /* Other tunnel types is not supported. */
7028                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7029                 rte_free(cld_filter);
7030                 return -EINVAL;
7031         }
7032
7033         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7034                                        &pfilter->element.flags);
7035         if (val < 0) {
7036                 rte_free(cld_filter);
7037                 return -EINVAL;
7038         }
7039
7040         pfilter->element.flags |= rte_cpu_to_le_16(
7041                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7042                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7043         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7044         pfilter->element.queue_number =
7045                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7046
7047         /* Check if there is the filter in SW list */
7048         memset(&check_filter, 0, sizeof(check_filter));
7049         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7050         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7051         if (add && node) {
7052                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7053                 return -EINVAL;
7054         }
7055
7056         if (!add && !node) {
7057                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7058                 return -EINVAL;
7059         }
7060
7061         if (add) {
7062                 ret = i40e_aq_add_cloud_filters(hw,
7063                                         vsi->seid, &cld_filter->element, 1);
7064                 if (ret < 0) {
7065                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7066                         return -ENOTSUP;
7067                 }
7068                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7069                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7070                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7071         } else {
7072                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7073                                                    &cld_filter->element, 1);
7074                 if (ret < 0) {
7075                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7076                         return -ENOTSUP;
7077                 }
7078                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7079         }
7080
7081         rte_free(cld_filter);
7082         return ret;
7083 }
7084
7085 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7086 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7087 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7088 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7089 #define I40E_TR_GRE_KEY_MASK                    0x400
7090 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7091 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7092
7093 static enum
7094 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7095 {
7096         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7097         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7098         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7099         enum i40e_status_code status = I40E_SUCCESS;
7100
7101         memset(&filter_replace, 0,
7102                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7103         memset(&filter_replace_buf, 0,
7104                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7105
7106         /* create L1 filter */
7107         filter_replace.old_filter_type =
7108                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7109         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7110         filter_replace.tr_bit = 0;
7111
7112         /* Prepare the buffer, 3 entries */
7113         filter_replace_buf.data[0] =
7114                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7115         filter_replace_buf.data[0] |=
7116                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7117         filter_replace_buf.data[2] = 0xFF;
7118         filter_replace_buf.data[3] = 0xFF;
7119         filter_replace_buf.data[4] =
7120                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7121         filter_replace_buf.data[4] |=
7122                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7123         filter_replace_buf.data[7] = 0xF0;
7124         filter_replace_buf.data[8]
7125                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7126         filter_replace_buf.data[8] |=
7127                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7128         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7129                 I40E_TR_GENEVE_KEY_MASK |
7130                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7131         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7132                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7133                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7134
7135         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7136                                                &filter_replace_buf);
7137         return status;
7138 }
7139
7140 static enum
7141 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7142 {
7143         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7144         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7145         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7146         enum i40e_status_code status = I40E_SUCCESS;
7147
7148         /* For MPLSoUDP */
7149         memset(&filter_replace, 0,
7150                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7151         memset(&filter_replace_buf, 0,
7152                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7153         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7154                 I40E_AQC_MIRROR_CLOUD_FILTER;
7155         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7156         filter_replace.new_filter_type =
7157                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7158         /* Prepare the buffer, 2 entries */
7159         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7160         filter_replace_buf.data[0] |=
7161                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7162         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7163         filter_replace_buf.data[4] |=
7164                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7165         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7166                                                &filter_replace_buf);
7167         if (status < 0)
7168                 return status;
7169
7170         /* For MPLSoGRE */
7171         memset(&filter_replace, 0,
7172                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7173         memset(&filter_replace_buf, 0,
7174                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7175
7176         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7177                 I40E_AQC_MIRROR_CLOUD_FILTER;
7178         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7179         filter_replace.new_filter_type =
7180                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7181         /* Prepare the buffer, 2 entries */
7182         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7183         filter_replace_buf.data[0] |=
7184                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7185         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7186         filter_replace_buf.data[4] |=
7187                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7188
7189         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7190                                                &filter_replace_buf);
7191         return status;
7192 }
7193
7194 int
7195 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7196                       struct i40e_tunnel_filter_conf *tunnel_filter,
7197                       uint8_t add)
7198 {
7199         uint16_t ip_type;
7200         uint32_t ipv4_addr;
7201         uint8_t i, tun_type = 0;
7202         /* internal variable to convert ipv6 byte order */
7203         uint32_t convert_ipv6[4];
7204         int val, ret = 0;
7205         struct i40e_pf_vf *vf = NULL;
7206         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7207         struct i40e_vsi *vsi;
7208         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7209         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7210         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7211         struct i40e_tunnel_filter *tunnel, *node;
7212         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7213         uint32_t teid_le;
7214         bool big_buffer = 0;
7215
7216         cld_filter = rte_zmalloc("tunnel_filter",
7217                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7218                          0);
7219
7220         if (cld_filter == NULL) {
7221                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7222                 return -ENOMEM;
7223         }
7224         pfilter = cld_filter;
7225
7226         ether_addr_copy(&tunnel_filter->outer_mac,
7227                         (struct ether_addr *)&pfilter->element.outer_mac);
7228         ether_addr_copy(&tunnel_filter->inner_mac,
7229                         (struct ether_addr *)&pfilter->element.inner_mac);
7230
7231         pfilter->element.inner_vlan =
7232                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7233         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7234                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7235                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7236                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7237                                 &rte_cpu_to_le_32(ipv4_addr),
7238                                 sizeof(pfilter->element.ipaddr.v4.data));
7239         } else {
7240                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7241                 for (i = 0; i < 4; i++) {
7242                         convert_ipv6[i] =
7243                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7244                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7245                 }
7246                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7247                            &convert_ipv6,
7248                            sizeof(pfilter->element.ipaddr.v6.data));
7249         }
7250
7251         /* check tunneled type */
7252         switch (tunnel_filter->tunnel_type) {
7253         case I40E_TUNNEL_TYPE_VXLAN:
7254                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7255                 break;
7256         case I40E_TUNNEL_TYPE_NVGRE:
7257                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7258                 break;
7259         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7260                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7261                 break;
7262         case I40E_TUNNEL_TYPE_MPLSoUDP:
7263                 if (!pf->mpls_replace_flag) {
7264                         i40e_replace_mpls_l1_filter(pf);
7265                         i40e_replace_mpls_cloud_filter(pf);
7266                         pf->mpls_replace_flag = 1;
7267                 }
7268                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7269                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7270                         teid_le >> 4;
7271                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7272                         (teid_le & 0xF) << 12;
7273                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7274                         0x40;
7275                 big_buffer = 1;
7276                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7277                 break;
7278         case I40E_TUNNEL_TYPE_MPLSoGRE:
7279                 if (!pf->mpls_replace_flag) {
7280                         i40e_replace_mpls_l1_filter(pf);
7281                         i40e_replace_mpls_cloud_filter(pf);
7282                         pf->mpls_replace_flag = 1;
7283                 }
7284                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7285                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7286                         teid_le >> 4;
7287                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7288                         (teid_le & 0xF) << 12;
7289                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7290                         0x0;
7291                 big_buffer = 1;
7292                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7293                 break;
7294         case I40E_TUNNEL_TYPE_QINQ:
7295                 if (!pf->qinq_replace_flag) {
7296                         ret = i40e_cloud_filter_qinq_create(pf);
7297                         if (ret < 0)
7298                                 PMD_DRV_LOG(DEBUG,
7299                                             "QinQ tunnel filter already created.");
7300                         pf->qinq_replace_flag = 1;
7301                 }
7302                 /*      Add in the General fields the values of
7303                  *      the Outer and Inner VLAN
7304                  *      Big Buffer should be set, see changes in
7305                  *      i40e_aq_add_cloud_filters
7306                  */
7307                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7308                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7309                 big_buffer = 1;
7310                 break;
7311         default:
7312                 /* Other tunnel types is not supported. */
7313                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7314                 rte_free(cld_filter);
7315                 return -EINVAL;
7316         }
7317
7318         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7319                 pfilter->element.flags =
7320                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7321         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7322                 pfilter->element.flags =
7323                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7324         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7325                 pfilter->element.flags |=
7326                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7327         else {
7328                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7329                                                 &pfilter->element.flags);
7330                 if (val < 0) {
7331                         rte_free(cld_filter);
7332                         return -EINVAL;
7333                 }
7334         }
7335
7336         pfilter->element.flags |= rte_cpu_to_le_16(
7337                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7338                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7339         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7340         pfilter->element.queue_number =
7341                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7342
7343         if (!tunnel_filter->is_to_vf)
7344                 vsi = pf->main_vsi;
7345         else {
7346                 if (tunnel_filter->vf_id >= pf->vf_num) {
7347                         PMD_DRV_LOG(ERR, "Invalid argument.");
7348                         return -EINVAL;
7349                 }
7350                 vf = &pf->vfs[tunnel_filter->vf_id];
7351                 vsi = vf->vsi;
7352         }
7353
7354         /* Check if there is the filter in SW list */
7355         memset(&check_filter, 0, sizeof(check_filter));
7356         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7357         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7358         check_filter.vf_id = tunnel_filter->vf_id;
7359         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7360         if (add && node) {
7361                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7362                 return -EINVAL;
7363         }
7364
7365         if (!add && !node) {
7366                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7367                 return -EINVAL;
7368         }
7369
7370         if (add) {
7371                 if (big_buffer)
7372                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7373                                                    vsi->seid, cld_filter, 1);
7374                 else
7375                         ret = i40e_aq_add_cloud_filters(hw,
7376                                         vsi->seid, &cld_filter->element, 1);
7377                 if (ret < 0) {
7378                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7379                         return -ENOTSUP;
7380                 }
7381                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7382                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7383                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7384         } else {
7385                 if (big_buffer)
7386                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7387                                 hw, vsi->seid, cld_filter, 1);
7388                 else
7389                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7390                                                    &cld_filter->element, 1);
7391                 if (ret < 0) {
7392                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7393                         return -ENOTSUP;
7394                 }
7395                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7396         }
7397
7398         rte_free(cld_filter);
7399         return ret;
7400 }
7401
7402 static int
7403 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7404 {
7405         uint8_t i;
7406
7407         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7408                 if (pf->vxlan_ports[i] == port)
7409                         return i;
7410         }
7411
7412         return -1;
7413 }
7414
7415 static int
7416 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7417 {
7418         int  idx, ret;
7419         uint8_t filter_idx;
7420         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7421
7422         idx = i40e_get_vxlan_port_idx(pf, port);
7423
7424         /* Check if port already exists */
7425         if (idx >= 0) {
7426                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7427                 return -EINVAL;
7428         }
7429
7430         /* Now check if there is space to add the new port */
7431         idx = i40e_get_vxlan_port_idx(pf, 0);
7432         if (idx < 0) {
7433                 PMD_DRV_LOG(ERR,
7434                         "Maximum number of UDP ports reached, not adding port %d",
7435                         port);
7436                 return -ENOSPC;
7437         }
7438
7439         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7440                                         &filter_idx, NULL);
7441         if (ret < 0) {
7442                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7443                 return -1;
7444         }
7445
7446         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7447                          port,  filter_idx);
7448
7449         /* New port: add it and mark its index in the bitmap */
7450         pf->vxlan_ports[idx] = port;
7451         pf->vxlan_bitmap |= (1 << idx);
7452
7453         if (!(pf->flags & I40E_FLAG_VXLAN))
7454                 pf->flags |= I40E_FLAG_VXLAN;
7455
7456         return 0;
7457 }
7458
7459 static int
7460 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7461 {
7462         int idx;
7463         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7464
7465         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7466                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7467                 return -EINVAL;
7468         }
7469
7470         idx = i40e_get_vxlan_port_idx(pf, port);
7471
7472         if (idx < 0) {
7473                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7474                 return -EINVAL;
7475         }
7476
7477         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7478                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7479                 return -1;
7480         }
7481
7482         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7483                         port, idx);
7484
7485         pf->vxlan_ports[idx] = 0;
7486         pf->vxlan_bitmap &= ~(1 << idx);
7487
7488         if (!pf->vxlan_bitmap)
7489                 pf->flags &= ~I40E_FLAG_VXLAN;
7490
7491         return 0;
7492 }
7493
7494 /* Add UDP tunneling port */
7495 static int
7496 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7497                              struct rte_eth_udp_tunnel *udp_tunnel)
7498 {
7499         int ret = 0;
7500         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7501
7502         if (udp_tunnel == NULL)
7503                 return -EINVAL;
7504
7505         switch (udp_tunnel->prot_type) {
7506         case RTE_TUNNEL_TYPE_VXLAN:
7507                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7508                 break;
7509
7510         case RTE_TUNNEL_TYPE_GENEVE:
7511         case RTE_TUNNEL_TYPE_TEREDO:
7512                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7513                 ret = -1;
7514                 break;
7515
7516         default:
7517                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7518                 ret = -1;
7519                 break;
7520         }
7521
7522         return ret;
7523 }
7524
7525 /* Remove UDP tunneling port */
7526 static int
7527 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7528                              struct rte_eth_udp_tunnel *udp_tunnel)
7529 {
7530         int ret = 0;
7531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7532
7533         if (udp_tunnel == NULL)
7534                 return -EINVAL;
7535
7536         switch (udp_tunnel->prot_type) {
7537         case RTE_TUNNEL_TYPE_VXLAN:
7538                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7539                 break;
7540         case RTE_TUNNEL_TYPE_GENEVE:
7541         case RTE_TUNNEL_TYPE_TEREDO:
7542                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7543                 ret = -1;
7544                 break;
7545         default:
7546                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7547                 ret = -1;
7548                 break;
7549         }
7550
7551         return ret;
7552 }
7553
7554 /* Calculate the maximum number of contiguous PF queues that are configured */
7555 static int
7556 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7557 {
7558         struct rte_eth_dev_data *data = pf->dev_data;
7559         int i, num;
7560         struct i40e_rx_queue *rxq;
7561
7562         num = 0;
7563         for (i = 0; i < pf->lan_nb_qps; i++) {
7564                 rxq = data->rx_queues[i];
7565                 if (rxq && rxq->q_set)
7566                         num++;
7567                 else
7568                         break;
7569         }
7570
7571         return num;
7572 }
7573
7574 /* Configure RSS */
7575 static int
7576 i40e_pf_config_rss(struct i40e_pf *pf)
7577 {
7578         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7579         struct rte_eth_rss_conf rss_conf;
7580         uint32_t i, lut = 0;
7581         uint16_t j, num;
7582
7583         /*
7584          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7585          * It's necessary to calculate the actual PF queues that are configured.
7586          */
7587         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7588                 num = i40e_pf_calc_configured_queues_num(pf);
7589         else
7590                 num = pf->dev_data->nb_rx_queues;
7591
7592         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7593         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7594                         num);
7595
7596         if (num == 0) {
7597                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7598                 return -ENOTSUP;
7599         }
7600
7601         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7602                 if (j == num)
7603                         j = 0;
7604                 lut = (lut << 8) | (j & ((0x1 <<
7605                         hw->func_caps.rss_table_entry_width) - 1));
7606                 if ((i & 3) == 3)
7607                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7608         }
7609
7610         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7611         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7612                 i40e_pf_disable_rss(pf);
7613                 return 0;
7614         }
7615         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7616                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7617                 /* Random default keys */
7618                 static uint32_t rss_key_default[] = {0x6b793944,
7619                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7620                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7621                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7622
7623                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7624                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7625                                                         sizeof(uint32_t);
7626         }
7627
7628         return i40e_hw_rss_hash_set(pf, &rss_conf);
7629 }
7630
7631 static int
7632 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7633                                struct rte_eth_tunnel_filter_conf *filter)
7634 {
7635         if (pf == NULL || filter == NULL) {
7636                 PMD_DRV_LOG(ERR, "Invalid parameter");
7637                 return -EINVAL;
7638         }
7639
7640         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7641                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7642                 return -EINVAL;
7643         }
7644
7645         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7646                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7647                 return -EINVAL;
7648         }
7649
7650         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7651                 (is_zero_ether_addr(&filter->outer_mac))) {
7652                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7653                 return -EINVAL;
7654         }
7655
7656         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7657                 (is_zero_ether_addr(&filter->inner_mac))) {
7658                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7659                 return -EINVAL;
7660         }
7661
7662         return 0;
7663 }
7664
7665 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7666 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7667 static int
7668 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7669 {
7670         uint32_t val, reg;
7671         int ret = -EINVAL;
7672
7673         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7674         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7675
7676         if (len == 3) {
7677                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7678         } else if (len == 4) {
7679                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7680         } else {
7681                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7682                 return ret;
7683         }
7684
7685         if (reg != val) {
7686                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7687                                                    reg, NULL);
7688                 if (ret != 0)
7689                         return ret;
7690         } else {
7691                 ret = 0;
7692         }
7693         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7694                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7695
7696         return ret;
7697 }
7698
7699 static int
7700 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7701 {
7702         int ret = -EINVAL;
7703
7704         if (!hw || !cfg)
7705                 return -EINVAL;
7706
7707         switch (cfg->cfg_type) {
7708         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7709                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7710                 break;
7711         default:
7712                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7713                 break;
7714         }
7715
7716         return ret;
7717 }
7718
7719 static int
7720 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7721                                enum rte_filter_op filter_op,
7722                                void *arg)
7723 {
7724         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7725         int ret = I40E_ERR_PARAM;
7726
7727         switch (filter_op) {
7728         case RTE_ETH_FILTER_SET:
7729                 ret = i40e_dev_global_config_set(hw,
7730                         (struct rte_eth_global_cfg *)arg);
7731                 break;
7732         default:
7733                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7734                 break;
7735         }
7736
7737         return ret;
7738 }
7739
7740 static int
7741 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7742                           enum rte_filter_op filter_op,
7743                           void *arg)
7744 {
7745         struct rte_eth_tunnel_filter_conf *filter;
7746         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7747         int ret = I40E_SUCCESS;
7748
7749         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7750
7751         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7752                 return I40E_ERR_PARAM;
7753
7754         switch (filter_op) {
7755         case RTE_ETH_FILTER_NOP:
7756                 if (!(pf->flags & I40E_FLAG_VXLAN))
7757                         ret = I40E_NOT_SUPPORTED;
7758                 break;
7759         case RTE_ETH_FILTER_ADD:
7760                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7761                 break;
7762         case RTE_ETH_FILTER_DELETE:
7763                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7764                 break;
7765         default:
7766                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7767                 ret = I40E_ERR_PARAM;
7768                 break;
7769         }
7770
7771         return ret;
7772 }
7773
7774 static int
7775 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7776 {
7777         int ret = 0;
7778         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7779
7780         /* RSS setup */
7781         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7782                 ret = i40e_pf_config_rss(pf);
7783         else
7784                 i40e_pf_disable_rss(pf);
7785
7786         return ret;
7787 }
7788
7789 /* Get the symmetric hash enable configurations per port */
7790 static void
7791 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7792 {
7793         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7794
7795         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7796 }
7797
7798 /* Set the symmetric hash enable configurations per port */
7799 static void
7800 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7801 {
7802         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7803
7804         if (enable > 0) {
7805                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7806                         PMD_DRV_LOG(INFO,
7807                                 "Symmetric hash has already been enabled");
7808                         return;
7809                 }
7810                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7811         } else {
7812                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7813                         PMD_DRV_LOG(INFO,
7814                                 "Symmetric hash has already been disabled");
7815                         return;
7816                 }
7817                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7818         }
7819         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7820         I40E_WRITE_FLUSH(hw);
7821 }
7822
7823 /*
7824  * Get global configurations of hash function type and symmetric hash enable
7825  * per flow type (pctype). Note that global configuration means it affects all
7826  * the ports on the same NIC.
7827  */
7828 static int
7829 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7830                                    struct rte_eth_hash_global_conf *g_cfg)
7831 {
7832         uint32_t reg, mask = I40E_FLOW_TYPES;
7833         uint16_t i;
7834         enum i40e_filter_pctype pctype;
7835
7836         memset(g_cfg, 0, sizeof(*g_cfg));
7837         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7838         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7839                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7840         else
7841                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7842         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7843                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7844
7845         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7846                 if (!(mask & (1UL << i)))
7847                         continue;
7848                 mask &= ~(1UL << i);
7849                 /* Bit set indicats the coresponding flow type is supported */
7850                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7851                 /* if flowtype is invalid, continue */
7852                 if (!I40E_VALID_FLOW(i))
7853                         continue;
7854                 pctype = i40e_flowtype_to_pctype(i);
7855                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7856                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7857                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7858         }
7859
7860         return 0;
7861 }
7862
7863 static int
7864 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7865 {
7866         uint32_t i;
7867         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7868
7869         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7870                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7871                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7872                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7873                                                 g_cfg->hash_func);
7874                 return -EINVAL;
7875         }
7876
7877         /*
7878          * As i40e supports less than 32 flow types, only first 32 bits need to
7879          * be checked.
7880          */
7881         mask0 = g_cfg->valid_bit_mask[0];
7882         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7883                 if (i == 0) {
7884                         /* Check if any unsupported flow type configured */
7885                         if ((mask0 | i40e_mask) ^ i40e_mask)
7886                                 goto mask_err;
7887                 } else {
7888                         if (g_cfg->valid_bit_mask[i])
7889                                 goto mask_err;
7890                 }
7891         }
7892
7893         return 0;
7894
7895 mask_err:
7896         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7897
7898         return -EINVAL;
7899 }
7900
7901 /*
7902  * Set global configurations of hash function type and symmetric hash enable
7903  * per flow type (pctype). Note any modifying global configuration will affect
7904  * all the ports on the same NIC.
7905  */
7906 static int
7907 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7908                                    struct rte_eth_hash_global_conf *g_cfg)
7909 {
7910         int ret;
7911         uint16_t i;
7912         uint32_t reg;
7913         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7914         enum i40e_filter_pctype pctype;
7915
7916         /* Check the input parameters */
7917         ret = i40e_hash_global_config_check(g_cfg);
7918         if (ret < 0)
7919                 return ret;
7920
7921         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7922                 if (!(mask0 & (1UL << i)))
7923                         continue;
7924                 mask0 &= ~(1UL << i);
7925                 /* if flowtype is invalid, continue */
7926                 if (!I40E_VALID_FLOW(i))
7927                         continue;
7928                 pctype = i40e_flowtype_to_pctype(i);
7929                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7930                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7931                 if (hw->mac.type == I40E_MAC_X722) {
7932                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7933                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7934                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7935                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7936                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7937                                   reg);
7938                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7939                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7940                                   reg);
7941                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7942                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7943                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7944                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7945                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7946                                   reg);
7947                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7948                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7949                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7950                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7951                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7952                                   reg);
7953                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7954                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7955                                   reg);
7956                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7957                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7958                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7959                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7960                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7961                                   reg);
7962                         } else {
7963                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7964                                   reg);
7965                         }
7966                 } else {
7967                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7968                 }
7969         }
7970
7971         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7972         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7973                 /* Toeplitz */
7974                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7975                         PMD_DRV_LOG(DEBUG,
7976                                 "Hash function already set to Toeplitz");
7977                         goto out;
7978                 }
7979                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7980         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7981                 /* Simple XOR */
7982                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7983                         PMD_DRV_LOG(DEBUG,
7984                                 "Hash function already set to Simple XOR");
7985                         goto out;
7986                 }
7987                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7988         } else
7989                 /* Use the default, and keep it as it is */
7990                 goto out;
7991
7992         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7993
7994 out:
7995         I40E_WRITE_FLUSH(hw);
7996
7997         return 0;
7998 }
7999
8000 /**
8001  * Valid input sets for hash and flow director filters per PCTYPE
8002  */
8003 static uint64_t
8004 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8005                 enum rte_filter_type filter)
8006 {
8007         uint64_t valid;
8008
8009         static const uint64_t valid_hash_inset_table[] = {
8010                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8011                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8012                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8013                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8014                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8015                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8016                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8017                         I40E_INSET_FLEX_PAYLOAD,
8018                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8019                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8020                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8021                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8022                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8023                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8024                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8025                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8026                         I40E_INSET_FLEX_PAYLOAD,
8027                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8028                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8029                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8031                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8032                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8033                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8034                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8035                         I40E_INSET_FLEX_PAYLOAD,
8036                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8037                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8038                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8039                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8040                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8041                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8042                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8043                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8044                         I40E_INSET_FLEX_PAYLOAD,
8045                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8046                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8047                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8048                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8049                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8050                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8051                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8052                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8053                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8054                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8055                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8056                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8057                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8058                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8059                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8060                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8061                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8062                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8063                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8064                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8065                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8066                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8067                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8068                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8069                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8070                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8071                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8072                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8076                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8077                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8078                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8079                         I40E_INSET_FLEX_PAYLOAD,
8080                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8081                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8082                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8083                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8084                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8085                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8086                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8087                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8088                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8089                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8090                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8091                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8092                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8093                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8094                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8095                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8096                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8100                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8101                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8102                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8103                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8104                         I40E_INSET_FLEX_PAYLOAD,
8105                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8106                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8107                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8108                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8109                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8110                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8111                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8112                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8113                         I40E_INSET_FLEX_PAYLOAD,
8114                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8118                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8119                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8120                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8121                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8122                         I40E_INSET_FLEX_PAYLOAD,
8123                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8124                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8125                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8126                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8127                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8128                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8129                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8130                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8131                         I40E_INSET_FLEX_PAYLOAD,
8132                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8133                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8134                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8135                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8136                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8137                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8138                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8139                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8140                         I40E_INSET_FLEX_PAYLOAD,
8141                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8142                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8143                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8144                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8145                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8146                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8147                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8148                         I40E_INSET_FLEX_PAYLOAD,
8149                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8150                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8151                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8152                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8153                         I40E_INSET_FLEX_PAYLOAD,
8154         };
8155
8156         /**
8157          * Flow director supports only fields defined in
8158          * union rte_eth_fdir_flow.
8159          */
8160         static const uint64_t valid_fdir_inset_table[] = {
8161                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8162                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8163                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8164                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8165                 I40E_INSET_IPV4_TTL,
8166                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8167                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8168                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8169                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8170                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8171                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8172                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8173                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8174                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8175                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8176                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8177                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8178                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8179                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8180                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8181                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8182                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8183                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8184                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8185                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8186                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8187                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8188                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8189                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8190                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8191                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8192                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8193                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8194                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8195                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8196                 I40E_INSET_SCTP_VT,
8197                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8198                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8200                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8201                 I40E_INSET_IPV4_TTL,
8202                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8203                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8204                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8205                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8206                 I40E_INSET_IPV6_HOP_LIMIT,
8207                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8208                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8209                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8210                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8211                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8212                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8213                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8214                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8215                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8216                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8217                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8218                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8219                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8220                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8221                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8222                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8223                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8224                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8225                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8226                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8227                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8228                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8229                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8230                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8231                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8232                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8233                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8234                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8235                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8236                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8237                 I40E_INSET_SCTP_VT,
8238                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8239                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8240                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8241                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8242                 I40E_INSET_IPV6_HOP_LIMIT,
8243                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8244                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8245                 I40E_INSET_LAST_ETHER_TYPE,
8246         };
8247
8248         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8249                 return 0;
8250         if (filter == RTE_ETH_FILTER_HASH)
8251                 valid = valid_hash_inset_table[pctype];
8252         else
8253                 valid = valid_fdir_inset_table[pctype];
8254
8255         return valid;
8256 }
8257
8258 /**
8259  * Validate if the input set is allowed for a specific PCTYPE
8260  */
8261 int
8262 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8263                 enum rte_filter_type filter, uint64_t inset)
8264 {
8265         uint64_t valid;
8266
8267         valid = i40e_get_valid_input_set(pctype, filter);
8268         if (inset & (~valid))
8269                 return -EINVAL;
8270
8271         return 0;
8272 }
8273
8274 /* default input set fields combination per pctype */
8275 uint64_t
8276 i40e_get_default_input_set(uint16_t pctype)
8277 {
8278         static const uint64_t default_inset_table[] = {
8279                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8280                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8281                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8282                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8283                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8284                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8285                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8286                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8287                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8288                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8290                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8291                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8292                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8293                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8294                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8295                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8296                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8297                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8298                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8299                         I40E_INSET_SCTP_VT,
8300                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8301                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8302                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8303                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8304                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8305                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8306                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8307                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8308                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8309                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8310                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8311                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8312                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8313                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8314                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8315                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8316                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8317                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8318                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8319                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8320                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8321                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8322                         I40E_INSET_SCTP_VT,
8323                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8324                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8325                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8326                         I40E_INSET_LAST_ETHER_TYPE,
8327         };
8328
8329         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8330                 return 0;
8331
8332         return default_inset_table[pctype];
8333 }
8334
8335 /**
8336  * Parse the input set from index to logical bit masks
8337  */
8338 static int
8339 i40e_parse_input_set(uint64_t *inset,
8340                      enum i40e_filter_pctype pctype,
8341                      enum rte_eth_input_set_field *field,
8342                      uint16_t size)
8343 {
8344         uint16_t i, j;
8345         int ret = -EINVAL;
8346
8347         static const struct {
8348                 enum rte_eth_input_set_field field;
8349                 uint64_t inset;
8350         } inset_convert_table[] = {
8351                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8352                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8353                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8354                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8355                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8356                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8357                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8358                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8359                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8360                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8361                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8362                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8363                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8364                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8365                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8366                         I40E_INSET_IPV6_NEXT_HDR},
8367                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8368                         I40E_INSET_IPV6_HOP_LIMIT},
8369                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8370                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8371                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8372                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8373                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8374                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8375                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8376                         I40E_INSET_SCTP_VT},
8377                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8378                         I40E_INSET_TUNNEL_DMAC},
8379                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8380                         I40E_INSET_VLAN_TUNNEL},
8381                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8382                         I40E_INSET_TUNNEL_ID},
8383                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8384                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8385                         I40E_INSET_FLEX_PAYLOAD_W1},
8386                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8387                         I40E_INSET_FLEX_PAYLOAD_W2},
8388                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8389                         I40E_INSET_FLEX_PAYLOAD_W3},
8390                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8391                         I40E_INSET_FLEX_PAYLOAD_W4},
8392                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8393                         I40E_INSET_FLEX_PAYLOAD_W5},
8394                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8395                         I40E_INSET_FLEX_PAYLOAD_W6},
8396                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8397                         I40E_INSET_FLEX_PAYLOAD_W7},
8398                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8399                         I40E_INSET_FLEX_PAYLOAD_W8},
8400         };
8401
8402         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8403                 return ret;
8404
8405         /* Only one item allowed for default or all */
8406         if (size == 1) {
8407                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8408                         *inset = i40e_get_default_input_set(pctype);
8409                         return 0;
8410                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8411                         *inset = I40E_INSET_NONE;
8412                         return 0;
8413                 }
8414         }
8415
8416         for (i = 0, *inset = 0; i < size; i++) {
8417                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8418                         if (field[i] == inset_convert_table[j].field) {
8419                                 *inset |= inset_convert_table[j].inset;
8420                                 break;
8421                         }
8422                 }
8423
8424                 /* It contains unsupported input set, return immediately */
8425                 if (j == RTE_DIM(inset_convert_table))
8426                         return ret;
8427         }
8428
8429         return 0;
8430 }
8431
8432 /**
8433  * Translate the input set from bit masks to register aware bit masks
8434  * and vice versa
8435  */
8436 uint64_t
8437 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8438 {
8439         uint64_t val = 0;
8440         uint16_t i;
8441
8442         struct inset_map {
8443                 uint64_t inset;
8444                 uint64_t inset_reg;
8445         };
8446
8447         static const struct inset_map inset_map_common[] = {
8448                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8449                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8450                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8451                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8452                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8453                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8454                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8455                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8456                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8457                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8458                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8459                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8460                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8461                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8462                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8463                 {I40E_INSET_TUNNEL_DMAC,
8464                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8465                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8466                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8467                 {I40E_INSET_TUNNEL_SRC_PORT,
8468                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8469                 {I40E_INSET_TUNNEL_DST_PORT,
8470                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8471                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8472                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8473                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8474                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8475                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8476                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8477                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8478                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8479                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8480         };
8481
8482     /* some different registers map in x722*/
8483         static const struct inset_map inset_map_diff_x722[] = {
8484                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8485                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8486                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8487                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8488         };
8489
8490         static const struct inset_map inset_map_diff_not_x722[] = {
8491                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8492                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8493                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8494                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8495         };
8496
8497         if (input == 0)
8498                 return val;
8499
8500         /* Translate input set to register aware inset */
8501         if (type == I40E_MAC_X722) {
8502                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8503                         if (input & inset_map_diff_x722[i].inset)
8504                                 val |= inset_map_diff_x722[i].inset_reg;
8505                 }
8506         } else {
8507                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8508                         if (input & inset_map_diff_not_x722[i].inset)
8509                                 val |= inset_map_diff_not_x722[i].inset_reg;
8510                 }
8511         }
8512
8513         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8514                 if (input & inset_map_common[i].inset)
8515                         val |= inset_map_common[i].inset_reg;
8516         }
8517
8518         return val;
8519 }
8520
8521 int
8522 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8523 {
8524         uint8_t i, idx = 0;
8525         uint64_t inset_need_mask = inset;
8526
8527         static const struct {
8528                 uint64_t inset;
8529                 uint32_t mask;
8530         } inset_mask_map[] = {
8531                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8532                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8533                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8534                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8535                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8536                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8537                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8538                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8539         };
8540
8541         if (!inset || !mask || !nb_elem)
8542                 return 0;
8543
8544         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8545                 /* Clear the inset bit, if no MASK is required,
8546                  * for example proto + ttl
8547                  */
8548                 if ((inset & inset_mask_map[i].inset) ==
8549                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8550                         inset_need_mask &= ~inset_mask_map[i].inset;
8551                 if (!inset_need_mask)
8552                         return 0;
8553         }
8554         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8555                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8556                     inset_mask_map[i].inset) {
8557                         if (idx >= nb_elem) {
8558                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8559                                 return -EINVAL;
8560                         }
8561                         mask[idx] = inset_mask_map[i].mask;
8562                         idx++;
8563                 }
8564         }
8565
8566         return idx;
8567 }
8568
8569 void
8570 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8571 {
8572         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8573
8574         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8575         if (reg != val)
8576                 i40e_write_rx_ctl(hw, addr, val);
8577         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8578                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8579 }
8580
8581 static void
8582 i40e_filter_input_set_init(struct i40e_pf *pf)
8583 {
8584         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8585         enum i40e_filter_pctype pctype;
8586         uint64_t input_set, inset_reg;
8587         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8588         int num, i;
8589
8590         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8591              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8592                 if (hw->mac.type == I40E_MAC_X722) {
8593                         if (!I40E_VALID_PCTYPE_X722(pctype))
8594                                 continue;
8595                 } else {
8596                         if (!I40E_VALID_PCTYPE(pctype))
8597                                 continue;
8598                 }
8599
8600                 input_set = i40e_get_default_input_set(pctype);
8601
8602                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8603                                                    I40E_INSET_MASK_NUM_REG);
8604                 if (num < 0)
8605                         return;
8606                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8607                                         input_set);
8608
8609                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8610                                       (uint32_t)(inset_reg & UINT32_MAX));
8611                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8612                                      (uint32_t)((inset_reg >>
8613                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8614                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8615                                       (uint32_t)(inset_reg & UINT32_MAX));
8616                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8617                                      (uint32_t)((inset_reg >>
8618                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8619
8620                 for (i = 0; i < num; i++) {
8621                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8622                                              mask_reg[i]);
8623                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8624                                              mask_reg[i]);
8625                 }
8626                 /*clear unused mask registers of the pctype */
8627                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8628                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8629                                              0);
8630                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8631                                              0);
8632                 }
8633                 I40E_WRITE_FLUSH(hw);
8634
8635                 /* store the default input set */
8636                 pf->hash_input_set[pctype] = input_set;
8637                 pf->fdir.input_set[pctype] = input_set;
8638         }
8639 }
8640
8641 int
8642 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8643                          struct rte_eth_input_set_conf *conf)
8644 {
8645         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8646         enum i40e_filter_pctype pctype;
8647         uint64_t input_set, inset_reg = 0;
8648         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8649         int ret, i, num;
8650
8651         if (!conf) {
8652                 PMD_DRV_LOG(ERR, "Invalid pointer");
8653                 return -EFAULT;
8654         }
8655         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8656             conf->op != RTE_ETH_INPUT_SET_ADD) {
8657                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8658                 return -EINVAL;
8659         }
8660
8661         if (!I40E_VALID_FLOW(conf->flow_type)) {
8662                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8663                 return -EINVAL;
8664         }
8665
8666         if (hw->mac.type == I40E_MAC_X722) {
8667                 /* get translated pctype value in fd pctype register */
8668                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8669                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8670                         conf->flow_type)));
8671         } else
8672                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8673
8674         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8675                                    conf->inset_size);
8676         if (ret) {
8677                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8678                 return -EINVAL;
8679         }
8680         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8681                                     input_set) != 0) {
8682                 PMD_DRV_LOG(ERR, "Invalid input set");
8683                 return -EINVAL;
8684         }
8685         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8686                 /* get inset value in register */
8687                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8688                 inset_reg <<= I40E_32_BIT_WIDTH;
8689                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8690                 input_set |= pf->hash_input_set[pctype];
8691         }
8692         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8693                                            I40E_INSET_MASK_NUM_REG);
8694         if (num < 0)
8695                 return -EINVAL;
8696
8697         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8698
8699         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8700                               (uint32_t)(inset_reg & UINT32_MAX));
8701         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8702                              (uint32_t)((inset_reg >>
8703                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8704
8705         for (i = 0; i < num; i++)
8706                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8707                                      mask_reg[i]);
8708         /*clear unused mask registers of the pctype */
8709         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8710                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8711                                      0);
8712         I40E_WRITE_FLUSH(hw);
8713
8714         pf->hash_input_set[pctype] = input_set;
8715         return 0;
8716 }
8717
8718 int
8719 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8720                          struct rte_eth_input_set_conf *conf)
8721 {
8722         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8723         enum i40e_filter_pctype pctype;
8724         uint64_t input_set, inset_reg = 0;
8725         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8726         int ret, i, num;
8727
8728         if (!hw || !conf) {
8729                 PMD_DRV_LOG(ERR, "Invalid pointer");
8730                 return -EFAULT;
8731         }
8732         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8733             conf->op != RTE_ETH_INPUT_SET_ADD) {
8734                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8735                 return -EINVAL;
8736         }
8737
8738         if (!I40E_VALID_FLOW(conf->flow_type)) {
8739                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8740                 return -EINVAL;
8741         }
8742
8743         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8744
8745         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8746                                    conf->inset_size);
8747         if (ret) {
8748                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8749                 return -EINVAL;
8750         }
8751         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8752                                     input_set) != 0) {
8753                 PMD_DRV_LOG(ERR, "Invalid input set");
8754                 return -EINVAL;
8755         }
8756
8757         /* get inset value in register */
8758         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8759         inset_reg <<= I40E_32_BIT_WIDTH;
8760         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8761
8762         /* Can not change the inset reg for flex payload for fdir,
8763          * it is done by writing I40E_PRTQF_FD_FLXINSET
8764          * in i40e_set_flex_mask_on_pctype.
8765          */
8766         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8767                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8768         else
8769                 input_set |= pf->fdir.input_set[pctype];
8770         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8771                                            I40E_INSET_MASK_NUM_REG);
8772         if (num < 0)
8773                 return -EINVAL;
8774
8775         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8776
8777         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8778                               (uint32_t)(inset_reg & UINT32_MAX));
8779         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8780                              (uint32_t)((inset_reg >>
8781                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8782
8783         for (i = 0; i < num; i++)
8784                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8785                                      mask_reg[i]);
8786         /*clear unused mask registers of the pctype */
8787         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8788                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8789                                      0);
8790         I40E_WRITE_FLUSH(hw);
8791
8792         pf->fdir.input_set[pctype] = input_set;
8793         return 0;
8794 }
8795
8796 static int
8797 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8798 {
8799         int ret = 0;
8800
8801         if (!hw || !info) {
8802                 PMD_DRV_LOG(ERR, "Invalid pointer");
8803                 return -EFAULT;
8804         }
8805
8806         switch (info->info_type) {
8807         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8808                 i40e_get_symmetric_hash_enable_per_port(hw,
8809                                         &(info->info.enable));
8810                 break;
8811         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8812                 ret = i40e_get_hash_filter_global_config(hw,
8813                                 &(info->info.global_conf));
8814                 break;
8815         default:
8816                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8817                                                         info->info_type);
8818                 ret = -EINVAL;
8819                 break;
8820         }
8821
8822         return ret;
8823 }
8824
8825 static int
8826 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8827 {
8828         int ret = 0;
8829
8830         if (!hw || !info) {
8831                 PMD_DRV_LOG(ERR, "Invalid pointer");
8832                 return -EFAULT;
8833         }
8834
8835         switch (info->info_type) {
8836         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8837                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8838                 break;
8839         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8840                 ret = i40e_set_hash_filter_global_config(hw,
8841                                 &(info->info.global_conf));
8842                 break;
8843         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8844                 ret = i40e_hash_filter_inset_select(hw,
8845                                                &(info->info.input_set_conf));
8846                 break;
8847
8848         default:
8849                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8850                                                         info->info_type);
8851                 ret = -EINVAL;
8852                 break;
8853         }
8854
8855         return ret;
8856 }
8857
8858 /* Operations for hash function */
8859 static int
8860 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8861                       enum rte_filter_op filter_op,
8862                       void *arg)
8863 {
8864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8865         int ret = 0;
8866
8867         switch (filter_op) {
8868         case RTE_ETH_FILTER_NOP:
8869                 break;
8870         case RTE_ETH_FILTER_GET:
8871                 ret = i40e_hash_filter_get(hw,
8872                         (struct rte_eth_hash_filter_info *)arg);
8873                 break;
8874         case RTE_ETH_FILTER_SET:
8875                 ret = i40e_hash_filter_set(hw,
8876                         (struct rte_eth_hash_filter_info *)arg);
8877                 break;
8878         default:
8879                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8880                                                                 filter_op);
8881                 ret = -ENOTSUP;
8882                 break;
8883         }
8884
8885         return ret;
8886 }
8887
8888 /* Convert ethertype filter structure */
8889 static int
8890 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8891                               struct i40e_ethertype_filter *filter)
8892 {
8893         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8894         filter->input.ether_type = input->ether_type;
8895         filter->flags = input->flags;
8896         filter->queue = input->queue;
8897
8898         return 0;
8899 }
8900
8901 /* Check if there exists the ehtertype filter */
8902 struct i40e_ethertype_filter *
8903 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8904                                 const struct i40e_ethertype_filter_input *input)
8905 {
8906         int ret;
8907
8908         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8909         if (ret < 0)
8910                 return NULL;
8911
8912         return ethertype_rule->hash_map[ret];
8913 }
8914
8915 /* Add ethertype filter in SW list */
8916 static int
8917 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8918                                 struct i40e_ethertype_filter *filter)
8919 {
8920         struct i40e_ethertype_rule *rule = &pf->ethertype;
8921         int ret;
8922
8923         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8924         if (ret < 0) {
8925                 PMD_DRV_LOG(ERR,
8926                             "Failed to insert ethertype filter"
8927                             " to hash table %d!",
8928                             ret);
8929                 return ret;
8930         }
8931         rule->hash_map[ret] = filter;
8932
8933         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8934
8935         return 0;
8936 }
8937
8938 /* Delete ethertype filter in SW list */
8939 int
8940 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8941                              struct i40e_ethertype_filter_input *input)
8942 {
8943         struct i40e_ethertype_rule *rule = &pf->ethertype;
8944         struct i40e_ethertype_filter *filter;
8945         int ret;
8946
8947         ret = rte_hash_del_key(rule->hash_table, input);
8948         if (ret < 0) {
8949                 PMD_DRV_LOG(ERR,
8950                             "Failed to delete ethertype filter"
8951                             " to hash table %d!",
8952                             ret);
8953                 return ret;
8954         }
8955         filter = rule->hash_map[ret];
8956         rule->hash_map[ret] = NULL;
8957
8958         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8959         rte_free(filter);
8960
8961         return 0;
8962 }
8963
8964 /*
8965  * Configure ethertype filter, which can director packet by filtering
8966  * with mac address and ether_type or only ether_type
8967  */
8968 int
8969 i40e_ethertype_filter_set(struct i40e_pf *pf,
8970                         struct rte_eth_ethertype_filter *filter,
8971                         bool add)
8972 {
8973         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8974         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8975         struct i40e_ethertype_filter *ethertype_filter, *node;
8976         struct i40e_ethertype_filter check_filter;
8977         struct i40e_control_filter_stats stats;
8978         uint16_t flags = 0;
8979         int ret;
8980
8981         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8982                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8983                 return -EINVAL;
8984         }
8985         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8986                 filter->ether_type == ETHER_TYPE_IPv6) {
8987                 PMD_DRV_LOG(ERR,
8988                         "unsupported ether_type(0x%04x) in control packet filter.",
8989                         filter->ether_type);
8990                 return -EINVAL;
8991         }
8992         if (filter->ether_type == ETHER_TYPE_VLAN)
8993                 PMD_DRV_LOG(WARNING,
8994                         "filter vlan ether_type in first tag is not supported.");
8995
8996         /* Check if there is the filter in SW list */
8997         memset(&check_filter, 0, sizeof(check_filter));
8998         i40e_ethertype_filter_convert(filter, &check_filter);
8999         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9000                                                &check_filter.input);
9001         if (add && node) {
9002                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9003                 return -EINVAL;
9004         }
9005
9006         if (!add && !node) {
9007                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9008                 return -EINVAL;
9009         }
9010
9011         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9012                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9013         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9014                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9015         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9016
9017         memset(&stats, 0, sizeof(stats));
9018         ret = i40e_aq_add_rem_control_packet_filter(hw,
9019                         filter->mac_addr.addr_bytes,
9020                         filter->ether_type, flags,
9021                         pf->main_vsi->seid,
9022                         filter->queue, add, &stats, NULL);
9023
9024         PMD_DRV_LOG(INFO,
9025                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9026                 ret, stats.mac_etype_used, stats.etype_used,
9027                 stats.mac_etype_free, stats.etype_free);
9028         if (ret < 0)
9029                 return -ENOSYS;
9030
9031         /* Add or delete a filter in SW list */
9032         if (add) {
9033                 ethertype_filter = rte_zmalloc("ethertype_filter",
9034                                        sizeof(*ethertype_filter), 0);
9035                 rte_memcpy(ethertype_filter, &check_filter,
9036                            sizeof(check_filter));
9037                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9038         } else {
9039                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9040         }
9041
9042         return ret;
9043 }
9044
9045 /*
9046  * Handle operations for ethertype filter.
9047  */
9048 static int
9049 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9050                                 enum rte_filter_op filter_op,
9051                                 void *arg)
9052 {
9053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9054         int ret = 0;
9055
9056         if (filter_op == RTE_ETH_FILTER_NOP)
9057                 return ret;
9058
9059         if (arg == NULL) {
9060                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9061                             filter_op);
9062                 return -EINVAL;
9063         }
9064
9065         switch (filter_op) {
9066         case RTE_ETH_FILTER_ADD:
9067                 ret = i40e_ethertype_filter_set(pf,
9068                         (struct rte_eth_ethertype_filter *)arg,
9069                         TRUE);
9070                 break;
9071         case RTE_ETH_FILTER_DELETE:
9072                 ret = i40e_ethertype_filter_set(pf,
9073                         (struct rte_eth_ethertype_filter *)arg,
9074                         FALSE);
9075                 break;
9076         default:
9077                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9078                 ret = -ENOSYS;
9079                 break;
9080         }
9081         return ret;
9082 }
9083
9084 static int
9085 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9086                      enum rte_filter_type filter_type,
9087                      enum rte_filter_op filter_op,
9088                      void *arg)
9089 {
9090         int ret = 0;
9091
9092         if (dev == NULL)
9093                 return -EINVAL;
9094
9095         switch (filter_type) {
9096         case RTE_ETH_FILTER_NONE:
9097                 /* For global configuration */
9098                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9099                 break;
9100         case RTE_ETH_FILTER_HASH:
9101                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9102                 break;
9103         case RTE_ETH_FILTER_MACVLAN:
9104                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9105                 break;
9106         case RTE_ETH_FILTER_ETHERTYPE:
9107                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9108                 break;
9109         case RTE_ETH_FILTER_TUNNEL:
9110                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9111                 break;
9112         case RTE_ETH_FILTER_FDIR:
9113                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9114                 break;
9115         case RTE_ETH_FILTER_GENERIC:
9116                 if (filter_op != RTE_ETH_FILTER_GET)
9117                         return -EINVAL;
9118                 *(const void **)arg = &i40e_flow_ops;
9119                 break;
9120         default:
9121                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9122                                                         filter_type);
9123                 ret = -EINVAL;
9124                 break;
9125         }
9126
9127         return ret;
9128 }
9129
9130 /*
9131  * Check and enable Extended Tag.
9132  * Enabling Extended Tag is important for 40G performance.
9133  */
9134 static void
9135 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9136 {
9137         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9138         uint32_t buf = 0;
9139         int ret;
9140
9141         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9142                                       PCI_DEV_CAP_REG);
9143         if (ret < 0) {
9144                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9145                             PCI_DEV_CAP_REG);
9146                 return;
9147         }
9148         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9149                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9150                 return;
9151         }
9152
9153         buf = 0;
9154         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9155                                       PCI_DEV_CTRL_REG);
9156         if (ret < 0) {
9157                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9158                             PCI_DEV_CTRL_REG);
9159                 return;
9160         }
9161         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9162                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9163                 return;
9164         }
9165         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9166         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9167                                        PCI_DEV_CTRL_REG);
9168         if (ret < 0) {
9169                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9170                             PCI_DEV_CTRL_REG);
9171                 return;
9172         }
9173 }
9174
9175 /*
9176  * As some registers wouldn't be reset unless a global hardware reset,
9177  * hardware initialization is needed to put those registers into an
9178  * expected initial state.
9179  */
9180 static void
9181 i40e_hw_init(struct rte_eth_dev *dev)
9182 {
9183         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9184
9185         i40e_enable_extended_tag(dev);
9186
9187         /* clear the PF Queue Filter control register */
9188         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9189
9190         /* Disable symmetric hash per port */
9191         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9192 }
9193
9194 enum i40e_filter_pctype
9195 i40e_flowtype_to_pctype(uint16_t flow_type)
9196 {
9197         static const enum i40e_filter_pctype pctype_table[] = {
9198                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9199                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9200                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9201                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9202                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9203                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9204                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9205                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9206                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9207                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9208                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9209                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9210                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9211                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9212                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9213                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9214                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9215                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9216                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9217         };
9218
9219         return pctype_table[flow_type];
9220 }
9221
9222 uint16_t
9223 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9224 {
9225         static const uint16_t flowtype_table[] = {
9226                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9227                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9228                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9229                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9230                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9231                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9232                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9233                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9234                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9235                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9236                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9237                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9238                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9239                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9240                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9241                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9242                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9243                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9244                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9245                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9246                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9247                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9248                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9249                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9250                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9251                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9252                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9253                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9254                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9255                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9256                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9257         };
9258
9259         return flowtype_table[pctype];
9260 }
9261
9262 /*
9263  * On X710, performance number is far from the expectation on recent firmware
9264  * versions; on XL710, performance number is also far from the expectation on
9265  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9266  * mode is enabled and port MAC address is equal to the packet destination MAC
9267  * address. The fix for this issue may not be integrated in the following
9268  * firmware version. So the workaround in software driver is needed. It needs
9269  * to modify the initial values of 3 internal only registers for both X710 and
9270  * XL710. Note that the values for X710 or XL710 could be different, and the
9271  * workaround can be removed when it is fixed in firmware in the future.
9272  */
9273
9274 /* For both X710 and XL710 */
9275 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9276 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9277 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9278
9279 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9280 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9281
9282 /* For X722 */
9283 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9284 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9285
9286 /* For X710 */
9287 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9288 /* For XL710 */
9289 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9290 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9291
9292 static int
9293 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9294 {
9295         enum i40e_status_code status;
9296         struct i40e_aq_get_phy_abilities_resp phy_ab;
9297         int ret = -ENOTSUP;
9298         int retries = 0;
9299
9300         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9301                                               NULL);
9302
9303         while (status) {
9304                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9305                         status);
9306                 retries++;
9307                 rte_delay_us(100000);
9308                 if  (retries < 5)
9309                         status = i40e_aq_get_phy_capabilities(hw, false,
9310                                         true, &phy_ab, NULL);
9311                 else
9312                         return ret;
9313         }
9314         return 0;
9315 }
9316
9317 static void
9318 i40e_configure_registers(struct i40e_hw *hw)
9319 {
9320         static struct {
9321                 uint32_t addr;
9322                 uint64_t val;
9323         } reg_table[] = {
9324                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9325                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9326                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9327         };
9328         uint64_t reg;
9329         uint32_t i;
9330         int ret;
9331
9332         for (i = 0; i < RTE_DIM(reg_table); i++) {
9333                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9334                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9335                                 reg_table[i].val =
9336                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9337                         else /* For X710/XL710/XXV710 */
9338                                 if (hw->aq.fw_maj_ver < 6)
9339                                         reg_table[i].val =
9340                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9341                                 else
9342                                         reg_table[i].val =
9343                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9344                 }
9345
9346                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9347                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9348                                 reg_table[i].val =
9349                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9350                         else /* For X710/XL710/XXV710 */
9351                                 reg_table[i].val =
9352                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9353                 }
9354
9355                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9356                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9357                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9358                                 reg_table[i].val =
9359                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9360                         else /* For X710 */
9361                                 reg_table[i].val =
9362                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9363                 }
9364
9365                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9366                                                         &reg, NULL);
9367                 if (ret < 0) {
9368                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9369                                                         reg_table[i].addr);
9370                         break;
9371                 }
9372                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9373                                                 reg_table[i].addr, reg);
9374                 if (reg == reg_table[i].val)
9375                         continue;
9376
9377                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9378                                                 reg_table[i].val, NULL);
9379                 if (ret < 0) {
9380                         PMD_DRV_LOG(ERR,
9381                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9382                                 reg_table[i].val, reg_table[i].addr);
9383                         break;
9384                 }
9385                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9386                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9387         }
9388 }
9389
9390 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9391 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9392 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9393 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9394 static int
9395 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9396 {
9397         uint32_t reg;
9398         int ret;
9399
9400         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9401                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9402                 return -EINVAL;
9403         }
9404
9405         /* Configure for double VLAN RX stripping */
9406         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9407         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9408                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9409                 ret = i40e_aq_debug_write_register(hw,
9410                                                    I40E_VSI_TSR(vsi->vsi_id),
9411                                                    reg, NULL);
9412                 if (ret < 0) {
9413                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9414                                     vsi->vsi_id);
9415                         return I40E_ERR_CONFIG;
9416                 }
9417         }
9418
9419         /* Configure for double VLAN TX insertion */
9420         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9421         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9422                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9423                 ret = i40e_aq_debug_write_register(hw,
9424                                                    I40E_VSI_L2TAGSTXVALID(
9425                                                    vsi->vsi_id), reg, NULL);
9426                 if (ret < 0) {
9427                         PMD_DRV_LOG(ERR,
9428                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9429                                 vsi->vsi_id);
9430                         return I40E_ERR_CONFIG;
9431                 }
9432         }
9433
9434         return 0;
9435 }
9436
9437 /**
9438  * i40e_aq_add_mirror_rule
9439  * @hw: pointer to the hardware structure
9440  * @seid: VEB seid to add mirror rule to
9441  * @dst_id: destination vsi seid
9442  * @entries: Buffer which contains the entities to be mirrored
9443  * @count: number of entities contained in the buffer
9444  * @rule_id:the rule_id of the rule to be added
9445  *
9446  * Add a mirror rule for a given veb.
9447  *
9448  **/
9449 static enum i40e_status_code
9450 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9451                         uint16_t seid, uint16_t dst_id,
9452                         uint16_t rule_type, uint16_t *entries,
9453                         uint16_t count, uint16_t *rule_id)
9454 {
9455         struct i40e_aq_desc desc;
9456         struct i40e_aqc_add_delete_mirror_rule cmd;
9457         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9458                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9459                 &desc.params.raw;
9460         uint16_t buff_len;
9461         enum i40e_status_code status;
9462
9463         i40e_fill_default_direct_cmd_desc(&desc,
9464                                           i40e_aqc_opc_add_mirror_rule);
9465         memset(&cmd, 0, sizeof(cmd));
9466
9467         buff_len = sizeof(uint16_t) * count;
9468         desc.datalen = rte_cpu_to_le_16(buff_len);
9469         if (buff_len > 0)
9470                 desc.flags |= rte_cpu_to_le_16(
9471                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9472         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9473                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9474         cmd.num_entries = rte_cpu_to_le_16(count);
9475         cmd.seid = rte_cpu_to_le_16(seid);
9476         cmd.destination = rte_cpu_to_le_16(dst_id);
9477
9478         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9479         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9480         PMD_DRV_LOG(INFO,
9481                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9482                 hw->aq.asq_last_status, resp->rule_id,
9483                 resp->mirror_rules_used, resp->mirror_rules_free);
9484         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9485
9486         return status;
9487 }
9488
9489 /**
9490  * i40e_aq_del_mirror_rule
9491  * @hw: pointer to the hardware structure
9492  * @seid: VEB seid to add mirror rule to
9493  * @entries: Buffer which contains the entities to be mirrored
9494  * @count: number of entities contained in the buffer
9495  * @rule_id:the rule_id of the rule to be delete
9496  *
9497  * Delete a mirror rule for a given veb.
9498  *
9499  **/
9500 static enum i40e_status_code
9501 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9502                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9503                 uint16_t count, uint16_t rule_id)
9504 {
9505         struct i40e_aq_desc desc;
9506         struct i40e_aqc_add_delete_mirror_rule cmd;
9507         uint16_t buff_len = 0;
9508         enum i40e_status_code status;
9509         void *buff = NULL;
9510
9511         i40e_fill_default_direct_cmd_desc(&desc,
9512                                           i40e_aqc_opc_delete_mirror_rule);
9513         memset(&cmd, 0, sizeof(cmd));
9514         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9515                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9516                                                           I40E_AQ_FLAG_RD));
9517                 cmd.num_entries = count;
9518                 buff_len = sizeof(uint16_t) * count;
9519                 desc.datalen = rte_cpu_to_le_16(buff_len);
9520                 buff = (void *)entries;
9521         } else
9522                 /* rule id is filled in destination field for deleting mirror rule */
9523                 cmd.destination = rte_cpu_to_le_16(rule_id);
9524
9525         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9526                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9527         cmd.seid = rte_cpu_to_le_16(seid);
9528
9529         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9530         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9531
9532         return status;
9533 }
9534
9535 /**
9536  * i40e_mirror_rule_set
9537  * @dev: pointer to the hardware structure
9538  * @mirror_conf: mirror rule info
9539  * @sw_id: mirror rule's sw_id
9540  * @on: enable/disable
9541  *
9542  * set a mirror rule.
9543  *
9544  **/
9545 static int
9546 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9547                         struct rte_eth_mirror_conf *mirror_conf,
9548                         uint8_t sw_id, uint8_t on)
9549 {
9550         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9552         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9553         struct i40e_mirror_rule *parent = NULL;
9554         uint16_t seid, dst_seid, rule_id;
9555         uint16_t i, j = 0;
9556         int ret;
9557
9558         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9559
9560         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9561                 PMD_DRV_LOG(ERR,
9562                         "mirror rule can not be configured without veb or vfs.");
9563                 return -ENOSYS;
9564         }
9565         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9566                 PMD_DRV_LOG(ERR, "mirror table is full.");
9567                 return -ENOSPC;
9568         }
9569         if (mirror_conf->dst_pool > pf->vf_num) {
9570                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9571                                  mirror_conf->dst_pool);
9572                 return -EINVAL;
9573         }
9574
9575         seid = pf->main_vsi->veb->seid;
9576
9577         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9578                 if (sw_id <= it->index) {
9579                         mirr_rule = it;
9580                         break;
9581                 }
9582                 parent = it;
9583         }
9584         if (mirr_rule && sw_id == mirr_rule->index) {
9585                 if (on) {
9586                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9587                         return -EEXIST;
9588                 } else {
9589                         ret = i40e_aq_del_mirror_rule(hw, seid,
9590                                         mirr_rule->rule_type,
9591                                         mirr_rule->entries,
9592                                         mirr_rule->num_entries, mirr_rule->id);
9593                         if (ret < 0) {
9594                                 PMD_DRV_LOG(ERR,
9595                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9596                                         ret, hw->aq.asq_last_status);
9597                                 return -ENOSYS;
9598                         }
9599                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9600                         rte_free(mirr_rule);
9601                         pf->nb_mirror_rule--;
9602                         return 0;
9603                 }
9604         } else if (!on) {
9605                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9606                 return -ENOENT;
9607         }
9608
9609         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9610                                 sizeof(struct i40e_mirror_rule) , 0);
9611         if (!mirr_rule) {
9612                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9613                 return I40E_ERR_NO_MEMORY;
9614         }
9615         switch (mirror_conf->rule_type) {
9616         case ETH_MIRROR_VLAN:
9617                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9618                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9619                                 mirr_rule->entries[j] =
9620                                         mirror_conf->vlan.vlan_id[i];
9621                                 j++;
9622                         }
9623                 }
9624                 if (j == 0) {
9625                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9626                         rte_free(mirr_rule);
9627                         return -EINVAL;
9628                 }
9629                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9630                 break;
9631         case ETH_MIRROR_VIRTUAL_POOL_UP:
9632         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9633                 /* check if the specified pool bit is out of range */
9634                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9635                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9636                         rte_free(mirr_rule);
9637                         return -EINVAL;
9638                 }
9639                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9640                         if (mirror_conf->pool_mask & (1ULL << i)) {
9641                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9642                                 j++;
9643                         }
9644                 }
9645                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9646                         /* add pf vsi to entries */
9647                         mirr_rule->entries[j] = pf->main_vsi_seid;
9648                         j++;
9649                 }
9650                 if (j == 0) {
9651                         PMD_DRV_LOG(ERR, "pool is not specified.");
9652                         rte_free(mirr_rule);
9653                         return -EINVAL;
9654                 }
9655                 /* egress and ingress in aq commands means from switch but not port */
9656                 mirr_rule->rule_type =
9657                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9658                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9659                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9660                 break;
9661         case ETH_MIRROR_UPLINK_PORT:
9662                 /* egress and ingress in aq commands means from switch but not port*/
9663                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9664                 break;
9665         case ETH_MIRROR_DOWNLINK_PORT:
9666                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9667                 break;
9668         default:
9669                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9670                         mirror_conf->rule_type);
9671                 rte_free(mirr_rule);
9672                 return -EINVAL;
9673         }
9674
9675         /* If the dst_pool is equal to vf_num, consider it as PF */
9676         if (mirror_conf->dst_pool == pf->vf_num)
9677                 dst_seid = pf->main_vsi_seid;
9678         else
9679                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9680
9681         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9682                                       mirr_rule->rule_type, mirr_rule->entries,
9683                                       j, &rule_id);
9684         if (ret < 0) {
9685                 PMD_DRV_LOG(ERR,
9686                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9687                         ret, hw->aq.asq_last_status);
9688                 rte_free(mirr_rule);
9689                 return -ENOSYS;
9690         }
9691
9692         mirr_rule->index = sw_id;
9693         mirr_rule->num_entries = j;
9694         mirr_rule->id = rule_id;
9695         mirr_rule->dst_vsi_seid = dst_seid;
9696
9697         if (parent)
9698                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9699         else
9700                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9701
9702         pf->nb_mirror_rule++;
9703         return 0;
9704 }
9705
9706 /**
9707  * i40e_mirror_rule_reset
9708  * @dev: pointer to the device
9709  * @sw_id: mirror rule's sw_id
9710  *
9711  * reset a mirror rule.
9712  *
9713  **/
9714 static int
9715 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9716 {
9717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9719         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9720         uint16_t seid;
9721         int ret;
9722
9723         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9724
9725         seid = pf->main_vsi->veb->seid;
9726
9727         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9728                 if (sw_id == it->index) {
9729                         mirr_rule = it;
9730                         break;
9731                 }
9732         }
9733         if (mirr_rule) {
9734                 ret = i40e_aq_del_mirror_rule(hw, seid,
9735                                 mirr_rule->rule_type,
9736                                 mirr_rule->entries,
9737                                 mirr_rule->num_entries, mirr_rule->id);
9738                 if (ret < 0) {
9739                         PMD_DRV_LOG(ERR,
9740                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9741                                 ret, hw->aq.asq_last_status);
9742                         return -ENOSYS;
9743                 }
9744                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9745                 rte_free(mirr_rule);
9746                 pf->nb_mirror_rule--;
9747         } else {
9748                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9749                 return -ENOENT;
9750         }
9751         return 0;
9752 }
9753
9754 static uint64_t
9755 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9756 {
9757         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9758         uint64_t systim_cycles;
9759
9760         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9761         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9762                         << 32;
9763
9764         return systim_cycles;
9765 }
9766
9767 static uint64_t
9768 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9769 {
9770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9771         uint64_t rx_tstamp;
9772
9773         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9774         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9775                         << 32;
9776
9777         return rx_tstamp;
9778 }
9779
9780 static uint64_t
9781 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9782 {
9783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9784         uint64_t tx_tstamp;
9785
9786         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9787         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9788                         << 32;
9789
9790         return tx_tstamp;
9791 }
9792
9793 static void
9794 i40e_start_timecounters(struct rte_eth_dev *dev)
9795 {
9796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9797         struct i40e_adapter *adapter =
9798                         (struct i40e_adapter *)dev->data->dev_private;
9799         struct rte_eth_link link;
9800         uint32_t tsync_inc_l;
9801         uint32_t tsync_inc_h;
9802
9803         /* Get current link speed. */
9804         memset(&link, 0, sizeof(link));
9805         i40e_dev_link_update(dev, 1);
9806         rte_i40e_dev_atomic_read_link_status(dev, &link);
9807
9808         switch (link.link_speed) {
9809         case ETH_SPEED_NUM_40G:
9810                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9811                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9812                 break;
9813         case ETH_SPEED_NUM_10G:
9814                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9815                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9816                 break;
9817         case ETH_SPEED_NUM_1G:
9818                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9819                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9820                 break;
9821         default:
9822                 tsync_inc_l = 0x0;
9823                 tsync_inc_h = 0x0;
9824         }
9825
9826         /* Set the timesync increment value. */
9827         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9828         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9829
9830         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9831         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9832         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9833
9834         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9835         adapter->systime_tc.cc_shift = 0;
9836         adapter->systime_tc.nsec_mask = 0;
9837
9838         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9839         adapter->rx_tstamp_tc.cc_shift = 0;
9840         adapter->rx_tstamp_tc.nsec_mask = 0;
9841
9842         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9843         adapter->tx_tstamp_tc.cc_shift = 0;
9844         adapter->tx_tstamp_tc.nsec_mask = 0;
9845 }
9846
9847 static int
9848 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9849 {
9850         struct i40e_adapter *adapter =
9851                         (struct i40e_adapter *)dev->data->dev_private;
9852
9853         adapter->systime_tc.nsec += delta;
9854         adapter->rx_tstamp_tc.nsec += delta;
9855         adapter->tx_tstamp_tc.nsec += delta;
9856
9857         return 0;
9858 }
9859
9860 static int
9861 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9862 {
9863         uint64_t ns;
9864         struct i40e_adapter *adapter =
9865                         (struct i40e_adapter *)dev->data->dev_private;
9866
9867         ns = rte_timespec_to_ns(ts);
9868
9869         /* Set the timecounters to a new value. */
9870         adapter->systime_tc.nsec = ns;
9871         adapter->rx_tstamp_tc.nsec = ns;
9872         adapter->tx_tstamp_tc.nsec = ns;
9873
9874         return 0;
9875 }
9876
9877 static int
9878 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9879 {
9880         uint64_t ns, systime_cycles;
9881         struct i40e_adapter *adapter =
9882                         (struct i40e_adapter *)dev->data->dev_private;
9883
9884         systime_cycles = i40e_read_systime_cyclecounter(dev);
9885         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9886         *ts = rte_ns_to_timespec(ns);
9887
9888         return 0;
9889 }
9890
9891 static int
9892 i40e_timesync_enable(struct rte_eth_dev *dev)
9893 {
9894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9895         uint32_t tsync_ctl_l;
9896         uint32_t tsync_ctl_h;
9897
9898         /* Stop the timesync system time. */
9899         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9900         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9901         /* Reset the timesync system time value. */
9902         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9903         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9904
9905         i40e_start_timecounters(dev);
9906
9907         /* Clear timesync registers. */
9908         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9909         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9910         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9911         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9912         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9913         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9914
9915         /* Enable timestamping of PTP packets. */
9916         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9917         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9918
9919         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9920         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9921         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9922
9923         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9924         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9925
9926         return 0;
9927 }
9928
9929 static int
9930 i40e_timesync_disable(struct rte_eth_dev *dev)
9931 {
9932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9933         uint32_t tsync_ctl_l;
9934         uint32_t tsync_ctl_h;
9935
9936         /* Disable timestamping of transmitted PTP packets. */
9937         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9938         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9939
9940         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9941         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9942
9943         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9944         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9945
9946         /* Reset the timesync increment value. */
9947         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9948         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9949
9950         return 0;
9951 }
9952
9953 static int
9954 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9955                                 struct timespec *timestamp, uint32_t flags)
9956 {
9957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9958         struct i40e_adapter *adapter =
9959                 (struct i40e_adapter *)dev->data->dev_private;
9960
9961         uint32_t sync_status;
9962         uint32_t index = flags & 0x03;
9963         uint64_t rx_tstamp_cycles;
9964         uint64_t ns;
9965
9966         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9967         if ((sync_status & (1 << index)) == 0)
9968                 return -EINVAL;
9969
9970         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9971         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9972         *timestamp = rte_ns_to_timespec(ns);
9973
9974         return 0;
9975 }
9976
9977 static int
9978 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9979                                 struct timespec *timestamp)
9980 {
9981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9982         struct i40e_adapter *adapter =
9983                 (struct i40e_adapter *)dev->data->dev_private;
9984
9985         uint32_t sync_status;
9986         uint64_t tx_tstamp_cycles;
9987         uint64_t ns;
9988
9989         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9990         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9991                 return -EINVAL;
9992
9993         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9994         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9995         *timestamp = rte_ns_to_timespec(ns);
9996
9997         return 0;
9998 }
9999
10000 /*
10001  * i40e_parse_dcb_configure - parse dcb configure from user
10002  * @dev: the device being configured
10003  * @dcb_cfg: pointer of the result of parse
10004  * @*tc_map: bit map of enabled traffic classes
10005  *
10006  * Returns 0 on success, negative value on failure
10007  */
10008 static int
10009 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10010                          struct i40e_dcbx_config *dcb_cfg,
10011                          uint8_t *tc_map)
10012 {
10013         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10014         uint8_t i, tc_bw, bw_lf;
10015
10016         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10017
10018         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10019         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10020                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10021                 return -EINVAL;
10022         }
10023
10024         /* assume each tc has the same bw */
10025         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10026         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10027                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10028         /* to ensure the sum of tcbw is equal to 100 */
10029         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10030         for (i = 0; i < bw_lf; i++)
10031                 dcb_cfg->etscfg.tcbwtable[i]++;
10032
10033         /* assume each tc has the same Transmission Selection Algorithm */
10034         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10035                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10036
10037         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10038                 dcb_cfg->etscfg.prioritytable[i] =
10039                                 dcb_rx_conf->dcb_tc[i];
10040
10041         /* FW needs one App to configure HW */
10042         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10043         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10044         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10045         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10046
10047         if (dcb_rx_conf->nb_tcs == 0)
10048                 *tc_map = 1; /* tc0 only */
10049         else
10050                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10051
10052         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10053                 dcb_cfg->pfc.willing = 0;
10054                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10055                 dcb_cfg->pfc.pfcenable = *tc_map;
10056         }
10057         return 0;
10058 }
10059
10060
10061 static enum i40e_status_code
10062 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10063                               struct i40e_aqc_vsi_properties_data *info,
10064                               uint8_t enabled_tcmap)
10065 {
10066         enum i40e_status_code ret;
10067         int i, total_tc = 0;
10068         uint16_t qpnum_per_tc, bsf, qp_idx;
10069         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10070         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10071         uint16_t used_queues;
10072
10073         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10074         if (ret != I40E_SUCCESS)
10075                 return ret;
10076
10077         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10078                 if (enabled_tcmap & (1 << i))
10079                         total_tc++;
10080         }
10081         if (total_tc == 0)
10082                 total_tc = 1;
10083         vsi->enabled_tc = enabled_tcmap;
10084
10085         /* different VSI has different queues assigned */
10086         if (vsi->type == I40E_VSI_MAIN)
10087                 used_queues = dev_data->nb_rx_queues -
10088                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10089         else if (vsi->type == I40E_VSI_VMDQ2)
10090                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10091         else {
10092                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10093                 return I40E_ERR_NO_AVAILABLE_VSI;
10094         }
10095
10096         qpnum_per_tc = used_queues / total_tc;
10097         /* Number of queues per enabled TC */
10098         if (qpnum_per_tc == 0) {
10099                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10100                 return I40E_ERR_INVALID_QP_ID;
10101         }
10102         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10103                                 I40E_MAX_Q_PER_TC);
10104         bsf = rte_bsf32(qpnum_per_tc);
10105
10106         /**
10107          * Configure TC and queue mapping parameters, for enabled TC,
10108          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10109          * default queue will serve it.
10110          */
10111         qp_idx = 0;
10112         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10113                 if (vsi->enabled_tc & (1 << i)) {
10114                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10115                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10116                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10117                         qp_idx += qpnum_per_tc;
10118                 } else
10119                         info->tc_mapping[i] = 0;
10120         }
10121
10122         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10123         if (vsi->type == I40E_VSI_SRIOV) {
10124                 info->mapping_flags |=
10125                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10126                 for (i = 0; i < vsi->nb_qps; i++)
10127                         info->queue_mapping[i] =
10128                                 rte_cpu_to_le_16(vsi->base_queue + i);
10129         } else {
10130                 info->mapping_flags |=
10131                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10132                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10133         }
10134         info->valid_sections |=
10135                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10136
10137         return I40E_SUCCESS;
10138 }
10139
10140 /*
10141  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10142  * @veb: VEB to be configured
10143  * @tc_map: enabled TC bitmap
10144  *
10145  * Returns 0 on success, negative value on failure
10146  */
10147 static enum i40e_status_code
10148 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10149 {
10150         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10151         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10152         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10153         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10154         enum i40e_status_code ret = I40E_SUCCESS;
10155         int i;
10156         uint32_t bw_max;
10157
10158         /* Check if enabled_tc is same as existing or new TCs */
10159         if (veb->enabled_tc == tc_map)
10160                 return ret;
10161
10162         /* configure tc bandwidth */
10163         memset(&veb_bw, 0, sizeof(veb_bw));
10164         veb_bw.tc_valid_bits = tc_map;
10165         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10166         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10167                 if (tc_map & BIT_ULL(i))
10168                         veb_bw.tc_bw_share_credits[i] = 1;
10169         }
10170         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10171                                                    &veb_bw, NULL);
10172         if (ret) {
10173                 PMD_INIT_LOG(ERR,
10174                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10175                         hw->aq.asq_last_status);
10176                 return ret;
10177         }
10178
10179         memset(&ets_query, 0, sizeof(ets_query));
10180         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10181                                                    &ets_query, NULL);
10182         if (ret != I40E_SUCCESS) {
10183                 PMD_DRV_LOG(ERR,
10184                         "Failed to get switch_comp ETS configuration %u",
10185                         hw->aq.asq_last_status);
10186                 return ret;
10187         }
10188         memset(&bw_query, 0, sizeof(bw_query));
10189         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10190                                                   &bw_query, NULL);
10191         if (ret != I40E_SUCCESS) {
10192                 PMD_DRV_LOG(ERR,
10193                         "Failed to get switch_comp bandwidth configuration %u",
10194                         hw->aq.asq_last_status);
10195                 return ret;
10196         }
10197
10198         /* store and print out BW info */
10199         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10200         veb->bw_info.bw_max = ets_query.tc_bw_max;
10201         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10202         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10203         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10204                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10205                      I40E_16_BIT_WIDTH);
10206         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10207                 veb->bw_info.bw_ets_share_credits[i] =
10208                                 bw_query.tc_bw_share_credits[i];
10209                 veb->bw_info.bw_ets_credits[i] =
10210                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10211                 /* 4 bits per TC, 4th bit is reserved */
10212                 veb->bw_info.bw_ets_max[i] =
10213                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10214                                   RTE_LEN2MASK(3, uint8_t));
10215                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10216                             veb->bw_info.bw_ets_share_credits[i]);
10217                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10218                             veb->bw_info.bw_ets_credits[i]);
10219                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10220                             veb->bw_info.bw_ets_max[i]);
10221         }
10222
10223         veb->enabled_tc = tc_map;
10224
10225         return ret;
10226 }
10227
10228
10229 /*
10230  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10231  * @vsi: VSI to be configured
10232  * @tc_map: enabled TC bitmap
10233  *
10234  * Returns 0 on success, negative value on failure
10235  */
10236 static enum i40e_status_code
10237 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10238 {
10239         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10240         struct i40e_vsi_context ctxt;
10241         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10242         enum i40e_status_code ret = I40E_SUCCESS;
10243         int i;
10244
10245         /* Check if enabled_tc is same as existing or new TCs */
10246         if (vsi->enabled_tc == tc_map)
10247                 return ret;
10248
10249         /* configure tc bandwidth */
10250         memset(&bw_data, 0, sizeof(bw_data));
10251         bw_data.tc_valid_bits = tc_map;
10252         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10253         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10254                 if (tc_map & BIT_ULL(i))
10255                         bw_data.tc_bw_credits[i] = 1;
10256         }
10257         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10258         if (ret) {
10259                 PMD_INIT_LOG(ERR,
10260                         "AQ command Config VSI BW allocation per TC failed = %d",
10261                         hw->aq.asq_last_status);
10262                 goto out;
10263         }
10264         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10265                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10266
10267         /* Update Queue Pairs Mapping for currently enabled UPs */
10268         ctxt.seid = vsi->seid;
10269         ctxt.pf_num = hw->pf_id;
10270         ctxt.vf_num = 0;
10271         ctxt.uplink_seid = vsi->uplink_seid;
10272         ctxt.info = vsi->info;
10273         i40e_get_cap(hw);
10274         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10275         if (ret)
10276                 goto out;
10277
10278         /* Update the VSI after updating the VSI queue-mapping information */
10279         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10280         if (ret) {
10281                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10282                         hw->aq.asq_last_status);
10283                 goto out;
10284         }
10285         /* update the local VSI info with updated queue map */
10286         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10287                                         sizeof(vsi->info.tc_mapping));
10288         (void)rte_memcpy(&vsi->info.queue_mapping,
10289                         &ctxt.info.queue_mapping,
10290                 sizeof(vsi->info.queue_mapping));
10291         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10292         vsi->info.valid_sections = 0;
10293
10294         /* query and update current VSI BW information */
10295         ret = i40e_vsi_get_bw_config(vsi);
10296         if (ret) {
10297                 PMD_INIT_LOG(ERR,
10298                          "Failed updating vsi bw info, err %s aq_err %s",
10299                          i40e_stat_str(hw, ret),
10300                          i40e_aq_str(hw, hw->aq.asq_last_status));
10301                 goto out;
10302         }
10303
10304         vsi->enabled_tc = tc_map;
10305
10306 out:
10307         return ret;
10308 }
10309
10310 /*
10311  * i40e_dcb_hw_configure - program the dcb setting to hw
10312  * @pf: pf the configuration is taken on
10313  * @new_cfg: new configuration
10314  * @tc_map: enabled TC bitmap
10315  *
10316  * Returns 0 on success, negative value on failure
10317  */
10318 static enum i40e_status_code
10319 i40e_dcb_hw_configure(struct i40e_pf *pf,
10320                       struct i40e_dcbx_config *new_cfg,
10321                       uint8_t tc_map)
10322 {
10323         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10324         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10325         struct i40e_vsi *main_vsi = pf->main_vsi;
10326         struct i40e_vsi_list *vsi_list;
10327         enum i40e_status_code ret;
10328         int i;
10329         uint32_t val;
10330
10331         /* Use the FW API if FW > v4.4*/
10332         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10333               (hw->aq.fw_maj_ver >= 5))) {
10334                 PMD_INIT_LOG(ERR,
10335                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10336                 return I40E_ERR_FIRMWARE_API_VERSION;
10337         }
10338
10339         /* Check if need reconfiguration */
10340         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10341                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10342                 return I40E_SUCCESS;
10343         }
10344
10345         /* Copy the new config to the current config */
10346         *old_cfg = *new_cfg;
10347         old_cfg->etsrec = old_cfg->etscfg;
10348         ret = i40e_set_dcb_config(hw);
10349         if (ret) {
10350                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10351                          i40e_stat_str(hw, ret),
10352                          i40e_aq_str(hw, hw->aq.asq_last_status));
10353                 return ret;
10354         }
10355         /* set receive Arbiter to RR mode and ETS scheme by default */
10356         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10357                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10358                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10359                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10360                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10361                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10362                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10363                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10364                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10365                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10366                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10367                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10368                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10369         }
10370         /* get local mib to check whether it is configured correctly */
10371         /* IEEE mode */
10372         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10373         /* Get Local DCB Config */
10374         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10375                                      &hw->local_dcbx_config);
10376
10377         /* if Veb is created, need to update TC of it at first */
10378         if (main_vsi->veb) {
10379                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10380                 if (ret)
10381                         PMD_INIT_LOG(WARNING,
10382                                  "Failed configuring TC for VEB seid=%d",
10383                                  main_vsi->veb->seid);
10384         }
10385         /* Update each VSI */
10386         i40e_vsi_config_tc(main_vsi, tc_map);
10387         if (main_vsi->veb) {
10388                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10389                         /* Beside main VSI and VMDQ VSIs, only enable default
10390                          * TC for other VSIs
10391                          */
10392                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10393                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10394                                                          tc_map);
10395                         else
10396                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10397                                                          I40E_DEFAULT_TCMAP);
10398                         if (ret)
10399                                 PMD_INIT_LOG(WARNING,
10400                                         "Failed configuring TC for VSI seid=%d",
10401                                         vsi_list->vsi->seid);
10402                         /* continue */
10403                 }
10404         }
10405         return I40E_SUCCESS;
10406 }
10407
10408 /*
10409  * i40e_dcb_init_configure - initial dcb config
10410  * @dev: device being configured
10411  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10412  *
10413  * Returns 0 on success, negative value on failure
10414  */
10415 static int
10416 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10417 {
10418         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10419         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10420         int i, ret = 0;
10421
10422         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10423                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10424                 return -ENOTSUP;
10425         }
10426
10427         /* DCB initialization:
10428          * Update DCB configuration from the Firmware and configure
10429          * LLDP MIB change event.
10430          */
10431         if (sw_dcb == TRUE) {
10432                 ret = i40e_init_dcb(hw);
10433                 /* If lldp agent is stopped, the return value from
10434                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10435                  * adminq status. Otherwise, it should return success.
10436                  */
10437                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10438                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10439                         memset(&hw->local_dcbx_config, 0,
10440                                 sizeof(struct i40e_dcbx_config));
10441                         /* set dcb default configuration */
10442                         hw->local_dcbx_config.etscfg.willing = 0;
10443                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10444                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10445                         hw->local_dcbx_config.etscfg.tsatable[0] =
10446                                                 I40E_IEEE_TSA_ETS;
10447                         /* all UPs mapping to TC0 */
10448                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10449                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10450                         hw->local_dcbx_config.etsrec =
10451                                 hw->local_dcbx_config.etscfg;
10452                         hw->local_dcbx_config.pfc.willing = 0;
10453                         hw->local_dcbx_config.pfc.pfccap =
10454                                                 I40E_MAX_TRAFFIC_CLASS;
10455                         /* FW needs one App to configure HW */
10456                         hw->local_dcbx_config.numapps = 1;
10457                         hw->local_dcbx_config.app[0].selector =
10458                                                 I40E_APP_SEL_ETHTYPE;
10459                         hw->local_dcbx_config.app[0].priority = 3;
10460                         hw->local_dcbx_config.app[0].protocolid =
10461                                                 I40E_APP_PROTOID_FCOE;
10462                         ret = i40e_set_dcb_config(hw);
10463                         if (ret) {
10464                                 PMD_INIT_LOG(ERR,
10465                                         "default dcb config fails. err = %d, aq_err = %d.",
10466                                         ret, hw->aq.asq_last_status);
10467                                 return -ENOSYS;
10468                         }
10469                 } else {
10470                         PMD_INIT_LOG(ERR,
10471                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10472                                 ret, hw->aq.asq_last_status);
10473                         return -ENOTSUP;
10474                 }
10475         } else {
10476                 ret = i40e_aq_start_lldp(hw, NULL);
10477                 if (ret != I40E_SUCCESS)
10478                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10479
10480                 ret = i40e_init_dcb(hw);
10481                 if (!ret) {
10482                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10483                                 PMD_INIT_LOG(ERR,
10484                                         "HW doesn't support DCBX offload.");
10485                                 return -ENOTSUP;
10486                         }
10487                 } else {
10488                         PMD_INIT_LOG(ERR,
10489                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10490                                 ret, hw->aq.asq_last_status);
10491                         return -ENOTSUP;
10492                 }
10493         }
10494         return 0;
10495 }
10496
10497 /*
10498  * i40e_dcb_setup - setup dcb related config
10499  * @dev: device being configured
10500  *
10501  * Returns 0 on success, negative value on failure
10502  */
10503 static int
10504 i40e_dcb_setup(struct rte_eth_dev *dev)
10505 {
10506         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10507         struct i40e_dcbx_config dcb_cfg;
10508         uint8_t tc_map = 0;
10509         int ret = 0;
10510
10511         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10512                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10513                 return -ENOTSUP;
10514         }
10515
10516         if (pf->vf_num != 0)
10517                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10518
10519         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10520         if (ret) {
10521                 PMD_INIT_LOG(ERR, "invalid dcb config");
10522                 return -EINVAL;
10523         }
10524         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10525         if (ret) {
10526                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10527                 return -ENOSYS;
10528         }
10529
10530         return 0;
10531 }
10532
10533 static int
10534 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10535                       struct rte_eth_dcb_info *dcb_info)
10536 {
10537         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10539         struct i40e_vsi *vsi = pf->main_vsi;
10540         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10541         uint16_t bsf, tc_mapping;
10542         int i, j = 0;
10543
10544         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10545                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10546         else
10547                 dcb_info->nb_tcs = 1;
10548         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10549                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10550         for (i = 0; i < dcb_info->nb_tcs; i++)
10551                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10552
10553         /* get queue mapping if vmdq is disabled */
10554         if (!pf->nb_cfg_vmdq_vsi) {
10555                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10556                         if (!(vsi->enabled_tc & (1 << i)))
10557                                 continue;
10558                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10559                         dcb_info->tc_queue.tc_rxq[j][i].base =
10560                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10561                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10562                         dcb_info->tc_queue.tc_txq[j][i].base =
10563                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10564                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10565                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10566                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10567                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10568                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10569                 }
10570                 return 0;
10571         }
10572
10573         /* get queue mapping if vmdq is enabled */
10574         do {
10575                 vsi = pf->vmdq[j].vsi;
10576                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10577                         if (!(vsi->enabled_tc & (1 << i)))
10578                                 continue;
10579                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10580                         dcb_info->tc_queue.tc_rxq[j][i].base =
10581                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10582                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10583                         dcb_info->tc_queue.tc_txq[j][i].base =
10584                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10585                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10586                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10587                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10588                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10589                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10590                 }
10591                 j++;
10592         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10593         return 0;
10594 }
10595
10596 static int
10597 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10598 {
10599         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10600         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10601         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10602         uint16_t interval =
10603                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10604         uint16_t msix_intr;
10605
10606         msix_intr = intr_handle->intr_vec[queue_id];
10607         if (msix_intr == I40E_MISC_VEC_ID)
10608                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10609                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10610                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10611                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10612                                (interval <<
10613                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10614         else
10615                 I40E_WRITE_REG(hw,
10616                                I40E_PFINT_DYN_CTLN(msix_intr -
10617                                                    I40E_RX_VEC_START),
10618                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10619                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10620                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10621                                (interval <<
10622                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10623
10624         I40E_WRITE_FLUSH(hw);
10625         rte_intr_enable(&pci_dev->intr_handle);
10626
10627         return 0;
10628 }
10629
10630 static int
10631 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10632 {
10633         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10634         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10635         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10636         uint16_t msix_intr;
10637
10638         msix_intr = intr_handle->intr_vec[queue_id];
10639         if (msix_intr == I40E_MISC_VEC_ID)
10640                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10641         else
10642                 I40E_WRITE_REG(hw,
10643                                I40E_PFINT_DYN_CTLN(msix_intr -
10644                                                    I40E_RX_VEC_START),
10645                                0);
10646         I40E_WRITE_FLUSH(hw);
10647
10648         return 0;
10649 }
10650
10651 static int i40e_get_regs(struct rte_eth_dev *dev,
10652                          struct rte_dev_reg_info *regs)
10653 {
10654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10655         uint32_t *ptr_data = regs->data;
10656         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10657         const struct i40e_reg_info *reg_info;
10658
10659         if (ptr_data == NULL) {
10660                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10661                 regs->width = sizeof(uint32_t);
10662                 return 0;
10663         }
10664
10665         /* The first few registers have to be read using AQ operations */
10666         reg_idx = 0;
10667         while (i40e_regs_adminq[reg_idx].name) {
10668                 reg_info = &i40e_regs_adminq[reg_idx++];
10669                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10670                         for (arr_idx2 = 0;
10671                                         arr_idx2 <= reg_info->count2;
10672                                         arr_idx2++) {
10673                                 reg_offset = arr_idx * reg_info->stride1 +
10674                                         arr_idx2 * reg_info->stride2;
10675                                 reg_offset += reg_info->base_addr;
10676                                 ptr_data[reg_offset >> 2] =
10677                                         i40e_read_rx_ctl(hw, reg_offset);
10678                         }
10679         }
10680
10681         /* The remaining registers can be read using primitives */
10682         reg_idx = 0;
10683         while (i40e_regs_others[reg_idx].name) {
10684                 reg_info = &i40e_regs_others[reg_idx++];
10685                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10686                         for (arr_idx2 = 0;
10687                                         arr_idx2 <= reg_info->count2;
10688                                         arr_idx2++) {
10689                                 reg_offset = arr_idx * reg_info->stride1 +
10690                                         arr_idx2 * reg_info->stride2;
10691                                 reg_offset += reg_info->base_addr;
10692                                 ptr_data[reg_offset >> 2] =
10693                                         I40E_READ_REG(hw, reg_offset);
10694                         }
10695         }
10696
10697         return 0;
10698 }
10699
10700 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10701 {
10702         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10703
10704         /* Convert word count to byte count */
10705         return hw->nvm.sr_size << 1;
10706 }
10707
10708 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10709                            struct rte_dev_eeprom_info *eeprom)
10710 {
10711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10712         uint16_t *data = eeprom->data;
10713         uint16_t offset, length, cnt_words;
10714         int ret_code;
10715
10716         offset = eeprom->offset >> 1;
10717         length = eeprom->length >> 1;
10718         cnt_words = length;
10719
10720         if (offset > hw->nvm.sr_size ||
10721                 offset + length > hw->nvm.sr_size) {
10722                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10723                 return -EINVAL;
10724         }
10725
10726         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10727
10728         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10729         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10730                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10731                 return -EIO;
10732         }
10733
10734         return 0;
10735 }
10736
10737 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10738                                       struct ether_addr *mac_addr)
10739 {
10740         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10741
10742         if (!is_valid_assigned_ether_addr(mac_addr)) {
10743                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10744                 return;
10745         }
10746
10747         /* Flags: 0x3 updates port address */
10748         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10749 }
10750
10751 static int
10752 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10753 {
10754         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10755         struct rte_eth_dev_data *dev_data = pf->dev_data;
10756         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10757         int ret = 0;
10758
10759         /* check if mtu is within the allowed range */
10760         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10761                 return -EINVAL;
10762
10763         /* mtu setting is forbidden if port is start */
10764         if (dev_data->dev_started) {
10765                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10766                             dev_data->port_id);
10767                 return -EBUSY;
10768         }
10769
10770         if (frame_size > ETHER_MAX_LEN)
10771                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10772         else
10773                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10774
10775         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10776
10777         return ret;
10778 }
10779
10780 /* Restore ethertype filter */
10781 static void
10782 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10783 {
10784         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10785         struct i40e_ethertype_filter_list
10786                 *ethertype_list = &pf->ethertype.ethertype_list;
10787         struct i40e_ethertype_filter *f;
10788         struct i40e_control_filter_stats stats;
10789         uint16_t flags;
10790
10791         TAILQ_FOREACH(f, ethertype_list, rules) {
10792                 flags = 0;
10793                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10794                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10795                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10796                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10797                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10798
10799                 memset(&stats, 0, sizeof(stats));
10800                 i40e_aq_add_rem_control_packet_filter(hw,
10801                                             f->input.mac_addr.addr_bytes,
10802                                             f->input.ether_type,
10803                                             flags, pf->main_vsi->seid,
10804                                             f->queue, 1, &stats, NULL);
10805         }
10806         PMD_DRV_LOG(INFO, "Ethertype filter:"
10807                     " mac_etype_used = %u, etype_used = %u,"
10808                     " mac_etype_free = %u, etype_free = %u",
10809                     stats.mac_etype_used, stats.etype_used,
10810                     stats.mac_etype_free, stats.etype_free);
10811 }
10812
10813 /* Restore tunnel filter */
10814 static void
10815 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10816 {
10817         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10818         struct i40e_vsi *vsi;
10819         struct i40e_pf_vf *vf;
10820         struct i40e_tunnel_filter_list
10821                 *tunnel_list = &pf->tunnel.tunnel_list;
10822         struct i40e_tunnel_filter *f;
10823         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10824         bool big_buffer = 0;
10825
10826         TAILQ_FOREACH(f, tunnel_list, rules) {
10827                 if (!f->is_to_vf)
10828                         vsi = pf->main_vsi;
10829                 else {
10830                         vf = &pf->vfs[f->vf_id];
10831                         vsi = vf->vsi;
10832                 }
10833                 memset(&cld_filter, 0, sizeof(cld_filter));
10834                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10835                         (struct ether_addr *)&cld_filter.element.outer_mac);
10836                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10837                         (struct ether_addr *)&cld_filter.element.inner_mac);
10838                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10839                 cld_filter.element.flags = f->input.flags;
10840                 cld_filter.element.tenant_id = f->input.tenant_id;
10841                 cld_filter.element.queue_number = f->queue;
10842                 rte_memcpy(cld_filter.general_fields,
10843                            f->input.general_fields,
10844                            sizeof(f->input.general_fields));
10845
10846                 if (((f->input.flags &
10847                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10848                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10849                     ((f->input.flags &
10850                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10851                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10852                     ((f->input.flags &
10853                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10854                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10855                         big_buffer = 1;
10856
10857                 if (big_buffer)
10858                         i40e_aq_add_cloud_filters_big_buffer(hw,
10859                                              vsi->seid, &cld_filter, 1);
10860                 else
10861                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10862                                                   &cld_filter.element, 1);
10863         }
10864 }
10865
10866 static void
10867 i40e_filter_restore(struct i40e_pf *pf)
10868 {
10869         i40e_ethertype_filter_restore(pf);
10870         i40e_tunnel_filter_restore(pf);
10871         i40e_fdir_filter_restore(pf);
10872 }
10873
10874 static bool
10875 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10876 {
10877         if (strcmp(dev->device->driver->name, drv->driver.name))
10878                 return false;
10879
10880         return true;
10881 }
10882
10883 bool
10884 is_i40e_supported(struct rte_eth_dev *dev)
10885 {
10886         return is_device_supported(dev, &rte_i40e_pmd);
10887 }
10888
10889 /* Create a QinQ cloud filter
10890  *
10891  * The Fortville NIC has limited resources for tunnel filters,
10892  * so we can only reuse existing filters.
10893  *
10894  * In step 1 we define which Field Vector fields can be used for
10895  * filter types.
10896  * As we do not have the inner tag defined as a field,
10897  * we have to define it first, by reusing one of L1 entries.
10898  *
10899  * In step 2 we are replacing one of existing filter types with
10900  * a new one for QinQ.
10901  * As we reusing L1 and replacing L2, some of the default filter
10902  * types will disappear,which depends on L1 and L2 entries we reuse.
10903  *
10904  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10905  *
10906  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10907  *              later when we define the cloud filter.
10908  *      a.      Valid_flags.replace_cloud = 0
10909  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10910  *      c.      New_filter = 0x10
10911  *      d.      TR bit = 0xff (optional, not used here)
10912  *      e.      Buffer – 2 entries:
10913  *              i.      Byte 0 = 8 (outer vlan FV index).
10914  *                      Byte 1 = 0 (rsv)
10915  *                      Byte 2-3 = 0x0fff
10916  *              ii.     Byte 0 = 37 (inner vlan FV index).
10917  *                      Byte 1 =0 (rsv)
10918  *                      Byte 2-3 = 0x0fff
10919  *
10920  * Step 2:
10921  * 2.   Create cloud filter using two L1 filters entries: stag and
10922  *              new filter(outer vlan+ inner vlan)
10923  *      a.      Valid_flags.replace_cloud = 1
10924  *      b.      Old_filter = 1 (instead of outer IP)
10925  *      c.      New_filter = 0x10
10926  *      d.      Buffer – 2 entries:
10927  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10928  *                      Byte 1-3 = 0 (rsv)
10929  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10930  *                      Byte 9-11 = 0 (rsv)
10931  */
10932 static int
10933 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10934 {
10935         int ret = -ENOTSUP;
10936         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10937         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10938         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10939
10940         /* Init */
10941         memset(&filter_replace, 0,
10942                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10943         memset(&filter_replace_buf, 0,
10944                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10945
10946         /* create L1 filter */
10947         filter_replace.old_filter_type =
10948                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10949         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10950         filter_replace.tr_bit = 0;
10951
10952         /* Prepare the buffer, 2 entries */
10953         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10954         filter_replace_buf.data[0] |=
10955                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10956         /* Field Vector 12b mask */
10957         filter_replace_buf.data[2] = 0xff;
10958         filter_replace_buf.data[3] = 0x0f;
10959         filter_replace_buf.data[4] =
10960                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10961         filter_replace_buf.data[4] |=
10962                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10963         /* Field Vector 12b mask */
10964         filter_replace_buf.data[6] = 0xff;
10965         filter_replace_buf.data[7] = 0x0f;
10966         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10967                         &filter_replace_buf);
10968         if (ret != I40E_SUCCESS)
10969                 return ret;
10970
10971         /* Apply the second L2 cloud filter */
10972         memset(&filter_replace, 0,
10973                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10974         memset(&filter_replace_buf, 0,
10975                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10976
10977         /* create L2 filter, input for L2 filter will be L1 filter  */
10978         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10979         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10980         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10981
10982         /* Prepare the buffer, 2 entries */
10983         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10984         filter_replace_buf.data[0] |=
10985                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10986         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10987         filter_replace_buf.data[4] |=
10988                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10989         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10990                         &filter_replace_buf);
10991         return ret;
10992 }
10993
10994 RTE_INIT(i40e_init_log);
10995 static void
10996 i40e_init_log(void)
10997 {
10998         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10999         if (i40e_logtype_init >= 0)
11000                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11001         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11002         if (i40e_logtype_driver >= 0)
11003                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11004 }