drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 /* Additional timesync values. */
 129 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 130 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 131 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 132 #define I40E_PRTTSYN_TSYNENA     0x80000000
 133 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 134 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffff
 135
 136 #define I40E_MAX_PERCENT            100
 137 #define I40E_DEFAULT_DCB_APP_NUM    1
 138 #define I40E_DEFAULT_DCB_APP_PRIO   3
 139
 140 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 141 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 143 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 144 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 145 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 146
 147 #define I40E_INSET_NONE            0x00000000000000000ULL
 148
 149 /* bit0 ~ bit 7 */
 150 #define I40E_INSET_DMAC            0x0000000000000001ULL
 151 #define I40E_INSET_SMAC            0x0000000000000002ULL
 152 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 153 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 154 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 155
 156 /* bit 8 ~ bit 15 */
 157 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 158 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 159 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 160 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 161 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 162 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 163 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 164
 165 /* bit 16 ~ bit 31 */
 166 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 167 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 168 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 169 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 170 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 171 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 172 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 173 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 174
 175 /* bit 32 ~ bit 47, tunnel fields */
 176 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 177 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 178 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 179 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 180 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 181 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 182
 183 /* bit 48 ~ bit 55 */
 184 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 185
 186 /* bit 56 ~ bit 63, Flex Payload */
 187 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 194 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 195 #define I40E_INSET_FLEX_PAYLOAD \
 196         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 197         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 198         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 199         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 200
 201 /**
 202  * Below are values for writing un-exposed registers suggested
 203  * by silicon experts
 204  */
 205 /* Destination MAC address */
 206 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 207 /* Source MAC address */
 208 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 209 /* VLAN tag in the outer L2 header */
 210 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 211 /* VLAN tag in the inner L2 header */
 212 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 213 /* Source IPv4 address */
 214 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 215 /* Destination IPv4 address */
 216 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 217 /* IPv4 Type of Service (TOS) */
 218 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 219 /* IPv4 Protocol */
 220 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 221 /* Source IPv6 address */
 222 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 223 /* Destination IPv6 address */
 224 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 225 /* IPv6 Traffic Class (TC) */
 226 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 227 /* IPv6 Next Header */
 228 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 229 /* Source L4 port */
 230 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 231 /* Destination L4 port */
 232 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 233 /* SCTP verification tag */
 234 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 235 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 236 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 237 /* Source port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 239 /* Destination port of tunneling UDP */
 240 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 241 /* UDP Tunneling ID, NVGRE/GRE key */
 242 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 243 /* Last ether type */
 244 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 245 /* Tunneling outer destination IPv4 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 247 /* Tunneling outer destination IPv6 address */
 248 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 249 /* 1st word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 251 /* 2nd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 253 /* 3rd word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 255 /* 4th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 257 /* 5th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 259 /* 6th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 261 /* 7th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 263 /* 8th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 265
 266 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 267
 268 #define I40E_TRANSLATE_INSET 0
 269 #define I40E_TRANSLATE_REG   1
 270
 271 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 272 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 274 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 275
 276 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 277 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 278 static int i40e_dev_configure(struct rte_eth_dev *dev);
 279 static int i40e_dev_start(struct rte_eth_dev *dev);
 280 static void i40e_dev_stop(struct rte_eth_dev *dev);
 281 static void i40e_dev_close(struct rte_eth_dev *dev);
 282 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 284 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 285 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 286 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 287 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 288 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_stats *stats);
 290 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 291                                struct rte_eth_xstats *xstats, unsigned n);
 292 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 293 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 294                                             uint16_t queue_id,
 295                                             uint8_t stat_idx,
 296                                             uint8_t is_rx);
 297 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 298                               struct rte_eth_dev_info *dev_info);
 299 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 300                                 uint16_t vlan_id,
 301                                 int on);
 302 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 303 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 304 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 305                                       uint16_t queue,
 306                                       int on);
 307 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 308 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 309 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 310 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 311                               struct rte_eth_fc_conf *fc_conf);
 312 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 313                               struct rte_eth_fc_conf *fc_conf);
 314 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 315                                        struct rte_eth_pfc_conf *pfc_conf);
 316 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 317                           struct ether_addr *mac_addr,
 318                           uint32_t index,
 319                           uint32_t pool);
 320 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 321 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 322                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 323                                     uint16_t reta_size);
 324 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 325                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 326                                    uint16_t reta_size);
 327
 328 static int i40e_get_cap(struct i40e_hw *hw);
 329 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 330 static int i40e_pf_setup(struct i40e_pf *pf);
 331 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 332 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 333 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 334 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 335 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 336                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 337 static void i40e_stat_update_48(struct i40e_hw *hw,
 338                                uint32_t hireg,
 339                                uint32_t loreg,
 340                                bool offset_loaded,
 341                                uint64_t *offset,
 342                                uint64_t *stat);
 343 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 344 static void i40e_dev_interrupt_handler(
 345                 __rte_unused struct rte_intr_handle *handle, void *param);
 346 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 347                                 uint32_t base, uint32_t num);
 348 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 349 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 350                         uint32_t base);
 351 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 352                         uint16_t num);
 353 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 354 static int i40e_veb_release(struct i40e_veb *veb);
 355 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 356                                                 struct i40e_vsi *vsi);
 357 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 358 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 359 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 360                                              struct i40e_macvlan_filter *mv_f,
 361                                              int num,
 362                                              struct ether_addr *addr);
 363 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 364                                              struct i40e_macvlan_filter *mv_f,
 365                                              int num,
 366                                              uint16_t vlan);
 367 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 368 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 369                                     struct rte_eth_rss_conf *rss_conf);
 370 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 371                                       struct rte_eth_rss_conf *rss_conf);
 372 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 373                                 struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 375                                 struct rte_eth_udp_tunnel *udp_tunnel);
 376 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 377                         struct rte_eth_ethertype_filter *filter,
 378                         bool add);
 379 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 380                                 enum rte_filter_op filter_op,
 381                                 void *arg);
 382 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 383                                 enum rte_filter_type filter_type,
 384                                 enum rte_filter_op filter_op,
 385                                 void *arg);
 386 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 387                                   struct rte_eth_dcb_info *dcb_info);
 388 static void i40e_configure_registers(struct i40e_hw *hw);
 389 static void i40e_hw_init(struct i40e_hw *hw);
 390 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 391 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 392                         struct rte_eth_mirror_conf *mirror_conf,
 393                         uint8_t sw_id, uint8_t on);
 394 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 395
 396 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 397 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 398 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 399                                            struct timespec *timestamp,
 400                                            uint32_t flags);
 401 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 402                                            struct timespec *timestamp);
 403 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 404
 405 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 406
 407 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 408                                    struct timespec *timestamp);
 409 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 410                                     const struct timespec *timestamp);
 411
 412 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 413                                          uint16_t queue_id);
 414 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 415                                           uint16_t queue_id);
 416
 417
 418 static const struct rte_pci_id pci_id_i40e_map[] = {
 419 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 420 #include "rte_pci_dev_ids.h"
 421 { .vendor_id = 0, /* sentinel */ },
 422 };
 423
 424 static const struct eth_dev_ops i40e_eth_dev_ops = {
 425         .dev_configure                = i40e_dev_configure,
 426         .dev_start                    = i40e_dev_start,
 427         .dev_stop                     = i40e_dev_stop,
 428         .dev_close                    = i40e_dev_close,
 429         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 430         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 431         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 432         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 433         .dev_set_link_up              = i40e_dev_set_link_up,
 434         .dev_set_link_down            = i40e_dev_set_link_down,
 435         .link_update                  = i40e_dev_link_update,
 436         .stats_get                    = i40e_dev_stats_get,
 437         .xstats_get                   = i40e_dev_xstats_get,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .dev_infos_get                = i40e_dev_info_get,
 442         .vlan_filter_set              = i40e_vlan_filter_set,
 443         .vlan_tpid_set                = i40e_vlan_tpid_set,
 444         .vlan_offload_set             = i40e_vlan_offload_set,
 445         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 446         .vlan_pvid_set                = i40e_vlan_pvid_set,
 447         .rx_queue_start               = i40e_dev_rx_queue_start,
 448         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 449         .tx_queue_start               = i40e_dev_tx_queue_start,
 450         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 451         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 452         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 453         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 454         .rx_queue_release             = i40e_dev_rx_queue_release,
 455         .rx_queue_count               = i40e_dev_rx_queue_count,
 456         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 457         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 458         .tx_queue_release             = i40e_dev_tx_queue_release,
 459         .dev_led_on                   = i40e_dev_led_on,
 460         .dev_led_off                  = i40e_dev_led_off,
 461         .flow_ctrl_get                = i40e_flow_ctrl_get,
 462         .flow_ctrl_set                = i40e_flow_ctrl_set,
 463         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 464         .mac_addr_add                 = i40e_macaddr_add,
 465         .mac_addr_remove              = i40e_macaddr_remove,
 466         .reta_update                  = i40e_dev_rss_reta_update,
 467         .reta_query                   = i40e_dev_rss_reta_query,
 468         .rss_hash_update              = i40e_dev_rss_hash_update,
 469         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 470         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 471         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 472         .filter_ctrl                  = i40e_dev_filter_ctrl,
 473         .rxq_info_get                 = i40e_rxq_info_get,
 474         .txq_info_get                 = i40e_txq_info_get,
 475         .mirror_rule_set              = i40e_mirror_rule_set,
 476         .mirror_rule_reset            = i40e_mirror_rule_reset,
 477         .timesync_enable              = i40e_timesync_enable,
 478         .timesync_disable             = i40e_timesync_disable,
 479         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 480         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 481         .get_dcb_info                 = i40e_dev_get_dcb_info,
 482         .timesync_adjust_time         = i40e_timesync_adjust_time,
 483         .timesync_read_time           = i40e_timesync_read_time,
 484         .timesync_write_time          = i40e_timesync_write_time,
 485 };
 486
 487 /* store statistics names and its offset in stats structure */
 488 struct rte_i40e_xstats_name_off {
 489         char name[RTE_ETH_XSTATS_NAME_SIZE];
 490         unsigned offset;
 491 };
 492
 493 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 494         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 495         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 496         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 497         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 498         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 499                 rx_unknown_protocol)},
 500         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 501         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 502         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 503         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 504 };
 505
 506 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 507                 sizeof(rte_i40e_stats_strings[0]))
 508
 509 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 510         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 511                 tx_dropped_link_down)},
 512         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 513         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 514                 illegal_bytes)},
 515         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 516         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 517                 mac_local_faults)},
 518         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 519                 mac_remote_faults)},
 520         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 521                 rx_length_errors)},
 522         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 523         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 524         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 525         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 526         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 527         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 528                 rx_size_127)},
 529         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 530                 rx_size_255)},
 531         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 532                 rx_size_511)},
 533         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 534                 rx_size_1023)},
 535         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 536                 rx_size_1522)},
 537         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_big)},
 539         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 540                 rx_undersize)},
 541         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 542                 rx_oversize)},
 543         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 544                 mac_short_packet_dropped)},
 545         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 546                 rx_fragments)},
 547         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 548         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 549         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 550                 tx_size_127)},
 551         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 552                 tx_size_255)},
 553         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 554                 tx_size_511)},
 555         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 556                 tx_size_1023)},
 557         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 558                 tx_size_1522)},
 559         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_big)},
 561         {"rx_flow_director_atr_match_packets",
 562                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 563         {"rx_flow_director_sb_match_packets",
 564                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 565         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 566                 tx_lpi_status)},
 567         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 568                 rx_lpi_status)},
 569         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 570                 tx_lpi_count)},
 571         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 572                 rx_lpi_count)},
 573 };
 574
 575 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 576                 sizeof(rte_i40e_hw_port_strings[0]))
 577
 578 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 579         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 580                 priority_xon_rx)},
 581         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 582                 priority_xoff_rx)},
 583 };
 584
 585 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 586                 sizeof(rte_i40e_rxq_prio_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_tx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_tx)},
 593         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 594                 priority_xon_2_xoff)},
 595 };
 596
 597 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 598                 sizeof(rte_i40e_txq_prio_strings[0]))
 599
 600 static struct eth_driver rte_i40e_pmd = {
 601         .pci_drv = {
 602                 .name = "rte_i40e_pmd",
 603                 .id_table = pci_id_i40e_map,
 604                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 605                         RTE_PCI_DRV_DETACHABLE,
 606         },
 607         .eth_dev_init = eth_i40e_dev_init,
 608         .eth_dev_uninit = eth_i40e_dev_uninit,
 609         .dev_private_size = sizeof(struct i40e_adapter),
 610 };
 611
 612 static inline int
 613 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 614                                      struct rte_eth_link *link)
 615 {
 616         struct rte_eth_link *dst = link;
 617         struct rte_eth_link *src = &(dev->data->dev_link);
 618
 619         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 620                                         *(uint64_t *)src) == 0)
 621                 return -1;
 622
 623         return 0;
 624 }
 625
 626 static inline int
 627 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 628                                       struct rte_eth_link *link)
 629 {
 630         struct rte_eth_link *dst = &(dev->data->dev_link);
 631         struct rte_eth_link *src = link;
 632
 633         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 634                                         *(uint64_t *)src) == 0)
 635                 return -1;
 636
 637         return 0;
 638 }
 639
 640 /*
 641  * Driver initialization routine.
 642  * Invoked once at EAL init time.
 643  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 644  */
 645 static int
 646 rte_i40e_pmd_init(const char *name __rte_unused,
 647                   const char *params __rte_unused)
 648 {
 649         PMD_INIT_FUNC_TRACE();
 650         rte_eth_driver_register(&rte_i40e_pmd);
 651
 652         return 0;
 653 }
 654
 655 static struct rte_driver rte_i40e_driver = {
 656         .type = PMD_PDEV,
 657         .init = rte_i40e_pmd_init,
 658 };
 659
 660 PMD_REGISTER_DRIVER(rte_i40e_driver);
 661
 662 /*
 663  * Initialize registers for flexible payload, which should be set by NVM.
 664  * This should be removed from code once it is fixed in NVM.
 665  */
 666 #ifndef I40E_GLQF_ORT
 667 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 668 #endif
 669 #ifndef I40E_GLQF_PIT
 670 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 671 #endif
 672
 673 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 674 {
 675         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 676         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 677         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 678         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 679         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 680         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 681         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 682         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 683         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 684         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 685
 686         /* GLQF_PIT Registers */
 687         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 688         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 689 }
 690
 691 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 692
 693 /*
 694  * Add a ethertype filter to drop all flow control frames transmitted
 695  * from VSIs.
 696 */
 697 static void
 698 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 699 {
 700         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 701         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 702                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 703                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 704         int ret;
 705
 706         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 707                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 708                                 pf->main_vsi_seid, 0,
 709                                 TRUE, NULL, NULL);
 710         if (ret)
 711                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 712                                   " frames from VSIs.");
 713 }
 714
 715 static int
 716 eth_i40e_dev_init(struct rte_eth_dev *dev)
 717 {
 718         struct rte_pci_device *pci_dev;
 719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 721         struct i40e_vsi *vsi;
 722         int ret;
 723         uint32_t len;
 724         uint8_t aq_fail = 0;
 725
 726         PMD_INIT_FUNC_TRACE();
 727
 728         dev->dev_ops = &i40e_eth_dev_ops;
 729         dev->rx_pkt_burst = i40e_recv_pkts;
 730         dev->tx_pkt_burst = i40e_xmit_pkts;
 731
 732         /* for secondary processes, we don't initialise any further as primary
 733          * has already done this work. Only check we don't need a different
 734          * RX function */
 735         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 736                 i40e_set_rx_function(dev);
 737                 i40e_set_tx_function(dev);
 738                 return 0;
 739         }
 740         pci_dev = dev->pci_dev;
 741
 742         rte_eth_copy_pci_info(dev, pci_dev);
 743
 744         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 745         pf->adapter->eth_dev = dev;
 746         pf->dev_data = dev->data;
 747
 748         hw->back = I40E_PF_TO_ADAPTER(pf);
 749         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 750         if (!hw->hw_addr) {
 751                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 752                              "as address is NULL");
 753                 return -ENODEV;
 754         }
 755
 756         hw->vendor_id = pci_dev->id.vendor_id;
 757         hw->device_id = pci_dev->id.device_id;
 758         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 759         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 760         hw->bus.device = pci_dev->addr.devid;
 761         hw->bus.func = pci_dev->addr.function;
 762         hw->adapter_stopped = 0;
 763
 764         /* Make sure all is clean before doing PF reset */
 765         i40e_clear_hw(hw);
 766
 767         /* Initialize the hardware */
 768         i40e_hw_init(hw);
 769
 770         /* Reset here to make sure all is clean for each PF */
 771         ret = i40e_pf_reset(hw);
 772         if (ret) {
 773                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 774                 return ret;
 775         }
 776
 777         /* Initialize the shared code (base driver) */
 778         ret = i40e_init_shared_code(hw);
 779         if (ret) {
 780                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 781                 return ret;
 782         }
 783
 784         /*
 785          * To work around the NVM issue,initialize registers
 786          * for flexible payload by software.
 787          * It should be removed once issues are fixed in NVM.
 788          */
 789         i40e_flex_payload_reg_init(hw);
 790
 791         /* Initialize the parameters for adminq */
 792         i40e_init_adminq_parameter(hw);
 793         ret = i40e_init_adminq(hw);
 794         if (ret != I40E_SUCCESS) {
 795                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 796                 return -EIO;
 797         }
 798         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 799                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 800                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 801                      ((hw->nvm.version >> 12) & 0xf),
 802                      ((hw->nvm.version >> 4) & 0xff),
 803                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 804
 805         /* Clear PXE mode */
 806         i40e_clear_pxe_mode(hw);
 807
 808         /*
 809          * On X710, performance number is far from the expectation on recent
 810          * firmware versions. The fix for this issue may not be integrated in
 811          * the following firmware version. So the workaround in software driver
 812          * is needed. It needs to modify the initial values of 3 internal only
 813          * registers. Note that the workaround can be removed when it is fixed
 814          * in firmware in the future.
 815          */
 816         i40e_configure_registers(hw);
 817
 818         /* Get hw capabilities */
 819         ret = i40e_get_cap(hw);
 820         if (ret != I40E_SUCCESS) {
 821                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 822                 goto err_get_capabilities;
 823         }
 824
 825         /* Initialize parameters for PF */
 826         ret = i40e_pf_parameter_init(dev);
 827         if (ret != 0) {
 828                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 829                 goto err_parameter_init;
 830         }
 831
 832         /* Initialize the queue management */
 833         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 834         if (ret < 0) {
 835                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 836                 goto err_qp_pool_init;
 837         }
 838         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 839                                 hw->func_caps.num_msix_vectors - 1);
 840         if (ret < 0) {
 841                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 842                 goto err_msix_pool_init;
 843         }
 844
 845         /* Initialize lan hmc */
 846         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 847                                 hw->func_caps.num_rx_qp, 0, 0);
 848         if (ret != I40E_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 850                 goto err_init_lan_hmc;
 851         }
 852
 853         /* Configure lan hmc */
 854         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 855         if (ret != I40E_SUCCESS) {
 856                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 857                 goto err_configure_lan_hmc;
 858         }
 859
 860         /* Get and check the mac address */
 861         i40e_get_mac_addr(hw, hw->mac.addr);
 862         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 863                 PMD_INIT_LOG(ERR, "mac address is not valid");
 864                 ret = -EIO;
 865                 goto err_get_mac_addr;
 866         }
 867         /* Copy the permanent MAC address */
 868         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 869                         (struct ether_addr *) hw->mac.perm_addr);
 870
 871         /* Disable flow control */
 872         hw->fc.requested_mode = I40E_FC_NONE;
 873         i40e_set_fc(hw, &aq_fail, TRUE);
 874
 875         /* PF setup, which includes VSI setup */
 876         ret = i40e_pf_setup(pf);
 877         if (ret) {
 878                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 879                 goto err_setup_pf_switch;
 880         }
 881
 882         vsi = pf->main_vsi;
 883
 884         /* Disable double vlan by default */
 885         i40e_vsi_config_double_vlan(vsi, FALSE);
 886
 887         if (!vsi->max_macaddrs)
 888                 len = ETHER_ADDR_LEN;
 889         else
 890                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 891
 892         /* Should be after VSI initialized */
 893         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 894         if (!dev->data->mac_addrs) {
 895                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 896                                         "for storing mac address");
 897                 goto err_mac_alloc;
 898         }
 899         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 900                                         &dev->data->mac_addrs[0]);
 901
 902         /* initialize pf host driver to setup SRIOV resource if applicable */
 903         i40e_pf_host_init(dev);
 904
 905         /* register callback func to eal lib */
 906         rte_intr_callback_register(&(pci_dev->intr_handle),
 907                 i40e_dev_interrupt_handler, (void *)dev);
 908
 909         /* configure and enable device interrupt */
 910         i40e_pf_config_irq0(hw, TRUE);
 911         i40e_pf_enable_irq0(hw);
 912
 913         /* enable uio intr after callback register */
 914         rte_intr_enable(&(pci_dev->intr_handle));
 915         /*
 916          * Add an ethertype filter to drop all flow control frames transmitted
 917          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 918          * frames to wire.
 919          */
 920         i40e_add_tx_flow_control_drop_filter(pf);
 921
 922         /* initialize mirror rule list */
 923         TAILQ_INIT(&pf->mirror_list);
 924
 925         /* Init dcb to sw mode by default */
 926         ret = i40e_dcb_init_configure(dev, TRUE);
 927         if (ret != I40E_SUCCESS) {
 928                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 929                 pf->flags &= ~I40E_FLAG_DCB;
 930         }
 931
 932         return 0;
 933
 934 err_mac_alloc:
 935         i40e_vsi_release(pf->main_vsi);
 936 err_setup_pf_switch:
 937 err_get_mac_addr:
 938 err_configure_lan_hmc:
 939         (void)i40e_shutdown_lan_hmc(hw);
 940 err_init_lan_hmc:
 941         i40e_res_pool_destroy(&pf->msix_pool);
 942 err_msix_pool_init:
 943         i40e_res_pool_destroy(&pf->qp_pool);
 944 err_qp_pool_init:
 945 err_parameter_init:
 946 err_get_capabilities:
 947         (void)i40e_shutdown_adminq(hw);
 948
 949         return ret;
 950 }
 951
 952 static int
 953 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 954 {
 955         struct rte_pci_device *pci_dev;
 956         struct i40e_hw *hw;
 957         struct i40e_filter_control_settings settings;
 958         int ret;
 959         uint8_t aq_fail = 0;
 960
 961         PMD_INIT_FUNC_TRACE();
 962
 963         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 964                 return 0;
 965
 966         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 967         pci_dev = dev->pci_dev;
 968
 969         if (hw->adapter_stopped == 0)
 970                 i40e_dev_close(dev);
 971
 972         dev->dev_ops = NULL;
 973         dev->rx_pkt_burst = NULL;
 974         dev->tx_pkt_burst = NULL;
 975
 976         /* Disable LLDP */
 977         ret = i40e_aq_stop_lldp(hw, true, NULL);
 978         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 979                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 980
 981         /* Clear PXE mode */
 982         i40e_clear_pxe_mode(hw);
 983
 984         /* Unconfigure filter control */
 985         memset(&settings, 0, sizeof(settings));
 986         ret = i40e_set_filter_control(hw, &settings);
 987         if (ret)
 988                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 989                                         ret);
 990
 991         /* Disable flow control */
 992         hw->fc.requested_mode = I40E_FC_NONE;
 993         i40e_set_fc(hw, &aq_fail, TRUE);
 994
 995         /* uninitialize pf host driver */
 996         i40e_pf_host_uninit(dev);
 997
 998         rte_free(dev->data->mac_addrs);
 999         dev->data->mac_addrs = NULL;
1000
1001         /* disable uio intr before callback unregister */
1002         rte_intr_disable(&(pci_dev->intr_handle));
1003
1004         /* register callback func to eal lib */
1005         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1006                 i40e_dev_interrupt_handler, (void *)dev);
1007
1008         return 0;
1009 }
1010
1011 static int
1012 i40e_dev_configure(struct rte_eth_dev *dev)
1013 {
1014         struct i40e_adapter *ad =
1015                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1018         int i, ret;
1019
1020         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1021          * bulk allocation or vector Rx preconditions we will reset it.
1022          */
1023         ad->rx_bulk_alloc_allowed = true;
1024         ad->rx_vec_allowed = true;
1025         ad->tx_simple_allowed = true;
1026         ad->tx_vec_allowed = true;
1027
1028         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1029                 ret = i40e_fdir_setup(pf);
1030                 if (ret != I40E_SUCCESS) {
1031                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1032                         return -ENOTSUP;
1033                 }
1034                 ret = i40e_fdir_configure(dev);
1035                 if (ret < 0) {
1036                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1037                         goto err;
1038                 }
1039         } else
1040                 i40e_fdir_teardown(pf);
1041
1042         ret = i40e_dev_init_vlan(dev);
1043         if (ret < 0)
1044                 goto err;
1045
1046         /* VMDQ setup.
1047          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1048          *  RSS setting have different requirements.
1049          *  General PMD driver call sequence are NIC init, configure,
1050          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1051          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1052          *  applicable. So, VMDQ setting has to be done before
1053          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1054          *  For RSS setting, it will try to calculate actual configured RX queue
1055          *  number, which will be available after rx_queue_setup(). dev_start()
1056          *  function is good to place RSS setup.
1057          */
1058         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1059                 ret = i40e_vmdq_setup(dev);
1060                 if (ret)
1061                         goto err;
1062         }
1063
1064         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1065                 ret = i40e_dcb_setup(dev);
1066                 if (ret) {
1067                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1068                         goto err_dcb;
1069                 }
1070         }
1071
1072         return 0;
1073
1074 err_dcb:
1075         /* need to release vmdq resource if exists */
1076         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1077                 i40e_vsi_release(pf->vmdq[i].vsi);
1078                 pf->vmdq[i].vsi = NULL;
1079         }
1080         rte_free(pf->vmdq);
1081         pf->vmdq = NULL;
1082 err:
1083         /* need to release fdir resource if exists */
1084         i40e_fdir_teardown(pf);
1085         return ret;
1086 }
1087
1088 void
1089 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1090 {
1091         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1092         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1093         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1094         uint16_t msix_vect = vsi->msix_intr;
1095         uint16_t i;
1096
1097         for (i = 0; i < vsi->nb_qps; i++) {
1098                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1099                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1100                 rte_wmb();
1101         }
1102
1103         if (vsi->type != I40E_VSI_SRIOV) {
1104                 if (!rte_intr_allow_others(intr_handle)) {
1105                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1106                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1107                         I40E_WRITE_REG(hw,
1108                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1109                                        0);
1110                 } else {
1111                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1112                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1113                         I40E_WRITE_REG(hw,
1114                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1115                                                        msix_vect - 1), 0);
1116                 }
1117         } else {
1118                 uint32_t reg;
1119                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1120                         vsi->user_param + (msix_vect - 1);
1121
1122                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1123                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1124         }
1125         I40E_WRITE_FLUSH(hw);
1126 }
1127
1128 static void
1129 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1130                        int base_queue, int nb_queue)
1131 {
1132         int i;
1133         uint32_t val;
1134         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1135
1136         /* Bind all RX queues to allocated MSIX interrupt */
1137         for (i = 0; i < nb_queue; i++) {
1138                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1139                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1140                         ((base_queue + i + 1) <<
1141                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1142                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1143                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1144
1145                 if (i == nb_queue - 1)
1146                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1147                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1148         }
1149
1150         /* Write first RX queue to Link list register as the head element */
1151         if (vsi->type != I40E_VSI_SRIOV) {
1152                 uint16_t interval =
1153                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1154
1155                 if (msix_vect == I40E_MISC_VEC_ID) {
1156                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1157                                        (base_queue <<
1158                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1159                                        (0x0 <<
1160                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1161                         I40E_WRITE_REG(hw,
1162                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1163                                        interval);
1164                 } else {
1165                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1166                                        (base_queue <<
1167                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1168                                        (0x0 <<
1169                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1170                         I40E_WRITE_REG(hw,
1171                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1172                                                        msix_vect - 1),
1173                                        interval);
1174                 }
1175         } else {
1176                 uint32_t reg;
1177
1178                 if (msix_vect == I40E_MISC_VEC_ID) {
1179                         I40E_WRITE_REG(hw,
1180                                        I40E_VPINT_LNKLST0(vsi->user_param),
1181                                        (base_queue <<
1182                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1183                                        (0x0 <<
1184                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1185                 } else {
1186                         /* num_msix_vectors_vf needs to minus irq0 */
1187                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1188                                 vsi->user_param + (msix_vect - 1);
1189
1190                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1191                                        (base_queue <<
1192                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1193                                        (0x0 <<
1194                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1195                 }
1196         }
1197
1198         I40E_WRITE_FLUSH(hw);
1199 }
1200
1201 void
1202 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1203 {
1204         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1205         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1207         uint16_t msix_vect = vsi->msix_intr;
1208         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1209         uint16_t queue_idx = 0;
1210         int record = 0;
1211         uint32_t val;
1212         int i;
1213
1214         for (i = 0; i < vsi->nb_qps; i++) {
1215                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1216                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1217         }
1218
1219         /* INTENA flag is not auto-cleared for interrupt */
1220         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1221         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1222                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1223                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1224         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1225
1226         /* VF bind interrupt */
1227         if (vsi->type == I40E_VSI_SRIOV) {
1228                 __vsi_queues_bind_intr(vsi, msix_vect,
1229                                        vsi->base_queue, vsi->nb_qps);
1230                 return;
1231         }
1232
1233         /* PF & VMDq bind interrupt */
1234         if (rte_intr_dp_is_en(intr_handle)) {
1235                 if (vsi->type == I40E_VSI_MAIN) {
1236                         queue_idx = 0;
1237                         record = 1;
1238                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1239                         struct i40e_vsi *main_vsi =
1240                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1241                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1242                         record = 1;
1243                 }
1244         }
1245
1246         for (i = 0; i < vsi->nb_used_qps; i++) {
1247                 if (nb_msix <= 1) {
1248                         if (!rte_intr_allow_others(intr_handle))
1249                                 /* allow to share MISC_VEC_ID */
1250                                 msix_vect = I40E_MISC_VEC_ID;
1251
1252                         /* no enough msix_vect, map all to one */
1253                         __vsi_queues_bind_intr(vsi, msix_vect,
1254                                                vsi->base_queue + i,
1255                                                vsi->nb_used_qps - i);
1256                         for (; !!record && i < vsi->nb_used_qps; i++)
1257                                 intr_handle->intr_vec[queue_idx + i] =
1258                                         msix_vect;
1259                         break;
1260                 }
1261                 /* 1:1 queue/msix_vect mapping */
1262                 __vsi_queues_bind_intr(vsi, msix_vect,
1263                                        vsi->base_queue + i, 1);
1264                 if (!!record)
1265                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1266
1267                 msix_vect++;
1268                 nb_msix--;
1269         }
1270 }
1271
1272 static void
1273 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1274 {
1275         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1276         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1278         uint16_t interval = i40e_calc_itr_interval(\
1279                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1280         uint16_t msix_intr, i;
1281
1282         if (rte_intr_allow_others(intr_handle))
1283                 for (i = 0; i < vsi->nb_msix; i++) {
1284                         msix_intr = vsi->msix_intr + i;
1285                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1286                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1287                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1288                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1289                                 (interval <<
1290                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1291                 }
1292         else
1293                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1294                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1295                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1296                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1297                                (interval <<
1298                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1299
1300         I40E_WRITE_FLUSH(hw);
1301 }
1302
1303 static void
1304 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1305 {
1306         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1307         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1308         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1309         uint16_t msix_intr, i;
1310
1311         if (rte_intr_allow_others(intr_handle))
1312                 for (i = 0; i < vsi->nb_msix; i++) {
1313                         msix_intr = vsi->msix_intr + i;
1314                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1315                                        0);
1316                 }
1317         else
1318                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1319
1320         I40E_WRITE_FLUSH(hw);
1321 }
1322
1323 static inline uint8_t
1324 i40e_parse_link_speed(uint16_t eth_link_speed)
1325 {
1326         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1327
1328         switch (eth_link_speed) {
1329         case ETH_LINK_SPEED_40G:
1330                 link_speed = I40E_LINK_SPEED_40GB;
1331                 break;
1332         case ETH_LINK_SPEED_20G:
1333                 link_speed = I40E_LINK_SPEED_20GB;
1334                 break;
1335         case ETH_LINK_SPEED_10G:
1336                 link_speed = I40E_LINK_SPEED_10GB;
1337                 break;
1338         case ETH_LINK_SPEED_1000:
1339                 link_speed = I40E_LINK_SPEED_1GB;
1340                 break;
1341         case ETH_LINK_SPEED_100:
1342                 link_speed = I40E_LINK_SPEED_100MB;
1343                 break;
1344         }
1345
1346         return link_speed;
1347 }
1348
1349 static int
1350 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1351                    __rte_unused uint8_t abilities,
1352                    __rte_unused uint8_t force_speed)
1353 {
1354         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1355          * for the link control limitation of that all link control should be
1356          * handled by firmware. It should follow up if link control will be
1357          * opened to software driver in future firmware versions.
1358          */
1359         return I40E_SUCCESS;
1360 }
1361
1362 static int
1363 i40e_apply_link_speed(struct rte_eth_dev *dev)
1364 {
1365         uint8_t speed;
1366         uint8_t abilities = 0;
1367         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1368         struct rte_eth_conf *conf = &dev->data->dev_conf;
1369
1370         speed = i40e_parse_link_speed(conf->link_speed);
1371         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1372         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1373                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1374         else
1375                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1376
1377         return i40e_phy_conf_link(hw, abilities, speed);
1378 }
1379
1380 static int
1381 i40e_dev_start(struct rte_eth_dev *dev)
1382 {
1383         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1384         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1385         struct i40e_vsi *main_vsi = pf->main_vsi;
1386         int ret, i;
1387         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1388         uint32_t intr_vector = 0;
1389
1390         hw->adapter_stopped = 0;
1391
1392         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1393                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1394                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1395                              dev->data->dev_conf.link_duplex,
1396                              dev->data->port_id);
1397                 return -EINVAL;
1398         }
1399
1400         rte_intr_disable(intr_handle);
1401
1402         if ((rte_intr_cap_multiple(intr_handle) ||
1403              !RTE_ETH_DEV_SRIOV(dev).active) &&
1404             dev->data->dev_conf.intr_conf.rxq != 0) {
1405                 intr_vector = dev->data->nb_rx_queues;
1406                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1407                         return -1;
1408         }
1409
1410         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1411                 intr_handle->intr_vec =
1412                         rte_zmalloc("intr_vec",
1413                                     dev->data->nb_rx_queues * sizeof(int),
1414                                     0);
1415                 if (!intr_handle->intr_vec) {
1416                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1417                                      " intr_vec\n", dev->data->nb_rx_queues);
1418                         return -ENOMEM;
1419                 }
1420         }
1421
1422         /* Initialize VSI */
1423         ret = i40e_dev_rxtx_init(pf);
1424         if (ret != I40E_SUCCESS) {
1425                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1426                 goto err_up;
1427         }
1428
1429         /* Map queues with MSIX interrupt */
1430         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1431                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1432         i40e_vsi_queues_bind_intr(main_vsi);
1433         i40e_vsi_enable_queues_intr(main_vsi);
1434
1435         /* Map VMDQ VSI queues with MSIX interrupt */
1436         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1437                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1438                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1439                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1440         }
1441
1442         /* enable FDIR MSIX interrupt */
1443         if (pf->fdir.fdir_vsi) {
1444                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1445                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1446         }
1447
1448         /* Enable all queues which have been configured */
1449         ret = i40e_dev_switch_queues(pf, TRUE);
1450         if (ret != I40E_SUCCESS) {
1451                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1452                 goto err_up;
1453         }
1454
1455         /* Enable receiving broadcast packets */
1456         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1457         if (ret != I40E_SUCCESS)
1458                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1459
1460         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1461                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1462                                                 true, NULL);
1463                 if (ret != I40E_SUCCESS)
1464                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1465         }
1466
1467         /* Apply link configure */
1468         ret = i40e_apply_link_speed(dev);
1469         if (I40E_SUCCESS != ret) {
1470                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1471                 goto err_up;
1472         }
1473
1474         if (!rte_intr_allow_others(intr_handle)) {
1475                 rte_intr_callback_unregister(intr_handle,
1476                                              i40e_dev_interrupt_handler,
1477                                              (void *)dev);
1478                 /* configure and enable device interrupt */
1479                 i40e_pf_config_irq0(hw, FALSE);
1480                 i40e_pf_enable_irq0(hw);
1481
1482                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1483                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1484                                      " no intr multiplex\n");
1485         }
1486
1487         /* enable uio intr after callback register */
1488         rte_intr_enable(intr_handle);
1489
1490         return I40E_SUCCESS;
1491
1492 err_up:
1493         i40e_dev_switch_queues(pf, FALSE);
1494         i40e_dev_clear_queues(dev);
1495
1496         return ret;
1497 }
1498
1499 static void
1500 i40e_dev_stop(struct rte_eth_dev *dev)
1501 {
1502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1503         struct i40e_vsi *main_vsi = pf->main_vsi;
1504         struct i40e_mirror_rule *p_mirror;
1505         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1506         int i;
1507
1508         /* Disable all queues */
1509         i40e_dev_switch_queues(pf, FALSE);
1510
1511         /* un-map queues with interrupt registers */
1512         i40e_vsi_disable_queues_intr(main_vsi);
1513         i40e_vsi_queues_unbind_intr(main_vsi);
1514
1515         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1516                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1517                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1518         }
1519
1520         if (pf->fdir.fdir_vsi) {
1521                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1522                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1523         }
1524         /* Clear all queues and release memory */
1525         i40e_dev_clear_queues(dev);
1526
1527         /* Set link down */
1528         i40e_dev_set_link_down(dev);
1529
1530         /* Remove all mirror rules */
1531         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1532                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1533                 rte_free(p_mirror);
1534         }
1535         pf->nb_mirror_rule = 0;
1536
1537         if (!rte_intr_allow_others(intr_handle))
1538                 /* resume to the default handler */
1539                 rte_intr_callback_register(intr_handle,
1540                                            i40e_dev_interrupt_handler,
1541                                            (void *)dev);
1542
1543         /* Clean datapath event and queue/vec mapping */
1544         rte_intr_efd_disable(intr_handle);
1545         if (intr_handle->intr_vec) {
1546                 rte_free(intr_handle->intr_vec);
1547                 intr_handle->intr_vec = NULL;
1548         }
1549 }
1550
1551 static void
1552 i40e_dev_close(struct rte_eth_dev *dev)
1553 {
1554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1556         uint32_t reg;
1557         int i;
1558
1559         PMD_INIT_FUNC_TRACE();
1560
1561         i40e_dev_stop(dev);
1562         hw->adapter_stopped = 1;
1563         i40e_dev_free_queues(dev);
1564
1565         /* Disable interrupt */
1566         i40e_pf_disable_irq0(hw);
1567         rte_intr_disable(&(dev->pci_dev->intr_handle));
1568
1569         /* shutdown and destroy the HMC */
1570         i40e_shutdown_lan_hmc(hw);
1571
1572         /* release all the existing VSIs and VEBs */
1573         i40e_fdir_teardown(pf);
1574         i40e_vsi_release(pf->main_vsi);
1575
1576         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1577                 i40e_vsi_release(pf->vmdq[i].vsi);
1578                 pf->vmdq[i].vsi = NULL;
1579         }
1580
1581         rte_free(pf->vmdq);
1582         pf->vmdq = NULL;
1583
1584         /* shutdown the adminq */
1585         i40e_aq_queue_shutdown(hw, true);
1586         i40e_shutdown_adminq(hw);
1587
1588         i40e_res_pool_destroy(&pf->qp_pool);
1589         i40e_res_pool_destroy(&pf->msix_pool);
1590
1591         /* force a PF reset to clean anything leftover */
1592         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1593         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1594                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1595         I40E_WRITE_FLUSH(hw);
1596 }
1597
1598 static void
1599 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1600 {
1601         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1602         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603         struct i40e_vsi *vsi = pf->main_vsi;
1604         int status;
1605
1606         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1607                                                         true, NULL);
1608         if (status != I40E_SUCCESS)
1609                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1610
1611         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1612                                                         TRUE, NULL);
1613         if (status != I40E_SUCCESS)
1614                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1615
1616 }
1617
1618 static void
1619 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1620 {
1621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1622         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         struct i40e_vsi *vsi = pf->main_vsi;
1624         int status;
1625
1626         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1627                                                         false, NULL);
1628         if (status != I40E_SUCCESS)
1629                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1630
1631         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1632                                                         false, NULL);
1633         if (status != I40E_SUCCESS)
1634                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1635 }
1636
1637 static void
1638 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1639 {
1640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1642         struct i40e_vsi *vsi = pf->main_vsi;
1643         int ret;
1644
1645         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1646         if (ret != I40E_SUCCESS)
1647                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1648 }
1649
1650 static void
1651 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1652 {
1653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1655         struct i40e_vsi *vsi = pf->main_vsi;
1656         int ret;
1657
1658         if (dev->data->promiscuous == 1)
1659                 return; /* must remain in all_multicast mode */
1660
1661         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1662                                 vsi->seid, FALSE, NULL);
1663         if (ret != I40E_SUCCESS)
1664                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1665 }
1666
1667 /*
1668  * Set device link up.
1669  */
1670 static int
1671 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1672 {
1673         /* re-apply link speed setting */
1674         return i40e_apply_link_speed(dev);
1675 }
1676
1677 /*
1678  * Set device link down.
1679  */
1680 static int
1681 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1682 {
1683         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1684         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686
1687         return i40e_phy_conf_link(hw, abilities, speed);
1688 }
1689
1690 int
1691 i40e_dev_link_update(struct rte_eth_dev *dev,
1692                      int wait_to_complete)
1693 {
1694 #define CHECK_INTERVAL 100  /* 100ms */
1695 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1696         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1697         struct i40e_link_status link_status;
1698         struct rte_eth_link link, old;
1699         int status;
1700         unsigned rep_cnt = MAX_REPEAT_TIME;
1701
1702         memset(&link, 0, sizeof(link));
1703         memset(&old, 0, sizeof(old));
1704         memset(&link_status, 0, sizeof(link_status));
1705         rte_i40e_dev_atomic_read_link_status(dev, &old);
1706
1707         do {
1708                 /* Get link status information from hardware */
1709                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1710                 if (status != I40E_SUCCESS) {
1711                         link.link_speed = ETH_LINK_SPEED_100;
1712                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1713                         PMD_DRV_LOG(ERR, "Failed to get link info");
1714                         goto out;
1715                 }
1716
1717                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1718                 if (!wait_to_complete)
1719                         break;
1720
1721                 rte_delay_ms(CHECK_INTERVAL);
1722         } while (!link.link_status && rep_cnt--);
1723
1724         if (!link.link_status)
1725                 goto out;
1726
1727         /* i40e uses full duplex only */
1728         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1729
1730         /* Parse the link status */
1731         switch (link_status.link_speed) {
1732         case I40E_LINK_SPEED_100MB:
1733                 link.link_speed = ETH_LINK_SPEED_100;
1734                 break;
1735         case I40E_LINK_SPEED_1GB:
1736                 link.link_speed = ETH_LINK_SPEED_1000;
1737                 break;
1738         case I40E_LINK_SPEED_10GB:
1739                 link.link_speed = ETH_LINK_SPEED_10G;
1740                 break;
1741         case I40E_LINK_SPEED_20GB:
1742                 link.link_speed = ETH_LINK_SPEED_20G;
1743                 break;
1744         case I40E_LINK_SPEED_40GB:
1745                 link.link_speed = ETH_LINK_SPEED_40G;
1746                 break;
1747         default:
1748                 link.link_speed = ETH_LINK_SPEED_100;
1749                 break;
1750         }
1751
1752 out:
1753         rte_i40e_dev_atomic_write_link_status(dev, &link);
1754         if (link.link_status == old.link_status)
1755                 return -1;
1756
1757         return 0;
1758 }
1759
1760 /* Get all the statistics of a VSI */
1761 void
1762 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1763 {
1764         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1765         struct i40e_eth_stats *nes = &vsi->eth_stats;
1766         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1767         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1768
1769         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1770                             vsi->offset_loaded, &oes->rx_bytes,
1771                             &nes->rx_bytes);
1772         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1773                             vsi->offset_loaded, &oes->rx_unicast,
1774                             &nes->rx_unicast);
1775         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1776                             vsi->offset_loaded, &oes->rx_multicast,
1777                             &nes->rx_multicast);
1778         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1779                             vsi->offset_loaded, &oes->rx_broadcast,
1780                             &nes->rx_broadcast);
1781         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1782                             &oes->rx_discards, &nes->rx_discards);
1783         /* GLV_REPC not supported */
1784         /* GLV_RMPC not supported */
1785         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1786                             &oes->rx_unknown_protocol,
1787                             &nes->rx_unknown_protocol);
1788         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1789                             vsi->offset_loaded, &oes->tx_bytes,
1790                             &nes->tx_bytes);
1791         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1792                             vsi->offset_loaded, &oes->tx_unicast,
1793                             &nes->tx_unicast);
1794         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1795                             vsi->offset_loaded, &oes->tx_multicast,
1796                             &nes->tx_multicast);
1797         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1798                             vsi->offset_loaded,  &oes->tx_broadcast,
1799                             &nes->tx_broadcast);
1800         /* GLV_TDPC not supported */
1801         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1802                             &oes->tx_errors, &nes->tx_errors);
1803         vsi->offset_loaded = true;
1804
1805         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1806                     vsi->vsi_id);
1807         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1808         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1809         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1810         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1811         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1812         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1813                     nes->rx_unknown_protocol);
1814         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1815         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1816         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1817         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1818         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1819         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1820         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1821                     vsi->vsi_id);
1822 }
1823
1824 static void
1825 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1826 {
1827         unsigned int i;
1828         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1829         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1830
1831         /* Get statistics of struct i40e_eth_stats */
1832         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1833                             I40E_GLPRT_GORCL(hw->port),
1834                             pf->offset_loaded, &os->eth.rx_bytes,
1835                             &ns->eth.rx_bytes);
1836         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1837                             I40E_GLPRT_UPRCL(hw->port),
1838                             pf->offset_loaded, &os->eth.rx_unicast,
1839                             &ns->eth.rx_unicast);
1840         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1841                             I40E_GLPRT_MPRCL(hw->port),
1842                             pf->offset_loaded, &os->eth.rx_multicast,
1843                             &ns->eth.rx_multicast);
1844         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1845                             I40E_GLPRT_BPRCL(hw->port),
1846                             pf->offset_loaded, &os->eth.rx_broadcast,
1847                             &ns->eth.rx_broadcast);
1848         /* Workaround: CRC size should not be included in byte statistics,
1849          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1850          */
1851         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1852                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1853
1854         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1855                             pf->offset_loaded, &os->eth.rx_discards,
1856                             &ns->eth.rx_discards);
1857         /* GLPRT_REPC not supported */
1858         /* GLPRT_RMPC not supported */
1859         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1860                             pf->offset_loaded,
1861                             &os->eth.rx_unknown_protocol,
1862                             &ns->eth.rx_unknown_protocol);
1863         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1864                             I40E_GLPRT_GOTCL(hw->port),
1865                             pf->offset_loaded, &os->eth.tx_bytes,
1866                             &ns->eth.tx_bytes);
1867         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1868                             I40E_GLPRT_UPTCL(hw->port),
1869                             pf->offset_loaded, &os->eth.tx_unicast,
1870                             &ns->eth.tx_unicast);
1871         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1872                             I40E_GLPRT_MPTCL(hw->port),
1873                             pf->offset_loaded, &os->eth.tx_multicast,
1874                             &ns->eth.tx_multicast);
1875         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1876                             I40E_GLPRT_BPTCL(hw->port),
1877                             pf->offset_loaded, &os->eth.tx_broadcast,
1878                             &ns->eth.tx_broadcast);
1879         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1880                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1881         /* GLPRT_TEPC not supported */
1882
1883         /* additional port specific stats */
1884         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1885                             pf->offset_loaded, &os->tx_dropped_link_down,
1886                             &ns->tx_dropped_link_down);
1887         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1888                             pf->offset_loaded, &os->crc_errors,
1889                             &ns->crc_errors);
1890         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1891                             pf->offset_loaded, &os->illegal_bytes,
1892                             &ns->illegal_bytes);
1893         /* GLPRT_ERRBC not supported */
1894         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1895                             pf->offset_loaded, &os->mac_local_faults,
1896                             &ns->mac_local_faults);
1897         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1898                             pf->offset_loaded, &os->mac_remote_faults,
1899                             &ns->mac_remote_faults);
1900         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1901                             pf->offset_loaded, &os->rx_length_errors,
1902                             &ns->rx_length_errors);
1903         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1904                             pf->offset_loaded, &os->link_xon_rx,
1905                             &ns->link_xon_rx);
1906         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1907                             pf->offset_loaded, &os->link_xoff_rx,
1908                             &ns->link_xoff_rx);
1909         for (i = 0; i < 8; i++) {
1910                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1911                                     pf->offset_loaded,
1912                                     &os->priority_xon_rx[i],
1913                                     &ns->priority_xon_rx[i]);
1914                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1915                                     pf->offset_loaded,
1916                                     &os->priority_xoff_rx[i],
1917                                     &ns->priority_xoff_rx[i]);
1918         }
1919         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1920                             pf->offset_loaded, &os->link_xon_tx,
1921                             &ns->link_xon_tx);
1922         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1923                             pf->offset_loaded, &os->link_xoff_tx,
1924                             &ns->link_xoff_tx);
1925         for (i = 0; i < 8; i++) {
1926                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1927                                     pf->offset_loaded,
1928                                     &os->priority_xon_tx[i],
1929                                     &ns->priority_xon_tx[i]);
1930                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1931                                     pf->offset_loaded,
1932                                     &os->priority_xoff_tx[i],
1933                                     &ns->priority_xoff_tx[i]);
1934                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1935                                     pf->offset_loaded,
1936                                     &os->priority_xon_2_xoff[i],
1937                                     &ns->priority_xon_2_xoff[i]);
1938         }
1939         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1940                             I40E_GLPRT_PRC64L(hw->port),
1941                             pf->offset_loaded, &os->rx_size_64,
1942                             &ns->rx_size_64);
1943         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1944                             I40E_GLPRT_PRC127L(hw->port),
1945                             pf->offset_loaded, &os->rx_size_127,
1946                             &ns->rx_size_127);
1947         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1948                             I40E_GLPRT_PRC255L(hw->port),
1949                             pf->offset_loaded, &os->rx_size_255,
1950                             &ns->rx_size_255);
1951         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1952                             I40E_GLPRT_PRC511L(hw->port),
1953                             pf->offset_loaded, &os->rx_size_511,
1954                             &ns->rx_size_511);
1955         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1956                             I40E_GLPRT_PRC1023L(hw->port),
1957                             pf->offset_loaded, &os->rx_size_1023,
1958                             &ns->rx_size_1023);
1959         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1960                             I40E_GLPRT_PRC1522L(hw->port),
1961                             pf->offset_loaded, &os->rx_size_1522,
1962                             &ns->rx_size_1522);
1963         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1964                             I40E_GLPRT_PRC9522L(hw->port),
1965                             pf->offset_loaded, &os->rx_size_big,
1966                             &ns->rx_size_big);
1967         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1968                             pf->offset_loaded, &os->rx_undersize,
1969                             &ns->rx_undersize);
1970         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1971                             pf->offset_loaded, &os->rx_fragments,
1972                             &ns->rx_fragments);
1973         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1974                             pf->offset_loaded, &os->rx_oversize,
1975                             &ns->rx_oversize);
1976         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1977                             pf->offset_loaded, &os->rx_jabber,
1978                             &ns->rx_jabber);
1979         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1980                             I40E_GLPRT_PTC64L(hw->port),
1981                             pf->offset_loaded, &os->tx_size_64,
1982                             &ns->tx_size_64);
1983         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1984                             I40E_GLPRT_PTC127L(hw->port),
1985                             pf->offset_loaded, &os->tx_size_127,
1986                             &ns->tx_size_127);
1987         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1988                             I40E_GLPRT_PTC255L(hw->port),
1989                             pf->offset_loaded, &os->tx_size_255,
1990                             &ns->tx_size_255);
1991         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1992                             I40E_GLPRT_PTC511L(hw->port),
1993                             pf->offset_loaded, &os->tx_size_511,
1994                             &ns->tx_size_511);
1995         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1996                             I40E_GLPRT_PTC1023L(hw->port),
1997                             pf->offset_loaded, &os->tx_size_1023,
1998                             &ns->tx_size_1023);
1999         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2000                             I40E_GLPRT_PTC1522L(hw->port),
2001                             pf->offset_loaded, &os->tx_size_1522,
2002                             &ns->tx_size_1522);
2003         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2004                             I40E_GLPRT_PTC9522L(hw->port),
2005                             pf->offset_loaded, &os->tx_size_big,
2006                             &ns->tx_size_big);
2007         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2008                            pf->offset_loaded,
2009                            &os->fd_sb_match, &ns->fd_sb_match);
2010         /* GLPRT_MSPDC not supported */
2011         /* GLPRT_XEC not supported */
2012
2013         pf->offset_loaded = true;
2014
2015         if (pf->main_vsi)
2016                 i40e_update_vsi_stats(pf->main_vsi);
2017 }
2018
2019 /* Get all statistics of a port */
2020 static void
2021 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2022 {
2023         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2024         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2026         unsigned i;
2027
2028         /* call read registers - updates values, now write them to struct */
2029         i40e_read_stats_registers(pf, hw);
2030
2031         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2032                         pf->main_vsi->eth_stats.rx_multicast +
2033                         pf->main_vsi->eth_stats.rx_broadcast -
2034                         pf->main_vsi->eth_stats.rx_discards;
2035         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2036                         pf->main_vsi->eth_stats.tx_multicast +
2037                         pf->main_vsi->eth_stats.tx_broadcast;
2038         stats->ibytes   = ns->eth.rx_bytes;
2039         stats->obytes   = ns->eth.tx_bytes;
2040         stats->oerrors  = ns->eth.tx_errors +
2041                         pf->main_vsi->eth_stats.tx_errors;
2042         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2043
2044         /* Rx Errors */
2045         stats->imissed  = ns->eth.rx_discards +
2046                         pf->main_vsi->eth_stats.rx_discards;
2047         stats->ierrors  = ns->crc_errors +
2048                         ns->rx_length_errors + ns->rx_undersize +
2049                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2050                         stats->imissed;
2051
2052         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2053         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2054         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2055         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2056         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2057         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2058         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2059                     ns->eth.rx_unknown_protocol);
2060         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2061         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2062         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2063         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2064         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2065         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2066
2067         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2068                     ns->tx_dropped_link_down);
2069         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2070         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2071                     ns->illegal_bytes);
2072         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2073         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2074                     ns->mac_local_faults);
2075         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2076                     ns->mac_remote_faults);
2077         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2078                     ns->rx_length_errors);
2079         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2080         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2081         for (i = 0; i < 8; i++) {
2082                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2083                                 i, ns->priority_xon_rx[i]);
2084                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2085                                 i, ns->priority_xoff_rx[i]);
2086         }
2087         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2088         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2089         for (i = 0; i < 8; i++) {
2090                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2091                                 i, ns->priority_xon_tx[i]);
2092                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2093                                 i, ns->priority_xoff_tx[i]);
2094                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2095                                 i, ns->priority_xon_2_xoff[i]);
2096         }
2097         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2098         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2099         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2100         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2101         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2102         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2103         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2104         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2105         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2106         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2107         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2108         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2109         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2110         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2111         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2112         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2113         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2114         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2115         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2116                         ns->mac_short_packet_dropped);
2117         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2118                     ns->checksum_error);
2119         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2120         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2121 }
2122
2123 /* Reset the statistics */
2124 static void
2125 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2126 {
2127         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129
2130         /* Mark PF and VSI stats to update the offset, aka "reset" */
2131         pf->offset_loaded = false;
2132         if (pf->main_vsi)
2133                 pf->main_vsi->offset_loaded = false;
2134
2135         /* read the stats, reading current register values into offset */
2136         i40e_read_stats_registers(pf, hw);
2137 }
2138
2139 static uint32_t
2140 i40e_xstats_calc_num(void)
2141 {
2142         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2143                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2144                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2145 }
2146
2147 static int
2148 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2149                     unsigned n)
2150 {
2151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2153         unsigned i, count, prio;
2154         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2155
2156         count = i40e_xstats_calc_num();
2157         if (n < count)
2158                 return count;
2159
2160         i40e_read_stats_registers(pf, hw);
2161
2162         if (xstats == NULL)
2163                 return 0;
2164
2165         count = 0;
2166
2167         /* Get stats from i40e_eth_stats struct */
2168         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2169                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2170                          "%s", rte_i40e_stats_strings[i].name);
2171                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2172                         rte_i40e_stats_strings[i].offset);
2173                 count++;
2174         }
2175
2176         /* Get individiual stats from i40e_hw_port struct */
2177         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2178                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2179                          "%s", rte_i40e_hw_port_strings[i].name);
2180                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2181                                 rte_i40e_hw_port_strings[i].offset);
2182                 count++;
2183         }
2184
2185         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2186                 for (prio = 0; prio < 8; prio++) {
2187                         snprintf(xstats[count].name,
2188                                  sizeof(xstats[count].name),
2189                                  "rx_priority%u_%s", prio,
2190                                  rte_i40e_rxq_prio_strings[i].name);
2191                         xstats[count].value =
2192                                 *(uint64_t *)(((char *)hw_stats) +
2193                                 rte_i40e_rxq_prio_strings[i].offset +
2194                                 (sizeof(uint64_t) * prio));
2195                         count++;
2196                 }
2197         }
2198
2199         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2200                 for (prio = 0; prio < 8; prio++) {
2201                         snprintf(xstats[count].name,
2202                                  sizeof(xstats[count].name),
2203                                  "tx_priority%u_%s", prio,
2204                                  rte_i40e_txq_prio_strings[i].name);
2205                         xstats[count].value =
2206                                 *(uint64_t *)(((char *)hw_stats) +
2207                                 rte_i40e_txq_prio_strings[i].offset +
2208                                 (sizeof(uint64_t) * prio));
2209                         count++;
2210                 }
2211         }
2212
2213         return count;
2214 }
2215
2216 static int
2217 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2218                                  __rte_unused uint16_t queue_id,
2219                                  __rte_unused uint8_t stat_idx,
2220                                  __rte_unused uint8_t is_rx)
2221 {
2222         PMD_INIT_FUNC_TRACE();
2223
2224         return -ENOSYS;
2225 }
2226
2227 static void
2228 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2229 {
2230         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2231         struct i40e_vsi *vsi = pf->main_vsi;
2232
2233         dev_info->max_rx_queues = vsi->nb_qps;
2234         dev_info->max_tx_queues = vsi->nb_qps;
2235         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2236         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2237         dev_info->max_mac_addrs = vsi->max_macaddrs;
2238         dev_info->max_vfs = dev->pci_dev->max_vfs;
2239         dev_info->rx_offload_capa =
2240                 DEV_RX_OFFLOAD_VLAN_STRIP |
2241                 DEV_RX_OFFLOAD_QINQ_STRIP |
2242                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2243                 DEV_RX_OFFLOAD_UDP_CKSUM |
2244                 DEV_RX_OFFLOAD_TCP_CKSUM;
2245         dev_info->tx_offload_capa =
2246                 DEV_TX_OFFLOAD_VLAN_INSERT |
2247                 DEV_TX_OFFLOAD_QINQ_INSERT |
2248                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2249                 DEV_TX_OFFLOAD_UDP_CKSUM |
2250                 DEV_TX_OFFLOAD_TCP_CKSUM |
2251                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2252                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2253                 DEV_TX_OFFLOAD_TCP_TSO;
2254         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2255                                                 sizeof(uint32_t);
2256         dev_info->reta_size = pf->hash_lut_size;
2257         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2258
2259         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2260                 .rx_thresh = {
2261                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2262                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2263                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2264                 },
2265                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2266                 .rx_drop_en = 0,
2267         };
2268
2269         dev_info->default_txconf = (struct rte_eth_txconf) {
2270                 .tx_thresh = {
2271                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2272                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2273                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2274                 },
2275                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2276                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2277                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2278                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2279         };
2280
2281         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2282                 .nb_max = I40E_MAX_RING_DESC,
2283                 .nb_min = I40E_MIN_RING_DESC,
2284                 .nb_align = I40E_ALIGN_RING_DESC,
2285         };
2286
2287         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2288                 .nb_max = I40E_MAX_RING_DESC,
2289                 .nb_min = I40E_MIN_RING_DESC,
2290                 .nb_align = I40E_ALIGN_RING_DESC,
2291         };
2292
2293         if (pf->flags & I40E_FLAG_VMDQ) {
2294                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2295                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2296                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2297                                                 pf->max_nb_vmdq_vsi;
2298                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2299                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2300                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2301         }
2302 }
2303
2304 static int
2305 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2306 {
2307         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2308         struct i40e_vsi *vsi = pf->main_vsi;
2309         PMD_INIT_FUNC_TRACE();
2310
2311         if (on)
2312                 return i40e_vsi_add_vlan(vsi, vlan_id);
2313         else
2314                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2315 }
2316
2317 static void
2318 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2319                    __rte_unused uint16_t tpid)
2320 {
2321         PMD_INIT_FUNC_TRACE();
2322 }
2323
2324 static void
2325 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2326 {
2327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2328         struct i40e_vsi *vsi = pf->main_vsi;
2329
2330         if (mask & ETH_VLAN_STRIP_MASK) {
2331                 /* Enable or disable VLAN stripping */
2332                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2333                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2334                 else
2335                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2336         }
2337
2338         if (mask & ETH_VLAN_EXTEND_MASK) {
2339                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2340                         i40e_vsi_config_double_vlan(vsi, TRUE);
2341                 else
2342                         i40e_vsi_config_double_vlan(vsi, FALSE);
2343         }
2344 }
2345
2346 static void
2347 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2348                           __rte_unused uint16_t queue,
2349                           __rte_unused int on)
2350 {
2351         PMD_INIT_FUNC_TRACE();
2352 }
2353
2354 static int
2355 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2356 {
2357         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2358         struct i40e_vsi *vsi = pf->main_vsi;
2359         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2360         struct i40e_vsi_vlan_pvid_info info;
2361
2362         memset(&info, 0, sizeof(info));
2363         info.on = on;
2364         if (info.on)
2365                 info.config.pvid = pvid;
2366         else {
2367                 info.config.reject.tagged =
2368                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2369                 info.config.reject.untagged =
2370                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2371         }
2372
2373         return i40e_vsi_vlan_pvid_set(vsi, &info);
2374 }
2375
2376 static int
2377 i40e_dev_led_on(struct rte_eth_dev *dev)
2378 {
2379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380         uint32_t mode = i40e_led_get(hw);
2381
2382         if (mode == 0)
2383                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2384
2385         return 0;
2386 }
2387
2388 static int
2389 i40e_dev_led_off(struct rte_eth_dev *dev)
2390 {
2391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392         uint32_t mode = i40e_led_get(hw);
2393
2394         if (mode != 0)
2395                 i40e_led_set(hw, 0, false);
2396
2397         return 0;
2398 }
2399
2400 static int
2401 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2402 {
2403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2405
2406         fc_conf->pause_time = pf->fc_conf.pause_time;
2407         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2408         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2409
2410          /* Return current mode according to actual setting*/
2411         switch (hw->fc.current_mode) {
2412         case I40E_FC_FULL:
2413                 fc_conf->mode = RTE_FC_FULL;
2414                 break;
2415         case I40E_FC_TX_PAUSE:
2416                 fc_conf->mode = RTE_FC_TX_PAUSE;
2417                 break;
2418         case I40E_FC_RX_PAUSE:
2419                 fc_conf->mode = RTE_FC_RX_PAUSE;
2420                 break;
2421         case I40E_FC_NONE:
2422         default:
2423                 fc_conf->mode = RTE_FC_NONE;
2424         };
2425
2426         return 0;
2427 }
2428
2429 static int
2430 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2431 {
2432         uint32_t mflcn_reg, fctrl_reg, reg;
2433         uint32_t max_high_water;
2434         uint8_t i, aq_failure;
2435         int err;
2436         struct i40e_hw *hw;
2437         struct i40e_pf *pf;
2438         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2439                 [RTE_FC_NONE] = I40E_FC_NONE,
2440                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2441                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2442                 [RTE_FC_FULL] = I40E_FC_FULL
2443         };
2444
2445         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2446
2447         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2448         if ((fc_conf->high_water > max_high_water) ||
2449                         (fc_conf->high_water < fc_conf->low_water)) {
2450                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2451                         "High_water must <= %d.", max_high_water);
2452                 return -EINVAL;
2453         }
2454
2455         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2457         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2458
2459         pf->fc_conf.pause_time = fc_conf->pause_time;
2460         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2461         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2462
2463         PMD_INIT_FUNC_TRACE();
2464
2465         /* All the link flow control related enable/disable register
2466          * configuration is handle by the F/W
2467          */
2468         err = i40e_set_fc(hw, &aq_failure, true);
2469         if (err < 0)
2470                 return -ENOSYS;
2471
2472         if (i40e_is_40G_device(hw->device_id)) {
2473                 /* Configure flow control refresh threshold,
2474                  * the value for stat_tx_pause_refresh_timer[8]
2475                  * is used for global pause operation.
2476                  */
2477
2478                 I40E_WRITE_REG(hw,
2479                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2480                                pf->fc_conf.pause_time);
2481
2482                 /* configure the timer value included in transmitted pause
2483                  * frame,
2484                  * the value for stat_tx_pause_quanta[8] is used for global
2485                  * pause operation
2486                  */
2487                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2488                                pf->fc_conf.pause_time);
2489
2490                 fctrl_reg = I40E_READ_REG(hw,
2491                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2492
2493                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2494                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2495                 else
2496                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2497
2498                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2499                                fctrl_reg);
2500         } else {
2501                 /* Configure pause time (2 TCs per register) */
2502                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2503                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2504                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2505
2506                 /* Configure flow control refresh threshold value */
2507                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2508                                pf->fc_conf.pause_time / 2);
2509
2510                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2511
2512                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2513                  *depending on configuration
2514                  */
2515                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2516                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2517                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2518                 } else {
2519                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2520                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2521                 }
2522
2523                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2524         }
2525
2526         /* config the water marker both based on the packets and bytes */
2527         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2528                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2529                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2530         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2531                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2532                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2533         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2534                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2535                        << I40E_KILOSHIFT);
2536         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2537                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2538                        << I40E_KILOSHIFT);
2539
2540         I40E_WRITE_FLUSH(hw);
2541
2542         return 0;
2543 }
2544
2545 static int
2546 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2547                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2548 {
2549         PMD_INIT_FUNC_TRACE();
2550
2551         return -ENOSYS;
2552 }
2553
2554 /* Add a MAC address, and update filters */
2555 static void
2556 i40e_macaddr_add(struct rte_eth_dev *dev,
2557                  struct ether_addr *mac_addr,
2558                  __rte_unused uint32_t index,
2559                  uint32_t pool)
2560 {
2561         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2562         struct i40e_mac_filter_info mac_filter;
2563         struct i40e_vsi *vsi;
2564         int ret;
2565
2566         /* If VMDQ not enabled or configured, return */
2567         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2568                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2569                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2570                         pool);
2571                 return;
2572         }
2573
2574         if (pool > pf->nb_cfg_vmdq_vsi) {
2575                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2576                                 pool, pf->nb_cfg_vmdq_vsi);
2577                 return;
2578         }
2579
2580         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2581         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2582
2583         if (pool == 0)
2584                 vsi = pf->main_vsi;
2585         else
2586                 vsi = pf->vmdq[pool - 1].vsi;
2587
2588         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2589         if (ret != I40E_SUCCESS) {
2590                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2591                 return;
2592         }
2593 }
2594
2595 /* Remove a MAC address, and update filters */
2596 static void
2597 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2598 {
2599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2600         struct i40e_vsi *vsi;
2601         struct rte_eth_dev_data *data = dev->data;
2602         struct ether_addr *macaddr;
2603         int ret;
2604         uint32_t i;
2605         uint64_t pool_sel;
2606
2607         macaddr = &(data->mac_addrs[index]);
2608
2609         pool_sel = dev->data->mac_pool_sel[index];
2610
2611         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2612                 if (pool_sel & (1ULL << i)) {
2613                         if (i == 0)
2614                                 vsi = pf->main_vsi;
2615                         else {
2616                                 /* No VMDQ pool enabled or configured */
2617                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2618                                         (i > pf->nb_cfg_vmdq_vsi)) {
2619                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2620                                                         "/configured");
2621                                         return;
2622                                 }
2623                                 vsi = pf->vmdq[i - 1].vsi;
2624                         }
2625                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2626
2627                         if (ret) {
2628                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2629                                 return;
2630                         }
2631                 }
2632         }
2633 }
2634
2635 /* Set perfect match or hash match of MAC and VLAN for a VF */
2636 static int
2637 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2638                  struct rte_eth_mac_filter *filter,
2639                  bool add)
2640 {
2641         struct i40e_hw *hw;
2642         struct i40e_mac_filter_info mac_filter;
2643         struct ether_addr old_mac;
2644         struct ether_addr *new_mac;
2645         struct i40e_pf_vf *vf = NULL;
2646         uint16_t vf_id;
2647         int ret;
2648
2649         if (pf == NULL) {
2650                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2651                 return -EINVAL;
2652         }
2653         hw = I40E_PF_TO_HW(pf);
2654
2655         if (filter == NULL) {
2656                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2657                 return -EINVAL;
2658         }
2659
2660         new_mac = &filter->mac_addr;
2661
2662         if (is_zero_ether_addr(new_mac)) {
2663                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2664                 return -EINVAL;
2665         }
2666
2667         vf_id = filter->dst_id;
2668
2669         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2670                 PMD_DRV_LOG(ERR, "Invalid argument.");
2671                 return -EINVAL;
2672         }
2673         vf = &pf->vfs[vf_id];
2674
2675         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2676                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2677                 return -EINVAL;
2678         }
2679
2680         if (add) {
2681                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2682                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2683                                 ETHER_ADDR_LEN);
2684                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2685                                  ETHER_ADDR_LEN);
2686
2687                 mac_filter.filter_type = filter->filter_type;
2688                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2689                 if (ret != I40E_SUCCESS) {
2690                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2691                         return -1;
2692                 }
2693                 ether_addr_copy(new_mac, &pf->dev_addr);
2694         } else {
2695                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2696                                 ETHER_ADDR_LEN);
2697                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2698                 if (ret != I40E_SUCCESS) {
2699                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2700                         return -1;
2701                 }
2702
2703                 /* Clear device address as it has been removed */
2704                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2705                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2706         }
2707
2708         return 0;
2709 }
2710
2711 /* MAC filter handle */
2712 static int
2713 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2714                 void *arg)
2715 {
2716         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2717         struct rte_eth_mac_filter *filter;
2718         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2719         int ret = I40E_NOT_SUPPORTED;
2720
2721         filter = (struct rte_eth_mac_filter *)(arg);
2722
2723         switch (filter_op) {
2724         case RTE_ETH_FILTER_NOP:
2725                 ret = I40E_SUCCESS;
2726                 break;
2727         case RTE_ETH_FILTER_ADD:
2728                 i40e_pf_disable_irq0(hw);
2729                 if (filter->is_vf)
2730                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2731                 i40e_pf_enable_irq0(hw);
2732                 break;
2733         case RTE_ETH_FILTER_DELETE:
2734                 i40e_pf_disable_irq0(hw);
2735                 if (filter->is_vf)
2736                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2737                 i40e_pf_enable_irq0(hw);
2738                 break;
2739         default:
2740                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2741                 ret = I40E_ERR_PARAM;
2742                 break;
2743         }
2744
2745         return ret;
2746 }
2747
2748 static int
2749 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2750 {
2751         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2752         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2753         int ret;
2754
2755         if (!lut)
2756                 return -EINVAL;
2757
2758         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2759                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2760                                           lut, lut_size);
2761                 if (ret) {
2762                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2763                         return ret;
2764                 }
2765         } else {
2766                 uint32_t *lut_dw = (uint32_t *)lut;
2767                 uint16_t i, lut_size_dw = lut_size / 4;
2768
2769                 for (i = 0; i < lut_size_dw; i++)
2770                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2771         }
2772
2773         return 0;
2774 }
2775
2776 static int
2777 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2778 {
2779         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2780         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2781         int ret;
2782
2783         if (!vsi || !lut)
2784                 return -EINVAL;
2785
2786         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2787                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2788                                           lut, lut_size);
2789                 if (ret) {
2790                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2791                         return ret;
2792                 }
2793         } else {
2794                 uint32_t *lut_dw = (uint32_t *)lut;
2795                 uint16_t i, lut_size_dw = lut_size / 4;
2796
2797                 for (i = 0; i < lut_size_dw; i++)
2798                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2799                 I40E_WRITE_FLUSH(hw);
2800         }
2801
2802         return 0;
2803 }
2804
2805 static int
2806 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2807                          struct rte_eth_rss_reta_entry64 *reta_conf,
2808                          uint16_t reta_size)
2809 {
2810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811         uint16_t i, lut_size = pf->hash_lut_size;
2812         uint16_t idx, shift;
2813         uint8_t *lut;
2814         int ret;
2815
2816         if (reta_size != lut_size ||
2817                 reta_size > ETH_RSS_RETA_SIZE_512) {
2818                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2819                         "(%d) doesn't match the number hardware can supported "
2820                                         "(%d)\n", reta_size, lut_size);
2821                 return -EINVAL;
2822         }
2823
2824         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2825         if (!lut) {
2826                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2827                 return -ENOMEM;
2828         }
2829         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2830         if (ret)
2831                 goto out;
2832         for (i = 0; i < reta_size; i++) {
2833                 idx = i / RTE_RETA_GROUP_SIZE;
2834                 shift = i % RTE_RETA_GROUP_SIZE;
2835                 if (reta_conf[idx].mask & (1ULL << shift))
2836                         lut[i] = reta_conf[idx].reta[shift];
2837         }
2838         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2839
2840 out:
2841         rte_free(lut);
2842
2843         return ret;
2844 }
2845
2846 static int
2847 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2848                         struct rte_eth_rss_reta_entry64 *reta_conf,
2849                         uint16_t reta_size)
2850 {
2851         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2852         uint16_t i, lut_size = pf->hash_lut_size;
2853         uint16_t idx, shift;
2854         uint8_t *lut;
2855         int ret;
2856
2857         if (reta_size != lut_size ||
2858                 reta_size > ETH_RSS_RETA_SIZE_512) {
2859                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2860                         "(%d) doesn't match the number hardware can supported "
2861                                         "(%d)\n", reta_size, lut_size);
2862                 return -EINVAL;
2863         }
2864
2865         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2866         if (!lut) {
2867                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2868                 return -ENOMEM;
2869         }
2870
2871         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2872         if (ret)
2873                 goto out;
2874         for (i = 0; i < reta_size; i++) {
2875                 idx = i / RTE_RETA_GROUP_SIZE;
2876                 shift = i % RTE_RETA_GROUP_SIZE;
2877                 if (reta_conf[idx].mask & (1ULL << shift))
2878                         reta_conf[idx].reta[shift] = lut[i];
2879         }
2880
2881 out:
2882         rte_free(lut);
2883
2884         return ret;
2885 }
2886
2887 /**
2888  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2889  * @hw:   pointer to the HW structure
2890  * @mem:  pointer to mem struct to fill out
2891  * @size: size of memory requested
2892  * @alignment: what to align the allocation to
2893  **/
2894 enum i40e_status_code
2895 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2896                         struct i40e_dma_mem *mem,
2897                         u64 size,
2898                         u32 alignment)
2899 {
2900         const struct rte_memzone *mz = NULL;
2901         char z_name[RTE_MEMZONE_NAMESIZE];
2902
2903         if (!mem)
2904                 return I40E_ERR_PARAM;
2905
2906         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2907         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2908                                          alignment, RTE_PGSIZE_2M);
2909         if (!mz)
2910                 return I40E_ERR_NO_MEMORY;
2911
2912         mem->size = size;
2913         mem->va = mz->addr;
2914         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2915         mem->zone = (const void *)mz;
2916         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2917                     "%"PRIu64, mz->name, mem->pa);
2918
2919         return I40E_SUCCESS;
2920 }
2921
2922 /**
2923  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2924  * @hw:   pointer to the HW structure
2925  * @mem:  ptr to mem struct to free
2926  **/
2927 enum i40e_status_code
2928 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2929                     struct i40e_dma_mem *mem)
2930 {
2931         if (!mem)
2932                 return I40E_ERR_PARAM;
2933
2934         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2935                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2936                     mem->pa);
2937         rte_memzone_free((const struct rte_memzone *)mem->zone);
2938         mem->zone = NULL;
2939         mem->va = NULL;
2940         mem->pa = (u64)0;
2941
2942         return I40E_SUCCESS;
2943 }
2944
2945 /**
2946  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2947  * @hw:   pointer to the HW structure
2948  * @mem:  pointer to mem struct to fill out
2949  * @size: size of memory requested
2950  **/
2951 enum i40e_status_code
2952 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2953                          struct i40e_virt_mem *mem,
2954                          u32 size)
2955 {
2956         if (!mem)
2957                 return I40E_ERR_PARAM;
2958
2959         mem->size = size;
2960         mem->va = rte_zmalloc("i40e", size, 0);
2961
2962         if (mem->va)
2963                 return I40E_SUCCESS;
2964         else
2965                 return I40E_ERR_NO_MEMORY;
2966 }
2967
2968 /**
2969  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2970  * @hw:   pointer to the HW structure
2971  * @mem:  pointer to mem struct to free
2972  **/
2973 enum i40e_status_code
2974 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2975                      struct i40e_virt_mem *mem)
2976 {
2977         if (!mem)
2978                 return I40E_ERR_PARAM;
2979
2980         rte_free(mem->va);
2981         mem->va = NULL;
2982
2983         return I40E_SUCCESS;
2984 }
2985
2986 void
2987 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2988 {
2989         rte_spinlock_init(&sp->spinlock);
2990 }
2991
2992 void
2993 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2994 {
2995         rte_spinlock_lock(&sp->spinlock);
2996 }
2997
2998 void
2999 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3000 {
3001         rte_spinlock_unlock(&sp->spinlock);
3002 }
3003
3004 void
3005 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3006 {
3007         return;
3008 }
3009
3010 /**
3011  * Get the hardware capabilities, which will be parsed
3012  * and saved into struct i40e_hw.
3013  */
3014 static int
3015 i40e_get_cap(struct i40e_hw *hw)
3016 {
3017         struct i40e_aqc_list_capabilities_element_resp *buf;
3018         uint16_t len, size = 0;
3019         int ret;
3020
3021         /* Calculate a huge enough buff for saving response data temporarily */
3022         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3023                                                 I40E_MAX_CAP_ELE_NUM;
3024         buf = rte_zmalloc("i40e", len, 0);
3025         if (!buf) {
3026                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3027                 return I40E_ERR_NO_MEMORY;
3028         }
3029
3030         /* Get, parse the capabilities and save it to hw */
3031         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3032                         i40e_aqc_opc_list_func_capabilities, NULL);
3033         if (ret != I40E_SUCCESS)
3034                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3035
3036         /* Free the temporary buffer after being used */
3037         rte_free(buf);
3038
3039         return ret;
3040 }
3041
3042 static int
3043 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3044 {
3045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3046         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3047         uint16_t qp_count = 0, vsi_count = 0;
3048
3049         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3050                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3051                 return -EINVAL;
3052         }
3053         /* Add the parameter init for LFC */
3054         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3055         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3056         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3057
3058         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3059         pf->max_num_vsi = hw->func_caps.num_vsis;
3060         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3061         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3062         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3063
3064         /* FDir queue/VSI allocation */
3065         pf->fdir_qp_offset = 0;
3066         if (hw->func_caps.fd) {
3067                 pf->flags |= I40E_FLAG_FDIR;
3068                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3069         } else {
3070                 pf->fdir_nb_qps = 0;
3071         }
3072         qp_count += pf->fdir_nb_qps;
3073         vsi_count += 1;
3074
3075         /* LAN queue/VSI allocation */
3076         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3077         if (!hw->func_caps.rss) {
3078                 pf->lan_nb_qps = 1;
3079         } else {
3080                 pf->flags |= I40E_FLAG_RSS;
3081                 if (hw->mac.type == I40E_MAC_X722)
3082                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3083                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3084         }
3085         qp_count += pf->lan_nb_qps;
3086         vsi_count += 1;
3087
3088         /* VF queue/VSI allocation */
3089         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3090         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3091                 pf->flags |= I40E_FLAG_SRIOV;
3092                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3093                 pf->vf_num = dev->pci_dev->max_vfs;
3094                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3095                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3096                             pf->vf_nb_qps * pf->vf_num);
3097         } else {
3098                 pf->vf_nb_qps = 0;
3099                 pf->vf_num = 0;
3100         }
3101         qp_count += pf->vf_nb_qps * pf->vf_num;
3102         vsi_count += pf->vf_num;
3103
3104         /* VMDq queue/VSI allocation */
3105         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3106         pf->vmdq_nb_qps = 0;
3107         pf->max_nb_vmdq_vsi = 0;
3108         if (hw->func_caps.vmdq) {
3109                 if (qp_count < hw->func_caps.num_tx_qp &&
3110                         vsi_count < hw->func_caps.num_vsis) {
3111                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3112                                 qp_count) / pf->vmdq_nb_qp_max;
3113
3114                         /* Limit the maximum number of VMDq vsi to the maximum
3115                          * ethdev can support
3116                          */
3117                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3118                                 hw->func_caps.num_vsis - vsi_count);
3119                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3120                                 ETH_64_POOLS);
3121                         if (pf->max_nb_vmdq_vsi) {
3122                                 pf->flags |= I40E_FLAG_VMDQ;
3123                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3124                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3125                                             "per VMDQ VSI, in total %u queues",
3126                                             pf->max_nb_vmdq_vsi,
3127                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3128                                             pf->max_nb_vmdq_vsi);
3129                         } else {
3130                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3131                                             "VMDq");
3132                         }
3133                 } else {
3134                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3135                 }
3136         }
3137         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3138         vsi_count += pf->max_nb_vmdq_vsi;
3139
3140         if (hw->func_caps.dcb)
3141                 pf->flags |= I40E_FLAG_DCB;
3142
3143         if (qp_count > hw->func_caps.num_tx_qp) {
3144                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3145                             "the hardware maximum %u", qp_count,
3146                             hw->func_caps.num_tx_qp);
3147                 return -EINVAL;
3148         }
3149         if (vsi_count > hw->func_caps.num_vsis) {
3150                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3151                             "the hardware maximum %u", vsi_count,
3152                             hw->func_caps.num_vsis);
3153                 return -EINVAL;
3154         }
3155
3156         return 0;
3157 }
3158
3159 static int
3160 i40e_pf_get_switch_config(struct i40e_pf *pf)
3161 {
3162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3163         struct i40e_aqc_get_switch_config_resp *switch_config;
3164         struct i40e_aqc_switch_config_element_resp *element;
3165         uint16_t start_seid = 0, num_reported;
3166         int ret;
3167
3168         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3169                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3170         if (!switch_config) {
3171                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3172                 return -ENOMEM;
3173         }
3174
3175         /* Get the switch configurations */
3176         ret = i40e_aq_get_switch_config(hw, switch_config,
3177                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3178         if (ret != I40E_SUCCESS) {
3179                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3180                 goto fail;
3181         }
3182         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3183         if (num_reported != 1) { /* The number should be 1 */
3184                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3185                 goto fail;
3186         }
3187
3188         /* Parse the switch configuration elements */
3189         element = &(switch_config->element[0]);
3190         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3191                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3192                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3193         } else
3194                 PMD_DRV_LOG(INFO, "Unknown element type");
3195
3196 fail:
3197         rte_free(switch_config);
3198
3199         return ret;
3200 }
3201
3202 static int
3203 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3204                         uint32_t num)
3205 {
3206         struct pool_entry *entry;
3207
3208         if (pool == NULL || num == 0)
3209                 return -EINVAL;
3210
3211         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3212         if (entry == NULL) {
3213                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3214                 return -ENOMEM;
3215         }
3216
3217         /* queue heap initialize */
3218         pool->num_free = num;
3219         pool->num_alloc = 0;
3220         pool->base = base;
3221         LIST_INIT(&pool->alloc_list);
3222         LIST_INIT(&pool->free_list);
3223
3224         /* Initialize element  */
3225         entry->base = 0;
3226         entry->len = num;
3227
3228         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3229         return 0;
3230 }
3231
3232 static void
3233 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3234 {
3235         struct pool_entry *entry;
3236
3237         if (pool == NULL)
3238                 return;
3239
3240         LIST_FOREACH(entry, &pool->alloc_list, next) {
3241                 LIST_REMOVE(entry, next);
3242                 rte_free(entry);
3243         }
3244
3245         LIST_FOREACH(entry, &pool->free_list, next) {
3246                 LIST_REMOVE(entry, next);
3247                 rte_free(entry);
3248         }
3249
3250         pool->num_free = 0;
3251         pool->num_alloc = 0;
3252         pool->base = 0;
3253         LIST_INIT(&pool->alloc_list);
3254         LIST_INIT(&pool->free_list);
3255 }
3256
3257 static int
3258 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3259                        uint32_t base)
3260 {
3261         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3262         uint32_t pool_offset;
3263         int insert;
3264
3265         if (pool == NULL) {
3266                 PMD_DRV_LOG(ERR, "Invalid parameter");
3267                 return -EINVAL;
3268         }
3269
3270         pool_offset = base - pool->base;
3271         /* Lookup in alloc list */
3272         LIST_FOREACH(entry, &pool->alloc_list, next) {
3273                 if (entry->base == pool_offset) {
3274                         valid_entry = entry;
3275                         LIST_REMOVE(entry, next);
3276                         break;
3277                 }
3278         }
3279
3280         /* Not find, return */
3281         if (valid_entry == NULL) {
3282                 PMD_DRV_LOG(ERR, "Failed to find entry");
3283                 return -EINVAL;
3284         }
3285
3286         /**
3287          * Found it, move it to free list  and try to merge.
3288          * In order to make merge easier, always sort it by qbase.
3289          * Find adjacent prev and last entries.
3290          */
3291         prev = next = NULL;
3292         LIST_FOREACH(entry, &pool->free_list, next) {
3293                 if (entry->base > valid_entry->base) {
3294                         next = entry;
3295                         break;
3296                 }
3297                 prev = entry;
3298         }
3299
3300         insert = 0;
3301         /* Try to merge with next one*/
3302         if (next != NULL) {
3303                 /* Merge with next one */
3304                 if (valid_entry->base + valid_entry->len == next->base) {
3305                         next->base = valid_entry->base;
3306                         next->len += valid_entry->len;
3307                         rte_free(valid_entry);
3308                         valid_entry = next;
3309                         insert = 1;
3310                 }
3311         }
3312
3313         if (prev != NULL) {
3314                 /* Merge with previous one */
3315                 if (prev->base + prev->len == valid_entry->base) {
3316                         prev->len += valid_entry->len;
3317                         /* If it merge with next one, remove next node */
3318                         if (insert == 1) {
3319                                 LIST_REMOVE(valid_entry, next);
3320                                 rte_free(valid_entry);
3321                         } else {
3322                                 rte_free(valid_entry);
3323                                 insert = 1;
3324                         }
3325                 }
3326         }
3327
3328         /* Not find any entry to merge, insert */
3329         if (insert == 0) {
3330                 if (prev != NULL)
3331                         LIST_INSERT_AFTER(prev, valid_entry, next);
3332                 else if (next != NULL)
3333                         LIST_INSERT_BEFORE(next, valid_entry, next);
3334                 else /* It's empty list, insert to head */
3335                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3336         }
3337
3338         pool->num_free += valid_entry->len;
3339         pool->num_alloc -= valid_entry->len;
3340
3341         return 0;
3342 }
3343
3344 static int
3345 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3346                        uint16_t num)
3347 {
3348         struct pool_entry *entry, *valid_entry;
3349
3350         if (pool == NULL || num == 0) {
3351                 PMD_DRV_LOG(ERR, "Invalid parameter");
3352                 return -EINVAL;
3353         }
3354
3355         if (pool->num_free < num) {
3356                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3357                             num, pool->num_free);
3358                 return -ENOMEM;
3359         }
3360
3361         valid_entry = NULL;
3362         /* Lookup  in free list and find most fit one */
3363         LIST_FOREACH(entry, &pool->free_list, next) {
3364                 if (entry->len >= num) {
3365                         /* Find best one */
3366                         if (entry->len == num) {
3367                                 valid_entry = entry;
3368                                 break;
3369                         }
3370                         if (valid_entry == NULL || valid_entry->len > entry->len)
3371                                 valid_entry = entry;
3372                 }
3373         }
3374
3375         /* Not find one to satisfy the request, return */
3376         if (valid_entry == NULL) {
3377                 PMD_DRV_LOG(ERR, "No valid entry found");
3378                 return -ENOMEM;
3379         }
3380         /**
3381          * The entry have equal queue number as requested,
3382          * remove it from alloc_list.
3383          */
3384         if (valid_entry->len == num) {
3385                 LIST_REMOVE(valid_entry, next);
3386         } else {
3387                 /**
3388                  * The entry have more numbers than requested,
3389                  * create a new entry for alloc_list and minus its
3390                  * queue base and number in free_list.
3391                  */
3392                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3393                 if (entry == NULL) {
3394                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3395                                     "resource pool");
3396                         return -ENOMEM;
3397                 }
3398                 entry->base = valid_entry->base;
3399                 entry->len = num;
3400                 valid_entry->base += num;
3401                 valid_entry->len -= num;
3402                 valid_entry = entry;
3403         }
3404
3405         /* Insert it into alloc list, not sorted */
3406         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3407
3408         pool->num_free -= valid_entry->len;
3409         pool->num_alloc += valid_entry->len;
3410
3411         return (valid_entry->base + pool->base);
3412 }
3413
3414 /**
3415  * bitmap_is_subset - Check whether src2 is subset of src1
3416  **/
3417 static inline int
3418 bitmap_is_subset(uint8_t src1, uint8_t src2)
3419 {
3420         return !((src1 ^ src2) & src2);
3421 }
3422
3423 static enum i40e_status_code
3424 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3425 {
3426         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3427
3428         /* If DCB is not supported, only default TC is supported */
3429         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3430                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3431                 return I40E_NOT_SUPPORTED;
3432         }
3433
3434         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3435                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3436                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3437                             enabled_tcmap);
3438                 return I40E_NOT_SUPPORTED;
3439         }
3440         return I40E_SUCCESS;
3441 }
3442
3443 int
3444 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3445                                 struct i40e_vsi_vlan_pvid_info *info)
3446 {
3447         struct i40e_hw *hw;
3448         struct i40e_vsi_context ctxt;
3449         uint8_t vlan_flags = 0;
3450         int ret;
3451
3452         if (vsi == NULL || info == NULL) {
3453                 PMD_DRV_LOG(ERR, "invalid parameters");
3454                 return I40E_ERR_PARAM;
3455         }
3456
3457         if (info->on) {
3458                 vsi->info.pvid = info->config.pvid;
3459                 /**
3460                  * If insert pvid is enabled, only tagged pkts are
3461                  * allowed to be sent out.
3462                  */
3463                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3464                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3465         } else {
3466                 vsi->info.pvid = 0;
3467                 if (info->config.reject.tagged == 0)
3468                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3469
3470                 if (info->config.reject.untagged == 0)
3471                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3472         }
3473         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3474                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3475         vsi->info.port_vlan_flags |= vlan_flags;
3476         vsi->info.valid_sections =
3477                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3478         memset(&ctxt, 0, sizeof(ctxt));
3479         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3480         ctxt.seid = vsi->seid;
3481
3482         hw = I40E_VSI_TO_HW(vsi);
3483         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3484         if (ret != I40E_SUCCESS)
3485                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3486
3487         return ret;
3488 }
3489
3490 static int
3491 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3492 {
3493         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3494         int i, ret;
3495         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3496
3497         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3498         if (ret != I40E_SUCCESS)
3499                 return ret;
3500
3501         if (!vsi->seid) {
3502                 PMD_DRV_LOG(ERR, "seid not valid");
3503                 return -EINVAL;
3504         }
3505
3506         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3507         tc_bw_data.tc_valid_bits = enabled_tcmap;
3508         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3509                 tc_bw_data.tc_bw_credits[i] =
3510                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3511
3512         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3513         if (ret != I40E_SUCCESS) {
3514                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3515                 return ret;
3516         }
3517
3518         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3519                                         sizeof(vsi->info.qs_handle));
3520         return I40E_SUCCESS;
3521 }
3522
3523 static enum i40e_status_code
3524 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3525                                  struct i40e_aqc_vsi_properties_data *info,
3526                                  uint8_t enabled_tcmap)
3527 {
3528         enum i40e_status_code ret;
3529         int i, total_tc = 0;
3530         uint16_t qpnum_per_tc, bsf, qp_idx;
3531
3532         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3533         if (ret != I40E_SUCCESS)
3534                 return ret;
3535
3536         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3537                 if (enabled_tcmap & (1 << i))
3538                         total_tc++;
3539         vsi->enabled_tc = enabled_tcmap;
3540
3541         /* Number of queues per enabled TC */
3542         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3543         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3544         bsf = rte_bsf32(qpnum_per_tc);
3545
3546         /* Adjust the queue number to actual queues that can be applied */
3547         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3548                 vsi->nb_qps = qpnum_per_tc * total_tc;
3549
3550         /**
3551          * Configure TC and queue mapping parameters, for enabled TC,
3552          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3553          * default queue will serve it.
3554          */
3555         qp_idx = 0;
3556         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3557                 if (vsi->enabled_tc & (1 << i)) {
3558                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3559                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3560                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3561                         qp_idx += qpnum_per_tc;
3562                 } else
3563                         info->tc_mapping[i] = 0;
3564         }
3565
3566         /* Associate queue number with VSI */
3567         if (vsi->type == I40E_VSI_SRIOV) {
3568                 info->mapping_flags |=
3569                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3570                 for (i = 0; i < vsi->nb_qps; i++)
3571                         info->queue_mapping[i] =
3572                                 rte_cpu_to_le_16(vsi->base_queue + i);
3573         } else {
3574                 info->mapping_flags |=
3575                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3576                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3577         }
3578         info->valid_sections |=
3579                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3580
3581         return I40E_SUCCESS;
3582 }
3583
3584 static int
3585 i40e_veb_release(struct i40e_veb *veb)
3586 {
3587         struct i40e_vsi *vsi;
3588         struct i40e_hw *hw;
3589
3590         if (veb == NULL || veb->associate_vsi == NULL)
3591                 return -EINVAL;
3592
3593         if (!TAILQ_EMPTY(&veb->head)) {
3594                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3595                 return -EACCES;
3596         }
3597
3598         vsi = veb->associate_vsi;
3599         hw = I40E_VSI_TO_HW(vsi);
3600
3601         vsi->uplink_seid = veb->uplink_seid;
3602         i40e_aq_delete_element(hw, veb->seid, NULL);
3603         rte_free(veb);
3604         vsi->veb = NULL;
3605         return I40E_SUCCESS;
3606 }
3607
3608 /* Setup a veb */
3609 static struct i40e_veb *
3610 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3611 {
3612         struct i40e_veb *veb;
3613         int ret;
3614         struct i40e_hw *hw;
3615
3616         if (NULL == pf || vsi == NULL) {
3617                 PMD_DRV_LOG(ERR, "veb setup failed, "
3618                             "associated VSI shouldn't null");
3619                 return NULL;
3620         }
3621         hw = I40E_PF_TO_HW(pf);
3622
3623         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3624         if (!veb) {
3625                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3626                 goto fail;
3627         }
3628
3629         veb->associate_vsi = vsi;
3630         TAILQ_INIT(&veb->head);
3631         veb->uplink_seid = vsi->uplink_seid;
3632
3633         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3634                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3635
3636         if (ret != I40E_SUCCESS) {
3637                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3638                             hw->aq.asq_last_status);
3639                 goto fail;
3640         }
3641
3642         /* get statistics index */
3643         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3644                                 &veb->stats_idx, NULL, NULL, NULL);
3645         if (ret != I40E_SUCCESS) {
3646                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3647                             hw->aq.asq_last_status);
3648                 goto fail;
3649         }
3650
3651         /* Get VEB bandwidth, to be implemented */
3652         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3653         vsi->uplink_seid = veb->seid;
3654
3655         return veb;
3656 fail:
3657         rte_free(veb);
3658         return NULL;
3659 }
3660
3661 int
3662 i40e_vsi_release(struct i40e_vsi *vsi)
3663 {
3664         struct i40e_pf *pf;
3665         struct i40e_hw *hw;
3666         struct i40e_vsi_list *vsi_list;
3667         int ret;
3668         struct i40e_mac_filter *f;
3669
3670         if (!vsi)
3671                 return I40E_SUCCESS;
3672
3673         pf = I40E_VSI_TO_PF(vsi);
3674         hw = I40E_VSI_TO_HW(vsi);
3675
3676         /* VSI has child to attach, release child first */
3677         if (vsi->veb) {
3678                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3679                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3680                                 return -1;
3681                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3682                 }
3683                 i40e_veb_release(vsi->veb);
3684         }
3685
3686         /* Remove all macvlan filters of the VSI */
3687         i40e_vsi_remove_all_macvlan_filter(vsi);
3688         TAILQ_FOREACH(f, &vsi->mac_list, next)
3689                 rte_free(f);
3690
3691         if (vsi->type != I40E_VSI_MAIN) {
3692                 /* Remove vsi from parent's sibling list */
3693                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3694                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3695                         return I40E_ERR_PARAM;
3696                 }
3697                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3698                                 &vsi->sib_vsi_list, list);
3699
3700                 /* Remove all switch element of the VSI */
3701                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3702                 if (ret != I40E_SUCCESS)
3703                         PMD_DRV_LOG(ERR, "Failed to delete element");
3704         }
3705         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3706
3707         if (vsi->type != I40E_VSI_SRIOV)
3708                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3709         rte_free(vsi);
3710
3711         return I40E_SUCCESS;
3712 }
3713
3714 static int
3715 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3716 {
3717         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3718         struct i40e_aqc_remove_macvlan_element_data def_filter;
3719         struct i40e_mac_filter_info filter;
3720         int ret;
3721
3722         if (vsi->type != I40E_VSI_MAIN)
3723                 return I40E_ERR_CONFIG;
3724         memset(&def_filter, 0, sizeof(def_filter));
3725         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3726                                         ETH_ADDR_LEN);
3727         def_filter.vlan_tag = 0;
3728         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3729                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3730         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3731         if (ret != I40E_SUCCESS) {
3732                 struct i40e_mac_filter *f;
3733                 struct ether_addr *mac;
3734
3735                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3736                             "macvlan filter");
3737                 /* It needs to add the permanent mac into mac list */
3738                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3739                 if (f == NULL) {
3740                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3741                         return I40E_ERR_NO_MEMORY;
3742                 }
3743                 mac = &f->mac_info.mac_addr;
3744                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3745                                 ETH_ADDR_LEN);
3746                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3747                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3748                 vsi->mac_num++;
3749
3750                 return ret;
3751         }
3752         (void)rte_memcpy(&filter.mac_addr,
3753                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3754         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3755         return i40e_vsi_add_mac(vsi, &filter);
3756 }
3757
3758 static int
3759 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3760 {
3761         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3762         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3763         struct i40e_hw *hw = &vsi->adapter->hw;
3764         i40e_status ret;
3765         int i;
3766
3767         memset(&bw_config, 0, sizeof(bw_config));
3768         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3769         if (ret != I40E_SUCCESS) {
3770                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3771                             hw->aq.asq_last_status);
3772                 return ret;
3773         }
3774
3775         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3776         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3777                                         &ets_sla_config, NULL);
3778         if (ret != I40E_SUCCESS) {
3779                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3780                             "configuration %u", hw->aq.asq_last_status);
3781                 return ret;
3782         }
3783
3784         /* Not store the info yet, just print out */
3785         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3786         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3787         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3788                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3789                             ets_sla_config.share_credits[i]);
3790                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3791                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3792                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3793                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3794                             (i * 4));
3795         }
3796
3797         return 0;
3798 }
3799
3800 /* Setup a VSI */
3801 struct i40e_vsi *
3802 i40e_vsi_setup(struct i40e_pf *pf,
3803                enum i40e_vsi_type type,
3804                struct i40e_vsi *uplink_vsi,
3805                uint16_t user_param)
3806 {
3807         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3808         struct i40e_vsi *vsi;
3809         struct i40e_mac_filter_info filter;
3810         int ret;
3811         struct i40e_vsi_context ctxt;
3812         struct ether_addr broadcast =
3813                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3814
3815         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3816                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3817                             "VSI link shouldn't be NULL");
3818                 return NULL;
3819         }
3820
3821         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3822                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3823                             "uplink VSI should be NULL");
3824                 return NULL;
3825         }
3826
3827         /* If uplink vsi didn't setup VEB, create one first */
3828         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3829                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3830
3831                 if (NULL == uplink_vsi->veb) {
3832                         PMD_DRV_LOG(ERR, "VEB setup failed");
3833                         return NULL;
3834                 }
3835         }
3836
3837         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3838         if (!vsi) {
3839                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3840                 return NULL;
3841         }
3842         TAILQ_INIT(&vsi->mac_list);
3843         vsi->type = type;
3844         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3845         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3846         vsi->parent_vsi = uplink_vsi;
3847         vsi->user_param = user_param;
3848         /* Allocate queues */
3849         switch (vsi->type) {
3850         case I40E_VSI_MAIN  :
3851                 vsi->nb_qps = pf->lan_nb_qps;
3852                 break;
3853         case I40E_VSI_SRIOV :
3854                 vsi->nb_qps = pf->vf_nb_qps;
3855                 break;
3856         case I40E_VSI_VMDQ2:
3857                 vsi->nb_qps = pf->vmdq_nb_qps;
3858                 break;
3859         case I40E_VSI_FDIR:
3860                 vsi->nb_qps = pf->fdir_nb_qps;
3861                 break;
3862         default:
3863                 goto fail_mem;
3864         }
3865         /*
3866          * The filter status descriptor is reported in rx queue 0,
3867          * while the tx queue for fdir filter programming has no
3868          * such constraints, can be non-zero queues.
3869          * To simplify it, choose FDIR vsi use queue 0 pair.
3870          * To make sure it will use queue 0 pair, queue allocation
3871          * need be done before this function is called
3872          */
3873         if (type != I40E_VSI_FDIR) {
3874                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3875                         if (ret < 0) {
3876                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3877                                                 vsi->seid, ret);
3878                                 goto fail_mem;
3879                         }
3880                         vsi->base_queue = ret;
3881         } else
3882                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3883
3884         /* VF has MSIX interrupt in VF range, don't allocate here */
3885         if (type == I40E_VSI_MAIN) {
3886                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3887                                           RTE_MIN(vsi->nb_qps,
3888                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3889                 if (ret < 0) {
3890                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3891                                     vsi->seid, ret);
3892                         goto fail_queue_alloc;
3893                 }
3894                 vsi->msix_intr = ret;
3895                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3896         } else if (type != I40E_VSI_SRIOV) {
3897                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3898                 if (ret < 0) {
3899                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3900                         goto fail_queue_alloc;
3901                 }
3902                 vsi->msix_intr = ret;
3903                 vsi->nb_msix = 1;
3904         } else {
3905                 vsi->msix_intr = 0;
3906                 vsi->nb_msix = 0;
3907         }
3908
3909         /* Add VSI */
3910         if (type == I40E_VSI_MAIN) {
3911                 /* For main VSI, no need to add since it's default one */
3912                 vsi->uplink_seid = pf->mac_seid;
3913                 vsi->seid = pf->main_vsi_seid;
3914                 /* Bind queues with specific MSIX interrupt */
3915                 /**
3916                  * Needs 2 interrupt at least, one for misc cause which will
3917                  * enabled from OS side, Another for queues binding the
3918                  * interrupt from device side only.
3919                  */
3920
3921                 /* Get default VSI parameters from hardware */
3922                 memset(&ctxt, 0, sizeof(ctxt));
3923                 ctxt.seid = vsi->seid;
3924                 ctxt.pf_num = hw->pf_id;
3925                 ctxt.uplink_seid = vsi->uplink_seid;
3926                 ctxt.vf_num = 0;
3927                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3928                 if (ret != I40E_SUCCESS) {
3929                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3930                         goto fail_msix_alloc;
3931                 }
3932                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3933                         sizeof(struct i40e_aqc_vsi_properties_data));
3934                 vsi->vsi_id = ctxt.vsi_number;
3935                 vsi->info.valid_sections = 0;
3936
3937                 /* Configure tc, enabled TC0 only */
3938                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3939                         I40E_SUCCESS) {
3940                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3941                         goto fail_msix_alloc;
3942                 }
3943
3944                 /* TC, queue mapping */
3945                 memset(&ctxt, 0, sizeof(ctxt));
3946                 vsi->info.valid_sections |=
3947                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3948                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3949                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3950                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3951                         sizeof(struct i40e_aqc_vsi_properties_data));
3952                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3953                                                 I40E_DEFAULT_TCMAP);
3954                 if (ret != I40E_SUCCESS) {
3955                         PMD_DRV_LOG(ERR, "Failed to configure "
3956                                     "TC queue mapping");
3957                         goto fail_msix_alloc;
3958                 }
3959                 ctxt.seid = vsi->seid;
3960                 ctxt.pf_num = hw->pf_id;
3961                 ctxt.uplink_seid = vsi->uplink_seid;
3962                 ctxt.vf_num = 0;
3963
3964                 /* Update VSI parameters */
3965                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3966                 if (ret != I40E_SUCCESS) {
3967                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3968                         goto fail_msix_alloc;
3969                 }
3970
3971                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3972                                                 sizeof(vsi->info.tc_mapping));
3973                 (void)rte_memcpy(&vsi->info.queue_mapping,
3974                                 &ctxt.info.queue_mapping,
3975                         sizeof(vsi->info.queue_mapping));
3976                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3977                 vsi->info.valid_sections = 0;
3978
3979                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3980                                 ETH_ADDR_LEN);
3981
3982                 /**
3983                  * Updating default filter settings are necessary to prevent
3984                  * reception of tagged packets.
3985                  * Some old firmware configurations load a default macvlan
3986                  * filter which accepts both tagged and untagged packets.
3987                  * The updating is to use a normal filter instead if needed.
3988                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3989                  * The firmware with correct configurations load the default
3990                  * macvlan filter which is expected and cannot be removed.
3991                  */
3992                 i40e_update_default_filter_setting(vsi);
3993                 i40e_config_qinq(hw, vsi);
3994         } else if (type == I40E_VSI_SRIOV) {
3995                 memset(&ctxt, 0, sizeof(ctxt));
3996                 /**
3997                  * For other VSI, the uplink_seid equals to uplink VSI's
3998                  * uplink_seid since they share same VEB
3999                  */
4000                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4001                 ctxt.pf_num = hw->pf_id;
4002                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4003                 ctxt.uplink_seid = vsi->uplink_seid;
4004                 ctxt.connection_type = 0x1;
4005                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4006
4007                 /**
4008                  * Do not configure switch ID to enable VEB switch by
4009                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4010                  * if the source mac address of packet sent from VF is not
4011                  * listed in the VEB's mac table, the VEB will switch the
4012                  * packet back to the VF. Need to enable it when HW issue
4013                  * is fixed.
4014                  */
4015
4016                 /* Configure port/vlan */
4017                 ctxt.info.valid_sections |=
4018                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4019                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4020                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4021                                                 I40E_DEFAULT_TCMAP);
4022                 if (ret != I40E_SUCCESS) {
4023                         PMD_DRV_LOG(ERR, "Failed to configure "
4024                                     "TC queue mapping");
4025                         goto fail_msix_alloc;
4026                 }
4027                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4028                 ctxt.info.valid_sections |=
4029                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4030                 /**
4031                  * Since VSI is not created yet, only configure parameter,
4032                  * will add vsi below.
4033                  */
4034
4035                 i40e_config_qinq(hw, vsi);
4036         } else if (type == I40E_VSI_VMDQ2) {
4037                 memset(&ctxt, 0, sizeof(ctxt));
4038                 /*
4039                  * For other VSI, the uplink_seid equals to uplink VSI's
4040                  * uplink_seid since they share same VEB
4041                  */
4042                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4043                 ctxt.pf_num = hw->pf_id;
4044                 ctxt.vf_num = 0;
4045                 ctxt.uplink_seid = vsi->uplink_seid;
4046                 ctxt.connection_type = 0x1;
4047                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4048
4049                 ctxt.info.valid_sections |=
4050                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4051                 /* user_param carries flag to enable loop back */
4052                 if (user_param) {
4053                         ctxt.info.switch_id =
4054                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4055                         ctxt.info.switch_id |=
4056                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4057                 }
4058
4059                 /* Configure port/vlan */
4060                 ctxt.info.valid_sections |=
4061                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4062                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4063                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4064                                                 I40E_DEFAULT_TCMAP);
4065                 if (ret != I40E_SUCCESS) {
4066                         PMD_DRV_LOG(ERR, "Failed to configure "
4067                                         "TC queue mapping");
4068                         goto fail_msix_alloc;
4069                 }
4070                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4071                 ctxt.info.valid_sections |=
4072                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4073         } else if (type == I40E_VSI_FDIR) {
4074                 memset(&ctxt, 0, sizeof(ctxt));
4075                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4076                 ctxt.pf_num = hw->pf_id;
4077                 ctxt.vf_num = 0;
4078                 ctxt.uplink_seid = vsi->uplink_seid;
4079                 ctxt.connection_type = 0x1;     /* regular data port */
4080                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4081                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4082                                                 I40E_DEFAULT_TCMAP);
4083                 if (ret != I40E_SUCCESS) {
4084                         PMD_DRV_LOG(ERR, "Failed to configure "
4085                                         "TC queue mapping.");
4086                         goto fail_msix_alloc;
4087                 }
4088                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4089                 ctxt.info.valid_sections |=
4090                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4091         } else {
4092                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4093                 goto fail_msix_alloc;
4094         }
4095
4096         if (vsi->type != I40E_VSI_MAIN) {
4097                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4098                 if (ret != I40E_SUCCESS) {
4099                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4100                                     hw->aq.asq_last_status);
4101                         goto fail_msix_alloc;
4102                 }
4103                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4104                 vsi->info.valid_sections = 0;
4105                 vsi->seid = ctxt.seid;
4106                 vsi->vsi_id = ctxt.vsi_number;
4107                 vsi->sib_vsi_list.vsi = vsi;
4108                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4109                                 &vsi->sib_vsi_list, list);
4110         }
4111
4112         /* MAC/VLAN configuration */
4113         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4114         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4115
4116         ret = i40e_vsi_add_mac(vsi, &filter);
4117         if (ret != I40E_SUCCESS) {
4118                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4119                 goto fail_msix_alloc;
4120         }
4121
4122         /* Get VSI BW information */
4123         i40e_vsi_dump_bw_config(vsi);
4124         return vsi;
4125 fail_msix_alloc:
4126         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4127 fail_queue_alloc:
4128         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4129 fail_mem:
4130         rte_free(vsi);
4131         return NULL;
4132 }
4133
4134 /* Configure vlan stripping on or off */
4135 int
4136 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4137 {
4138         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4139         struct i40e_vsi_context ctxt;
4140         uint8_t vlan_flags;
4141         int ret = I40E_SUCCESS;
4142
4143         /* Check if it has been already on or off */
4144         if (vsi->info.valid_sections &
4145                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4146                 if (on) {
4147                         if ((vsi->info.port_vlan_flags &
4148                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4149                                 return 0; /* already on */
4150                 } else {
4151                         if ((vsi->info.port_vlan_flags &
4152                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4153                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4154                                 return 0; /* already off */
4155                 }
4156         }
4157
4158         if (on)
4159                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4160         else
4161                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4162         vsi->info.valid_sections =
4163                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4164         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4165         vsi->info.port_vlan_flags |= vlan_flags;
4166         ctxt.seid = vsi->seid;
4167         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4168         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4169         if (ret)
4170                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4171                             on ? "enable" : "disable");
4172
4173         return ret;
4174 }
4175
4176 static int
4177 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4178 {
4179         struct rte_eth_dev_data *data = dev->data;
4180         int ret;
4181
4182         /* Apply vlan offload setting */
4183         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4184
4185         /* Apply double-vlan setting, not implemented yet */
4186
4187         /* Apply pvid setting */
4188         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4189                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4190         if (ret)
4191                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4192
4193         return ret;
4194 }
4195
4196 static int
4197 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4198 {
4199         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4200
4201         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4202 }
4203
4204 static int
4205 i40e_update_flow_control(struct i40e_hw *hw)
4206 {
4207 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4208         struct i40e_link_status link_status;
4209         uint32_t rxfc = 0, txfc = 0, reg;
4210         uint8_t an_info;
4211         int ret;
4212
4213         memset(&link_status, 0, sizeof(link_status));
4214         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4215         if (ret != I40E_SUCCESS) {
4216                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4217                 goto write_reg; /* Disable flow control */
4218         }
4219
4220         an_info = hw->phy.link_info.an_info;
4221         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4222                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4223                 ret = I40E_ERR_NOT_READY;
4224                 goto write_reg; /* Disable flow control */
4225         }
4226         /**
4227          * If link auto negotiation is enabled, flow control needs to
4228          * be configured according to it
4229          */
4230         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4231         case I40E_LINK_PAUSE_RXTX:
4232                 rxfc = 1;
4233                 txfc = 1;
4234                 hw->fc.current_mode = I40E_FC_FULL;
4235                 break;
4236         case I40E_AQ_LINK_PAUSE_RX:
4237                 rxfc = 1;
4238                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4239                 break;
4240         case I40E_AQ_LINK_PAUSE_TX:
4241                 txfc = 1;
4242                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4243                 break;
4244         default:
4245                 hw->fc.current_mode = I40E_FC_NONE;
4246                 break;
4247         }
4248
4249 write_reg:
4250         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4251                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4252         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4253         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4254         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4255         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4256
4257         return ret;
4258 }
4259
4260 /* PF setup */
4261 static int
4262 i40e_pf_setup(struct i40e_pf *pf)
4263 {
4264         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4265         struct i40e_filter_control_settings settings;
4266         struct i40e_vsi *vsi;
4267         int ret;
4268
4269         /* Clear all stats counters */
4270         pf->offset_loaded = FALSE;
4271         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4272         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4273
4274         ret = i40e_pf_get_switch_config(pf);
4275         if (ret != I40E_SUCCESS) {
4276                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4277                 return ret;
4278         }
4279         if (pf->flags & I40E_FLAG_FDIR) {
4280                 /* make queue allocated first, let FDIR use queue pair 0*/
4281                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4282                 if (ret != I40E_FDIR_QUEUE_ID) {
4283                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4284                                     " ret =%d", ret);
4285                         pf->flags &= ~I40E_FLAG_FDIR;
4286                 }
4287         }
4288         /*  main VSI setup */
4289         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4290         if (!vsi) {
4291                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4292                 return I40E_ERR_NOT_READY;
4293         }
4294         pf->main_vsi = vsi;
4295
4296         /* Configure filter control */
4297         memset(&settings, 0, sizeof(settings));
4298         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4299                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4300         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4301                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4302         else {
4303                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4304                                                 hw->func_caps.rss_table_size);
4305                 return I40E_ERR_PARAM;
4306         }
4307         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4308                         "size: %u\n", hw->func_caps.rss_table_size);
4309         pf->hash_lut_size = hw->func_caps.rss_table_size;
4310
4311         /* Enable ethtype and macvlan filters */
4312         settings.enable_ethtype = TRUE;
4313         settings.enable_macvlan = TRUE;
4314         ret = i40e_set_filter_control(hw, &settings);
4315         if (ret)
4316                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4317                                                                 ret);
4318
4319         /* Update flow control according to the auto negotiation */
4320         i40e_update_flow_control(hw);
4321
4322         return I40E_SUCCESS;
4323 }
4324
4325 int
4326 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4327 {
4328         uint32_t reg;
4329         uint16_t j;
4330
4331         /**
4332          * Set or clear TX Queue Disable flags,
4333          * which is required by hardware.
4334          */
4335         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4336         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4337
4338         /* Wait until the request is finished */
4339         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4340                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4341                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4342                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4343                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4344                                                         & 0x1))) {
4345                         break;
4346                 }
4347         }
4348         if (on) {
4349                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4350                         return I40E_SUCCESS; /* already on, skip next steps */
4351
4352                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4353                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4354         } else {
4355                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4356                         return I40E_SUCCESS; /* already off, skip next steps */
4357                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4358         }
4359         /* Write the register */
4360         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4361         /* Check the result */
4362         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4363                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4364                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4365                 if (on) {
4366                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4367                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4368                                 break;
4369                 } else {
4370                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4371                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4372                                 break;
4373                 }
4374         }
4375         /* Check if it is timeout */
4376         if (j >= I40E_CHK_Q_ENA_COUNT) {
4377                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4378                             (on ? "enable" : "disable"), q_idx);
4379                 return I40E_ERR_TIMEOUT;
4380         }
4381
4382         return I40E_SUCCESS;
4383 }
4384
4385 /* Swith on or off the tx queues */
4386 static int
4387 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4388 {
4389         struct rte_eth_dev_data *dev_data = pf->dev_data;
4390         struct i40e_tx_queue *txq;
4391         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4392         uint16_t i;
4393         int ret;
4394
4395         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4396                 txq = dev_data->tx_queues[i];
4397                 /* Don't operate the queue if not configured or
4398                  * if starting only per queue */
4399                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4400                         continue;
4401                 if (on)
4402                         ret = i40e_dev_tx_queue_start(dev, i);
4403                 else
4404                         ret = i40e_dev_tx_queue_stop(dev, i);
4405                 if ( ret != I40E_SUCCESS)
4406                         return ret;
4407         }
4408
4409         return I40E_SUCCESS;
4410 }
4411
4412 int
4413 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4414 {
4415         uint32_t reg;
4416         uint16_t j;
4417
4418         /* Wait until the request is finished */
4419         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4420                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4421                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4422                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4423                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4424                         break;
4425         }
4426
4427         if (on) {
4428                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4429                         return I40E_SUCCESS; /* Already on, skip next steps */
4430                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4431         } else {
4432                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4433                         return I40E_SUCCESS; /* Already off, skip next steps */
4434                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4435         }
4436
4437         /* Write the register */
4438         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4439         /* Check the result */
4440         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4441                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4442                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4443                 if (on) {
4444                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4445                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4446                                 break;
4447                 } else {
4448                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4449                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4450                                 break;
4451                 }
4452         }
4453
4454         /* Check if it is timeout */
4455         if (j >= I40E_CHK_Q_ENA_COUNT) {
4456                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4457                             (on ? "enable" : "disable"), q_idx);
4458                 return I40E_ERR_TIMEOUT;
4459         }
4460
4461         return I40E_SUCCESS;
4462 }
4463 /* Switch on or off the rx queues */
4464 static int
4465 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4466 {
4467         struct rte_eth_dev_data *dev_data = pf->dev_data;
4468         struct i40e_rx_queue *rxq;
4469         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4470         uint16_t i;
4471         int ret;
4472
4473         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4474                 rxq = dev_data->rx_queues[i];
4475                 /* Don't operate the queue if not configured or
4476                  * if starting only per queue */
4477                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4478                         continue;
4479                 if (on)
4480                         ret = i40e_dev_rx_queue_start(dev, i);
4481                 else
4482                         ret = i40e_dev_rx_queue_stop(dev, i);
4483                 if (ret != I40E_SUCCESS)
4484                         return ret;
4485         }
4486
4487         return I40E_SUCCESS;
4488 }
4489
4490 /* Switch on or off all the rx/tx queues */
4491 int
4492 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4493 {
4494         int ret;
4495
4496         if (on) {
4497                 /* enable rx queues before enabling tx queues */
4498                 ret = i40e_dev_switch_rx_queues(pf, on);
4499                 if (ret) {
4500                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4501                         return ret;
4502                 }
4503                 ret = i40e_dev_switch_tx_queues(pf, on);
4504         } else {
4505                 /* Stop tx queues before stopping rx queues */
4506                 ret = i40e_dev_switch_tx_queues(pf, on);
4507                 if (ret) {
4508                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4509                         return ret;
4510                 }
4511                 ret = i40e_dev_switch_rx_queues(pf, on);
4512         }
4513
4514         return ret;
4515 }
4516
4517 /* Initialize VSI for TX */
4518 static int
4519 i40e_dev_tx_init(struct i40e_pf *pf)
4520 {
4521         struct rte_eth_dev_data *data = pf->dev_data;
4522         uint16_t i;
4523         uint32_t ret = I40E_SUCCESS;
4524         struct i40e_tx_queue *txq;
4525
4526         for (i = 0; i < data->nb_tx_queues; i++) {
4527                 txq = data->tx_queues[i];
4528                 if (!txq || !txq->q_set)
4529                         continue;
4530                 ret = i40e_tx_queue_init(txq);
4531                 if (ret != I40E_SUCCESS)
4532                         break;
4533         }
4534         if (ret == I40E_SUCCESS)
4535                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4536                                      ->eth_dev);
4537
4538         return ret;
4539 }
4540
4541 /* Initialize VSI for RX */
4542 static int
4543 i40e_dev_rx_init(struct i40e_pf *pf)
4544 {
4545         struct rte_eth_dev_data *data = pf->dev_data;
4546         int ret = I40E_SUCCESS;
4547         uint16_t i;
4548         struct i40e_rx_queue *rxq;
4549
4550         i40e_pf_config_mq_rx(pf);
4551         for (i = 0; i < data->nb_rx_queues; i++) {
4552                 rxq = data->rx_queues[i];
4553                 if (!rxq || !rxq->q_set)
4554                         continue;
4555
4556                 ret = i40e_rx_queue_init(rxq);
4557                 if (ret != I40E_SUCCESS) {
4558                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4559                                     "initialization");
4560                         break;
4561                 }
4562         }
4563         if (ret == I40E_SUCCESS)
4564                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4565                                      ->eth_dev);
4566
4567         return ret;
4568 }
4569
4570 static int
4571 i40e_dev_rxtx_init(struct i40e_pf *pf)
4572 {
4573         int err;
4574
4575         err = i40e_dev_tx_init(pf);
4576         if (err) {
4577                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4578                 return err;
4579         }
4580         err = i40e_dev_rx_init(pf);
4581         if (err) {
4582                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4583                 return err;
4584         }
4585
4586         return err;
4587 }
4588
4589 static int
4590 i40e_vmdq_setup(struct rte_eth_dev *dev)
4591 {
4592         struct rte_eth_conf *conf = &dev->data->dev_conf;
4593         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4594         int i, err, conf_vsis, j, loop;
4595         struct i40e_vsi *vsi;
4596         struct i40e_vmdq_info *vmdq_info;
4597         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4598         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4599
4600         /*
4601          * Disable interrupt to avoid message from VF. Furthermore, it will
4602          * avoid race condition in VSI creation/destroy.
4603          */
4604         i40e_pf_disable_irq0(hw);
4605
4606         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4607                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4608                 return -ENOTSUP;
4609         }
4610
4611         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4612         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4613                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4614                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4615                         pf->max_nb_vmdq_vsi);
4616                 return -ENOTSUP;
4617         }
4618
4619         if (pf->vmdq != NULL) {
4620                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4621                 return 0;
4622         }
4623
4624         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4625                                 sizeof(*vmdq_info) * conf_vsis, 0);
4626
4627         if (pf->vmdq == NULL) {
4628                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4629                 return -ENOMEM;
4630         }
4631
4632         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4633
4634         /* Create VMDQ VSI */
4635         for (i = 0; i < conf_vsis; i++) {
4636                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4637                                 vmdq_conf->enable_loop_back);
4638                 if (vsi == NULL) {
4639                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4640                         err = -1;
4641                         goto err_vsi_setup;
4642                 }
4643                 vmdq_info = &pf->vmdq[i];
4644                 vmdq_info->pf = pf;
4645                 vmdq_info->vsi = vsi;
4646         }
4647         pf->nb_cfg_vmdq_vsi = conf_vsis;
4648
4649         /* Configure Vlan */
4650         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4651         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4652                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4653                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4654                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4655                                         vmdq_conf->pool_map[i].vlan_id, j);
4656
4657                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4658                                                 vmdq_conf->pool_map[i].vlan_id);
4659                                 if (err) {
4660                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4661                                         err = -1;
4662                                         goto err_vsi_setup;
4663                                 }
4664                         }
4665                 }
4666         }
4667
4668         i40e_pf_enable_irq0(hw);
4669
4670         return 0;
4671
4672 err_vsi_setup:
4673         for (i = 0; i < conf_vsis; i++)
4674                 if (pf->vmdq[i].vsi == NULL)
4675                         break;
4676                 else
4677                         i40e_vsi_release(pf->vmdq[i].vsi);
4678
4679         rte_free(pf->vmdq);
4680         pf->vmdq = NULL;
4681         i40e_pf_enable_irq0(hw);
4682         return err;
4683 }
4684
4685 static void
4686 i40e_stat_update_32(struct i40e_hw *hw,
4687                    uint32_t reg,
4688                    bool offset_loaded,
4689                    uint64_t *offset,
4690                    uint64_t *stat)
4691 {
4692         uint64_t new_data;
4693
4694         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4695         if (!offset_loaded)
4696                 *offset = new_data;
4697
4698         if (new_data >= *offset)
4699                 *stat = (uint64_t)(new_data - *offset);
4700         else
4701                 *stat = (uint64_t)((new_data +
4702                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4703 }
4704
4705 static void
4706 i40e_stat_update_48(struct i40e_hw *hw,
4707                    uint32_t hireg,
4708                    uint32_t loreg,
4709                    bool offset_loaded,
4710                    uint64_t *offset,
4711                    uint64_t *stat)
4712 {
4713         uint64_t new_data;
4714
4715         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4716         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4717                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4718
4719         if (!offset_loaded)
4720                 *offset = new_data;
4721
4722         if (new_data >= *offset)
4723                 *stat = new_data - *offset;
4724         else
4725                 *stat = (uint64_t)((new_data +
4726                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4727
4728         *stat &= I40E_48_BIT_MASK;
4729 }
4730
4731 /* Disable IRQ0 */
4732 void
4733 i40e_pf_disable_irq0(struct i40e_hw *hw)
4734 {
4735         /* Disable all interrupt types */
4736         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4737         I40E_WRITE_FLUSH(hw);
4738 }
4739
4740 /* Enable IRQ0 */
4741 void
4742 i40e_pf_enable_irq0(struct i40e_hw *hw)
4743 {
4744         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4745                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4746                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4747                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4748         I40E_WRITE_FLUSH(hw);
4749 }
4750
4751 static void
4752 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4753 {
4754         /* read pending request and disable first */
4755         i40e_pf_disable_irq0(hw);
4756         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4757         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4758                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4759
4760         if (no_queue)
4761                 /* Link no queues with irq0 */
4762                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4763                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4764 }
4765
4766 static void
4767 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4768 {
4769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4770         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4771         int i;
4772         uint16_t abs_vf_id;
4773         uint32_t index, offset, val;
4774
4775         if (!pf->vfs)
4776                 return;
4777         /**
4778          * Try to find which VF trigger a reset, use absolute VF id to access
4779          * since the reg is global register.
4780          */
4781         for (i = 0; i < pf->vf_num; i++) {
4782                 abs_vf_id = hw->func_caps.vf_base_id + i;
4783                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4784                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4785                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4786                 /* VFR event occured */
4787                 if (val & (0x1 << offset)) {
4788                         int ret;
4789
4790                         /* Clear the event first */
4791                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4792                                                         (0x1 << offset));
4793                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4794                         /**
4795                          * Only notify a VF reset event occured,
4796                          * don't trigger another SW reset
4797                          */
4798                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4799                         if (ret != I40E_SUCCESS)
4800                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4801                 }
4802         }
4803 }
4804
4805 static void
4806 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4807 {
4808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4809         struct i40e_arq_event_info info;
4810         uint16_t pending, opcode;
4811         int ret;
4812
4813         info.buf_len = I40E_AQ_BUF_SZ;
4814         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4815         if (!info.msg_buf) {
4816                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4817                 return;
4818         }
4819
4820         pending = 1;
4821         while (pending) {
4822                 ret = i40e_clean_arq_element(hw, &info, &pending);
4823
4824                 if (ret != I40E_SUCCESS) {
4825                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4826                                     "aq_err: %u", hw->aq.asq_last_status);
4827                         break;
4828                 }
4829                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4830
4831                 switch (opcode) {
4832                 case i40e_aqc_opc_send_msg_to_pf:
4833                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4834                         i40e_pf_host_handle_vf_msg(dev,
4835                                         rte_le_to_cpu_16(info.desc.retval),
4836                                         rte_le_to_cpu_32(info.desc.cookie_high),
4837                                         rte_le_to_cpu_32(info.desc.cookie_low),
4838                                         info.msg_buf,
4839                                         info.msg_len);
4840                         break;
4841                 default:
4842                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4843                                     opcode);
4844                         break;
4845                 }
4846         }
4847         rte_free(info.msg_buf);
4848 }
4849
4850 /*
4851  * Interrupt handler is registered as the alarm callback for handling LSC
4852  * interrupt in a definite of time, in order to wait the NIC into a stable
4853  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4854  * no need for link down interrupt.
4855  */
4856 static void
4857 i40e_dev_interrupt_delayed_handler(void *param)
4858 {
4859         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4860         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4861         uint32_t icr0;
4862
4863         /* read interrupt causes again */
4864         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4865
4866 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4867         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4868                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4869         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4870                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4871         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4872                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4873         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4874                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4875         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4876                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4877                                                                 "state\n");
4878         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4879                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4880         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4881                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4882 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4883
4884         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4885                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4886                 i40e_dev_handle_vfr_event(dev);
4887         }
4888         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4889                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4890                 i40e_dev_handle_aq_msg(dev);
4891         }
4892
4893         /* handle the link up interrupt in an alarm callback */
4894         i40e_dev_link_update(dev, 0);
4895         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4896
4897         i40e_pf_enable_irq0(hw);
4898         rte_intr_enable(&(dev->pci_dev->intr_handle));
4899 }
4900
4901 /**
4902  * Interrupt handler triggered by NIC  for handling
4903  * specific interrupt.
4904  *
4905  * @param handle
4906  *  Pointer to interrupt handle.
4907  * @param param
4908  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4909  *
4910  * @return
4911  *  void
4912  */
4913 static void
4914 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4915                            void *param)
4916 {
4917         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4919         uint32_t icr0;
4920
4921         /* Disable interrupt */
4922         i40e_pf_disable_irq0(hw);
4923
4924         /* read out interrupt causes */
4925         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4926
4927         /* No interrupt event indicated */
4928         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4929                 PMD_DRV_LOG(INFO, "No interrupt event");
4930                 goto done;
4931         }
4932 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4933         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4934                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4935         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4936                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4937         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4938                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4939         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4940                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4941         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4942                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4943         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4944                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4945         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4946                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4947 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4948
4949         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4950                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4951                 i40e_dev_handle_vfr_event(dev);
4952         }
4953         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4954                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4955                 i40e_dev_handle_aq_msg(dev);
4956         }
4957
4958         /* Link Status Change interrupt */
4959         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4960 #define I40E_US_PER_SECOND 1000000
4961                 struct rte_eth_link link;
4962
4963                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4964                 memset(&link, 0, sizeof(link));
4965                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4966                 i40e_dev_link_update(dev, 0);
4967
4968                 /*
4969                  * For link up interrupt, it needs to wait 1 second to let the
4970                  * hardware be a stable state. Otherwise several consecutive
4971                  * interrupts can be observed.
4972                  * For link down interrupt, no need to wait.
4973                  */
4974                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4975                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4976                         return;
4977                 else
4978                         _rte_eth_dev_callback_process(dev,
4979                                 RTE_ETH_EVENT_INTR_LSC);
4980         }
4981
4982 done:
4983         /* Enable interrupt */
4984         i40e_pf_enable_irq0(hw);
4985         rte_intr_enable(&(dev->pci_dev->intr_handle));
4986 }
4987
4988 static int
4989 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4990                          struct i40e_macvlan_filter *filter,
4991                          int total)
4992 {
4993         int ele_num, ele_buff_size;
4994         int num, actual_num, i;
4995         uint16_t flags;
4996         int ret = I40E_SUCCESS;
4997         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4998         struct i40e_aqc_add_macvlan_element_data *req_list;
4999
5000         if (filter == NULL  || total == 0)
5001                 return I40E_ERR_PARAM;
5002         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5003         ele_buff_size = hw->aq.asq_buf_size;
5004
5005         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5006         if (req_list == NULL) {
5007                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5008                 return I40E_ERR_NO_MEMORY;
5009         }
5010
5011         num = 0;
5012         do {
5013                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5014                 memset(req_list, 0, ele_buff_size);
5015
5016                 for (i = 0; i < actual_num; i++) {
5017                         (void)rte_memcpy(req_list[i].mac_addr,
5018                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5019                         req_list[i].vlan_tag =
5020                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5021
5022                         switch (filter[num + i].filter_type) {
5023                         case RTE_MAC_PERFECT_MATCH:
5024                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5025                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5026                                 break;
5027                         case RTE_MACVLAN_PERFECT_MATCH:
5028                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5029                                 break;
5030                         case RTE_MAC_HASH_MATCH:
5031                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5032                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5033                                 break;
5034                         case RTE_MACVLAN_HASH_MATCH:
5035                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5036                                 break;
5037                         default:
5038                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5039                                 ret = I40E_ERR_PARAM;
5040                                 goto DONE;
5041                         }
5042
5043                         req_list[i].queue_number = 0;
5044
5045                         req_list[i].flags = rte_cpu_to_le_16(flags);
5046                 }
5047
5048                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5049                                                 actual_num, NULL);
5050                 if (ret != I40E_SUCCESS) {
5051                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5052                         goto DONE;
5053                 }
5054                 num += actual_num;
5055         } while (num < total);
5056
5057 DONE:
5058         rte_free(req_list);
5059         return ret;
5060 }
5061
5062 static int
5063 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5064                             struct i40e_macvlan_filter *filter,
5065                             int total)
5066 {
5067         int ele_num, ele_buff_size;
5068         int num, actual_num, i;
5069         uint16_t flags;
5070         int ret = I40E_SUCCESS;
5071         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5072         struct i40e_aqc_remove_macvlan_element_data *req_list;
5073
5074         if (filter == NULL  || total == 0)
5075                 return I40E_ERR_PARAM;
5076
5077         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5078         ele_buff_size = hw->aq.asq_buf_size;
5079
5080         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5081         if (req_list == NULL) {
5082                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5083                 return I40E_ERR_NO_MEMORY;
5084         }
5085
5086         num = 0;
5087         do {
5088                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5089                 memset(req_list, 0, ele_buff_size);
5090
5091                 for (i = 0; i < actual_num; i++) {
5092                         (void)rte_memcpy(req_list[i].mac_addr,
5093                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5094                         req_list[i].vlan_tag =
5095                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5096
5097                         switch (filter[num + i].filter_type) {
5098                         case RTE_MAC_PERFECT_MATCH:
5099                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5100                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5101                                 break;
5102                         case RTE_MACVLAN_PERFECT_MATCH:
5103                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5104                                 break;
5105                         case RTE_MAC_HASH_MATCH:
5106                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5107                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5108                                 break;
5109                         case RTE_MACVLAN_HASH_MATCH:
5110                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5111                                 break;
5112                         default:
5113                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5114                                 ret = I40E_ERR_PARAM;
5115                                 goto DONE;
5116                         }
5117                         req_list[i].flags = rte_cpu_to_le_16(flags);
5118                 }
5119
5120                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5121                                                 actual_num, NULL);
5122                 if (ret != I40E_SUCCESS) {
5123                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5124                         goto DONE;
5125                 }
5126                 num += actual_num;
5127         } while (num < total);
5128
5129 DONE:
5130         rte_free(req_list);
5131         return ret;
5132 }
5133
5134 /* Find out specific MAC filter */
5135 static struct i40e_mac_filter *
5136 i40e_find_mac_filter(struct i40e_vsi *vsi,
5137                          struct ether_addr *macaddr)
5138 {
5139         struct i40e_mac_filter *f;
5140
5141         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5142                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5143                         return f;
5144         }
5145
5146         return NULL;
5147 }
5148
5149 static bool
5150 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5151                          uint16_t vlan_id)
5152 {
5153         uint32_t vid_idx, vid_bit;
5154
5155         if (vlan_id > ETH_VLAN_ID_MAX)
5156                 return 0;
5157
5158         vid_idx = I40E_VFTA_IDX(vlan_id);
5159         vid_bit = I40E_VFTA_BIT(vlan_id);
5160
5161         if (vsi->vfta[vid_idx] & vid_bit)
5162                 return 1;
5163         else
5164                 return 0;
5165 }
5166
5167 static void
5168 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5169                          uint16_t vlan_id, bool on)
5170 {
5171         uint32_t vid_idx, vid_bit;
5172
5173         if (vlan_id > ETH_VLAN_ID_MAX)
5174                 return;
5175
5176         vid_idx = I40E_VFTA_IDX(vlan_id);
5177         vid_bit = I40E_VFTA_BIT(vlan_id);
5178
5179         if (on)
5180                 vsi->vfta[vid_idx] |= vid_bit;
5181         else
5182                 vsi->vfta[vid_idx] &= ~vid_bit;
5183 }
5184
5185 /**
5186  * Find all vlan options for specific mac addr,
5187  * return with actual vlan found.
5188  */
5189 static inline int
5190 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5191                            struct i40e_macvlan_filter *mv_f,
5192                            int num, struct ether_addr *addr)
5193 {
5194         int i;
5195         uint32_t j, k;
5196
5197         /**
5198          * Not to use i40e_find_vlan_filter to decrease the loop time,
5199          * although the code looks complex.
5200           */
5201         if (num < vsi->vlan_num)
5202                 return I40E_ERR_PARAM;
5203
5204         i = 0;
5205         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5206                 if (vsi->vfta[j]) {
5207                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5208                                 if (vsi->vfta[j] & (1 << k)) {
5209                                         if (i > num - 1) {
5210                                                 PMD_DRV_LOG(ERR, "vlan number "
5211                                                             "not match");
5212                                                 return I40E_ERR_PARAM;
5213                                         }
5214                                         (void)rte_memcpy(&mv_f[i].macaddr,
5215                                                         addr, ETH_ADDR_LEN);
5216                                         mv_f[i].vlan_id =
5217                                                 j * I40E_UINT32_BIT_SIZE + k;
5218                                         i++;
5219                                 }
5220                         }
5221                 }
5222         }
5223         return I40E_SUCCESS;
5224 }
5225
5226 static inline int
5227 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5228                            struct i40e_macvlan_filter *mv_f,
5229                            int num,
5230                            uint16_t vlan)
5231 {
5232         int i = 0;
5233         struct i40e_mac_filter *f;
5234
5235         if (num < vsi->mac_num)
5236                 return I40E_ERR_PARAM;
5237
5238         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5239                 if (i > num - 1) {
5240                         PMD_DRV_LOG(ERR, "buffer number not match");
5241                         return I40E_ERR_PARAM;
5242                 }
5243                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5244                                 ETH_ADDR_LEN);
5245                 mv_f[i].vlan_id = vlan;
5246                 mv_f[i].filter_type = f->mac_info.filter_type;
5247                 i++;
5248         }
5249
5250         return I40E_SUCCESS;
5251 }
5252
5253 static int
5254 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5255 {
5256         int i, num;
5257         struct i40e_mac_filter *f;
5258         struct i40e_macvlan_filter *mv_f;
5259         int ret = I40E_SUCCESS;
5260
5261         if (vsi == NULL || vsi->mac_num == 0)
5262                 return I40E_ERR_PARAM;
5263
5264         /* Case that no vlan is set */
5265         if (vsi->vlan_num == 0)
5266                 num = vsi->mac_num;
5267         else
5268                 num = vsi->mac_num * vsi->vlan_num;
5269
5270         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5271         if (mv_f == NULL) {
5272                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5273                 return I40E_ERR_NO_MEMORY;
5274         }
5275
5276         i = 0;
5277         if (vsi->vlan_num == 0) {
5278                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5279                         (void)rte_memcpy(&mv_f[i].macaddr,
5280                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5281                         mv_f[i].vlan_id = 0;
5282                         i++;
5283                 }
5284         } else {
5285                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5286                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5287                                         vsi->vlan_num, &f->mac_info.mac_addr);
5288                         if (ret != I40E_SUCCESS)
5289                                 goto DONE;
5290                         i += vsi->vlan_num;
5291                 }
5292         }
5293
5294         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5295 DONE:
5296         rte_free(mv_f);
5297
5298         return ret;
5299 }
5300
5301 int
5302 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5303 {
5304         struct i40e_macvlan_filter *mv_f;
5305         int mac_num;
5306         int ret = I40E_SUCCESS;
5307
5308         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5309                 return I40E_ERR_PARAM;
5310
5311         /* If it's already set, just return */
5312         if (i40e_find_vlan_filter(vsi,vlan))
5313                 return I40E_SUCCESS;
5314
5315         mac_num = vsi->mac_num;
5316
5317         if (mac_num == 0) {
5318                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5319                 return I40E_ERR_PARAM;
5320         }
5321
5322         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5323
5324         if (mv_f == NULL) {
5325                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5326                 return I40E_ERR_NO_MEMORY;
5327         }
5328
5329         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5330
5331         if (ret != I40E_SUCCESS)
5332                 goto DONE;
5333
5334         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5335
5336         if (ret != I40E_SUCCESS)
5337                 goto DONE;
5338
5339         i40e_set_vlan_filter(vsi, vlan, 1);
5340
5341         vsi->vlan_num++;
5342         ret = I40E_SUCCESS;
5343 DONE:
5344         rte_free(mv_f);
5345         return ret;
5346 }
5347
5348 int
5349 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5350 {
5351         struct i40e_macvlan_filter *mv_f;
5352         int mac_num;
5353         int ret = I40E_SUCCESS;
5354
5355         /**
5356          * Vlan 0 is the generic filter for untagged packets
5357          * and can't be removed.
5358          */
5359         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5360                 return I40E_ERR_PARAM;
5361
5362         /* If can't find it, just return */
5363         if (!i40e_find_vlan_filter(vsi, vlan))
5364                 return I40E_ERR_PARAM;
5365
5366         mac_num = vsi->mac_num;
5367
5368         if (mac_num == 0) {
5369                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5370                 return I40E_ERR_PARAM;
5371         }
5372
5373         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5374
5375         if (mv_f == NULL) {
5376                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5377                 return I40E_ERR_NO_MEMORY;
5378         }
5379
5380         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5381
5382         if (ret != I40E_SUCCESS)
5383                 goto DONE;
5384
5385         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5386
5387         if (ret != I40E_SUCCESS)
5388                 goto DONE;
5389
5390         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5391         if (vsi->vlan_num == 1) {
5392                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5393                 if (ret != I40E_SUCCESS)
5394                         goto DONE;
5395
5396                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5397                 if (ret != I40E_SUCCESS)
5398                         goto DONE;
5399         }
5400
5401         i40e_set_vlan_filter(vsi, vlan, 0);
5402
5403         vsi->vlan_num--;
5404         ret = I40E_SUCCESS;
5405 DONE:
5406         rte_free(mv_f);
5407         return ret;
5408 }
5409
5410 int
5411 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5412 {
5413         struct i40e_mac_filter *f;
5414         struct i40e_macvlan_filter *mv_f;
5415         int i, vlan_num = 0;
5416         int ret = I40E_SUCCESS;
5417
5418         /* If it's add and we've config it, return */
5419         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5420         if (f != NULL)
5421                 return I40E_SUCCESS;
5422         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5423                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5424
5425                 /**
5426                  * If vlan_num is 0, that's the first time to add mac,
5427                  * set mask for vlan_id 0.
5428                  */
5429                 if (vsi->vlan_num == 0) {
5430                         i40e_set_vlan_filter(vsi, 0, 1);
5431                         vsi->vlan_num = 1;
5432                 }
5433                 vlan_num = vsi->vlan_num;
5434         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5435                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5436                 vlan_num = 1;
5437
5438         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5439         if (mv_f == NULL) {
5440                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5441                 return I40E_ERR_NO_MEMORY;
5442         }
5443
5444         for (i = 0; i < vlan_num; i++) {
5445                 mv_f[i].filter_type = mac_filter->filter_type;
5446                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5447                                 ETH_ADDR_LEN);
5448         }
5449
5450         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5451                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5452                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5453                                         &mac_filter->mac_addr);
5454                 if (ret != I40E_SUCCESS)
5455                         goto DONE;
5456         }
5457
5458         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5459         if (ret != I40E_SUCCESS)
5460                 goto DONE;
5461
5462         /* Add the mac addr into mac list */
5463         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5464         if (f == NULL) {
5465                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5466                 ret = I40E_ERR_NO_MEMORY;
5467                 goto DONE;
5468         }
5469         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5470                         ETH_ADDR_LEN);
5471         f->mac_info.filter_type = mac_filter->filter_type;
5472         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5473         vsi->mac_num++;
5474
5475         ret = I40E_SUCCESS;
5476 DONE:
5477         rte_free(mv_f);
5478
5479         return ret;
5480 }
5481
5482 int
5483 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5484 {
5485         struct i40e_mac_filter *f;
5486         struct i40e_macvlan_filter *mv_f;
5487         int i, vlan_num;
5488         enum rte_mac_filter_type filter_type;
5489         int ret = I40E_SUCCESS;
5490
5491         /* Can't find it, return an error */
5492         f = i40e_find_mac_filter(vsi, addr);
5493         if (f == NULL)
5494                 return I40E_ERR_PARAM;
5495
5496         vlan_num = vsi->vlan_num;
5497         filter_type = f->mac_info.filter_type;
5498         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5499                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5500                 if (vlan_num == 0) {
5501                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5502                         return I40E_ERR_PARAM;
5503                 }
5504         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5505                         filter_type == RTE_MAC_HASH_MATCH)
5506                 vlan_num = 1;
5507
5508         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5509         if (mv_f == NULL) {
5510                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5511                 return I40E_ERR_NO_MEMORY;
5512         }
5513
5514         for (i = 0; i < vlan_num; i++) {
5515                 mv_f[i].filter_type = filter_type;
5516                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5517                                 ETH_ADDR_LEN);
5518         }
5519         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5520                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5521                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5522                 if (ret != I40E_SUCCESS)
5523                         goto DONE;
5524         }
5525
5526         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5527         if (ret != I40E_SUCCESS)
5528                 goto DONE;
5529
5530         /* Remove the mac addr into mac list */
5531         TAILQ_REMOVE(&vsi->mac_list, f, next);
5532         rte_free(f);
5533         vsi->mac_num--;
5534
5535         ret = I40E_SUCCESS;
5536 DONE:
5537         rte_free(mv_f);
5538         return ret;
5539 }
5540
5541 /* Configure hash enable flags for RSS */
5542 uint64_t
5543 i40e_config_hena(uint64_t flags)
5544 {
5545         uint64_t hena = 0;
5546
5547         if (!flags)
5548                 return hena;
5549
5550         if (flags & ETH_RSS_FRAG_IPV4)
5551                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5552         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5553                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5554         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5555                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5556         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5557                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5558         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5559                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5560         if (flags & ETH_RSS_FRAG_IPV6)
5561                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5562         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5563                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5564         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5565                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5566         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5567                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5568         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5569                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5570         if (flags & ETH_RSS_L2_PAYLOAD)
5571                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5572
5573         return hena;
5574 }
5575
5576 /* Parse the hash enable flags */
5577 uint64_t
5578 i40e_parse_hena(uint64_t flags)
5579 {
5580         uint64_t rss_hf = 0;
5581
5582         if (!flags)
5583                 return rss_hf;
5584         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5585                 rss_hf |= ETH_RSS_FRAG_IPV4;
5586         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5587                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5588         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5589                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5590         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5591                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5592         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5593                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5594         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5595                 rss_hf |= ETH_RSS_FRAG_IPV6;
5596         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5597                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5598         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5599                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5600         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5601                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5602         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5603                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5604         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5605                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5606
5607         return rss_hf;
5608 }
5609
5610 /* Disable RSS */
5611 static void
5612 i40e_pf_disable_rss(struct i40e_pf *pf)
5613 {
5614         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5615         uint64_t hena;
5616
5617         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5618         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5619         hena &= ~I40E_RSS_HENA_ALL;
5620         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5621         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5622         I40E_WRITE_FLUSH(hw);
5623 }
5624
5625 static int
5626 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5627 {
5628         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5629         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5630         int ret = 0;
5631
5632         if (!key || key_len == 0) {
5633                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5634                 return 0;
5635         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5636                 sizeof(uint32_t)) {
5637                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5638                 return -EINVAL;
5639         }
5640
5641         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5642                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5643                         (struct i40e_aqc_get_set_rss_key_data *)key;
5644
5645                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5646                 if (ret)
5647                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5648                                      "via AQ");
5649         } else {
5650                 uint32_t *hash_key = (uint32_t *)key;
5651                 uint16_t i;
5652
5653                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5654                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5655                 I40E_WRITE_FLUSH(hw);
5656         }
5657
5658         return ret;
5659 }
5660
5661 static int
5662 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5663 {
5664         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5665         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5666         int ret;
5667
5668         if (!key || !key_len)
5669                 return -EINVAL;
5670
5671         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5672                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5673                         (struct i40e_aqc_get_set_rss_key_data *)key);
5674                 if (ret) {
5675                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5676                         return ret;
5677                 }
5678         } else {
5679                 uint32_t *key_dw = (uint32_t *)key;
5680                 uint16_t i;
5681
5682                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5683                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5684         }
5685         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5686
5687         return 0;
5688 }
5689
5690 static int
5691 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5692 {
5693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5694         uint64_t rss_hf;
5695         uint64_t hena;
5696         int ret;
5697
5698         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5699                                rss_conf->rss_key_len);
5700         if (ret)
5701                 return ret;
5702
5703         rss_hf = rss_conf->rss_hf;
5704         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5705         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5706         hena &= ~I40E_RSS_HENA_ALL;
5707         hena |= i40e_config_hena(rss_hf);
5708         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5709         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5710         I40E_WRITE_FLUSH(hw);
5711
5712         return 0;
5713 }
5714
5715 static int
5716 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5717                          struct rte_eth_rss_conf *rss_conf)
5718 {
5719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5721         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5722         uint64_t hena;
5723
5724         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5725         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5726         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5727                 if (rss_hf != 0) /* Enable RSS */
5728                         return -EINVAL;
5729                 return 0; /* Nothing to do */
5730         }
5731         /* RSS enabled */
5732         if (rss_hf == 0) /* Disable RSS */
5733                 return -EINVAL;
5734
5735         return i40e_hw_rss_hash_set(pf, rss_conf);
5736 }
5737
5738 static int
5739 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5740                            struct rte_eth_rss_conf *rss_conf)
5741 {
5742         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5743         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5744         uint64_t hena;
5745
5746         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5747                          &rss_conf->rss_key_len);
5748
5749         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5750         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5751         rss_conf->rss_hf = i40e_parse_hena(hena);
5752
5753         return 0;
5754 }
5755
5756 static int
5757 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5758 {
5759         switch (filter_type) {
5760         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5761                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5762                 break;
5763         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5764                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5765                 break;
5766         case RTE_TUNNEL_FILTER_IMAC_TENID:
5767                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5768                 break;
5769         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5770                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5771                 break;
5772         case ETH_TUNNEL_FILTER_IMAC:
5773                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5774                 break;
5775         default:
5776                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5777                 return -EINVAL;
5778         }
5779
5780         return 0;
5781 }
5782
5783 static int
5784 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5785                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5786                         uint8_t add)
5787 {
5788         uint16_t ip_type;
5789         uint8_t tun_type = 0;
5790         int val, ret = 0;
5791         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5792         struct i40e_vsi *vsi = pf->main_vsi;
5793         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5794         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5795
5796         cld_filter = rte_zmalloc("tunnel_filter",
5797                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5798                 0);
5799
5800         if (NULL == cld_filter) {
5801                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5802                 return -EINVAL;
5803         }
5804         pfilter = cld_filter;
5805
5806         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5807                         sizeof(struct ether_addr));
5808         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5809                         sizeof(struct ether_addr));
5810
5811         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5812         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5813                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5814                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5815                                 &tunnel_filter->ip_addr,
5816                                 sizeof(pfilter->ipaddr.v4.data));
5817         } else {
5818                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5819                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5820                                 &tunnel_filter->ip_addr,
5821                                 sizeof(pfilter->ipaddr.v6.data));
5822         }
5823
5824         /* check tunneled type */
5825         switch (tunnel_filter->tunnel_type) {
5826         case RTE_TUNNEL_TYPE_VXLAN:
5827                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5828                 break;
5829         case RTE_TUNNEL_TYPE_NVGRE:
5830                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5831                 break;
5832         default:
5833                 /* Other tunnel types is not supported. */
5834                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5835                 rte_free(cld_filter);
5836                 return -EINVAL;
5837         }
5838
5839         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5840                                                 &pfilter->flags);
5841         if (val < 0) {
5842                 rte_free(cld_filter);
5843                 return -EINVAL;
5844         }
5845
5846         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5847                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5848         pfilter->tenant_id = tunnel_filter->tenant_id;
5849         pfilter->queue_number = tunnel_filter->queue_id;
5850
5851         if (add)
5852                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5853         else
5854                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5855                                                 cld_filter, 1);
5856
5857         rte_free(cld_filter);
5858         return ret;
5859 }
5860
5861 static int
5862 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5863 {
5864         uint8_t i;
5865
5866         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5867                 if (pf->vxlan_ports[i] == port)
5868                         return i;
5869         }
5870
5871         return -1;
5872 }
5873
5874 static int
5875 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5876 {
5877         int  idx, ret;
5878         uint8_t filter_idx;
5879         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5880
5881         idx = i40e_get_vxlan_port_idx(pf, port);
5882
5883         /* Check if port already exists */
5884         if (idx >= 0) {
5885                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5886                 return -EINVAL;
5887         }
5888
5889         /* Now check if there is space to add the new port */
5890         idx = i40e_get_vxlan_port_idx(pf, 0);
5891         if (idx < 0) {
5892                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5893                         "not adding port %d", port);
5894                 return -ENOSPC;
5895         }
5896
5897         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5898                                         &filter_idx, NULL);
5899         if (ret < 0) {
5900                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5901                 return -1;
5902         }
5903
5904         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5905                          port,  filter_idx);
5906
5907         /* New port: add it and mark its index in the bitmap */
5908         pf->vxlan_ports[idx] = port;
5909         pf->vxlan_bitmap |= (1 << idx);
5910
5911         if (!(pf->flags & I40E_FLAG_VXLAN))
5912                 pf->flags |= I40E_FLAG_VXLAN;
5913
5914         return 0;
5915 }
5916
5917 static int
5918 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5919 {
5920         int idx;
5921         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5922
5923         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5924                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5925                 return -EINVAL;
5926         }
5927
5928         idx = i40e_get_vxlan_port_idx(pf, port);
5929
5930         if (idx < 0) {
5931                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5932                 return -EINVAL;
5933         }
5934
5935         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5936                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5937                 return -1;
5938         }
5939
5940         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5941                         port, idx);
5942
5943         pf->vxlan_ports[idx] = 0;
5944         pf->vxlan_bitmap &= ~(1 << idx);
5945
5946         if (!pf->vxlan_bitmap)
5947                 pf->flags &= ~I40E_FLAG_VXLAN;
5948
5949         return 0;
5950 }
5951
5952 /* Add UDP tunneling port */
5953 static int
5954 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5955                         struct rte_eth_udp_tunnel *udp_tunnel)
5956 {
5957         int ret = 0;
5958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5959
5960         if (udp_tunnel == NULL)
5961                 return -EINVAL;
5962
5963         switch (udp_tunnel->prot_type) {
5964         case RTE_TUNNEL_TYPE_VXLAN:
5965                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5966                 break;
5967
5968         case RTE_TUNNEL_TYPE_GENEVE:
5969         case RTE_TUNNEL_TYPE_TEREDO:
5970                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5971                 ret = -1;
5972                 break;
5973
5974         default:
5975                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5976                 ret = -1;
5977                 break;
5978         }
5979
5980         return ret;
5981 }
5982
5983 /* Remove UDP tunneling port */
5984 static int
5985 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5986                         struct rte_eth_udp_tunnel *udp_tunnel)
5987 {
5988         int ret = 0;
5989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5990
5991         if (udp_tunnel == NULL)
5992                 return -EINVAL;
5993
5994         switch (udp_tunnel->prot_type) {
5995         case RTE_TUNNEL_TYPE_VXLAN:
5996                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5997                 break;
5998         case RTE_TUNNEL_TYPE_GENEVE:
5999         case RTE_TUNNEL_TYPE_TEREDO:
6000                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6001                 ret = -1;
6002                 break;
6003         default:
6004                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6005                 ret = -1;
6006                 break;
6007         }
6008
6009         return ret;
6010 }
6011
6012 /* Calculate the maximum number of contiguous PF queues that are configured */
6013 static int
6014 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6015 {
6016         struct rte_eth_dev_data *data = pf->dev_data;
6017         int i, num;
6018         struct i40e_rx_queue *rxq;
6019
6020         num = 0;
6021         for (i = 0; i < pf->lan_nb_qps; i++) {
6022                 rxq = data->rx_queues[i];
6023                 if (rxq && rxq->q_set)
6024                         num++;
6025                 else
6026                         break;
6027         }
6028
6029         return num;
6030 }
6031
6032 /* Configure RSS */
6033 static int
6034 i40e_pf_config_rss(struct i40e_pf *pf)
6035 {
6036         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6037         struct rte_eth_rss_conf rss_conf;
6038         uint32_t i, lut = 0;
6039         uint16_t j, num;
6040
6041         /*
6042          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6043          * It's necessary to calulate the actual PF queues that are configured.
6044          */
6045         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6046                 num = i40e_pf_calc_configured_queues_num(pf);
6047         else
6048                 num = pf->dev_data->nb_rx_queues;
6049
6050         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6051         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6052                         num);
6053
6054         if (num == 0) {
6055                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6056                 return -ENOTSUP;
6057         }
6058
6059         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6060                 if (j == num)
6061                         j = 0;
6062                 lut = (lut << 8) | (j & ((0x1 <<
6063                         hw->func_caps.rss_table_entry_width) - 1));
6064                 if ((i & 3) == 3)
6065                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6066         }
6067
6068         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6069         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6070                 i40e_pf_disable_rss(pf);
6071                 return 0;
6072         }
6073         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6074                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6075                 /* Random default keys */
6076                 static uint32_t rss_key_default[] = {0x6b793944,
6077                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6078                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6079                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6080
6081                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6082                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6083                                                         sizeof(uint32_t);
6084         }
6085
6086         return i40e_hw_rss_hash_set(pf, &rss_conf);
6087 }
6088
6089 static int
6090 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6091                                struct rte_eth_tunnel_filter_conf *filter)
6092 {
6093         if (pf == NULL || filter == NULL) {
6094                 PMD_DRV_LOG(ERR, "Invalid parameter");
6095                 return -EINVAL;
6096         }
6097
6098         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6099                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6100                 return -EINVAL;
6101         }
6102
6103         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6104                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6105                 return -EINVAL;
6106         }
6107
6108         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6109                 (is_zero_ether_addr(filter->outer_mac))) {
6110                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6111                 return -EINVAL;
6112         }
6113
6114         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6115                 (is_zero_ether_addr(filter->inner_mac))) {
6116                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6117                 return -EINVAL;
6118         }
6119
6120         return 0;
6121 }
6122
6123 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6124 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6125 static int
6126 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6127 {
6128         uint32_t val, reg;
6129         int ret = -EINVAL;
6130
6131         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6132         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6133
6134         if (len == 3) {
6135                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6136         } else if (len == 4) {
6137                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6138         } else {
6139                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6140                 return ret;
6141         }
6142
6143         if (reg != val) {
6144                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6145                                                    reg, NULL);
6146                 if (ret != 0)
6147                         return ret;
6148         } else {
6149                 ret = 0;
6150         }
6151         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6152                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6153
6154         return ret;
6155 }
6156
6157 static int
6158 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6159 {
6160         int ret = -EINVAL;
6161
6162         if (!hw || !cfg)
6163                 return -EINVAL;
6164
6165         switch (cfg->cfg_type) {
6166         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6167                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6168                 break;
6169         default:
6170                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6171                 break;
6172         }
6173
6174         return ret;
6175 }
6176
6177 static int
6178 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6179                                enum rte_filter_op filter_op,
6180                                void *arg)
6181 {
6182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6183         int ret = I40E_ERR_PARAM;
6184
6185         switch (filter_op) {
6186         case RTE_ETH_FILTER_SET:
6187                 ret = i40e_dev_global_config_set(hw,
6188                         (struct rte_eth_global_cfg *)arg);
6189                 break;
6190         default:
6191                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6192                 break;
6193         }
6194
6195         return ret;
6196 }
6197
6198 static int
6199 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6200                           enum rte_filter_op filter_op,
6201                           void *arg)
6202 {
6203         struct rte_eth_tunnel_filter_conf *filter;
6204         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6205         int ret = I40E_SUCCESS;
6206
6207         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6208
6209         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6210                 return I40E_ERR_PARAM;
6211
6212         switch (filter_op) {
6213         case RTE_ETH_FILTER_NOP:
6214                 if (!(pf->flags & I40E_FLAG_VXLAN))
6215                         ret = I40E_NOT_SUPPORTED;
6216                 break;
6217         case RTE_ETH_FILTER_ADD:
6218                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6219                 break;
6220         case RTE_ETH_FILTER_DELETE:
6221                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6222                 break;
6223         default:
6224                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6225                 ret = I40E_ERR_PARAM;
6226                 break;
6227         }
6228
6229         return ret;
6230 }
6231
6232 static int
6233 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6234 {
6235         int ret = 0;
6236         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6237
6238         /* RSS setup */
6239         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6240                 ret = i40e_pf_config_rss(pf);
6241         else
6242                 i40e_pf_disable_rss(pf);
6243
6244         return ret;
6245 }
6246
6247 /* Get the symmetric hash enable configurations per port */
6248 static void
6249 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6250 {
6251         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6252
6253         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6254 }
6255
6256 /* Set the symmetric hash enable configurations per port */
6257 static void
6258 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6259 {
6260         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6261
6262         if (enable > 0) {
6263                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6264                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6265                                                         "been enabled");
6266                         return;
6267                 }
6268                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6269         } else {
6270                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6271                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6272                                                         "been disabled");
6273                         return;
6274                 }
6275                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6276         }
6277         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6278         I40E_WRITE_FLUSH(hw);
6279 }
6280
6281 /*
6282  * Get global configurations of hash function type and symmetric hash enable
6283  * per flow type (pctype). Note that global configuration means it affects all
6284  * the ports on the same NIC.
6285  */
6286 static int
6287 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6288                                    struct rte_eth_hash_global_conf *g_cfg)
6289 {
6290         uint32_t reg, mask = I40E_FLOW_TYPES;
6291         uint16_t i;
6292         enum i40e_filter_pctype pctype;
6293
6294         memset(g_cfg, 0, sizeof(*g_cfg));
6295         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6296         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6297                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6298         else
6299                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6300         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6301                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6302
6303         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6304                 if (!(mask & (1UL << i)))
6305                         continue;
6306                 mask &= ~(1UL << i);
6307                 /* Bit set indicats the coresponding flow type is supported */
6308                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6309                 pctype = i40e_flowtype_to_pctype(i);
6310                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6311                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6312                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6313         }
6314
6315         return 0;
6316 }
6317
6318 static int
6319 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6320 {
6321         uint32_t i;
6322         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6323
6324         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6325                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6326                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6327                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6328                                                 g_cfg->hash_func);
6329                 return -EINVAL;
6330         }
6331
6332         /*
6333          * As i40e supports less than 32 flow types, only first 32 bits need to
6334          * be checked.
6335          */
6336         mask0 = g_cfg->valid_bit_mask[0];
6337         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6338                 if (i == 0) {
6339                         /* Check if any unsupported flow type configured */
6340                         if ((mask0 | i40e_mask) ^ i40e_mask)
6341                                 goto mask_err;
6342                 } else {
6343                         if (g_cfg->valid_bit_mask[i])
6344                                 goto mask_err;
6345                 }
6346         }
6347
6348         return 0;
6349
6350 mask_err:
6351         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6352
6353         return -EINVAL;
6354 }
6355
6356 /*
6357  * Set global configurations of hash function type and symmetric hash enable
6358  * per flow type (pctype). Note any modifying global configuration will affect
6359  * all the ports on the same NIC.
6360  */
6361 static int
6362 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6363                                    struct rte_eth_hash_global_conf *g_cfg)
6364 {
6365         int ret;
6366         uint16_t i;
6367         uint32_t reg;
6368         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6369         enum i40e_filter_pctype pctype;
6370
6371         /* Check the input parameters */
6372         ret = i40e_hash_global_config_check(g_cfg);
6373         if (ret < 0)
6374                 return ret;
6375
6376         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6377                 if (!(mask0 & (1UL << i)))
6378                         continue;
6379                 mask0 &= ~(1UL << i);
6380                 pctype = i40e_flowtype_to_pctype(i);
6381                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6382                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6383                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6384         }
6385
6386         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6387         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6388                 /* Toeplitz */
6389                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6390                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6391                                                                 "Toeplitz");
6392                         goto out;
6393                 }
6394                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6395         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6396                 /* Simple XOR */
6397                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6398                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6399                                                         "Simple XOR");
6400                         goto out;
6401                 }
6402                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6403         } else
6404                 /* Use the default, and keep it as it is */
6405                 goto out;
6406
6407         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6408
6409 out:
6410         I40E_WRITE_FLUSH(hw);
6411
6412         return 0;
6413 }
6414
6415 /**
6416  * Valid input sets for hash and flow director filters per PCTYPE
6417  */
6418 static uint64_t
6419 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6420                 enum rte_filter_type filter)
6421 {
6422         uint64_t valid;
6423
6424         static const uint64_t valid_hash_inset_table[] = {
6425                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6426                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6427                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6428                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6429                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6430                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6431                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6432                         I40E_INSET_FLEX_PAYLOAD,
6433                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6434                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6435                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6436                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6437                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6438                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6439                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6440                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6441                         I40E_INSET_FLEX_PAYLOAD,
6442                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6443                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6444                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6445                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6446                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6447                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6448                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6449                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6450                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6451                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6452                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6453                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6454                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6455                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6456                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6457                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6458                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6459                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6460                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6461                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6462                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6463                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6464                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6465                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6466                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6467                         I40E_INSET_FLEX_PAYLOAD,
6468                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6469                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6470                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6471                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6472                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6473                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6474                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6475                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6476                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6477                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6478                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6479                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6480                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6481                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6482                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6483                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6484                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6485                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6486                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6487                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6488                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6489                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6490                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6491                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6492                         I40E_INSET_FLEX_PAYLOAD,
6493                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6494                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6495                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6496                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6497                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6498                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6499                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6500                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6501                         I40E_INSET_FLEX_PAYLOAD,
6502                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6503                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6504                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6505                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6506                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6507                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6508                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6509                         I40E_INSET_FLEX_PAYLOAD,
6510                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6511                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6512                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6513                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6514                         I40E_INSET_FLEX_PAYLOAD,
6515         };
6516
6517         /**
6518          * Flow director supports only fields defined in
6519          * union rte_eth_fdir_flow.
6520          */
6521         static const uint64_t valid_fdir_inset_table[] = {
6522                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6523                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6524                 I40E_INSET_FLEX_PAYLOAD,
6525                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6526                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6527                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6528                 I40E_INSET_FLEX_PAYLOAD,
6529                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6530                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6531                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6532                 I40E_INSET_FLEX_PAYLOAD,
6533                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6534                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6535                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6536                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6537                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6538                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6539                 I40E_INSET_FLEX_PAYLOAD,
6540                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6541                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6542                 I40E_INSET_FLEX_PAYLOAD,
6543                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6544                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6545                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6546                 I40E_INSET_FLEX_PAYLOAD,
6547                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6548                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6549                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6550                 I40E_INSET_FLEX_PAYLOAD,
6551                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6552                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6553                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6554                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6555                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6556                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6557                 I40E_INSET_FLEX_PAYLOAD,
6558                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6559                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6560         };
6561
6562         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6563                 return 0;
6564         if (filter == RTE_ETH_FILTER_HASH)
6565                 valid = valid_hash_inset_table[pctype];
6566         else
6567                 valid = valid_fdir_inset_table[pctype];
6568
6569         return valid;
6570 }
6571
6572 /**
6573  * Validate if the input set is allowed for a specific PCTYPE
6574  */
6575 static int
6576 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6577                 enum rte_filter_type filter, uint64_t inset)
6578 {
6579         uint64_t valid;
6580
6581         valid = i40e_get_valid_input_set(pctype, filter);
6582         if (inset & (~valid))
6583                 return -EINVAL;
6584
6585         return 0;
6586 }
6587
6588 /* default input set fields combination per pctype */
6589 static uint64_t
6590 i40e_get_default_input_set(uint16_t pctype)
6591 {
6592         static const uint64_t default_inset_table[] = {
6593                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6594                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6595                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6596                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6597                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6598                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6599                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6600                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6601                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6602                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6603                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6604                         I40E_INSET_SCTP_VT,
6605                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6606                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6607                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6608                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6609                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6610                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6611                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6612                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6613                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6614                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6615                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6616                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6617                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6618                         I40E_INSET_SCTP_VT,
6619                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6620                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6621                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6622                         I40E_INSET_LAST_ETHER_TYPE,
6623         };
6624
6625         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6626                 return 0;
6627
6628         return default_inset_table[pctype];
6629 }
6630
6631 /**
6632  * Parse the input set from index to logical bit masks
6633  */
6634 static int
6635 i40e_parse_input_set(uint64_t *inset,
6636                      enum i40e_filter_pctype pctype,
6637                      enum rte_eth_input_set_field *field,
6638                      uint16_t size)
6639 {
6640         uint16_t i, j;
6641         int ret = -EINVAL;
6642
6643         static const struct {
6644                 enum rte_eth_input_set_field field;
6645                 uint64_t inset;
6646         } inset_convert_table[] = {
6647                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6648                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6649                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6650                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6651                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6652                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6653                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6654                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6655                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6656                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6657                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6658                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6659                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6660                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6661                         I40E_INSET_IPV6_NEXT_HDR},
6662                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6663                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6664                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6665                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6666                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6667                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6668                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6669                         I40E_INSET_SCTP_VT},
6670                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6671                         I40E_INSET_TUNNEL_DMAC},
6672                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6673                         I40E_INSET_VLAN_TUNNEL},
6674                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6675                         I40E_INSET_TUNNEL_ID},
6676                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6677                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6678                         I40E_INSET_FLEX_PAYLOAD_W1},
6679                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6680                         I40E_INSET_FLEX_PAYLOAD_W2},
6681                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6682                         I40E_INSET_FLEX_PAYLOAD_W3},
6683                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6684                         I40E_INSET_FLEX_PAYLOAD_W4},
6685                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6686                         I40E_INSET_FLEX_PAYLOAD_W5},
6687                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6688                         I40E_INSET_FLEX_PAYLOAD_W6},
6689                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6690                         I40E_INSET_FLEX_PAYLOAD_W7},
6691                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6692                         I40E_INSET_FLEX_PAYLOAD_W8},
6693         };
6694
6695         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6696                 return ret;
6697
6698         /* Only one item allowed for default or all */
6699         if (size == 1) {
6700                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6701                         *inset = i40e_get_default_input_set(pctype);
6702                         return 0;
6703                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6704                         *inset = I40E_INSET_NONE;
6705                         return 0;
6706                 }
6707         }
6708
6709         for (i = 0, *inset = 0; i < size; i++) {
6710                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6711                         if (field[i] == inset_convert_table[j].field) {
6712                                 *inset |= inset_convert_table[j].inset;
6713                                 break;
6714                         }
6715                 }
6716
6717                 /* It contains unsupported input set, return immediately */
6718                 if (j == RTE_DIM(inset_convert_table))
6719                         return ret;
6720         }
6721
6722         return 0;
6723 }
6724
6725 /**
6726  * Translate the input set from bit masks to register aware bit masks
6727  * and vice versa
6728  */
6729 static uint64_t
6730 i40e_translate_input_set_reg(uint64_t input)
6731 {
6732         uint64_t val = 0;
6733         uint16_t i;
6734
6735         static const struct {
6736                 uint64_t inset;
6737                 uint64_t inset_reg;
6738         } inset_map[] = {
6739                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6740                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6741                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6742                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6743                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6744                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6745                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6746                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6747                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6748                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6749                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6750                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6751                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6752                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6753                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6754                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6755                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6756                 {I40E_INSET_TUNNEL_DMAC,
6757                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6758                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6759                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6760                 {I40E_INSET_TUNNEL_SRC_PORT,
6761                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6762                 {I40E_INSET_TUNNEL_DST_PORT,
6763                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6764                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6765                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6766                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6767                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6768                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6769                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6770                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6771                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6772                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6773         };
6774
6775         if (input == 0)
6776                 return val;
6777
6778         /* Translate input set to register aware inset */
6779         for (i = 0; i < RTE_DIM(inset_map); i++) {
6780                 if (input & inset_map[i].inset)
6781                         val |= inset_map[i].inset_reg;
6782         }
6783
6784         return val;
6785 }
6786
6787 static uint8_t
6788 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6789 {
6790         uint8_t i, idx = 0;
6791
6792         static const struct {
6793                 uint64_t inset;
6794                 uint32_t mask;
6795         } inset_mask_map[] = {
6796                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6797                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6798                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6799                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6800         };
6801
6802         if (!inset || !mask || !nb_elem)
6803                 return 0;
6804
6805         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6806                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6807                         mask[i] = 0;
6808                 return I40E_INSET_MASK_NUM_REG;
6809         }
6810
6811         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6812                 if (idx >= nb_elem)
6813                         break;
6814                 if (inset & inset_mask_map[i].inset) {
6815                         mask[idx] = inset_mask_map[i].mask;
6816                         idx++;
6817                 }
6818         }
6819
6820         return idx;
6821 }
6822
6823 static uint64_t
6824 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6825                             enum i40e_filter_pctype pctype)
6826 {
6827         uint64_t reg = 0;
6828
6829         if (filter == RTE_ETH_FILTER_HASH) {
6830                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6831                 reg <<= I40E_32_BIT_WIDTH;
6832                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6833         } else if (filter == RTE_ETH_FILTER_FDIR) {
6834                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6835                 reg <<= I40E_32_BIT_WIDTH;
6836                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6837         }
6838
6839         return reg;
6840 }
6841
6842 static void
6843 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6844 {
6845         uint32_t reg = I40E_READ_REG(hw, addr);
6846
6847         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6848         if (reg != val)
6849                 I40E_WRITE_REG(hw, addr, val);
6850         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6851                     (uint32_t)I40E_READ_REG(hw, addr));
6852 }
6853
6854 static int
6855 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6856                          enum i40e_filter_pctype pctype,
6857                          enum rte_filter_input_set_op op,
6858                          uint32_t *mask_reg,
6859                          uint8_t num)
6860 {
6861         uint32_t reg;
6862         uint8_t i;
6863
6864         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6865                 return -EINVAL;
6866
6867         if (op == RTE_ETH_INPUT_SET_SELECT) {
6868                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6869                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6870                                              0);
6871                         if (i >= num)
6872                                 continue;
6873                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6874                                              mask_reg[i]);
6875                 }
6876         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6877                 uint8_t j, count = 0;
6878
6879                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6880                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6881                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6882                                 count++;
6883                 }
6884                 if (count + num > I40E_INSET_MASK_NUM_REG)
6885                         return -EINVAL;
6886
6887                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6888                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6889                                              mask_reg[j]);
6890         }
6891
6892         return 0;
6893 }
6894
6895 static int
6896 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6897                        enum i40e_filter_pctype pctype,
6898                        enum rte_filter_input_set_op op,
6899                        uint32_t *mask_reg,
6900                        uint8_t num)
6901 {
6902         uint32_t reg;
6903         uint8_t i;
6904
6905         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6906                 return -EINVAL;
6907
6908         if (op == RTE_ETH_INPUT_SET_SELECT) {
6909                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6910                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6911                                              0);
6912                         if (i >= num)
6913                                 continue;
6914                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6915                                              mask_reg[i]);
6916                 }
6917         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6918                 uint8_t j, count = 0;
6919
6920                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6921                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6922                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6923                                 count++;
6924                 }
6925                 if (count + num > I40E_INSET_MASK_NUM_REG)
6926                         return -EINVAL;
6927
6928                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6929                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6930                                              mask_reg[j]);
6931         }
6932
6933         return 0;
6934 }
6935
6936 int
6937 i40e_filter_inset_select(struct i40e_hw *hw,
6938                          struct rte_eth_input_set_conf *conf,
6939                          enum rte_filter_type filter)
6940 {
6941         enum i40e_filter_pctype pctype;
6942         uint64_t inset_reg = 0, input_set;
6943         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6944         uint8_t num;
6945         int ret;
6946
6947         if (!hw || !conf) {
6948                 PMD_DRV_LOG(ERR, "Invalid pointer");
6949                 return -EFAULT;
6950         }
6951
6952         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6953         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6954                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6955                             conf->flow_type);
6956                 return -EINVAL;
6957         }
6958         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6959                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6960                 return -EINVAL;
6961         }
6962
6963         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6964                                    conf->inset_size);
6965         if (ret) {
6966                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6967                 return -EINVAL;
6968         }
6969         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6970                 PMD_DRV_LOG(ERR, "Invalid input set");
6971                 return -EINVAL;
6972         }
6973
6974         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6975                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6976         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6977                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6978                 return -EINVAL;
6979         }
6980         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6981                                            I40E_INSET_MASK_NUM_REG);
6982         inset_reg |= i40e_translate_input_set_reg(input_set);
6983
6984         if (filter == RTE_ETH_FILTER_HASH) {
6985                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
6986                                                num);
6987                 if (ret)
6988                         return -EINVAL;
6989
6990                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
6991                                       (uint32_t)(inset_reg & UINT32_MAX));
6992                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
6993                                      (uint32_t)((inset_reg >>
6994                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
6995         } else if (filter == RTE_ETH_FILTER_FDIR) {
6996                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
6997                                              num);
6998                 if (ret)
6999                         return -EINVAL;
7000
7001                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7002                                       (uint32_t)(inset_reg & UINT32_MAX));
7003                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7004                                      (uint32_t)((inset_reg >>
7005                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7006         } else {
7007                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7008                 return -EINVAL;
7009         }
7010         I40E_WRITE_FLUSH(hw);
7011
7012         return 0;
7013 }
7014
7015 static int
7016 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7017 {
7018         int ret = 0;
7019
7020         if (!hw || !info) {
7021                 PMD_DRV_LOG(ERR, "Invalid pointer");
7022                 return -EFAULT;
7023         }
7024
7025         switch (info->info_type) {
7026         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7027                 i40e_get_symmetric_hash_enable_per_port(hw,
7028                                         &(info->info.enable));
7029                 break;
7030         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7031                 ret = i40e_get_hash_filter_global_config(hw,
7032                                 &(info->info.global_conf));
7033                 break;
7034         default:
7035                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7036                                                         info->info_type);
7037                 ret = -EINVAL;
7038                 break;
7039         }
7040
7041         return ret;
7042 }
7043
7044 static int
7045 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7046 {
7047         int ret = 0;
7048
7049         if (!hw || !info) {
7050                 PMD_DRV_LOG(ERR, "Invalid pointer");
7051                 return -EFAULT;
7052         }
7053
7054         switch (info->info_type) {
7055         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7056                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7057                 break;
7058         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7059                 ret = i40e_set_hash_filter_global_config(hw,
7060                                 &(info->info.global_conf));
7061                 break;
7062         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7063                 ret = i40e_filter_inset_select(hw,
7064                                                &(info->info.input_set_conf),
7065                                                RTE_ETH_FILTER_HASH);
7066                 break;
7067
7068         default:
7069                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7070                                                         info->info_type);
7071                 ret = -EINVAL;
7072                 break;
7073         }
7074
7075         return ret;
7076 }
7077
7078 /* Operations for hash function */
7079 static int
7080 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7081                       enum rte_filter_op filter_op,
7082                       void *arg)
7083 {
7084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7085         int ret = 0;
7086
7087         switch (filter_op) {
7088         case RTE_ETH_FILTER_NOP:
7089                 break;
7090         case RTE_ETH_FILTER_GET:
7091                 ret = i40e_hash_filter_get(hw,
7092                         (struct rte_eth_hash_filter_info *)arg);
7093                 break;
7094         case RTE_ETH_FILTER_SET:
7095                 ret = i40e_hash_filter_set(hw,
7096                         (struct rte_eth_hash_filter_info *)arg);
7097                 break;
7098         default:
7099                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7100                                                                 filter_op);
7101                 ret = -ENOTSUP;
7102                 break;
7103         }
7104
7105         return ret;
7106 }
7107
7108 /*
7109  * Configure ethertype filter, which can director packet by filtering
7110  * with mac address and ether_type or only ether_type
7111  */
7112 static int
7113 i40e_ethertype_filter_set(struct i40e_pf *pf,
7114                         struct rte_eth_ethertype_filter *filter,
7115                         bool add)
7116 {
7117         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7118         struct i40e_control_filter_stats stats;
7119         uint16_t flags = 0;
7120         int ret;
7121
7122         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7123                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7124                 return -EINVAL;
7125         }
7126         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7127                 filter->ether_type == ETHER_TYPE_IPv6) {
7128                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7129                         " control packet filter.", filter->ether_type);
7130                 return -EINVAL;
7131         }
7132         if (filter->ether_type == ETHER_TYPE_VLAN)
7133                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7134                         " not supported.");
7135
7136         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7137                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7138         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7139                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7140         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7141
7142         memset(&stats, 0, sizeof(stats));
7143         ret = i40e_aq_add_rem_control_packet_filter(hw,
7144                         filter->mac_addr.addr_bytes,
7145                         filter->ether_type, flags,
7146                         pf->main_vsi->seid,
7147                         filter->queue, add, &stats, NULL);
7148
7149         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7150                          " mac_etype_used = %u, etype_used = %u,"
7151                          " mac_etype_free = %u, etype_free = %u\n",
7152                          ret, stats.mac_etype_used, stats.etype_used,
7153                          stats.mac_etype_free, stats.etype_free);
7154         if (ret < 0)
7155                 return -ENOSYS;
7156         return 0;
7157 }
7158
7159 /*
7160  * Handle operations for ethertype filter.
7161  */
7162 static int
7163 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7164                                 enum rte_filter_op filter_op,
7165                                 void *arg)
7166 {
7167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7168         int ret = 0;
7169
7170         if (filter_op == RTE_ETH_FILTER_NOP)
7171                 return ret;
7172
7173         if (arg == NULL) {
7174                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7175                             filter_op);
7176                 return -EINVAL;
7177         }
7178
7179         switch (filter_op) {
7180         case RTE_ETH_FILTER_ADD:
7181                 ret = i40e_ethertype_filter_set(pf,
7182                         (struct rte_eth_ethertype_filter *)arg,
7183                         TRUE);
7184                 break;
7185         case RTE_ETH_FILTER_DELETE:
7186                 ret = i40e_ethertype_filter_set(pf,
7187                         (struct rte_eth_ethertype_filter *)arg,
7188                         FALSE);
7189                 break;
7190         default:
7191                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7192                 ret = -ENOSYS;
7193                 break;
7194         }
7195         return ret;
7196 }
7197
7198 static int
7199 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7200                      enum rte_filter_type filter_type,
7201                      enum rte_filter_op filter_op,
7202                      void *arg)
7203 {
7204         int ret = 0;
7205
7206         if (dev == NULL)
7207                 return -EINVAL;
7208
7209         switch (filter_type) {
7210         case RTE_ETH_FILTER_NONE:
7211                 /* For global configuration */
7212                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7213                 break;
7214         case RTE_ETH_FILTER_HASH:
7215                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7216                 break;
7217         case RTE_ETH_FILTER_MACVLAN:
7218                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7219                 break;
7220         case RTE_ETH_FILTER_ETHERTYPE:
7221                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7222                 break;
7223         case RTE_ETH_FILTER_TUNNEL:
7224                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7225                 break;
7226         case RTE_ETH_FILTER_FDIR:
7227                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7228                 break;
7229         default:
7230                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7231                                                         filter_type);
7232                 ret = -EINVAL;
7233                 break;
7234         }
7235
7236         return ret;
7237 }
7238
7239 /*
7240  * As some registers wouldn't be reset unless a global hardware reset,
7241  * hardware initialization is needed to put those registers into an
7242  * expected initial state.
7243  */
7244 static void
7245 i40e_hw_init(struct i40e_hw *hw)
7246 {
7247         /* clear the PF Queue Filter control register */
7248         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7249
7250         /* Disable symmetric hash per port */
7251         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7252 }
7253
7254 enum i40e_filter_pctype
7255 i40e_flowtype_to_pctype(uint16_t flow_type)
7256 {
7257         static const enum i40e_filter_pctype pctype_table[] = {
7258                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7259                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7260                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7261                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7262                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7263                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7264                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7265                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7266                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7267                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7268                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7269                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7270                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7271                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7272                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7273                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7274                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7275                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7276                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7277         };
7278
7279         return pctype_table[flow_type];
7280 }
7281
7282 uint16_t
7283 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7284 {
7285         static const uint16_t flowtype_table[] = {
7286                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7287                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7288                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7289                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7290                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7291                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7292                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7293                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7294                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7295                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7296                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7297                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7298                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7299                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7300                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7301                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7302                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7303                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7304                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7305         };
7306
7307         return flowtype_table[pctype];
7308 }
7309
7310 /*
7311  * On X710, performance number is far from the expectation on recent firmware
7312  * versions; on XL710, performance number is also far from the expectation on
7313  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7314  * mode is enabled and port MAC address is equal to the packet destination MAC
7315  * address. The fix for this issue may not be integrated in the following
7316  * firmware version. So the workaround in software driver is needed. It needs
7317  * to modify the initial values of 3 internal only registers for both X710 and
7318  * XL710. Note that the values for X710 or XL710 could be different, and the
7319  * workaround can be removed when it is fixed in firmware in the future.
7320  */
7321
7322 /* For both X710 and XL710 */
7323 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7324 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7325
7326 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7327 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7328
7329 /* For X710 */
7330 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7331 /* For XL710 */
7332 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7333 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7334
7335 static void
7336 i40e_configure_registers(struct i40e_hw *hw)
7337 {
7338         static struct {
7339                 uint32_t addr;
7340                 uint64_t val;
7341         } reg_table[] = {
7342                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7343                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7344                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7345         };
7346         uint64_t reg;
7347         uint32_t i;
7348         int ret;
7349
7350         for (i = 0; i < RTE_DIM(reg_table); i++) {
7351                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7352                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7353                                 reg_table[i].val =
7354                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7355                         else /* For X710 */
7356                                 reg_table[i].val =
7357                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7358                 }
7359
7360                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7361                                                         &reg, NULL);
7362                 if (ret < 0) {
7363                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7364                                                         reg_table[i].addr);
7365                         break;
7366                 }
7367                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7368                                                 reg_table[i].addr, reg);
7369                 if (reg == reg_table[i].val)
7370                         continue;
7371
7372                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7373                                                 reg_table[i].val, NULL);
7374                 if (ret < 0) {
7375                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7376                                 "address of 0x%"PRIx32, reg_table[i].val,
7377                                                         reg_table[i].addr);
7378                         break;
7379                 }
7380                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7381                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7382         }
7383 }
7384
7385 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7386 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7387 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7388 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7389 static int
7390 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7391 {
7392         uint32_t reg;
7393         int ret;
7394
7395         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7396                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7397                 return -EINVAL;
7398         }
7399
7400         /* Configure for double VLAN RX stripping */
7401         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7402         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7403                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7404                 ret = i40e_aq_debug_write_register(hw,
7405                                                    I40E_VSI_TSR(vsi->vsi_id),
7406                                                    reg, NULL);
7407                 if (ret < 0) {
7408                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7409                                     vsi->vsi_id);
7410                         return I40E_ERR_CONFIG;
7411                 }
7412         }
7413
7414         /* Configure for double VLAN TX insertion */
7415         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7416         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7417                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7418                 ret = i40e_aq_debug_write_register(hw,
7419                                                    I40E_VSI_L2TAGSTXVALID(
7420                                                    vsi->vsi_id), reg, NULL);
7421                 if (ret < 0) {
7422                         PMD_DRV_LOG(ERR, "Failed to update "
7423                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7424                         return I40E_ERR_CONFIG;
7425                 }
7426         }
7427
7428         return 0;
7429 }
7430
7431 /**
7432  * i40e_aq_add_mirror_rule
7433  * @hw: pointer to the hardware structure
7434  * @seid: VEB seid to add mirror rule to
7435  * @dst_id: destination vsi seid
7436  * @entries: Buffer which contains the entities to be mirrored
7437  * @count: number of entities contained in the buffer
7438  * @rule_id:the rule_id of the rule to be added
7439  *
7440  * Add a mirror rule for a given veb.
7441  *
7442  **/
7443 static enum i40e_status_code
7444 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7445                         uint16_t seid, uint16_t dst_id,
7446                         uint16_t rule_type, uint16_t *entries,
7447                         uint16_t count, uint16_t *rule_id)
7448 {
7449         struct i40e_aq_desc desc;
7450         struct i40e_aqc_add_delete_mirror_rule cmd;
7451         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7452                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7453                 &desc.params.raw;
7454         uint16_t buff_len;
7455         enum i40e_status_code status;
7456
7457         i40e_fill_default_direct_cmd_desc(&desc,
7458                                           i40e_aqc_opc_add_mirror_rule);
7459         memset(&cmd, 0, sizeof(cmd));
7460
7461         buff_len = sizeof(uint16_t) * count;
7462         desc.datalen = rte_cpu_to_le_16(buff_len);
7463         if (buff_len > 0)
7464                 desc.flags |= rte_cpu_to_le_16(
7465                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7466         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7467                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7468         cmd.num_entries = rte_cpu_to_le_16(count);
7469         cmd.seid = rte_cpu_to_le_16(seid);
7470         cmd.destination = rte_cpu_to_le_16(dst_id);
7471
7472         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7473         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7474         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7475                          "rule_id = %u"
7476                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7477                          hw->aq.asq_last_status, resp->rule_id,
7478                          resp->mirror_rules_used, resp->mirror_rules_free);
7479         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7480
7481         return status;
7482 }
7483
7484 /**
7485  * i40e_aq_del_mirror_rule
7486  * @hw: pointer to the hardware structure
7487  * @seid: VEB seid to add mirror rule to
7488  * @entries: Buffer which contains the entities to be mirrored
7489  * @count: number of entities contained in the buffer
7490  * @rule_id:the rule_id of the rule to be delete
7491  *
7492  * Delete a mirror rule for a given veb.
7493  *
7494  **/
7495 static enum i40e_status_code
7496 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7497                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7498                 uint16_t count, uint16_t rule_id)
7499 {
7500         struct i40e_aq_desc desc;
7501         struct i40e_aqc_add_delete_mirror_rule cmd;
7502         uint16_t buff_len = 0;
7503         enum i40e_status_code status;
7504         void *buff = NULL;
7505
7506         i40e_fill_default_direct_cmd_desc(&desc,
7507                                           i40e_aqc_opc_delete_mirror_rule);
7508         memset(&cmd, 0, sizeof(cmd));
7509         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7510                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7511                                                           I40E_AQ_FLAG_RD));
7512                 cmd.num_entries = count;
7513                 buff_len = sizeof(uint16_t) * count;
7514                 desc.datalen = rte_cpu_to_le_16(buff_len);
7515                 buff = (void *)entries;
7516         } else
7517                 /* rule id is filled in destination field for deleting mirror rule */
7518                 cmd.destination = rte_cpu_to_le_16(rule_id);
7519
7520         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7521                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7522         cmd.seid = rte_cpu_to_le_16(seid);
7523
7524         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7525         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7526
7527         return status;
7528 }
7529
7530 /**
7531  * i40e_mirror_rule_set
7532  * @dev: pointer to the hardware structure
7533  * @mirror_conf: mirror rule info
7534  * @sw_id: mirror rule's sw_id
7535  * @on: enable/disable
7536  *
7537  * set a mirror rule.
7538  *
7539  **/
7540 static int
7541 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7542                         struct rte_eth_mirror_conf *mirror_conf,
7543                         uint8_t sw_id, uint8_t on)
7544 {
7545         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7546         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7547         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7548         struct i40e_mirror_rule *parent = NULL;
7549         uint16_t seid, dst_seid, rule_id;
7550         uint16_t i, j = 0;
7551         int ret;
7552
7553         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7554
7555         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7556                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7557                         " without veb or vfs.");
7558                 return -ENOSYS;
7559         }
7560         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7561                 PMD_DRV_LOG(ERR, "mirror table is full.");
7562                 return -ENOSPC;
7563         }
7564         if (mirror_conf->dst_pool > pf->vf_num) {
7565                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7566                                  mirror_conf->dst_pool);
7567                 return -EINVAL;
7568         }
7569
7570         seid = pf->main_vsi->veb->seid;
7571
7572         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7573                 if (sw_id <= it->index) {
7574                         mirr_rule = it;
7575                         break;
7576                 }
7577                 parent = it;
7578         }
7579         if (mirr_rule && sw_id == mirr_rule->index) {
7580                 if (on) {
7581                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7582                         return -EEXIST;
7583                 } else {
7584                         ret = i40e_aq_del_mirror_rule(hw, seid,
7585                                         mirr_rule->rule_type,
7586                                         mirr_rule->entries,
7587                                         mirr_rule->num_entries, mirr_rule->id);
7588                         if (ret < 0) {
7589                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7590                                                    " ret = %d, aq_err = %d.",
7591                                                    ret, hw->aq.asq_last_status);
7592                                 return -ENOSYS;
7593                         }
7594                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7595                         rte_free(mirr_rule);
7596                         pf->nb_mirror_rule--;
7597                         return 0;
7598                 }
7599         } else if (!on) {
7600                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7601                 return -ENOENT;
7602         }
7603
7604         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7605                                 sizeof(struct i40e_mirror_rule) , 0);
7606         if (!mirr_rule) {
7607                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7608                 return I40E_ERR_NO_MEMORY;
7609         }
7610         switch (mirror_conf->rule_type) {
7611         case ETH_MIRROR_VLAN:
7612                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7613                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7614                                 mirr_rule->entries[j] =
7615                                         mirror_conf->vlan.vlan_id[i];
7616                                 j++;
7617                         }
7618                 }
7619                 if (j == 0) {
7620                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7621                         rte_free(mirr_rule);
7622                         return -EINVAL;
7623                 }
7624                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7625                 break;
7626         case ETH_MIRROR_VIRTUAL_POOL_UP:
7627         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7628                 /* check if the specified pool bit is out of range */
7629                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7630                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7631                         rte_free(mirr_rule);
7632                         return -EINVAL;
7633                 }
7634                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7635                         if (mirror_conf->pool_mask & (1ULL << i)) {
7636                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7637                                 j++;
7638                         }
7639                 }
7640                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7641                         /* add pf vsi to entries */
7642                         mirr_rule->entries[j] = pf->main_vsi_seid;
7643                         j++;
7644                 }
7645                 if (j == 0) {
7646                         PMD_DRV_LOG(ERR, "pool is not specified.");
7647                         rte_free(mirr_rule);
7648                         return -EINVAL;
7649                 }
7650                 /* egress and ingress in aq commands means from switch but not port */
7651                 mirr_rule->rule_type =
7652                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7653                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7654                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7655                 break;
7656         case ETH_MIRROR_UPLINK_PORT:
7657                 /* egress and ingress in aq commands means from switch but not port*/
7658                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7659                 break;
7660         case ETH_MIRROR_DOWNLINK_PORT:
7661                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7662                 break;
7663         default:
7664                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7665                         mirror_conf->rule_type);
7666                 rte_free(mirr_rule);
7667                 return -EINVAL;
7668         }
7669
7670         /* If the dst_pool is equal to vf_num, consider it as PF */
7671         if (mirror_conf->dst_pool == pf->vf_num)
7672                 dst_seid = pf->main_vsi_seid;
7673         else
7674                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7675
7676         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7677                                       mirr_rule->rule_type, mirr_rule->entries,
7678                                       j, &rule_id);
7679         if (ret < 0) {
7680                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7681                                    " ret = %d, aq_err = %d.",
7682                                    ret, hw->aq.asq_last_status);
7683                 rte_free(mirr_rule);
7684                 return -ENOSYS;
7685         }
7686
7687         mirr_rule->index = sw_id;
7688         mirr_rule->num_entries = j;
7689         mirr_rule->id = rule_id;
7690         mirr_rule->dst_vsi_seid = dst_seid;
7691
7692         if (parent)
7693                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7694         else
7695                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7696
7697         pf->nb_mirror_rule++;
7698         return 0;
7699 }
7700
7701 /**
7702  * i40e_mirror_rule_reset
7703  * @dev: pointer to the device
7704  * @sw_id: mirror rule's sw_id
7705  *
7706  * reset a mirror rule.
7707  *
7708  **/
7709 static int
7710 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7711 {
7712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7714         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7715         uint16_t seid;
7716         int ret;
7717
7718         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7719
7720         seid = pf->main_vsi->veb->seid;
7721
7722         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7723                 if (sw_id == it->index) {
7724                         mirr_rule = it;
7725                         break;
7726                 }
7727         }
7728         if (mirr_rule) {
7729                 ret = i40e_aq_del_mirror_rule(hw, seid,
7730                                 mirr_rule->rule_type,
7731                                 mirr_rule->entries,
7732                                 mirr_rule->num_entries, mirr_rule->id);
7733                 if (ret < 0) {
7734                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7735                                            " status = %d, aq_err = %d.",
7736                                            ret, hw->aq.asq_last_status);
7737                         return -ENOSYS;
7738                 }
7739                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7740                 rte_free(mirr_rule);
7741                 pf->nb_mirror_rule--;
7742         } else {
7743                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7744                 return -ENOENT;
7745         }
7746         return 0;
7747 }
7748
7749 static uint64_t
7750 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
7751 {
7752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7753         uint64_t systim_cycles;
7754
7755         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
7756         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
7757                         << 32;
7758
7759         return systim_cycles;
7760 }
7761
7762 static uint64_t
7763 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
7764 {
7765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7766         uint64_t rx_tstamp;
7767
7768         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7769         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
7770                         << 32;
7771
7772         return rx_tstamp;
7773 }
7774
7775 static uint64_t
7776 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7777 {
7778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7779         uint64_t tx_tstamp;
7780
7781         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7782         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
7783                         << 32;
7784
7785         return tx_tstamp;
7786 }
7787
7788 static void
7789 i40e_start_timecounters(struct rte_eth_dev *dev)
7790 {
7791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7792         struct i40e_adapter *adapter =
7793                         (struct i40e_adapter *)dev->data->dev_private;
7794         struct rte_eth_link link;
7795         uint32_t tsync_inc_l;
7796         uint32_t tsync_inc_h;
7797
7798         /* Get current link speed. */
7799         memset(&link, 0, sizeof(link));
7800         i40e_dev_link_update(dev, 1);
7801         rte_i40e_dev_atomic_read_link_status(dev, &link);
7802
7803         switch (link.link_speed) {
7804         case ETH_LINK_SPEED_40G:
7805                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7806                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7807                 break;
7808         case ETH_LINK_SPEED_10G:
7809                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7810                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7811                 break;
7812         case ETH_LINK_SPEED_1000:
7813                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7814                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7815                 break;
7816         default:
7817                 tsync_inc_l = 0x0;
7818                 tsync_inc_h = 0x0;
7819         }
7820
7821         /* Set the timesync increment value. */
7822         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7823         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7824
7825         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7826         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7827         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7828
7829         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7830         adapter->systime_tc.cc_shift = 0;
7831         adapter->systime_tc.nsec_mask = 0;
7832
7833         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7834         adapter->rx_tstamp_tc.cc_shift = 0;
7835         adapter->rx_tstamp_tc.nsec_mask = 0;
7836
7837         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
7838         adapter->tx_tstamp_tc.cc_shift = 0;
7839         adapter->tx_tstamp_tc.nsec_mask = 0;
7840 }
7841
7842 static int
7843 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7844 {
7845         struct i40e_adapter *adapter =
7846                         (struct i40e_adapter *)dev->data->dev_private;
7847
7848         adapter->systime_tc.nsec += delta;
7849         adapter->rx_tstamp_tc.nsec += delta;
7850         adapter->tx_tstamp_tc.nsec += delta;
7851
7852         return 0;
7853 }
7854
7855 static int
7856 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7857 {
7858         uint64_t ns;
7859         struct i40e_adapter *adapter =
7860                         (struct i40e_adapter *)dev->data->dev_private;
7861
7862         ns = rte_timespec_to_ns(ts);
7863
7864         /* Set the timecounters to a new value. */
7865         adapter->systime_tc.nsec = ns;
7866         adapter->rx_tstamp_tc.nsec = ns;
7867         adapter->tx_tstamp_tc.nsec = ns;
7868
7869         return 0;
7870 }
7871
7872 static int
7873 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7874 {
7875         uint64_t ns, systime_cycles;
7876         struct i40e_adapter *adapter =
7877                         (struct i40e_adapter *)dev->data->dev_private;
7878
7879         systime_cycles = i40e_read_systime_cyclecounter(dev);
7880         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7881         *ts = rte_ns_to_timespec(ns);
7882
7883         return 0;
7884 }
7885
7886 static int
7887 i40e_timesync_enable(struct rte_eth_dev *dev)
7888 {
7889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7890         uint32_t tsync_ctl_l;
7891         uint32_t tsync_ctl_h;
7892
7893         /* Stop the timesync system time. */
7894         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7895         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7896         /* Reset the timesync system time value. */
7897         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
7898         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
7899
7900         i40e_start_timecounters(dev);
7901
7902         /* Clear timesync registers. */
7903         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7904         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7905         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
7906         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
7907         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
7908         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
7909
7910         /* Enable timestamping of PTP packets. */
7911         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7912         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7913
7914         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7915         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7916         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7917
7918         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7919         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7920
7921         return 0;
7922 }
7923
7924 static int
7925 i40e_timesync_disable(struct rte_eth_dev *dev)
7926 {
7927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7928         uint32_t tsync_ctl_l;
7929         uint32_t tsync_ctl_h;
7930
7931         /* Disable timestamping of transmitted PTP packets. */
7932         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7933         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7934
7935         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7936         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7937
7938         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7939         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7940
7941         /* Reset the timesync increment value. */
7942         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7943         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7944
7945         return 0;
7946 }
7947
7948 static int
7949 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7950                                 struct timespec *timestamp, uint32_t flags)
7951 {
7952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7953         struct i40e_adapter *adapter =
7954                 (struct i40e_adapter *)dev->data->dev_private;
7955
7956         uint32_t sync_status;
7957         uint32_t index = flags & 0x03;
7958         uint64_t rx_tstamp_cycles;
7959         uint64_t ns;
7960
7961         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7962         if ((sync_status & (1 << index)) == 0)
7963                 return -EINVAL;
7964
7965         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
7966         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7967         *timestamp = rte_ns_to_timespec(ns);
7968
7969         return 0;
7970 }
7971
7972 static int
7973 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7974                                 struct timespec *timestamp)
7975 {
7976         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7977         struct i40e_adapter *adapter =
7978                 (struct i40e_adapter *)dev->data->dev_private;
7979
7980         uint32_t sync_status;
7981         uint64_t tx_tstamp_cycles;
7982         uint64_t ns;
7983
7984         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7985         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7986                 return -EINVAL;
7987
7988         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
7989         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7990         *timestamp = rte_ns_to_timespec(ns);
7991
7992         return 0;
7993 }
7994
7995 /*
7996  * i40e_parse_dcb_configure - parse dcb configure from user
7997  * @dev: the device being configured
7998  * @dcb_cfg: pointer of the result of parse
7999  * @*tc_map: bit map of enabled traffic classes
8000  *
8001  * Returns 0 on success, negative value on failure
8002  */
8003 static int
8004 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8005                          struct i40e_dcbx_config *dcb_cfg,
8006                          uint8_t *tc_map)
8007 {
8008         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8009         uint8_t i, tc_bw, bw_lf;
8010
8011         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8012
8013         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8014         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8015                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8016                 return -EINVAL;
8017         }
8018
8019         /* assume each tc has the same bw */
8020         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8021         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8022                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8023         /* to ensure the sum of tcbw is equal to 100 */
8024         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8025         for (i = 0; i < bw_lf; i++)
8026                 dcb_cfg->etscfg.tcbwtable[i]++;
8027
8028         /* assume each tc has the same Transmission Selection Algorithm */
8029         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8030                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8031
8032         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8033                 dcb_cfg->etscfg.prioritytable[i] =
8034                                 dcb_rx_conf->dcb_tc[i];
8035
8036         /* FW needs one App to configure HW */
8037         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8038         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8039         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8040         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8041
8042         if (dcb_rx_conf->nb_tcs == 0)
8043                 *tc_map = 1; /* tc0 only */
8044         else
8045                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8046
8047         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8048                 dcb_cfg->pfc.willing = 0;
8049                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8050                 dcb_cfg->pfc.pfcenable = *tc_map;
8051         }
8052         return 0;
8053 }
8054
8055 /*
8056  * i40e_vsi_get_bw_info - Query VSI BW Information
8057  * @vsi: the VSI being queried
8058  *
8059  * Returns 0 on success, negative value on failure
8060  */
8061 static enum i40e_status_code
8062 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
8063 {
8064         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
8065         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
8066         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8067         enum i40e_status_code ret;
8068         int i;
8069         uint32_t tc_bw_max;
8070
8071         /* Get the VSI level BW configuration */
8072         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
8073         if (ret) {
8074                 PMD_INIT_LOG(ERR,
8075                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
8076                          i40e_stat_str(hw, ret),
8077                          i40e_aq_str(hw, hw->aq.asq_last_status));
8078                 return ret;
8079         }
8080
8081         /* Get the VSI level BW configuration per TC */
8082         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
8083                                                   NULL);
8084         if (ret) {
8085                 PMD_INIT_LOG(ERR,
8086                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
8087                          i40e_stat_str(hw, ret),
8088                          i40e_aq_str(hw, hw->aq.asq_last_status));
8089                 return ret;
8090         }
8091
8092         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
8093                 PMD_INIT_LOG(WARNING,
8094                          "Enabled TCs mismatch from querying VSI BW info"
8095                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
8096                          bw_ets_config.tc_valid_bits);
8097                 /* Still continuing */
8098         }
8099
8100         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
8101         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
8102         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
8103                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
8104         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8105                 vsi->bw_info.bw_ets_share_credits[i] =
8106                                 bw_ets_config.share_credits[i];
8107                 vsi->bw_info.bw_ets_limit_credits[i] =
8108                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
8109                 /* 3 bits out of 4 for each TC */
8110                 vsi->bw_info.bw_ets_max_quanta[i] =
8111                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
8112                 PMD_INIT_LOG(DEBUG,
8113                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
8114                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
8115         }
8116
8117         return ret;
8118 }
8119
8120 static enum i40e_status_code
8121 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8122                               struct i40e_aqc_vsi_properties_data *info,
8123                               uint8_t enabled_tcmap)
8124 {
8125         enum i40e_status_code ret;
8126         int i, total_tc = 0;
8127         uint16_t qpnum_per_tc, bsf, qp_idx;
8128         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8129
8130         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8131         if (ret != I40E_SUCCESS)
8132                 return ret;
8133
8134         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8135                 if (enabled_tcmap & (1 << i))
8136                         total_tc++;
8137         }
8138         if (total_tc == 0)
8139                 total_tc = 1;
8140         vsi->enabled_tc = enabled_tcmap;
8141
8142         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8143         /* Number of queues per enabled TC */
8144         if (qpnum_per_tc == 0) {
8145                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8146                 return I40E_ERR_INVALID_QP_ID;
8147         }
8148         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8149                                 I40E_MAX_Q_PER_TC);
8150         bsf = rte_bsf32(qpnum_per_tc);
8151
8152         /**
8153          * Configure TC and queue mapping parameters, for enabled TC,
8154          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8155          * default queue will serve it.
8156          */
8157         qp_idx = 0;
8158         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8159                 if (vsi->enabled_tc & (1 << i)) {
8160                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8161                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8162                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8163                         qp_idx += qpnum_per_tc;
8164                 } else
8165                         info->tc_mapping[i] = 0;
8166         }
8167
8168         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8169         if (vsi->type == I40E_VSI_SRIOV) {
8170                 info->mapping_flags |=
8171                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8172                 for (i = 0; i < vsi->nb_qps; i++)
8173                         info->queue_mapping[i] =
8174                                 rte_cpu_to_le_16(vsi->base_queue + i);
8175         } else {
8176                 info->mapping_flags |=
8177                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8178                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8179         }
8180         info->valid_sections |=
8181                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8182
8183         return I40E_SUCCESS;
8184 }
8185
8186 /*
8187  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8188  * @vsi: VSI to be configured
8189  * @tc_map: enabled TC bitmap
8190  *
8191  * Returns 0 on success, negative value on failure
8192  */
8193 static enum i40e_status_code
8194 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8195 {
8196         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8197         struct i40e_vsi_context ctxt;
8198         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8199         enum i40e_status_code ret = I40E_SUCCESS;
8200         int i;
8201
8202         /* Check if enabled_tc is same as existing or new TCs */
8203         if (vsi->enabled_tc == tc_map)
8204                 return ret;
8205
8206         /* configure tc bandwidth */
8207         memset(&bw_data, 0, sizeof(bw_data));
8208         bw_data.tc_valid_bits = tc_map;
8209         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8210         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8211                 if (tc_map & BIT_ULL(i))
8212                         bw_data.tc_bw_credits[i] = 1;
8213         }
8214         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8215         if (ret) {
8216                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8217                         " per TC failed = %d",
8218                         hw->aq.asq_last_status);
8219                 goto out;
8220         }
8221         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8222                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8223
8224         /* Update Queue Pairs Mapping for currently enabled UPs */
8225         ctxt.seid = vsi->seid;
8226         ctxt.pf_num = hw->pf_id;
8227         ctxt.vf_num = 0;
8228         ctxt.uplink_seid = vsi->uplink_seid;
8229         ctxt.info = vsi->info;
8230         i40e_get_cap(hw);
8231         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8232         if (ret)
8233                 goto out;
8234
8235         /* Update the VSI after updating the VSI queue-mapping information */
8236         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8237         if (ret) {
8238                 PMD_INIT_LOG(ERR, "Failed to configure "
8239                             "TC queue mapping = %d",
8240                             hw->aq.asq_last_status);
8241                 goto out;
8242         }
8243         /* update the local VSI info with updated queue map */
8244         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8245                                         sizeof(vsi->info.tc_mapping));
8246         (void)rte_memcpy(&vsi->info.queue_mapping,
8247                         &ctxt.info.queue_mapping,
8248                 sizeof(vsi->info.queue_mapping));
8249         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8250         vsi->info.valid_sections = 0;
8251
8252         /* Update current VSI BW information */
8253         ret = i40e_vsi_get_bw_info(vsi);
8254         if (ret) {
8255                 PMD_INIT_LOG(ERR,
8256                          "Failed updating vsi bw info, err %s aq_err %s",
8257                          i40e_stat_str(hw, ret),
8258                          i40e_aq_str(hw, hw->aq.asq_last_status));
8259                 goto out;
8260         }
8261
8262         vsi->enabled_tc = tc_map;
8263
8264 out:
8265         return ret;
8266 }
8267
8268 /*
8269  * i40e_dcb_hw_configure - program the dcb setting to hw
8270  * @pf: pf the configuration is taken on
8271  * @new_cfg: new configuration
8272  * @tc_map: enabled TC bitmap
8273  *
8274  * Returns 0 on success, negative value on failure
8275  */
8276 static enum i40e_status_code
8277 i40e_dcb_hw_configure(struct i40e_pf *pf,
8278                       struct i40e_dcbx_config *new_cfg,
8279                       uint8_t tc_map)
8280 {
8281         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8282         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8283         struct i40e_vsi *main_vsi = pf->main_vsi;
8284         struct i40e_vsi_list *vsi_list;
8285         enum i40e_status_code ret;
8286         int i;
8287         uint32_t val;
8288
8289         /* Use the FW API if FW > v4.4*/
8290         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8291                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8292                                   " to configure DCB");
8293                 return I40E_ERR_FIRMWARE_API_VERSION;
8294         }
8295
8296         /* Check if need reconfiguration */
8297         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8298                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8299                 return I40E_SUCCESS;
8300         }
8301
8302         /* Copy the new config to the current config */
8303         *old_cfg = *new_cfg;
8304         old_cfg->etsrec = old_cfg->etscfg;
8305         ret = i40e_set_dcb_config(hw);
8306         if (ret) {
8307                 PMD_INIT_LOG(ERR,
8308                          "Set DCB Config failed, err %s aq_err %s\n",
8309                          i40e_stat_str(hw, ret),
8310                          i40e_aq_str(hw, hw->aq.asq_last_status));
8311                 return ret;
8312         }
8313         /* set receive Arbiter to RR mode and ETS scheme by default */
8314         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8315                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8316                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8317                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8318                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8319                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8320                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8321                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8322                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8323                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8324                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8325                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8326                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8327         }
8328         /* get local mib to check whether it is configured correctly */
8329         /* IEEE mode */
8330         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8331         /* Get Local DCB Config */
8332         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8333                                      &hw->local_dcbx_config);
8334
8335         /* Update each VSI */
8336         i40e_vsi_config_tc(main_vsi, tc_map);
8337         if (main_vsi->veb) {
8338                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8339                         /* Beside main VSI, only enable default
8340                          * TC for other VSIs
8341                          */
8342                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8343                                                 I40E_DEFAULT_TCMAP);
8344                         if (ret)
8345                                 PMD_INIT_LOG(WARNING,
8346                                          "Failed configuring TC for VSI seid=%d\n",
8347                                          vsi_list->vsi->seid);
8348                         /* continue */
8349                 }
8350         }
8351         return I40E_SUCCESS;
8352 }
8353
8354 /*
8355  * i40e_dcb_init_configure - initial dcb config
8356  * @dev: device being configured
8357  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8358  *
8359  * Returns 0 on success, negative value on failure
8360  */
8361 static int
8362 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8363 {
8364         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8365         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8366         int ret = 0;
8367
8368         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8369                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8370                 return -ENOTSUP;
8371         }
8372
8373         /* DCB initialization:
8374          * Update DCB configuration from the Firmware and configure
8375          * LLDP MIB change event.
8376          */
8377         if (sw_dcb == TRUE) {
8378                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8379                 if (ret != I40E_SUCCESS)
8380                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8381
8382                 ret = i40e_init_dcb(hw);
8383                 /* if sw_dcb, lldp agent is stopped, the return from
8384                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8385                  * adminq status.
8386                  */
8387                 if (ret != I40E_SUCCESS &&
8388                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8389                         memset(&hw->local_dcbx_config, 0,
8390                                 sizeof(struct i40e_dcbx_config));
8391                         /* set dcb default configuration */
8392                         hw->local_dcbx_config.etscfg.willing = 0;
8393                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8394                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8395                         hw->local_dcbx_config.etscfg.tsatable[0] =
8396                                                 I40E_IEEE_TSA_ETS;
8397                         hw->local_dcbx_config.etsrec =
8398                                 hw->local_dcbx_config.etscfg;
8399                         hw->local_dcbx_config.pfc.willing = 0;
8400                         hw->local_dcbx_config.pfc.pfccap =
8401                                                 I40E_MAX_TRAFFIC_CLASS;
8402                         /* FW needs one App to configure HW */
8403                         hw->local_dcbx_config.numapps = 1;
8404                         hw->local_dcbx_config.app[0].selector =
8405                                                 I40E_APP_SEL_ETHTYPE;
8406                         hw->local_dcbx_config.app[0].priority = 3;
8407                         hw->local_dcbx_config.app[0].protocolid =
8408                                                 I40E_APP_PROTOID_FCOE;
8409                         ret = i40e_set_dcb_config(hw);
8410                         if (ret) {
8411                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8412                                         " err = %d, aq_err = %d.", ret,
8413                                           hw->aq.asq_last_status);
8414                                 return -ENOSYS;
8415                         }
8416                 } else {
8417                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8418                                           " aq_err = %d.", ret,
8419                                           hw->aq.asq_last_status);
8420                         return -ENOTSUP;
8421                 }
8422         } else {
8423                 ret = i40e_aq_start_lldp(hw, NULL);
8424                 if (ret != I40E_SUCCESS)
8425                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8426
8427                 ret = i40e_init_dcb(hw);
8428                 if (!ret) {
8429                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8430                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8431                                                   " DCBX offload.");
8432                                 return -ENOTSUP;
8433                         }
8434                 } else {
8435                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8436                                           " aq_err = %d.", ret,
8437                                           hw->aq.asq_last_status);
8438                         return -ENOTSUP;
8439                 }
8440         }
8441         return 0;
8442 }
8443
8444 /*
8445  * i40e_dcb_setup - setup dcb related config
8446  * @dev: device being configured
8447  *
8448  * Returns 0 on success, negative value on failure
8449  */
8450 static int
8451 i40e_dcb_setup(struct rte_eth_dev *dev)
8452 {
8453         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8454         struct i40e_dcbx_config dcb_cfg;
8455         uint8_t tc_map = 0;
8456         int ret = 0;
8457
8458         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8459                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8460                 return -ENOTSUP;
8461         }
8462
8463         if (pf->vf_num != 0 ||
8464             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8465                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8466
8467         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8468         if (ret) {
8469                 PMD_INIT_LOG(ERR, "invalid dcb config");
8470                 return -EINVAL;
8471         }
8472         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8473         if (ret) {
8474                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8475                 return -ENOSYS;
8476         }
8477
8478         return 0;
8479 }
8480
8481 static int
8482 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8483                       struct rte_eth_dcb_info *dcb_info)
8484 {
8485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8487         struct i40e_vsi *vsi = pf->main_vsi;
8488         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8489         uint16_t bsf, tc_mapping;
8490         int i;
8491
8492         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8493                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8494         else
8495                 dcb_info->nb_tcs = 1;
8496         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8497                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8498         for (i = 0; i < dcb_info->nb_tcs; i++)
8499                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8500
8501         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8502                 if (vsi->enabled_tc & (1 << i)) {
8503                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8504                         /* only main vsi support multi TCs */
8505                         dcb_info->tc_queue.tc_rxq[0][i].base =
8506                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8507                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8508                         dcb_info->tc_queue.tc_txq[0][i].base =
8509                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8510                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8511                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8512                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8513                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8514                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8515                 }
8516         }
8517
8518         return 0;
8519 }
8520
8521 static int
8522 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8523 {
8524         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8525         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8526         uint16_t interval =
8527                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8528         uint16_t msix_intr;
8529
8530         msix_intr = intr_handle->intr_vec[queue_id];
8531         if (msix_intr == I40E_MISC_VEC_ID)
8532                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8533                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8534                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8535                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8536                                (interval <<
8537                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8538         else
8539                 I40E_WRITE_REG(hw,
8540                                I40E_PFINT_DYN_CTLN(msix_intr -
8541                                                    I40E_RX_VEC_START),
8542                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8543                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8544                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8545                                (interval <<
8546                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8547
8548         I40E_WRITE_FLUSH(hw);
8549         rte_intr_enable(&dev->pci_dev->intr_handle);
8550
8551         return 0;
8552 }
8553
8554 static int
8555 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8556 {
8557         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8558         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8559         uint16_t msix_intr;
8560
8561         msix_intr = intr_handle->intr_vec[queue_id];
8562         if (msix_intr == I40E_MISC_VEC_ID)
8563                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8564         else
8565                 I40E_WRITE_REG(hw,
8566                                I40E_PFINT_DYN_CTLN(msix_intr -
8567                                                    I40E_RX_VEC_START),
8568                                0);
8569         I40E_WRITE_FLUSH(hw);
8570
8571         return 0;
8572 }