drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  49
  50 #define I40E_CLEAR_PXE_WAIT_MS     200
  51 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  52 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  53
  54 /* Maximun number of capability elements */
  55 #define I40E_MAX_CAP_ELE_NUM       128
  56
  57 /* Wait count and interval */
  58 #define I40E_CHK_Q_ENA_COUNT       1000
  59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  60
  61 /* Maximun number of VSI */
  62 #define I40E_MAX_NUM_VSIS          (384UL)
  63
  64 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  65
  66 /* Flow control default timer */
  67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  68
  69 /* Flow control enable fwd bit */
  70 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  71
  72 /* Receive Packet Buffer size */
  73 #define I40E_RXPBSIZE (968 * 1024)
  74
  75 /* Kilobytes shift */
  76 #define I40E_KILOSHIFT 10
  77
  78 /* Flow control default high water */
  79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Flow control default low water */
  82 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  83
  84 /* Receive Average Packet Size in Byte*/
  85 #define I40E_PACKET_AVERAGE_SIZE 128
  86
  87 /* Mask of PF interrupt causes */
  88 #define I40E_PFINT_ICR0_ENA_MASK ( \
  89                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  93                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  94                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  98
  99 #define I40E_FLOW_TYPES ( \
 100         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 105         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 110         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 111
 112 /* Additional timesync values. */
 113 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 114 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 115 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 116 #define I40E_PRTTSYN_TSYNENA     0x80000000
 117 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 118 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 119
 120 /**
 121  * Below are values for writing un-exposed registers suggested
 122  * by silicon experts
 123  */
 124 /* Destination MAC address */
 125 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 126 /* Source MAC address */
 127 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 129 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 131 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 132 /* Single VLAN tag in the inner L2 header */
 133 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 134 /* Source IPv4 address */
 135 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 136 /* Destination IPv4 address */
 137 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 138 /* Source IPv4 address for X722 */
 139 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 140 /* Destination IPv4 address for X722 */
 141 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 142 /* IPv4 Protocol for X722 */
 143 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 144 /* IPv4 Time to Live for X722 */
 145 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 146 /* IPv4 Type of Service (TOS) */
 147 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 148 /* IPv4 Protocol */
 149 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 150 /* IPv4 Time to Live */
 151 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 152 /* Source IPv6 address */
 153 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 154 /* Destination IPv6 address */
 155 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 156 /* IPv6 Traffic Class (TC) */
 157 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 158 /* IPv6 Next Header */
 159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 160 /* IPv6 Hop Limit */
 161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 162 /* Source L4 port */
 163 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 164 /* Destination L4 port */
 165 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 166 /* SCTP verification tag */
 167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 170 /* Source port of tunneling UDP */
 171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 172 /* Destination port of tunneling UDP */
 173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 174 /* UDP Tunneling ID, NVGRE/GRE key */
 175 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 176 /* Last ether type */
 177 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 178 /* Tunneling outer destination IPv4 address */
 179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 180 /* Tunneling outer destination IPv6 address */
 181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 182 /* 1st word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 184 /* 2nd word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 186 /* 3rd word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 188 /* 4th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 190 /* 5th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 192 /* 6th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 194 /* 7th word of flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 196 /* 8th word of flex payload */
 197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 198 /* all 8 words flex payload */
 199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 200 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 201
 202 #define I40E_TRANSLATE_INSET 0
 203 #define I40E_TRANSLATE_REG   1
 204
 205 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 206 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 207 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 208 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 210 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 211
 212 /* PCI offset for querying capability */
 213 #define PCI_DEV_CAP_REG            0xA4
 214 /* PCI offset for enabling/disabling Extended Tag */
 215 #define PCI_DEV_CTRL_REG           0xA8
 216 /* Bit mask of Extended Tag capability */
 217 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 218 /* Bit shift of Extended Tag enable/disable */
 219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 220 /* Bit mask of Extended Tag enable/disable */
 221 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 222
 223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 225 static int i40e_dev_configure(struct rte_eth_dev *dev);
 226 static int i40e_dev_start(struct rte_eth_dev *dev);
 227 static int i40e_dev_stop(struct rte_eth_dev *dev);
 228 static int i40e_dev_close(struct rte_eth_dev *dev);
 229 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_stats *stats);
 238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 239                                struct rte_eth_xstat *xstats, unsigned n);
 240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 241                                      struct rte_eth_xstat_name *xstats_names,
 242                                      unsigned limit);
 243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 247                              struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct rte_ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 309                                              struct i40e_macvlan_filter *mv_f,
 310                                              int num,
 311                                              uint16_t vlan);
 312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 314                                     struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 316                                       struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static int i40e_get_module_info(struct rte_eth_dev *dev,
 373                                 struct rte_eth_dev_module_info *modinfo);
 374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 375                                   struct rte_dev_eeprom_info *info);
 376
 377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 378                                       struct rte_ether_addr *mac_addr);
 379
 380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 381
 382 static int i40e_ethertype_filter_convert(
 383         const struct rte_eth_ethertype_filter *input,
 384         struct i40e_ethertype_filter *filter);
 385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 386                                    struct i40e_ethertype_filter *filter);
 387
 388 static int i40e_tunnel_filter_convert(
 389         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 390         struct i40e_tunnel_filter *tunnel_filter);
 391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 392                                 struct i40e_tunnel_filter *tunnel_filter);
 393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 394
 395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 397 static void i40e_filter_restore(struct i40e_pf *pf);
 398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 399 static int i40e_pf_config_rss(struct i40e_pf *pf);
 400
 401 static const char *const valid_keys[] = {
 402         ETH_I40E_FLOATING_VEB_ARG,
 403         ETH_I40E_FLOATING_VEB_LIST_ARG,
 404         ETH_I40E_SUPPORT_MULTI_DRIVER,
 405         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 406         ETH_I40E_USE_LATEST_VEC,
 407         ETH_I40E_VF_MSG_CFG,
 408         NULL};
 409
 410 static const struct rte_pci_id pci_id_i40e_map[] = {
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 437         { .vendor_id = 0, /* sentinel */ },
 438 };
 439
 440 static const struct eth_dev_ops i40e_eth_dev_ops = {
 441         .dev_configure                = i40e_dev_configure,
 442         .dev_start                    = i40e_dev_start,
 443         .dev_stop                     = i40e_dev_stop,
 444         .dev_close                    = i40e_dev_close,
 445         .dev_reset                    = i40e_dev_reset,
 446         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 447         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 448         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 449         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 450         .dev_set_link_up              = i40e_dev_set_link_up,
 451         .dev_set_link_down            = i40e_dev_set_link_down,
 452         .link_update                  = i40e_dev_link_update,
 453         .stats_get                    = i40e_dev_stats_get,
 454         .xstats_get                   = i40e_dev_xstats_get,
 455         .xstats_get_names             = i40e_dev_xstats_get_names,
 456         .stats_reset                  = i40e_dev_stats_reset,
 457         .xstats_reset                 = i40e_dev_stats_reset,
 458         .fw_version_get               = i40e_fw_version_get,
 459         .dev_infos_get                = i40e_dev_info_get,
 460         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 461         .vlan_filter_set              = i40e_vlan_filter_set,
 462         .vlan_tpid_set                = i40e_vlan_tpid_set,
 463         .vlan_offload_set             = i40e_vlan_offload_set,
 464         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 465         .vlan_pvid_set                = i40e_vlan_pvid_set,
 466         .rx_queue_start               = i40e_dev_rx_queue_start,
 467         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 468         .tx_queue_start               = i40e_dev_tx_queue_start,
 469         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 470         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 471         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 472         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 473         .rx_queue_release             = i40e_dev_rx_queue_release,
 474         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 475         .tx_queue_release             = i40e_dev_tx_queue_release,
 476         .dev_led_on                   = i40e_dev_led_on,
 477         .dev_led_off                  = i40e_dev_led_off,
 478         .flow_ctrl_get                = i40e_flow_ctrl_get,
 479         .flow_ctrl_set                = i40e_flow_ctrl_set,
 480         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 481         .mac_addr_add                 = i40e_macaddr_add,
 482         .mac_addr_remove              = i40e_macaddr_remove,
 483         .reta_update                  = i40e_dev_rss_reta_update,
 484         .reta_query                   = i40e_dev_rss_reta_query,
 485         .rss_hash_update              = i40e_dev_rss_hash_update,
 486         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 487         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 488         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 489         .filter_ctrl                  = i40e_dev_filter_ctrl,
 490         .rxq_info_get                 = i40e_rxq_info_get,
 491         .txq_info_get                 = i40e_txq_info_get,
 492         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 493         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 494         .mirror_rule_set              = i40e_mirror_rule_set,
 495         .mirror_rule_reset            = i40e_mirror_rule_reset,
 496         .timesync_enable              = i40e_timesync_enable,
 497         .timesync_disable             = i40e_timesync_disable,
 498         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 499         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 500         .get_dcb_info                 = i40e_dev_get_dcb_info,
 501         .timesync_adjust_time         = i40e_timesync_adjust_time,
 502         .timesync_read_time           = i40e_timesync_read_time,
 503         .timesync_write_time          = i40e_timesync_write_time,
 504         .get_reg                      = i40e_get_regs,
 505         .get_eeprom_length            = i40e_get_eeprom_length,
 506         .get_eeprom                   = i40e_get_eeprom,
 507         .get_module_info              = i40e_get_module_info,
 508         .get_module_eeprom            = i40e_get_module_eeprom,
 509         .mac_addr_set                 = i40e_set_default_mac_addr,
 510         .mtu_set                      = i40e_dev_mtu_set,
 511         .tm_ops_get                   = i40e_tm_ops_get,
 512         .tx_done_cleanup              = i40e_tx_done_cleanup,
 513 };
 514
 515 /* store statistics names and its offset in stats structure */
 516 struct rte_i40e_xstats_name_off {
 517         char name[RTE_ETH_XSTATS_NAME_SIZE];
 518         unsigned offset;
 519 };
 520
 521 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 522         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 523         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 524         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 525         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 526         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 527                 rx_unknown_protocol)},
 528         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 529         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 530         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 531         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 532 };
 533
 534 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 535                 sizeof(rte_i40e_stats_strings[0]))
 536
 537 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 538         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 539                 tx_dropped_link_down)},
 540         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 541         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 542                 illegal_bytes)},
 543         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 544         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 545                 mac_local_faults)},
 546         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_remote_faults)},
 548         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 549                 rx_length_errors)},
 550         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 551         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 552         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 553         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 554         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 555         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_127)},
 557         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_255)},
 559         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_511)},
 561         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_1023)},
 563         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1522)},
 565         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_big)},
 567         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 568                 rx_undersize)},
 569         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_oversize)},
 571         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 572                 mac_short_packet_dropped)},
 573         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_fragments)},
 575         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 576         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 577         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_127)},
 579         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_255)},
 581         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_511)},
 583         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_1023)},
 585         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1522)},
 587         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_big)},
 589         {"rx_flow_director_atr_match_packets",
 590                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 591         {"rx_flow_director_sb_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 593         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 594                 tx_lpi_status)},
 595         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 rx_lpi_status)},
 597         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_count)},
 599         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_count)},
 601 };
 602
 603 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 604                 sizeof(rte_i40e_hw_port_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_rx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_rx)},
 611 };
 612
 613 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 614                 sizeof(rte_i40e_rxq_prio_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_tx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_tx)},
 621         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_2_xoff)},
 623 };
 624
 625 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 626                 sizeof(rte_i40e_txq_prio_strings[0]))
 627
 628 static int
 629 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 630         struct rte_pci_device *pci_dev)
 631 {
 632         char name[RTE_ETH_NAME_MAX_LEN];
 633         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 634         int i, retval;
 635
 636         if (pci_dev->device.devargs) {
 637                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 638                                 &eth_da);
 639                 if (retval)
 640                         return retval;
 641         }
 642
 643         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 644                 sizeof(struct i40e_adapter),
 645                 eth_dev_pci_specific_init, pci_dev,
 646                 eth_i40e_dev_init, NULL);
 647
 648         if (retval || eth_da.nb_representor_ports < 1)
 649                 return retval;
 650
 651         /* probe VF representor ports */
 652         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 653                 pci_dev->device.name);
 654
 655         if (pf_ethdev == NULL)
 656                 return -ENODEV;
 657
 658         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 659                 struct i40e_vf_representor representor = {
 660                         .vf_id = eth_da.representor_ports[i],
 661                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 662                                 pf_ethdev->data->dev_private)->switch_domain_id,
 663                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 664                                 pf_ethdev->data->dev_private)
 665                 };
 666
 667                 /* representor port net_bdf_port */
 668                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 669                         pci_dev->device.name, eth_da.representor_ports[i]);
 670
 671                 retval = rte_eth_dev_create(&pci_dev->device, name,
 672                         sizeof(struct i40e_vf_representor), NULL, NULL,
 673                         i40e_vf_representor_init, &representor);
 674
 675                 if (retval)
 676                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 677                                 "representor %s.", name);
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 684 {
 685         struct rte_eth_dev *ethdev;
 686
 687         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 688         if (!ethdev)
 689                 return 0;
 690
 691         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 692                 return rte_eth_dev_pci_generic_remove(pci_dev,
 693                                         i40e_vf_representor_uninit);
 694         else
 695                 return rte_eth_dev_pci_generic_remove(pci_dev,
 696                                                 eth_i40e_dev_uninit);
 697 }
 698
 699 static struct rte_pci_driver rte_i40e_pmd = {
 700         .id_table = pci_id_i40e_map,
 701         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 702         .probe = eth_i40e_pci_probe,
 703         .remove = eth_i40e_pci_remove,
 704 };
 705
 706 static inline void
 707 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 708                          uint32_t reg_val)
 709 {
 710         uint32_t ori_reg_val;
 711         struct rte_eth_dev *dev;
 712
 713         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 714         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 715         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 716         if (ori_reg_val != reg_val)
 717                 PMD_DRV_LOG(WARNING,
 718                             "i40e device %s changed global register [0x%08x]."
 719                             " original: 0x%08x, new: 0x%08x",
 720                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 721 }
 722
 723 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 724 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 725 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 726
 727 #ifndef I40E_GLQF_ORT
 728 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 729 #endif
 730 #ifndef I40E_GLQF_PIT
 731 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 732 #endif
 733 #ifndef I40E_GLQF_L3_MAP
 734 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 735 #endif
 736
 737 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 738 {
 739         /*
 740          * Initialize registers for parsing packet type of QinQ
 741          * This should be removed from code once proper
 742          * configuration API is added to avoid configuration conflicts
 743          * between ports of the same device.
 744          */
 745         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 746         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 747 }
 748
 749 static inline void i40e_config_automask(struct i40e_pf *pf)
 750 {
 751         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 752         uint32_t val;
 753
 754         /* INTENA flag is not auto-cleared for interrupt */
 755         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 756         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 757                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 758
 759         /* If support multi-driver, PF will use INT0. */
 760         if (!pf->support_multi_driver)
 761                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 762
 763         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 764 }
 765
 766 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 767
 768 /*
 769  * Add a ethertype filter to drop all flow control frames transmitted
 770  * from VSIs.
 771 */
 772 static void
 773 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 774 {
 775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 776         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 777                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 778                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 779         int ret;
 780
 781         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 782                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 783                                 pf->main_vsi_seid, 0,
 784                                 TRUE, NULL, NULL);
 785         if (ret)
 786                 PMD_INIT_LOG(ERR,
 787                         "Failed to add filter to drop flow control frames from VSIs.");
 788 }
 789
 790 static int
 791 floating_veb_list_handler(__rte_unused const char *key,
 792                           const char *floating_veb_value,
 793                           void *opaque)
 794 {
 795         int idx = 0;
 796         unsigned int count = 0;
 797         char *end = NULL;
 798         int min, max;
 799         bool *vf_floating_veb = opaque;
 800
 801         while (isblank(*floating_veb_value))
 802                 floating_veb_value++;
 803
 804         /* Reset floating VEB configuration for VFs */
 805         for (idx = 0; idx < I40E_MAX_VF; idx++)
 806                 vf_floating_veb[idx] = false;
 807
 808         min = I40E_MAX_VF;
 809         do {
 810                 while (isblank(*floating_veb_value))
 811                         floating_veb_value++;
 812                 if (*floating_veb_value == '\0')
 813                         return -1;
 814                 errno = 0;
 815                 idx = strtoul(floating_veb_value, &end, 10);
 816                 if (errno || end == NULL)
 817                         return -1;
 818                 while (isblank(*end))
 819                         end++;
 820                 if (*end == '-') {
 821                         min = idx;
 822                 } else if ((*end == ';') || (*end == '\0')) {
 823                         max = idx;
 824                         if (min == I40E_MAX_VF)
 825                                 min = idx;
 826                         if (max >= I40E_MAX_VF)
 827                                 max = I40E_MAX_VF - 1;
 828                         for (idx = min; idx <= max; idx++) {
 829                                 vf_floating_veb[idx] = true;
 830                                 count++;
 831                         }
 832                         min = I40E_MAX_VF;
 833                 } else {
 834                         return -1;
 835                 }
 836                 floating_veb_value = end + 1;
 837         } while (*end != '\0');
 838
 839         if (count == 0)
 840                 return -1;
 841
 842         return 0;
 843 }
 844
 845 static void
 846 config_vf_floating_veb(struct rte_devargs *devargs,
 847                        uint16_t floating_veb,
 848                        bool *vf_floating_veb)
 849 {
 850         struct rte_kvargs *kvlist;
 851         int i;
 852         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 853
 854         if (!floating_veb)
 855                 return;
 856         /* All the VFs attach to the floating VEB by default
 857          * when the floating VEB is enabled.
 858          */
 859         for (i = 0; i < I40E_MAX_VF; i++)
 860                 vf_floating_veb[i] = true;
 861
 862         if (devargs == NULL)
 863                 return;
 864
 865         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 866         if (kvlist == NULL)
 867                 return;
 868
 869         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         /* When the floating_veb_list parameter exists, all the VFs
 874          * will attach to the legacy VEB firstly, then configure VFs
 875          * to the floating VEB according to the floating_veb_list.
 876          */
 877         if (rte_kvargs_process(kvlist, floating_veb_list,
 878                                floating_veb_list_handler,
 879                                vf_floating_veb) < 0) {
 880                 rte_kvargs_free(kvlist);
 881                 return;
 882         }
 883         rte_kvargs_free(kvlist);
 884 }
 885
 886 static int
 887 i40e_check_floating_handler(__rte_unused const char *key,
 888                             const char *value,
 889                             __rte_unused void *opaque)
 890 {
 891         if (strcmp(value, "1"))
 892                 return -1;
 893
 894         return 0;
 895 }
 896
 897 static int
 898 is_floating_veb_supported(struct rte_devargs *devargs)
 899 {
 900         struct rte_kvargs *kvlist;
 901         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 902
 903         if (devargs == NULL)
 904                 return 0;
 905
 906         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 907         if (kvlist == NULL)
 908                 return 0;
 909
 910         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 911                 rte_kvargs_free(kvlist);
 912                 return 0;
 913         }
 914         /* Floating VEB is enabled when there's key-value:
 915          * enable_floating_veb=1
 916          */
 917         if (rte_kvargs_process(kvlist, floating_veb_key,
 918                                i40e_check_floating_handler, NULL) < 0) {
 919                 rte_kvargs_free(kvlist);
 920                 return 0;
 921         }
 922         rte_kvargs_free(kvlist);
 923
 924         return 1;
 925 }
 926
 927 static void
 928 config_floating_veb(struct rte_eth_dev *dev)
 929 {
 930         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 931         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933
 934         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 935
 936         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 937                 pf->floating_veb =
 938                         is_floating_veb_supported(pci_dev->device.devargs);
 939                 config_vf_floating_veb(pci_dev->device.devargs,
 940                                        pf->floating_veb,
 941                                        pf->floating_veb_list);
 942         } else {
 943                 pf->floating_veb = false;
 944         }
 945 }
 946
 947 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 948 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 949
 950 static int
 951 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 952 {
 953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 954         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 955         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 956         int ret;
 957
 958         struct rte_hash_parameters ethertype_hash_params = {
 959                 .name = ethertype_hash_name,
 960                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 961                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 962                 .hash_func = rte_hash_crc,
 963                 .hash_func_init_val = 0,
 964                 .socket_id = rte_socket_id(),
 965         };
 966
 967         /* Initialize ethertype filter rule list and hash */
 968         TAILQ_INIT(&ethertype_rule->ethertype_list);
 969         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 970                  "ethertype_%s", dev->device->name);
 971         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 972         if (!ethertype_rule->hash_table) {
 973                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 974                 return -EINVAL;
 975         }
 976         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 977                                        sizeof(struct i40e_ethertype_filter *) *
 978                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 979                                        0);
 980         if (!ethertype_rule->hash_map) {
 981                 PMD_INIT_LOG(ERR,
 982                              "Failed to allocate memory for ethertype hash map!");
 983                 ret = -ENOMEM;
 984                 goto err_ethertype_hash_map_alloc;
 985         }
 986
 987         return 0;
 988
 989 err_ethertype_hash_map_alloc:
 990         rte_hash_free(ethertype_rule->hash_table);
 991
 992         return ret;
 993 }
 994
 995 static int
 996 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1000         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1001         int ret;
1002
1003         struct rte_hash_parameters tunnel_hash_params = {
1004                 .name = tunnel_hash_name,
1005                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1006                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1007                 .hash_func = rte_hash_crc,
1008                 .hash_func_init_val = 0,
1009                 .socket_id = rte_socket_id(),
1010         };
1011
1012         /* Initialize tunnel filter rule list and hash */
1013         TAILQ_INIT(&tunnel_rule->tunnel_list);
1014         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1015                  "tunnel_%s", dev->device->name);
1016         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1017         if (!tunnel_rule->hash_table) {
1018                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1019                 return -EINVAL;
1020         }
1021         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1022                                     sizeof(struct i40e_tunnel_filter *) *
1023                                     I40E_MAX_TUNNEL_FILTER_NUM,
1024                                     0);
1025         if (!tunnel_rule->hash_map) {
1026                 PMD_INIT_LOG(ERR,
1027                              "Failed to allocate memory for tunnel hash map!");
1028                 ret = -ENOMEM;
1029                 goto err_tunnel_hash_map_alloc;
1030         }
1031
1032         return 0;
1033
1034 err_tunnel_hash_map_alloc:
1035         rte_hash_free(tunnel_rule->hash_table);
1036
1037         return ret;
1038 }
1039
1040 static int
1041 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1042 {
1043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1044         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1045         struct i40e_fdir_info *fdir_info = &pf->fdir;
1046         char fdir_hash_name[RTE_HASH_NAMESIZE];
1047         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1048         uint32_t best = hw->func_caps.fd_filters_best_effort;
1049         struct rte_bitmap *bmp = NULL;
1050         uint32_t bmp_size;
1051         void *mem = NULL;
1052         uint32_t i = 0;
1053         int ret;
1054
1055         struct rte_hash_parameters fdir_hash_params = {
1056                 .name = fdir_hash_name,
1057                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1058                 .key_len = sizeof(struct i40e_fdir_input),
1059                 .hash_func = rte_hash_crc,
1060                 .hash_func_init_val = 0,
1061                 .socket_id = rte_socket_id(),
1062         };
1063
1064         /* Initialize flow director filter rule list and hash */
1065         TAILQ_INIT(&fdir_info->fdir_list);
1066         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1067                  "fdir_%s", dev->device->name);
1068         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1069         if (!fdir_info->hash_table) {
1070                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1071                 return -EINVAL;
1072         }
1073
1074         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1075                                           sizeof(struct i40e_fdir_filter *) *
1076                                           I40E_MAX_FDIR_FILTER_NUM,
1077                                           0);
1078         if (!fdir_info->hash_map) {
1079                 PMD_INIT_LOG(ERR,
1080                              "Failed to allocate memory for fdir hash map!");
1081                 ret = -ENOMEM;
1082                 goto err_fdir_hash_map_alloc;
1083         }
1084
1085         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1086                         sizeof(struct i40e_fdir_filter) *
1087                         I40E_MAX_FDIR_FILTER_NUM,
1088                         0);
1089
1090         if (!fdir_info->fdir_filter_array) {
1091                 PMD_INIT_LOG(ERR,
1092                              "Failed to allocate memory for fdir filter array!");
1093                 ret = -ENOMEM;
1094                 goto err_fdir_filter_array_alloc;
1095         }
1096
1097         fdir_info->fdir_space_size = alloc + best;
1098         fdir_info->fdir_actual_cnt = 0;
1099         fdir_info->fdir_guarantee_total_space = alloc;
1100         fdir_info->fdir_guarantee_free_space =
1101                 fdir_info->fdir_guarantee_total_space;
1102
1103         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1104
1105         fdir_info->fdir_flow_pool.pool =
1106                         rte_zmalloc("i40e_fdir_entry",
1107                                 sizeof(struct i40e_fdir_entry) *
1108                                 fdir_info->fdir_space_size,
1109                                 0);
1110
1111         if (!fdir_info->fdir_flow_pool.pool) {
1112                 PMD_INIT_LOG(ERR,
1113                              "Failed to allocate memory for bitmap flow!");
1114                 ret = -ENOMEM;
1115                 goto err_fdir_bitmap_flow_alloc;
1116         }
1117
1118         for (i = 0; i < fdir_info->fdir_space_size; i++)
1119                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1120
1121         bmp_size =
1122                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1123         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1124         if (mem == NULL) {
1125                 PMD_INIT_LOG(ERR,
1126                              "Failed to allocate memory for fdir bitmap!");
1127                 ret = -ENOMEM;
1128                 goto err_fdir_mem_alloc;
1129         }
1130         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1131         if (bmp == NULL) {
1132                 PMD_INIT_LOG(ERR,
1133                              "Failed to initialization fdir bitmap!");
1134                 ret = -ENOMEM;
1135                 goto err_fdir_bmp_alloc;
1136         }
1137         for (i = 0; i < fdir_info->fdir_space_size; i++)
1138                 rte_bitmap_set(bmp, i);
1139
1140         fdir_info->fdir_flow_pool.bitmap = bmp;
1141
1142         return 0;
1143
1144 err_fdir_bmp_alloc:
1145         rte_free(mem);
1146 err_fdir_mem_alloc:
1147         rte_free(fdir_info->fdir_flow_pool.pool);
1148 err_fdir_bitmap_flow_alloc:
1149         rte_free(fdir_info->fdir_filter_array);
1150 err_fdir_filter_array_alloc:
1151         rte_free(fdir_info->hash_map);
1152 err_fdir_hash_map_alloc:
1153         rte_hash_free(fdir_info->hash_table);
1154
1155         return ret;
1156 }
1157
1158 static void
1159 i40e_init_customized_info(struct i40e_pf *pf)
1160 {
1161         int i;
1162
1163         /* Initialize customized pctype */
1164         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1165                 pf->customized_pctype[i].index = i;
1166                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1167                 pf->customized_pctype[i].valid = false;
1168         }
1169
1170         pf->gtp_support = false;
1171         pf->esp_support = false;
1172 }
1173
1174 static void
1175 i40e_init_filter_invalidation(struct i40e_pf *pf)
1176 {
1177         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1178         struct i40e_fdir_info *fdir_info = &pf->fdir;
1179         uint32_t glqf_ctl_reg = 0;
1180
1181         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1182         if (!pf->support_multi_driver) {
1183                 fdir_info->fdir_invalprio = 1;
1184                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1185                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1186                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1187         } else {
1188                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1189                         fdir_info->fdir_invalprio = 1;
1190                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1191                 } else {
1192                         fdir_info->fdir_invalprio = 0;
1193                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1194                 }
1195         }
1196 }
1197
1198 void
1199 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1200 {
1201         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1202         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1203         struct i40e_queue_regions *info = &pf->queue_region;
1204         uint16_t i;
1205
1206         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1207                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1208
1209         memset(info, 0, sizeof(struct i40e_queue_regions));
1210 }
1211
1212 static int
1213 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1214                                const char *value,
1215                                void *opaque)
1216 {
1217         struct i40e_pf *pf;
1218         unsigned long support_multi_driver;
1219         char *end;
1220
1221         pf = (struct i40e_pf *)opaque;
1222
1223         errno = 0;
1224         support_multi_driver = strtoul(value, &end, 10);
1225         if (errno != 0 || end == value || *end != 0) {
1226                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1227                 return -(EINVAL);
1228         }
1229
1230         if (support_multi_driver == 1 || support_multi_driver == 0)
1231                 pf->support_multi_driver = (bool)support_multi_driver;
1232         else
1233                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1234                             "enable global configuration by default."
1235                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1236         return 0;
1237 }
1238
1239 static int
1240 i40e_support_multi_driver(struct rte_eth_dev *dev)
1241 {
1242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1243         struct rte_kvargs *kvlist;
1244         int kvargs_count;
1245
1246         /* Enable global configuration by default */
1247         pf->support_multi_driver = false;
1248
1249         if (!dev->device->devargs)
1250                 return 0;
1251
1252         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1253         if (!kvlist)
1254                 return -EINVAL;
1255
1256         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1257         if (!kvargs_count) {
1258                 rte_kvargs_free(kvlist);
1259                 return 0;
1260         }
1261
1262         if (kvargs_count > 1)
1263                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1264                             "the first invalid or last valid one is used !",
1265                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1266
1267         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1268                                i40e_parse_multi_drv_handler, pf) < 0) {
1269                 rte_kvargs_free(kvlist);
1270                 return -EINVAL;
1271         }
1272
1273         rte_kvargs_free(kvlist);
1274         return 0;
1275 }
1276
1277 static int
1278 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1279                                     uint32_t reg_addr, uint64_t reg_val,
1280                                     struct i40e_asq_cmd_details *cmd_details)
1281 {
1282         uint64_t ori_reg_val;
1283         struct rte_eth_dev *dev;
1284         int ret;
1285
1286         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1287         if (ret != I40E_SUCCESS) {
1288                 PMD_DRV_LOG(ERR,
1289                             "Fail to debug read from 0x%08x",
1290                             reg_addr);
1291                 return -EIO;
1292         }
1293         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1294
1295         if (ori_reg_val != reg_val)
1296                 PMD_DRV_LOG(WARNING,
1297                             "i40e device %s changed global register [0x%08x]."
1298                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1299                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1300
1301         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1302 }
1303
1304 static int
1305 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1306                                 const char *value,
1307                                 void *opaque)
1308 {
1309         struct i40e_adapter *ad = opaque;
1310         int use_latest_vec;
1311
1312         use_latest_vec = atoi(value);
1313
1314         if (use_latest_vec != 0 && use_latest_vec != 1)
1315                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1316
1317         ad->use_latest_vec = (uint8_t)use_latest_vec;
1318
1319         return 0;
1320 }
1321
1322 static int
1323 i40e_use_latest_vec(struct rte_eth_dev *dev)
1324 {
1325         struct i40e_adapter *ad =
1326                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1327         struct rte_kvargs *kvlist;
1328         int kvargs_count;
1329
1330         ad->use_latest_vec = false;
1331
1332         if (!dev->device->devargs)
1333                 return 0;
1334
1335         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1336         if (!kvlist)
1337                 return -EINVAL;
1338
1339         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1340         if (!kvargs_count) {
1341                 rte_kvargs_free(kvlist);
1342                 return 0;
1343         }
1344
1345         if (kvargs_count > 1)
1346                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1347                             "the first invalid or last valid one is used !",
1348                             ETH_I40E_USE_LATEST_VEC);
1349
1350         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1351                                 i40e_parse_latest_vec_handler, ad) < 0) {
1352                 rte_kvargs_free(kvlist);
1353                 return -EINVAL;
1354         }
1355
1356         rte_kvargs_free(kvlist);
1357         return 0;
1358 }
1359
1360 static int
1361 read_vf_msg_config(__rte_unused const char *key,
1362                                const char *value,
1363                                void *opaque)
1364 {
1365         struct i40e_vf_msg_cfg *cfg = opaque;
1366
1367         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1368                         &cfg->ignore_second) != 3) {
1369                 memset(cfg, 0, sizeof(*cfg));
1370                 PMD_DRV_LOG(ERR, "format error! example: "
1371                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1372                 return -EINVAL;
1373         }
1374
1375         /*
1376          * If the message validation function been enabled, the 'period'
1377          * and 'ignore_second' must greater than 0.
1378          */
1379         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1380                 memset(cfg, 0, sizeof(*cfg));
1381                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1382                                 " number must be greater than 0!",
1383                                 ETH_I40E_VF_MSG_CFG);
1384                 return -EINVAL;
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int
1391 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1392                 struct i40e_vf_msg_cfg *msg_cfg)
1393 {
1394         struct rte_kvargs *kvlist;
1395         int kvargs_count;
1396         int ret = 0;
1397
1398         memset(msg_cfg, 0, sizeof(*msg_cfg));
1399
1400         if (!dev->device->devargs)
1401                 return ret;
1402
1403         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1404         if (!kvlist)
1405                 return -EINVAL;
1406
1407         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1408         if (!kvargs_count)
1409                 goto free_end;
1410
1411         if (kvargs_count > 1) {
1412                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1413                                 ETH_I40E_VF_MSG_CFG);
1414                 ret = -EINVAL;
1415                 goto free_end;
1416         }
1417
1418         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1419                         read_vf_msg_config, msg_cfg) < 0)
1420                 ret = -EINVAL;
1421
1422 free_end:
1423         rte_kvargs_free(kvlist);
1424         return ret;
1425 }
1426
1427 #define I40E_ALARM_INTERVAL 50000 /* us */
1428
1429 static int
1430 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1431 {
1432         struct rte_pci_device *pci_dev;
1433         struct rte_intr_handle *intr_handle;
1434         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1435         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1436         struct i40e_vsi *vsi;
1437         int ret;
1438         uint32_t len, val;
1439         uint8_t aq_fail = 0;
1440
1441         PMD_INIT_FUNC_TRACE();
1442
1443         dev->dev_ops = &i40e_eth_dev_ops;
1444         dev->rx_queue_count = i40e_dev_rx_queue_count;
1445         dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1446         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1447         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1448         dev->rx_pkt_burst = i40e_recv_pkts;
1449         dev->tx_pkt_burst = i40e_xmit_pkts;
1450         dev->tx_pkt_prepare = i40e_prep_pkts;
1451
1452         /* for secondary processes, we don't initialise any further as primary
1453          * has already done this work. Only check we don't need a different
1454          * RX function */
1455         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1456                 i40e_set_rx_function(dev);
1457                 i40e_set_tx_function(dev);
1458                 return 0;
1459         }
1460         i40e_set_default_ptype_table(dev);
1461         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1462         intr_handle = &pci_dev->intr_handle;
1463
1464         rte_eth_copy_pci_info(dev, pci_dev);
1465         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1466
1467         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1468         pf->adapter->eth_dev = dev;
1469         pf->dev_data = dev->data;
1470
1471         hw->back = I40E_PF_TO_ADAPTER(pf);
1472         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1473         if (!hw->hw_addr) {
1474                 PMD_INIT_LOG(ERR,
1475                         "Hardware is not available, as address is NULL");
1476                 return -ENODEV;
1477         }
1478
1479         hw->vendor_id = pci_dev->id.vendor_id;
1480         hw->device_id = pci_dev->id.device_id;
1481         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1482         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1483         hw->bus.device = pci_dev->addr.devid;
1484         hw->bus.func = pci_dev->addr.function;
1485         hw->adapter_stopped = 0;
1486         hw->adapter_closed = 0;
1487
1488         /* Init switch device pointer */
1489         hw->switch_dev = NULL;
1490
1491         /*
1492          * Switch Tag value should not be identical to either the First Tag
1493          * or Second Tag values. So set something other than common Ethertype
1494          * for internal switching.
1495          */
1496         hw->switch_tag = 0xffff;
1497
1498         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1499         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1500                 PMD_INIT_LOG(ERR, "\nERROR: "
1501                         "Firmware recovery mode detected. Limiting functionality.\n"
1502                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1503                         "User Guide for details on firmware recovery mode.");
1504                 return -EIO;
1505         }
1506
1507         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1508         /* Check if need to support multi-driver */
1509         i40e_support_multi_driver(dev);
1510         /* Check if users want the latest supported vec path */
1511         i40e_use_latest_vec(dev);
1512
1513         /* Make sure all is clean before doing PF reset */
1514         i40e_clear_hw(hw);
1515
1516         /* Reset here to make sure all is clean for each PF */
1517         ret = i40e_pf_reset(hw);
1518         if (ret) {
1519                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1520                 return ret;
1521         }
1522
1523         /* Initialize the shared code (base driver) */
1524         ret = i40e_init_shared_code(hw);
1525         if (ret) {
1526                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1527                 return ret;
1528         }
1529
1530         /* Initialize the parameters for adminq */
1531         i40e_init_adminq_parameter(hw);
1532         ret = i40e_init_adminq(hw);
1533         if (ret != I40E_SUCCESS) {
1534                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1535                 return -EIO;
1536         }
1537         /* Firmware of SFP x722 does not support adminq option */
1538         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1539                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1540
1541         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1542                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1543                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1544                      ((hw->nvm.version >> 12) & 0xf),
1545                      ((hw->nvm.version >> 4) & 0xff),
1546                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1547
1548         /* Initialize the hardware */
1549         i40e_hw_init(dev);
1550
1551         i40e_config_automask(pf);
1552
1553         i40e_set_default_pctype_table(dev);
1554
1555         /*
1556          * To work around the NVM issue, initialize registers
1557          * for packet type of QinQ by software.
1558          * It should be removed once issues are fixed in NVM.
1559          */
1560         if (!pf->support_multi_driver)
1561                 i40e_GLQF_reg_init(hw);
1562
1563         /* Initialize the input set for filters (hash and fd) to default value */
1564         i40e_filter_input_set_init(pf);
1565
1566         /* initialise the L3_MAP register */
1567         if (!pf->support_multi_driver) {
1568                 ret = i40e_aq_debug_write_global_register(hw,
1569                                                    I40E_GLQF_L3_MAP(40),
1570                                                    0x00000028,  NULL);
1571                 if (ret)
1572                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1573                                      ret);
1574                 PMD_INIT_LOG(DEBUG,
1575                              "Global register 0x%08x is changed with 0x28",
1576                              I40E_GLQF_L3_MAP(40));
1577         }
1578
1579         /* Need the special FW version to support floating VEB */
1580         config_floating_veb(dev);
1581         /* Clear PXE mode */
1582         i40e_clear_pxe_mode(hw);
1583         i40e_dev_sync_phy_type(hw);
1584
1585         /*
1586          * On X710, performance number is far from the expectation on recent
1587          * firmware versions. The fix for this issue may not be integrated in
1588          * the following firmware version. So the workaround in software driver
1589          * is needed. It needs to modify the initial values of 3 internal only
1590          * registers. Note that the workaround can be removed when it is fixed
1591          * in firmware in the future.
1592          */
1593         i40e_configure_registers(hw);
1594
1595         /* Get hw capabilities */
1596         ret = i40e_get_cap(hw);
1597         if (ret != I40E_SUCCESS) {
1598                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1599                 goto err_get_capabilities;
1600         }
1601
1602         /* Initialize parameters for PF */
1603         ret = i40e_pf_parameter_init(dev);
1604         if (ret != 0) {
1605                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1606                 goto err_parameter_init;
1607         }
1608
1609         /* Initialize the queue management */
1610         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1611         if (ret < 0) {
1612                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1613                 goto err_qp_pool_init;
1614         }
1615         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1616                                 hw->func_caps.num_msix_vectors - 1);
1617         if (ret < 0) {
1618                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1619                 goto err_msix_pool_init;
1620         }
1621
1622         /* Initialize lan hmc */
1623         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1624                                 hw->func_caps.num_rx_qp, 0, 0);
1625         if (ret != I40E_SUCCESS) {
1626                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1627                 goto err_init_lan_hmc;
1628         }
1629
1630         /* Configure lan hmc */
1631         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1632         if (ret != I40E_SUCCESS) {
1633                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1634                 goto err_configure_lan_hmc;
1635         }
1636
1637         /* Get and check the mac address */
1638         i40e_get_mac_addr(hw, hw->mac.addr);
1639         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1640                 PMD_INIT_LOG(ERR, "mac address is not valid");
1641                 ret = -EIO;
1642                 goto err_get_mac_addr;
1643         }
1644         /* Copy the permanent MAC address */
1645         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1646                         (struct rte_ether_addr *)hw->mac.perm_addr);
1647
1648         /* Disable flow control */
1649         hw->fc.requested_mode = I40E_FC_NONE;
1650         i40e_set_fc(hw, &aq_fail, TRUE);
1651
1652         /* Set the global registers with default ether type value */
1653         if (!pf->support_multi_driver) {
1654                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1655                                          RTE_ETHER_TYPE_VLAN);
1656                 if (ret != I40E_SUCCESS) {
1657                         PMD_INIT_LOG(ERR,
1658                                      "Failed to set the default outer "
1659                                      "VLAN ether type");
1660                         goto err_setup_pf_switch;
1661                 }
1662         }
1663
1664         /* PF setup, which includes VSI setup */
1665         ret = i40e_pf_setup(pf);
1666         if (ret) {
1667                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1668                 goto err_setup_pf_switch;
1669         }
1670
1671         vsi = pf->main_vsi;
1672
1673         /* Disable double vlan by default */
1674         i40e_vsi_config_double_vlan(vsi, FALSE);
1675
1676         /* Disable S-TAG identification when floating_veb is disabled */
1677         if (!pf->floating_veb) {
1678                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1679                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1680                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1681                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1682                 }
1683         }
1684
1685         if (!vsi->max_macaddrs)
1686                 len = RTE_ETHER_ADDR_LEN;
1687         else
1688                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1689
1690         /* Should be after VSI initialized */
1691         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1692         if (!dev->data->mac_addrs) {
1693                 PMD_INIT_LOG(ERR,
1694                         "Failed to allocated memory for storing mac address");
1695                 goto err_mac_alloc;
1696         }
1697         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1698                                         &dev->data->mac_addrs[0]);
1699
1700         /* Init dcb to sw mode by default */
1701         ret = i40e_dcb_init_configure(dev, TRUE);
1702         if (ret != I40E_SUCCESS) {
1703                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1704                 pf->flags &= ~I40E_FLAG_DCB;
1705         }
1706         /* Update HW struct after DCB configuration */
1707         i40e_get_cap(hw);
1708
1709         /* initialize pf host driver to setup SRIOV resource if applicable */
1710         i40e_pf_host_init(dev);
1711
1712         /* register callback func to eal lib */
1713         rte_intr_callback_register(intr_handle,
1714                                    i40e_dev_interrupt_handler, dev);
1715
1716         /* configure and enable device interrupt */
1717         i40e_pf_config_irq0(hw, TRUE);
1718         i40e_pf_enable_irq0(hw);
1719
1720         /* enable uio intr after callback register */
1721         rte_intr_enable(intr_handle);
1722
1723         /* By default disable flexible payload in global configuration */
1724         if (!pf->support_multi_driver)
1725                 i40e_flex_payload_reg_set_default(hw);
1726
1727         /*
1728          * Add an ethertype filter to drop all flow control frames transmitted
1729          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1730          * frames to wire.
1731          */
1732         i40e_add_tx_flow_control_drop_filter(pf);
1733
1734         /* Set the max frame size to 0x2600 by default,
1735          * in case other drivers changed the default value.
1736          */
1737         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1738
1739         /* initialize mirror rule list */
1740         TAILQ_INIT(&pf->mirror_list);
1741
1742         /* initialize RSS rule list */
1743         TAILQ_INIT(&pf->rss_config_list);
1744
1745         /* initialize Traffic Manager configuration */
1746         i40e_tm_conf_init(dev);
1747
1748         /* Initialize customized information */
1749         i40e_init_customized_info(pf);
1750
1751         /* Initialize the filter invalidation configuration */
1752         i40e_init_filter_invalidation(pf);
1753
1754         ret = i40e_init_ethtype_filter_list(dev);
1755         if (ret < 0)
1756                 goto err_init_ethtype_filter_list;
1757         ret = i40e_init_tunnel_filter_list(dev);
1758         if (ret < 0)
1759                 goto err_init_tunnel_filter_list;
1760         ret = i40e_init_fdir_filter_list(dev);
1761         if (ret < 0)
1762                 goto err_init_fdir_filter_list;
1763
1764         /* initialize queue region configuration */
1765         i40e_init_queue_region_conf(dev);
1766
1767         /* initialize RSS configuration from rte_flow */
1768         memset(&pf->rss_info, 0,
1769                 sizeof(struct i40e_rte_flow_rss_conf));
1770
1771         /* reset all stats of the device, including pf and main vsi */
1772         i40e_dev_stats_reset(dev);
1773
1774         return 0;
1775
1776 err_init_fdir_filter_list:
1777         rte_free(pf->tunnel.hash_table);
1778         rte_free(pf->tunnel.hash_map);
1779 err_init_tunnel_filter_list:
1780         rte_free(pf->ethertype.hash_table);
1781         rte_free(pf->ethertype.hash_map);
1782 err_init_ethtype_filter_list:
1783         rte_free(dev->data->mac_addrs);
1784         dev->data->mac_addrs = NULL;
1785 err_mac_alloc:
1786         i40e_vsi_release(pf->main_vsi);
1787 err_setup_pf_switch:
1788 err_get_mac_addr:
1789 err_configure_lan_hmc:
1790         (void)i40e_shutdown_lan_hmc(hw);
1791 err_init_lan_hmc:
1792         i40e_res_pool_destroy(&pf->msix_pool);
1793 err_msix_pool_init:
1794         i40e_res_pool_destroy(&pf->qp_pool);
1795 err_qp_pool_init:
1796 err_parameter_init:
1797 err_get_capabilities:
1798         (void)i40e_shutdown_adminq(hw);
1799
1800         return ret;
1801 }
1802
1803 static void
1804 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1805 {
1806         struct i40e_ethertype_filter *p_ethertype;
1807         struct i40e_ethertype_rule *ethertype_rule;
1808
1809         ethertype_rule = &pf->ethertype;
1810         /* Remove all ethertype filter rules and hash */
1811         if (ethertype_rule->hash_map)
1812                 rte_free(ethertype_rule->hash_map);
1813         if (ethertype_rule->hash_table)
1814                 rte_hash_free(ethertype_rule->hash_table);
1815
1816         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1817                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1818                              p_ethertype, rules);
1819                 rte_free(p_ethertype);
1820         }
1821 }
1822
1823 static void
1824 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1825 {
1826         struct i40e_tunnel_filter *p_tunnel;
1827         struct i40e_tunnel_rule *tunnel_rule;
1828
1829         tunnel_rule = &pf->tunnel;
1830         /* Remove all tunnel director rules and hash */
1831         if (tunnel_rule->hash_map)
1832                 rte_free(tunnel_rule->hash_map);
1833         if (tunnel_rule->hash_table)
1834                 rte_hash_free(tunnel_rule->hash_table);
1835
1836         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1837                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1838                 rte_free(p_tunnel);
1839         }
1840 }
1841
1842 static void
1843 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1844 {
1845         struct i40e_fdir_filter *p_fdir;
1846         struct i40e_fdir_info *fdir_info;
1847
1848         fdir_info = &pf->fdir;
1849
1850         /* Remove all flow director rules */
1851         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1852                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1853 }
1854
1855 static void
1856 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1857 {
1858         struct i40e_fdir_info *fdir_info;
1859
1860         fdir_info = &pf->fdir;
1861
1862         /* flow director memory cleanup */
1863         if (fdir_info->hash_map)
1864                 rte_free(fdir_info->hash_map);
1865         if (fdir_info->hash_table)
1866                 rte_hash_free(fdir_info->hash_table);
1867         if (fdir_info->fdir_flow_pool.bitmap)
1868                 rte_free(fdir_info->fdir_flow_pool.bitmap);
1869         if (fdir_info->fdir_flow_pool.pool)
1870                 rte_free(fdir_info->fdir_flow_pool.pool);
1871         if (fdir_info->fdir_filter_array)
1872                 rte_free(fdir_info->fdir_filter_array);
1873 }
1874
1875 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1876 {
1877         /*
1878          * Disable by default flexible payload
1879          * for corresponding L2/L3/L4 layers.
1880          */
1881         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1882         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1883         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1884 }
1885
1886 static int
1887 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1888 {
1889         struct i40e_hw *hw;
1890
1891         PMD_INIT_FUNC_TRACE();
1892
1893         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1894                 return 0;
1895
1896         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897
1898         if (hw->adapter_closed == 0)
1899                 i40e_dev_close(dev);
1900
1901         return 0;
1902 }
1903
1904 static int
1905 i40e_dev_configure(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_adapter *ad =
1908                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1909         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1912         int i, ret;
1913
1914         ret = i40e_dev_sync_phy_type(hw);
1915         if (ret)
1916                 return ret;
1917
1918         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1919          * bulk allocation or vector Rx preconditions we will reset it.
1920          */
1921         ad->rx_bulk_alloc_allowed = true;
1922         ad->rx_vec_allowed = true;
1923         ad->tx_simple_allowed = true;
1924         ad->tx_vec_allowed = true;
1925
1926         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1927                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1928
1929         /* Only legacy filter API needs the following fdir config. So when the
1930          * legacy filter API is deprecated, the following codes should also be
1931          * removed.
1932          */
1933         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1934                 ret = i40e_fdir_setup(pf);
1935                 if (ret != I40E_SUCCESS) {
1936                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1937                         return -ENOTSUP;
1938                 }
1939                 ret = i40e_fdir_configure(dev);
1940                 if (ret < 0) {
1941                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1942                         goto err;
1943                 }
1944         } else
1945                 i40e_fdir_teardown(pf);
1946
1947         ret = i40e_dev_init_vlan(dev);
1948         if (ret < 0)
1949                 goto err;
1950
1951         /* VMDQ setup.
1952          *  General PMD driver call sequence are NIC init, configure,
1953          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1954          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1955          *  applicable. So, VMDQ setting has to be done before
1956          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1957          *  For RSS setting, it will try to calculate actual configured RX queue
1958          *  number, which will be available after rx_queue_setup(). dev_start()
1959          *  function is good to place RSS setup.
1960          */
1961         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1962                 ret = i40e_vmdq_setup(dev);
1963                 if (ret)
1964                         goto err;
1965         }
1966
1967         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1968                 ret = i40e_dcb_setup(dev);
1969                 if (ret) {
1970                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1971                         goto err_dcb;
1972                 }
1973         }
1974
1975         TAILQ_INIT(&pf->flow_list);
1976
1977         return 0;
1978
1979 err_dcb:
1980         /* need to release vmdq resource if exists */
1981         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1982                 i40e_vsi_release(pf->vmdq[i].vsi);
1983                 pf->vmdq[i].vsi = NULL;
1984         }
1985         rte_free(pf->vmdq);
1986         pf->vmdq = NULL;
1987 err:
1988         /* Need to release fdir resource if exists.
1989          * Only legacy filter API needs the following fdir config. So when the
1990          * legacy filter API is deprecated, the following code should also be
1991          * removed.
1992          */
1993         i40e_fdir_teardown(pf);
1994         return ret;
1995 }
1996
1997 void
1998 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1999 {
2000         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2001         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2002         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2003         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2004         uint16_t msix_vect = vsi->msix_intr;
2005         uint16_t i;
2006
2007         for (i = 0; i < vsi->nb_qps; i++) {
2008                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2009                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2010                 rte_wmb();
2011         }
2012
2013         if (vsi->type != I40E_VSI_SRIOV) {
2014                 if (!rte_intr_allow_others(intr_handle)) {
2015                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2016                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2017                         I40E_WRITE_REG(hw,
2018                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2019                                        0);
2020                 } else {
2021                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2022                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2023                         I40E_WRITE_REG(hw,
2024                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2025                                                        msix_vect - 1), 0);
2026                 }
2027         } else {
2028                 uint32_t reg;
2029                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2030                         vsi->user_param + (msix_vect - 1);
2031
2032                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2033                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2034         }
2035         I40E_WRITE_FLUSH(hw);
2036 }
2037
2038 static void
2039 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2040                        int base_queue, int nb_queue,
2041                        uint16_t itr_idx)
2042 {
2043         int i;
2044         uint32_t val;
2045         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2046         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2047
2048         /* Bind all RX queues to allocated MSIX interrupt */
2049         for (i = 0; i < nb_queue; i++) {
2050                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2051                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2052                         ((base_queue + i + 1) <<
2053                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2054                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2055                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2056
2057                 if (i == nb_queue - 1)
2058                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2059                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2060         }
2061
2062         /* Write first RX queue to Link list register as the head element */
2063         if (vsi->type != I40E_VSI_SRIOV) {
2064                 uint16_t interval =
2065                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2066
2067                 if (msix_vect == I40E_MISC_VEC_ID) {
2068                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2069                                        (base_queue <<
2070                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2071                                        (0x0 <<
2072                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2073                         I40E_WRITE_REG(hw,
2074                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2075                                        interval);
2076                 } else {
2077                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2078                                        (base_queue <<
2079                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2080                                        (0x0 <<
2081                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2082                         I40E_WRITE_REG(hw,
2083                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2084                                                        msix_vect - 1),
2085                                        interval);
2086                 }
2087         } else {
2088                 uint32_t reg;
2089
2090                 if (msix_vect == I40E_MISC_VEC_ID) {
2091                         I40E_WRITE_REG(hw,
2092                                        I40E_VPINT_LNKLST0(vsi->user_param),
2093                                        (base_queue <<
2094                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2095                                        (0x0 <<
2096                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2097                 } else {
2098                         /* num_msix_vectors_vf needs to minus irq0 */
2099                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2100                                 vsi->user_param + (msix_vect - 1);
2101
2102                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2103                                        (base_queue <<
2104                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2105                                        (0x0 <<
2106                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2107                 }
2108         }
2109
2110         I40E_WRITE_FLUSH(hw);
2111 }
2112
2113 int
2114 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2115 {
2116         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2117         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2118         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2119         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2120         uint16_t msix_vect = vsi->msix_intr;
2121         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2122         uint16_t queue_idx = 0;
2123         int record = 0;
2124         int i;
2125
2126         for (i = 0; i < vsi->nb_qps; i++) {
2127                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2128                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2129         }
2130
2131         /* VF bind interrupt */
2132         if (vsi->type == I40E_VSI_SRIOV) {
2133                 if (vsi->nb_msix == 0) {
2134                         PMD_DRV_LOG(ERR, "No msix resource");
2135                         return -EINVAL;
2136                 }
2137                 __vsi_queues_bind_intr(vsi, msix_vect,
2138                                        vsi->base_queue, vsi->nb_qps,
2139                                        itr_idx);
2140                 return 0;
2141         }
2142
2143         /* PF & VMDq bind interrupt */
2144         if (rte_intr_dp_is_en(intr_handle)) {
2145                 if (vsi->type == I40E_VSI_MAIN) {
2146                         queue_idx = 0;
2147                         record = 1;
2148                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2149                         struct i40e_vsi *main_vsi =
2150                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2151                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2152                         record = 1;
2153                 }
2154         }
2155
2156         for (i = 0; i < vsi->nb_used_qps; i++) {
2157                 if (vsi->nb_msix == 0) {
2158                         PMD_DRV_LOG(ERR, "No msix resource");
2159                         return -EINVAL;
2160                 } else if (nb_msix <= 1) {
2161                         if (!rte_intr_allow_others(intr_handle))
2162                                 /* allow to share MISC_VEC_ID */
2163                                 msix_vect = I40E_MISC_VEC_ID;
2164
2165                         /* no enough msix_vect, map all to one */
2166                         __vsi_queues_bind_intr(vsi, msix_vect,
2167                                                vsi->base_queue + i,
2168                                                vsi->nb_used_qps - i,
2169                                                itr_idx);
2170                         for (; !!record && i < vsi->nb_used_qps; i++)
2171                                 intr_handle->intr_vec[queue_idx + i] =
2172                                         msix_vect;
2173                         break;
2174                 }
2175                 /* 1:1 queue/msix_vect mapping */
2176                 __vsi_queues_bind_intr(vsi, msix_vect,
2177                                        vsi->base_queue + i, 1,
2178                                        itr_idx);
2179                 if (!!record)
2180                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2181
2182                 msix_vect++;
2183                 nb_msix--;
2184         }
2185
2186         return 0;
2187 }
2188
2189 void
2190 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2191 {
2192         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2193         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2194         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2195         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2196         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2197         uint16_t msix_intr, i;
2198
2199         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2200                 for (i = 0; i < vsi->nb_msix; i++) {
2201                         msix_intr = vsi->msix_intr + i;
2202                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2203                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2204                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2205                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2206                 }
2207         else
2208                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2209                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2210                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2211                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2212
2213         I40E_WRITE_FLUSH(hw);
2214 }
2215
2216 void
2217 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2218 {
2219         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2220         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2221         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2222         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2223         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2224         uint16_t msix_intr, i;
2225
2226         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2227                 for (i = 0; i < vsi->nb_msix; i++) {
2228                         msix_intr = vsi->msix_intr + i;
2229                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2230                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2231                 }
2232         else
2233                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2234                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2235
2236         I40E_WRITE_FLUSH(hw);
2237 }
2238
2239 static inline uint8_t
2240 i40e_parse_link_speeds(uint16_t link_speeds)
2241 {
2242         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2243
2244         if (link_speeds & ETH_LINK_SPEED_40G)
2245                 link_speed |= I40E_LINK_SPEED_40GB;
2246         if (link_speeds & ETH_LINK_SPEED_25G)
2247                 link_speed |= I40E_LINK_SPEED_25GB;
2248         if (link_speeds & ETH_LINK_SPEED_20G)
2249                 link_speed |= I40E_LINK_SPEED_20GB;
2250         if (link_speeds & ETH_LINK_SPEED_10G)
2251                 link_speed |= I40E_LINK_SPEED_10GB;
2252         if (link_speeds & ETH_LINK_SPEED_1G)
2253                 link_speed |= I40E_LINK_SPEED_1GB;
2254         if (link_speeds & ETH_LINK_SPEED_100M)
2255                 link_speed |= I40E_LINK_SPEED_100MB;
2256
2257         return link_speed;
2258 }
2259
2260 static int
2261 i40e_phy_conf_link(struct i40e_hw *hw,
2262                    uint8_t abilities,
2263                    uint8_t force_speed,
2264                    bool is_up)
2265 {
2266         enum i40e_status_code status;
2267         struct i40e_aq_get_phy_abilities_resp phy_ab;
2268         struct i40e_aq_set_phy_config phy_conf;
2269         enum i40e_aq_phy_type cnt;
2270         uint8_t avail_speed;
2271         uint32_t phy_type_mask = 0;
2272
2273         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2274                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2275                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2276                         I40E_AQ_PHY_FLAG_LOW_POWER;
2277         int ret = -ENOTSUP;
2278
2279         /* To get phy capabilities of available speeds. */
2280         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2281                                               NULL);
2282         if (status) {
2283                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2284                                 status);
2285                 return ret;
2286         }
2287         avail_speed = phy_ab.link_speed;
2288
2289         /* To get the current phy config. */
2290         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2291                                               NULL);
2292         if (status) {
2293                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2294                                 status);
2295                 return ret;
2296         }
2297
2298         /* If link needs to go up and it is in autoneg mode the speed is OK,
2299          * no need to set up again.
2300          */
2301         if (is_up && phy_ab.phy_type != 0 &&
2302                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2303                      phy_ab.link_speed != 0)
2304                 return I40E_SUCCESS;
2305
2306         memset(&phy_conf, 0, sizeof(phy_conf));
2307
2308         /* bits 0-2 use the values from get_phy_abilities_resp */
2309         abilities &= ~mask;
2310         abilities |= phy_ab.abilities & mask;
2311
2312         phy_conf.abilities = abilities;
2313
2314         /* If link needs to go up, but the force speed is not supported,
2315          * Warn users and config the default available speeds.
2316          */
2317         if (is_up && !(force_speed & avail_speed)) {
2318                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2319                 phy_conf.link_speed = avail_speed;
2320         } else {
2321                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2322         }
2323
2324         /* PHY type mask needs to include each type except PHY type extension */
2325         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2326                 phy_type_mask |= 1 << cnt;
2327
2328         /* use get_phy_abilities_resp value for the rest */
2329         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2330         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2331                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2332                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2333         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2334         phy_conf.eee_capability = phy_ab.eee_capability;
2335         phy_conf.eeer = phy_ab.eeer_val;
2336         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2337
2338         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2339                     phy_ab.abilities, phy_ab.link_speed);
2340         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2341                     phy_conf.abilities, phy_conf.link_speed);
2342
2343         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2344         if (status)
2345                 return ret;
2346
2347         return I40E_SUCCESS;
2348 }
2349
2350 static int
2351 i40e_apply_link_speed(struct rte_eth_dev *dev)
2352 {
2353         uint8_t speed;
2354         uint8_t abilities = 0;
2355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356         struct rte_eth_conf *conf = &dev->data->dev_conf;
2357
2358         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2359                      I40E_AQ_PHY_LINK_ENABLED;
2360
2361         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2362                 conf->link_speeds = ETH_LINK_SPEED_40G |
2363                                     ETH_LINK_SPEED_25G |
2364                                     ETH_LINK_SPEED_20G |
2365                                     ETH_LINK_SPEED_10G |
2366                                     ETH_LINK_SPEED_1G |
2367                                     ETH_LINK_SPEED_100M;
2368
2369                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2370         } else {
2371                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2372         }
2373         speed = i40e_parse_link_speeds(conf->link_speeds);
2374
2375         return i40e_phy_conf_link(hw, abilities, speed, true);
2376 }
2377
2378 static int
2379 i40e_dev_start(struct rte_eth_dev *dev)
2380 {
2381         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383         struct i40e_vsi *main_vsi = pf->main_vsi;
2384         int ret, i;
2385         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2386         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2387         uint32_t intr_vector = 0;
2388         struct i40e_vsi *vsi;
2389         uint16_t nb_rxq, nb_txq;
2390
2391         hw->adapter_stopped = 0;
2392
2393         rte_intr_disable(intr_handle);
2394
2395         if ((rte_intr_cap_multiple(intr_handle) ||
2396              !RTE_ETH_DEV_SRIOV(dev).active) &&
2397             dev->data->dev_conf.intr_conf.rxq != 0) {
2398                 intr_vector = dev->data->nb_rx_queues;
2399                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2400                 if (ret)
2401                         return ret;
2402         }
2403
2404         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2405                 intr_handle->intr_vec =
2406                         rte_zmalloc("intr_vec",
2407                                     dev->data->nb_rx_queues * sizeof(int),
2408                                     0);
2409                 if (!intr_handle->intr_vec) {
2410                         PMD_INIT_LOG(ERR,
2411                                 "Failed to allocate %d rx_queues intr_vec",
2412                                 dev->data->nb_rx_queues);
2413                         return -ENOMEM;
2414                 }
2415         }
2416
2417         /* Initialize VSI */
2418         ret = i40e_dev_rxtx_init(pf);
2419         if (ret != I40E_SUCCESS) {
2420                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2421                 return ret;
2422         }
2423
2424         /* Map queues with MSIX interrupt */
2425         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2426                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2427         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2428         if (ret < 0)
2429                 return ret;
2430         i40e_vsi_enable_queues_intr(main_vsi);
2431
2432         /* Map VMDQ VSI queues with MSIX interrupt */
2433         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2434                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2435                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2436                                                 I40E_ITR_INDEX_DEFAULT);
2437                 if (ret < 0)
2438                         return ret;
2439                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2440         }
2441
2442         /* Enable all queues which have been configured */
2443         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2444                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2445                 if (ret)
2446                         goto rx_err;
2447         }
2448
2449         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2450                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2451                 if (ret)
2452                         goto tx_err;
2453         }
2454
2455         /* Enable receiving broadcast packets */
2456         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2457         if (ret != I40E_SUCCESS)
2458                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2459
2460         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2461                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2462                                                 true, NULL);
2463                 if (ret != I40E_SUCCESS)
2464                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2465         }
2466
2467         /* Enable the VLAN promiscuous mode. */
2468         if (pf->vfs) {
2469                 for (i = 0; i < pf->vf_num; i++) {
2470                         vsi = pf->vfs[i].vsi;
2471                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2472                                                      true, NULL);
2473                 }
2474         }
2475
2476         /* Enable mac loopback mode */
2477         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2478             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2479                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2480                 if (ret != I40E_SUCCESS) {
2481                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2482                         goto tx_err;
2483                 }
2484         }
2485
2486         /* Apply link configure */
2487         ret = i40e_apply_link_speed(dev);
2488         if (I40E_SUCCESS != ret) {
2489                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2490                 goto tx_err;
2491         }
2492
2493         if (!rte_intr_allow_others(intr_handle)) {
2494                 rte_intr_callback_unregister(intr_handle,
2495                                              i40e_dev_interrupt_handler,
2496                                              (void *)dev);
2497                 /* configure and enable device interrupt */
2498                 i40e_pf_config_irq0(hw, FALSE);
2499                 i40e_pf_enable_irq0(hw);
2500
2501                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2502                         PMD_INIT_LOG(INFO,
2503                                 "lsc won't enable because of no intr multiplex");
2504         } else {
2505                 ret = i40e_aq_set_phy_int_mask(hw,
2506                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2507                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2508                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2509                 if (ret != I40E_SUCCESS)
2510                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2511
2512                 /* Call get_link_info aq commond to enable/disable LSE */
2513                 i40e_dev_link_update(dev, 0);
2514         }
2515
2516         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2517                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2518                                   i40e_dev_alarm_handler, dev);
2519         } else {
2520                 /* enable uio intr after callback register */
2521                 rte_intr_enable(intr_handle);
2522         }
2523
2524         i40e_filter_restore(pf);
2525
2526         if (pf->tm_conf.root && !pf->tm_conf.committed)
2527                 PMD_DRV_LOG(WARNING,
2528                             "please call hierarchy_commit() "
2529                             "before starting the port");
2530
2531         return I40E_SUCCESS;
2532
2533 tx_err:
2534         for (i = 0; i < nb_txq; i++)
2535                 i40e_dev_tx_queue_stop(dev, i);
2536 rx_err:
2537         for (i = 0; i < nb_rxq; i++)
2538                 i40e_dev_rx_queue_stop(dev, i);
2539
2540         return ret;
2541 }
2542
2543 static int
2544 i40e_dev_stop(struct rte_eth_dev *dev)
2545 {
2546         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2547         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548         struct i40e_vsi *main_vsi = pf->main_vsi;
2549         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2551         int i;
2552
2553         if (hw->adapter_stopped == 1)
2554                 return 0;
2555
2556         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2557                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2558                 rte_intr_enable(intr_handle);
2559         }
2560
2561         /* Disable all queues */
2562         for (i = 0; i < dev->data->nb_tx_queues; i++)
2563                 i40e_dev_tx_queue_stop(dev, i);
2564
2565         for (i = 0; i < dev->data->nb_rx_queues; i++)
2566                 i40e_dev_rx_queue_stop(dev, i);
2567
2568         /* un-map queues with interrupt registers */
2569         i40e_vsi_disable_queues_intr(main_vsi);
2570         i40e_vsi_queues_unbind_intr(main_vsi);
2571
2572         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2573                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2574                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2575         }
2576
2577         /* Clear all queues and release memory */
2578         i40e_dev_clear_queues(dev);
2579
2580         /* Set link down */
2581         i40e_dev_set_link_down(dev);
2582
2583         if (!rte_intr_allow_others(intr_handle))
2584                 /* resume to the default handler */
2585                 rte_intr_callback_register(intr_handle,
2586                                            i40e_dev_interrupt_handler,
2587                                            (void *)dev);
2588
2589         /* Clean datapath event and queue/vec mapping */
2590         rte_intr_efd_disable(intr_handle);
2591         if (intr_handle->intr_vec) {
2592                 rte_free(intr_handle->intr_vec);
2593                 intr_handle->intr_vec = NULL;
2594         }
2595
2596         /* reset hierarchy commit */
2597         pf->tm_conf.committed = false;
2598
2599         hw->adapter_stopped = 1;
2600         dev->data->dev_started = 0;
2601
2602         pf->adapter->rss_reta_updated = 0;
2603
2604         return 0;
2605 }
2606
2607 static int
2608 i40e_dev_close(struct rte_eth_dev *dev)
2609 {
2610         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2613         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2614         struct i40e_mirror_rule *p_mirror;
2615         struct i40e_filter_control_settings settings;
2616         struct rte_flow *p_flow;
2617         uint32_t reg;
2618         int i;
2619         int ret;
2620         uint8_t aq_fail = 0;
2621         int retries = 0;
2622
2623         PMD_INIT_FUNC_TRACE();
2624         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2625                 return 0;
2626
2627         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2628         if (ret)
2629                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2630
2631
2632         ret = i40e_dev_stop(dev);
2633
2634         /* Remove all mirror rules */
2635         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2636                 ret = i40e_aq_del_mirror_rule(hw,
2637                                               pf->main_vsi->veb->seid,
2638                                               p_mirror->rule_type,
2639                                               p_mirror->entries,
2640                                               p_mirror->num_entries,
2641                                               p_mirror->id);
2642                 if (ret < 0)
2643                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2644                                     "status = %d, aq_err = %d.", ret,
2645                                     hw->aq.asq_last_status);
2646
2647                 /* remove mirror software resource anyway */
2648                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2649                 rte_free(p_mirror);
2650                 pf->nb_mirror_rule--;
2651         }
2652
2653         i40e_dev_free_queues(dev);
2654
2655         /* Disable interrupt */
2656         i40e_pf_disable_irq0(hw);
2657         rte_intr_disable(intr_handle);
2658
2659         /*
2660          * Only legacy filter API needs the following fdir config. So when the
2661          * legacy filter API is deprecated, the following code should also be
2662          * removed.
2663          */
2664         i40e_fdir_teardown(pf);
2665
2666         /* shutdown and destroy the HMC */
2667         i40e_shutdown_lan_hmc(hw);
2668
2669         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2670                 i40e_vsi_release(pf->vmdq[i].vsi);
2671                 pf->vmdq[i].vsi = NULL;
2672         }
2673         rte_free(pf->vmdq);
2674         pf->vmdq = NULL;
2675
2676         /* release all the existing VSIs and VEBs */
2677         i40e_vsi_release(pf->main_vsi);
2678
2679         /* shutdown the adminq */
2680         i40e_aq_queue_shutdown(hw, true);
2681         i40e_shutdown_adminq(hw);
2682
2683         i40e_res_pool_destroy(&pf->qp_pool);
2684         i40e_res_pool_destroy(&pf->msix_pool);
2685
2686         /* Disable flexible payload in global configuration */
2687         if (!pf->support_multi_driver)
2688                 i40e_flex_payload_reg_set_default(hw);
2689
2690         /* force a PF reset to clean anything leftover */
2691         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2692         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2693                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2694         I40E_WRITE_FLUSH(hw);
2695
2696         /* Clear PXE mode */
2697         i40e_clear_pxe_mode(hw);
2698
2699         /* Unconfigure filter control */
2700         memset(&settings, 0, sizeof(settings));
2701         ret = i40e_set_filter_control(hw, &settings);
2702         if (ret)
2703                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2704                                         ret);
2705
2706         /* Disable flow control */
2707         hw->fc.requested_mode = I40E_FC_NONE;
2708         i40e_set_fc(hw, &aq_fail, TRUE);
2709
2710         /* uninitialize pf host driver */
2711         i40e_pf_host_uninit(dev);
2712
2713         do {
2714                 ret = rte_intr_callback_unregister(intr_handle,
2715                                 i40e_dev_interrupt_handler, dev);
2716                 if (ret >= 0 || ret == -ENOENT) {
2717                         break;
2718                 } else if (ret != -EAGAIN) {
2719                         PMD_INIT_LOG(ERR,
2720                                  "intr callback unregister failed: %d",
2721                                  ret);
2722                 }
2723                 i40e_msec_delay(500);
2724         } while (retries++ < 5);
2725
2726         i40e_rm_ethtype_filter_list(pf);
2727         i40e_rm_tunnel_filter_list(pf);
2728         i40e_rm_fdir_filter_list(pf);
2729
2730         /* Remove all flows */
2731         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2732                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2733                 /* Do not free FDIR flows since they are static allocated */
2734                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2735                         rte_free(p_flow);
2736         }
2737
2738         /* release the fdir static allocated memory */
2739         i40e_fdir_memory_cleanup(pf);
2740
2741         /* Remove all Traffic Manager configuration */
2742         i40e_tm_conf_uninit(dev);
2743
2744         hw->adapter_closed = 1;
2745         return ret;
2746 }
2747
2748 /*
2749  * Reset PF device only to re-initialize resources in PMD layer
2750  */
2751 static int
2752 i40e_dev_reset(struct rte_eth_dev *dev)
2753 {
2754         int ret;
2755
2756         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2757          * its VF to make them align with it. The detailed notification
2758          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2759          * To avoid unexpected behavior in VF, currently reset of PF with
2760          * SR-IOV activation is not supported. It might be supported later.
2761          */
2762         if (dev->data->sriov.active)
2763                 return -ENOTSUP;
2764
2765         ret = eth_i40e_dev_uninit(dev);
2766         if (ret)
2767                 return ret;
2768
2769         ret = eth_i40e_dev_init(dev, NULL);
2770
2771         return ret;
2772 }
2773
2774 static int
2775 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2776 {
2777         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779         struct i40e_vsi *vsi = pf->main_vsi;
2780         int status;
2781
2782         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2783                                                      true, NULL, true);
2784         if (status != I40E_SUCCESS) {
2785                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2786                 return -EAGAIN;
2787         }
2788
2789         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2790                                                         TRUE, NULL);
2791         if (status != I40E_SUCCESS) {
2792                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2793                 /* Rollback unicast promiscuous mode */
2794                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2795                                                     false, NULL, true);
2796                 return -EAGAIN;
2797         }
2798
2799         return 0;
2800 }
2801
2802 static int
2803 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2804 {
2805         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807         struct i40e_vsi *vsi = pf->main_vsi;
2808         int status;
2809
2810         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2811                                                      false, NULL, true);
2812         if (status != I40E_SUCCESS) {
2813                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2814                 return -EAGAIN;
2815         }
2816
2817         /* must remain in all_multicast mode */
2818         if (dev->data->all_multicast == 1)
2819                 return 0;
2820
2821         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2822                                                         false, NULL);
2823         if (status != I40E_SUCCESS) {
2824                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2825                 /* Rollback unicast promiscuous mode */
2826                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2827                                                     true, NULL, true);
2828                 return -EAGAIN;
2829         }
2830
2831         return 0;
2832 }
2833
2834 static int
2835 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2836 {
2837         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839         struct i40e_vsi *vsi = pf->main_vsi;
2840         int ret;
2841
2842         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2843         if (ret != I40E_SUCCESS) {
2844                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2845                 return -EAGAIN;
2846         }
2847
2848         return 0;
2849 }
2850
2851 static int
2852 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2853 {
2854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2856         struct i40e_vsi *vsi = pf->main_vsi;
2857         int ret;
2858
2859         if (dev->data->promiscuous == 1)
2860                 return 0; /* must remain in all_multicast mode */
2861
2862         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2863                                 vsi->seid, FALSE, NULL);
2864         if (ret != I40E_SUCCESS) {
2865                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2866                 return -EAGAIN;
2867         }
2868
2869         return 0;
2870 }
2871
2872 /*
2873  * Set device link up.
2874  */
2875 static int
2876 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2877 {
2878         /* re-apply link speed setting */
2879         return i40e_apply_link_speed(dev);
2880 }
2881
2882 /*
2883  * Set device link down.
2884  */
2885 static int
2886 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2887 {
2888         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2889         uint8_t abilities = 0;
2890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2891
2892         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2893         return i40e_phy_conf_link(hw, abilities, speed, false);
2894 }
2895
2896 static __rte_always_inline void
2897 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2898 {
2899 /* Link status registers and values*/
2900 #define I40E_PRTMAC_LINKSTA             0x001E2420
2901 #define I40E_REG_LINK_UP                0x40000080
2902 #define I40E_PRTMAC_MACC                0x001E24E0
2903 #define I40E_REG_MACC_25GB              0x00020000
2904 #define I40E_REG_SPEED_MASK             0x38000000
2905 #define I40E_REG_SPEED_0                0x00000000
2906 #define I40E_REG_SPEED_1                0x08000000
2907 #define I40E_REG_SPEED_2                0x10000000
2908 #define I40E_REG_SPEED_3                0x18000000
2909 #define I40E_REG_SPEED_4                0x20000000
2910         uint32_t link_speed;
2911         uint32_t reg_val;
2912
2913         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2914         link_speed = reg_val & I40E_REG_SPEED_MASK;
2915         reg_val &= I40E_REG_LINK_UP;
2916         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2917
2918         if (unlikely(link->link_status == 0))
2919                 return;
2920
2921         /* Parse the link status */
2922         switch (link_speed) {
2923         case I40E_REG_SPEED_0:
2924                 link->link_speed = ETH_SPEED_NUM_100M;
2925                 break;
2926         case I40E_REG_SPEED_1:
2927                 link->link_speed = ETH_SPEED_NUM_1G;
2928                 break;
2929         case I40E_REG_SPEED_2:
2930                 if (hw->mac.type == I40E_MAC_X722)
2931                         link->link_speed = ETH_SPEED_NUM_2_5G;
2932                 else
2933                         link->link_speed = ETH_SPEED_NUM_10G;
2934                 break;
2935         case I40E_REG_SPEED_3:
2936                 if (hw->mac.type == I40E_MAC_X722) {
2937                         link->link_speed = ETH_SPEED_NUM_5G;
2938                 } else {
2939                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2940
2941                         if (reg_val & I40E_REG_MACC_25GB)
2942                                 link->link_speed = ETH_SPEED_NUM_25G;
2943                         else
2944                                 link->link_speed = ETH_SPEED_NUM_40G;
2945                 }
2946                 break;
2947         case I40E_REG_SPEED_4:
2948                 if (hw->mac.type == I40E_MAC_X722)
2949                         link->link_speed = ETH_SPEED_NUM_10G;
2950                 else
2951                         link->link_speed = ETH_SPEED_NUM_20G;
2952                 break;
2953         default:
2954                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2955                 break;
2956         }
2957 }
2958
2959 static __rte_always_inline void
2960 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2961         bool enable_lse, int wait_to_complete)
2962 {
2963 #define CHECK_INTERVAL             100  /* 100ms */
2964 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2965         uint32_t rep_cnt = MAX_REPEAT_TIME;
2966         struct i40e_link_status link_status;
2967         int status;
2968
2969         memset(&link_status, 0, sizeof(link_status));
2970
2971         do {
2972                 memset(&link_status, 0, sizeof(link_status));
2973
2974                 /* Get link status information from hardware */
2975                 status = i40e_aq_get_link_info(hw, enable_lse,
2976                                                 &link_status, NULL);
2977                 if (unlikely(status != I40E_SUCCESS)) {
2978                         link->link_speed = ETH_SPEED_NUM_NONE;
2979                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2980                         PMD_DRV_LOG(ERR, "Failed to get link info");
2981                         return;
2982                 }
2983
2984                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2985                 if (!wait_to_complete || link->link_status)
2986                         break;
2987
2988                 rte_delay_ms(CHECK_INTERVAL);
2989         } while (--rep_cnt);
2990
2991         /* Parse the link status */
2992         switch (link_status.link_speed) {
2993         case I40E_LINK_SPEED_100MB:
2994                 link->link_speed = ETH_SPEED_NUM_100M;
2995                 break;
2996         case I40E_LINK_SPEED_1GB:
2997                 link->link_speed = ETH_SPEED_NUM_1G;
2998                 break;
2999         case I40E_LINK_SPEED_10GB:
3000                 link->link_speed = ETH_SPEED_NUM_10G;
3001                 break;
3002         case I40E_LINK_SPEED_20GB:
3003                 link->link_speed = ETH_SPEED_NUM_20G;
3004                 break;
3005         case I40E_LINK_SPEED_25GB:
3006                 link->link_speed = ETH_SPEED_NUM_25G;
3007                 break;
3008         case I40E_LINK_SPEED_40GB:
3009                 link->link_speed = ETH_SPEED_NUM_40G;
3010                 break;
3011         default:
3012                 if (link->link_status)
3013                         link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3014                 else
3015                         link->link_speed = ETH_SPEED_NUM_NONE;
3016                 break;
3017         }
3018 }
3019
3020 int
3021 i40e_dev_link_update(struct rte_eth_dev *dev,
3022                      int wait_to_complete)
3023 {
3024         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025         struct rte_eth_link link;
3026         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3027         int ret;
3028
3029         memset(&link, 0, sizeof(link));
3030
3031         /* i40e uses full duplex only */
3032         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3033         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3034                         ETH_LINK_SPEED_FIXED);
3035
3036         if (!wait_to_complete && !enable_lse)
3037                 update_link_reg(hw, &link);
3038         else
3039                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3040
3041         if (hw->switch_dev)
3042                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3043
3044         ret = rte_eth_linkstatus_set(dev, &link);
3045         i40e_notify_all_vfs_link_status(dev);
3046
3047         return ret;
3048 }
3049
3050 static void
3051 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3052                           uint32_t loreg, bool offset_loaded, uint64_t *offset,
3053                           uint64_t *stat, uint64_t *prev_stat)
3054 {
3055         i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3056         /* enlarge the limitation when statistics counters overflowed */
3057         if (offset_loaded) {
3058                 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3059                         *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3060                 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3061         }
3062         *prev_stat = *stat;
3063 }
3064
3065 /* Get all the statistics of a VSI */
3066 void
3067 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3068 {
3069         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3070         struct i40e_eth_stats *nes = &vsi->eth_stats;
3071         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3072         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3073
3074         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3075                                   vsi->offset_loaded, &oes->rx_bytes,
3076                                   &nes->rx_bytes, &vsi->prev_rx_bytes);
3077         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3078                             vsi->offset_loaded, &oes->rx_unicast,
3079                             &nes->rx_unicast);
3080         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3081                             vsi->offset_loaded, &oes->rx_multicast,
3082                             &nes->rx_multicast);
3083         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3084                             vsi->offset_loaded, &oes->rx_broadcast,
3085                             &nes->rx_broadcast);
3086         /* exclude CRC bytes */
3087         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3088                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3089
3090         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3091                             &oes->rx_discards, &nes->rx_discards);
3092         /* GLV_REPC not supported */
3093         /* GLV_RMPC not supported */
3094         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3095                             &oes->rx_unknown_protocol,
3096                             &nes->rx_unknown_protocol);
3097         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3098                                   vsi->offset_loaded, &oes->tx_bytes,
3099                                   &nes->tx_bytes, &vsi->prev_tx_bytes);
3100         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3101                             vsi->offset_loaded, &oes->tx_unicast,
3102                             &nes->tx_unicast);
3103         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3104                             vsi->offset_loaded, &oes->tx_multicast,
3105                             &nes->tx_multicast);
3106         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3107                             vsi->offset_loaded,  &oes->tx_broadcast,
3108                             &nes->tx_broadcast);
3109         /* GLV_TDPC not supported */
3110         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3111                             &oes->tx_errors, &nes->tx_errors);
3112         vsi->offset_loaded = true;
3113
3114         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3115                     vsi->vsi_id);
3116         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3117         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3118         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3119         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3120         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3121         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3122                     nes->rx_unknown_protocol);
3123         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3124         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3125         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3126         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3127         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3128         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3129         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3130                     vsi->vsi_id);
3131 }
3132
3133 static void
3134 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3135 {
3136         unsigned int i;
3137         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3138         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3139
3140         /* Get rx/tx bytes of internal transfer packets */
3141         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3142                                   I40E_GLV_GORCL(hw->port),
3143                                   pf->offset_loaded,
3144                                   &pf->internal_stats_offset.rx_bytes,
3145                                   &pf->internal_stats.rx_bytes,
3146                                   &pf->internal_prev_rx_bytes);
3147         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3148                                   I40E_GLV_GOTCL(hw->port),
3149                                   pf->offset_loaded,
3150                                   &pf->internal_stats_offset.tx_bytes,
3151                                   &pf->internal_stats.tx_bytes,
3152                                   &pf->internal_prev_tx_bytes);
3153         /* Get total internal rx packet count */
3154         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3155                             I40E_GLV_UPRCL(hw->port),
3156                             pf->offset_loaded,
3157                             &pf->internal_stats_offset.rx_unicast,
3158                             &pf->internal_stats.rx_unicast);
3159         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3160                             I40E_GLV_MPRCL(hw->port),
3161                             pf->offset_loaded,
3162                             &pf->internal_stats_offset.rx_multicast,
3163                             &pf->internal_stats.rx_multicast);
3164         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3165                             I40E_GLV_BPRCL(hw->port),
3166                             pf->offset_loaded,
3167                             &pf->internal_stats_offset.rx_broadcast,
3168                             &pf->internal_stats.rx_broadcast);
3169         /* Get total internal tx packet count */
3170         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3171                             I40E_GLV_UPTCL(hw->port),
3172                             pf->offset_loaded,
3173                             &pf->internal_stats_offset.tx_unicast,
3174                             &pf->internal_stats.tx_unicast);
3175         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3176                             I40E_GLV_MPTCL(hw->port),
3177                             pf->offset_loaded,
3178                             &pf->internal_stats_offset.tx_multicast,
3179                             &pf->internal_stats.tx_multicast);
3180         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3181                             I40E_GLV_BPTCL(hw->port),
3182                             pf->offset_loaded,
3183                             &pf->internal_stats_offset.tx_broadcast,
3184                             &pf->internal_stats.tx_broadcast);
3185
3186         /* exclude CRC size */
3187         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3188                 pf->internal_stats.rx_multicast +
3189                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3190
3191         /* Get statistics of struct i40e_eth_stats */
3192         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3193                                   I40E_GLPRT_GORCL(hw->port),
3194                                   pf->offset_loaded, &os->eth.rx_bytes,
3195                                   &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3196         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3197                             I40E_GLPRT_UPRCL(hw->port),
3198                             pf->offset_loaded, &os->eth.rx_unicast,
3199                             &ns->eth.rx_unicast);
3200         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3201                             I40E_GLPRT_MPRCL(hw->port),
3202                             pf->offset_loaded, &os->eth.rx_multicast,
3203                             &ns->eth.rx_multicast);
3204         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3205                             I40E_GLPRT_BPRCL(hw->port),
3206                             pf->offset_loaded, &os->eth.rx_broadcast,
3207                             &ns->eth.rx_broadcast);
3208         /* Workaround: CRC size should not be included in byte statistics,
3209          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3210          * packet.
3211          */
3212         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3213                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3214
3215         /* exclude internal rx bytes
3216          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3217          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3218          * value.
3219          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3220          */
3221         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3222                 ns->eth.rx_bytes = 0;
3223         else
3224                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3225
3226         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3227                 ns->eth.rx_unicast = 0;
3228         else
3229                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3230
3231         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3232                 ns->eth.rx_multicast = 0;
3233         else
3234                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3235
3236         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3237                 ns->eth.rx_broadcast = 0;
3238         else
3239                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3240
3241         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3242                             pf->offset_loaded, &os->eth.rx_discards,
3243                             &ns->eth.rx_discards);
3244         /* GLPRT_REPC not supported */
3245         /* GLPRT_RMPC not supported */
3246         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3247                             pf->offset_loaded,
3248                             &os->eth.rx_unknown_protocol,
3249                             &ns->eth.rx_unknown_protocol);
3250         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3251                                   I40E_GLPRT_GOTCL(hw->port),
3252                                   pf->offset_loaded, &os->eth.tx_bytes,
3253                                   &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3254         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3255                             I40E_GLPRT_UPTCL(hw->port),
3256                             pf->offset_loaded, &os->eth.tx_unicast,
3257                             &ns->eth.tx_unicast);
3258         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3259                             I40E_GLPRT_MPTCL(hw->port),
3260                             pf->offset_loaded, &os->eth.tx_multicast,
3261                             &ns->eth.tx_multicast);
3262         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3263                             I40E_GLPRT_BPTCL(hw->port),
3264                             pf->offset_loaded, &os->eth.tx_broadcast,
3265                             &ns->eth.tx_broadcast);
3266         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3267                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3268
3269         /* exclude internal tx bytes
3270          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3271          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3272          * value.
3273          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3274          */
3275         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3276                 ns->eth.tx_bytes = 0;
3277         else
3278                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3279
3280         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3281                 ns->eth.tx_unicast = 0;
3282         else
3283                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3284
3285         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3286                 ns->eth.tx_multicast = 0;
3287         else
3288                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3289
3290         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3291                 ns->eth.tx_broadcast = 0;
3292         else
3293                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3294
3295         /* GLPRT_TEPC not supported */
3296
3297         /* additional port specific stats */
3298         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3299                             pf->offset_loaded, &os->tx_dropped_link_down,
3300                             &ns->tx_dropped_link_down);
3301         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3302                             pf->offset_loaded, &os->crc_errors,
3303                             &ns->crc_errors);
3304         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3305                             pf->offset_loaded, &os->illegal_bytes,
3306                             &ns->illegal_bytes);
3307         /* GLPRT_ERRBC not supported */
3308         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3309                             pf->offset_loaded, &os->mac_local_faults,
3310                             &ns->mac_local_faults);
3311         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3312                             pf->offset_loaded, &os->mac_remote_faults,
3313                             &ns->mac_remote_faults);
3314         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3315                             pf->offset_loaded, &os->rx_length_errors,
3316                             &ns->rx_length_errors);
3317         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3318                             pf->offset_loaded, &os->link_xon_rx,
3319                             &ns->link_xon_rx);
3320         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3321                             pf->offset_loaded, &os->link_xoff_rx,
3322                             &ns->link_xoff_rx);
3323         for (i = 0; i < 8; i++) {
3324                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3325                                     pf->offset_loaded,
3326                                     &os->priority_xon_rx[i],
3327                                     &ns->priority_xon_rx[i]);
3328                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3329                                     pf->offset_loaded,
3330                                     &os->priority_xoff_rx[i],
3331                                     &ns->priority_xoff_rx[i]);
3332         }
3333         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3334                             pf->offset_loaded, &os->link_xon_tx,
3335                             &ns->link_xon_tx);
3336         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3337                             pf->offset_loaded, &os->link_xoff_tx,
3338                             &ns->link_xoff_tx);
3339         for (i = 0; i < 8; i++) {
3340                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3341                                     pf->offset_loaded,
3342                                     &os->priority_xon_tx[i],
3343                                     &ns->priority_xon_tx[i]);
3344                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3345                                     pf->offset_loaded,
3346                                     &os->priority_xoff_tx[i],
3347                                     &ns->priority_xoff_tx[i]);
3348                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3349                                     pf->offset_loaded,
3350                                     &os->priority_xon_2_xoff[i],
3351                                     &ns->priority_xon_2_xoff[i]);
3352         }
3353         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3354                             I40E_GLPRT_PRC64L(hw->port),
3355                             pf->offset_loaded, &os->rx_size_64,
3356                             &ns->rx_size_64);
3357         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3358                             I40E_GLPRT_PRC127L(hw->port),
3359                             pf->offset_loaded, &os->rx_size_127,
3360                             &ns->rx_size_127);
3361         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3362                             I40E_GLPRT_PRC255L(hw->port),
3363                             pf->offset_loaded, &os->rx_size_255,
3364                             &ns->rx_size_255);
3365         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3366                             I40E_GLPRT_PRC511L(hw->port),
3367                             pf->offset_loaded, &os->rx_size_511,
3368                             &ns->rx_size_511);
3369         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3370                             I40E_GLPRT_PRC1023L(hw->port),
3371                             pf->offset_loaded, &os->rx_size_1023,
3372                             &ns->rx_size_1023);
3373         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3374                             I40E_GLPRT_PRC1522L(hw->port),
3375                             pf->offset_loaded, &os->rx_size_1522,
3376                             &ns->rx_size_1522);
3377         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3378                             I40E_GLPRT_PRC9522L(hw->port),
3379                             pf->offset_loaded, &os->rx_size_big,
3380                             &ns->rx_size_big);
3381         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3382                             pf->offset_loaded, &os->rx_undersize,
3383                             &ns->rx_undersize);
3384         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3385                             pf->offset_loaded, &os->rx_fragments,
3386                             &ns->rx_fragments);
3387         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3388                             pf->offset_loaded, &os->rx_oversize,
3389                             &ns->rx_oversize);
3390         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3391                             pf->offset_loaded, &os->rx_jabber,
3392                             &ns->rx_jabber);
3393         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3394                             I40E_GLPRT_PTC64L(hw->port),
3395                             pf->offset_loaded, &os->tx_size_64,
3396                             &ns->tx_size_64);
3397         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3398                             I40E_GLPRT_PTC127L(hw->port),
3399                             pf->offset_loaded, &os->tx_size_127,
3400                             &ns->tx_size_127);
3401         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3402                             I40E_GLPRT_PTC255L(hw->port),
3403                             pf->offset_loaded, &os->tx_size_255,
3404                             &ns->tx_size_255);
3405         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3406                             I40E_GLPRT_PTC511L(hw->port),
3407                             pf->offset_loaded, &os->tx_size_511,
3408                             &ns->tx_size_511);
3409         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3410                             I40E_GLPRT_PTC1023L(hw->port),
3411                             pf->offset_loaded, &os->tx_size_1023,
3412                             &ns->tx_size_1023);
3413         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3414                             I40E_GLPRT_PTC1522L(hw->port),
3415                             pf->offset_loaded, &os->tx_size_1522,
3416                             &ns->tx_size_1522);
3417         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3418                             I40E_GLPRT_PTC9522L(hw->port),
3419                             pf->offset_loaded, &os->tx_size_big,
3420                             &ns->tx_size_big);
3421         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3422                            pf->offset_loaded,
3423                            &os->fd_sb_match, &ns->fd_sb_match);
3424         /* GLPRT_MSPDC not supported */
3425         /* GLPRT_XEC not supported */
3426
3427         pf->offset_loaded = true;
3428
3429         if (pf->main_vsi)
3430                 i40e_update_vsi_stats(pf->main_vsi);
3431 }
3432
3433 /* Get all statistics of a port */
3434 static int
3435 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3436 {
3437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3439         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3440         struct i40e_vsi *vsi;
3441         unsigned i;
3442
3443         /* call read registers - updates values, now write them to struct */
3444         i40e_read_stats_registers(pf, hw);
3445
3446         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3447                         pf->main_vsi->eth_stats.rx_multicast +
3448                         pf->main_vsi->eth_stats.rx_broadcast -
3449                         pf->main_vsi->eth_stats.rx_discards;
3450         stats->opackets = ns->eth.tx_unicast +
3451                         ns->eth.tx_multicast +
3452                         ns->eth.tx_broadcast;
3453         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3454         stats->obytes   = ns->eth.tx_bytes;
3455         stats->oerrors  = ns->eth.tx_errors +
3456                         pf->main_vsi->eth_stats.tx_errors;
3457
3458         /* Rx Errors */
3459         stats->imissed  = ns->eth.rx_discards +
3460                         pf->main_vsi->eth_stats.rx_discards;
3461         stats->ierrors  = ns->crc_errors +
3462                         ns->rx_length_errors + ns->rx_undersize +
3463                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3464
3465         if (pf->vfs) {
3466                 for (i = 0; i < pf->vf_num; i++) {
3467                         vsi = pf->vfs[i].vsi;
3468                         i40e_update_vsi_stats(vsi);
3469
3470                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3471                                         vsi->eth_stats.rx_multicast +
3472                                         vsi->eth_stats.rx_broadcast -
3473                                         vsi->eth_stats.rx_discards);
3474                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3475                         stats->oerrors  += vsi->eth_stats.tx_errors;
3476                         stats->imissed  += vsi->eth_stats.rx_discards;
3477                 }
3478         }
3479
3480         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3481         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3482         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3483         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3484         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3485         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3486         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3487                     ns->eth.rx_unknown_protocol);
3488         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3489         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3490         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3491         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3492         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3493         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3494
3495         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3496                     ns->tx_dropped_link_down);
3497         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3498         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3499                     ns->illegal_bytes);
3500         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3501         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3502                     ns->mac_local_faults);
3503         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3504                     ns->mac_remote_faults);
3505         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3506                     ns->rx_length_errors);
3507         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3508         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3509         for (i = 0; i < 8; i++) {
3510                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3511                                 i, ns->priority_xon_rx[i]);
3512                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3513                                 i, ns->priority_xoff_rx[i]);
3514         }
3515         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3516         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3517         for (i = 0; i < 8; i++) {
3518                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3519                                 i, ns->priority_xon_tx[i]);
3520                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3521                                 i, ns->priority_xoff_tx[i]);
3522                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3523                                 i, ns->priority_xon_2_xoff[i]);
3524         }
3525         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3526         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3527         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3528         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3529         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3530         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3531         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3532         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3533         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3534         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3535         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3536         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3537         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3538         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3539         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3540         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3541         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3542         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3543         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3544                         ns->mac_short_packet_dropped);
3545         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3546                     ns->checksum_error);
3547         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3548         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3549         return 0;
3550 }
3551
3552 /* Reset the statistics */
3553 static int
3554 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3555 {
3556         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3557         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3558
3559         /* Mark PF and VSI stats to update the offset, aka "reset" */
3560         pf->offset_loaded = false;
3561         if (pf->main_vsi)
3562                 pf->main_vsi->offset_loaded = false;
3563
3564         /* read the stats, reading current register values into offset */
3565         i40e_read_stats_registers(pf, hw);
3566
3567         return 0;
3568 }
3569
3570 static uint32_t
3571 i40e_xstats_calc_num(void)
3572 {
3573         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3574                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3575                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3576 }
3577
3578 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3579                                      struct rte_eth_xstat_name *xstats_names,
3580                                      __rte_unused unsigned limit)
3581 {
3582         unsigned count = 0;
3583         unsigned i, prio;
3584
3585         if (xstats_names == NULL)
3586                 return i40e_xstats_calc_num();
3587
3588         /* Note: limit checked in rte_eth_xstats_names() */
3589
3590         /* Get stats from i40e_eth_stats struct */
3591         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3592                 strlcpy(xstats_names[count].name,
3593                         rte_i40e_stats_strings[i].name,
3594                         sizeof(xstats_names[count].name));
3595                 count++;
3596         }
3597
3598         /* Get individiual stats from i40e_hw_port struct */
3599         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3600                 strlcpy(xstats_names[count].name,
3601                         rte_i40e_hw_port_strings[i].name,
3602                         sizeof(xstats_names[count].name));
3603                 count++;
3604         }
3605
3606         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3607                 for (prio = 0; prio < 8; prio++) {
3608                         snprintf(xstats_names[count].name,
3609                                  sizeof(xstats_names[count].name),
3610                                  "rx_priority%u_%s", prio,
3611                                  rte_i40e_rxq_prio_strings[i].name);
3612                         count++;
3613                 }
3614         }
3615
3616         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3617                 for (prio = 0; prio < 8; prio++) {
3618                         snprintf(xstats_names[count].name,
3619                                  sizeof(xstats_names[count].name),
3620                                  "tx_priority%u_%s", prio,
3621                                  rte_i40e_txq_prio_strings[i].name);
3622                         count++;
3623                 }
3624         }
3625         return count;
3626 }
3627
3628 static int
3629 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3630                     unsigned n)
3631 {
3632         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3633         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3634         unsigned i, count, prio;
3635         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3636
3637         count = i40e_xstats_calc_num();
3638         if (n < count)
3639                 return count;
3640
3641         i40e_read_stats_registers(pf, hw);
3642
3643         if (xstats == NULL)
3644                 return 0;
3645
3646         count = 0;
3647
3648         /* Get stats from i40e_eth_stats struct */
3649         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3650                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3651                         rte_i40e_stats_strings[i].offset);
3652                 xstats[count].id = count;
3653                 count++;
3654         }
3655
3656         /* Get individiual stats from i40e_hw_port struct */
3657         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3658                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3659                         rte_i40e_hw_port_strings[i].offset);
3660                 xstats[count].id = count;
3661                 count++;
3662         }
3663
3664         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3665                 for (prio = 0; prio < 8; prio++) {
3666                         xstats[count].value =
3667                                 *(uint64_t *)(((char *)hw_stats) +
3668                                 rte_i40e_rxq_prio_strings[i].offset +
3669                                 (sizeof(uint64_t) * prio));
3670                         xstats[count].id = count;
3671                         count++;
3672                 }
3673         }
3674
3675         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3676                 for (prio = 0; prio < 8; prio++) {
3677                         xstats[count].value =
3678                                 *(uint64_t *)(((char *)hw_stats) +
3679                                 rte_i40e_txq_prio_strings[i].offset +
3680                                 (sizeof(uint64_t) * prio));
3681                         xstats[count].id = count;
3682                         count++;
3683                 }
3684         }
3685
3686         return count;
3687 }
3688
3689 static int
3690 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3691 {
3692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3693         u32 full_ver;
3694         u8 ver, patch;
3695         u16 build;
3696         int ret;
3697
3698         full_ver = hw->nvm.oem_ver;
3699         ver = (u8)(full_ver >> 24);
3700         build = (u16)((full_ver >> 8) & 0xffff);
3701         patch = (u8)(full_ver & 0xff);
3702
3703         ret = snprintf(fw_version, fw_size,
3704                  "%d.%d%d 0x%08x %d.%d.%d",
3705                  ((hw->nvm.version >> 12) & 0xf),
3706                  ((hw->nvm.version >> 4) & 0xff),
3707                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3708                  ver, build, patch);
3709
3710         ret += 1; /* add the size of '\0' */
3711         if (fw_size < (u32)ret)
3712                 return ret;
3713         else
3714                 return 0;
3715 }
3716
3717 /*
3718  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3719  * the Rx data path does not hang if the FW LLDP is stopped.
3720  * return true if lldp need to stop
3721  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3722  */
3723 static bool
3724 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3725 {
3726         double nvm_ver;
3727         char ver_str[64] = {0};
3728         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729
3730         i40e_fw_version_get(dev, ver_str, 64);
3731         nvm_ver = atof(ver_str);
3732         if ((hw->mac.type == I40E_MAC_X722 ||
3733              hw->mac.type == I40E_MAC_X722_VF) &&
3734              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3735                 return true;
3736         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3737                 return true;
3738
3739         return false;
3740 }
3741
3742 static int
3743 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3744 {
3745         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3746         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3747         struct i40e_vsi *vsi = pf->main_vsi;
3748         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3749
3750         dev_info->max_rx_queues = vsi->nb_qps;
3751         dev_info->max_tx_queues = vsi->nb_qps;
3752         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3753         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3754         dev_info->max_mac_addrs = vsi->max_macaddrs;
3755         dev_info->max_vfs = pci_dev->max_vfs;
3756         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3757         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3758         dev_info->rx_queue_offload_capa = 0;
3759         dev_info->rx_offload_capa =
3760                 DEV_RX_OFFLOAD_VLAN_STRIP |
3761                 DEV_RX_OFFLOAD_QINQ_STRIP |
3762                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3763                 DEV_RX_OFFLOAD_UDP_CKSUM |
3764                 DEV_RX_OFFLOAD_TCP_CKSUM |
3765                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3766                 DEV_RX_OFFLOAD_KEEP_CRC |
3767                 DEV_RX_OFFLOAD_SCATTER |
3768                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3769                 DEV_RX_OFFLOAD_VLAN_FILTER |
3770                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3771                 DEV_RX_OFFLOAD_RSS_HASH;
3772
3773         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3774         dev_info->tx_offload_capa =
3775                 DEV_TX_OFFLOAD_VLAN_INSERT |
3776                 DEV_TX_OFFLOAD_QINQ_INSERT |
3777                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3778                 DEV_TX_OFFLOAD_UDP_CKSUM |
3779                 DEV_TX_OFFLOAD_TCP_CKSUM |
3780                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3781                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3782                 DEV_TX_OFFLOAD_TCP_TSO |
3783                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3784                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3785                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3786                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3787                 DEV_TX_OFFLOAD_MULTI_SEGS |
3788                 dev_info->tx_queue_offload_capa;
3789         dev_info->dev_capa =
3790                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3791                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3792
3793         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3794                                                 sizeof(uint32_t);
3795         dev_info->reta_size = pf->hash_lut_size;
3796         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3797
3798         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3799                 .rx_thresh = {
3800                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3801                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3802                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3803                 },
3804                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3805                 .rx_drop_en = 0,
3806                 .offloads = 0,
3807         };
3808
3809         dev_info->default_txconf = (struct rte_eth_txconf) {
3810                 .tx_thresh = {
3811                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3812                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3813                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3814                 },
3815                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3816                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3817                 .offloads = 0,
3818         };
3819
3820         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3821                 .nb_max = I40E_MAX_RING_DESC,
3822                 .nb_min = I40E_MIN_RING_DESC,
3823                 .nb_align = I40E_ALIGN_RING_DESC,
3824         };
3825
3826         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3827                 .nb_max = I40E_MAX_RING_DESC,
3828                 .nb_min = I40E_MIN_RING_DESC,
3829                 .nb_align = I40E_ALIGN_RING_DESC,
3830                 .nb_seg_max = I40E_TX_MAX_SEG,
3831                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3832         };
3833
3834         if (pf->flags & I40E_FLAG_VMDQ) {
3835                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3836                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3837                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3838                                                 pf->max_nb_vmdq_vsi;
3839                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3840                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3841                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3842         }
3843
3844         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3845                 /* For XL710 */
3846                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3847                 dev_info->default_rxportconf.nb_queues = 2;
3848                 dev_info->default_txportconf.nb_queues = 2;
3849                 if (dev->data->nb_rx_queues == 1)
3850                         dev_info->default_rxportconf.ring_size = 2048;
3851                 else
3852                         dev_info->default_rxportconf.ring_size = 1024;
3853                 if (dev->data->nb_tx_queues == 1)
3854                         dev_info->default_txportconf.ring_size = 1024;
3855                 else
3856                         dev_info->default_txportconf.ring_size = 512;
3857
3858         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3859                 /* For XXV710 */
3860                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3861                 dev_info->default_rxportconf.nb_queues = 1;
3862                 dev_info->default_txportconf.nb_queues = 1;
3863                 dev_info->default_rxportconf.ring_size = 256;
3864                 dev_info->default_txportconf.ring_size = 256;
3865         } else {
3866                 /* For X710 */
3867                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3868                 dev_info->default_rxportconf.nb_queues = 1;
3869                 dev_info->default_txportconf.nb_queues = 1;
3870                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3871                         dev_info->default_rxportconf.ring_size = 512;
3872                         dev_info->default_txportconf.ring_size = 256;
3873                 } else {
3874                         dev_info->default_rxportconf.ring_size = 256;
3875                         dev_info->default_txportconf.ring_size = 256;
3876                 }
3877         }
3878         dev_info->default_rxportconf.burst_size = 32;
3879         dev_info->default_txportconf.burst_size = 32;
3880
3881         return 0;
3882 }
3883
3884 static int
3885 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3886 {
3887         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3888         struct i40e_vsi *vsi = pf->main_vsi;
3889         PMD_INIT_FUNC_TRACE();
3890
3891         if (on)
3892                 return i40e_vsi_add_vlan(vsi, vlan_id);
3893         else
3894                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3895 }
3896
3897 static int
3898 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3899                                 enum rte_vlan_type vlan_type,
3900                                 uint16_t tpid, int qinq)
3901 {
3902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3903         uint64_t reg_r = 0;
3904         uint64_t reg_w = 0;
3905         uint16_t reg_id = 3;
3906         int ret;
3907
3908         if (qinq) {
3909                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3910                         reg_id = 2;
3911         }
3912
3913         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3914                                           &reg_r, NULL);
3915         if (ret != I40E_SUCCESS) {
3916                 PMD_DRV_LOG(ERR,
3917                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3918                            reg_id);
3919                 return -EIO;
3920         }
3921         PMD_DRV_LOG(DEBUG,
3922                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3923                     reg_id, reg_r);
3924
3925         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3926         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3927         if (reg_r == reg_w) {
3928                 PMD_DRV_LOG(DEBUG, "No need to write");
3929                 return 0;
3930         }
3931
3932         ret = i40e_aq_debug_write_global_register(hw,
3933                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3934                                            reg_w, NULL);
3935         if (ret != I40E_SUCCESS) {
3936                 PMD_DRV_LOG(ERR,
3937                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3938                             reg_id);
3939                 return -EIO;
3940         }
3941         PMD_DRV_LOG(DEBUG,
3942                     "Global register 0x%08x is changed with value 0x%08x",
3943                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3944
3945         return 0;
3946 }
3947
3948 static int
3949 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3950                    enum rte_vlan_type vlan_type,
3951                    uint16_t tpid)
3952 {
3953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3954         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3955         int qinq = dev->data->dev_conf.rxmode.offloads &
3956                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3957         int ret = 0;
3958
3959         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3960              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3961             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3962                 PMD_DRV_LOG(ERR,
3963                             "Unsupported vlan type.");
3964                 return -EINVAL;
3965         }
3966
3967         if (pf->support_multi_driver) {
3968                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3969                 return -ENOTSUP;
3970         }
3971
3972         /* 802.1ad frames ability is added in NVM API 1.7*/
3973         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3974                 if (qinq) {
3975                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3976                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3977                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3978                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3979                 } else {
3980                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3981                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3982                 }
3983                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3984                 if (ret != I40E_SUCCESS) {
3985                         PMD_DRV_LOG(ERR,
3986                                     "Set switch config failed aq_err: %d",
3987                                     hw->aq.asq_last_status);
3988                         ret = -EIO;
3989                 }
3990         } else
3991                 /* If NVM API < 1.7, keep the register setting */
3992                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3993                                                       tpid, qinq);
3994
3995         return ret;
3996 }
3997
3998 /* Configure outer vlan stripping on or off in QinQ mode */
3999 static int
4000 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
4001 {
4002         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4003         int ret = I40E_SUCCESS;
4004         uint32_t reg;
4005
4006         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
4007                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
4008                 return -EINVAL;
4009         }
4010
4011         /* Configure for outer VLAN RX stripping */
4012         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4013
4014         if (on)
4015                 reg |= I40E_VSI_TSR_QINQ_STRIP;
4016         else
4017                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4018
4019         ret = i40e_aq_debug_write_register(hw,
4020                                                    I40E_VSI_TSR(vsi->vsi_id),
4021                                                    reg, NULL);
4022         if (ret < 0) {
4023                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4024                                     vsi->vsi_id);
4025                 return I40E_ERR_CONFIG;
4026         }
4027
4028         return ret;
4029 }
4030
4031 static int
4032 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4033 {
4034         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4035         struct i40e_vsi *vsi = pf->main_vsi;
4036         struct rte_eth_rxmode *rxmode;
4037
4038         rxmode = &dev->data->dev_conf.rxmode;
4039         if (mask & ETH_VLAN_FILTER_MASK) {
4040                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4041                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4042                 else
4043                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4044         }
4045
4046         if (mask & ETH_VLAN_STRIP_MASK) {
4047                 /* Enable or disable VLAN stripping */
4048                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4049                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4050                 else
4051                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4052         }
4053
4054         if (mask & ETH_VLAN_EXTEND_MASK) {
4055                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4056                         i40e_vsi_config_double_vlan(vsi, TRUE);
4057                         /* Set global registers with default ethertype. */
4058                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4059                                            RTE_ETHER_TYPE_VLAN);
4060                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4061                                            RTE_ETHER_TYPE_VLAN);
4062                 }
4063                 else
4064                         i40e_vsi_config_double_vlan(vsi, FALSE);
4065         }
4066
4067         if (mask & ETH_QINQ_STRIP_MASK) {
4068                 /* Enable or disable outer VLAN stripping */
4069                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4070                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4071                 else
4072                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4073         }
4074
4075         return 0;
4076 }
4077
4078 static void
4079 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4080                           __rte_unused uint16_t queue,
4081                           __rte_unused int on)
4082 {
4083         PMD_INIT_FUNC_TRACE();
4084 }
4085
4086 static int
4087 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4088 {
4089         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4090         struct i40e_vsi *vsi = pf->main_vsi;
4091         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4092         struct i40e_vsi_vlan_pvid_info info;
4093
4094         memset(&info, 0, sizeof(info));
4095         info.on = on;
4096         if (info.on)
4097                 info.config.pvid = pvid;
4098         else {
4099                 info.config.reject.tagged =
4100                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4101                 info.config.reject.untagged =
4102                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4103         }
4104
4105         return i40e_vsi_vlan_pvid_set(vsi, &info);
4106 }
4107
4108 static int
4109 i40e_dev_led_on(struct rte_eth_dev *dev)
4110 {
4111         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112         uint32_t mode = i40e_led_get(hw);
4113
4114         if (mode == 0)
4115                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4116
4117         return 0;
4118 }
4119
4120 static int
4121 i40e_dev_led_off(struct rte_eth_dev *dev)
4122 {
4123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4124         uint32_t mode = i40e_led_get(hw);
4125
4126         if (mode != 0)
4127                 i40e_led_set(hw, 0, false);
4128
4129         return 0;
4130 }
4131
4132 static int
4133 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4134 {
4135         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4136         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4137
4138         fc_conf->pause_time = pf->fc_conf.pause_time;
4139
4140         /* read out from register, in case they are modified by other port */
4141         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4142                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4143         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4144                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4145
4146         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4147         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4148
4149          /* Return current mode according to actual setting*/
4150         switch (hw->fc.current_mode) {
4151         case I40E_FC_FULL:
4152                 fc_conf->mode = RTE_FC_FULL;
4153                 break;
4154         case I40E_FC_TX_PAUSE:
4155                 fc_conf->mode = RTE_FC_TX_PAUSE;
4156                 break;
4157         case I40E_FC_RX_PAUSE:
4158                 fc_conf->mode = RTE_FC_RX_PAUSE;
4159                 break;
4160         case I40E_FC_NONE:
4161         default:
4162                 fc_conf->mode = RTE_FC_NONE;
4163         };
4164
4165         return 0;
4166 }
4167
4168 static int
4169 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4170 {
4171         uint32_t mflcn_reg, fctrl_reg, reg;
4172         uint32_t max_high_water;
4173         uint8_t i, aq_failure;
4174         int err;
4175         struct i40e_hw *hw;
4176         struct i40e_pf *pf;
4177         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4178                 [RTE_FC_NONE] = I40E_FC_NONE,
4179                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4180                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4181                 [RTE_FC_FULL] = I40E_FC_FULL
4182         };
4183
4184         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4185
4186         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4187         if ((fc_conf->high_water > max_high_water) ||
4188                         (fc_conf->high_water < fc_conf->low_water)) {
4189                 PMD_INIT_LOG(ERR,
4190                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4191                         max_high_water);
4192                 return -EINVAL;
4193         }
4194
4195         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4196         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4197         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4198
4199         pf->fc_conf.pause_time = fc_conf->pause_time;
4200         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4201         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4202
4203         PMD_INIT_FUNC_TRACE();
4204
4205         /* All the link flow control related enable/disable register
4206          * configuration is handle by the F/W
4207          */
4208         err = i40e_set_fc(hw, &aq_failure, true);
4209         if (err < 0)
4210                 return -ENOSYS;
4211
4212         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4213                 /* Configure flow control refresh threshold,
4214                  * the value for stat_tx_pause_refresh_timer[8]
4215                  * is used for global pause operation.
4216                  */
4217
4218                 I40E_WRITE_REG(hw,
4219                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4220                                pf->fc_conf.pause_time);
4221
4222                 /* configure the timer value included in transmitted pause
4223                  * frame,
4224                  * the value for stat_tx_pause_quanta[8] is used for global
4225                  * pause operation
4226                  */
4227                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4228                                pf->fc_conf.pause_time);
4229
4230                 fctrl_reg = I40E_READ_REG(hw,
4231                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4232
4233                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4234                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4235                 else
4236                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4237
4238                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4239                                fctrl_reg);
4240         } else {
4241                 /* Configure pause time (2 TCs per register) */
4242                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4243                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4244                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4245
4246                 /* Configure flow control refresh threshold value */
4247                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4248                                pf->fc_conf.pause_time / 2);
4249
4250                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4251
4252                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4253                  *depending on configuration
4254                  */
4255                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4256                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4257                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4258                 } else {
4259                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4260                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4261                 }
4262
4263                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4264         }
4265
4266         if (!pf->support_multi_driver) {
4267                 /* config water marker both based on the packets and bytes */
4268                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4269                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4270                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4271                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4272                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4273                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4274                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4275                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4276                                   << I40E_KILOSHIFT);
4277                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4278                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4279                                    << I40E_KILOSHIFT);
4280         } else {
4281                 PMD_DRV_LOG(ERR,
4282                             "Water marker configuration is not supported.");
4283         }
4284
4285         I40E_WRITE_FLUSH(hw);
4286
4287         return 0;
4288 }
4289
4290 static int
4291 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4292                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4293 {
4294         PMD_INIT_FUNC_TRACE();
4295
4296         return -ENOSYS;
4297 }
4298
4299 /* Add a MAC address, and update filters */
4300 static int
4301 i40e_macaddr_add(struct rte_eth_dev *dev,
4302                  struct rte_ether_addr *mac_addr,
4303                  __rte_unused uint32_t index,
4304                  uint32_t pool)
4305 {
4306         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4307         struct i40e_mac_filter_info mac_filter;
4308         struct i40e_vsi *vsi;
4309         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4310         int ret;
4311
4312         /* If VMDQ not enabled or configured, return */
4313         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4314                           !pf->nb_cfg_vmdq_vsi)) {
4315                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4316                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4317                         pool);
4318                 return -ENOTSUP;
4319         }
4320
4321         if (pool > pf->nb_cfg_vmdq_vsi) {
4322                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4323                                 pool, pf->nb_cfg_vmdq_vsi);
4324                 return -EINVAL;
4325         }
4326
4327         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4328         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4329                 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4330         else
4331                 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4332
4333         if (pool == 0)
4334                 vsi = pf->main_vsi;
4335         else
4336                 vsi = pf->vmdq[pool - 1].vsi;
4337
4338         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4339         if (ret != I40E_SUCCESS) {
4340                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4341                 return -ENODEV;
4342         }
4343         return 0;
4344 }
4345
4346 /* Remove a MAC address, and update filters */
4347 static void
4348 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4349 {
4350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4351         struct i40e_vsi *vsi;
4352         struct rte_eth_dev_data *data = dev->data;
4353         struct rte_ether_addr *macaddr;
4354         int ret;
4355         uint32_t i;
4356         uint64_t pool_sel;
4357
4358         macaddr = &(data->mac_addrs[index]);
4359
4360         pool_sel = dev->data->mac_pool_sel[index];
4361
4362         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4363                 if (pool_sel & (1ULL << i)) {
4364                         if (i == 0)
4365                                 vsi = pf->main_vsi;
4366                         else {
4367                                 /* No VMDQ pool enabled or configured */
4368                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4369                                         (i > pf->nb_cfg_vmdq_vsi)) {
4370                                         PMD_DRV_LOG(ERR,
4371                                                 "No VMDQ pool enabled/configured");
4372                                         return;
4373                                 }
4374                                 vsi = pf->vmdq[i - 1].vsi;
4375                         }
4376                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4377
4378                         if (ret) {
4379                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4380                                 return;
4381                         }
4382                 }
4383         }
4384 }
4385
4386 static int
4387 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4388 {
4389         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4390         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4391         uint32_t reg;
4392         int ret;
4393
4394         if (!lut)
4395                 return -EINVAL;
4396
4397         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4398                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4399                                           vsi->type != I40E_VSI_SRIOV,
4400                                           lut, lut_size);
4401                 if (ret) {
4402                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4403                         return ret;
4404                 }
4405         } else {
4406                 uint32_t *lut_dw = (uint32_t *)lut;
4407                 uint16_t i, lut_size_dw = lut_size / 4;
4408
4409                 if (vsi->type == I40E_VSI_SRIOV) {
4410                         for (i = 0; i <= lut_size_dw; i++) {
4411                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4412                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4413                         }
4414                 } else {
4415                         for (i = 0; i < lut_size_dw; i++)
4416                                 lut_dw[i] = I40E_READ_REG(hw,
4417                                                           I40E_PFQF_HLUT(i));
4418                 }
4419         }
4420
4421         return 0;
4422 }
4423
4424 int
4425 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4426 {
4427         struct i40e_pf *pf;
4428         struct i40e_hw *hw;
4429         int ret;
4430
4431         if (!vsi || !lut)
4432                 return -EINVAL;
4433
4434         pf = I40E_VSI_TO_PF(vsi);
4435         hw = I40E_VSI_TO_HW(vsi);
4436
4437         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4438                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4439                                           vsi->type != I40E_VSI_SRIOV,
4440                                           lut, lut_size);
4441                 if (ret) {
4442                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4443                         return ret;
4444                 }
4445         } else {
4446                 uint32_t *lut_dw = (uint32_t *)lut;
4447                 uint16_t i, lut_size_dw = lut_size / 4;
4448
4449                 if (vsi->type == I40E_VSI_SRIOV) {
4450                         for (i = 0; i < lut_size_dw; i++)
4451                                 I40E_WRITE_REG(
4452                                         hw,
4453                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4454                                         lut_dw[i]);
4455                 } else {
4456                         for (i = 0; i < lut_size_dw; i++)
4457                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4458                                                lut_dw[i]);
4459                 }
4460                 I40E_WRITE_FLUSH(hw);
4461         }
4462
4463         return 0;
4464 }
4465
4466 static int
4467 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4468                          struct rte_eth_rss_reta_entry64 *reta_conf,
4469                          uint16_t reta_size)
4470 {
4471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4472         uint16_t i, lut_size = pf->hash_lut_size;
4473         uint16_t idx, shift;
4474         uint8_t *lut;
4475         int ret;
4476
4477         if (reta_size != lut_size ||
4478                 reta_size > ETH_RSS_RETA_SIZE_512) {
4479                 PMD_DRV_LOG(ERR,
4480                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4481                         reta_size, lut_size);
4482                 return -EINVAL;
4483         }
4484
4485         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4486         if (!lut) {
4487                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4488                 return -ENOMEM;
4489         }
4490         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4491         if (ret)
4492                 goto out;
4493         for (i = 0; i < reta_size; i++) {
4494                 idx = i / RTE_RETA_GROUP_SIZE;
4495                 shift = i % RTE_RETA_GROUP_SIZE;
4496                 if (reta_conf[idx].mask & (1ULL << shift))
4497                         lut[i] = reta_conf[idx].reta[shift];
4498         }
4499         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4500
4501         pf->adapter->rss_reta_updated = 1;
4502
4503 out:
4504         rte_free(lut);
4505
4506         return ret;
4507 }
4508
4509 static int
4510 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4511                         struct rte_eth_rss_reta_entry64 *reta_conf,
4512                         uint16_t reta_size)
4513 {
4514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4515         uint16_t i, lut_size = pf->hash_lut_size;
4516         uint16_t idx, shift;
4517         uint8_t *lut;
4518         int ret;
4519
4520         if (reta_size != lut_size ||
4521                 reta_size > ETH_RSS_RETA_SIZE_512) {
4522                 PMD_DRV_LOG(ERR,
4523                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4524                         reta_size, lut_size);
4525                 return -EINVAL;
4526         }
4527
4528         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4529         if (!lut) {
4530                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4531                 return -ENOMEM;
4532         }
4533
4534         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4535         if (ret)
4536                 goto out;
4537         for (i = 0; i < reta_size; i++) {
4538                 idx = i / RTE_RETA_GROUP_SIZE;
4539                 shift = i % RTE_RETA_GROUP_SIZE;
4540                 if (reta_conf[idx].mask & (1ULL << shift))
4541                         reta_conf[idx].reta[shift] = lut[i];
4542         }
4543
4544 out:
4545         rte_free(lut);
4546
4547         return ret;
4548 }
4549
4550 /**
4551  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4552  * @hw:   pointer to the HW structure
4553  * @mem:  pointer to mem struct to fill out
4554  * @size: size of memory requested
4555  * @alignment: what to align the allocation to
4556  **/
4557 enum i40e_status_code
4558 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4559                         struct i40e_dma_mem *mem,
4560                         u64 size,
4561                         u32 alignment)
4562 {
4563         const struct rte_memzone *mz = NULL;
4564         char z_name[RTE_MEMZONE_NAMESIZE];
4565
4566         if (!mem)
4567                 return I40E_ERR_PARAM;
4568
4569         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4570         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4571                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4572         if (!mz)
4573                 return I40E_ERR_NO_MEMORY;
4574
4575         mem->size = size;
4576         mem->va = mz->addr;
4577         mem->pa = mz->iova;
4578         mem->zone = (const void *)mz;
4579         PMD_DRV_LOG(DEBUG,
4580                 "memzone %s allocated with physical address: %"PRIu64,
4581                 mz->name, mem->pa);
4582
4583         return I40E_SUCCESS;
4584 }
4585
4586 /**
4587  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4588  * @hw:   pointer to the HW structure
4589  * @mem:  ptr to mem struct to free
4590  **/
4591 enum i40e_status_code
4592 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4593                     struct i40e_dma_mem *mem)
4594 {
4595         if (!mem)
4596                 return I40E_ERR_PARAM;
4597
4598         PMD_DRV_LOG(DEBUG,
4599                 "memzone %s to be freed with physical address: %"PRIu64,
4600                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4601         rte_memzone_free((const struct rte_memzone *)mem->zone);
4602         mem->zone = NULL;
4603         mem->va = NULL;
4604         mem->pa = (u64)0;
4605
4606         return I40E_SUCCESS;
4607 }
4608
4609 /**
4610  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4611  * @hw:   pointer to the HW structure
4612  * @mem:  pointer to mem struct to fill out
4613  * @size: size of memory requested
4614  **/
4615 enum i40e_status_code
4616 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4617                          struct i40e_virt_mem *mem,
4618                          u32 size)
4619 {
4620         if (!mem)
4621                 return I40E_ERR_PARAM;
4622
4623         mem->size = size;
4624         mem->va = rte_zmalloc("i40e", size, 0);
4625
4626         if (mem->va)
4627                 return I40E_SUCCESS;
4628         else
4629                 return I40E_ERR_NO_MEMORY;
4630 }
4631
4632 /**
4633  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4634  * @hw:   pointer to the HW structure
4635  * @mem:  pointer to mem struct to free
4636  **/
4637 enum i40e_status_code
4638 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4639                      struct i40e_virt_mem *mem)
4640 {
4641         if (!mem)
4642                 return I40E_ERR_PARAM;
4643
4644         rte_free(mem->va);
4645         mem->va = NULL;
4646
4647         return I40E_SUCCESS;
4648 }
4649
4650 void
4651 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4652 {
4653         rte_spinlock_init(&sp->spinlock);
4654 }
4655
4656 void
4657 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4658 {
4659         rte_spinlock_lock(&sp->spinlock);
4660 }
4661
4662 void
4663 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4664 {
4665         rte_spinlock_unlock(&sp->spinlock);
4666 }
4667
4668 void
4669 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4670 {
4671         return;
4672 }
4673
4674 /**
4675  * Get the hardware capabilities, which will be parsed
4676  * and saved into struct i40e_hw.
4677  */
4678 static int
4679 i40e_get_cap(struct i40e_hw *hw)
4680 {
4681         struct i40e_aqc_list_capabilities_element_resp *buf;
4682         uint16_t len, size = 0;
4683         int ret;
4684
4685         /* Calculate a huge enough buff for saving response data temporarily */
4686         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4687                                                 I40E_MAX_CAP_ELE_NUM;
4688         buf = rte_zmalloc("i40e", len, 0);
4689         if (!buf) {
4690                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4691                 return I40E_ERR_NO_MEMORY;
4692         }
4693
4694         /* Get, parse the capabilities and save it to hw */
4695         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4696                         i40e_aqc_opc_list_func_capabilities, NULL);
4697         if (ret != I40E_SUCCESS)
4698                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4699
4700         /* Free the temporary buffer after being used */
4701         rte_free(buf);
4702
4703         return ret;
4704 }
4705
4706 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4707
4708 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4709                 const char *value,
4710                 void *opaque)
4711 {
4712         struct i40e_pf *pf;
4713         unsigned long num;
4714         char *end;
4715
4716         pf = (struct i40e_pf *)opaque;
4717         RTE_SET_USED(key);
4718
4719         errno = 0;
4720         num = strtoul(value, &end, 0);
4721         if (errno != 0 || end == value || *end != 0) {
4722                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4723                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4724                 return -(EINVAL);
4725         }
4726
4727         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4728                 pf->vf_nb_qp_max = (uint16_t)num;
4729         else
4730                 /* here return 0 to make next valid same argument work */
4731                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4732                             "power of 2 and equal or less than 16 !, Now it is "
4733                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4734
4735         return 0;
4736 }
4737
4738 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4739 {
4740         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4741         struct rte_kvargs *kvlist;
4742         int kvargs_count;
4743
4744         /* set default queue number per VF as 4 */
4745         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4746
4747         if (dev->device->devargs == NULL)
4748                 return 0;
4749
4750         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4751         if (kvlist == NULL)
4752                 return -(EINVAL);
4753
4754         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4755         if (!kvargs_count) {
4756                 rte_kvargs_free(kvlist);
4757                 return 0;
4758         }
4759
4760         if (kvargs_count > 1)
4761                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4762                             "the first invalid or last valid one is used !",
4763                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4764
4765         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4766                            i40e_pf_parse_vf_queue_number_handler, pf);
4767
4768         rte_kvargs_free(kvlist);
4769
4770         return 0;
4771 }
4772
4773 static int
4774 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4775 {
4776         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4778         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4779         uint16_t qp_count = 0, vsi_count = 0;
4780
4781         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4782                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4783                 return -EINVAL;
4784         }
4785
4786         i40e_pf_config_vf_rxq_number(dev);
4787
4788         /* Add the parameter init for LFC */
4789         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4790         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4791         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4792
4793         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4794         pf->max_num_vsi = hw->func_caps.num_vsis;
4795         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4796         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4797
4798         /* FDir queue/VSI allocation */
4799         pf->fdir_qp_offset = 0;
4800         if (hw->func_caps.fd) {
4801                 pf->flags |= I40E_FLAG_FDIR;
4802                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4803         } else {
4804                 pf->fdir_nb_qps = 0;
4805         }
4806         qp_count += pf->fdir_nb_qps;
4807         vsi_count += 1;
4808
4809         /* LAN queue/VSI allocation */
4810         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4811         if (!hw->func_caps.rss) {
4812                 pf->lan_nb_qps = 1;
4813         } else {
4814                 pf->flags |= I40E_FLAG_RSS;
4815                 if (hw->mac.type == I40E_MAC_X722)
4816                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4817                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4818         }
4819         qp_count += pf->lan_nb_qps;
4820         vsi_count += 1;
4821
4822         /* VF queue/VSI allocation */
4823         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4824         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4825                 pf->flags |= I40E_FLAG_SRIOV;
4826                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4827                 pf->vf_num = pci_dev->max_vfs;
4828                 PMD_DRV_LOG(DEBUG,
4829                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4830                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4831         } else {
4832                 pf->vf_nb_qps = 0;
4833                 pf->vf_num = 0;
4834         }
4835         qp_count += pf->vf_nb_qps * pf->vf_num;
4836         vsi_count += pf->vf_num;
4837
4838         /* VMDq queue/VSI allocation */
4839         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4840         pf->vmdq_nb_qps = 0;
4841         pf->max_nb_vmdq_vsi = 0;
4842         if (hw->func_caps.vmdq) {
4843                 if (qp_count < hw->func_caps.num_tx_qp &&
4844                         vsi_count < hw->func_caps.num_vsis) {
4845                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4846                                 qp_count) / pf->vmdq_nb_qp_max;
4847
4848                         /* Limit the maximum number of VMDq vsi to the maximum
4849                          * ethdev can support
4850                          */
4851                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4852                                 hw->func_caps.num_vsis - vsi_count);
4853                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4854                                 ETH_64_POOLS);
4855                         if (pf->max_nb_vmdq_vsi) {
4856                                 pf->flags |= I40E_FLAG_VMDQ;
4857                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4858                                 PMD_DRV_LOG(DEBUG,
4859                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4860                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4861                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4862                         } else {
4863                                 PMD_DRV_LOG(INFO,
4864                                         "No enough queues left for VMDq");
4865                         }
4866                 } else {
4867                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4868                 }
4869         }
4870         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4871         vsi_count += pf->max_nb_vmdq_vsi;
4872
4873         if (hw->func_caps.dcb)
4874                 pf->flags |= I40E_FLAG_DCB;
4875
4876         if (qp_count > hw->func_caps.num_tx_qp) {
4877                 PMD_DRV_LOG(ERR,
4878                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4879                         qp_count, hw->func_caps.num_tx_qp);
4880                 return -EINVAL;
4881         }
4882         if (vsi_count > hw->func_caps.num_vsis) {
4883                 PMD_DRV_LOG(ERR,
4884                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4885                         vsi_count, hw->func_caps.num_vsis);
4886                 return -EINVAL;
4887         }
4888
4889         return 0;
4890 }
4891
4892 static int
4893 i40e_pf_get_switch_config(struct i40e_pf *pf)
4894 {
4895         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4896         struct i40e_aqc_get_switch_config_resp *switch_config;
4897         struct i40e_aqc_switch_config_element_resp *element;
4898         uint16_t start_seid = 0, num_reported;
4899         int ret;
4900
4901         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4902                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4903         if (!switch_config) {
4904                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4905                 return -ENOMEM;
4906         }
4907
4908         /* Get the switch configurations */
4909         ret = i40e_aq_get_switch_config(hw, switch_config,
4910                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4911         if (ret != I40E_SUCCESS) {
4912                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4913                 goto fail;
4914         }
4915         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4916         if (num_reported != 1) { /* The number should be 1 */
4917                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4918                 goto fail;
4919         }
4920
4921         /* Parse the switch configuration elements */
4922         element = &(switch_config->element[0]);
4923         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4924                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4925                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4926         } else
4927                 PMD_DRV_LOG(INFO, "Unknown element type");
4928
4929 fail:
4930         rte_free(switch_config);
4931
4932         return ret;
4933 }
4934
4935 static int
4936 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4937                         uint32_t num)
4938 {
4939         struct pool_entry *entry;
4940
4941         if (pool == NULL || num == 0)
4942                 return -EINVAL;
4943
4944         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4945         if (entry == NULL) {
4946                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4947                 return -ENOMEM;
4948         }
4949
4950         /* queue heap initialize */
4951         pool->num_free = num;
4952         pool->num_alloc = 0;
4953         pool->base = base;
4954         LIST_INIT(&pool->alloc_list);
4955         LIST_INIT(&pool->free_list);
4956
4957         /* Initialize element  */
4958         entry->base = 0;
4959         entry->len = num;
4960
4961         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4962         return 0;
4963 }
4964
4965 static void
4966 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4967 {
4968         struct pool_entry *entry, *next_entry;
4969
4970         if (pool == NULL)
4971                 return;
4972
4973         for (entry = LIST_FIRST(&pool->alloc_list);
4974                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4975                         entry = next_entry) {
4976                 LIST_REMOVE(entry, next);
4977                 rte_free(entry);
4978         }
4979
4980         for (entry = LIST_FIRST(&pool->free_list);
4981                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4982                         entry = next_entry) {
4983                 LIST_REMOVE(entry, next);
4984                 rte_free(entry);
4985         }
4986
4987         pool->num_free = 0;
4988         pool->num_alloc = 0;
4989         pool->base = 0;
4990         LIST_INIT(&pool->alloc_list);
4991         LIST_INIT(&pool->free_list);
4992 }
4993
4994 static int
4995 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4996                        uint32_t base)
4997 {
4998         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4999         uint32_t pool_offset;
5000         uint16_t len;
5001         int insert;
5002
5003         if (pool == NULL) {
5004                 PMD_DRV_LOG(ERR, "Invalid parameter");
5005                 return -EINVAL;
5006         }
5007
5008         pool_offset = base - pool->base;
5009         /* Lookup in alloc list */
5010         LIST_FOREACH(entry, &pool->alloc_list, next) {
5011                 if (entry->base == pool_offset) {
5012                         valid_entry = entry;
5013                         LIST_REMOVE(entry, next);
5014                         break;
5015                 }
5016         }
5017
5018         /* Not find, return */
5019         if (valid_entry == NULL) {
5020                 PMD_DRV_LOG(ERR, "Failed to find entry");
5021                 return -EINVAL;
5022         }
5023
5024         /**
5025          * Found it, move it to free list  and try to merge.
5026          * In order to make merge easier, always sort it by qbase.
5027          * Find adjacent prev and last entries.
5028          */
5029         prev = next = NULL;
5030         LIST_FOREACH(entry, &pool->free_list, next) {
5031                 if (entry->base > valid_entry->base) {
5032                         next = entry;
5033                         break;
5034                 }
5035                 prev = entry;
5036         }
5037
5038         insert = 0;
5039         len = valid_entry->len;
5040         /* Try to merge with next one*/
5041         if (next != NULL) {
5042                 /* Merge with next one */
5043                 if (valid_entry->base + len == next->base) {
5044                         next->base = valid_entry->base;
5045                         next->len += len;
5046                         rte_free(valid_entry);
5047                         valid_entry = next;
5048                         insert = 1;
5049                 }
5050         }
5051
5052         if (prev != NULL) {
5053                 /* Merge with previous one */
5054                 if (prev->base + prev->len == valid_entry->base) {
5055                         prev->len += len;
5056                         /* If it merge with next one, remove next node */
5057                         if (insert == 1) {
5058                                 LIST_REMOVE(valid_entry, next);
5059                                 rte_free(valid_entry);
5060                                 valid_entry = NULL;
5061                         } else {
5062                                 rte_free(valid_entry);
5063                                 valid_entry = NULL;
5064                                 insert = 1;
5065                         }
5066                 }
5067         }
5068
5069         /* Not find any entry to merge, insert */
5070         if (insert == 0) {
5071                 if (prev != NULL)
5072                         LIST_INSERT_AFTER(prev, valid_entry, next);
5073                 else if (next != NULL)
5074                         LIST_INSERT_BEFORE(next, valid_entry, next);
5075                 else /* It's empty list, insert to head */
5076                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5077         }
5078
5079         pool->num_free += len;
5080         pool->num_alloc -= len;
5081
5082         return 0;
5083 }
5084
5085 static int
5086 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5087                        uint16_t num)
5088 {
5089         struct pool_entry *entry, *valid_entry;
5090
5091         if (pool == NULL || num == 0) {
5092                 PMD_DRV_LOG(ERR, "Invalid parameter");
5093                 return -EINVAL;
5094         }
5095
5096         if (pool->num_free < num) {
5097                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5098                             num, pool->num_free);
5099                 return -ENOMEM;
5100         }
5101
5102         valid_entry = NULL;
5103         /* Lookup  in free list and find most fit one */
5104         LIST_FOREACH(entry, &pool->free_list, next) {
5105                 if (entry->len >= num) {
5106                         /* Find best one */
5107                         if (entry->len == num) {
5108                                 valid_entry = entry;
5109                                 break;
5110                         }
5111                         if (valid_entry == NULL || valid_entry->len > entry->len)
5112                                 valid_entry = entry;
5113                 }
5114         }
5115
5116         /* Not find one to satisfy the request, return */
5117         if (valid_entry == NULL) {
5118                 PMD_DRV_LOG(ERR, "No valid entry found");
5119                 return -ENOMEM;
5120         }
5121         /**
5122          * The entry have equal queue number as requested,
5123          * remove it from alloc_list.
5124          */
5125         if (valid_entry->len == num) {
5126                 LIST_REMOVE(valid_entry, next);
5127         } else {
5128                 /**
5129                  * The entry have more numbers than requested,
5130                  * create a new entry for alloc_list and minus its
5131                  * queue base and number in free_list.
5132                  */
5133                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5134                 if (entry == NULL) {
5135                         PMD_DRV_LOG(ERR,
5136                                 "Failed to allocate memory for resource pool");
5137                         return -ENOMEM;
5138                 }
5139                 entry->base = valid_entry->base;
5140                 entry->len = num;
5141                 valid_entry->base += num;
5142                 valid_entry->len -= num;
5143                 valid_entry = entry;
5144         }
5145
5146         /* Insert it into alloc list, not sorted */
5147         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5148
5149         pool->num_free -= valid_entry->len;
5150         pool->num_alloc += valid_entry->len;
5151
5152         return valid_entry->base + pool->base;
5153 }
5154
5155 /**
5156  * bitmap_is_subset - Check whether src2 is subset of src1
5157  **/
5158 static inline int
5159 bitmap_is_subset(uint8_t src1, uint8_t src2)
5160 {
5161         return !((src1 ^ src2) & src2);
5162 }
5163
5164 static enum i40e_status_code
5165 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5166 {
5167         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5168
5169         /* If DCB is not supported, only default TC is supported */
5170         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5171                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5172                 return I40E_NOT_SUPPORTED;
5173         }
5174
5175         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5176                 PMD_DRV_LOG(ERR,
5177                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5178                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5179                 return I40E_NOT_SUPPORTED;
5180         }
5181         return I40E_SUCCESS;
5182 }
5183
5184 int
5185 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5186                                 struct i40e_vsi_vlan_pvid_info *info)
5187 {
5188         struct i40e_hw *hw;
5189         struct i40e_vsi_context ctxt;
5190         uint8_t vlan_flags = 0;
5191         int ret;
5192
5193         if (vsi == NULL || info == NULL) {
5194                 PMD_DRV_LOG(ERR, "invalid parameters");
5195                 return I40E_ERR_PARAM;
5196         }
5197
5198         if (info->on) {
5199                 vsi->info.pvid = info->config.pvid;
5200                 /**
5201                  * If insert pvid is enabled, only tagged pkts are
5202                  * allowed to be sent out.
5203                  */
5204                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5205                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5206         } else {
5207                 vsi->info.pvid = 0;
5208                 if (info->config.reject.tagged == 0)
5209                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5210
5211                 if (info->config.reject.untagged == 0)
5212                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5213         }
5214         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5215                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5216         vsi->info.port_vlan_flags |= vlan_flags;
5217         vsi->info.valid_sections =
5218                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5219         memset(&ctxt, 0, sizeof(ctxt));
5220         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5221         ctxt.seid = vsi->seid;
5222
5223         hw = I40E_VSI_TO_HW(vsi);
5224         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5225         if (ret != I40E_SUCCESS)
5226                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5227
5228         return ret;
5229 }
5230
5231 static int
5232 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5233 {
5234         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5235         int i, ret;
5236         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5237
5238         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5239         if (ret != I40E_SUCCESS)
5240                 return ret;
5241
5242         if (!vsi->seid) {
5243                 PMD_DRV_LOG(ERR, "seid not valid");
5244                 return -EINVAL;
5245         }
5246
5247         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5248         tc_bw_data.tc_valid_bits = enabled_tcmap;
5249         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5250                 tc_bw_data.tc_bw_credits[i] =
5251                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5252
5253         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5254         if (ret != I40E_SUCCESS) {
5255                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5256                 return ret;
5257         }
5258
5259         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5260                                         sizeof(vsi->info.qs_handle));
5261         return I40E_SUCCESS;
5262 }
5263
5264 static enum i40e_status_code
5265 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5266                                  struct i40e_aqc_vsi_properties_data *info,
5267                                  uint8_t enabled_tcmap)
5268 {
5269         enum i40e_status_code ret;
5270         int i, total_tc = 0;
5271         uint16_t qpnum_per_tc, bsf, qp_idx;
5272
5273         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5274         if (ret != I40E_SUCCESS)
5275                 return ret;
5276
5277         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5278                 if (enabled_tcmap & (1 << i))
5279                         total_tc++;
5280         if (total_tc == 0)
5281                 total_tc = 1;
5282         vsi->enabled_tc = enabled_tcmap;
5283
5284         /* Number of queues per enabled TC */
5285         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5286         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5287         bsf = rte_bsf32(qpnum_per_tc);
5288
5289         /* Adjust the queue number to actual queues that can be applied */
5290         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5291                 vsi->nb_qps = qpnum_per_tc * total_tc;
5292
5293         /**
5294          * Configure TC and queue mapping parameters, for enabled TC,
5295          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5296          * default queue will serve it.
5297          */
5298         qp_idx = 0;
5299         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5300                 if (vsi->enabled_tc & (1 << i)) {
5301                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5302                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5303                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5304                         qp_idx += qpnum_per_tc;
5305                 } else
5306                         info->tc_mapping[i] = 0;
5307         }
5308
5309         /* Associate queue number with VSI */
5310         if (vsi->type == I40E_VSI_SRIOV) {
5311                 info->mapping_flags |=
5312                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5313                 for (i = 0; i < vsi->nb_qps; i++)
5314                         info->queue_mapping[i] =
5315                                 rte_cpu_to_le_16(vsi->base_queue + i);
5316         } else {
5317                 info->mapping_flags |=
5318                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5319                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5320         }
5321         info->valid_sections |=
5322                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5323
5324         return I40E_SUCCESS;
5325 }
5326
5327 static int
5328 i40e_veb_release(struct i40e_veb *veb)
5329 {
5330         struct i40e_vsi *vsi;
5331         struct i40e_hw *hw;
5332
5333         if (veb == NULL)
5334                 return -EINVAL;
5335
5336         if (!TAILQ_EMPTY(&veb->head)) {
5337                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5338                 return -EACCES;
5339         }
5340         /* associate_vsi field is NULL for floating VEB */
5341         if (veb->associate_vsi != NULL) {
5342                 vsi = veb->associate_vsi;
5343                 hw = I40E_VSI_TO_HW(vsi);
5344
5345                 vsi->uplink_seid = veb->uplink_seid;
5346                 vsi->veb = NULL;
5347         } else {
5348                 veb->associate_pf->main_vsi->floating_veb = NULL;
5349                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5350         }
5351
5352         i40e_aq_delete_element(hw, veb->seid, NULL);
5353         rte_free(veb);
5354         return I40E_SUCCESS;
5355 }
5356
5357 /* Setup a veb */
5358 static struct i40e_veb *
5359 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5360 {
5361         struct i40e_veb *veb;
5362         int ret;
5363         struct i40e_hw *hw;
5364
5365         if (pf == NULL) {
5366                 PMD_DRV_LOG(ERR,
5367                             "veb setup failed, associated PF shouldn't null");
5368                 return NULL;
5369         }
5370         hw = I40E_PF_TO_HW(pf);
5371
5372         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5373         if (!veb) {
5374                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5375                 goto fail;
5376         }
5377
5378         veb->associate_vsi = vsi;
5379         veb->associate_pf = pf;
5380         TAILQ_INIT(&veb->head);
5381         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5382
5383         /* create floating veb if vsi is NULL */
5384         if (vsi != NULL) {
5385                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5386                                       I40E_DEFAULT_TCMAP, false,
5387                                       &veb->seid, false, NULL);
5388         } else {
5389                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5390                                       true, &veb->seid, false, NULL);
5391         }
5392
5393         if (ret != I40E_SUCCESS) {
5394                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5395                             hw->aq.asq_last_status);
5396                 goto fail;
5397         }
5398         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5399
5400         /* get statistics index */
5401         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5402                                 &veb->stats_idx, NULL, NULL, NULL);
5403         if (ret != I40E_SUCCESS) {
5404                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5405                             hw->aq.asq_last_status);
5406                 goto fail;
5407         }
5408         /* Get VEB bandwidth, to be implemented */
5409         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5410         if (vsi)
5411                 vsi->uplink_seid = veb->seid;
5412
5413         return veb;
5414 fail:
5415         rte_free(veb);
5416         return NULL;
5417 }
5418
5419 int
5420 i40e_vsi_release(struct i40e_vsi *vsi)
5421 {
5422         struct i40e_pf *pf;
5423         struct i40e_hw *hw;
5424         struct i40e_vsi_list *vsi_list;
5425         void *temp;
5426         int ret;
5427         struct i40e_mac_filter *f;
5428         uint16_t user_param;
5429
5430         if (!vsi)
5431                 return I40E_SUCCESS;
5432
5433         if (!vsi->adapter)
5434                 return -EFAULT;
5435
5436         user_param = vsi->user_param;
5437
5438         pf = I40E_VSI_TO_PF(vsi);
5439         hw = I40E_VSI_TO_HW(vsi);
5440
5441         /* VSI has child to attach, release child first */
5442         if (vsi->veb) {
5443                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5444                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5445                                 return -1;
5446                 }
5447                 i40e_veb_release(vsi->veb);
5448         }
5449
5450         if (vsi->floating_veb) {
5451                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5452                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5453                                 return -1;
5454                 }
5455         }
5456
5457         /* Remove all macvlan filters of the VSI */
5458         i40e_vsi_remove_all_macvlan_filter(vsi);
5459         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5460                 rte_free(f);
5461
5462         if (vsi->type != I40E_VSI_MAIN &&
5463             ((vsi->type != I40E_VSI_SRIOV) ||
5464             !pf->floating_veb_list[user_param])) {
5465                 /* Remove vsi from parent's sibling list */
5466                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5467                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5468                         return I40E_ERR_PARAM;
5469                 }
5470                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5471                                 &vsi->sib_vsi_list, list);
5472
5473                 /* Remove all switch element of the VSI */
5474                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5475                 if (ret != I40E_SUCCESS)
5476                         PMD_DRV_LOG(ERR, "Failed to delete element");
5477         }
5478
5479         if ((vsi->type == I40E_VSI_SRIOV) &&
5480             pf->floating_veb_list[user_param]) {
5481                 /* Remove vsi from parent's sibling list */
5482                 if (vsi->parent_vsi == NULL ||
5483                     vsi->parent_vsi->floating_veb == NULL) {
5484                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5485                         return I40E_ERR_PARAM;
5486                 }
5487                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5488                              &vsi->sib_vsi_list, list);
5489
5490                 /* Remove all switch element of the VSI */
5491                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5492                 if (ret != I40E_SUCCESS)
5493                         PMD_DRV_LOG(ERR, "Failed to delete element");
5494         }
5495
5496         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5497
5498         if (vsi->type != I40E_VSI_SRIOV)
5499                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5500         rte_free(vsi);
5501
5502         return I40E_SUCCESS;
5503 }
5504
5505 static int
5506 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5507 {
5508         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5509         struct i40e_aqc_remove_macvlan_element_data def_filter;
5510         struct i40e_mac_filter_info filter;
5511         int ret;
5512
5513         if (vsi->type != I40E_VSI_MAIN)
5514                 return I40E_ERR_CONFIG;
5515         memset(&def_filter, 0, sizeof(def_filter));
5516         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5517                                         ETH_ADDR_LEN);
5518         def_filter.vlan_tag = 0;
5519         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5520                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5521         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5522         if (ret != I40E_SUCCESS) {
5523                 struct i40e_mac_filter *f;
5524                 struct rte_ether_addr *mac;
5525
5526                 PMD_DRV_LOG(DEBUG,
5527                             "Cannot remove the default macvlan filter");
5528                 /* It needs to add the permanent mac into mac list */
5529                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5530                 if (f == NULL) {
5531                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5532                         return I40E_ERR_NO_MEMORY;
5533                 }
5534                 mac = &f->mac_info.mac_addr;
5535                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5536                                 ETH_ADDR_LEN);
5537                 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5538                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5539                 vsi->mac_num++;
5540
5541                 return ret;
5542         }
5543         rte_memcpy(&filter.mac_addr,
5544                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5545         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5546         return i40e_vsi_add_mac(vsi, &filter);
5547 }
5548
5549 /*
5550  * i40e_vsi_get_bw_config - Query VSI BW Information
5551  * @vsi: the VSI to be queried
5552  *
5553  * Returns 0 on success, negative value on failure
5554  */
5555 static enum i40e_status_code
5556 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5557 {
5558         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5559         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5560         struct i40e_hw *hw = &vsi->adapter->hw;
5561         i40e_status ret;
5562         int i;
5563         uint32_t bw_max;
5564
5565         memset(&bw_config, 0, sizeof(bw_config));
5566         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5567         if (ret != I40E_SUCCESS) {
5568                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5569                             hw->aq.asq_last_status);
5570                 return ret;
5571         }
5572
5573         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5574         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5575                                         &ets_sla_config, NULL);
5576         if (ret != I40E_SUCCESS) {
5577                 PMD_DRV_LOG(ERR,
5578                         "VSI failed to get TC bandwdith configuration %u",
5579                         hw->aq.asq_last_status);
5580                 return ret;
5581         }
5582
5583         /* store and print out BW info */
5584         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5585         vsi->bw_info.bw_max = bw_config.max_bw;
5586         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5587         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5588         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5589                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5590                      I40E_16_BIT_WIDTH);
5591         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5592                 vsi->bw_info.bw_ets_share_credits[i] =
5593                                 ets_sla_config.share_credits[i];
5594                 vsi->bw_info.bw_ets_credits[i] =
5595                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5596                 /* 4 bits per TC, 4th bit is reserved */
5597                 vsi->bw_info.bw_ets_max[i] =
5598                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5599                                   RTE_LEN2MASK(3, uint8_t));
5600                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5601                             vsi->bw_info.bw_ets_share_credits[i]);
5602                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5603                             vsi->bw_info.bw_ets_credits[i]);
5604                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5605                             vsi->bw_info.bw_ets_max[i]);
5606         }
5607
5608         return I40E_SUCCESS;
5609 }
5610
5611 /* i40e_enable_pf_lb
5612  * @pf: pointer to the pf structure
5613  *
5614  * allow loopback on pf
5615  */
5616 static inline void
5617 i40e_enable_pf_lb(struct i40e_pf *pf)
5618 {
5619         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5620         struct i40e_vsi_context ctxt;
5621         int ret;
5622
5623         /* Use the FW API if FW >= v5.0 */
5624         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5625                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5626                 return;
5627         }
5628
5629         memset(&ctxt, 0, sizeof(ctxt));
5630         ctxt.seid = pf->main_vsi_seid;
5631         ctxt.pf_num = hw->pf_id;
5632         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5633         if (ret) {
5634                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5635                             ret, hw->aq.asq_last_status);
5636                 return;
5637         }
5638         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5639         ctxt.info.valid_sections =
5640                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5641         ctxt.info.switch_id |=
5642                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5643
5644         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5645         if (ret)
5646                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5647                             hw->aq.asq_last_status);
5648 }
5649
5650 /* Setup a VSI */
5651 struct i40e_vsi *
5652 i40e_vsi_setup(struct i40e_pf *pf,
5653                enum i40e_vsi_type type,
5654                struct i40e_vsi *uplink_vsi,
5655                uint16_t user_param)
5656 {
5657         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5658         struct i40e_vsi *vsi;
5659         struct i40e_mac_filter_info filter;
5660         int ret;
5661         struct i40e_vsi_context ctxt;
5662         struct rte_ether_addr broadcast =
5663                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5664
5665         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5666             uplink_vsi == NULL) {
5667                 PMD_DRV_LOG(ERR,
5668                         "VSI setup failed, VSI link shouldn't be NULL");
5669                 return NULL;
5670         }
5671
5672         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5673                 PMD_DRV_LOG(ERR,
5674                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5675                 return NULL;
5676         }
5677
5678         /* two situations
5679          * 1.type is not MAIN and uplink vsi is not NULL
5680          * If uplink vsi didn't setup VEB, create one first under veb field
5681          * 2.type is SRIOV and the uplink is NULL
5682          * If floating VEB is NULL, create one veb under floating veb field
5683          */
5684
5685         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5686             uplink_vsi->veb == NULL) {
5687                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5688
5689                 if (uplink_vsi->veb == NULL) {
5690                         PMD_DRV_LOG(ERR, "VEB setup failed");
5691                         return NULL;
5692                 }
5693                 /* set ALLOWLOOPBACk on pf, when veb is created */
5694                 i40e_enable_pf_lb(pf);
5695         }
5696
5697         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5698             pf->main_vsi->floating_veb == NULL) {
5699                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5700
5701                 if (pf->main_vsi->floating_veb == NULL) {
5702                         PMD_DRV_LOG(ERR, "VEB setup failed");
5703                         return NULL;
5704                 }
5705         }
5706
5707         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5708         if (!vsi) {
5709                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5710                 return NULL;
5711         }
5712         TAILQ_INIT(&vsi->mac_list);
5713         vsi->type = type;
5714         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5715         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5716         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5717         vsi->user_param = user_param;
5718         vsi->vlan_anti_spoof_on = 0;
5719         vsi->vlan_filter_on = 0;
5720         /* Allocate queues */
5721         switch (vsi->type) {
5722         case I40E_VSI_MAIN  :
5723                 vsi->nb_qps = pf->lan_nb_qps;
5724                 break;
5725         case I40E_VSI_SRIOV :
5726                 vsi->nb_qps = pf->vf_nb_qps;
5727                 break;
5728         case I40E_VSI_VMDQ2:
5729                 vsi->nb_qps = pf->vmdq_nb_qps;
5730                 break;
5731         case I40E_VSI_FDIR:
5732                 vsi->nb_qps = pf->fdir_nb_qps;
5733                 break;
5734         default:
5735                 goto fail_mem;
5736         }
5737         /*
5738          * The filter status descriptor is reported in rx queue 0,
5739          * while the tx queue for fdir filter programming has no
5740          * such constraints, can be non-zero queues.
5741          * To simplify it, choose FDIR vsi use queue 0 pair.
5742          * To make sure it will use queue 0 pair, queue allocation
5743          * need be done before this function is called
5744          */
5745         if (type != I40E_VSI_FDIR) {
5746                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5747                         if (ret < 0) {
5748                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5749                                                 vsi->seid, ret);
5750                                 goto fail_mem;
5751                         }
5752                         vsi->base_queue = ret;
5753         } else
5754                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5755
5756         /* VF has MSIX interrupt in VF range, don't allocate here */
5757         if (type == I40E_VSI_MAIN) {
5758                 if (pf->support_multi_driver) {
5759                         /* If support multi-driver, need to use INT0 instead of
5760                          * allocating from msix pool. The Msix pool is init from
5761                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5762                          * to 1 without calling i40e_res_pool_alloc.
5763                          */
5764                         vsi->msix_intr = 0;
5765                         vsi->nb_msix = 1;
5766                 } else {
5767                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5768                                                   RTE_MIN(vsi->nb_qps,
5769                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5770                         if (ret < 0) {
5771                                 PMD_DRV_LOG(ERR,
5772                                             "VSI MAIN %d get heap failed %d",
5773                                             vsi->seid, ret);
5774                                 goto fail_queue_alloc;
5775                         }
5776                         vsi->msix_intr = ret;
5777                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5778                                                RTE_MAX_RXTX_INTR_VEC_ID);
5779                 }
5780         } else if (type != I40E_VSI_SRIOV) {
5781                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5782                 if (ret < 0) {
5783                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5784                         if (type != I40E_VSI_FDIR)
5785                                 goto fail_queue_alloc;
5786                         vsi->msix_intr = 0;
5787                         vsi->nb_msix = 0;
5788                 } else {
5789                         vsi->msix_intr = ret;
5790                         vsi->nb_msix = 1;
5791                 }
5792         } else {
5793                 vsi->msix_intr = 0;
5794                 vsi->nb_msix = 0;
5795         }
5796
5797         /* Add VSI */
5798         if (type == I40E_VSI_MAIN) {
5799                 /* For main VSI, no need to add since it's default one */
5800                 vsi->uplink_seid = pf->mac_seid;
5801                 vsi->seid = pf->main_vsi_seid;
5802                 /* Bind queues with specific MSIX interrupt */
5803                 /**
5804                  * Needs 2 interrupt at least, one for misc cause which will
5805                  * enabled from OS side, Another for queues binding the
5806                  * interrupt from device side only.
5807                  */
5808
5809                 /* Get default VSI parameters from hardware */
5810                 memset(&ctxt, 0, sizeof(ctxt));
5811                 ctxt.seid = vsi->seid;
5812                 ctxt.pf_num = hw->pf_id;
5813                 ctxt.uplink_seid = vsi->uplink_seid;
5814                 ctxt.vf_num = 0;
5815                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5816                 if (ret != I40E_SUCCESS) {
5817                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5818                         goto fail_msix_alloc;
5819                 }
5820                 rte_memcpy(&vsi->info, &ctxt.info,
5821                         sizeof(struct i40e_aqc_vsi_properties_data));
5822                 vsi->vsi_id = ctxt.vsi_number;
5823                 vsi->info.valid_sections = 0;
5824
5825                 /* Configure tc, enabled TC0 only */
5826                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5827                         I40E_SUCCESS) {
5828                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5829                         goto fail_msix_alloc;
5830                 }
5831
5832                 /* TC, queue mapping */
5833                 memset(&ctxt, 0, sizeof(ctxt));
5834                 vsi->info.valid_sections |=
5835                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5836                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5837                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5838                 rte_memcpy(&ctxt.info, &vsi->info,
5839                         sizeof(struct i40e_aqc_vsi_properties_data));
5840                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5841                                                 I40E_DEFAULT_TCMAP);
5842                 if (ret != I40E_SUCCESS) {
5843                         PMD_DRV_LOG(ERR,
5844                                 "Failed to configure TC queue mapping");
5845                         goto fail_msix_alloc;
5846                 }
5847                 ctxt.seid = vsi->seid;
5848                 ctxt.pf_num = hw->pf_id;
5849                 ctxt.uplink_seid = vsi->uplink_seid;
5850                 ctxt.vf_num = 0;
5851
5852                 /* Update VSI parameters */
5853                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5854                 if (ret != I40E_SUCCESS) {
5855                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5856                         goto fail_msix_alloc;
5857                 }
5858
5859                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5860                                                 sizeof(vsi->info.tc_mapping));
5861                 rte_memcpy(&vsi->info.queue_mapping,
5862                                 &ctxt.info.queue_mapping,
5863                         sizeof(vsi->info.queue_mapping));
5864                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5865                 vsi->info.valid_sections = 0;
5866
5867                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5868                                 ETH_ADDR_LEN);
5869
5870                 /**
5871                  * Updating default filter settings are necessary to prevent
5872                  * reception of tagged packets.
5873                  * Some old firmware configurations load a default macvlan
5874                  * filter which accepts both tagged and untagged packets.
5875                  * The updating is to use a normal filter instead if needed.
5876                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5877                  * The firmware with correct configurations load the default
5878                  * macvlan filter which is expected and cannot be removed.
5879                  */
5880                 i40e_update_default_filter_setting(vsi);
5881                 i40e_config_qinq(hw, vsi);
5882         } else if (type == I40E_VSI_SRIOV) {
5883                 memset(&ctxt, 0, sizeof(ctxt));
5884                 /**
5885                  * For other VSI, the uplink_seid equals to uplink VSI's
5886                  * uplink_seid since they share same VEB
5887                  */
5888                 if (uplink_vsi == NULL)
5889                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5890                 else
5891                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5892                 ctxt.pf_num = hw->pf_id;
5893                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5894                 ctxt.uplink_seid = vsi->uplink_seid;
5895                 ctxt.connection_type = 0x1;
5896                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5897
5898                 /* Use the VEB configuration if FW >= v5.0 */
5899                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5900                         /* Configure switch ID */
5901                         ctxt.info.valid_sections |=
5902                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5903                         ctxt.info.switch_id =
5904                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5905                 }
5906
5907                 /* Configure port/vlan */
5908                 ctxt.info.valid_sections |=
5909                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5910                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5911                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5912                                                 hw->func_caps.enabled_tcmap);
5913                 if (ret != I40E_SUCCESS) {
5914                         PMD_DRV_LOG(ERR,
5915                                 "Failed to configure TC queue mapping");
5916                         goto fail_msix_alloc;
5917                 }
5918
5919                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5920                 ctxt.info.valid_sections |=
5921                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5922                 /**
5923                  * Since VSI is not created yet, only configure parameter,
5924                  * will add vsi below.
5925                  */
5926
5927                 i40e_config_qinq(hw, vsi);
5928         } else if (type == I40E_VSI_VMDQ2) {
5929                 memset(&ctxt, 0, sizeof(ctxt));
5930                 /*
5931                  * For other VSI, the uplink_seid equals to uplink VSI's
5932                  * uplink_seid since they share same VEB
5933                  */
5934                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5935                 ctxt.pf_num = hw->pf_id;
5936                 ctxt.vf_num = 0;
5937                 ctxt.uplink_seid = vsi->uplink_seid;
5938                 ctxt.connection_type = 0x1;
5939                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5940
5941                 ctxt.info.valid_sections |=
5942                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5943                 /* user_param carries flag to enable loop back */
5944                 if (user_param) {
5945                         ctxt.info.switch_id =
5946                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5947                         ctxt.info.switch_id |=
5948                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5949                 }
5950
5951                 /* Configure port/vlan */
5952                 ctxt.info.valid_sections |=
5953                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5954                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5955                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5956                                                 I40E_DEFAULT_TCMAP);
5957                 if (ret != I40E_SUCCESS) {
5958                         PMD_DRV_LOG(ERR,
5959                                 "Failed to configure TC queue mapping");
5960                         goto fail_msix_alloc;
5961                 }
5962                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5963                 ctxt.info.valid_sections |=
5964                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5965         } else if (type == I40E_VSI_FDIR) {
5966                 memset(&ctxt, 0, sizeof(ctxt));
5967                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5968                 ctxt.pf_num = hw->pf_id;
5969                 ctxt.vf_num = 0;
5970                 ctxt.uplink_seid = vsi->uplink_seid;
5971                 ctxt.connection_type = 0x1;     /* regular data port */
5972                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5973                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5974                                                 I40E_DEFAULT_TCMAP);
5975                 if (ret != I40E_SUCCESS) {
5976                         PMD_DRV_LOG(ERR,
5977                                 "Failed to configure TC queue mapping.");
5978                         goto fail_msix_alloc;
5979                 }
5980                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5981                 ctxt.info.valid_sections |=
5982                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5983         } else {
5984                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5985                 goto fail_msix_alloc;
5986         }
5987
5988         if (vsi->type != I40E_VSI_MAIN) {
5989                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5990                 if (ret != I40E_SUCCESS) {
5991                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5992                                     hw->aq.asq_last_status);
5993                         goto fail_msix_alloc;
5994                 }
5995                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5996                 vsi->info.valid_sections = 0;
5997                 vsi->seid = ctxt.seid;
5998                 vsi->vsi_id = ctxt.vsi_number;
5999                 vsi->sib_vsi_list.vsi = vsi;
6000                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6001                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6002                                           &vsi->sib_vsi_list, list);
6003                 } else {
6004                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6005                                           &vsi->sib_vsi_list, list);
6006                 }
6007         }
6008
6009         /* MAC/VLAN configuration */
6010         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6011         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
6012
6013         ret = i40e_vsi_add_mac(vsi, &filter);
6014         if (ret != I40E_SUCCESS) {
6015                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6016                 goto fail_msix_alloc;
6017         }
6018
6019         /* Get VSI BW information */
6020         i40e_vsi_get_bw_config(vsi);
6021         return vsi;
6022 fail_msix_alloc:
6023         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6024 fail_queue_alloc:
6025         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6026 fail_mem:
6027         rte_free(vsi);
6028         return NULL;
6029 }
6030
6031 /* Configure vlan filter on or off */
6032 int
6033 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6034 {
6035         int i, num;
6036         struct i40e_mac_filter *f;
6037         void *temp;
6038         struct i40e_mac_filter_info *mac_filter;
6039         enum i40e_mac_filter_type desired_filter;
6040         int ret = I40E_SUCCESS;
6041
6042         if (on) {
6043                 /* Filter to match MAC and VLAN */
6044                 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6045         } else {
6046                 /* Filter to match only MAC */
6047                 desired_filter = I40E_MAC_PERFECT_MATCH;
6048         }
6049
6050         num = vsi->mac_num;
6051
6052         mac_filter = rte_zmalloc("mac_filter_info_data",
6053                                  num * sizeof(*mac_filter), 0);
6054         if (mac_filter == NULL) {
6055                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6056                 return I40E_ERR_NO_MEMORY;
6057         }
6058
6059         i = 0;
6060
6061         /* Remove all existing mac */
6062         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6063                 mac_filter[i] = f->mac_info;
6064                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6065                 if (ret) {
6066                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6067                                     on ? "enable" : "disable");
6068                         goto DONE;
6069                 }
6070                 i++;
6071         }
6072
6073         /* Override with new filter */
6074         for (i = 0; i < num; i++) {
6075                 mac_filter[i].filter_type = desired_filter;
6076                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6077                 if (ret) {
6078                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6079                                     on ? "enable" : "disable");
6080                         goto DONE;
6081                 }
6082         }
6083
6084 DONE:
6085         rte_free(mac_filter);
6086         return ret;
6087 }
6088
6089 /* Configure vlan stripping on or off */
6090 int
6091 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6092 {
6093         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6094         struct i40e_vsi_context ctxt;
6095         uint8_t vlan_flags;
6096         int ret = I40E_SUCCESS;
6097
6098         /* Check if it has been already on or off */
6099         if (vsi->info.valid_sections &
6100                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6101                 if (on) {
6102                         if ((vsi->info.port_vlan_flags &
6103                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6104                                 return 0; /* already on */
6105                 } else {
6106                         if ((vsi->info.port_vlan_flags &
6107                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6108                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6109                                 return 0; /* already off */
6110                 }
6111         }
6112
6113         if (on)
6114                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6115         else
6116                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6117         vsi->info.valid_sections =
6118                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6119         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6120         vsi->info.port_vlan_flags |= vlan_flags;
6121         ctxt.seid = vsi->seid;
6122         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6123         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6124         if (ret)
6125                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6126                             on ? "enable" : "disable");
6127
6128         return ret;
6129 }
6130
6131 static int
6132 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6133 {
6134         struct rte_eth_dev_data *data = dev->data;
6135         int ret;
6136         int mask = 0;
6137
6138         /* Apply vlan offload setting */
6139         mask = ETH_VLAN_STRIP_MASK |
6140                ETH_QINQ_STRIP_MASK |
6141                ETH_VLAN_FILTER_MASK |
6142                ETH_VLAN_EXTEND_MASK;
6143         ret = i40e_vlan_offload_set(dev, mask);
6144         if (ret) {
6145                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6146                 return ret;
6147         }
6148
6149         /* Apply pvid setting */
6150         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6151                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6152         if (ret)
6153                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6154
6155         return ret;
6156 }
6157
6158 static int
6159 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6160 {
6161         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6162
6163         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6164 }
6165
6166 static int
6167 i40e_update_flow_control(struct i40e_hw *hw)
6168 {
6169 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6170         struct i40e_link_status link_status;
6171         uint32_t rxfc = 0, txfc = 0, reg;
6172         uint8_t an_info;
6173         int ret;
6174
6175         memset(&link_status, 0, sizeof(link_status));
6176         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6177         if (ret != I40E_SUCCESS) {
6178                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6179                 goto write_reg; /* Disable flow control */
6180         }
6181
6182         an_info = hw->phy.link_info.an_info;
6183         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6184                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6185                 ret = I40E_ERR_NOT_READY;
6186                 goto write_reg; /* Disable flow control */
6187         }
6188         /**
6189          * If link auto negotiation is enabled, flow control needs to
6190          * be configured according to it
6191          */
6192         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6193         case I40E_LINK_PAUSE_RXTX:
6194                 rxfc = 1;
6195                 txfc = 1;
6196                 hw->fc.current_mode = I40E_FC_FULL;
6197                 break;
6198         case I40E_AQ_LINK_PAUSE_RX:
6199                 rxfc = 1;
6200                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6201                 break;
6202         case I40E_AQ_LINK_PAUSE_TX:
6203                 txfc = 1;
6204                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6205                 break;
6206         default:
6207                 hw->fc.current_mode = I40E_FC_NONE;
6208                 break;
6209         }
6210
6211 write_reg:
6212         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6213                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6214         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6215         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6216         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6217         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6218
6219         return ret;
6220 }
6221
6222 /* PF setup */
6223 static int
6224 i40e_pf_setup(struct i40e_pf *pf)
6225 {
6226         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6227         struct i40e_filter_control_settings settings;
6228         struct i40e_vsi *vsi;
6229         int ret;
6230
6231         /* Clear all stats counters */
6232         pf->offset_loaded = FALSE;
6233         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6234         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6235         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6236         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6237
6238         ret = i40e_pf_get_switch_config(pf);
6239         if (ret != I40E_SUCCESS) {
6240                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6241                 return ret;
6242         }
6243
6244         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6245         if (ret)
6246                 PMD_INIT_LOG(WARNING,
6247                         "failed to allocate switch domain for device %d", ret);
6248
6249         if (pf->flags & I40E_FLAG_FDIR) {
6250                 /* make queue allocated first, let FDIR use queue pair 0*/
6251                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6252                 if (ret != I40E_FDIR_QUEUE_ID) {
6253                         PMD_DRV_LOG(ERR,
6254                                 "queue allocation fails for FDIR: ret =%d",
6255                                 ret);
6256                         pf->flags &= ~I40E_FLAG_FDIR;
6257                 }
6258         }
6259         /*  main VSI setup */
6260         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6261         if (!vsi) {
6262                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6263                 return I40E_ERR_NOT_READY;
6264         }
6265         pf->main_vsi = vsi;
6266
6267         /* Configure filter control */
6268         memset(&settings, 0, sizeof(settings));
6269         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6270                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6271         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6272                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6273         else {
6274                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6275                         hw->func_caps.rss_table_size);
6276                 return I40E_ERR_PARAM;
6277         }
6278         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6279                 hw->func_caps.rss_table_size);
6280         pf->hash_lut_size = hw->func_caps.rss_table_size;
6281
6282         /* Enable ethtype and macvlan filters */
6283         settings.enable_ethtype = TRUE;
6284         settings.enable_macvlan = TRUE;
6285         ret = i40e_set_filter_control(hw, &settings);
6286         if (ret)
6287                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6288                                                                 ret);
6289
6290         /* Update flow control according to the auto negotiation */
6291         i40e_update_flow_control(hw);
6292
6293         return I40E_SUCCESS;
6294 }
6295
6296 int
6297 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6298 {
6299         uint32_t reg;
6300         uint16_t j;
6301
6302         /**
6303          * Set or clear TX Queue Disable flags,
6304          * which is required by hardware.
6305          */
6306         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6307         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6308
6309         /* Wait until the request is finished */
6310         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6311                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6312                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6313                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6314                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6315                                                         & 0x1))) {
6316                         break;
6317                 }
6318         }
6319         if (on) {
6320                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6321                         return I40E_SUCCESS; /* already on, skip next steps */
6322
6323                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6324                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6325         } else {
6326                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6327                         return I40E_SUCCESS; /* already off, skip next steps */
6328                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6329         }
6330         /* Write the register */
6331         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6332         /* Check the result */
6333         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6334                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6335                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6336                 if (on) {
6337                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6338                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6339                                 break;
6340                 } else {
6341                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6342                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6343                                 break;
6344                 }
6345         }
6346         /* Check if it is timeout */
6347         if (j >= I40E_CHK_Q_ENA_COUNT) {
6348                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6349                             (on ? "enable" : "disable"), q_idx);
6350                 return I40E_ERR_TIMEOUT;
6351         }
6352
6353         return I40E_SUCCESS;
6354 }
6355
6356 int
6357 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6358 {
6359         uint32_t reg;
6360         uint16_t j;
6361
6362         /* Wait until the request is finished */
6363         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6364                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6365                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6366                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6367                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6368                         break;
6369         }
6370
6371         if (on) {
6372                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6373                         return I40E_SUCCESS; /* Already on, skip next steps */
6374                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6375         } else {
6376                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6377                         return I40E_SUCCESS; /* Already off, skip next steps */
6378                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6379         }
6380
6381         /* Write the register */
6382         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6383         /* Check the result */
6384         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6385                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6386                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6387                 if (on) {
6388                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6389                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6390                                 break;
6391                 } else {
6392                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6393                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6394                                 break;
6395                 }
6396         }
6397
6398         /* Check if it is timeout */
6399         if (j >= I40E_CHK_Q_ENA_COUNT) {
6400                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6401                             (on ? "enable" : "disable"), q_idx);
6402                 return I40E_ERR_TIMEOUT;
6403         }
6404
6405         return I40E_SUCCESS;
6406 }
6407
6408 /* Initialize VSI for TX */
6409 static int
6410 i40e_dev_tx_init(struct i40e_pf *pf)
6411 {
6412         struct rte_eth_dev_data *data = pf->dev_data;
6413         uint16_t i;
6414         uint32_t ret = I40E_SUCCESS;
6415         struct i40e_tx_queue *txq;
6416
6417         for (i = 0; i < data->nb_tx_queues; i++) {
6418                 txq = data->tx_queues[i];
6419                 if (!txq || !txq->q_set)
6420                         continue;
6421                 ret = i40e_tx_queue_init(txq);
6422                 if (ret != I40E_SUCCESS)
6423                         break;
6424         }
6425         if (ret == I40E_SUCCESS)
6426                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6427                                      ->eth_dev);
6428
6429         return ret;
6430 }
6431
6432 /* Initialize VSI for RX */
6433 static int
6434 i40e_dev_rx_init(struct i40e_pf *pf)
6435 {
6436         struct rte_eth_dev_data *data = pf->dev_data;
6437         int ret = I40E_SUCCESS;
6438         uint16_t i;
6439         struct i40e_rx_queue *rxq;
6440
6441         i40e_pf_config_rss(pf);
6442         for (i = 0; i < data->nb_rx_queues; i++) {
6443                 rxq = data->rx_queues[i];
6444                 if (!rxq || !rxq->q_set)
6445                         continue;
6446
6447                 ret = i40e_rx_queue_init(rxq);
6448                 if (ret != I40E_SUCCESS) {
6449                         PMD_DRV_LOG(ERR,
6450                                 "Failed to do RX queue initialization");
6451                         break;
6452                 }
6453         }
6454         if (ret == I40E_SUCCESS)
6455                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6456                                      ->eth_dev);
6457
6458         return ret;
6459 }
6460
6461 static int
6462 i40e_dev_rxtx_init(struct i40e_pf *pf)
6463 {
6464         int err;
6465
6466         err = i40e_dev_tx_init(pf);
6467         if (err) {
6468                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6469                 return err;
6470         }
6471         err = i40e_dev_rx_init(pf);
6472         if (err) {
6473                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6474                 return err;
6475         }
6476
6477         return err;
6478 }
6479
6480 static int
6481 i40e_vmdq_setup(struct rte_eth_dev *dev)
6482 {
6483         struct rte_eth_conf *conf = &dev->data->dev_conf;
6484         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6485         int i, err, conf_vsis, j, loop;
6486         struct i40e_vsi *vsi;
6487         struct i40e_vmdq_info *vmdq_info;
6488         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6489         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6490
6491         /*
6492          * Disable interrupt to avoid message from VF. Furthermore, it will
6493          * avoid race condition in VSI creation/destroy.
6494          */
6495         i40e_pf_disable_irq0(hw);
6496
6497         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6498                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6499                 return -ENOTSUP;
6500         }
6501
6502         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6503         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6504                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6505                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6506                         pf->max_nb_vmdq_vsi);
6507                 return -ENOTSUP;
6508         }
6509
6510         if (pf->vmdq != NULL) {
6511                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6512                 return 0;
6513         }
6514
6515         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6516                                 sizeof(*vmdq_info) * conf_vsis, 0);
6517
6518         if (pf->vmdq == NULL) {
6519                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6520                 return -ENOMEM;
6521         }
6522
6523         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6524
6525         /* Create VMDQ VSI */
6526         for (i = 0; i < conf_vsis; i++) {
6527                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6528                                 vmdq_conf->enable_loop_back);
6529                 if (vsi == NULL) {
6530                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6531                         err = -1;
6532                         goto err_vsi_setup;
6533                 }
6534                 vmdq_info = &pf->vmdq[i];
6535                 vmdq_info->pf = pf;
6536                 vmdq_info->vsi = vsi;
6537         }
6538         pf->nb_cfg_vmdq_vsi = conf_vsis;
6539
6540         /* Configure Vlan */
6541         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6542         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6543                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6544                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6545                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6546                                         vmdq_conf->pool_map[i].vlan_id, j);
6547
6548                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6549                                                 vmdq_conf->pool_map[i].vlan_id);
6550                                 if (err) {
6551                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6552                                         err = -1;
6553                                         goto err_vsi_setup;
6554                                 }
6555                         }
6556                 }
6557         }
6558
6559         i40e_pf_enable_irq0(hw);
6560
6561         return 0;
6562
6563 err_vsi_setup:
6564         for (i = 0; i < conf_vsis; i++)
6565                 if (pf->vmdq[i].vsi == NULL)
6566                         break;
6567                 else
6568                         i40e_vsi_release(pf->vmdq[i].vsi);
6569
6570         rte_free(pf->vmdq);
6571         pf->vmdq = NULL;
6572         i40e_pf_enable_irq0(hw);
6573         return err;
6574 }
6575
6576 static void
6577 i40e_stat_update_32(struct i40e_hw *hw,
6578                    uint32_t reg,
6579                    bool offset_loaded,
6580                    uint64_t *offset,
6581                    uint64_t *stat)
6582 {
6583         uint64_t new_data;
6584
6585         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6586         if (!offset_loaded)
6587                 *offset = new_data;
6588
6589         if (new_data >= *offset)
6590                 *stat = (uint64_t)(new_data - *offset);
6591         else
6592                 *stat = (uint64_t)((new_data +
6593                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6594 }
6595
6596 static void
6597 i40e_stat_update_48(struct i40e_hw *hw,
6598                    uint32_t hireg,
6599                    uint32_t loreg,
6600                    bool offset_loaded,
6601                    uint64_t *offset,
6602                    uint64_t *stat)
6603 {
6604         uint64_t new_data;
6605
6606         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6607         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6608                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6609
6610         if (!offset_loaded)
6611                 *offset = new_data;
6612
6613         if (new_data >= *offset)
6614                 *stat = new_data - *offset;
6615         else
6616                 *stat = (uint64_t)((new_data +
6617                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6618
6619         *stat &= I40E_48_BIT_MASK;
6620 }
6621
6622 /* Disable IRQ0 */
6623 void
6624 i40e_pf_disable_irq0(struct i40e_hw *hw)
6625 {
6626         /* Disable all interrupt types */
6627         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6628                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6629         I40E_WRITE_FLUSH(hw);
6630 }
6631
6632 /* Enable IRQ0 */
6633 void
6634 i40e_pf_enable_irq0(struct i40e_hw *hw)
6635 {
6636         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6637                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6638                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6639                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6640         I40E_WRITE_FLUSH(hw);
6641 }
6642
6643 static void
6644 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6645 {
6646         /* read pending request and disable first */
6647         i40e_pf_disable_irq0(hw);
6648         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6649         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6650                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6651
6652         if (no_queue)
6653                 /* Link no queues with irq0 */
6654                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6655                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6656 }
6657
6658 static void
6659 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6660 {
6661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6662         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6663         int i;
6664         uint16_t abs_vf_id;
6665         uint32_t index, offset, val;
6666
6667         if (!pf->vfs)
6668                 return;
6669         /**
6670          * Try to find which VF trigger a reset, use absolute VF id to access
6671          * since the reg is global register.
6672          */
6673         for (i = 0; i < pf->vf_num; i++) {
6674                 abs_vf_id = hw->func_caps.vf_base_id + i;
6675                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6676                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6677                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6678                 /* VFR event occurred */
6679                 if (val & (0x1 << offset)) {
6680                         int ret;
6681
6682                         /* Clear the event first */
6683                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6684                                                         (0x1 << offset));
6685                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6686                         /**
6687                          * Only notify a VF reset event occurred,
6688                          * don't trigger another SW reset
6689                          */
6690                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6691                         if (ret != I40E_SUCCESS)
6692                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6693                 }
6694         }
6695 }
6696
6697 static void
6698 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6699 {
6700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6701         int i;
6702
6703         for (i = 0; i < pf->vf_num; i++)
6704                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6705 }
6706
6707 static void
6708 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6709 {
6710         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6711         struct i40e_arq_event_info info;
6712         uint16_t pending, opcode;
6713         int ret;
6714
6715         info.buf_len = I40E_AQ_BUF_SZ;
6716         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6717         if (!info.msg_buf) {
6718                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6719                 return;
6720         }
6721
6722         pending = 1;
6723         while (pending) {
6724                 ret = i40e_clean_arq_element(hw, &info, &pending);
6725
6726                 if (ret != I40E_SUCCESS) {
6727                         PMD_DRV_LOG(INFO,
6728                                 "Failed to read msg from AdminQ, aq_err: %u",
6729                                 hw->aq.asq_last_status);
6730                         break;
6731                 }
6732                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6733
6734                 switch (opcode) {
6735                 case i40e_aqc_opc_send_msg_to_pf:
6736                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6737                         i40e_pf_host_handle_vf_msg(dev,
6738                                         rte_le_to_cpu_16(info.desc.retval),
6739                                         rte_le_to_cpu_32(info.desc.cookie_high),
6740                                         rte_le_to_cpu_32(info.desc.cookie_low),
6741                                         info.msg_buf,
6742                                         info.msg_len);
6743                         break;
6744                 case i40e_aqc_opc_get_link_status:
6745                         ret = i40e_dev_link_update(dev, 0);
6746                         if (!ret)
6747                                 rte_eth_dev_callback_process(dev,
6748                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6749                         break;
6750                 default:
6751                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6752                                     opcode);
6753                         break;
6754                 }
6755         }
6756         rte_free(info.msg_buf);
6757 }
6758
6759 static void
6760 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6761 {
6762 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6763 #define I40E_MDD_CLEAR16 0xFFFF
6764         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6765         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6766         bool mdd_detected = false;
6767         struct i40e_pf_vf *vf;
6768         uint32_t reg;
6769         int i;
6770
6771         /* find what triggered the MDD event */
6772         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6773         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6774                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6775                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6776                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6777                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6778                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6779                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6780                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6781                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6782                                         hw->func_caps.base_queue;
6783                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6784                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6785                                 event, queue, pf_num, vf_num, dev->data->name);
6786                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6787                 mdd_detected = true;
6788         }
6789         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6790         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6791                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6792                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6793                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6794                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6795                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6796                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6797                                         hw->func_caps.base_queue;
6798
6799                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6800                                 "queue %d of function 0x%02x device %s\n",
6801                                         event, queue, func, dev->data->name);
6802                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6803                 mdd_detected = true;
6804         }
6805
6806         if (mdd_detected) {
6807                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6808                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6809                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6810                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6811                 }
6812                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6813                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6814                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6815                                         I40E_MDD_CLEAR16);
6816                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6817                 }
6818         }
6819
6820         /* see if one of the VFs needs its hand slapped */
6821         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6822                 vf = &pf->vfs[i];
6823                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6824                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6825                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6826                                         I40E_MDD_CLEAR16);
6827                         vf->num_mdd_events++;
6828                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6829                                         PRIu64 "times\n",
6830                                         i, vf->num_mdd_events);
6831                 }
6832
6833                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6834                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6835                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6836                                         I40E_MDD_CLEAR16);
6837                         vf->num_mdd_events++;
6838                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6839                                         PRIu64 "times\n",
6840                                         i, vf->num_mdd_events);
6841                 }
6842         }
6843 }
6844
6845 /**
6846  * Interrupt handler triggered by NIC  for handling
6847  * specific interrupt.
6848  *
6849  * @param handle
6850  *  Pointer to interrupt handle.
6851  * @param param
6852  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6853  *
6854  * @return
6855  *  void
6856  */
6857 static void
6858 i40e_dev_interrupt_handler(void *param)
6859 {
6860         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6862         uint32_t icr0;
6863
6864         /* Disable interrupt */
6865         i40e_pf_disable_irq0(hw);
6866
6867         /* read out interrupt causes */
6868         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6869
6870         /* No interrupt event indicated */
6871         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6872                 PMD_DRV_LOG(INFO, "No interrupt event");
6873                 goto done;
6874         }
6875         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6876                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6877         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6878                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6879                 i40e_handle_mdd_event(dev);
6880         }
6881         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6882                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6883         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6884                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6885         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6886                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6887         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6888                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6889         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6890                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6891
6892         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6893                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6894                 i40e_dev_handle_vfr_event(dev);
6895         }
6896         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6897                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6898                 i40e_dev_handle_aq_msg(dev);
6899         }
6900
6901 done:
6902         /* Enable interrupt */
6903         i40e_pf_enable_irq0(hw);
6904 }
6905
6906 static void
6907 i40e_dev_alarm_handler(void *param)
6908 {
6909         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6911         uint32_t icr0;
6912
6913         /* Disable interrupt */
6914         i40e_pf_disable_irq0(hw);
6915
6916         /* read out interrupt causes */
6917         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6918
6919         /* No interrupt event indicated */
6920         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6921                 goto done;
6922         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6923                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6924         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6925                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6926                 i40e_handle_mdd_event(dev);
6927         }
6928         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6929                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6930         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6931                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6932         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6933                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6934         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6935                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6936         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6937                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6938
6939         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6940                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6941                 i40e_dev_handle_vfr_event(dev);
6942         }
6943         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6944                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6945                 i40e_dev_handle_aq_msg(dev);
6946         }
6947
6948 done:
6949         /* Enable interrupt */
6950         i40e_pf_enable_irq0(hw);
6951         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6952                           i40e_dev_alarm_handler, dev);
6953 }
6954
6955 int
6956 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6957                          struct i40e_macvlan_filter *filter,
6958                          int total)
6959 {
6960         int ele_num, ele_buff_size;
6961         int num, actual_num, i;
6962         uint16_t flags;
6963         int ret = I40E_SUCCESS;
6964         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6965         struct i40e_aqc_add_macvlan_element_data *req_list;
6966
6967         if (filter == NULL  || total == 0)
6968                 return I40E_ERR_PARAM;
6969         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6970         ele_buff_size = hw->aq.asq_buf_size;
6971
6972         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6973         if (req_list == NULL) {
6974                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6975                 return I40E_ERR_NO_MEMORY;
6976         }
6977
6978         num = 0;
6979         do {
6980                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6981                 memset(req_list, 0, ele_buff_size);
6982
6983                 for (i = 0; i < actual_num; i++) {
6984                         rte_memcpy(req_list[i].mac_addr,
6985                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6986                         req_list[i].vlan_tag =
6987                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6988
6989                         switch (filter[num + i].filter_type) {
6990                         case I40E_MAC_PERFECT_MATCH:
6991                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6992                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6993                                 break;
6994                         case I40E_MACVLAN_PERFECT_MATCH:
6995                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6996                                 break;
6997                         case I40E_MAC_HASH_MATCH:
6998                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6999                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7000                                 break;
7001                         case I40E_MACVLAN_HASH_MATCH:
7002                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7003                                 break;
7004                         default:
7005                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7006                                 ret = I40E_ERR_PARAM;
7007                                 goto DONE;
7008                         }
7009
7010                         req_list[i].queue_number = 0;
7011
7012                         req_list[i].flags = rte_cpu_to_le_16(flags);
7013                 }
7014
7015                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7016                                                 actual_num, NULL);
7017                 if (ret != I40E_SUCCESS) {
7018                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7019                         goto DONE;
7020                 }
7021                 num += actual_num;
7022         } while (num < total);
7023
7024 DONE:
7025         rte_free(req_list);
7026         return ret;
7027 }
7028
7029 int
7030 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7031                             struct i40e_macvlan_filter *filter,
7032                             int total)
7033 {
7034         int ele_num, ele_buff_size;
7035         int num, actual_num, i;
7036         uint16_t flags;
7037         int ret = I40E_SUCCESS;
7038         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7039         struct i40e_aqc_remove_macvlan_element_data *req_list;
7040
7041         if (filter == NULL  || total == 0)
7042                 return I40E_ERR_PARAM;
7043
7044         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7045         ele_buff_size = hw->aq.asq_buf_size;
7046
7047         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7048         if (req_list == NULL) {
7049                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7050                 return I40E_ERR_NO_MEMORY;
7051         }
7052
7053         num = 0;
7054         do {
7055                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7056                 memset(req_list, 0, ele_buff_size);
7057
7058                 for (i = 0; i < actual_num; i++) {
7059                         rte_memcpy(req_list[i].mac_addr,
7060                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7061                         req_list[i].vlan_tag =
7062                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7063
7064                         switch (filter[num + i].filter_type) {
7065                         case I40E_MAC_PERFECT_MATCH:
7066                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7067                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7068                                 break;
7069                         case I40E_MACVLAN_PERFECT_MATCH:
7070                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7071                                 break;
7072                         case I40E_MAC_HASH_MATCH:
7073                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7074                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7075                                 break;
7076                         case I40E_MACVLAN_HASH_MATCH:
7077                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7078                                 break;
7079                         default:
7080                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7081                                 ret = I40E_ERR_PARAM;
7082                                 goto DONE;
7083                         }
7084                         req_list[i].flags = rte_cpu_to_le_16(flags);
7085                 }
7086
7087                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7088                                                 actual_num, NULL);
7089                 if (ret != I40E_SUCCESS) {
7090                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7091                         goto DONE;
7092                 }
7093                 num += actual_num;
7094         } while (num < total);
7095
7096 DONE:
7097         rte_free(req_list);
7098         return ret;
7099 }
7100
7101 /* Find out specific MAC filter */
7102 static struct i40e_mac_filter *
7103 i40e_find_mac_filter(struct i40e_vsi *vsi,
7104                          struct rte_ether_addr *macaddr)
7105 {
7106         struct i40e_mac_filter *f;
7107
7108         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7109                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7110                         return f;
7111         }
7112
7113         return NULL;
7114 }
7115
7116 static bool
7117 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7118                          uint16_t vlan_id)
7119 {
7120         uint32_t vid_idx, vid_bit;
7121
7122         if (vlan_id > ETH_VLAN_ID_MAX)
7123                 return 0;
7124
7125         vid_idx = I40E_VFTA_IDX(vlan_id);
7126         vid_bit = I40E_VFTA_BIT(vlan_id);
7127
7128         if (vsi->vfta[vid_idx] & vid_bit)
7129                 return 1;
7130         else
7131                 return 0;
7132 }
7133
7134 static void
7135 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7136                        uint16_t vlan_id, bool on)
7137 {
7138         uint32_t vid_idx, vid_bit;
7139
7140         vid_idx = I40E_VFTA_IDX(vlan_id);
7141         vid_bit = I40E_VFTA_BIT(vlan_id);
7142
7143         if (on)
7144                 vsi->vfta[vid_idx] |= vid_bit;
7145         else
7146                 vsi->vfta[vid_idx] &= ~vid_bit;
7147 }
7148
7149 void
7150 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7151                      uint16_t vlan_id, bool on)
7152 {
7153         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7154         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7155         int ret;
7156
7157         if (vlan_id > ETH_VLAN_ID_MAX)
7158                 return;
7159
7160         i40e_store_vlan_filter(vsi, vlan_id, on);
7161
7162         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7163                 return;
7164
7165         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7166
7167         if (on) {
7168                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7169                                        &vlan_data, 1, NULL);
7170                 if (ret != I40E_SUCCESS)
7171                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7172         } else {
7173                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7174                                           &vlan_data, 1, NULL);
7175                 if (ret != I40E_SUCCESS)
7176                         PMD_DRV_LOG(ERR,
7177                                     "Failed to remove vlan filter");
7178         }
7179 }
7180
7181 /**
7182  * Find all vlan options for specific mac addr,
7183  * return with actual vlan found.
7184  */
7185 int
7186 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7187                            struct i40e_macvlan_filter *mv_f,
7188                            int num, struct rte_ether_addr *addr)
7189 {
7190         int i;
7191         uint32_t j, k;
7192
7193         /**
7194          * Not to use i40e_find_vlan_filter to decrease the loop time,
7195          * although the code looks complex.
7196           */
7197         if (num < vsi->vlan_num)
7198                 return I40E_ERR_PARAM;
7199
7200         i = 0;
7201         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7202                 if (vsi->vfta[j]) {
7203                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7204                                 if (vsi->vfta[j] & (1 << k)) {
7205                                         if (i > num - 1) {
7206                                                 PMD_DRV_LOG(ERR,
7207                                                         "vlan number doesn't match");
7208                                                 return I40E_ERR_PARAM;
7209                                         }
7210                                         rte_memcpy(&mv_f[i].macaddr,
7211                                                         addr, ETH_ADDR_LEN);
7212                                         mv_f[i].vlan_id =
7213                                                 j * I40E_UINT32_BIT_SIZE + k;
7214                                         i++;
7215                                 }
7216                         }
7217                 }
7218         }
7219         return I40E_SUCCESS;
7220 }
7221
7222 static inline int
7223 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7224                            struct i40e_macvlan_filter *mv_f,
7225                            int num,
7226                            uint16_t vlan)
7227 {
7228         int i = 0;
7229         struct i40e_mac_filter *f;
7230
7231         if (num < vsi->mac_num)
7232                 return I40E_ERR_PARAM;
7233
7234         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7235                 if (i > num - 1) {
7236                         PMD_DRV_LOG(ERR, "buffer number not match");
7237                         return I40E_ERR_PARAM;
7238                 }
7239                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7240                                 ETH_ADDR_LEN);
7241                 mv_f[i].vlan_id = vlan;
7242                 mv_f[i].filter_type = f->mac_info.filter_type;
7243                 i++;
7244         }
7245
7246         return I40E_SUCCESS;
7247 }
7248
7249 static int
7250 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7251 {
7252         int i, j, num;
7253         struct i40e_mac_filter *f;
7254         struct i40e_macvlan_filter *mv_f;
7255         int ret = I40E_SUCCESS;
7256
7257         if (vsi == NULL || vsi->mac_num == 0)
7258                 return I40E_ERR_PARAM;
7259
7260         /* Case that no vlan is set */
7261         if (vsi->vlan_num == 0)
7262                 num = vsi->mac_num;
7263         else
7264                 num = vsi->mac_num * vsi->vlan_num;
7265
7266         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7267         if (mv_f == NULL) {
7268                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7269                 return I40E_ERR_NO_MEMORY;
7270         }
7271
7272         i = 0;
7273         if (vsi->vlan_num == 0) {
7274                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7275                         rte_memcpy(&mv_f[i].macaddr,
7276                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7277                         mv_f[i].filter_type = f->mac_info.filter_type;
7278                         mv_f[i].vlan_id = 0;
7279                         i++;
7280                 }
7281         } else {
7282                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7283                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7284                                         vsi->vlan_num, &f->mac_info.mac_addr);
7285                         if (ret != I40E_SUCCESS)
7286                                 goto DONE;
7287                         for (j = i; j < i + vsi->vlan_num; j++)
7288                                 mv_f[j].filter_type = f->mac_info.filter_type;
7289                         i += vsi->vlan_num;
7290                 }
7291         }
7292
7293         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7294 DONE:
7295         rte_free(mv_f);
7296
7297         return ret;
7298 }
7299
7300 int
7301 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7302 {
7303         struct i40e_macvlan_filter *mv_f;
7304         int mac_num;
7305         int ret = I40E_SUCCESS;
7306
7307         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7308                 return I40E_ERR_PARAM;
7309
7310         /* If it's already set, just return */
7311         if (i40e_find_vlan_filter(vsi,vlan))
7312                 return I40E_SUCCESS;
7313
7314         mac_num = vsi->mac_num;
7315
7316         if (mac_num == 0) {
7317                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7318                 return I40E_ERR_PARAM;
7319         }
7320
7321         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7322
7323         if (mv_f == NULL) {
7324                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7325                 return I40E_ERR_NO_MEMORY;
7326         }
7327
7328         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7329
7330         if (ret != I40E_SUCCESS)
7331                 goto DONE;
7332
7333         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7334
7335         if (ret != I40E_SUCCESS)
7336                 goto DONE;
7337
7338         i40e_set_vlan_filter(vsi, vlan, 1);
7339
7340         vsi->vlan_num++;
7341         ret = I40E_SUCCESS;
7342 DONE:
7343         rte_free(mv_f);
7344         return ret;
7345 }
7346
7347 int
7348 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7349 {
7350         struct i40e_macvlan_filter *mv_f;
7351         int mac_num;
7352         int ret = I40E_SUCCESS;
7353
7354         /**
7355          * Vlan 0 is the generic filter for untagged packets
7356          * and can't be removed.
7357          */
7358         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7359                 return I40E_ERR_PARAM;
7360
7361         /* If can't find it, just return */
7362         if (!i40e_find_vlan_filter(vsi, vlan))
7363                 return I40E_ERR_PARAM;
7364
7365         mac_num = vsi->mac_num;
7366
7367         if (mac_num == 0) {
7368                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7369                 return I40E_ERR_PARAM;
7370         }
7371
7372         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7373
7374         if (mv_f == NULL) {
7375                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7376                 return I40E_ERR_NO_MEMORY;
7377         }
7378
7379         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7380
7381         if (ret != I40E_SUCCESS)
7382                 goto DONE;
7383
7384         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7385
7386         if (ret != I40E_SUCCESS)
7387                 goto DONE;
7388
7389         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7390         if (vsi->vlan_num == 1) {
7391                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7392                 if (ret != I40E_SUCCESS)
7393                         goto DONE;
7394
7395                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7396                 if (ret != I40E_SUCCESS)
7397                         goto DONE;
7398         }
7399
7400         i40e_set_vlan_filter(vsi, vlan, 0);
7401
7402         vsi->vlan_num--;
7403         ret = I40E_SUCCESS;
7404 DONE:
7405         rte_free(mv_f);
7406         return ret;
7407 }
7408
7409 int
7410 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7411 {
7412         struct i40e_mac_filter *f;
7413         struct i40e_macvlan_filter *mv_f;
7414         int i, vlan_num = 0;
7415         int ret = I40E_SUCCESS;
7416
7417         /* If it's add and we've config it, return */
7418         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7419         if (f != NULL)
7420                 return I40E_SUCCESS;
7421         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7422                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7423
7424                 /**
7425                  * If vlan_num is 0, that's the first time to add mac,
7426                  * set mask for vlan_id 0.
7427                  */
7428                 if (vsi->vlan_num == 0) {
7429                         i40e_set_vlan_filter(vsi, 0, 1);
7430                         vsi->vlan_num = 1;
7431                 }
7432                 vlan_num = vsi->vlan_num;
7433         } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7434                         mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7435                 vlan_num = 1;
7436
7437         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7438         if (mv_f == NULL) {
7439                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7440                 return I40E_ERR_NO_MEMORY;
7441         }
7442
7443         for (i = 0; i < vlan_num; i++) {
7444                 mv_f[i].filter_type = mac_filter->filter_type;
7445                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7446                                 ETH_ADDR_LEN);
7447         }
7448
7449         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7450                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7451                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7452                                         &mac_filter->mac_addr);
7453                 if (ret != I40E_SUCCESS)
7454                         goto DONE;
7455         }
7456
7457         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7458         if (ret != I40E_SUCCESS)
7459                 goto DONE;
7460
7461         /* Add the mac addr into mac list */
7462         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7463         if (f == NULL) {
7464                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7465                 ret = I40E_ERR_NO_MEMORY;
7466                 goto DONE;
7467         }
7468         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7469                         ETH_ADDR_LEN);
7470         f->mac_info.filter_type = mac_filter->filter_type;
7471         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7472         vsi->mac_num++;
7473
7474         ret = I40E_SUCCESS;
7475 DONE:
7476         rte_free(mv_f);
7477
7478         return ret;
7479 }
7480
7481 int
7482 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7483 {
7484         struct i40e_mac_filter *f;
7485         struct i40e_macvlan_filter *mv_f;
7486         int i, vlan_num;
7487         enum i40e_mac_filter_type filter_type;
7488         int ret = I40E_SUCCESS;
7489
7490         /* Can't find it, return an error */
7491         f = i40e_find_mac_filter(vsi, addr);
7492         if (f == NULL)
7493                 return I40E_ERR_PARAM;
7494
7495         vlan_num = vsi->vlan_num;
7496         filter_type = f->mac_info.filter_type;
7497         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7498                 filter_type == I40E_MACVLAN_HASH_MATCH) {
7499                 if (vlan_num == 0) {
7500                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7501                         return I40E_ERR_PARAM;
7502                 }
7503         } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7504                         filter_type == I40E_MAC_HASH_MATCH)
7505                 vlan_num = 1;
7506
7507         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7508         if (mv_f == NULL) {
7509                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7510                 return I40E_ERR_NO_MEMORY;
7511         }
7512
7513         for (i = 0; i < vlan_num; i++) {
7514                 mv_f[i].filter_type = filter_type;
7515                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7516                                 ETH_ADDR_LEN);
7517         }
7518         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7519                         filter_type == I40E_MACVLAN_HASH_MATCH) {
7520                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7521                 if (ret != I40E_SUCCESS)
7522                         goto DONE;
7523         }
7524
7525         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7526         if (ret != I40E_SUCCESS)
7527                 goto DONE;
7528
7529         /* Remove the mac addr into mac list */
7530         TAILQ_REMOVE(&vsi->mac_list, f, next);
7531         rte_free(f);
7532         vsi->mac_num--;
7533
7534         ret = I40E_SUCCESS;
7535 DONE:
7536         rte_free(mv_f);
7537         return ret;
7538 }
7539
7540 /* Configure hash enable flags for RSS */
7541 uint64_t
7542 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7543 {
7544         uint64_t hena = 0;
7545         int i;
7546
7547         if (!flags)
7548                 return hena;
7549
7550         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7551                 if (flags & (1ULL << i))
7552                         hena |= adapter->pctypes_tbl[i];
7553         }
7554
7555         return hena;
7556 }
7557
7558 /* Parse the hash enable flags */
7559 uint64_t
7560 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7561 {
7562         uint64_t rss_hf = 0;
7563
7564         if (!flags)
7565                 return rss_hf;
7566         int i;
7567
7568         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7569                 if (flags & adapter->pctypes_tbl[i])
7570                         rss_hf |= (1ULL << i);
7571         }
7572         return rss_hf;
7573 }
7574
7575 /* Disable RSS */
7576 static void
7577 i40e_pf_disable_rss(struct i40e_pf *pf)
7578 {
7579         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7580
7581         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7582         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7583         I40E_WRITE_FLUSH(hw);
7584 }
7585
7586 int
7587 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7588 {
7589         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7590         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7591         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7592                            I40E_VFQF_HKEY_MAX_INDEX :
7593                            I40E_PFQF_HKEY_MAX_INDEX;
7594         int ret = 0;
7595
7596         if (!key || key_len == 0) {
7597                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7598                 return 0;
7599         } else if (key_len != (key_idx + 1) *
7600                 sizeof(uint32_t)) {
7601                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7602                 return -EINVAL;
7603         }
7604
7605         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7606                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7607                         (struct i40e_aqc_get_set_rss_key_data *)key;
7608
7609                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7610                 if (ret)
7611                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7612         } else {
7613                 uint32_t *hash_key = (uint32_t *)key;
7614                 uint16_t i;
7615
7616                 if (vsi->type == I40E_VSI_SRIOV) {
7617                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7618                                 I40E_WRITE_REG(
7619                                         hw,
7620                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7621                                         hash_key[i]);
7622
7623                 } else {
7624                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7625                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7626                                                hash_key[i]);
7627                 }
7628                 I40E_WRITE_FLUSH(hw);
7629         }
7630
7631         return ret;
7632 }
7633
7634 static int
7635 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7636 {
7637         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7638         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7639         uint32_t reg;
7640         int ret;
7641
7642         if (!key || !key_len)
7643                 return 0;
7644
7645         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7646                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7647                         (struct i40e_aqc_get_set_rss_key_data *)key);
7648                 if (ret) {
7649                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7650                         return ret;
7651                 }
7652         } else {
7653                 uint32_t *key_dw = (uint32_t *)key;
7654                 uint16_t i;
7655
7656                 if (vsi->type == I40E_VSI_SRIOV) {
7657                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7658                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7659                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7660                         }
7661                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7662                                    sizeof(uint32_t);
7663                 } else {
7664                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7665                                 reg = I40E_PFQF_HKEY(i);
7666                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7667                         }
7668                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7669                                    sizeof(uint32_t);
7670                 }
7671         }
7672         return 0;
7673 }
7674
7675 static int
7676 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7677 {
7678         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7679         uint64_t hena;
7680         int ret;
7681
7682         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7683                                rss_conf->rss_key_len);
7684         if (ret)
7685                 return ret;
7686
7687         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7688         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7689         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7690         I40E_WRITE_FLUSH(hw);
7691
7692         return 0;
7693 }
7694
7695 static int
7696 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7697                          struct rte_eth_rss_conf *rss_conf)
7698 {
7699         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7700         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7701         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7702         uint64_t hena;
7703
7704         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7705         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7706
7707         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7708                 if (rss_hf != 0) /* Enable RSS */
7709                         return -EINVAL;
7710                 return 0; /* Nothing to do */
7711         }
7712         /* RSS enabled */
7713         if (rss_hf == 0) /* Disable RSS */
7714                 return -EINVAL;
7715
7716         return i40e_hw_rss_hash_set(pf, rss_conf);
7717 }
7718
7719 static int
7720 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7721                            struct rte_eth_rss_conf *rss_conf)
7722 {
7723         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7724         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7725         uint64_t hena;
7726         int ret;
7727
7728         if (!rss_conf)
7729                 return -EINVAL;
7730
7731         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7732                          &rss_conf->rss_key_len);
7733         if (ret)
7734                 return ret;
7735
7736         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7737         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7738         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7739
7740         return 0;
7741 }
7742
7743 static int
7744 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7745 {
7746         switch (filter_type) {
7747         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7748                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7749                 break;
7750         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7751                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7752                 break;
7753         case RTE_TUNNEL_FILTER_IMAC_TENID:
7754                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7755                 break;
7756         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7757                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7758                 break;
7759         case ETH_TUNNEL_FILTER_IMAC:
7760                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7761                 break;
7762         case ETH_TUNNEL_FILTER_OIP:
7763                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7764                 break;
7765         case ETH_TUNNEL_FILTER_IIP:
7766                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7767                 break;
7768         default:
7769                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7770                 return -EINVAL;
7771         }
7772
7773         return 0;
7774 }
7775
7776 /* Convert tunnel filter structure */
7777 static int
7778 i40e_tunnel_filter_convert(
7779         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7780         struct i40e_tunnel_filter *tunnel_filter)
7781 {
7782         rte_ether_addr_copy((struct rte_ether_addr *)
7783                         &cld_filter->element.outer_mac,
7784                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7785         rte_ether_addr_copy((struct rte_ether_addr *)
7786                         &cld_filter->element.inner_mac,
7787                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7788         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7789         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7790              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7791             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7792                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7793         else
7794                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7795         tunnel_filter->input.flags = cld_filter->element.flags;
7796         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7797         tunnel_filter->queue = cld_filter->element.queue_number;
7798         rte_memcpy(tunnel_filter->input.general_fields,
7799                    cld_filter->general_fields,
7800                    sizeof(cld_filter->general_fields));
7801
7802         return 0;
7803 }
7804
7805 /* Check if there exists the tunnel filter */
7806 struct i40e_tunnel_filter *
7807 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7808                              const struct i40e_tunnel_filter_input *input)
7809 {
7810         int ret;
7811
7812         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7813         if (ret < 0)
7814                 return NULL;
7815
7816         return tunnel_rule->hash_map[ret];
7817 }
7818
7819 /* Add a tunnel filter into the SW list */
7820 static int
7821 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7822                              struct i40e_tunnel_filter *tunnel_filter)
7823 {
7824         struct i40e_tunnel_rule *rule = &pf->tunnel;
7825         int ret;
7826
7827         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7828         if (ret < 0) {
7829                 PMD_DRV_LOG(ERR,
7830                             "Failed to insert tunnel filter to hash table %d!",
7831                             ret);
7832                 return ret;
7833         }
7834         rule->hash_map[ret] = tunnel_filter;
7835
7836         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7837
7838         return 0;
7839 }
7840
7841 /* Delete a tunnel filter from the SW list */
7842 int
7843 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7844                           struct i40e_tunnel_filter_input *input)
7845 {
7846         struct i40e_tunnel_rule *rule = &pf->tunnel;
7847         struct i40e_tunnel_filter *tunnel_filter;
7848         int ret;
7849
7850         ret = rte_hash_del_key(rule->hash_table, input);
7851         if (ret < 0) {
7852                 PMD_DRV_LOG(ERR,
7853                             "Failed to delete tunnel filter to hash table %d!",
7854                             ret);
7855                 return ret;
7856         }
7857         tunnel_filter = rule->hash_map[ret];
7858         rule->hash_map[ret] = NULL;
7859
7860         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7861         rte_free(tunnel_filter);
7862
7863         return 0;
7864 }
7865
7866 int
7867 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7868                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7869                         uint8_t add)
7870 {
7871         uint16_t ip_type;
7872         uint32_t ipv4_addr, ipv4_addr_le;
7873         uint8_t i, tun_type = 0;
7874         /* internal varialbe to convert ipv6 byte order */
7875         uint32_t convert_ipv6[4];
7876         int val, ret = 0;
7877         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7878         struct i40e_vsi *vsi = pf->main_vsi;
7879         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7880         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7881         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7882         struct i40e_tunnel_filter *tunnel, *node;
7883         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7884
7885         cld_filter = rte_zmalloc("tunnel_filter",
7886                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7887         0);
7888
7889         if (NULL == cld_filter) {
7890                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7891                 return -ENOMEM;
7892         }
7893         pfilter = cld_filter;
7894
7895         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7896                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7897         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7898                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7899
7900         pfilter->element.inner_vlan =
7901                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7902         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7903                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7904                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7905                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7906                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7907                                 &ipv4_addr_le,
7908                                 sizeof(pfilter->element.ipaddr.v4.data));
7909         } else {
7910                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7911                 for (i = 0; i < 4; i++) {
7912                         convert_ipv6[i] =
7913                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7914                 }
7915                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7916                            &convert_ipv6,
7917                            sizeof(pfilter->element.ipaddr.v6.data));
7918         }
7919
7920         /* check tunneled type */
7921         switch (tunnel_filter->tunnel_type) {
7922         case RTE_TUNNEL_TYPE_VXLAN:
7923                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7924                 break;
7925         case RTE_TUNNEL_TYPE_NVGRE:
7926                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7927                 break;
7928         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7929                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7930                 break;
7931         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7932                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7933                 break;
7934         default:
7935                 /* Other tunnel types is not supported. */
7936                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7937                 rte_free(cld_filter);
7938                 return -EINVAL;
7939         }
7940
7941         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7942                                        &pfilter->element.flags);
7943         if (val < 0) {
7944                 rte_free(cld_filter);
7945                 return -EINVAL;
7946         }
7947
7948         pfilter->element.flags |= rte_cpu_to_le_16(
7949                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7950                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7951         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7952         pfilter->element.queue_number =
7953                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7954
7955         /* Check if there is the filter in SW list */
7956         memset(&check_filter, 0, sizeof(check_filter));
7957         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7958         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7959         if (add && node) {
7960                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7961                 rte_free(cld_filter);
7962                 return -EINVAL;
7963         }
7964
7965         if (!add && !node) {
7966                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7967                 rte_free(cld_filter);
7968                 return -EINVAL;
7969         }
7970
7971         if (add) {
7972                 ret = i40e_aq_add_cloud_filters(hw,
7973                                         vsi->seid, &cld_filter->element, 1);
7974                 if (ret < 0) {
7975                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7976                         rte_free(cld_filter);
7977                         return -ENOTSUP;
7978                 }
7979                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7980                 if (tunnel == NULL) {
7981                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7982                         rte_free(cld_filter);
7983                         return -ENOMEM;
7984                 }
7985
7986                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7987                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7988                 if (ret < 0)
7989                         rte_free(tunnel);
7990         } else {
7991                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7992                                                    &cld_filter->element, 1);
7993                 if (ret < 0) {
7994                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7995                         rte_free(cld_filter);
7996                         return -ENOTSUP;
7997                 }
7998                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7999         }
8000
8001         rte_free(cld_filter);
8002         return ret;
8003 }
8004
8005 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8006 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
8007 #define I40E_TR_GENEVE_KEY_MASK                 0x8
8008 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
8009 #define I40E_TR_GRE_KEY_MASK                    0x400
8010 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
8011 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
8012 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8013 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8014 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8015 #define I40E_DIRECTION_INGRESS_KEY              0x8000
8016 #define I40E_TR_L4_TYPE_TCP                     0x2
8017 #define I40E_TR_L4_TYPE_UDP                     0x4
8018 #define I40E_TR_L4_TYPE_SCTP                    0x8
8019
8020 static enum
8021 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8022 {
8023         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8024         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8025         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8026         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8027         enum i40e_status_code status = I40E_SUCCESS;
8028
8029         if (pf->support_multi_driver) {
8030                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8031                 return I40E_NOT_SUPPORTED;
8032         }
8033
8034         memset(&filter_replace, 0,
8035                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8036         memset(&filter_replace_buf, 0,
8037                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8038
8039         /* create L1 filter */
8040         filter_replace.old_filter_type =
8041                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8042         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8043         filter_replace.tr_bit = 0;
8044
8045         /* Prepare the buffer, 3 entries */
8046         filter_replace_buf.data[0] =
8047                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8048         filter_replace_buf.data[0] |=
8049                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8050         filter_replace_buf.data[2] = 0xFF;
8051         filter_replace_buf.data[3] = 0xFF;
8052         filter_replace_buf.data[4] =
8053                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8054         filter_replace_buf.data[4] |=
8055                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8056         filter_replace_buf.data[7] = 0xF0;
8057         filter_replace_buf.data[8]
8058                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8059         filter_replace_buf.data[8] |=
8060                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8061         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8062                 I40E_TR_GENEVE_KEY_MASK |
8063                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8064         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8065                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8066                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8067
8068         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8069                                                &filter_replace_buf);
8070         if (!status && (filter_replace.old_filter_type !=
8071                         filter_replace.new_filter_type))
8072                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8073                             " original: 0x%x, new: 0x%x",
8074                             dev->device->name,
8075                             filter_replace.old_filter_type,
8076                             filter_replace.new_filter_type);
8077
8078         return status;
8079 }
8080
8081 static enum
8082 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8083 {
8084         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8085         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8086         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8087         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8088         enum i40e_status_code status = I40E_SUCCESS;
8089
8090         if (pf->support_multi_driver) {
8091                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8092                 return I40E_NOT_SUPPORTED;
8093         }
8094
8095         /* For MPLSoUDP */
8096         memset(&filter_replace, 0,
8097                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8098         memset(&filter_replace_buf, 0,
8099                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8100         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8101                 I40E_AQC_MIRROR_CLOUD_FILTER;
8102         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8103         filter_replace.new_filter_type =
8104                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8105         /* Prepare the buffer, 2 entries */
8106         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8107         filter_replace_buf.data[0] |=
8108                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8109         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8110         filter_replace_buf.data[4] |=
8111                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8112         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8113                                                &filter_replace_buf);
8114         if (status < 0)
8115                 return status;
8116         if (filter_replace.old_filter_type !=
8117             filter_replace.new_filter_type)
8118                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8119                             " original: 0x%x, new: 0x%x",
8120                             dev->device->name,
8121                             filter_replace.old_filter_type,
8122                             filter_replace.new_filter_type);
8123
8124         /* For MPLSoGRE */
8125         memset(&filter_replace, 0,
8126                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8127         memset(&filter_replace_buf, 0,
8128                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8129
8130         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8131                 I40E_AQC_MIRROR_CLOUD_FILTER;
8132         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8133         filter_replace.new_filter_type =
8134                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8135         /* Prepare the buffer, 2 entries */
8136         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8137         filter_replace_buf.data[0] |=
8138                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8139         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8140         filter_replace_buf.data[4] |=
8141                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8142
8143         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8144                                                &filter_replace_buf);
8145         if (!status && (filter_replace.old_filter_type !=
8146                         filter_replace.new_filter_type))
8147                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8148                             " original: 0x%x, new: 0x%x",
8149                             dev->device->name,
8150                             filter_replace.old_filter_type,
8151                             filter_replace.new_filter_type);
8152
8153         return status;
8154 }
8155
8156 static enum i40e_status_code
8157 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8158 {
8159         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8160         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8161         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8162         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8163         enum i40e_status_code status = I40E_SUCCESS;
8164
8165         if (pf->support_multi_driver) {
8166                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8167                 return I40E_NOT_SUPPORTED;
8168         }
8169
8170         /* For GTP-C */
8171         memset(&filter_replace, 0,
8172                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8173         memset(&filter_replace_buf, 0,
8174                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8175         /* create L1 filter */
8176         filter_replace.old_filter_type =
8177                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8178         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8179         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8180                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8181         /* Prepare the buffer, 2 entries */
8182         filter_replace_buf.data[0] =
8183                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8184         filter_replace_buf.data[0] |=
8185                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8186         filter_replace_buf.data[2] = 0xFF;
8187         filter_replace_buf.data[3] = 0xFF;
8188         filter_replace_buf.data[4] =
8189                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8190         filter_replace_buf.data[4] |=
8191                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8192         filter_replace_buf.data[6] = 0xFF;
8193         filter_replace_buf.data[7] = 0xFF;
8194         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8195                                                &filter_replace_buf);
8196         if (status < 0)
8197                 return status;
8198         if (filter_replace.old_filter_type !=
8199             filter_replace.new_filter_type)
8200                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8201                             " original: 0x%x, new: 0x%x",
8202                             dev->device->name,
8203                             filter_replace.old_filter_type,
8204                             filter_replace.new_filter_type);
8205
8206         /* for GTP-U */
8207         memset(&filter_replace, 0,
8208                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8209         memset(&filter_replace_buf, 0,
8210                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8211         /* create L1 filter */
8212         filter_replace.old_filter_type =
8213                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8214         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8215         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8216                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8217         /* Prepare the buffer, 2 entries */
8218         filter_replace_buf.data[0] =
8219                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8220         filter_replace_buf.data[0] |=
8221                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8222         filter_replace_buf.data[2] = 0xFF;
8223         filter_replace_buf.data[3] = 0xFF;
8224         filter_replace_buf.data[4] =
8225                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8226         filter_replace_buf.data[4] |=
8227                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8228         filter_replace_buf.data[6] = 0xFF;
8229         filter_replace_buf.data[7] = 0xFF;
8230
8231         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8232                                                &filter_replace_buf);
8233         if (!status && (filter_replace.old_filter_type !=
8234                         filter_replace.new_filter_type))
8235                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8236                             " original: 0x%x, new: 0x%x",
8237                             dev->device->name,
8238                             filter_replace.old_filter_type,
8239                             filter_replace.new_filter_type);
8240
8241         return status;
8242 }
8243
8244 static enum
8245 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8246 {
8247         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8248         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8249         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8250         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8251         enum i40e_status_code status = I40E_SUCCESS;
8252
8253         if (pf->support_multi_driver) {
8254                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8255                 return I40E_NOT_SUPPORTED;
8256         }
8257
8258         /* for GTP-C */
8259         memset(&filter_replace, 0,
8260                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8261         memset(&filter_replace_buf, 0,
8262                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8263         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8264         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8265         filter_replace.new_filter_type =
8266                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8267         /* Prepare the buffer, 2 entries */
8268         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8269         filter_replace_buf.data[0] |=
8270                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8271         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8272         filter_replace_buf.data[4] |=
8273                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8274         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8275                                                &filter_replace_buf);
8276         if (status < 0)
8277                 return status;
8278         if (filter_replace.old_filter_type !=
8279             filter_replace.new_filter_type)
8280                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8281                             " original: 0x%x, new: 0x%x",
8282                             dev->device->name,
8283                             filter_replace.old_filter_type,
8284                             filter_replace.new_filter_type);
8285
8286         /* for GTP-U */
8287         memset(&filter_replace, 0,
8288                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8289         memset(&filter_replace_buf, 0,
8290                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8291         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8292         filter_replace.old_filter_type =
8293                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8294         filter_replace.new_filter_type =
8295                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8296         /* Prepare the buffer, 2 entries */
8297         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8298         filter_replace_buf.data[0] |=
8299                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8300         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8301         filter_replace_buf.data[4] |=
8302                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8303
8304         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8305                                                &filter_replace_buf);
8306         if (!status && (filter_replace.old_filter_type !=
8307                         filter_replace.new_filter_type))
8308                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8309                             " original: 0x%x, new: 0x%x",
8310                             dev->device->name,
8311                             filter_replace.old_filter_type,
8312                             filter_replace.new_filter_type);
8313
8314         return status;
8315 }
8316
8317 static enum i40e_status_code
8318 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8319                             enum i40e_l4_port_type l4_port_type)
8320 {
8321         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8322         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8323         enum i40e_status_code status = I40E_SUCCESS;
8324         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8325         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8326
8327         if (pf->support_multi_driver) {
8328                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8329                 return I40E_NOT_SUPPORTED;
8330         }
8331
8332         memset(&filter_replace, 0,
8333                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8334         memset(&filter_replace_buf, 0,
8335                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8336
8337         /* create L1 filter */
8338         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8339                 filter_replace.old_filter_type =
8340                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8341                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8342                 filter_replace_buf.data[8] =
8343                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8344         } else {
8345                 filter_replace.old_filter_type =
8346                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8347                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8348                 filter_replace_buf.data[8] =
8349                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8350         }
8351
8352         filter_replace.tr_bit = 0;
8353         /* Prepare the buffer, 3 entries */
8354         filter_replace_buf.data[0] =
8355                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8356         filter_replace_buf.data[0] |=
8357                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8358         filter_replace_buf.data[2] = 0x00;
8359         filter_replace_buf.data[3] =
8360                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8361         filter_replace_buf.data[4] =
8362                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8363         filter_replace_buf.data[4] |=
8364                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8365         filter_replace_buf.data[5] = 0x00;
8366         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8367                 I40E_TR_L4_TYPE_TCP |
8368                 I40E_TR_L4_TYPE_SCTP;
8369         filter_replace_buf.data[7] = 0x00;
8370         filter_replace_buf.data[8] |=
8371                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8372         filter_replace_buf.data[9] = 0x00;
8373         filter_replace_buf.data[10] = 0xFF;
8374         filter_replace_buf.data[11] = 0xFF;
8375
8376         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8377                                                &filter_replace_buf);
8378         if (!status && filter_replace.old_filter_type !=
8379             filter_replace.new_filter_type)
8380                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8381                             " original: 0x%x, new: 0x%x",
8382                             dev->device->name,
8383                             filter_replace.old_filter_type,
8384                             filter_replace.new_filter_type);
8385
8386         return status;
8387 }
8388
8389 static enum i40e_status_code
8390 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8391                                enum i40e_l4_port_type l4_port_type)
8392 {
8393         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8394         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8395         enum i40e_status_code status = I40E_SUCCESS;
8396         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8397         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8398
8399         if (pf->support_multi_driver) {
8400                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8401                 return I40E_NOT_SUPPORTED;
8402         }
8403
8404         memset(&filter_replace, 0,
8405                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8406         memset(&filter_replace_buf, 0,
8407                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8408
8409         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8410                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8411                 filter_replace.new_filter_type =
8412                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8413                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8414         } else {
8415                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8416                 filter_replace.new_filter_type =
8417                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8418                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8419         }
8420
8421         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8422         filter_replace.tr_bit = 0;
8423         /* Prepare the buffer, 2 entries */
8424         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8425         filter_replace_buf.data[0] |=
8426                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8427         filter_replace_buf.data[4] |=
8428                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8429         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8430                                                &filter_replace_buf);
8431
8432         if (!status && filter_replace.old_filter_type !=
8433             filter_replace.new_filter_type)
8434                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8435                             " original: 0x%x, new: 0x%x",
8436                             dev->device->name,
8437                             filter_replace.old_filter_type,
8438                             filter_replace.new_filter_type);
8439
8440         return status;
8441 }
8442
8443 int
8444 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8445                       struct i40e_tunnel_filter_conf *tunnel_filter,
8446                       uint8_t add)
8447 {
8448         uint16_t ip_type;
8449         uint32_t ipv4_addr, ipv4_addr_le;
8450         uint8_t i, tun_type = 0;
8451         /* internal variable to convert ipv6 byte order */
8452         uint32_t convert_ipv6[4];
8453         int val, ret = 0;
8454         struct i40e_pf_vf *vf = NULL;
8455         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8456         struct i40e_vsi *vsi;
8457         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8458         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8459         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8460         struct i40e_tunnel_filter *tunnel, *node;
8461         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8462         uint32_t teid_le;
8463         bool big_buffer = 0;
8464
8465         cld_filter = rte_zmalloc("tunnel_filter",
8466                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8467                          0);
8468
8469         if (cld_filter == NULL) {
8470                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8471                 return -ENOMEM;
8472         }
8473         pfilter = cld_filter;
8474
8475         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8476                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8477         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8478                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8479
8480         pfilter->element.inner_vlan =
8481                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8482         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8483                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8484                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8485                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8486                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8487                                 &ipv4_addr_le,
8488                                 sizeof(pfilter->element.ipaddr.v4.data));
8489         } else {
8490                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8491                 for (i = 0; i < 4; i++) {
8492                         convert_ipv6[i] =
8493                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8494                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8495                 }
8496                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8497                            &convert_ipv6,
8498                            sizeof(pfilter->element.ipaddr.v6.data));
8499         }
8500
8501         /* check tunneled type */
8502         switch (tunnel_filter->tunnel_type) {
8503         case I40E_TUNNEL_TYPE_VXLAN:
8504                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8505                 break;
8506         case I40E_TUNNEL_TYPE_NVGRE:
8507                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8508                 break;
8509         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8510                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8511                 break;
8512         case I40E_TUNNEL_TYPE_MPLSoUDP:
8513                 if (!pf->mpls_replace_flag) {
8514                         i40e_replace_mpls_l1_filter(pf);
8515                         i40e_replace_mpls_cloud_filter(pf);
8516                         pf->mpls_replace_flag = 1;
8517                 }
8518                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8519                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8520                         teid_le >> 4;
8521                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8522                         (teid_le & 0xF) << 12;
8523                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8524                         0x40;
8525                 big_buffer = 1;
8526                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8527                 break;
8528         case I40E_TUNNEL_TYPE_MPLSoGRE:
8529                 if (!pf->mpls_replace_flag) {
8530                         i40e_replace_mpls_l1_filter(pf);
8531                         i40e_replace_mpls_cloud_filter(pf);
8532                         pf->mpls_replace_flag = 1;
8533                 }
8534                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8535                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8536                         teid_le >> 4;
8537                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8538                         (teid_le & 0xF) << 12;
8539                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8540                         0x0;
8541                 big_buffer = 1;
8542                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8543                 break;
8544         case I40E_TUNNEL_TYPE_GTPC:
8545                 if (!pf->gtp_replace_flag) {
8546                         i40e_replace_gtp_l1_filter(pf);
8547                         i40e_replace_gtp_cloud_filter(pf);
8548                         pf->gtp_replace_flag = 1;
8549                 }
8550                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8551                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8552                         (teid_le >> 16) & 0xFFFF;
8553                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8554                         teid_le & 0xFFFF;
8555                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8556                         0x0;
8557                 big_buffer = 1;
8558                 break;
8559         case I40E_TUNNEL_TYPE_GTPU:
8560                 if (!pf->gtp_replace_flag) {
8561                         i40e_replace_gtp_l1_filter(pf);
8562                         i40e_replace_gtp_cloud_filter(pf);
8563                         pf->gtp_replace_flag = 1;
8564                 }
8565                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8566                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8567                         (teid_le >> 16) & 0xFFFF;
8568                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8569                         teid_le & 0xFFFF;
8570                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8571                         0x0;
8572                 big_buffer = 1;
8573                 break;
8574         case I40E_TUNNEL_TYPE_QINQ:
8575                 if (!pf->qinq_replace_flag) {
8576                         ret = i40e_cloud_filter_qinq_create(pf);
8577                         if (ret < 0)
8578                                 PMD_DRV_LOG(DEBUG,
8579                                             "QinQ tunnel filter already created.");
8580                         pf->qinq_replace_flag = 1;
8581                 }
8582                 /*      Add in the General fields the values of
8583                  *      the Outer and Inner VLAN
8584                  *      Big Buffer should be set, see changes in
8585                  *      i40e_aq_add_cloud_filters
8586                  */
8587                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8588                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8589                 big_buffer = 1;
8590                 break;
8591         case I40E_CLOUD_TYPE_UDP:
8592         case I40E_CLOUD_TYPE_TCP:
8593         case I40E_CLOUD_TYPE_SCTP:
8594                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8595                         if (!pf->sport_replace_flag) {
8596                                 i40e_replace_port_l1_filter(pf,
8597                                                 tunnel_filter->l4_port_type);
8598                                 i40e_replace_port_cloud_filter(pf,
8599                                                 tunnel_filter->l4_port_type);
8600                                 pf->sport_replace_flag = 1;
8601                         }
8602                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8603                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8604                                 I40E_DIRECTION_INGRESS_KEY;
8605
8606                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8607                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8608                                         I40E_TR_L4_TYPE_UDP;
8609                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8610                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8611                                         I40E_TR_L4_TYPE_TCP;
8612                         else
8613                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8614                                         I40E_TR_L4_TYPE_SCTP;
8615
8616                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8617                                 (teid_le >> 16) & 0xFFFF;
8618                         big_buffer = 1;
8619                 } else {
8620                         if (!pf->dport_replace_flag) {
8621                                 i40e_replace_port_l1_filter(pf,
8622                                                 tunnel_filter->l4_port_type);
8623                                 i40e_replace_port_cloud_filter(pf,
8624                                                 tunnel_filter->l4_port_type);
8625                                 pf->dport_replace_flag = 1;
8626                         }
8627                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8628                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8629                                 I40E_DIRECTION_INGRESS_KEY;
8630
8631                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8632                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8633                                         I40E_TR_L4_TYPE_UDP;
8634                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8635                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8636                                         I40E_TR_L4_TYPE_TCP;
8637                         else
8638                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8639                                         I40E_TR_L4_TYPE_SCTP;
8640
8641                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8642                                 (teid_le >> 16) & 0xFFFF;
8643                         big_buffer = 1;
8644                 }
8645
8646                 break;
8647         default:
8648                 /* Other tunnel types is not supported. */
8649                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8650                 rte_free(cld_filter);
8651                 return -EINVAL;
8652         }
8653
8654         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8655                 pfilter->element.flags =
8656                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8657         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8658                 pfilter->element.flags =
8659                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8660         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8661                 pfilter->element.flags =
8662                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8663         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8664                 pfilter->element.flags =
8665                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8666         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8667                 pfilter->element.flags |=
8668                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8669         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8670                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8671                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8672                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8673                         pfilter->element.flags |=
8674                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8675                 else
8676                         pfilter->element.flags |=
8677                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8678         } else {
8679                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8680                                                 &pfilter->element.flags);
8681                 if (val < 0) {
8682                         rte_free(cld_filter);
8683                         return -EINVAL;
8684                 }
8685         }
8686
8687         pfilter->element.flags |= rte_cpu_to_le_16(
8688                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8689                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8690         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8691         pfilter->element.queue_number =
8692                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8693
8694         if (!tunnel_filter->is_to_vf)
8695                 vsi = pf->main_vsi;
8696         else {
8697                 if (tunnel_filter->vf_id >= pf->vf_num) {
8698                         PMD_DRV_LOG(ERR, "Invalid argument.");
8699                         rte_free(cld_filter);
8700                         return -EINVAL;
8701                 }
8702                 vf = &pf->vfs[tunnel_filter->vf_id];
8703                 vsi = vf->vsi;
8704         }
8705
8706         /* Check if there is the filter in SW list */
8707         memset(&check_filter, 0, sizeof(check_filter));
8708         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8709         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8710         check_filter.vf_id = tunnel_filter->vf_id;
8711         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8712         if (add && node) {
8713                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8714                 rte_free(cld_filter);
8715                 return -EINVAL;
8716         }
8717
8718         if (!add && !node) {
8719                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8720                 rte_free(cld_filter);
8721                 return -EINVAL;
8722         }
8723
8724         if (add) {
8725                 if (big_buffer)
8726                         ret = i40e_aq_add_cloud_filters_bb(hw,
8727                                                    vsi->seid, cld_filter, 1);
8728                 else
8729                         ret = i40e_aq_add_cloud_filters(hw,
8730                                         vsi->seid, &cld_filter->element, 1);
8731                 if (ret < 0) {
8732                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8733                         rte_free(cld_filter);
8734                         return -ENOTSUP;
8735                 }
8736                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8737                 if (tunnel == NULL) {
8738                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8739                         rte_free(cld_filter);
8740                         return -ENOMEM;
8741                 }
8742
8743                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8744                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8745                 if (ret < 0)
8746                         rte_free(tunnel);
8747         } else {
8748                 if (big_buffer)
8749                         ret = i40e_aq_rem_cloud_filters_bb(
8750                                 hw, vsi->seid, cld_filter, 1);
8751                 else
8752                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8753                                                 &cld_filter->element, 1);
8754                 if (ret < 0) {
8755                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8756                         rte_free(cld_filter);
8757                         return -ENOTSUP;
8758                 }
8759                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8760         }
8761
8762         rte_free(cld_filter);
8763         return ret;
8764 }
8765
8766 static int
8767 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8768 {
8769         uint8_t i;
8770
8771         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8772                 if (pf->vxlan_ports[i] == port)
8773                         return i;
8774         }
8775
8776         return -1;
8777 }
8778
8779 static int
8780 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8781 {
8782         int  idx, ret;
8783         uint8_t filter_idx = 0;
8784         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8785
8786         idx = i40e_get_vxlan_port_idx(pf, port);
8787
8788         /* Check if port already exists */
8789         if (idx >= 0) {
8790                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8791                 return -EINVAL;
8792         }
8793
8794         /* Now check if there is space to add the new port */
8795         idx = i40e_get_vxlan_port_idx(pf, 0);
8796         if (idx < 0) {
8797                 PMD_DRV_LOG(ERR,
8798                         "Maximum number of UDP ports reached, not adding port %d",
8799                         port);
8800                 return -ENOSPC;
8801         }
8802
8803         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8804                                         &filter_idx, NULL);
8805         if (ret < 0) {
8806                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8807                 return -1;
8808         }
8809
8810         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8811                          port,  filter_idx);
8812
8813         /* New port: add it and mark its index in the bitmap */
8814         pf->vxlan_ports[idx] = port;
8815         pf->vxlan_bitmap |= (1 << idx);
8816
8817         if (!(pf->flags & I40E_FLAG_VXLAN))
8818                 pf->flags |= I40E_FLAG_VXLAN;
8819
8820         return 0;
8821 }
8822
8823 static int
8824 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8825 {
8826         int idx;
8827         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8828
8829         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8830                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8831                 return -EINVAL;
8832         }
8833
8834         idx = i40e_get_vxlan_port_idx(pf, port);
8835
8836         if (idx < 0) {
8837                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8838                 return -EINVAL;
8839         }
8840
8841         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8842                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8843                 return -1;
8844         }
8845
8846         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8847                         port, idx);
8848
8849         pf->vxlan_ports[idx] = 0;
8850         pf->vxlan_bitmap &= ~(1 << idx);
8851
8852         if (!pf->vxlan_bitmap)
8853                 pf->flags &= ~I40E_FLAG_VXLAN;
8854
8855         return 0;
8856 }
8857
8858 /* Add UDP tunneling port */
8859 static int
8860 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8861                              struct rte_eth_udp_tunnel *udp_tunnel)
8862 {
8863         int ret = 0;
8864         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8865
8866         if (udp_tunnel == NULL)
8867                 return -EINVAL;
8868
8869         switch (udp_tunnel->prot_type) {
8870         case RTE_TUNNEL_TYPE_VXLAN:
8871                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8872                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8873                 break;
8874         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8875                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8876                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8877                 break;
8878         case RTE_TUNNEL_TYPE_GENEVE:
8879         case RTE_TUNNEL_TYPE_TEREDO:
8880                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8881                 ret = -1;
8882                 break;
8883
8884         default:
8885                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8886                 ret = -1;
8887                 break;
8888         }
8889
8890         return ret;
8891 }
8892
8893 /* Remove UDP tunneling port */
8894 static int
8895 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8896                              struct rte_eth_udp_tunnel *udp_tunnel)
8897 {
8898         int ret = 0;
8899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8900
8901         if (udp_tunnel == NULL)
8902                 return -EINVAL;
8903
8904         switch (udp_tunnel->prot_type) {
8905         case RTE_TUNNEL_TYPE_VXLAN:
8906         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8907                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8908                 break;
8909         case RTE_TUNNEL_TYPE_GENEVE:
8910         case RTE_TUNNEL_TYPE_TEREDO:
8911                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8912                 ret = -1;
8913                 break;
8914         default:
8915                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8916                 ret = -1;
8917                 break;
8918         }
8919
8920         return ret;
8921 }
8922
8923 /* Calculate the maximum number of contiguous PF queues that are configured */
8924 static int
8925 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8926 {
8927         struct rte_eth_dev_data *data = pf->dev_data;
8928         int i, num;
8929         struct i40e_rx_queue *rxq;
8930
8931         num = 0;
8932         for (i = 0; i < pf->lan_nb_qps; i++) {
8933                 rxq = data->rx_queues[i];
8934                 if (rxq && rxq->q_set)
8935                         num++;
8936                 else
8937                         break;
8938         }
8939
8940         return num;
8941 }
8942
8943 /* Configure RSS */
8944 static int
8945 i40e_pf_config_rss(struct i40e_pf *pf)
8946 {
8947         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8948         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8949         struct rte_eth_rss_conf rss_conf;
8950         uint32_t i, lut = 0;
8951         uint16_t j, num;
8952
8953         /*
8954          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8955          * It's necessary to calculate the actual PF queues that are configured.
8956          */
8957         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8958                 num = i40e_pf_calc_configured_queues_num(pf);
8959         else
8960                 num = pf->dev_data->nb_rx_queues;
8961
8962         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8963         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8964                         num);
8965
8966         if (num == 0) {
8967                 PMD_INIT_LOG(ERR,
8968                         "No PF queues are configured to enable RSS for port %u",
8969                         pf->dev_data->port_id);
8970                 return -ENOTSUP;
8971         }
8972
8973         if (pf->adapter->rss_reta_updated == 0) {
8974                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8975                         if (j == num)
8976                                 j = 0;
8977                         lut = (lut << 8) | (j & ((0x1 <<
8978                                 hw->func_caps.rss_table_entry_width) - 1));
8979                         if ((i & 3) == 3)
8980                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8981                                                rte_bswap32(lut));
8982                 }
8983         }
8984
8985         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8986         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
8987             !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
8988                 i40e_pf_disable_rss(pf);
8989                 return 0;
8990         }
8991         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8992                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8993                 /* Random default keys */
8994                 static uint32_t rss_key_default[] = {0x6b793944,
8995                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8996                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8997                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8998
8999                 rss_conf.rss_key = (uint8_t *)rss_key_default;
9000                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9001                                                         sizeof(uint32_t);
9002         }
9003
9004         return i40e_hw_rss_hash_set(pf, &rss_conf);
9005 }
9006
9007 static int
9008 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9009                                struct rte_eth_tunnel_filter_conf *filter)
9010 {
9011         if (pf == NULL || filter == NULL) {
9012                 PMD_DRV_LOG(ERR, "Invalid parameter");
9013                 return -EINVAL;
9014         }
9015
9016         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9017                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9018                 return -EINVAL;
9019         }
9020
9021         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9022                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9023                 return -EINVAL;
9024         }
9025
9026         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9027                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9028                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9029                 return -EINVAL;
9030         }
9031
9032         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9033                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9034                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9035                 return -EINVAL;
9036         }
9037
9038         return 0;
9039 }
9040
9041 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9042 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
9043 int
9044 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9045 {
9046         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9047         uint32_t val, reg;
9048         int ret = -EINVAL;
9049
9050         if (pf->support_multi_driver) {
9051                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9052                 return -ENOTSUP;
9053         }
9054
9055         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9056         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9057
9058         if (len == 3) {
9059                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9060         } else if (len == 4) {
9061                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9062         } else {
9063                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9064                 return ret;
9065         }
9066
9067         if (reg != val) {
9068                 ret = i40e_aq_debug_write_global_register(hw,
9069                                                    I40E_GL_PRS_FVBM(2),
9070                                                    reg, NULL);
9071                 if (ret != 0)
9072                         return ret;
9073                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9074                             "with value 0x%08x",
9075                             I40E_GL_PRS_FVBM(2), reg);
9076         } else {
9077                 ret = 0;
9078         }
9079         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9080                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9081
9082         return ret;
9083 }
9084
9085 static int
9086 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9087 {
9088         int ret = -EINVAL;
9089
9090         if (!hw || !cfg)
9091                 return -EINVAL;
9092
9093         switch (cfg->cfg_type) {
9094         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9095                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9096                 break;
9097         default:
9098                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9099                 break;
9100         }
9101
9102         return ret;
9103 }
9104
9105 static int
9106 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9107                                enum rte_filter_op filter_op,
9108                                void *arg)
9109 {
9110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9111         int ret = I40E_ERR_PARAM;
9112
9113         switch (filter_op) {
9114         case RTE_ETH_FILTER_SET:
9115                 ret = i40e_dev_global_config_set(hw,
9116                         (struct rte_eth_global_cfg *)arg);
9117                 break;
9118         default:
9119                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9120                 break;
9121         }
9122
9123         return ret;
9124 }
9125
9126 static int
9127 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9128                           enum rte_filter_op filter_op,
9129                           void *arg)
9130 {
9131         struct rte_eth_tunnel_filter_conf *filter;
9132         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9133         int ret = I40E_SUCCESS;
9134
9135         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9136
9137         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9138                 return I40E_ERR_PARAM;
9139
9140         switch (filter_op) {
9141         case RTE_ETH_FILTER_NOP:
9142                 if (!(pf->flags & I40E_FLAG_VXLAN))
9143                         ret = I40E_NOT_SUPPORTED;
9144                 break;
9145         case RTE_ETH_FILTER_ADD:
9146                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9147                 break;
9148         case RTE_ETH_FILTER_DELETE:
9149                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9150                 break;
9151         default:
9152                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9153                 ret = I40E_ERR_PARAM;
9154                 break;
9155         }
9156
9157         return ret;
9158 }
9159
9160 /* Get the symmetric hash enable configurations per port */
9161 static void
9162 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9163 {
9164         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9165
9166         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9167 }
9168
9169 /* Set the symmetric hash enable configurations per port */
9170 static void
9171 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9172 {
9173         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9174
9175         if (enable > 0) {
9176                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9177                         PMD_DRV_LOG(INFO,
9178                                 "Symmetric hash has already been enabled");
9179                         return;
9180                 }
9181                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9182         } else {
9183                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9184                         PMD_DRV_LOG(INFO,
9185                                 "Symmetric hash has already been disabled");
9186                         return;
9187                 }
9188                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9189         }
9190         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9191         I40E_WRITE_FLUSH(hw);
9192 }
9193
9194 /*
9195  * Get global configurations of hash function type and symmetric hash enable
9196  * per flow type (pctype). Note that global configuration means it affects all
9197  * the ports on the same NIC.
9198  */
9199 static int
9200 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9201                                    struct rte_eth_hash_global_conf *g_cfg)
9202 {
9203         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9204         uint32_t reg;
9205         uint16_t i, j;
9206
9207         memset(g_cfg, 0, sizeof(*g_cfg));
9208         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9209         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9210                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9211         else
9212                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9213         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9214                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9215
9216         /*
9217          * As i40e supports less than 64 flow types, only first 64 bits need to
9218          * be checked.
9219          */
9220         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9221                 g_cfg->valid_bit_mask[i] = 0ULL;
9222                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9223         }
9224
9225         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9226
9227         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9228                 if (!adapter->pctypes_tbl[i])
9229                         continue;
9230                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9231                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9232                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9233                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9234                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9235                                         g_cfg->sym_hash_enable_mask[0] |=
9236                                                                 (1ULL << i);
9237                                 }
9238                         }
9239                 }
9240         }
9241
9242         return 0;
9243 }
9244
9245 static int
9246 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9247                               const struct rte_eth_hash_global_conf *g_cfg)
9248 {
9249         uint32_t i;
9250         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9251
9252         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9253                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9254                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9255                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9256                                                 g_cfg->hash_func);
9257                 return -EINVAL;
9258         }
9259
9260         /*
9261          * As i40e supports less than 64 flow types, only first 64 bits need to
9262          * be checked.
9263          */
9264         mask0 = g_cfg->valid_bit_mask[0];
9265         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9266                 if (i == 0) {
9267                         /* Check if any unsupported flow type configured */
9268                         if ((mask0 | i40e_mask) ^ i40e_mask)
9269                                 goto mask_err;
9270                 } else {
9271                         if (g_cfg->valid_bit_mask[i])
9272                                 goto mask_err;
9273                 }
9274         }
9275
9276         return 0;
9277
9278 mask_err:
9279         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9280
9281         return -EINVAL;
9282 }
9283
9284 /*
9285  * Set global configurations of hash function type and symmetric hash enable
9286  * per flow type (pctype). Note any modifying global configuration will affect
9287  * all the ports on the same NIC.
9288  */
9289 static int
9290 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9291                                    struct rte_eth_hash_global_conf *g_cfg)
9292 {
9293         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9294         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9295         int ret;
9296         uint16_t i, j;
9297         uint32_t reg;
9298         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9299
9300         if (pf->support_multi_driver) {
9301                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9302                 return -ENOTSUP;
9303         }
9304
9305         /* Check the input parameters */
9306         ret = i40e_hash_global_config_check(adapter, g_cfg);
9307         if (ret < 0)
9308                 return ret;
9309
9310         /*
9311          * As i40e supports less than 64 flow types, only first 64 bits need to
9312          * be configured.
9313          */
9314         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9315                 if (mask0 & (1UL << i)) {
9316                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9317                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9318
9319                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9320                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9321                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9322                                         i40e_write_global_rx_ctl(hw,
9323                                                           I40E_GLQF_HSYM(j),
9324                                                           reg);
9325                         }
9326                 }
9327         }
9328
9329         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9330         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9331                 /* Toeplitz */
9332                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9333                         PMD_DRV_LOG(DEBUG,
9334                                 "Hash function already set to Toeplitz");
9335                         goto out;
9336                 }
9337                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9338         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9339                 /* Simple XOR */
9340                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9341                         PMD_DRV_LOG(DEBUG,
9342                                 "Hash function already set to Simple XOR");
9343                         goto out;
9344                 }
9345                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9346         } else
9347                 /* Use the default, and keep it as it is */
9348                 goto out;
9349
9350         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9351
9352 out:
9353         I40E_WRITE_FLUSH(hw);
9354
9355         return 0;
9356 }
9357
9358 /**
9359  * Valid input sets for hash and flow director filters per PCTYPE
9360  */
9361 static uint64_t
9362 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9363                 enum rte_filter_type filter)
9364 {
9365         uint64_t valid;
9366
9367         static const uint64_t valid_hash_inset_table[] = {
9368                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9369                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9370                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9371                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9372                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9373                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9374                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9375                         I40E_INSET_FLEX_PAYLOAD,
9376                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9377                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9378                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9379                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9380                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9381                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9382                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9383                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9384                         I40E_INSET_FLEX_PAYLOAD,
9385                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9386                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9387                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9388                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9389                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9390                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9391                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9392                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9393                         I40E_INSET_FLEX_PAYLOAD,
9394                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9395                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9396                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9397                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9398                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9399                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9400                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9401                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9402                         I40E_INSET_FLEX_PAYLOAD,
9403                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9404                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9405                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9406                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9407                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9408                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9409                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9410                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9411                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9412                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9413                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9414                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9415                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9416                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9417                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9418                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9419                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9420                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9421                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9422                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9423                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9424                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9425                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9426                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9427                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9428                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9429                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9430                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9431                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9432                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9433                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9434                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9435                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9436                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9437                         I40E_INSET_FLEX_PAYLOAD,
9438                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9439                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9440                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9441                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9442                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9443                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9444                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9445                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9446                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9447                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9448                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9449                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9450                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9451                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9452                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9453                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9454                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9455                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9456                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9457                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9458                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9459                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9460                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9461                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9462                         I40E_INSET_FLEX_PAYLOAD,
9463                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9464                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9465                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9466                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9467                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9468                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9469                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9470                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9471                         I40E_INSET_FLEX_PAYLOAD,
9472                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9473                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9474                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9475                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9476                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9477                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9478                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9479                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9480                         I40E_INSET_FLEX_PAYLOAD,
9481                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9482                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9483                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9484                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9485                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9486                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9487                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9488                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9489                         I40E_INSET_FLEX_PAYLOAD,
9490                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9491                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9492                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9493                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9494                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9495                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9496                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9497                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9498                         I40E_INSET_FLEX_PAYLOAD,
9499                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9500                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9501                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9502                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9503                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9504                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9505                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9506                         I40E_INSET_FLEX_PAYLOAD,
9507                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9508                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9509                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9510                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9511                         I40E_INSET_FLEX_PAYLOAD,
9512         };
9513
9514         /**
9515          * Flow director supports only fields defined in
9516          * union rte_eth_fdir_flow.
9517          */
9518         static const uint64_t valid_fdir_inset_table[] = {
9519                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9520                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9521                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9522                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9523                 I40E_INSET_IPV4_TTL,
9524                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9525                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9526                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9527                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9528                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9529                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9530                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9531                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9532                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9533                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9534                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9535                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9536                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9537                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9538                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9539                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9540                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9541                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9542                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9543                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9544                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9545                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9546                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9547                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9548                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9549                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9550                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9551                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9552                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9553                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9554                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9555                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9556                 I40E_INSET_SCTP_VT,
9557                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9558                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9559                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9560                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9561                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9562                 I40E_INSET_IPV4_TTL,
9563                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9564                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9565                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9566                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9567                 I40E_INSET_IPV6_HOP_LIMIT,
9568                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9569                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9570                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9571                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9572                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9573                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9574                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9575                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9576                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9577                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9578                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9579                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9580                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9581                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9582                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9583                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9584                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9585                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9586                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9587                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9588                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9589                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9590                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9591                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9592                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9593                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9594                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9595                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9596                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9597                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9598                 I40E_INSET_SCTP_VT,
9599                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9600                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9601                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9602                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9603                 I40E_INSET_IPV6_HOP_LIMIT,
9604                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9605                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9606                 I40E_INSET_LAST_ETHER_TYPE,
9607         };
9608
9609         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9610                 return 0;
9611         if (filter == RTE_ETH_FILTER_HASH)
9612                 valid = valid_hash_inset_table[pctype];
9613         else
9614                 valid = valid_fdir_inset_table[pctype];
9615
9616         return valid;
9617 }
9618
9619 /**
9620  * Validate if the input set is allowed for a specific PCTYPE
9621  */
9622 int
9623 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9624                 enum rte_filter_type filter, uint64_t inset)
9625 {
9626         uint64_t valid;
9627
9628         valid = i40e_get_valid_input_set(pctype, filter);
9629         if (inset & (~valid))
9630                 return -EINVAL;
9631
9632         return 0;
9633 }
9634
9635 /* default input set fields combination per pctype */
9636 uint64_t
9637 i40e_get_default_input_set(uint16_t pctype)
9638 {
9639         static const uint64_t default_inset_table[] = {
9640                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9641                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9642                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9643                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9644                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9645                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9646                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9647                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9648                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9649                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9650                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9651                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9652                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9653                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9654                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9655                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9656                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9657                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9658                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9659                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9660                         I40E_INSET_SCTP_VT,
9661                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9662                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9663                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9664                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9665                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9666                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9667                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9668                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9669                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9670                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9671                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9672                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9673                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9674                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9675                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9676                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9677                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9678                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9679                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9680                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9681                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9682                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9683                         I40E_INSET_SCTP_VT,
9684                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9685                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9686                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9687                         I40E_INSET_LAST_ETHER_TYPE,
9688         };
9689
9690         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9691                 return 0;
9692
9693         return default_inset_table[pctype];
9694 }
9695
9696 /**
9697  * Parse the input set from index to logical bit masks
9698  */
9699 static int
9700 i40e_parse_input_set(uint64_t *inset,
9701                      enum i40e_filter_pctype pctype,
9702                      enum rte_eth_input_set_field *field,
9703                      uint16_t size)
9704 {
9705         uint16_t i, j;
9706         int ret = -EINVAL;
9707
9708         static const struct {
9709                 enum rte_eth_input_set_field field;
9710                 uint64_t inset;
9711         } inset_convert_table[] = {
9712                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9713                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9714                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9715                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9716                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9717                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9718                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9719                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9720                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9721                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9722                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9723                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9724                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9725                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9726                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9727                         I40E_INSET_IPV6_NEXT_HDR},
9728                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9729                         I40E_INSET_IPV6_HOP_LIMIT},
9730                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9731                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9732                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9733                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9734                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9735                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9736                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9737                         I40E_INSET_SCTP_VT},
9738                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9739                         I40E_INSET_TUNNEL_DMAC},
9740                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9741                         I40E_INSET_VLAN_TUNNEL},
9742                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9743                         I40E_INSET_TUNNEL_ID},
9744                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9745                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9746                         I40E_INSET_FLEX_PAYLOAD_W1},
9747                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9748                         I40E_INSET_FLEX_PAYLOAD_W2},
9749                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9750                         I40E_INSET_FLEX_PAYLOAD_W3},
9751                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9752                         I40E_INSET_FLEX_PAYLOAD_W4},
9753                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9754                         I40E_INSET_FLEX_PAYLOAD_W5},
9755                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9756                         I40E_INSET_FLEX_PAYLOAD_W6},
9757                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9758                         I40E_INSET_FLEX_PAYLOAD_W7},
9759                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9760                         I40E_INSET_FLEX_PAYLOAD_W8},
9761         };
9762
9763         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9764                 return ret;
9765
9766         /* Only one item allowed for default or all */
9767         if (size == 1) {
9768                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9769                         *inset = i40e_get_default_input_set(pctype);
9770                         return 0;
9771                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9772                         *inset = I40E_INSET_NONE;
9773                         return 0;
9774                 }
9775         }
9776
9777         for (i = 0, *inset = 0; i < size; i++) {
9778                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9779                         if (field[i] == inset_convert_table[j].field) {
9780                                 *inset |= inset_convert_table[j].inset;
9781                                 break;
9782                         }
9783                 }
9784
9785                 /* It contains unsupported input set, return immediately */
9786                 if (j == RTE_DIM(inset_convert_table))
9787                         return ret;
9788         }
9789
9790         return 0;
9791 }
9792
9793 /**
9794  * Translate the input set from bit masks to register aware bit masks
9795  * and vice versa
9796  */
9797 uint64_t
9798 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9799 {
9800         uint64_t val = 0;
9801         uint16_t i;
9802
9803         struct inset_map {
9804                 uint64_t inset;
9805                 uint64_t inset_reg;
9806         };
9807
9808         static const struct inset_map inset_map_common[] = {
9809                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9810                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9811                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9812                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9813                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9814                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9815                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9816                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9817                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9818                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9819                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9820                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9821                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9822                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9823                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9824                 {I40E_INSET_TUNNEL_DMAC,
9825                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9826                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9827                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9828                 {I40E_INSET_TUNNEL_SRC_PORT,
9829                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9830                 {I40E_INSET_TUNNEL_DST_PORT,
9831                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9832                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9833                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9834                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9835                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9836                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9837                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9838                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9839                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9840                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9841         };
9842
9843     /* some different registers map in x722*/
9844         static const struct inset_map inset_map_diff_x722[] = {
9845                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9846                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9847                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9848                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9849         };
9850
9851         static const struct inset_map inset_map_diff_not_x722[] = {
9852                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9853                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9854                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9855                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9856         };
9857
9858         if (input == 0)
9859                 return val;
9860
9861         /* Translate input set to register aware inset */
9862         if (type == I40E_MAC_X722) {
9863                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9864                         if (input & inset_map_diff_x722[i].inset)
9865                                 val |= inset_map_diff_x722[i].inset_reg;
9866                 }
9867         } else {
9868                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9869                         if (input & inset_map_diff_not_x722[i].inset)
9870                                 val |= inset_map_diff_not_x722[i].inset_reg;
9871                 }
9872         }
9873
9874         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9875                 if (input & inset_map_common[i].inset)
9876                         val |= inset_map_common[i].inset_reg;
9877         }
9878
9879         return val;
9880 }
9881
9882 int
9883 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9884 {
9885         uint8_t i, idx = 0;
9886         uint64_t inset_need_mask = inset;
9887
9888         static const struct {
9889                 uint64_t inset;
9890                 uint32_t mask;
9891         } inset_mask_map[] = {
9892                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9893                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9894                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9895                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9896                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9897                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9898                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9899                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9900         };
9901
9902         if (!inset || !mask || !nb_elem)
9903                 return 0;
9904
9905         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9906                 /* Clear the inset bit, if no MASK is required,
9907                  * for example proto + ttl
9908                  */
9909                 if ((inset & inset_mask_map[i].inset) ==
9910                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9911                         inset_need_mask &= ~inset_mask_map[i].inset;
9912                 if (!inset_need_mask)
9913                         return 0;
9914         }
9915         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9916                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9917                     inset_mask_map[i].inset) {
9918                         if (idx >= nb_elem) {
9919                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9920                                 return -EINVAL;
9921                         }
9922                         mask[idx] = inset_mask_map[i].mask;
9923                         idx++;
9924                 }
9925         }
9926
9927         return idx;
9928 }
9929
9930 void
9931 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9932 {
9933         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9934
9935         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9936         if (reg != val)
9937                 i40e_write_rx_ctl(hw, addr, val);
9938         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9939                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9940 }
9941
9942 void
9943 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9944 {
9945         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9946         struct rte_eth_dev *dev;
9947
9948         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9949         if (reg != val) {
9950                 i40e_write_rx_ctl(hw, addr, val);
9951                 PMD_DRV_LOG(WARNING,
9952                             "i40e device %s changed global register [0x%08x]."
9953                             " original: 0x%08x, new: 0x%08x",
9954                             dev->device->name, addr, reg,
9955                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9956         }
9957 }
9958
9959 static void
9960 i40e_filter_input_set_init(struct i40e_pf *pf)
9961 {
9962         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9963         enum i40e_filter_pctype pctype;
9964         uint64_t input_set, inset_reg;
9965         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9966         int num, i;
9967         uint16_t flow_type;
9968
9969         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9970              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9971                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9972
9973                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9974                         continue;
9975
9976                 input_set = i40e_get_default_input_set(pctype);
9977
9978                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9979                                                    I40E_INSET_MASK_NUM_REG);
9980                 if (num < 0)
9981                         return;
9982                 if (pf->support_multi_driver && num > 0) {
9983                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9984                         return;
9985                 }
9986                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9987                                         input_set);
9988
9989                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9990                                       (uint32_t)(inset_reg & UINT32_MAX));
9991                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9992                                      (uint32_t)((inset_reg >>
9993                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9994                 if (!pf->support_multi_driver) {
9995                         i40e_check_write_global_reg(hw,
9996                                             I40E_GLQF_HASH_INSET(0, pctype),
9997                                             (uint32_t)(inset_reg & UINT32_MAX));
9998                         i40e_check_write_global_reg(hw,
9999                                              I40E_GLQF_HASH_INSET(1, pctype),
10000                                              (uint32_t)((inset_reg >>
10001                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
10002
10003                         for (i = 0; i < num; i++) {
10004                                 i40e_check_write_global_reg(hw,
10005                                                     I40E_GLQF_FD_MSK(i, pctype),
10006                                                     mask_reg[i]);
10007                                 i40e_check_write_global_reg(hw,
10008                                                   I40E_GLQF_HASH_MSK(i, pctype),
10009                                                   mask_reg[i]);
10010                         }
10011                         /*clear unused mask registers of the pctype */
10012                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10013                                 i40e_check_write_global_reg(hw,
10014                                                     I40E_GLQF_FD_MSK(i, pctype),
10015                                                     0);
10016                                 i40e_check_write_global_reg(hw,
10017                                                   I40E_GLQF_HASH_MSK(i, pctype),
10018                                                   0);
10019                         }
10020                 } else {
10021                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10022                 }
10023                 I40E_WRITE_FLUSH(hw);
10024
10025                 /* store the default input set */
10026                 if (!pf->support_multi_driver)
10027                         pf->hash_input_set[pctype] = input_set;
10028                 pf->fdir.input_set[pctype] = input_set;
10029         }
10030 }
10031
10032 int
10033 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10034                          struct rte_eth_input_set_conf *conf)
10035 {
10036         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10037         enum i40e_filter_pctype pctype;
10038         uint64_t input_set, inset_reg = 0;
10039         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10040         int ret, i, num;
10041
10042         if (!conf) {
10043                 PMD_DRV_LOG(ERR, "Invalid pointer");
10044                 return -EFAULT;
10045         }
10046         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10047             conf->op != RTE_ETH_INPUT_SET_ADD) {
10048                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10049                 return -EINVAL;
10050         }
10051
10052         if (pf->support_multi_driver) {
10053                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10054                 return -ENOTSUP;
10055         }
10056
10057         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10058         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10059                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10060                 return -EINVAL;
10061         }
10062
10063         if (hw->mac.type == I40E_MAC_X722) {
10064                 /* get translated pctype value in fd pctype register */
10065                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10066                         I40E_GLQF_FD_PCTYPES((int)pctype));
10067         }
10068
10069         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10070                                    conf->inset_size);
10071         if (ret) {
10072                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10073                 return -EINVAL;
10074         }
10075
10076         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10077                 /* get inset value in register */
10078                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10079                 inset_reg <<= I40E_32_BIT_WIDTH;
10080                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10081                 input_set |= pf->hash_input_set[pctype];
10082         }
10083         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10084                                            I40E_INSET_MASK_NUM_REG);
10085         if (num < 0)
10086                 return -EINVAL;
10087
10088         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10089
10090         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10091                                     (uint32_t)(inset_reg & UINT32_MAX));
10092         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10093                                     (uint32_t)((inset_reg >>
10094                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
10095
10096         for (i = 0; i < num; i++)
10097                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10098                                             mask_reg[i]);
10099         /*clear unused mask registers of the pctype */
10100         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10101                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10102                                             0);
10103         I40E_WRITE_FLUSH(hw);
10104
10105         pf->hash_input_set[pctype] = input_set;
10106         return 0;
10107 }
10108
10109 int
10110 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10111                          struct rte_eth_input_set_conf *conf)
10112 {
10113         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10114         enum i40e_filter_pctype pctype;
10115         uint64_t input_set, inset_reg = 0;
10116         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10117         int ret, i, num;
10118
10119         if (!hw || !conf) {
10120                 PMD_DRV_LOG(ERR, "Invalid pointer");
10121                 return -EFAULT;
10122         }
10123         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10124             conf->op != RTE_ETH_INPUT_SET_ADD) {
10125                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10126                 return -EINVAL;
10127         }
10128
10129         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10130
10131         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10132                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10133                 return -EINVAL;
10134         }
10135
10136         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10137                                    conf->inset_size);
10138         if (ret) {
10139                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10140                 return -EINVAL;
10141         }
10142
10143         /* get inset value in register */
10144         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10145         inset_reg <<= I40E_32_BIT_WIDTH;
10146         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10147
10148         /* Can not change the inset reg for flex payload for fdir,
10149          * it is done by writing I40E_PRTQF_FD_FLXINSET
10150          * in i40e_set_flex_mask_on_pctype.
10151          */
10152         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10153                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10154         else
10155                 input_set |= pf->fdir.input_set[pctype];
10156         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10157                                            I40E_INSET_MASK_NUM_REG);
10158         if (num < 0)
10159                 return -EINVAL;
10160         if (pf->support_multi_driver && num > 0) {
10161                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10162                 return -ENOTSUP;
10163         }
10164
10165         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10166
10167         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10168                               (uint32_t)(inset_reg & UINT32_MAX));
10169         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10170                              (uint32_t)((inset_reg >>
10171                              I40E_32_BIT_WIDTH) & UINT32_MAX));
10172
10173         if (!pf->support_multi_driver) {
10174                 for (i = 0; i < num; i++)
10175                         i40e_check_write_global_reg(hw,
10176                                                     I40E_GLQF_FD_MSK(i, pctype),
10177                                                     mask_reg[i]);
10178                 /*clear unused mask registers of the pctype */
10179                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10180                         i40e_check_write_global_reg(hw,
10181                                                     I40E_GLQF_FD_MSK(i, pctype),
10182                                                     0);
10183         } else {
10184                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10185         }
10186         I40E_WRITE_FLUSH(hw);
10187
10188         pf->fdir.input_set[pctype] = input_set;
10189         return 0;
10190 }
10191
10192 static int
10193 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10194 {
10195         int ret = 0;
10196
10197         if (!hw || !info) {
10198                 PMD_DRV_LOG(ERR, "Invalid pointer");
10199                 return -EFAULT;
10200         }
10201
10202         switch (info->info_type) {
10203         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10204                 i40e_get_symmetric_hash_enable_per_port(hw,
10205                                         &(info->info.enable));
10206                 break;
10207         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10208                 ret = i40e_get_hash_filter_global_config(hw,
10209                                 &(info->info.global_conf));
10210                 break;
10211         default:
10212                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10213                                                         info->info_type);
10214                 ret = -EINVAL;
10215                 break;
10216         }
10217
10218         return ret;
10219 }
10220
10221 static int
10222 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10223 {
10224         int ret = 0;
10225
10226         if (!hw || !info) {
10227                 PMD_DRV_LOG(ERR, "Invalid pointer");
10228                 return -EFAULT;
10229         }
10230
10231         switch (info->info_type) {
10232         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10233                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10234                 break;
10235         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10236                 ret = i40e_set_hash_filter_global_config(hw,
10237                                 &(info->info.global_conf));
10238                 break;
10239         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10240                 ret = i40e_hash_filter_inset_select(hw,
10241                                                &(info->info.input_set_conf));
10242                 break;
10243
10244         default:
10245                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10246                                                         info->info_type);
10247                 ret = -EINVAL;
10248                 break;
10249         }
10250
10251         return ret;
10252 }
10253
10254 /* Operations for hash function */
10255 static int
10256 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10257                       enum rte_filter_op filter_op,
10258                       void *arg)
10259 {
10260         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10261         int ret = 0;
10262
10263         switch (filter_op) {
10264         case RTE_ETH_FILTER_NOP:
10265                 break;
10266         case RTE_ETH_FILTER_GET:
10267                 ret = i40e_hash_filter_get(hw,
10268                         (struct rte_eth_hash_filter_info *)arg);
10269                 break;
10270         case RTE_ETH_FILTER_SET:
10271                 ret = i40e_hash_filter_set(hw,
10272                         (struct rte_eth_hash_filter_info *)arg);
10273                 break;
10274         default:
10275                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10276                                                                 filter_op);
10277                 ret = -ENOTSUP;
10278                 break;
10279         }
10280
10281         return ret;
10282 }
10283
10284 /* Convert ethertype filter structure */
10285 static int
10286 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10287                               struct i40e_ethertype_filter *filter)
10288 {
10289         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10290                 RTE_ETHER_ADDR_LEN);
10291         filter->input.ether_type = input->ether_type;
10292         filter->flags = input->flags;
10293         filter->queue = input->queue;
10294
10295         return 0;
10296 }
10297
10298 /* Check if there exists the ehtertype filter */
10299 struct i40e_ethertype_filter *
10300 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10301                                 const struct i40e_ethertype_filter_input *input)
10302 {
10303         int ret;
10304
10305         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10306         if (ret < 0)
10307                 return NULL;
10308
10309         return ethertype_rule->hash_map[ret];
10310 }
10311
10312 /* Add ethertype filter in SW list */
10313 static int
10314 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10315                                 struct i40e_ethertype_filter *filter)
10316 {
10317         struct i40e_ethertype_rule *rule = &pf->ethertype;
10318         int ret;
10319
10320         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10321         if (ret < 0) {
10322                 PMD_DRV_LOG(ERR,
10323                             "Failed to insert ethertype filter"
10324                             " to hash table %d!",
10325                             ret);
10326                 return ret;
10327         }
10328         rule->hash_map[ret] = filter;
10329
10330         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10331
10332         return 0;
10333 }
10334
10335 /* Delete ethertype filter in SW list */
10336 int
10337 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10338                              struct i40e_ethertype_filter_input *input)
10339 {
10340         struct i40e_ethertype_rule *rule = &pf->ethertype;
10341         struct i40e_ethertype_filter *filter;
10342         int ret;
10343
10344         ret = rte_hash_del_key(rule->hash_table, input);
10345         if (ret < 0) {
10346                 PMD_DRV_LOG(ERR,
10347                             "Failed to delete ethertype filter"
10348                             " to hash table %d!",
10349                             ret);
10350                 return ret;
10351         }
10352         filter = rule->hash_map[ret];
10353         rule->hash_map[ret] = NULL;
10354
10355         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10356         rte_free(filter);
10357
10358         return 0;
10359 }
10360
10361 /*
10362  * Configure ethertype filter, which can director packet by filtering
10363  * with mac address and ether_type or only ether_type
10364  */
10365 int
10366 i40e_ethertype_filter_set(struct i40e_pf *pf,
10367                         struct rte_eth_ethertype_filter *filter,
10368                         bool add)
10369 {
10370         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10371         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10372         struct i40e_ethertype_filter *ethertype_filter, *node;
10373         struct i40e_ethertype_filter check_filter;
10374         struct i40e_control_filter_stats stats;
10375         uint16_t flags = 0;
10376         int ret;
10377
10378         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10379                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10380                 return -EINVAL;
10381         }
10382         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10383                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10384                 PMD_DRV_LOG(ERR,
10385                         "unsupported ether_type(0x%04x) in control packet filter.",
10386                         filter->ether_type);
10387                 return -EINVAL;
10388         }
10389         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10390                 PMD_DRV_LOG(WARNING,
10391                         "filter vlan ether_type in first tag is not supported.");
10392
10393         /* Check if there is the filter in SW list */
10394         memset(&check_filter, 0, sizeof(check_filter));
10395         i40e_ethertype_filter_convert(filter, &check_filter);
10396         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10397                                                &check_filter.input);
10398         if (add && node) {
10399                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10400                 return -EINVAL;
10401         }
10402
10403         if (!add && !node) {
10404                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10405                 return -EINVAL;
10406         }
10407
10408         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10409                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10410         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10411                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10412         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10413
10414         memset(&stats, 0, sizeof(stats));
10415         ret = i40e_aq_add_rem_control_packet_filter(hw,
10416                         filter->mac_addr.addr_bytes,
10417                         filter->ether_type, flags,
10418                         pf->main_vsi->seid,
10419                         filter->queue, add, &stats, NULL);
10420
10421         PMD_DRV_LOG(INFO,
10422                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10423                 ret, stats.mac_etype_used, stats.etype_used,
10424                 stats.mac_etype_free, stats.etype_free);
10425         if (ret < 0)
10426                 return -ENOSYS;
10427
10428         /* Add or delete a filter in SW list */
10429         if (add) {
10430                 ethertype_filter = rte_zmalloc("ethertype_filter",
10431                                        sizeof(*ethertype_filter), 0);
10432                 if (ethertype_filter == NULL) {
10433                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10434                         return -ENOMEM;
10435                 }
10436
10437                 rte_memcpy(ethertype_filter, &check_filter,
10438                            sizeof(check_filter));
10439                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10440                 if (ret < 0)
10441                         rte_free(ethertype_filter);
10442         } else {
10443                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10444         }
10445
10446         return ret;
10447 }
10448
10449 static int
10450 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10451                      enum rte_filter_type filter_type,
10452                      enum rte_filter_op filter_op,
10453                      void *arg)
10454 {
10455         int ret = 0;
10456
10457         if (dev == NULL)
10458                 return -EINVAL;
10459
10460         switch (filter_type) {
10461         case RTE_ETH_FILTER_NONE:
10462                 /* For global configuration */
10463                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10464                 break;
10465         case RTE_ETH_FILTER_HASH:
10466                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10467                 break;
10468         case RTE_ETH_FILTER_TUNNEL:
10469                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10470                 break;
10471         case RTE_ETH_FILTER_FDIR:
10472                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10473                 break;
10474         case RTE_ETH_FILTER_GENERIC:
10475                 if (filter_op != RTE_ETH_FILTER_GET)
10476                         return -EINVAL;
10477                 *(const void **)arg = &i40e_flow_ops;
10478                 break;
10479         default:
10480                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10481                                                         filter_type);
10482                 ret = -EINVAL;
10483                 break;
10484         }
10485
10486         return ret;
10487 }
10488
10489 /*
10490  * Check and enable Extended Tag.
10491  * Enabling Extended Tag is important for 40G performance.
10492  */
10493 static void
10494 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10495 {
10496         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10497         uint32_t buf = 0;
10498         int ret;
10499
10500         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10501                                       PCI_DEV_CAP_REG);
10502         if (ret < 0) {
10503                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10504                             PCI_DEV_CAP_REG);
10505                 return;
10506         }
10507         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10508                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10509                 return;
10510         }
10511
10512         buf = 0;
10513         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10514                                       PCI_DEV_CTRL_REG);
10515         if (ret < 0) {
10516                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10517                             PCI_DEV_CTRL_REG);
10518                 return;
10519         }
10520         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10521                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10522                 return;
10523         }
10524         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10525         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10526                                        PCI_DEV_CTRL_REG);
10527         if (ret < 0) {
10528                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10529                             PCI_DEV_CTRL_REG);
10530                 return;
10531         }
10532 }
10533
10534 /*
10535  * As some registers wouldn't be reset unless a global hardware reset,
10536  * hardware initialization is needed to put those registers into an
10537  * expected initial state.
10538  */
10539 static void
10540 i40e_hw_init(struct rte_eth_dev *dev)
10541 {
10542         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10543
10544         i40e_enable_extended_tag(dev);
10545
10546         /* clear the PF Queue Filter control register */
10547         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10548
10549         /* Disable symmetric hash per port */
10550         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10551 }
10552
10553 /*
10554  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10555  * however this function will return only one highest pctype index,
10556  * which is not quite correct. This is known problem of i40e driver
10557  * and needs to be fixed later.
10558  */
10559 enum i40e_filter_pctype
10560 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10561 {
10562         int i;
10563         uint64_t pctype_mask;
10564
10565         if (flow_type < I40E_FLOW_TYPE_MAX) {
10566                 pctype_mask = adapter->pctypes_tbl[flow_type];
10567                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10568                         if (pctype_mask & (1ULL << i))
10569                                 return (enum i40e_filter_pctype)i;
10570                 }
10571         }
10572         return I40E_FILTER_PCTYPE_INVALID;
10573 }
10574
10575 uint16_t
10576 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10577                         enum i40e_filter_pctype pctype)
10578 {
10579         uint16_t flowtype;
10580         uint64_t pctype_mask = 1ULL << pctype;
10581
10582         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10583              flowtype++) {
10584                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10585                         return flowtype;
10586         }
10587
10588         return RTE_ETH_FLOW_UNKNOWN;
10589 }
10590
10591 /*
10592  * On X710, performance number is far from the expectation on recent firmware
10593  * versions; on XL710, performance number is also far from the expectation on
10594  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10595  * mode is enabled and port MAC address is equal to the packet destination MAC
10596  * address. The fix for this issue may not be integrated in the following
10597  * firmware version. So the workaround in software driver is needed. It needs
10598  * to modify the initial values of 3 internal only registers for both X710 and
10599  * XL710. Note that the values for X710 or XL710 could be different, and the
10600  * workaround can be removed when it is fixed in firmware in the future.
10601  */
10602
10603 /* For both X710 and XL710 */
10604 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10605 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10606 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10607
10608 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10609 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10610
10611 /* For X722 */
10612 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10613 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10614
10615 /* For X710 */
10616 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10617 /* For XL710 */
10618 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10619 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10620
10621 /*
10622  * GL_SWR_PM_UP_THR:
10623  * The value is not impacted from the link speed, its value is set according
10624  * to the total number of ports for a better pipe-monitor configuration.
10625  */
10626 static bool
10627 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10628 {
10629 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10630                 .device_id = (dev),   \
10631                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10632
10633 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10634                 .device_id = (dev),   \
10635                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10636
10637         static const struct {
10638                 uint16_t device_id;
10639                 uint32_t val;
10640         } swr_pm_table[] = {
10641                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10642                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10643                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10644                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10645                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10646
10647                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10648                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10649                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10650                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10651                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10652                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10653                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10654         };
10655         uint32_t i;
10656
10657         if (value == NULL) {
10658                 PMD_DRV_LOG(ERR, "value is NULL");
10659                 return false;
10660         }
10661
10662         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10663                 if (hw->device_id == swr_pm_table[i].device_id) {
10664                         *value = swr_pm_table[i].val;
10665
10666                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10667                                     "value - 0x%08x",
10668                                     hw->device_id, *value);
10669                         return true;
10670                 }
10671         }
10672
10673         return false;
10674 }
10675
10676 static int
10677 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10678 {
10679         enum i40e_status_code status;
10680         struct i40e_aq_get_phy_abilities_resp phy_ab;
10681         int ret = -ENOTSUP;
10682         int retries = 0;
10683
10684         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10685                                               NULL);
10686
10687         while (status) {
10688                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10689                         status);
10690                 retries++;
10691                 rte_delay_us(100000);
10692                 if  (retries < 5)
10693                         status = i40e_aq_get_phy_capabilities(hw, false,
10694                                         true, &phy_ab, NULL);
10695                 else
10696                         return ret;
10697         }
10698         return 0;
10699 }
10700
10701 static void
10702 i40e_configure_registers(struct i40e_hw *hw)
10703 {
10704         static struct {
10705                 uint32_t addr;
10706                 uint64_t val;
10707         } reg_table[] = {
10708                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10709                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10710                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10711         };
10712         uint64_t reg;
10713         uint32_t i;
10714         int ret;
10715
10716         for (i = 0; i < RTE_DIM(reg_table); i++) {
10717                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10718                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10719                                 reg_table[i].val =
10720                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10721                         else /* For X710/XL710/XXV710 */
10722                                 if (hw->aq.fw_maj_ver < 6)
10723                                         reg_table[i].val =
10724                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10725                                 else
10726                                         reg_table[i].val =
10727                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10728                 }
10729
10730                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10731                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10732                                 reg_table[i].val =
10733                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10734                         else /* For X710/XL710/XXV710 */
10735                                 reg_table[i].val =
10736                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10737                 }
10738
10739                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10740                         uint32_t cfg_val;
10741
10742                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10743                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10744                                             "GL_SWR_PM_UP_THR value fixup",
10745                                             hw->device_id);
10746                                 continue;
10747                         }
10748
10749                         reg_table[i].val = cfg_val;
10750                 }
10751
10752                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10753                                                         &reg, NULL);
10754                 if (ret < 0) {
10755                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10756                                                         reg_table[i].addr);
10757                         break;
10758                 }
10759                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10760                                                 reg_table[i].addr, reg);
10761                 if (reg == reg_table[i].val)
10762                         continue;
10763
10764                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10765                                                 reg_table[i].val, NULL);
10766                 if (ret < 0) {
10767                         PMD_DRV_LOG(ERR,
10768                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10769                                 reg_table[i].val, reg_table[i].addr);
10770                         break;
10771                 }
10772                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10773                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10774         }
10775 }
10776
10777 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10778 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10779 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10780 static int
10781 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10782 {
10783         uint32_t reg;
10784         int ret;
10785
10786         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10787                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10788                 return -EINVAL;
10789         }
10790
10791         /* Configure for double VLAN RX stripping */
10792         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10793         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10794                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10795                 ret = i40e_aq_debug_write_register(hw,
10796                                                    I40E_VSI_TSR(vsi->vsi_id),
10797                                                    reg, NULL);
10798                 if (ret < 0) {
10799                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10800                                     vsi->vsi_id);
10801                         return I40E_ERR_CONFIG;
10802                 }
10803         }
10804
10805         /* Configure for double VLAN TX insertion */
10806         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10807         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10808                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10809                 ret = i40e_aq_debug_write_register(hw,
10810                                                    I40E_VSI_L2TAGSTXVALID(
10811                                                    vsi->vsi_id), reg, NULL);
10812                 if (ret < 0) {
10813                         PMD_DRV_LOG(ERR,
10814                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10815                                 vsi->vsi_id);
10816                         return I40E_ERR_CONFIG;
10817                 }
10818         }
10819
10820         return 0;
10821 }
10822
10823 /**
10824  * i40e_aq_add_mirror_rule
10825  * @hw: pointer to the hardware structure
10826  * @seid: VEB seid to add mirror rule to
10827  * @dst_id: destination vsi seid
10828  * @entries: Buffer which contains the entities to be mirrored
10829  * @count: number of entities contained in the buffer
10830  * @rule_id:the rule_id of the rule to be added
10831  *
10832  * Add a mirror rule for a given veb.
10833  *
10834  **/
10835 static enum i40e_status_code
10836 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10837                         uint16_t seid, uint16_t dst_id,
10838                         uint16_t rule_type, uint16_t *entries,
10839                         uint16_t count, uint16_t *rule_id)
10840 {
10841         struct i40e_aq_desc desc;
10842         struct i40e_aqc_add_delete_mirror_rule cmd;
10843         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10844                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10845                 &desc.params.raw;
10846         uint16_t buff_len;
10847         enum i40e_status_code status;
10848
10849         i40e_fill_default_direct_cmd_desc(&desc,
10850                                           i40e_aqc_opc_add_mirror_rule);
10851         memset(&cmd, 0, sizeof(cmd));
10852
10853         buff_len = sizeof(uint16_t) * count;
10854         desc.datalen = rte_cpu_to_le_16(buff_len);
10855         if (buff_len > 0)
10856                 desc.flags |= rte_cpu_to_le_16(
10857                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10858         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10859                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10860         cmd.num_entries = rte_cpu_to_le_16(count);
10861         cmd.seid = rte_cpu_to_le_16(seid);
10862         cmd.destination = rte_cpu_to_le_16(dst_id);
10863
10864         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10865         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10866         PMD_DRV_LOG(INFO,
10867                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10868                 hw->aq.asq_last_status, resp->rule_id,
10869                 resp->mirror_rules_used, resp->mirror_rules_free);
10870         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10871
10872         return status;
10873 }
10874
10875 /**
10876  * i40e_aq_del_mirror_rule
10877  * @hw: pointer to the hardware structure
10878  * @seid: VEB seid to add mirror rule to
10879  * @entries: Buffer which contains the entities to be mirrored
10880  * @count: number of entities contained in the buffer
10881  * @rule_id:the rule_id of the rule to be delete
10882  *
10883  * Delete a mirror rule for a given veb.
10884  *
10885  **/
10886 static enum i40e_status_code
10887 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10888                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10889                 uint16_t count, uint16_t rule_id)
10890 {
10891         struct i40e_aq_desc desc;
10892         struct i40e_aqc_add_delete_mirror_rule cmd;
10893         uint16_t buff_len = 0;
10894         enum i40e_status_code status;
10895         void *buff = NULL;
10896
10897         i40e_fill_default_direct_cmd_desc(&desc,
10898                                           i40e_aqc_opc_delete_mirror_rule);
10899         memset(&cmd, 0, sizeof(cmd));
10900         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10901                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10902                                                           I40E_AQ_FLAG_RD));
10903                 cmd.num_entries = count;
10904                 buff_len = sizeof(uint16_t) * count;
10905                 desc.datalen = rte_cpu_to_le_16(buff_len);
10906                 buff = (void *)entries;
10907         } else
10908                 /* rule id is filled in destination field for deleting mirror rule */
10909                 cmd.destination = rte_cpu_to_le_16(rule_id);
10910
10911         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10912                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10913         cmd.seid = rte_cpu_to_le_16(seid);
10914
10915         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10916         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10917
10918         return status;
10919 }
10920
10921 /**
10922  * i40e_mirror_rule_set
10923  * @dev: pointer to the hardware structure
10924  * @mirror_conf: mirror rule info
10925  * @sw_id: mirror rule's sw_id
10926  * @on: enable/disable
10927  *
10928  * set a mirror rule.
10929  *
10930  **/
10931 static int
10932 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10933                         struct rte_eth_mirror_conf *mirror_conf,
10934                         uint8_t sw_id, uint8_t on)
10935 {
10936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10938         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10939         struct i40e_mirror_rule *parent = NULL;
10940         uint16_t seid, dst_seid, rule_id;
10941         uint16_t i, j = 0;
10942         int ret;
10943
10944         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10945
10946         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10947                 PMD_DRV_LOG(ERR,
10948                         "mirror rule can not be configured without veb or vfs.");
10949                 return -ENOSYS;
10950         }
10951         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10952                 PMD_DRV_LOG(ERR, "mirror table is full.");
10953                 return -ENOSPC;
10954         }
10955         if (mirror_conf->dst_pool > pf->vf_num) {
10956                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10957                                  mirror_conf->dst_pool);
10958                 return -EINVAL;
10959         }
10960
10961         seid = pf->main_vsi->veb->seid;
10962
10963         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10964                 if (sw_id <= it->index) {
10965                         mirr_rule = it;
10966                         break;
10967                 }
10968                 parent = it;
10969         }
10970         if (mirr_rule && sw_id == mirr_rule->index) {
10971                 if (on) {
10972                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10973                         return -EEXIST;
10974                 } else {
10975                         ret = i40e_aq_del_mirror_rule(hw, seid,
10976                                         mirr_rule->rule_type,
10977                                         mirr_rule->entries,
10978                                         mirr_rule->num_entries, mirr_rule->id);
10979                         if (ret < 0) {
10980                                 PMD_DRV_LOG(ERR,
10981                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10982                                         ret, hw->aq.asq_last_status);
10983                                 return -ENOSYS;
10984                         }
10985                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10986                         rte_free(mirr_rule);
10987                         pf->nb_mirror_rule--;
10988                         return 0;
10989                 }
10990         } else if (!on) {
10991                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10992                 return -ENOENT;
10993         }
10994
10995         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10996                                 sizeof(struct i40e_mirror_rule) , 0);
10997         if (!mirr_rule) {
10998                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10999                 return I40E_ERR_NO_MEMORY;
11000         }
11001         switch (mirror_conf->rule_type) {
11002         case ETH_MIRROR_VLAN:
11003                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11004                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11005                                 mirr_rule->entries[j] =
11006                                         mirror_conf->vlan.vlan_id[i];
11007                                 j++;
11008                         }
11009                 }
11010                 if (j == 0) {
11011                         PMD_DRV_LOG(ERR, "vlan is not specified.");
11012                         rte_free(mirr_rule);
11013                         return -EINVAL;
11014                 }
11015                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11016                 break;
11017         case ETH_MIRROR_VIRTUAL_POOL_UP:
11018         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11019                 /* check if the specified pool bit is out of range */
11020                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11021                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
11022                         rte_free(mirr_rule);
11023                         return -EINVAL;
11024                 }
11025                 for (i = 0, j = 0; i < pf->vf_num; i++) {
11026                         if (mirror_conf->pool_mask & (1ULL << i)) {
11027                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11028                                 j++;
11029                         }
11030                 }
11031                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11032                         /* add pf vsi to entries */
11033                         mirr_rule->entries[j] = pf->main_vsi_seid;
11034                         j++;
11035                 }
11036                 if (j == 0) {
11037                         PMD_DRV_LOG(ERR, "pool is not specified.");
11038                         rte_free(mirr_rule);
11039                         return -EINVAL;
11040                 }
11041                 /* egress and ingress in aq commands means from switch but not port */
11042                 mirr_rule->rule_type =
11043                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11044                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11045                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11046                 break;
11047         case ETH_MIRROR_UPLINK_PORT:
11048                 /* egress and ingress in aq commands means from switch but not port*/
11049                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11050                 break;
11051         case ETH_MIRROR_DOWNLINK_PORT:
11052                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11053                 break;
11054         default:
11055                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11056                         mirror_conf->rule_type);
11057                 rte_free(mirr_rule);
11058                 return -EINVAL;
11059         }
11060
11061         /* If the dst_pool is equal to vf_num, consider it as PF */
11062         if (mirror_conf->dst_pool == pf->vf_num)
11063                 dst_seid = pf->main_vsi_seid;
11064         else
11065                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11066
11067         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11068                                       mirr_rule->rule_type, mirr_rule->entries,
11069                                       j, &rule_id);
11070         if (ret < 0) {
11071                 PMD_DRV_LOG(ERR,
11072                         "failed to add mirror rule: ret = %d, aq_err = %d.",
11073                         ret, hw->aq.asq_last_status);
11074                 rte_free(mirr_rule);
11075                 return -ENOSYS;
11076         }
11077
11078         mirr_rule->index = sw_id;
11079         mirr_rule->num_entries = j;
11080         mirr_rule->id = rule_id;
11081         mirr_rule->dst_vsi_seid = dst_seid;
11082
11083         if (parent)
11084                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11085         else
11086                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11087
11088         pf->nb_mirror_rule++;
11089         return 0;
11090 }
11091
11092 /**
11093  * i40e_mirror_rule_reset
11094  * @dev: pointer to the device
11095  * @sw_id: mirror rule's sw_id
11096  *
11097  * reset a mirror rule.
11098  *
11099  **/
11100 static int
11101 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11102 {
11103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11105         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11106         uint16_t seid;
11107         int ret;
11108
11109         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11110
11111         seid = pf->main_vsi->veb->seid;
11112
11113         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11114                 if (sw_id == it->index) {
11115                         mirr_rule = it;
11116                         break;
11117                 }
11118         }
11119         if (mirr_rule) {
11120                 ret = i40e_aq_del_mirror_rule(hw, seid,
11121                                 mirr_rule->rule_type,
11122                                 mirr_rule->entries,
11123                                 mirr_rule->num_entries, mirr_rule->id);
11124                 if (ret < 0) {
11125                         PMD_DRV_LOG(ERR,
11126                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
11127                                 ret, hw->aq.asq_last_status);
11128                         return -ENOSYS;
11129                 }
11130                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11131                 rte_free(mirr_rule);
11132                 pf->nb_mirror_rule--;
11133         } else {
11134                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11135                 return -ENOENT;
11136         }
11137         return 0;
11138 }
11139
11140 static uint64_t
11141 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11142 {
11143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11144         uint64_t systim_cycles;
11145
11146         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11147         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11148                         << 32;
11149
11150         return systim_cycles;
11151 }
11152
11153 static uint64_t
11154 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11155 {
11156         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11157         uint64_t rx_tstamp;
11158
11159         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11160         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11161                         << 32;
11162
11163         return rx_tstamp;
11164 }
11165
11166 static uint64_t
11167 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11168 {
11169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11170         uint64_t tx_tstamp;
11171
11172         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11173         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11174                         << 32;
11175
11176         return tx_tstamp;
11177 }
11178
11179 static void
11180 i40e_start_timecounters(struct rte_eth_dev *dev)
11181 {
11182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11183         struct i40e_adapter *adapter = dev->data->dev_private;
11184         struct rte_eth_link link;
11185         uint32_t tsync_inc_l;
11186         uint32_t tsync_inc_h;
11187
11188         /* Get current link speed. */
11189         i40e_dev_link_update(dev, 1);
11190         rte_eth_linkstatus_get(dev, &link);
11191
11192         switch (link.link_speed) {
11193         case ETH_SPEED_NUM_40G:
11194         case ETH_SPEED_NUM_25G:
11195                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11196                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11197                 break;
11198         case ETH_SPEED_NUM_10G:
11199                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11200                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11201                 break;
11202         case ETH_SPEED_NUM_1G:
11203                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11204                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11205                 break;
11206         default:
11207                 tsync_inc_l = 0x0;
11208                 tsync_inc_h = 0x0;
11209         }
11210
11211         /* Set the timesync increment value. */
11212         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11213         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11214
11215         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11216         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11217         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11218
11219         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11220         adapter->systime_tc.cc_shift = 0;
11221         adapter->systime_tc.nsec_mask = 0;
11222
11223         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11224         adapter->rx_tstamp_tc.cc_shift = 0;
11225         adapter->rx_tstamp_tc.nsec_mask = 0;
11226
11227         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11228         adapter->tx_tstamp_tc.cc_shift = 0;
11229         adapter->tx_tstamp_tc.nsec_mask = 0;
11230 }
11231
11232 static int
11233 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11234 {
11235         struct i40e_adapter *adapter = dev->data->dev_private;
11236
11237         adapter->systime_tc.nsec += delta;
11238         adapter->rx_tstamp_tc.nsec += delta;
11239         adapter->tx_tstamp_tc.nsec += delta;
11240
11241         return 0;
11242 }
11243
11244 static int
11245 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11246 {
11247         uint64_t ns;
11248         struct i40e_adapter *adapter = dev->data->dev_private;
11249
11250         ns = rte_timespec_to_ns(ts);
11251
11252         /* Set the timecounters to a new value. */
11253         adapter->systime_tc.nsec = ns;
11254         adapter->rx_tstamp_tc.nsec = ns;
11255         adapter->tx_tstamp_tc.nsec = ns;
11256
11257         return 0;
11258 }
11259
11260 static int
11261 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11262 {
11263         uint64_t ns, systime_cycles;
11264         struct i40e_adapter *adapter = dev->data->dev_private;
11265
11266         systime_cycles = i40e_read_systime_cyclecounter(dev);
11267         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11268         *ts = rte_ns_to_timespec(ns);
11269
11270         return 0;
11271 }
11272
11273 static int
11274 i40e_timesync_enable(struct rte_eth_dev *dev)
11275 {
11276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11277         uint32_t tsync_ctl_l;
11278         uint32_t tsync_ctl_h;
11279
11280         /* Stop the timesync system time. */
11281         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11282         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11283         /* Reset the timesync system time value. */
11284         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11285         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11286
11287         i40e_start_timecounters(dev);
11288
11289         /* Clear timesync registers. */
11290         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11291         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11292         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11293         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11294         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11295         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11296
11297         /* Enable timestamping of PTP packets. */
11298         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11299         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11300
11301         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11302         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11303         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11304
11305         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11306         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11307
11308         return 0;
11309 }
11310
11311 static int
11312 i40e_timesync_disable(struct rte_eth_dev *dev)
11313 {
11314         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11315         uint32_t tsync_ctl_l;
11316         uint32_t tsync_ctl_h;
11317
11318         /* Disable timestamping of transmitted PTP packets. */
11319         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11320         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11321
11322         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11323         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11324
11325         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11326         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11327
11328         /* Reset the timesync increment value. */
11329         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11330         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11331
11332         return 0;
11333 }
11334
11335 static int
11336 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11337                                 struct timespec *timestamp, uint32_t flags)
11338 {
11339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11340         struct i40e_adapter *adapter = dev->data->dev_private;
11341         uint32_t sync_status;
11342         uint32_t index = flags & 0x03;
11343         uint64_t rx_tstamp_cycles;
11344         uint64_t ns;
11345
11346         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11347         if ((sync_status & (1 << index)) == 0)
11348                 return -EINVAL;
11349
11350         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11351         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11352         *timestamp = rte_ns_to_timespec(ns);
11353
11354         return 0;
11355 }
11356
11357 static int
11358 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11359                                 struct timespec *timestamp)
11360 {
11361         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11362         struct i40e_adapter *adapter = dev->data->dev_private;
11363         uint32_t sync_status;
11364         uint64_t tx_tstamp_cycles;
11365         uint64_t ns;
11366
11367         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11368         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11369                 return -EINVAL;
11370
11371         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11372         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11373         *timestamp = rte_ns_to_timespec(ns);
11374
11375         return 0;
11376 }
11377
11378 /*
11379  * i40e_parse_dcb_configure - parse dcb configure from user
11380  * @dev: the device being configured
11381  * @dcb_cfg: pointer of the result of parse
11382  * @*tc_map: bit map of enabled traffic classes
11383  *
11384  * Returns 0 on success, negative value on failure
11385  */
11386 static int
11387 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11388                          struct i40e_dcbx_config *dcb_cfg,
11389                          uint8_t *tc_map)
11390 {
11391         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11392         uint8_t i, tc_bw, bw_lf;
11393
11394         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11395
11396         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11397         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11398                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11399                 return -EINVAL;
11400         }
11401
11402         /* assume each tc has the same bw */
11403         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11404         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11405                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11406         /* to ensure the sum of tcbw is equal to 100 */
11407         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11408         for (i = 0; i < bw_lf; i++)
11409                 dcb_cfg->etscfg.tcbwtable[i]++;
11410
11411         /* assume each tc has the same Transmission Selection Algorithm */
11412         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11413                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11414
11415         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11416                 dcb_cfg->etscfg.prioritytable[i] =
11417                                 dcb_rx_conf->dcb_tc[i];
11418
11419         /* FW needs one App to configure HW */
11420         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11421         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11422         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11423         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11424
11425         if (dcb_rx_conf->nb_tcs == 0)
11426                 *tc_map = 1; /* tc0 only */
11427         else
11428                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11429
11430         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11431                 dcb_cfg->pfc.willing = 0;
11432                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11433                 dcb_cfg->pfc.pfcenable = *tc_map;
11434         }
11435         return 0;
11436 }
11437
11438
11439 static enum i40e_status_code
11440 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11441                               struct i40e_aqc_vsi_properties_data *info,
11442                               uint8_t enabled_tcmap)
11443 {
11444         enum i40e_status_code ret;
11445         int i, total_tc = 0;
11446         uint16_t qpnum_per_tc, bsf, qp_idx;
11447         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11448         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11449         uint16_t used_queues;
11450
11451         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11452         if (ret != I40E_SUCCESS)
11453                 return ret;
11454
11455         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11456                 if (enabled_tcmap & (1 << i))
11457                         total_tc++;
11458         }
11459         if (total_tc == 0)
11460                 total_tc = 1;
11461         vsi->enabled_tc = enabled_tcmap;
11462
11463         /* different VSI has different queues assigned */
11464         if (vsi->type == I40E_VSI_MAIN)
11465                 used_queues = dev_data->nb_rx_queues -
11466                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11467         else if (vsi->type == I40E_VSI_VMDQ2)
11468                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11469         else {
11470                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11471                 return I40E_ERR_NO_AVAILABLE_VSI;
11472         }
11473
11474         qpnum_per_tc = used_queues / total_tc;
11475         /* Number of queues per enabled TC */
11476         if (qpnum_per_tc == 0) {
11477                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11478                 return I40E_ERR_INVALID_QP_ID;
11479         }
11480         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11481                                 I40E_MAX_Q_PER_TC);
11482         bsf = rte_bsf32(qpnum_per_tc);
11483
11484         /**
11485          * Configure TC and queue mapping parameters, for enabled TC,
11486          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11487          * default queue will serve it.
11488          */
11489         qp_idx = 0;
11490         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11491                 if (vsi->enabled_tc & (1 << i)) {
11492                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11493                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11494                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11495                         qp_idx += qpnum_per_tc;
11496                 } else
11497                         info->tc_mapping[i] = 0;
11498         }
11499
11500         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11501         if (vsi->type == I40E_VSI_SRIOV) {
11502                 info->mapping_flags |=
11503                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11504                 for (i = 0; i < vsi->nb_qps; i++)
11505                         info->queue_mapping[i] =
11506                                 rte_cpu_to_le_16(vsi->base_queue + i);
11507         } else {
11508                 info->mapping_flags |=
11509                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11510                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11511         }
11512         info->valid_sections |=
11513                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11514
11515         return I40E_SUCCESS;
11516 }
11517
11518 /*
11519  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11520  * @veb: VEB to be configured
11521  * @tc_map: enabled TC bitmap
11522  *
11523  * Returns 0 on success, negative value on failure
11524  */
11525 static enum i40e_status_code
11526 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11527 {
11528         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11529         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11530         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11531         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11532         enum i40e_status_code ret = I40E_SUCCESS;
11533         int i;
11534         uint32_t bw_max;
11535
11536         /* Check if enabled_tc is same as existing or new TCs */
11537         if (veb->enabled_tc == tc_map)
11538                 return ret;
11539
11540         /* configure tc bandwidth */
11541         memset(&veb_bw, 0, sizeof(veb_bw));
11542         veb_bw.tc_valid_bits = tc_map;
11543         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11544         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11545                 if (tc_map & BIT_ULL(i))
11546                         veb_bw.tc_bw_share_credits[i] = 1;
11547         }
11548         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11549                                                    &veb_bw, NULL);
11550         if (ret) {
11551                 PMD_INIT_LOG(ERR,
11552                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11553                         hw->aq.asq_last_status);
11554                 return ret;
11555         }
11556
11557         memset(&ets_query, 0, sizeof(ets_query));
11558         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11559                                                    &ets_query, NULL);
11560         if (ret != I40E_SUCCESS) {
11561                 PMD_DRV_LOG(ERR,
11562                         "Failed to get switch_comp ETS configuration %u",
11563                         hw->aq.asq_last_status);
11564                 return ret;
11565         }
11566         memset(&bw_query, 0, sizeof(bw_query));
11567         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11568                                                   &bw_query, NULL);
11569         if (ret != I40E_SUCCESS) {
11570                 PMD_DRV_LOG(ERR,
11571                         "Failed to get switch_comp bandwidth configuration %u",
11572                         hw->aq.asq_last_status);
11573                 return ret;
11574         }
11575
11576         /* store and print out BW info */
11577         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11578         veb->bw_info.bw_max = ets_query.tc_bw_max;
11579         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11580         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11581         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11582                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11583                      I40E_16_BIT_WIDTH);
11584         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11585                 veb->bw_info.bw_ets_share_credits[i] =
11586                                 bw_query.tc_bw_share_credits[i];
11587                 veb->bw_info.bw_ets_credits[i] =
11588                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11589                 /* 4 bits per TC, 4th bit is reserved */
11590                 veb->bw_info.bw_ets_max[i] =
11591                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11592                                   RTE_LEN2MASK(3, uint8_t));
11593                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11594                             veb->bw_info.bw_ets_share_credits[i]);
11595                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11596                             veb->bw_info.bw_ets_credits[i]);
11597                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11598                             veb->bw_info.bw_ets_max[i]);
11599         }
11600
11601         veb->enabled_tc = tc_map;
11602
11603         return ret;
11604 }
11605
11606
11607 /*
11608  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11609  * @vsi: VSI to be configured
11610  * @tc_map: enabled TC bitmap
11611  *
11612  * Returns 0 on success, negative value on failure
11613  */
11614 static enum i40e_status_code
11615 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11616 {
11617         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11618         struct i40e_vsi_context ctxt;
11619         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11620         enum i40e_status_code ret = I40E_SUCCESS;
11621         int i;
11622
11623         /* Check if enabled_tc is same as existing or new TCs */
11624         if (vsi->enabled_tc == tc_map)
11625                 return ret;
11626
11627         /* configure tc bandwidth */
11628         memset(&bw_data, 0, sizeof(bw_data));
11629         bw_data.tc_valid_bits = tc_map;
11630         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11631         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11632                 if (tc_map & BIT_ULL(i))
11633                         bw_data.tc_bw_credits[i] = 1;
11634         }
11635         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11636         if (ret) {
11637                 PMD_INIT_LOG(ERR,
11638                         "AQ command Config VSI BW allocation per TC failed = %d",
11639                         hw->aq.asq_last_status);
11640                 goto out;
11641         }
11642         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11643                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11644
11645         /* Update Queue Pairs Mapping for currently enabled UPs */
11646         ctxt.seid = vsi->seid;
11647         ctxt.pf_num = hw->pf_id;
11648         ctxt.vf_num = 0;
11649         ctxt.uplink_seid = vsi->uplink_seid;
11650         ctxt.info = vsi->info;
11651         i40e_get_cap(hw);
11652         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11653         if (ret)
11654                 goto out;
11655
11656         /* Update the VSI after updating the VSI queue-mapping information */
11657         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11658         if (ret) {
11659                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11660                         hw->aq.asq_last_status);
11661                 goto out;
11662         }
11663         /* update the local VSI info with updated queue map */
11664         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11665                                         sizeof(vsi->info.tc_mapping));
11666         rte_memcpy(&vsi->info.queue_mapping,
11667                         &ctxt.info.queue_mapping,
11668                 sizeof(vsi->info.queue_mapping));
11669         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11670         vsi->info.valid_sections = 0;
11671
11672         /* query and update current VSI BW information */
11673         ret = i40e_vsi_get_bw_config(vsi);
11674         if (ret) {
11675                 PMD_INIT_LOG(ERR,
11676                          "Failed updating vsi bw info, err %s aq_err %s",
11677                          i40e_stat_str(hw, ret),
11678                          i40e_aq_str(hw, hw->aq.asq_last_status));
11679                 goto out;
11680         }
11681
11682         vsi->enabled_tc = tc_map;
11683
11684 out:
11685         return ret;
11686 }
11687
11688 /*
11689  * i40e_dcb_hw_configure - program the dcb setting to hw
11690  * @pf: pf the configuration is taken on
11691  * @new_cfg: new configuration
11692  * @tc_map: enabled TC bitmap
11693  *
11694  * Returns 0 on success, negative value on failure
11695  */
11696 static enum i40e_status_code
11697 i40e_dcb_hw_configure(struct i40e_pf *pf,
11698                       struct i40e_dcbx_config *new_cfg,
11699                       uint8_t tc_map)
11700 {
11701         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11702         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11703         struct i40e_vsi *main_vsi = pf->main_vsi;
11704         struct i40e_vsi_list *vsi_list;
11705         enum i40e_status_code ret;
11706         int i;
11707         uint32_t val;
11708
11709         /* Use the FW API if FW > v4.4*/
11710         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11711               (hw->aq.fw_maj_ver >= 5))) {
11712                 PMD_INIT_LOG(ERR,
11713                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11714                 return I40E_ERR_FIRMWARE_API_VERSION;
11715         }
11716
11717         /* Check if need reconfiguration */
11718         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11719                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11720                 return I40E_SUCCESS;
11721         }
11722
11723         /* Copy the new config to the current config */
11724         *old_cfg = *new_cfg;
11725         old_cfg->etsrec = old_cfg->etscfg;
11726         ret = i40e_set_dcb_config(hw);
11727         if (ret) {
11728                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11729                          i40e_stat_str(hw, ret),
11730                          i40e_aq_str(hw, hw->aq.asq_last_status));
11731                 return ret;
11732         }
11733         /* set receive Arbiter to RR mode and ETS scheme by default */
11734         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11735                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11736                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11737                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11738                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11739                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11740                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11741                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11742                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11743                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11744                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11745                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11746                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11747         }
11748         /* get local mib to check whether it is configured correctly */
11749         /* IEEE mode */
11750         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11751         /* Get Local DCB Config */
11752         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11753                                      &hw->local_dcbx_config);
11754
11755         /* if Veb is created, need to update TC of it at first */
11756         if (main_vsi->veb) {
11757                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11758                 if (ret)
11759                         PMD_INIT_LOG(WARNING,
11760                                  "Failed configuring TC for VEB seid=%d",
11761                                  main_vsi->veb->seid);
11762         }
11763         /* Update each VSI */
11764         i40e_vsi_config_tc(main_vsi, tc_map);
11765         if (main_vsi->veb) {
11766                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11767                         /* Beside main VSI and VMDQ VSIs, only enable default
11768                          * TC for other VSIs
11769                          */
11770                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11771                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11772                                                          tc_map);
11773                         else
11774                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11775                                                          I40E_DEFAULT_TCMAP);
11776                         if (ret)
11777                                 PMD_INIT_LOG(WARNING,
11778                                         "Failed configuring TC for VSI seid=%d",
11779                                         vsi_list->vsi->seid);
11780                         /* continue */
11781                 }
11782         }
11783         return I40E_SUCCESS;
11784 }
11785
11786 /*
11787  * i40e_dcb_init_configure - initial dcb config
11788  * @dev: device being configured
11789  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11790  *
11791  * Returns 0 on success, negative value on failure
11792  */
11793 int
11794 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11795 {
11796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11798         int i, ret = 0;
11799
11800         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11801                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11802                 return -ENOTSUP;
11803         }
11804
11805         /* DCB initialization:
11806          * Update DCB configuration from the Firmware and configure
11807          * LLDP MIB change event.
11808          */
11809         if (sw_dcb == TRUE) {
11810                 /* Stopping lldp is necessary for DPDK, but it will cause
11811                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11812                  * for successful initialization of DCB is that LLDP is
11813                  * enabled. So it is needed to start lldp before DCB init
11814                  * and stop it after initialization.
11815                  */
11816                 ret = i40e_aq_start_lldp(hw, true, NULL);
11817                 if (ret != I40E_SUCCESS)
11818                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11819
11820                 ret = i40e_init_dcb(hw, true);
11821                 /* If lldp agent is stopped, the return value from
11822                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11823                  * adminq status. Otherwise, it should return success.
11824                  */
11825                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11826                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11827                         memset(&hw->local_dcbx_config, 0,
11828                                 sizeof(struct i40e_dcbx_config));
11829                         /* set dcb default configuration */
11830                         hw->local_dcbx_config.etscfg.willing = 0;
11831                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11832                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11833                         hw->local_dcbx_config.etscfg.tsatable[0] =
11834                                                 I40E_IEEE_TSA_ETS;
11835                         /* all UPs mapping to TC0 */
11836                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11837                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11838                         hw->local_dcbx_config.etsrec =
11839                                 hw->local_dcbx_config.etscfg;
11840                         hw->local_dcbx_config.pfc.willing = 0;
11841                         hw->local_dcbx_config.pfc.pfccap =
11842                                                 I40E_MAX_TRAFFIC_CLASS;
11843                         /* FW needs one App to configure HW */
11844                         hw->local_dcbx_config.numapps = 1;
11845                         hw->local_dcbx_config.app[0].selector =
11846                                                 I40E_APP_SEL_ETHTYPE;
11847                         hw->local_dcbx_config.app[0].priority = 3;
11848                         hw->local_dcbx_config.app[0].protocolid =
11849                                                 I40E_APP_PROTOID_FCOE;
11850                         ret = i40e_set_dcb_config(hw);
11851                         if (ret) {
11852                                 PMD_INIT_LOG(ERR,
11853                                         "default dcb config fails. err = %d, aq_err = %d.",
11854                                         ret, hw->aq.asq_last_status);
11855                                 return -ENOSYS;
11856                         }
11857                 } else {
11858                         PMD_INIT_LOG(ERR,
11859                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11860                                 ret, hw->aq.asq_last_status);
11861                         return -ENOTSUP;
11862                 }
11863
11864                 if (i40e_need_stop_lldp(dev)) {
11865                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11866                         if (ret != I40E_SUCCESS)
11867                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11868                 }
11869         } else {
11870                 ret = i40e_aq_start_lldp(hw, true, NULL);
11871                 if (ret != I40E_SUCCESS)
11872                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11873
11874                 ret = i40e_init_dcb(hw, true);
11875                 if (!ret) {
11876                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11877                                 PMD_INIT_LOG(ERR,
11878                                         "HW doesn't support DCBX offload.");
11879                                 return -ENOTSUP;
11880                         }
11881                 } else {
11882                         PMD_INIT_LOG(ERR,
11883                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11884                                 ret, hw->aq.asq_last_status);
11885                         return -ENOTSUP;
11886                 }
11887         }
11888         return 0;
11889 }
11890
11891 /*
11892  * i40e_dcb_setup - setup dcb related config
11893  * @dev: device being configured
11894  *
11895  * Returns 0 on success, negative value on failure
11896  */
11897 static int
11898 i40e_dcb_setup(struct rte_eth_dev *dev)
11899 {
11900         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11901         struct i40e_dcbx_config dcb_cfg;
11902         uint8_t tc_map = 0;
11903         int ret = 0;
11904
11905         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11906                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11907                 return -ENOTSUP;
11908         }
11909
11910         if (pf->vf_num != 0)
11911                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11912
11913         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11914         if (ret) {
11915                 PMD_INIT_LOG(ERR, "invalid dcb config");
11916                 return -EINVAL;
11917         }
11918         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11919         if (ret) {
11920                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11921                 return -ENOSYS;
11922         }
11923
11924         return 0;
11925 }
11926
11927 static int
11928 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11929                       struct rte_eth_dcb_info *dcb_info)
11930 {
11931         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11933         struct i40e_vsi *vsi = pf->main_vsi;
11934         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11935         uint16_t bsf, tc_mapping;
11936         int i, j = 0;
11937
11938         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11939                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11940         else
11941                 dcb_info->nb_tcs = 1;
11942         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11943                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11944         for (i = 0; i < dcb_info->nb_tcs; i++)
11945                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11946
11947         /* get queue mapping if vmdq is disabled */
11948         if (!pf->nb_cfg_vmdq_vsi) {
11949                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11950                         if (!(vsi->enabled_tc & (1 << i)))
11951                                 continue;
11952                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11953                         dcb_info->tc_queue.tc_rxq[j][i].base =
11954                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11955                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11956                         dcb_info->tc_queue.tc_txq[j][i].base =
11957                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11958                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11959                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11960                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11961                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11962                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11963                 }
11964                 return 0;
11965         }
11966
11967         /* get queue mapping if vmdq is enabled */
11968         do {
11969                 vsi = pf->vmdq[j].vsi;
11970                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11971                         if (!(vsi->enabled_tc & (1 << i)))
11972                                 continue;
11973                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11974                         dcb_info->tc_queue.tc_rxq[j][i].base =
11975                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11976                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11977                         dcb_info->tc_queue.tc_txq[j][i].base =
11978                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11979                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11980                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11981                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11982                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11983                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11984                 }
11985                 j++;
11986         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11987         return 0;
11988 }
11989
11990 static int
11991 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11992 {
11993         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11994         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11995         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11996         uint16_t msix_intr;
11997
11998         msix_intr = intr_handle->intr_vec[queue_id];
11999         if (msix_intr == I40E_MISC_VEC_ID)
12000                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12001                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
12002                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12003                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12004         else
12005                 I40E_WRITE_REG(hw,
12006                                I40E_PFINT_DYN_CTLN(msix_intr -
12007                                                    I40E_RX_VEC_START),
12008                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
12009                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12010                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12011
12012         I40E_WRITE_FLUSH(hw);
12013         rte_intr_ack(&pci_dev->intr_handle);
12014
12015         return 0;
12016 }
12017
12018 static int
12019 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12020 {
12021         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12022         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12023         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12024         uint16_t msix_intr;
12025
12026         msix_intr = intr_handle->intr_vec[queue_id];
12027         if (msix_intr == I40E_MISC_VEC_ID)
12028                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12029                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12030         else
12031                 I40E_WRITE_REG(hw,
12032                                I40E_PFINT_DYN_CTLN(msix_intr -
12033                                                    I40E_RX_VEC_START),
12034                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12035         I40E_WRITE_FLUSH(hw);
12036
12037         return 0;
12038 }
12039
12040 /**
12041  * This function is used to check if the register is valid.
12042  * Below is the valid registers list for X722 only:
12043  * 0x2b800--0x2bb00
12044  * 0x38700--0x38a00
12045  * 0x3d800--0x3db00
12046  * 0x208e00--0x209000
12047  * 0x20be00--0x20c000
12048  * 0x263c00--0x264000
12049  * 0x265c00--0x266000
12050  */
12051 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12052 {
12053         if ((type != I40E_MAC_X722) &&
12054             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12055              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12056              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12057              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12058              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12059              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12060              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12061                 return 0;
12062         else
12063                 return 1;
12064 }
12065
12066 static int i40e_get_regs(struct rte_eth_dev *dev,
12067                          struct rte_dev_reg_info *regs)
12068 {
12069         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12070         uint32_t *ptr_data = regs->data;
12071         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12072         const struct i40e_reg_info *reg_info;
12073
12074         if (ptr_data == NULL) {
12075                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12076                 regs->width = sizeof(uint32_t);
12077                 return 0;
12078         }
12079
12080         /* The first few registers have to be read using AQ operations */
12081         reg_idx = 0;
12082         while (i40e_regs_adminq[reg_idx].name) {
12083                 reg_info = &i40e_regs_adminq[reg_idx++];
12084                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12085                         for (arr_idx2 = 0;
12086                                         arr_idx2 <= reg_info->count2;
12087                                         arr_idx2++) {
12088                                 reg_offset = arr_idx * reg_info->stride1 +
12089                                         arr_idx2 * reg_info->stride2;
12090                                 reg_offset += reg_info->base_addr;
12091                                 ptr_data[reg_offset >> 2] =
12092                                         i40e_read_rx_ctl(hw, reg_offset);
12093                         }
12094         }
12095
12096         /* The remaining registers can be read using primitives */
12097         reg_idx = 0;
12098         while (i40e_regs_others[reg_idx].name) {
12099                 reg_info = &i40e_regs_others[reg_idx++];
12100                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12101                         for (arr_idx2 = 0;
12102                                         arr_idx2 <= reg_info->count2;
12103                                         arr_idx2++) {
12104                                 reg_offset = arr_idx * reg_info->stride1 +
12105                                         arr_idx2 * reg_info->stride2;
12106                                 reg_offset += reg_info->base_addr;
12107                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12108                                         ptr_data[reg_offset >> 2] = 0;
12109                                 else
12110                                         ptr_data[reg_offset >> 2] =
12111                                                 I40E_READ_REG(hw, reg_offset);
12112                         }
12113         }
12114
12115         return 0;
12116 }
12117
12118 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12119 {
12120         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12121
12122         /* Convert word count to byte count */
12123         return hw->nvm.sr_size << 1;
12124 }
12125
12126 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12127                            struct rte_dev_eeprom_info *eeprom)
12128 {
12129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12130         uint16_t *data = eeprom->data;
12131         uint16_t offset, length, cnt_words;
12132         int ret_code;
12133
12134         offset = eeprom->offset >> 1;
12135         length = eeprom->length >> 1;
12136         cnt_words = length;
12137
12138         if (offset > hw->nvm.sr_size ||
12139                 offset + length > hw->nvm.sr_size) {
12140                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12141                 return -EINVAL;
12142         }
12143
12144         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12145
12146         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12147         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12148                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12149                 return -EIO;
12150         }
12151
12152         return 0;
12153 }
12154
12155 static int i40e_get_module_info(struct rte_eth_dev *dev,
12156                                 struct rte_eth_dev_module_info *modinfo)
12157 {
12158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12159         uint32_t sff8472_comp = 0;
12160         uint32_t sff8472_swap = 0;
12161         uint32_t sff8636_rev = 0;
12162         i40e_status status;
12163         uint32_t type = 0;
12164
12165         /* Check if firmware supports reading module EEPROM. */
12166         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12167                 PMD_DRV_LOG(ERR,
12168                             "Module EEPROM memory read not supported. "
12169                             "Please update the NVM image.\n");
12170                 return -EINVAL;
12171         }
12172
12173         status = i40e_update_link_info(hw);
12174         if (status)
12175                 return -EIO;
12176
12177         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12178                 PMD_DRV_LOG(ERR,
12179                             "Cannot read module EEPROM memory. "
12180                             "No module connected.\n");
12181                 return -EINVAL;
12182         }
12183
12184         type = hw->phy.link_info.module_type[0];
12185
12186         switch (type) {
12187         case I40E_MODULE_TYPE_SFP:
12188                 status = i40e_aq_get_phy_register(hw,
12189                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12190                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12191                                 I40E_MODULE_SFF_8472_COMP,
12192                                 &sff8472_comp, NULL);
12193                 if (status)
12194                         return -EIO;
12195
12196                 status = i40e_aq_get_phy_register(hw,
12197                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12198                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12199                                 I40E_MODULE_SFF_8472_SWAP,
12200                                 &sff8472_swap, NULL);
12201                 if (status)
12202                         return -EIO;
12203
12204                 /* Check if the module requires address swap to access
12205                  * the other EEPROM memory page.
12206                  */
12207                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12208                         PMD_DRV_LOG(WARNING,
12209                                     "Module address swap to access "
12210                                     "page 0xA2 is not supported.\n");
12211                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12212                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12213                 } else if (sff8472_comp == 0x00) {
12214                         /* Module is not SFF-8472 compliant */
12215                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12216                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12217                 } else {
12218                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12219                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12220                 }
12221                 break;
12222         case I40E_MODULE_TYPE_QSFP_PLUS:
12223                 /* Read from memory page 0. */
12224                 status = i40e_aq_get_phy_register(hw,
12225                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12226                                 0, 1,
12227                                 I40E_MODULE_REVISION_ADDR,
12228                                 &sff8636_rev, NULL);
12229                 if (status)
12230                         return -EIO;
12231                 /* Determine revision compliance byte */
12232                 if (sff8636_rev > 0x02) {
12233                         /* Module is SFF-8636 compliant */
12234                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12235                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12236                 } else {
12237                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12238                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12239                 }
12240                 break;
12241         case I40E_MODULE_TYPE_QSFP28:
12242                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12243                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12244                 break;
12245         default:
12246                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12247                 return -EINVAL;
12248         }
12249         return 0;
12250 }
12251
12252 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12253                                   struct rte_dev_eeprom_info *info)
12254 {
12255         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12256         bool is_sfp = false;
12257         i40e_status status;
12258         uint8_t *data;
12259         uint32_t value = 0;
12260         uint32_t i;
12261
12262         if (!info || !info->length || !info->data)
12263                 return -EINVAL;
12264
12265         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12266                 is_sfp = true;
12267
12268         data = info->data;
12269         for (i = 0; i < info->length; i++) {
12270                 u32 offset = i + info->offset;
12271                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12272
12273                 /* Check if we need to access the other memory page */
12274                 if (is_sfp) {
12275                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12276                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12277                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12278                         }
12279                 } else {
12280                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12281                                 /* Compute memory page number and offset. */
12282                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12283                                 addr++;
12284                         }
12285                 }
12286                 status = i40e_aq_get_phy_register(hw,
12287                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12288                                 addr, 1, offset, &value, NULL);
12289                 if (status)
12290                         return -EIO;
12291                 data[i] = (uint8_t)value;
12292         }
12293         return 0;
12294 }
12295
12296 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12297                                      struct rte_ether_addr *mac_addr)
12298 {
12299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12301         struct i40e_vsi *vsi = pf->main_vsi;
12302         struct i40e_mac_filter_info mac_filter;
12303         struct i40e_mac_filter *f;
12304         int ret;
12305
12306         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12307                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12308                 return -EINVAL;
12309         }
12310
12311         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12312                 if (rte_is_same_ether_addr(&pf->dev_addr,
12313                                                 &f->mac_info.mac_addr))
12314                         break;
12315         }
12316
12317         if (f == NULL) {
12318                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12319                 return -EIO;
12320         }
12321
12322         mac_filter = f->mac_info;
12323         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12324         if (ret != I40E_SUCCESS) {
12325                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12326                 return -EIO;
12327         }
12328         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12329         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12330         if (ret != I40E_SUCCESS) {
12331                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12332                 return -EIO;
12333         }
12334         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12335
12336         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12337                                         mac_addr->addr_bytes, NULL);
12338         if (ret != I40E_SUCCESS) {
12339                 PMD_DRV_LOG(ERR, "Failed to change mac");
12340                 return -EIO;
12341         }
12342
12343         return 0;
12344 }
12345
12346 static int
12347 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12348 {
12349         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12350         struct rte_eth_dev_data *dev_data = pf->dev_data;
12351         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12352         int ret = 0;
12353
12354         /* check if mtu is within the allowed range */
12355         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12356                 return -EINVAL;
12357
12358         /* mtu setting is forbidden if port is start */
12359         if (dev_data->dev_started) {
12360                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12361                             dev_data->port_id);
12362                 return -EBUSY;
12363         }
12364
12365         if (frame_size > RTE_ETHER_MAX_LEN)
12366                 dev_data->dev_conf.rxmode.offloads |=
12367                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12368         else
12369                 dev_data->dev_conf.rxmode.offloads &=
12370                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12371
12372         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12373
12374         return ret;
12375 }
12376
12377 /* Restore ethertype filter */
12378 static void
12379 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12380 {
12381         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12382         struct i40e_ethertype_filter_list
12383                 *ethertype_list = &pf->ethertype.ethertype_list;
12384         struct i40e_ethertype_filter *f;
12385         struct i40e_control_filter_stats stats;
12386         uint16_t flags;
12387
12388         TAILQ_FOREACH(f, ethertype_list, rules) {
12389                 flags = 0;
12390                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12391                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12392                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12393                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12394                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12395
12396                 memset(&stats, 0, sizeof(stats));
12397                 i40e_aq_add_rem_control_packet_filter(hw,
12398                                             f->input.mac_addr.addr_bytes,
12399                                             f->input.ether_type,
12400                                             flags, pf->main_vsi->seid,
12401                                             f->queue, 1, &stats, NULL);
12402         }
12403         PMD_DRV_LOG(INFO, "Ethertype filter:"
12404                     " mac_etype_used = %u, etype_used = %u,"
12405                     " mac_etype_free = %u, etype_free = %u",
12406                     stats.mac_etype_used, stats.etype_used,
12407                     stats.mac_etype_free, stats.etype_free);
12408 }
12409
12410 /* Restore tunnel filter */
12411 static void
12412 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12413 {
12414         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12415         struct i40e_vsi *vsi;
12416         struct i40e_pf_vf *vf;
12417         struct i40e_tunnel_filter_list
12418                 *tunnel_list = &pf->tunnel.tunnel_list;
12419         struct i40e_tunnel_filter *f;
12420         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12421         bool big_buffer = 0;
12422
12423         TAILQ_FOREACH(f, tunnel_list, rules) {
12424                 if (!f->is_to_vf)
12425                         vsi = pf->main_vsi;
12426                 else {
12427                         vf = &pf->vfs[f->vf_id];
12428                         vsi = vf->vsi;
12429                 }
12430                 memset(&cld_filter, 0, sizeof(cld_filter));
12431                 rte_ether_addr_copy((struct rte_ether_addr *)
12432                                 &f->input.outer_mac,
12433                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12434                 rte_ether_addr_copy((struct rte_ether_addr *)
12435                                 &f->input.inner_mac,
12436                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12437                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12438                 cld_filter.element.flags = f->input.flags;
12439                 cld_filter.element.tenant_id = f->input.tenant_id;
12440                 cld_filter.element.queue_number = f->queue;
12441                 rte_memcpy(cld_filter.general_fields,
12442                            f->input.general_fields,
12443                            sizeof(f->input.general_fields));
12444
12445                 if (((f->input.flags &
12446                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12447                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12448                     ((f->input.flags &
12449                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12450                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12451                     ((f->input.flags &
12452                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12453                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12454                         big_buffer = 1;
12455
12456                 if (big_buffer)
12457                         i40e_aq_add_cloud_filters_bb(hw,
12458                                         vsi->seid, &cld_filter, 1);
12459                 else
12460                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12461                                                   &cld_filter.element, 1);
12462         }
12463 }
12464
12465 /* Restore RSS filter */
12466 static inline void
12467 i40e_rss_filter_restore(struct i40e_pf *pf)
12468 {
12469         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12470         struct i40e_rss_filter *filter;
12471
12472         TAILQ_FOREACH(filter, list, next) {
12473                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12474         }
12475 }
12476
12477 static void
12478 i40e_filter_restore(struct i40e_pf *pf)
12479 {
12480         i40e_ethertype_filter_restore(pf);
12481         i40e_tunnel_filter_restore(pf);
12482         i40e_fdir_filter_restore(pf);
12483         i40e_rss_filter_restore(pf);
12484 }
12485
12486 bool
12487 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12488 {
12489         if (strcmp(dev->device->driver->name, drv->driver.name))
12490                 return false;
12491
12492         return true;
12493 }
12494
12495 bool
12496 is_i40e_supported(struct rte_eth_dev *dev)
12497 {
12498         return is_device_supported(dev, &rte_i40e_pmd);
12499 }
12500
12501 struct i40e_customized_pctype*
12502 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12503 {
12504         int i;
12505
12506         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12507                 if (pf->customized_pctype[i].index == index)
12508                         return &pf->customized_pctype[i];
12509         }
12510         return NULL;
12511 }
12512
12513 static int
12514 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12515                               uint32_t pkg_size, uint32_t proto_num,
12516                               struct rte_pmd_i40e_proto_info *proto,
12517                               enum rte_pmd_i40e_package_op op)
12518 {
12519         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12520         uint32_t pctype_num;
12521         struct rte_pmd_i40e_ptype_info *pctype;
12522         uint32_t buff_size;
12523         struct i40e_customized_pctype *new_pctype = NULL;
12524         uint8_t proto_id;
12525         uint8_t pctype_value;
12526         char name[64];
12527         uint32_t i, j, n;
12528         int ret;
12529
12530         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12531             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12532                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12533                 return -1;
12534         }
12535
12536         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12537                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12538                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12539         if (ret) {
12540                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12541                 return -1;
12542         }
12543         if (!pctype_num) {
12544                 PMD_DRV_LOG(INFO, "No new pctype added");
12545                 return -1;
12546         }
12547
12548         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12549         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12550         if (!pctype) {
12551                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12552                 return -1;
12553         }
12554         /* get information about new pctype list */
12555         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12556                                         (uint8_t *)pctype, buff_size,
12557                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12558         if (ret) {
12559                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12560                 rte_free(pctype);
12561                 return -1;
12562         }
12563
12564         /* Update customized pctype. */
12565         for (i = 0; i < pctype_num; i++) {
12566                 pctype_value = pctype[i].ptype_id;
12567                 memset(name, 0, sizeof(name));
12568                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12569                         proto_id = pctype[i].protocols[j];
12570                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12571                                 continue;
12572                         for (n = 0; n < proto_num; n++) {
12573                                 if (proto[n].proto_id != proto_id)
12574                                         continue;
12575                                 strlcat(name, proto[n].name, sizeof(name));
12576                                 strlcat(name, "_", sizeof(name));
12577                                 break;
12578                         }
12579                 }
12580                 name[strlen(name) - 1] = '\0';
12581                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12582                 if (!strcmp(name, "GTPC"))
12583                         new_pctype =
12584                                 i40e_find_customized_pctype(pf,
12585                                                       I40E_CUSTOMIZED_GTPC);
12586                 else if (!strcmp(name, "GTPU_IPV4"))
12587                         new_pctype =
12588                                 i40e_find_customized_pctype(pf,
12589                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12590                 else if (!strcmp(name, "GTPU_IPV6"))
12591                         new_pctype =
12592                                 i40e_find_customized_pctype(pf,
12593                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12594                 else if (!strcmp(name, "GTPU"))
12595                         new_pctype =
12596                                 i40e_find_customized_pctype(pf,
12597                                                       I40E_CUSTOMIZED_GTPU);
12598                 else if (!strcmp(name, "IPV4_L2TPV3"))
12599                         new_pctype =
12600                                 i40e_find_customized_pctype(pf,
12601                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12602                 else if (!strcmp(name, "IPV6_L2TPV3"))
12603                         new_pctype =
12604                                 i40e_find_customized_pctype(pf,
12605                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12606                 else if (!strcmp(name, "IPV4_ESP"))
12607                         new_pctype =
12608                                 i40e_find_customized_pctype(pf,
12609                                                 I40E_CUSTOMIZED_ESP_IPV4);
12610                 else if (!strcmp(name, "IPV6_ESP"))
12611                         new_pctype =
12612                                 i40e_find_customized_pctype(pf,
12613                                                 I40E_CUSTOMIZED_ESP_IPV6);
12614                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12615                         new_pctype =
12616                                 i40e_find_customized_pctype(pf,
12617                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12618                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12619                         new_pctype =
12620                                 i40e_find_customized_pctype(pf,
12621                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12622                 else if (!strcmp(name, "IPV4_AH"))
12623                         new_pctype =
12624                                 i40e_find_customized_pctype(pf,
12625                                                 I40E_CUSTOMIZED_AH_IPV4);
12626                 else if (!strcmp(name, "IPV6_AH"))
12627                         new_pctype =
12628                                 i40e_find_customized_pctype(pf,
12629                                                 I40E_CUSTOMIZED_AH_IPV6);
12630                 if (new_pctype) {
12631                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12632                                 new_pctype->pctype = pctype_value;
12633                                 new_pctype->valid = true;
12634                         } else {
12635                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12636                                 new_pctype->valid = false;
12637                         }
12638                 }
12639         }
12640
12641         rte_free(pctype);
12642         return 0;
12643 }
12644
12645 static int
12646 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12647                              uint32_t pkg_size, uint32_t proto_num,
12648                              struct rte_pmd_i40e_proto_info *proto,
12649                              enum rte_pmd_i40e_package_op op)
12650 {
12651         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12652         uint16_t port_id = dev->data->port_id;
12653         uint32_t ptype_num;
12654         struct rte_pmd_i40e_ptype_info *ptype;
12655         uint32_t buff_size;
12656         uint8_t proto_id;
12657         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12658         uint32_t i, j, n;
12659         bool in_tunnel;
12660         int ret;
12661
12662         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12663             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12664                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12665                 return -1;
12666         }
12667
12668         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12669                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12670                 return 0;
12671         }
12672
12673         /* get information about new ptype num */
12674         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12675                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12676                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12677         if (ret) {
12678                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12679                 return ret;
12680         }
12681         if (!ptype_num) {
12682                 PMD_DRV_LOG(INFO, "No new ptype added");
12683                 return -1;
12684         }
12685
12686         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12687         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12688         if (!ptype) {
12689                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12690                 return -1;
12691         }
12692
12693         /* get information about new ptype list */
12694         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12695                                         (uint8_t *)ptype, buff_size,
12696                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12697         if (ret) {
12698                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12699                 rte_free(ptype);
12700                 return ret;
12701         }
12702
12703         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12704         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12705         if (!ptype_mapping) {
12706                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12707                 rte_free(ptype);
12708                 return -1;
12709         }
12710
12711         /* Update ptype mapping table. */
12712         for (i = 0; i < ptype_num; i++) {
12713                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12714                 ptype_mapping[i].sw_ptype = 0;
12715                 in_tunnel = false;
12716                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12717                         proto_id = ptype[i].protocols[j];
12718                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12719                                 continue;
12720                         for (n = 0; n < proto_num; n++) {
12721                                 if (proto[n].proto_id != proto_id)
12722                                         continue;
12723                                 memset(name, 0, sizeof(name));
12724                                 strcpy(name, proto[n].name);
12725                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12726                                 if (!strncasecmp(name, "PPPOE", 5))
12727                                         ptype_mapping[i].sw_ptype |=
12728                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12729                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12730                                          !in_tunnel) {
12731                                         ptype_mapping[i].sw_ptype |=
12732                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12733                                         ptype_mapping[i].sw_ptype |=
12734                                                 RTE_PTYPE_L4_FRAG;
12735                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12736                                            in_tunnel) {
12737                                         ptype_mapping[i].sw_ptype |=
12738                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12739                                         ptype_mapping[i].sw_ptype |=
12740                                                 RTE_PTYPE_INNER_L4_FRAG;
12741                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12742                                         ptype_mapping[i].sw_ptype |=
12743                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12744                                         in_tunnel = true;
12745                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12746                                            !in_tunnel)
12747                                         ptype_mapping[i].sw_ptype |=
12748                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12749                                 else if (!strncasecmp(name, "IPV4", 4) &&
12750                                          in_tunnel)
12751                                         ptype_mapping[i].sw_ptype |=
12752                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12753                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12754                                          !in_tunnel) {
12755                                         ptype_mapping[i].sw_ptype |=
12756                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12757                                         ptype_mapping[i].sw_ptype |=
12758                                                 RTE_PTYPE_L4_FRAG;
12759                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12760                                            in_tunnel) {
12761                                         ptype_mapping[i].sw_ptype |=
12762                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12763                                         ptype_mapping[i].sw_ptype |=
12764                                                 RTE_PTYPE_INNER_L4_FRAG;
12765                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12766                                         ptype_mapping[i].sw_ptype |=
12767                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12768                                         in_tunnel = true;
12769                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12770                                            !in_tunnel)
12771                                         ptype_mapping[i].sw_ptype |=
12772                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12773                                 else if (!strncasecmp(name, "IPV6", 4) &&
12774                                          in_tunnel)
12775                                         ptype_mapping[i].sw_ptype |=
12776                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12777                                 else if (!strncasecmp(name, "UDP", 3) &&
12778                                          !in_tunnel)
12779                                         ptype_mapping[i].sw_ptype |=
12780                                                 RTE_PTYPE_L4_UDP;
12781                                 else if (!strncasecmp(name, "UDP", 3) &&
12782                                          in_tunnel)
12783                                         ptype_mapping[i].sw_ptype |=
12784                                                 RTE_PTYPE_INNER_L4_UDP;
12785                                 else if (!strncasecmp(name, "TCP", 3) &&
12786                                          !in_tunnel)
12787                                         ptype_mapping[i].sw_ptype |=
12788                                                 RTE_PTYPE_L4_TCP;
12789                                 else if (!strncasecmp(name, "TCP", 3) &&
12790                                          in_tunnel)
12791                                         ptype_mapping[i].sw_ptype |=
12792                                                 RTE_PTYPE_INNER_L4_TCP;
12793                                 else if (!strncasecmp(name, "SCTP", 4) &&
12794                                          !in_tunnel)
12795                                         ptype_mapping[i].sw_ptype |=
12796                                                 RTE_PTYPE_L4_SCTP;
12797                                 else if (!strncasecmp(name, "SCTP", 4) &&
12798                                          in_tunnel)
12799                                         ptype_mapping[i].sw_ptype |=
12800                                                 RTE_PTYPE_INNER_L4_SCTP;
12801                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12802                                           !strncasecmp(name, "ICMPV6", 6)) &&
12803                                          !in_tunnel)
12804                                         ptype_mapping[i].sw_ptype |=
12805                                                 RTE_PTYPE_L4_ICMP;
12806                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12807                                           !strncasecmp(name, "ICMPV6", 6)) &&
12808                                          in_tunnel)
12809                                         ptype_mapping[i].sw_ptype |=
12810                                                 RTE_PTYPE_INNER_L4_ICMP;
12811                                 else if (!strncasecmp(name, "GTPC", 4)) {
12812                                         ptype_mapping[i].sw_ptype |=
12813                                                 RTE_PTYPE_TUNNEL_GTPC;
12814                                         in_tunnel = true;
12815                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12816                                         ptype_mapping[i].sw_ptype |=
12817                                                 RTE_PTYPE_TUNNEL_GTPU;
12818                                         in_tunnel = true;
12819                                 } else if (!strncasecmp(name, "ESP", 3)) {
12820                                         ptype_mapping[i].sw_ptype |=
12821                                                 RTE_PTYPE_TUNNEL_ESP;
12822                                         in_tunnel = true;
12823                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12824                                         ptype_mapping[i].sw_ptype |=
12825                                                 RTE_PTYPE_TUNNEL_GRENAT;
12826                                         in_tunnel = true;
12827                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12828                                            !strncasecmp(name, "L2TPV2", 6) ||
12829                                            !strncasecmp(name, "L2TPV3", 6)) {
12830                                         ptype_mapping[i].sw_ptype |=
12831                                                 RTE_PTYPE_TUNNEL_L2TP;
12832                                         in_tunnel = true;
12833                                 }
12834
12835                                 break;
12836                         }
12837                 }
12838         }
12839
12840         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12841                                                 ptype_num, 0);
12842         if (ret)
12843                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12844
12845         rte_free(ptype_mapping);
12846         rte_free(ptype);
12847         return ret;
12848 }
12849
12850 void
12851 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12852                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12853 {
12854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12855         uint32_t proto_num;
12856         struct rte_pmd_i40e_proto_info *proto;
12857         uint32_t buff_size;
12858         uint32_t i;
12859         int ret;
12860
12861         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12862             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12863                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12864                 return;
12865         }
12866
12867         /* get information about protocol number */
12868         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12869                                        (uint8_t *)&proto_num, sizeof(proto_num),
12870                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12871         if (ret) {
12872                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12873                 return;
12874         }
12875         if (!proto_num) {
12876                 PMD_DRV_LOG(INFO, "No new protocol added");
12877                 return;
12878         }
12879
12880         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12881         proto = rte_zmalloc("new_proto", buff_size, 0);
12882         if (!proto) {
12883                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12884                 return;
12885         }
12886
12887         /* get information about protocol list */
12888         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12889                                         (uint8_t *)proto, buff_size,
12890                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12891         if (ret) {
12892                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12893                 rte_free(proto);
12894                 return;
12895         }
12896
12897         /* Check if GTP is supported. */
12898         for (i = 0; i < proto_num; i++) {
12899                 if (!strncmp(proto[i].name, "GTP", 3)) {
12900                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12901                                 pf->gtp_support = true;
12902                         else
12903                                 pf->gtp_support = false;
12904                         break;
12905                 }
12906         }
12907
12908         /* Check if ESP is supported. */
12909         for (i = 0; i < proto_num; i++) {
12910                 if (!strncmp(proto[i].name, "ESP", 3)) {
12911                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12912                                 pf->esp_support = true;
12913                         else
12914                                 pf->esp_support = false;
12915                         break;
12916                 }
12917         }
12918
12919         /* Update customized pctype info */
12920         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12921                                             proto_num, proto, op);
12922         if (ret)
12923                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12924
12925         /* Update customized ptype info */
12926         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12927                                            proto_num, proto, op);
12928         if (ret)
12929                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12930
12931         rte_free(proto);
12932 }
12933
12934 /* Create a QinQ cloud filter
12935  *
12936  * The Fortville NIC has limited resources for tunnel filters,
12937  * so we can only reuse existing filters.
12938  *
12939  * In step 1 we define which Field Vector fields can be used for
12940  * filter types.
12941  * As we do not have the inner tag defined as a field,
12942  * we have to define it first, by reusing one of L1 entries.
12943  *
12944  * In step 2 we are replacing one of existing filter types with
12945  * a new one for QinQ.
12946  * As we reusing L1 and replacing L2, some of the default filter
12947  * types will disappear,which depends on L1 and L2 entries we reuse.
12948  *
12949  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12950  *
12951  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12952  *              later when we define the cloud filter.
12953  *      a.      Valid_flags.replace_cloud = 0
12954  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12955  *      c.      New_filter = 0x10
12956  *      d.      TR bit = 0xff (optional, not used here)
12957  *      e.      Buffer – 2 entries:
12958  *              i.      Byte 0 = 8 (outer vlan FV index).
12959  *                      Byte 1 = 0 (rsv)
12960  *                      Byte 2-3 = 0x0fff
12961  *              ii.     Byte 0 = 37 (inner vlan FV index).
12962  *                      Byte 1 =0 (rsv)
12963  *                      Byte 2-3 = 0x0fff
12964  *
12965  * Step 2:
12966  * 2.   Create cloud filter using two L1 filters entries: stag and
12967  *              new filter(outer vlan+ inner vlan)
12968  *      a.      Valid_flags.replace_cloud = 1
12969  *      b.      Old_filter = 1 (instead of outer IP)
12970  *      c.      New_filter = 0x10
12971  *      d.      Buffer – 2 entries:
12972  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12973  *                      Byte 1-3 = 0 (rsv)
12974  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12975  *                      Byte 9-11 = 0 (rsv)
12976  */
12977 static int
12978 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12979 {
12980         int ret = -ENOTSUP;
12981         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12982         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12983         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12984         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12985
12986         if (pf->support_multi_driver) {
12987                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12988                 return ret;
12989         }
12990
12991         /* Init */
12992         memset(&filter_replace, 0,
12993                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12994         memset(&filter_replace_buf, 0,
12995                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12996
12997         /* create L1 filter */
12998         filter_replace.old_filter_type =
12999                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13000         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13001         filter_replace.tr_bit = 0;
13002
13003         /* Prepare the buffer, 2 entries */
13004         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13005         filter_replace_buf.data[0] |=
13006                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13007         /* Field Vector 12b mask */
13008         filter_replace_buf.data[2] = 0xff;
13009         filter_replace_buf.data[3] = 0x0f;
13010         filter_replace_buf.data[4] =
13011                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13012         filter_replace_buf.data[4] |=
13013                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13014         /* Field Vector 12b mask */
13015         filter_replace_buf.data[6] = 0xff;
13016         filter_replace_buf.data[7] = 0x0f;
13017         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13018                         &filter_replace_buf);
13019         if (ret != I40E_SUCCESS)
13020                 return ret;
13021
13022         if (filter_replace.old_filter_type !=
13023             filter_replace.new_filter_type)
13024                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13025                             " original: 0x%x, new: 0x%x",
13026                             dev->device->name,
13027                             filter_replace.old_filter_type,
13028                             filter_replace.new_filter_type);
13029
13030         /* Apply the second L2 cloud filter */
13031         memset(&filter_replace, 0,
13032                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13033         memset(&filter_replace_buf, 0,
13034                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13035
13036         /* create L2 filter, input for L2 filter will be L1 filter  */
13037         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13038         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13039         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13040
13041         /* Prepare the buffer, 2 entries */
13042         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13043         filter_replace_buf.data[0] |=
13044                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13045         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13046         filter_replace_buf.data[4] |=
13047                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13048         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13049                         &filter_replace_buf);
13050         if (!ret && (filter_replace.old_filter_type !=
13051                      filter_replace.new_filter_type))
13052                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13053                             " original: 0x%x, new: 0x%x",
13054                             dev->device->name,
13055                             filter_replace.old_filter_type,
13056                             filter_replace.new_filter_type);
13057
13058         return ret;
13059 }
13060
13061 int
13062 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13063                    const struct rte_flow_action_rss *in)
13064 {
13065         if (in->key_len > RTE_DIM(out->key) ||
13066             in->queue_num > RTE_DIM(out->queue))
13067                 return -EINVAL;
13068         if (!in->key && in->key_len)
13069                 return -EINVAL;
13070         out->conf = (struct rte_flow_action_rss){
13071                 .func = in->func,
13072                 .level = in->level,
13073                 .types = in->types,
13074                 .key_len = in->key_len,
13075                 .queue_num = in->queue_num,
13076                 .queue = memcpy(out->queue, in->queue,
13077                                 sizeof(*in->queue) * in->queue_num),
13078         };
13079         if (in->key)
13080                 out->conf.key = memcpy(out->key, in->key, in->key_len);
13081         return 0;
13082 }
13083
13084 /* Write HENA register to enable hash */
13085 static int
13086 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13087 {
13088         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13089         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13090         uint64_t hena;
13091         int ret;
13092
13093         ret = i40e_set_rss_key(pf->main_vsi, key,
13094                                rss_conf->conf.key_len);
13095         if (ret)
13096                 return ret;
13097
13098         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13099         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13100         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13101         I40E_WRITE_FLUSH(hw);
13102
13103         return 0;
13104 }
13105
13106 /* Configure hash input set */
13107 static int
13108 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13109 {
13110         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13111         struct rte_eth_input_set_conf conf;
13112         uint64_t mask0;
13113         int ret = 0;
13114         uint32_t j;
13115         int i;
13116         static const struct {
13117                 uint64_t type;
13118                 enum rte_eth_input_set_field field;
13119         } inset_match_table[] = {
13120                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13121                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13122                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13123                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13124                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13125                         RTE_ETH_INPUT_SET_UNKNOWN},
13126                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13127                         RTE_ETH_INPUT_SET_UNKNOWN},
13128
13129                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13130                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13131                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13132                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13133                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13134                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13135                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13136                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13137
13138                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13139                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13140                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13141                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13142                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13143                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13144                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13145                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13146
13147                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13148                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13149                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13150                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13151                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13152                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13153                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13154                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13155
13156                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13157                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13158                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13159                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13160                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13161                         RTE_ETH_INPUT_SET_UNKNOWN},
13162                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13163                         RTE_ETH_INPUT_SET_UNKNOWN},
13164
13165                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13166                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13167                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13168                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13169                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13170                         RTE_ETH_INPUT_SET_UNKNOWN},
13171                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13172                         RTE_ETH_INPUT_SET_UNKNOWN},
13173
13174                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13175                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13176                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13177                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13178                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13179                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13180                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13181                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13182
13183                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13184                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13185                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13186                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13187                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13188                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13189                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13190                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13191
13192                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13193                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13194                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13195                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13196                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13197                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13198                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13199                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13200
13201                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13202                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13203                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13204                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13205                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13206                         RTE_ETH_INPUT_SET_UNKNOWN},
13207                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13208                         RTE_ETH_INPUT_SET_UNKNOWN},
13209         };
13210
13211         mask0 = types & pf->adapter->flow_types_mask;
13212         conf.op = RTE_ETH_INPUT_SET_SELECT;
13213         conf.inset_size = 0;
13214         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13215                 if (mask0 & (1ULL << i)) {
13216                         conf.flow_type = i;
13217                         break;
13218                 }
13219         }
13220
13221         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13222                 if ((types & inset_match_table[j].type) ==
13223                     inset_match_table[j].type) {
13224                         if (inset_match_table[j].field ==
13225                             RTE_ETH_INPUT_SET_UNKNOWN)
13226                                 return -EINVAL;
13227
13228                         conf.field[conf.inset_size] =
13229                                 inset_match_table[j].field;
13230                         conf.inset_size++;
13231                 }
13232         }
13233
13234         if (conf.inset_size) {
13235                 ret = i40e_hash_filter_inset_select(hw, &conf);
13236                 if (ret)
13237                         return ret;
13238         }
13239
13240         return ret;
13241 }
13242
13243 /* Look up the conflicted rule then mark it as invalid */
13244 static void
13245 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13246                 struct i40e_rte_flow_rss_conf *conf)
13247 {
13248         struct i40e_rss_filter *rss_item;
13249         uint64_t rss_inset;
13250
13251         /* Clear input set bits before comparing the pctype */
13252         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13253                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13254
13255         /* Look up the conflicted rule then mark it as invalid */
13256         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13257                 if (!rss_item->rss_filter_info.valid)
13258                         continue;
13259
13260                 if (conf->conf.queue_num &&
13261                     rss_item->rss_filter_info.conf.queue_num)
13262                         rss_item->rss_filter_info.valid = false;
13263
13264                 if (conf->conf.types &&
13265                     (rss_item->rss_filter_info.conf.types &
13266                     rss_inset) ==
13267                     (conf->conf.types & rss_inset))
13268                         rss_item->rss_filter_info.valid = false;
13269
13270                 if (conf->conf.func ==
13271                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13272                     rss_item->rss_filter_info.conf.func ==
13273                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13274                         rss_item->rss_filter_info.valid = false;
13275         }
13276 }
13277
13278 /* Configure RSS hash function */
13279 static int
13280 i40e_rss_config_hash_function(struct i40e_pf *pf,
13281                 struct i40e_rte_flow_rss_conf *conf)
13282 {
13283         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13284         uint32_t reg, i;
13285         uint64_t mask0;
13286         uint16_t j;
13287
13288         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13289                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13290                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13291                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13292                         I40E_WRITE_FLUSH(hw);
13293                         i40e_rss_mark_invalid_rule(pf, conf);
13294
13295                         return 0;
13296                 }
13297                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13298
13299                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13300                 I40E_WRITE_FLUSH(hw);
13301                 i40e_rss_mark_invalid_rule(pf, conf);
13302         } else if (conf->conf.func ==
13303                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13304                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13305
13306                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13307                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13308                         if (mask0 & (1UL << i))
13309                                 break;
13310                 }
13311
13312                 if (i == UINT64_BIT)
13313                         return -EINVAL;
13314
13315                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13316                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13317                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13318                                 i40e_write_global_rx_ctl(hw,
13319                                         I40E_GLQF_HSYM(j),
13320                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13321                 }
13322         }
13323
13324         return 0;
13325 }
13326
13327 /* Enable RSS according to the configuration */
13328 static int
13329 i40e_rss_enable_hash(struct i40e_pf *pf,
13330                 struct i40e_rte_flow_rss_conf *conf)
13331 {
13332         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13333         struct i40e_rte_flow_rss_conf rss_conf;
13334
13335         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13336                 return -ENOTSUP;
13337
13338         memset(&rss_conf, 0, sizeof(rss_conf));
13339         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13340
13341         /* Configure hash input set */
13342         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13343                 return -EINVAL;
13344
13345         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13346             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13347                 /* Random default keys */
13348                 static uint32_t rss_key_default[] = {0x6b793944,
13349                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13350                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13351                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13352
13353                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13354                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13355                                 sizeof(uint32_t);
13356                 PMD_DRV_LOG(INFO,
13357                         "No valid RSS key config for i40e, using default\n");
13358         }
13359
13360         rss_conf.conf.types |= rss_info->conf.types;
13361         i40e_rss_hash_set(pf, &rss_conf);
13362
13363         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13364                 i40e_rss_config_hash_function(pf, conf);
13365
13366         i40e_rss_mark_invalid_rule(pf, conf);
13367
13368         return 0;
13369 }
13370
13371 /* Configure RSS queue region */
13372 static int
13373 i40e_rss_config_queue_region(struct i40e_pf *pf,
13374                 struct i40e_rte_flow_rss_conf *conf)
13375 {
13376         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13377         uint32_t lut = 0;
13378         uint16_t j, num;
13379         uint32_t i;
13380
13381         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13382          * It's necessary to calculate the actual PF queues that are configured.
13383          */
13384         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13385                 num = i40e_pf_calc_configured_queues_num(pf);
13386         else
13387                 num = pf->dev_data->nb_rx_queues;
13388
13389         num = RTE_MIN(num, conf->conf.queue_num);
13390         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13391                         num);
13392
13393         if (num == 0) {
13394                 PMD_DRV_LOG(ERR,
13395                         "No PF queues are configured to enable RSS for port %u",
13396                         pf->dev_data->port_id);
13397                 return -ENOTSUP;
13398         }
13399
13400         /* Fill in redirection table */
13401         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13402                 if (j == num)
13403                         j = 0;
13404                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13405                         hw->func_caps.rss_table_entry_width) - 1));
13406                 if ((i & 3) == 3)
13407                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13408         }
13409
13410         i40e_rss_mark_invalid_rule(pf, conf);
13411
13412         return 0;
13413 }
13414
13415 /* Configure RSS hash function to default */
13416 static int
13417 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13418                 struct i40e_rte_flow_rss_conf *conf)
13419 {
13420         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13421         uint32_t i, reg;
13422         uint64_t mask0;
13423         uint16_t j;
13424
13425         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13426                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13427                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13428                         PMD_DRV_LOG(DEBUG,
13429                                 "Hash function already set to Toeplitz");
13430                         I40E_WRITE_FLUSH(hw);
13431
13432                         return 0;
13433                 }
13434                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13435
13436                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13437                 I40E_WRITE_FLUSH(hw);
13438         } else if (conf->conf.func ==
13439                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13440                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13441
13442                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13443                         if (mask0 & (1UL << i))
13444                                 break;
13445                 }
13446
13447                 if (i == UINT64_BIT)
13448                         return -EINVAL;
13449
13450                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13451                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13452                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13453                                 i40e_write_global_rx_ctl(hw,
13454                                         I40E_GLQF_HSYM(j),
13455                                         0);
13456                 }
13457         }
13458
13459         return 0;
13460 }
13461
13462 /* Disable RSS hash and configure default input set */
13463 static int
13464 i40e_rss_disable_hash(struct i40e_pf *pf,
13465                 struct i40e_rte_flow_rss_conf *conf)
13466 {
13467         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13468         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13469         struct i40e_rte_flow_rss_conf rss_conf;
13470         uint32_t i;
13471
13472         memset(&rss_conf, 0, sizeof(rss_conf));
13473         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13474
13475         /* Disable RSS hash */
13476         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13477         i40e_rss_hash_set(pf, &rss_conf);
13478
13479         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13480                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13481                     !(conf->conf.types & (1ULL << i)))
13482                         continue;
13483
13484                 /* Configure default input set */
13485                 struct rte_eth_input_set_conf input_conf = {
13486                         .op = RTE_ETH_INPUT_SET_SELECT,
13487                         .flow_type = i,
13488                         .inset_size = 1,
13489                 };
13490                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13491                 i40e_hash_filter_inset_select(hw, &input_conf);
13492         }
13493
13494         rss_info->conf.types = rss_conf.conf.types;
13495
13496         i40e_rss_clear_hash_function(pf, conf);
13497
13498         return 0;
13499 }
13500
13501 /* Configure RSS queue region to default */
13502 static int
13503 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13504 {
13505         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13506         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13507         uint16_t queue[I40E_MAX_Q_PER_TC];
13508         uint32_t num_rxq, i;
13509         uint32_t lut = 0;
13510         uint16_t j, num;
13511
13512         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13513
13514         for (j = 0; j < num_rxq; j++)
13515                 queue[j] = j;
13516
13517         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13518          * It's necessary to calculate the actual PF queues that are configured.
13519          */
13520         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13521                 num = i40e_pf_calc_configured_queues_num(pf);
13522         else
13523                 num = pf->dev_data->nb_rx_queues;
13524
13525         num = RTE_MIN(num, num_rxq);
13526         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13527                         num);
13528
13529         if (num == 0) {
13530                 PMD_DRV_LOG(ERR,
13531                         "No PF queues are configured to enable RSS for port %u",
13532                         pf->dev_data->port_id);
13533                 return -ENOTSUP;
13534         }
13535
13536         /* Fill in redirection table */
13537         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13538                 if (j == num)
13539                         j = 0;
13540                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13541                         hw->func_caps.rss_table_entry_width) - 1));
13542                 if ((i & 3) == 3)
13543                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13544         }
13545
13546         rss_info->conf.queue_num = 0;
13547         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13548
13549         return 0;
13550 }
13551
13552 int
13553 i40e_config_rss_filter(struct i40e_pf *pf,
13554                 struct i40e_rte_flow_rss_conf *conf, bool add)
13555 {
13556         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13557         struct rte_flow_action_rss update_conf = rss_info->conf;
13558         int ret = 0;
13559
13560         if (add) {
13561                 if (conf->conf.queue_num) {
13562                         /* Configure RSS queue region */
13563                         ret = i40e_rss_config_queue_region(pf, conf);
13564                         if (ret)
13565                                 return ret;
13566
13567                         update_conf.queue_num = conf->conf.queue_num;
13568                         update_conf.queue = conf->conf.queue;
13569                 } else if (conf->conf.func ==
13570                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13571                         /* Configure hash function */
13572                         ret = i40e_rss_config_hash_function(pf, conf);
13573                         if (ret)
13574                                 return ret;
13575
13576                         update_conf.func = conf->conf.func;
13577                 } else {
13578                         /* Configure hash enable and input set */
13579                         ret = i40e_rss_enable_hash(pf, conf);
13580                         if (ret)
13581                                 return ret;
13582
13583                         update_conf.types |= conf->conf.types;
13584                         update_conf.key = conf->conf.key;
13585                         update_conf.key_len = conf->conf.key_len;
13586                 }
13587
13588                 /* Update RSS info in pf */
13589                 if (i40e_rss_conf_init(rss_info, &update_conf))
13590                         return -EINVAL;
13591         } else {
13592                 if (!conf->valid)
13593                         return 0;
13594
13595                 if (conf->conf.queue_num)
13596                         i40e_rss_clear_queue_region(pf);
13597                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13598                         i40e_rss_clear_hash_function(pf, conf);
13599                 else
13600                         i40e_rss_disable_hash(pf, conf);
13601         }
13602
13603         return 0;
13604 }
13605
13606 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13607 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13608 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13609 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13610 #endif
13611 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13612 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13613 #endif
13614 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13615 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13616 #endif
13617
13618 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13619                               ETH_I40E_FLOATING_VEB_ARG "=1"
13620                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13621                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13622                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13623                               ETH_I40E_USE_LATEST_VEC "=0|1");