drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA  0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 133
 134 #define I40E_MAX_PERCENT            100
 135 #define I40E_DEFAULT_DCB_APP_NUM    1
 136 #define I40E_DEFAULT_DCB_APP_PRIO   3
 137
 138 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 139 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 140 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 141 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 143 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 144
 145 #define I40E_INSET_NONE            0x00000000000000000ULL
 146
 147 /* bit0 ~ bit 7 */
 148 #define I40E_INSET_DMAC            0x0000000000000001ULL
 149 #define I40E_INSET_SMAC            0x0000000000000002ULL
 150 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 151 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 152 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 153
 154 /* bit 8 ~ bit 15 */
 155 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 156 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 157 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 158 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 159 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 160 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 161 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 162
 163 /* bit 16 ~ bit 31 */
 164 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 165 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 166 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 167 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 168 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 169 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 170 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 171 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 172
 173 /* bit 32 ~ bit 47, tunnel fields */
 174 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 175 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 176 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 177 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 178 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 179 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 180
 181 /* bit 48 ~ bit 55 */
 182 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 183
 184 /* bit 56 ~ bit 63, Flex Payload */
 185 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD \
 194         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 195         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 196         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 197         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 198
 199 /**
 200  * Below are values for writing un-exposed registers suggested
 201  * by silicon experts
 202  */
 203 /* Destination MAC address */
 204 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 205 /* Source MAC address */
 206 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 207 /* VLAN tag in the outer L2 header */
 208 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 209 /* VLAN tag in the inner L2 header */
 210 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 211 /* Source IPv4 address */
 212 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 213 /* Destination IPv4 address */
 214 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 215 /* IPv4 Type of Service (TOS) */
 216 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 217 /* IPv4 Protocol */
 218 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 219 /* Source IPv6 address */
 220 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 221 /* Destination IPv6 address */
 222 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 223 /* IPv6 Traffic Class (TC) */
 224 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 225 /* IPv6 Next Header */
 226 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263
 264 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 265
 266 #define I40E_TRANSLATE_INSET 0
 267 #define I40E_TRANSLATE_REG   1
 268
 269 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 270 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 271 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 272 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 273
 274 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 275 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 276 static int i40e_dev_configure(struct rte_eth_dev *dev);
 277 static int i40e_dev_start(struct rte_eth_dev *dev);
 278 static void i40e_dev_stop(struct rte_eth_dev *dev);
 279 static void i40e_dev_close(struct rte_eth_dev *dev);
 280 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 281 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 282 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 284 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 285 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 286 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 287                                struct rte_eth_stats *stats);
 288 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_xstats *xstats, unsigned n);
 290 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 291 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
 292 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 293                                             uint16_t queue_id,
 294                                             uint8_t stat_idx,
 295                                             uint8_t is_rx);
 296 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 297                               struct rte_eth_dev_info *dev_info);
 298 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 299                                 uint16_t vlan_id,
 300                                 int on);
 301 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 302 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 303 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 304                                       uint16_t queue,
 305                                       int on);
 306 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 307 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 308 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 309 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 310                               struct rte_eth_fc_conf *fc_conf);
 311 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 312                               struct rte_eth_fc_conf *fc_conf);
 313 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 314                                        struct rte_eth_pfc_conf *pfc_conf);
 315 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 316                           struct ether_addr *mac_addr,
 317                           uint32_t index,
 318                           uint32_t pool);
 319 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 320 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 321                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 322                                     uint16_t reta_size);
 323 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 324                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 325                                    uint16_t reta_size);
 326
 327 static int i40e_get_cap(struct i40e_hw *hw);
 328 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 329 static int i40e_pf_setup(struct i40e_pf *pf);
 330 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 331 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 332 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 333 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 334 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 335                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 336 static void i40e_stat_update_48(struct i40e_hw *hw,
 337                                uint32_t hireg,
 338                                uint32_t loreg,
 339                                bool offset_loaded,
 340                                uint64_t *offset,
 341                                uint64_t *stat);
 342 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 343 static void i40e_dev_interrupt_handler(
 344                 __rte_unused struct rte_intr_handle *handle, void *param);
 345 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 346                                 uint32_t base, uint32_t num);
 347 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 348 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 349                         uint32_t base);
 350 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 351                         uint16_t num);
 352 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 353 static int i40e_veb_release(struct i40e_veb *veb);
 354 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 355                                                 struct i40e_vsi *vsi);
 356 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 357 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 358 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 359                                              struct i40e_macvlan_filter *mv_f,
 360                                              int num,
 361                                              struct ether_addr *addr);
 362 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 363                                              struct i40e_macvlan_filter *mv_f,
 364                                              int num,
 365                                              uint16_t vlan);
 366 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 367 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 368                                     struct rte_eth_rss_conf *rss_conf);
 369 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 370                                       struct rte_eth_rss_conf *rss_conf);
 371 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 372                                 struct rte_eth_udp_tunnel *udp_tunnel);
 373 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 374                                 struct rte_eth_udp_tunnel *udp_tunnel);
 375 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 376                         struct rte_eth_ethertype_filter *filter,
 377                         bool add);
 378 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 379                                 enum rte_filter_op filter_op,
 380                                 void *arg);
 381 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 382                                 enum rte_filter_type filter_type,
 383                                 enum rte_filter_op filter_op,
 384                                 void *arg);
 385 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 386                                   struct rte_eth_dcb_info *dcb_info);
 387 static void i40e_configure_registers(struct i40e_hw *hw);
 388 static void i40e_hw_init(struct i40e_hw *hw);
 389 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 390 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 391                         struct rte_eth_mirror_conf *mirror_conf,
 392                         uint8_t sw_id, uint8_t on);
 393 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 394
 395 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 396 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 397 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 398                                            struct timespec *timestamp,
 399                                            uint32_t flags);
 400 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 401                                            struct timespec *timestamp);
 402 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 403 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 404                                          uint16_t queue_id);
 405 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 406                                           uint16_t queue_id);
 407
 408 static const struct rte_pci_id pci_id_i40e_map[] = {
 409 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 410 #include "rte_pci_dev_ids.h"
 411 { .vendor_id = 0, /* sentinel */ },
 412 };
 413
 414 static const struct eth_dev_ops i40e_eth_dev_ops = {
 415         .dev_configure                = i40e_dev_configure,
 416         .dev_start                    = i40e_dev_start,
 417         .dev_stop                     = i40e_dev_stop,
 418         .dev_close                    = i40e_dev_close,
 419         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 420         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 421         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 422         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 423         .dev_set_link_up              = i40e_dev_set_link_up,
 424         .dev_set_link_down            = i40e_dev_set_link_down,
 425         .link_update                  = i40e_dev_link_update,
 426         .stats_get                    = i40e_dev_stats_get,
 427         .xstats_get                   = i40e_dev_xstats_get,
 428         .stats_reset                  = i40e_dev_stats_reset,
 429         .xstats_reset                 = i40e_dev_xstats_reset,
 430         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 431         .dev_infos_get                = i40e_dev_info_get,
 432         .vlan_filter_set              = i40e_vlan_filter_set,
 433         .vlan_tpid_set                = i40e_vlan_tpid_set,
 434         .vlan_offload_set             = i40e_vlan_offload_set,
 435         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 436         .vlan_pvid_set                = i40e_vlan_pvid_set,
 437         .rx_queue_start               = i40e_dev_rx_queue_start,
 438         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 439         .tx_queue_start               = i40e_dev_tx_queue_start,
 440         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 441         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 442         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 443         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 444         .rx_queue_release             = i40e_dev_rx_queue_release,
 445         .rx_queue_count               = i40e_dev_rx_queue_count,
 446         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 447         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 448         .tx_queue_release             = i40e_dev_tx_queue_release,
 449         .dev_led_on                   = i40e_dev_led_on,
 450         .dev_led_off                  = i40e_dev_led_off,
 451         .flow_ctrl_get                = i40e_flow_ctrl_get,
 452         .flow_ctrl_set                = i40e_flow_ctrl_set,
 453         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 454         .mac_addr_add                 = i40e_macaddr_add,
 455         .mac_addr_remove              = i40e_macaddr_remove,
 456         .reta_update                  = i40e_dev_rss_reta_update,
 457         .reta_query                   = i40e_dev_rss_reta_query,
 458         .rss_hash_update              = i40e_dev_rss_hash_update,
 459         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 460         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 461         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 462         .filter_ctrl                  = i40e_dev_filter_ctrl,
 463         .rxq_info_get                 = i40e_rxq_info_get,
 464         .txq_info_get                 = i40e_txq_info_get,
 465         .mirror_rule_set              = i40e_mirror_rule_set,
 466         .mirror_rule_reset            = i40e_mirror_rule_reset,
 467         .timesync_enable              = i40e_timesync_enable,
 468         .timesync_disable             = i40e_timesync_disable,
 469         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 470         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 471         .get_dcb_info                 = i40e_dev_get_dcb_info,
 472 };
 473
 474 /* store statistics names and its offset in stats structure */
 475 struct rte_i40e_xstats_name_off {
 476         char name[RTE_ETH_XSTATS_NAME_SIZE];
 477         unsigned offset;
 478 };
 479
 480 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 481         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 482         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 483         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 484         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 485         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 486                 rx_unknown_protocol)},
 487         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 488         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 489         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 490         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 491 };
 492
 493 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 494         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 495                 tx_dropped_link_down)},
 496         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 497         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 498                 illegal_bytes)},
 499         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 500         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 501                 mac_local_faults)},
 502         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 503                 mac_remote_faults)},
 504         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 505                 rx_length_errors)},
 506         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 507         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 508         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 509         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 510         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 511         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 512                 rx_size_127)},
 513         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 514                 rx_size_255)},
 515         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 516                 rx_size_511)},
 517         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 518                 rx_size_1023)},
 519         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 520                 rx_size_1522)},
 521         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 522                 rx_size_big)},
 523         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 524                 rx_undersize)},
 525         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 526                 rx_oversize)},
 527         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 528                 mac_short_packet_dropped)},
 529         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 530                 rx_fragments)},
 531         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 532         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 533         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 534                 tx_size_127)},
 535         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 536                 tx_size_255)},
 537         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 538                 tx_size_511)},
 539         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 540                 tx_size_1023)},
 541         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 542                 tx_size_1522)},
 543         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 544                 tx_size_big)},
 545         {"rx_flow_director_atr_match_packets",
 546                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 547         {"rx_flow_director_sb_match_packets",
 548                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 549         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 550                 tx_lpi_status)},
 551         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 552                 rx_lpi_status)},
 553         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 554                 tx_lpi_count)},
 555         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 556                 rx_lpi_count)},
 557 };
 558
 559 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
 560 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
 561
 562 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 563                 sizeof(rte_i40e_stats_strings[0]))
 564 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 565                 sizeof(rte_i40e_hw_port_strings[0]))
 566 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
 567                 I40E_NB_HW_PORT_Q_STATS)
 568
 569 static struct eth_driver rte_i40e_pmd = {
 570         .pci_drv = {
 571                 .name = "rte_i40e_pmd",
 572                 .id_table = pci_id_i40e_map,
 573                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 574                         RTE_PCI_DRV_DETACHABLE,
 575         },
 576         .eth_dev_init = eth_i40e_dev_init,
 577         .eth_dev_uninit = eth_i40e_dev_uninit,
 578         .dev_private_size = sizeof(struct i40e_adapter),
 579 };
 580
 581 static inline int
 582 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 583                                      struct rte_eth_link *link)
 584 {
 585         struct rte_eth_link *dst = link;
 586         struct rte_eth_link *src = &(dev->data->dev_link);
 587
 588         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 589                                         *(uint64_t *)src) == 0)
 590                 return -1;
 591
 592         return 0;
 593 }
 594
 595 static inline int
 596 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 597                                       struct rte_eth_link *link)
 598 {
 599         struct rte_eth_link *dst = &(dev->data->dev_link);
 600         struct rte_eth_link *src = link;
 601
 602         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 603                                         *(uint64_t *)src) == 0)
 604                 return -1;
 605
 606         return 0;
 607 }
 608
 609 /*
 610  * Driver initialization routine.
 611  * Invoked once at EAL init time.
 612  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 613  */
 614 static int
 615 rte_i40e_pmd_init(const char *name __rte_unused,
 616                   const char *params __rte_unused)
 617 {
 618         PMD_INIT_FUNC_TRACE();
 619         rte_eth_driver_register(&rte_i40e_pmd);
 620
 621         return 0;
 622 }
 623
 624 static struct rte_driver rte_i40e_driver = {
 625         .type = PMD_PDEV,
 626         .init = rte_i40e_pmd_init,
 627 };
 628
 629 PMD_REGISTER_DRIVER(rte_i40e_driver);
 630
 631 /*
 632  * Initialize registers for flexible payload, which should be set by NVM.
 633  * This should be removed from code once it is fixed in NVM.
 634  */
 635 #ifndef I40E_GLQF_ORT
 636 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 637 #endif
 638 #ifndef I40E_GLQF_PIT
 639 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 640 #endif
 641
 642 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 643 {
 644         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 645         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 646         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 647         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 648         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 649         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 650         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 651         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 652         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 653         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 654
 655         /* GLQF_PIT Registers */
 656         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 657         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 658 }
 659
 660 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 661
 662 /*
 663  * Add a ethertype filter to drop all flow control frames transmitted
 664  * from VSIs.
 665 */
 666 static void
 667 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 668 {
 669         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 670         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 671                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 672                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 673         int ret;
 674
 675         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 676                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 677                                 pf->main_vsi_seid, 0,
 678                                 TRUE, NULL, NULL);
 679         if (ret)
 680                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 681                                   " frames from VSIs.");
 682 }
 683
 684 static int
 685 eth_i40e_dev_init(struct rte_eth_dev *dev)
 686 {
 687         struct rte_pci_device *pci_dev;
 688         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 690         struct i40e_vsi *vsi;
 691         int ret;
 692         uint32_t len;
 693         uint8_t aq_fail = 0;
 694
 695         PMD_INIT_FUNC_TRACE();
 696
 697         dev->dev_ops = &i40e_eth_dev_ops;
 698         dev->rx_pkt_burst = i40e_recv_pkts;
 699         dev->tx_pkt_burst = i40e_xmit_pkts;
 700
 701         /* for secondary processes, we don't initialise any further as primary
 702          * has already done this work. Only check we don't need a different
 703          * RX function */
 704         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 705                 i40e_set_rx_function(dev);
 706                 i40e_set_tx_function(dev);
 707                 return 0;
 708         }
 709         pci_dev = dev->pci_dev;
 710
 711         rte_eth_copy_pci_info(dev, pci_dev);
 712
 713         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 714         pf->adapter->eth_dev = dev;
 715         pf->dev_data = dev->data;
 716
 717         hw->back = I40E_PF_TO_ADAPTER(pf);
 718         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 719         if (!hw->hw_addr) {
 720                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 721                              "as address is NULL");
 722                 return -ENODEV;
 723         }
 724
 725         hw->vendor_id = pci_dev->id.vendor_id;
 726         hw->device_id = pci_dev->id.device_id;
 727         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 728         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 729         hw->bus.device = pci_dev->addr.devid;
 730         hw->bus.func = pci_dev->addr.function;
 731         hw->adapter_stopped = 0;
 732
 733         /* Make sure all is clean before doing PF reset */
 734         i40e_clear_hw(hw);
 735
 736         /* Initialize the hardware */
 737         i40e_hw_init(hw);
 738
 739         /* Reset here to make sure all is clean for each PF */
 740         ret = i40e_pf_reset(hw);
 741         if (ret) {
 742                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 743                 return ret;
 744         }
 745
 746         /* Initialize the shared code (base driver) */
 747         ret = i40e_init_shared_code(hw);
 748         if (ret) {
 749                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 750                 return ret;
 751         }
 752
 753         /*
 754          * To work around the NVM issue,initialize registers
 755          * for flexible payload by software.
 756          * It should be removed once issues are fixed in NVM.
 757          */
 758         i40e_flex_payload_reg_init(hw);
 759
 760         /* Initialize the parameters for adminq */
 761         i40e_init_adminq_parameter(hw);
 762         ret = i40e_init_adminq(hw);
 763         if (ret != I40E_SUCCESS) {
 764                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 765                 return -EIO;
 766         }
 767         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 768                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 769                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 770                      ((hw->nvm.version >> 12) & 0xf),
 771                      ((hw->nvm.version >> 4) & 0xff),
 772                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 773
 774         /* Clear PXE mode */
 775         i40e_clear_pxe_mode(hw);
 776
 777         /*
 778          * On X710, performance number is far from the expectation on recent
 779          * firmware versions. The fix for this issue may not be integrated in
 780          * the following firmware version. So the workaround in software driver
 781          * is needed. It needs to modify the initial values of 3 internal only
 782          * registers. Note that the workaround can be removed when it is fixed
 783          * in firmware in the future.
 784          */
 785         i40e_configure_registers(hw);
 786
 787         /* Get hw capabilities */
 788         ret = i40e_get_cap(hw);
 789         if (ret != I40E_SUCCESS) {
 790                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 791                 goto err_get_capabilities;
 792         }
 793
 794         /* Initialize parameters for PF */
 795         ret = i40e_pf_parameter_init(dev);
 796         if (ret != 0) {
 797                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 798                 goto err_parameter_init;
 799         }
 800
 801         /* Initialize the queue management */
 802         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 803         if (ret < 0) {
 804                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 805                 goto err_qp_pool_init;
 806         }
 807         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 808                                 hw->func_caps.num_msix_vectors - 1);
 809         if (ret < 0) {
 810                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 811                 goto err_msix_pool_init;
 812         }
 813
 814         /* Initialize lan hmc */
 815         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 816                                 hw->func_caps.num_rx_qp, 0, 0);
 817         if (ret != I40E_SUCCESS) {
 818                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 819                 goto err_init_lan_hmc;
 820         }
 821
 822         /* Configure lan hmc */
 823         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 824         if (ret != I40E_SUCCESS) {
 825                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 826                 goto err_configure_lan_hmc;
 827         }
 828
 829         /* Get and check the mac address */
 830         i40e_get_mac_addr(hw, hw->mac.addr);
 831         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 832                 PMD_INIT_LOG(ERR, "mac address is not valid");
 833                 ret = -EIO;
 834                 goto err_get_mac_addr;
 835         }
 836         /* Copy the permanent MAC address */
 837         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 838                         (struct ether_addr *) hw->mac.perm_addr);
 839
 840         /* Disable flow control */
 841         hw->fc.requested_mode = I40E_FC_NONE;
 842         i40e_set_fc(hw, &aq_fail, TRUE);
 843
 844         /* PF setup, which includes VSI setup */
 845         ret = i40e_pf_setup(pf);
 846         if (ret) {
 847                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 848                 goto err_setup_pf_switch;
 849         }
 850
 851         vsi = pf->main_vsi;
 852
 853         /* Disable double vlan by default */
 854         i40e_vsi_config_double_vlan(vsi, FALSE);
 855
 856         if (!vsi->max_macaddrs)
 857                 len = ETHER_ADDR_LEN;
 858         else
 859                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 860
 861         /* Should be after VSI initialized */
 862         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 863         if (!dev->data->mac_addrs) {
 864                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 865                                         "for storing mac address");
 866                 goto err_mac_alloc;
 867         }
 868         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 869                                         &dev->data->mac_addrs[0]);
 870
 871         /* initialize pf host driver to setup SRIOV resource if applicable */
 872         i40e_pf_host_init(dev);
 873
 874         /* register callback func to eal lib */
 875         rte_intr_callback_register(&(pci_dev->intr_handle),
 876                 i40e_dev_interrupt_handler, (void *)dev);
 877
 878         /* configure and enable device interrupt */
 879         i40e_pf_config_irq0(hw, TRUE);
 880         i40e_pf_enable_irq0(hw);
 881
 882         /* enable uio intr after callback register */
 883         rte_intr_enable(&(pci_dev->intr_handle));
 884         /*
 885          * Add an ethertype filter to drop all flow control frames transmitted
 886          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 887          * frames to wire.
 888          */
 889         i40e_add_tx_flow_control_drop_filter(pf);
 890
 891         /* initialize mirror rule list */
 892         TAILQ_INIT(&pf->mirror_list);
 893
 894         /* Init dcb to sw mode by default */
 895         ret = i40e_dcb_init_configure(dev, TRUE);
 896         if (ret != I40E_SUCCESS) {
 897                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 898                 pf->flags &= ~I40E_FLAG_DCB;
 899         }
 900
 901         return 0;
 902
 903 err_mac_alloc:
 904         i40e_vsi_release(pf->main_vsi);
 905 err_setup_pf_switch:
 906 err_get_mac_addr:
 907 err_configure_lan_hmc:
 908         (void)i40e_shutdown_lan_hmc(hw);
 909 err_init_lan_hmc:
 910         i40e_res_pool_destroy(&pf->msix_pool);
 911 err_msix_pool_init:
 912         i40e_res_pool_destroy(&pf->qp_pool);
 913 err_qp_pool_init:
 914 err_parameter_init:
 915 err_get_capabilities:
 916         (void)i40e_shutdown_adminq(hw);
 917
 918         return ret;
 919 }
 920
 921 static int
 922 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 923 {
 924         struct rte_pci_device *pci_dev;
 925         struct i40e_hw *hw;
 926         struct i40e_filter_control_settings settings;
 927         int ret;
 928         uint8_t aq_fail = 0;
 929
 930         PMD_INIT_FUNC_TRACE();
 931
 932         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 933                 return 0;
 934
 935         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936         pci_dev = dev->pci_dev;
 937
 938         if (hw->adapter_stopped == 0)
 939                 i40e_dev_close(dev);
 940
 941         dev->dev_ops = NULL;
 942         dev->rx_pkt_burst = NULL;
 943         dev->tx_pkt_burst = NULL;
 944
 945         /* Disable LLDP */
 946         ret = i40e_aq_stop_lldp(hw, true, NULL);
 947         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 948                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 949
 950         /* Clear PXE mode */
 951         i40e_clear_pxe_mode(hw);
 952
 953         /* Unconfigure filter control */
 954         memset(&settings, 0, sizeof(settings));
 955         ret = i40e_set_filter_control(hw, &settings);
 956         if (ret)
 957                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 958                                         ret);
 959
 960         /* Disable flow control */
 961         hw->fc.requested_mode = I40E_FC_NONE;
 962         i40e_set_fc(hw, &aq_fail, TRUE);
 963
 964         /* uninitialize pf host driver */
 965         i40e_pf_host_uninit(dev);
 966
 967         rte_free(dev->data->mac_addrs);
 968         dev->data->mac_addrs = NULL;
 969
 970         /* disable uio intr before callback unregister */
 971         rte_intr_disable(&(pci_dev->intr_handle));
 972
 973         /* register callback func to eal lib */
 974         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 975                 i40e_dev_interrupt_handler, (void *)dev);
 976
 977         return 0;
 978 }
 979
 980 static int
 981 i40e_dev_configure(struct rte_eth_dev *dev)
 982 {
 983         struct i40e_adapter *ad =
 984                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 986         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 987         int i, ret;
 988
 989         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 990          * bulk allocation or vector Rx preconditions we will reset it.
 991          */
 992         ad->rx_bulk_alloc_allowed = true;
 993         ad->rx_vec_allowed = true;
 994         ad->tx_simple_allowed = true;
 995         ad->tx_vec_allowed = true;
 996
 997         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 998                 ret = i40e_fdir_setup(pf);
 999                 if (ret != I40E_SUCCESS) {
1000                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1001                         return -ENOTSUP;
1002                 }
1003                 ret = i40e_fdir_configure(dev);
1004                 if (ret < 0) {
1005                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1006                         goto err;
1007                 }
1008         } else
1009                 i40e_fdir_teardown(pf);
1010
1011         ret = i40e_dev_init_vlan(dev);
1012         if (ret < 0)
1013                 goto err;
1014
1015         /* VMDQ setup.
1016          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1017          *  RSS setting have different requirements.
1018          *  General PMD driver call sequence are NIC init, configure,
1019          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1020          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1021          *  applicable. So, VMDQ setting has to be done before
1022          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1023          *  For RSS setting, it will try to calculate actual configured RX queue
1024          *  number, which will be available after rx_queue_setup(). dev_start()
1025          *  function is good to place RSS setup.
1026          */
1027         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1028                 ret = i40e_vmdq_setup(dev);
1029                 if (ret)
1030                         goto err;
1031         }
1032
1033         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1034                 ret = i40e_dcb_setup(dev);
1035                 if (ret) {
1036                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1037                         goto err_dcb;
1038                 }
1039         }
1040
1041         return 0;
1042
1043 err_dcb:
1044         /* need to release vmdq resource if exists */
1045         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1046                 i40e_vsi_release(pf->vmdq[i].vsi);
1047                 pf->vmdq[i].vsi = NULL;
1048         }
1049         rte_free(pf->vmdq);
1050         pf->vmdq = NULL;
1051 err:
1052         /* need to release fdir resource if exists */
1053         i40e_fdir_teardown(pf);
1054         return ret;
1055 }
1056
1057 void
1058 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1059 {
1060         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1061         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1062         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1063         uint16_t msix_vect = vsi->msix_intr;
1064         uint16_t i;
1065
1066         for (i = 0; i < vsi->nb_qps; i++) {
1067                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1068                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1069                 rte_wmb();
1070         }
1071
1072         if (vsi->type != I40E_VSI_SRIOV) {
1073                 if (!rte_intr_allow_others(intr_handle)) {
1074                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1075                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1076                         I40E_WRITE_REG(hw,
1077                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1078                                        0);
1079                 } else {
1080                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1081                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1082                         I40E_WRITE_REG(hw,
1083                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1084                                                        msix_vect - 1), 0);
1085                 }
1086         } else {
1087                 uint32_t reg;
1088                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1089                         vsi->user_param + (msix_vect - 1);
1090
1091                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1092                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1093         }
1094         I40E_WRITE_FLUSH(hw);
1095 }
1096
1097 static void
1098 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1099                        int base_queue, int nb_queue)
1100 {
1101         int i;
1102         uint32_t val;
1103         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1104
1105         /* Bind all RX queues to allocated MSIX interrupt */
1106         for (i = 0; i < nb_queue; i++) {
1107                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1108                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1109                         ((base_queue + i + 1) <<
1110                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1111                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1112                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1113
1114                 if (i == nb_queue - 1)
1115                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1116                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1117         }
1118
1119         /* Write first RX queue to Link list register as the head element */
1120         if (vsi->type != I40E_VSI_SRIOV) {
1121                 uint16_t interval =
1122                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1123
1124                 if (msix_vect == I40E_MISC_VEC_ID) {
1125                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1126                                        (base_queue <<
1127                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1128                                        (0x0 <<
1129                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1130                         I40E_WRITE_REG(hw,
1131                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1132                                        interval);
1133                 } else {
1134                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1135                                        (base_queue <<
1136                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1137                                        (0x0 <<
1138                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1139                         I40E_WRITE_REG(hw,
1140                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1141                                                        msix_vect - 1),
1142                                        interval);
1143                 }
1144         } else {
1145                 uint32_t reg;
1146
1147                 if (msix_vect == I40E_MISC_VEC_ID) {
1148                         I40E_WRITE_REG(hw,
1149                                        I40E_VPINT_LNKLST0(vsi->user_param),
1150                                        (base_queue <<
1151                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1152                                        (0x0 <<
1153                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1154                 } else {
1155                         /* num_msix_vectors_vf needs to minus irq0 */
1156                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1157                                 vsi->user_param + (msix_vect - 1);
1158
1159                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1160                                        (base_queue <<
1161                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1162                                        (0x0 <<
1163                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1164                 }
1165         }
1166
1167         I40E_WRITE_FLUSH(hw);
1168 }
1169
1170 void
1171 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1172 {
1173         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1174         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1175         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1176         uint16_t msix_vect = vsi->msix_intr;
1177         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1178         uint16_t queue_idx = 0;
1179         int record = 0;
1180         uint32_t val;
1181         int i;
1182
1183         for (i = 0; i < vsi->nb_qps; i++) {
1184                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1185                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1186         }
1187
1188         /* INTENA flag is not auto-cleared for interrupt */
1189         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1190         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1191                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1192                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1193         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1194
1195         /* VF bind interrupt */
1196         if (vsi->type == I40E_VSI_SRIOV) {
1197                 __vsi_queues_bind_intr(vsi, msix_vect,
1198                                        vsi->base_queue, vsi->nb_qps);
1199                 return;
1200         }
1201
1202         /* PF & VMDq bind interrupt */
1203         if (rte_intr_dp_is_en(intr_handle)) {
1204                 if (vsi->type == I40E_VSI_MAIN) {
1205                         queue_idx = 0;
1206                         record = 1;
1207                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1208                         struct i40e_vsi *main_vsi =
1209                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1210                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1211                         record = 1;
1212                 }
1213         }
1214
1215         for (i = 0; i < vsi->nb_used_qps; i++) {
1216                 if (nb_msix <= 1) {
1217                         if (!rte_intr_allow_others(intr_handle))
1218                                 /* allow to share MISC_VEC_ID */
1219                                 msix_vect = I40E_MISC_VEC_ID;
1220
1221                         /* no enough msix_vect, map all to one */
1222                         __vsi_queues_bind_intr(vsi, msix_vect,
1223                                                vsi->base_queue + i,
1224                                                vsi->nb_used_qps - i);
1225                         for (; !!record && i < vsi->nb_used_qps; i++)
1226                                 intr_handle->intr_vec[queue_idx + i] =
1227                                         msix_vect;
1228                         break;
1229                 }
1230                 /* 1:1 queue/msix_vect mapping */
1231                 __vsi_queues_bind_intr(vsi, msix_vect,
1232                                        vsi->base_queue + i, 1);
1233                 if (!!record)
1234                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1235
1236                 msix_vect++;
1237                 nb_msix--;
1238         }
1239 }
1240
1241 static void
1242 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1243 {
1244         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1245         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1246         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1247         uint16_t interval = i40e_calc_itr_interval(\
1248                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1249         uint16_t msix_intr, i;
1250
1251         if (rte_intr_allow_others(intr_handle))
1252                 for (i = 0; i < vsi->nb_msix; i++) {
1253                         msix_intr = vsi->msix_intr + i;
1254                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1255                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1256                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1257                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1258                                 (interval <<
1259                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1260                 }
1261         else
1262                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1263                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1264                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1265                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1266                                (interval <<
1267                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1268
1269         I40E_WRITE_FLUSH(hw);
1270 }
1271
1272 static void
1273 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1274 {
1275         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1276         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1278         uint16_t msix_intr, i;
1279
1280         if (rte_intr_allow_others(intr_handle))
1281                 for (i = 0; i < vsi->nb_msix; i++) {
1282                         msix_intr = vsi->msix_intr + i;
1283                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1284                                        0);
1285                 }
1286         else
1287                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1288
1289         I40E_WRITE_FLUSH(hw);
1290 }
1291
1292 static inline uint8_t
1293 i40e_parse_link_speed(uint16_t eth_link_speed)
1294 {
1295         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1296
1297         switch (eth_link_speed) {
1298         case ETH_LINK_SPEED_40G:
1299                 link_speed = I40E_LINK_SPEED_40GB;
1300                 break;
1301         case ETH_LINK_SPEED_20G:
1302                 link_speed = I40E_LINK_SPEED_20GB;
1303                 break;
1304         case ETH_LINK_SPEED_10G:
1305                 link_speed = I40E_LINK_SPEED_10GB;
1306                 break;
1307         case ETH_LINK_SPEED_1000:
1308                 link_speed = I40E_LINK_SPEED_1GB;
1309                 break;
1310         case ETH_LINK_SPEED_100:
1311                 link_speed = I40E_LINK_SPEED_100MB;
1312                 break;
1313         }
1314
1315         return link_speed;
1316 }
1317
1318 static int
1319 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1320 {
1321         enum i40e_status_code status;
1322         struct i40e_aq_get_phy_abilities_resp phy_ab;
1323         struct i40e_aq_set_phy_config phy_conf;
1324         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1325                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1326                         I40E_AQ_PHY_FLAG_LOW_POWER;
1327         const uint8_t advt = I40E_LINK_SPEED_40GB |
1328                         I40E_LINK_SPEED_10GB |
1329                         I40E_LINK_SPEED_1GB |
1330                         I40E_LINK_SPEED_100MB;
1331         int ret = -ENOTSUP;
1332
1333         /* Skip it on 40G interfaces, as a workaround for the link issue */
1334         if (i40e_is_40G_device(hw->device_id))
1335                 return I40E_SUCCESS;
1336
1337         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1338                                               NULL);
1339         if (status)
1340                 return ret;
1341
1342         memset(&phy_conf, 0, sizeof(phy_conf));
1343
1344         /* bits 0-2 use the values from get_phy_abilities_resp */
1345         abilities &= ~mask;
1346         abilities |= phy_ab.abilities & mask;
1347
1348         /* update ablities and speed */
1349         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1350                 phy_conf.link_speed = advt;
1351         else
1352                 phy_conf.link_speed = force_speed;
1353
1354         phy_conf.abilities = abilities;
1355
1356         /* use get_phy_abilities_resp value for the rest */
1357         phy_conf.phy_type = phy_ab.phy_type;
1358         phy_conf.eee_capability = phy_ab.eee_capability;
1359         phy_conf.eeer = phy_ab.eeer_val;
1360         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1361
1362         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1363                     phy_ab.abilities, phy_ab.link_speed);
1364         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1365                     phy_conf.abilities, phy_conf.link_speed);
1366
1367         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1368         if (status)
1369                 return ret;
1370
1371         return I40E_SUCCESS;
1372 }
1373
1374 static int
1375 i40e_apply_link_speed(struct rte_eth_dev *dev)
1376 {
1377         uint8_t speed;
1378         uint8_t abilities = 0;
1379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380         struct rte_eth_conf *conf = &dev->data->dev_conf;
1381
1382         speed = i40e_parse_link_speed(conf->link_speed);
1383         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1384         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1385                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1386         else
1387                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1388
1389         return i40e_phy_conf_link(hw, abilities, speed);
1390 }
1391
1392 static int
1393 i40e_dev_start(struct rte_eth_dev *dev)
1394 {
1395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         struct i40e_vsi *main_vsi = pf->main_vsi;
1398         int ret, i;
1399         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1400         uint32_t intr_vector = 0;
1401
1402         hw->adapter_stopped = 0;
1403
1404         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1405                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1406                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1407                              dev->data->dev_conf.link_duplex,
1408                              dev->data->port_id);
1409                 return -EINVAL;
1410         }
1411
1412         rte_intr_disable(intr_handle);
1413
1414         if ((rte_intr_cap_multiple(intr_handle) ||
1415              !RTE_ETH_DEV_SRIOV(dev).active) &&
1416             dev->data->dev_conf.intr_conf.rxq != 0) {
1417                 intr_vector = dev->data->nb_rx_queues;
1418                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1419                         return -1;
1420         }
1421
1422         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1423                 intr_handle->intr_vec =
1424                         rte_zmalloc("intr_vec",
1425                                     dev->data->nb_rx_queues * sizeof(int),
1426                                     0);
1427                 if (!intr_handle->intr_vec) {
1428                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1429                                      " intr_vec\n", dev->data->nb_rx_queues);
1430                         return -ENOMEM;
1431                 }
1432         }
1433
1434         /* Initialize VSI */
1435         ret = i40e_dev_rxtx_init(pf);
1436         if (ret != I40E_SUCCESS) {
1437                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1438                 goto err_up;
1439         }
1440
1441         /* Map queues with MSIX interrupt */
1442         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1443                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1444         i40e_vsi_queues_bind_intr(main_vsi);
1445         i40e_vsi_enable_queues_intr(main_vsi);
1446
1447         /* Map VMDQ VSI queues with MSIX interrupt */
1448         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1449                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1450                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1451                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1452         }
1453
1454         /* enable FDIR MSIX interrupt */
1455         if (pf->fdir.fdir_vsi) {
1456                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1457                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1458         }
1459
1460         /* Enable all queues which have been configured */
1461         ret = i40e_dev_switch_queues(pf, TRUE);
1462         if (ret != I40E_SUCCESS) {
1463                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1464                 goto err_up;
1465         }
1466
1467         /* Enable receiving broadcast packets */
1468         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1469         if (ret != I40E_SUCCESS)
1470                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1471
1472         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1473                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1474                                                 true, NULL);
1475                 if (ret != I40E_SUCCESS)
1476                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1477         }
1478
1479         /* Apply link configure */
1480         ret = i40e_apply_link_speed(dev);
1481         if (I40E_SUCCESS != ret) {
1482                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1483                 goto err_up;
1484         }
1485
1486         if (!rte_intr_allow_others(intr_handle)) {
1487                 rte_intr_callback_unregister(intr_handle,
1488                                              i40e_dev_interrupt_handler,
1489                                              (void *)dev);
1490                 /* configure and enable device interrupt */
1491                 i40e_pf_config_irq0(hw, FALSE);
1492                 i40e_pf_enable_irq0(hw);
1493
1494                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1495                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1496                                      " no intr multiplex\n");
1497         }
1498
1499         /* enable uio intr after callback register */
1500         rte_intr_enable(intr_handle);
1501
1502         return I40E_SUCCESS;
1503
1504 err_up:
1505         i40e_dev_switch_queues(pf, FALSE);
1506         i40e_dev_clear_queues(dev);
1507
1508         return ret;
1509 }
1510
1511 static void
1512 i40e_dev_stop(struct rte_eth_dev *dev)
1513 {
1514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515         struct i40e_vsi *main_vsi = pf->main_vsi;
1516         struct i40e_mirror_rule *p_mirror;
1517         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1518         int i;
1519
1520         /* Disable all queues */
1521         i40e_dev_switch_queues(pf, FALSE);
1522
1523         /* un-map queues with interrupt registers */
1524         i40e_vsi_disable_queues_intr(main_vsi);
1525         i40e_vsi_queues_unbind_intr(main_vsi);
1526
1527         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1528                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1529                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1530         }
1531
1532         if (pf->fdir.fdir_vsi) {
1533                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1534                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1535         }
1536         /* Clear all queues and release memory */
1537         i40e_dev_clear_queues(dev);
1538
1539         /* Set link down */
1540         i40e_dev_set_link_down(dev);
1541
1542         /* Remove all mirror rules */
1543         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1544                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1545                 rte_free(p_mirror);
1546         }
1547         pf->nb_mirror_rule = 0;
1548
1549         if (!rte_intr_allow_others(intr_handle))
1550                 /* resume to the default handler */
1551                 rte_intr_callback_register(intr_handle,
1552                                            i40e_dev_interrupt_handler,
1553                                            (void *)dev);
1554
1555         /* Clean datapath event and queue/vec mapping */
1556         rte_intr_efd_disable(intr_handle);
1557         if (intr_handle->intr_vec) {
1558                 rte_free(intr_handle->intr_vec);
1559                 intr_handle->intr_vec = NULL;
1560         }
1561 }
1562
1563 static void
1564 i40e_dev_close(struct rte_eth_dev *dev)
1565 {
1566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568         uint32_t reg;
1569         int i;
1570
1571         PMD_INIT_FUNC_TRACE();
1572
1573         i40e_dev_stop(dev);
1574         hw->adapter_stopped = 1;
1575         i40e_dev_free_queues(dev);
1576
1577         /* Disable interrupt */
1578         i40e_pf_disable_irq0(hw);
1579         rte_intr_disable(&(dev->pci_dev->intr_handle));
1580
1581         /* shutdown and destroy the HMC */
1582         i40e_shutdown_lan_hmc(hw);
1583
1584         /* release all the existing VSIs and VEBs */
1585         i40e_fdir_teardown(pf);
1586         i40e_vsi_release(pf->main_vsi);
1587
1588         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1589                 i40e_vsi_release(pf->vmdq[i].vsi);
1590                 pf->vmdq[i].vsi = NULL;
1591         }
1592
1593         rte_free(pf->vmdq);
1594         pf->vmdq = NULL;
1595
1596         /* shutdown the adminq */
1597         i40e_aq_queue_shutdown(hw, true);
1598         i40e_shutdown_adminq(hw);
1599
1600         i40e_res_pool_destroy(&pf->qp_pool);
1601         i40e_res_pool_destroy(&pf->msix_pool);
1602
1603         /* force a PF reset to clean anything leftover */
1604         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1605         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1606                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1607         I40E_WRITE_FLUSH(hw);
1608 }
1609
1610 static void
1611 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1612 {
1613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1614         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615         struct i40e_vsi *vsi = pf->main_vsi;
1616         int status;
1617
1618         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1619                                                         true, NULL);
1620         if (status != I40E_SUCCESS)
1621                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1622
1623         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1624                                                         TRUE, NULL);
1625         if (status != I40E_SUCCESS)
1626                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1627
1628 }
1629
1630 static void
1631 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1632 {
1633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635         struct i40e_vsi *vsi = pf->main_vsi;
1636         int status;
1637
1638         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1639                                                         false, NULL);
1640         if (status != I40E_SUCCESS)
1641                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1642
1643         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1644                                                         false, NULL);
1645         if (status != I40E_SUCCESS)
1646                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1647 }
1648
1649 static void
1650 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1651 {
1652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         struct i40e_vsi *vsi = pf->main_vsi;
1655         int ret;
1656
1657         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1658         if (ret != I40E_SUCCESS)
1659                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1660 }
1661
1662 static void
1663 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1664 {
1665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667         struct i40e_vsi *vsi = pf->main_vsi;
1668         int ret;
1669
1670         if (dev->data->promiscuous == 1)
1671                 return; /* must remain in all_multicast mode */
1672
1673         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1674                                 vsi->seid, FALSE, NULL);
1675         if (ret != I40E_SUCCESS)
1676                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1677 }
1678
1679 /*
1680  * Set device link up.
1681  */
1682 static int
1683 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1684 {
1685         /* re-apply link speed setting */
1686         return i40e_apply_link_speed(dev);
1687 }
1688
1689 /*
1690  * Set device link down.
1691  */
1692 static int
1693 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1694 {
1695         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1696         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698
1699         return i40e_phy_conf_link(hw, abilities, speed);
1700 }
1701
1702 int
1703 i40e_dev_link_update(struct rte_eth_dev *dev,
1704                      int wait_to_complete)
1705 {
1706 #define CHECK_INTERVAL 100  /* 100ms */
1707 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         struct i40e_link_status link_status;
1710         struct rte_eth_link link, old;
1711         int status;
1712         unsigned rep_cnt = MAX_REPEAT_TIME;
1713
1714         memset(&link, 0, sizeof(link));
1715         memset(&old, 0, sizeof(old));
1716         memset(&link_status, 0, sizeof(link_status));
1717         rte_i40e_dev_atomic_read_link_status(dev, &old);
1718
1719         do {
1720                 /* Get link status information from hardware */
1721                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1722                 if (status != I40E_SUCCESS) {
1723                         link.link_speed = ETH_LINK_SPEED_100;
1724                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1725                         PMD_DRV_LOG(ERR, "Failed to get link info");
1726                         goto out;
1727                 }
1728
1729                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1730                 if (!wait_to_complete)
1731                         break;
1732
1733                 rte_delay_ms(CHECK_INTERVAL);
1734         } while (!link.link_status && rep_cnt--);
1735
1736         if (!link.link_status)
1737                 goto out;
1738
1739         /* i40e uses full duplex only */
1740         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1741
1742         /* Parse the link status */
1743         switch (link_status.link_speed) {
1744         case I40E_LINK_SPEED_100MB:
1745                 link.link_speed = ETH_LINK_SPEED_100;
1746                 break;
1747         case I40E_LINK_SPEED_1GB:
1748                 link.link_speed = ETH_LINK_SPEED_1000;
1749                 break;
1750         case I40E_LINK_SPEED_10GB:
1751                 link.link_speed = ETH_LINK_SPEED_10G;
1752                 break;
1753         case I40E_LINK_SPEED_20GB:
1754                 link.link_speed = ETH_LINK_SPEED_20G;
1755                 break;
1756         case I40E_LINK_SPEED_40GB:
1757                 link.link_speed = ETH_LINK_SPEED_40G;
1758                 break;
1759         default:
1760                 link.link_speed = ETH_LINK_SPEED_100;
1761                 break;
1762         }
1763
1764 out:
1765         rte_i40e_dev_atomic_write_link_status(dev, &link);
1766         if (link.link_status == old.link_status)
1767                 return -1;
1768
1769         return 0;
1770 }
1771
1772 /* Get all the statistics of a VSI */
1773 void
1774 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1775 {
1776         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1777         struct i40e_eth_stats *nes = &vsi->eth_stats;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1780
1781         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1782                             vsi->offset_loaded, &oes->rx_bytes,
1783                             &nes->rx_bytes);
1784         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1785                             vsi->offset_loaded, &oes->rx_unicast,
1786                             &nes->rx_unicast);
1787         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1788                             vsi->offset_loaded, &oes->rx_multicast,
1789                             &nes->rx_multicast);
1790         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1791                             vsi->offset_loaded, &oes->rx_broadcast,
1792                             &nes->rx_broadcast);
1793         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1794                             &oes->rx_discards, &nes->rx_discards);
1795         /* GLV_REPC not supported */
1796         /* GLV_RMPC not supported */
1797         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1798                             &oes->rx_unknown_protocol,
1799                             &nes->rx_unknown_protocol);
1800         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1801                             vsi->offset_loaded, &oes->tx_bytes,
1802                             &nes->tx_bytes);
1803         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1804                             vsi->offset_loaded, &oes->tx_unicast,
1805                             &nes->tx_unicast);
1806         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1807                             vsi->offset_loaded, &oes->tx_multicast,
1808                             &nes->tx_multicast);
1809         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1810                             vsi->offset_loaded,  &oes->tx_broadcast,
1811                             &nes->tx_broadcast);
1812         /* GLV_TDPC not supported */
1813         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1814                             &oes->tx_errors, &nes->tx_errors);
1815         vsi->offset_loaded = true;
1816
1817         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1818                     vsi->vsi_id);
1819         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1820         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1821         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1822         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1823         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1824         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1825                     nes->rx_unknown_protocol);
1826         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1827         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1828         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1829         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1830         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1831         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1832         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1833                     vsi->vsi_id);
1834 }
1835
1836 static void
1837 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1838 {
1839         unsigned int i;
1840         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1841         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1842         /* Get statistics of struct i40e_eth_stats */
1843         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1844                             I40E_GLPRT_GORCL(hw->port),
1845                             pf->offset_loaded, &os->eth.rx_bytes,
1846                             &ns->eth.rx_bytes);
1847         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1848                             I40E_GLPRT_UPRCL(hw->port),
1849                             pf->offset_loaded, &os->eth.rx_unicast,
1850                             &ns->eth.rx_unicast);
1851         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1852                             I40E_GLPRT_MPRCL(hw->port),
1853                             pf->offset_loaded, &os->eth.rx_multicast,
1854                             &ns->eth.rx_multicast);
1855         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1856                             I40E_GLPRT_BPRCL(hw->port),
1857                             pf->offset_loaded, &os->eth.rx_broadcast,
1858                             &ns->eth.rx_broadcast);
1859         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1860                             pf->offset_loaded, &os->eth.rx_discards,
1861                             &ns->eth.rx_discards);
1862         /* GLPRT_REPC not supported */
1863         /* GLPRT_RMPC not supported */
1864         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1865                             pf->offset_loaded,
1866                             &os->eth.rx_unknown_protocol,
1867                             &ns->eth.rx_unknown_protocol);
1868         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1869                             I40E_GLPRT_GOTCL(hw->port),
1870                             pf->offset_loaded, &os->eth.tx_bytes,
1871                             &ns->eth.tx_bytes);
1872         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1873                             I40E_GLPRT_UPTCL(hw->port),
1874                             pf->offset_loaded, &os->eth.tx_unicast,
1875                             &ns->eth.tx_unicast);
1876         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1877                             I40E_GLPRT_MPTCL(hw->port),
1878                             pf->offset_loaded, &os->eth.tx_multicast,
1879                             &ns->eth.tx_multicast);
1880         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1881                             I40E_GLPRT_BPTCL(hw->port),
1882                             pf->offset_loaded, &os->eth.tx_broadcast,
1883                             &ns->eth.tx_broadcast);
1884         /* GLPRT_TEPC not supported */
1885
1886         /* additional port specific stats */
1887         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1888                             pf->offset_loaded, &os->tx_dropped_link_down,
1889                             &ns->tx_dropped_link_down);
1890         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1891                             pf->offset_loaded, &os->crc_errors,
1892                             &ns->crc_errors);
1893         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1894                             pf->offset_loaded, &os->illegal_bytes,
1895                             &ns->illegal_bytes);
1896         /* GLPRT_ERRBC not supported */
1897         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1898                             pf->offset_loaded, &os->mac_local_faults,
1899                             &ns->mac_local_faults);
1900         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1901                             pf->offset_loaded, &os->mac_remote_faults,
1902                             &ns->mac_remote_faults);
1903         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1904                             pf->offset_loaded, &os->rx_length_errors,
1905                             &ns->rx_length_errors);
1906         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1907                             pf->offset_loaded, &os->link_xon_rx,
1908                             &ns->link_xon_rx);
1909         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1910                             pf->offset_loaded, &os->link_xoff_rx,
1911                             &ns->link_xoff_rx);
1912         for (i = 0; i < 8; i++) {
1913                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1914                                     pf->offset_loaded,
1915                                     &os->priority_xon_rx[i],
1916                                     &ns->priority_xon_rx[i]);
1917                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1918                                     pf->offset_loaded,
1919                                     &os->priority_xoff_rx[i],
1920                                     &ns->priority_xoff_rx[i]);
1921         }
1922         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1923                             pf->offset_loaded, &os->link_xon_tx,
1924                             &ns->link_xon_tx);
1925         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1926                             pf->offset_loaded, &os->link_xoff_tx,
1927                             &ns->link_xoff_tx);
1928         for (i = 0; i < 8; i++) {
1929                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1930                                     pf->offset_loaded,
1931                                     &os->priority_xon_tx[i],
1932                                     &ns->priority_xon_tx[i]);
1933                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1934                                     pf->offset_loaded,
1935                                     &os->priority_xoff_tx[i],
1936                                     &ns->priority_xoff_tx[i]);
1937                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1938                                     pf->offset_loaded,
1939                                     &os->priority_xon_2_xoff[i],
1940                                     &ns->priority_xon_2_xoff[i]);
1941         }
1942         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1943                             I40E_GLPRT_PRC64L(hw->port),
1944                             pf->offset_loaded, &os->rx_size_64,
1945                             &ns->rx_size_64);
1946         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1947                             I40E_GLPRT_PRC127L(hw->port),
1948                             pf->offset_loaded, &os->rx_size_127,
1949                             &ns->rx_size_127);
1950         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1951                             I40E_GLPRT_PRC255L(hw->port),
1952                             pf->offset_loaded, &os->rx_size_255,
1953                             &ns->rx_size_255);
1954         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1955                             I40E_GLPRT_PRC511L(hw->port),
1956                             pf->offset_loaded, &os->rx_size_511,
1957                             &ns->rx_size_511);
1958         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1959                             I40E_GLPRT_PRC1023L(hw->port),
1960                             pf->offset_loaded, &os->rx_size_1023,
1961                             &ns->rx_size_1023);
1962         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1963                             I40E_GLPRT_PRC1522L(hw->port),
1964                             pf->offset_loaded, &os->rx_size_1522,
1965                             &ns->rx_size_1522);
1966         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1967                             I40E_GLPRT_PRC9522L(hw->port),
1968                             pf->offset_loaded, &os->rx_size_big,
1969                             &ns->rx_size_big);
1970         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1971                             pf->offset_loaded, &os->rx_undersize,
1972                             &ns->rx_undersize);
1973         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1974                             pf->offset_loaded, &os->rx_fragments,
1975                             &ns->rx_fragments);
1976         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1977                             pf->offset_loaded, &os->rx_oversize,
1978                             &ns->rx_oversize);
1979         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1980                             pf->offset_loaded, &os->rx_jabber,
1981                             &ns->rx_jabber);
1982         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1983                             I40E_GLPRT_PTC64L(hw->port),
1984                             pf->offset_loaded, &os->tx_size_64,
1985                             &ns->tx_size_64);
1986         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1987                             I40E_GLPRT_PTC127L(hw->port),
1988                             pf->offset_loaded, &os->tx_size_127,
1989                             &ns->tx_size_127);
1990         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1991                             I40E_GLPRT_PTC255L(hw->port),
1992                             pf->offset_loaded, &os->tx_size_255,
1993                             &ns->tx_size_255);
1994         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1995                             I40E_GLPRT_PTC511L(hw->port),
1996                             pf->offset_loaded, &os->tx_size_511,
1997                             &ns->tx_size_511);
1998         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1999                             I40E_GLPRT_PTC1023L(hw->port),
2000                             pf->offset_loaded, &os->tx_size_1023,
2001                             &ns->tx_size_1023);
2002         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2003                             I40E_GLPRT_PTC1522L(hw->port),
2004                             pf->offset_loaded, &os->tx_size_1522,
2005                             &ns->tx_size_1522);
2006         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2007                             I40E_GLPRT_PTC9522L(hw->port),
2008                             pf->offset_loaded, &os->tx_size_big,
2009                             &ns->tx_size_big);
2010         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2011                            pf->offset_loaded,
2012                            &os->fd_sb_match, &ns->fd_sb_match);
2013         /* GLPRT_MSPDC not supported */
2014         /* GLPRT_XEC not supported */
2015
2016         pf->offset_loaded = true;
2017
2018         if (pf->main_vsi)
2019                 i40e_update_vsi_stats(pf->main_vsi);
2020 }
2021
2022 /* Get all statistics of a port */
2023 static void
2024 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2025 {
2026         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2027         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2029         unsigned i;
2030
2031         /* call read registers - updates values, now write them to struct */
2032         i40e_read_stats_registers(pf, hw);
2033
2034         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2035                         pf->main_vsi->eth_stats.rx_multicast +
2036                         pf->main_vsi->eth_stats.rx_broadcast -
2037                         pf->main_vsi->eth_stats.rx_discards;
2038         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2039                         pf->main_vsi->eth_stats.tx_multicast +
2040                         pf->main_vsi->eth_stats.tx_broadcast;
2041         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
2042         stats->obytes   = pf->main_vsi->eth_stats.tx_bytes;
2043         stats->oerrors  = ns->eth.tx_errors +
2044                         pf->main_vsi->eth_stats.tx_errors;
2045         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2046         stats->fdirmatch = ns->fd_sb_match;
2047
2048         /* Rx Errors */
2049         stats->ibadcrc  = ns->crc_errors;
2050         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
2051                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2052         stats->imissed  = ns->eth.rx_discards +
2053                         pf->main_vsi->eth_stats.rx_discards;
2054         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
2055
2056         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2057         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2058         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2059         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2060         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2061         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2062         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2063                     ns->eth.rx_unknown_protocol);
2064         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2065         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2066         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2067         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2068         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2069         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2070
2071         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2072                     ns->tx_dropped_link_down);
2073         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2074         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2075                     ns->illegal_bytes);
2076         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2077         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2078                     ns->mac_local_faults);
2079         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2080                     ns->mac_remote_faults);
2081         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2082                     ns->rx_length_errors);
2083         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2084         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2085         for (i = 0; i < 8; i++) {
2086                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2087                                 i, ns->priority_xon_rx[i]);
2088                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2089                                 i, ns->priority_xoff_rx[i]);
2090         }
2091         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2092         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2093         for (i = 0; i < 8; i++) {
2094                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2095                                 i, ns->priority_xon_tx[i]);
2096                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2097                                 i, ns->priority_xoff_tx[i]);
2098                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2099                                 i, ns->priority_xon_2_xoff[i]);
2100         }
2101         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2102         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2103         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2104         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2105         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2106         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2107         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2108         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2109         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2110         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2111         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2112         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2113         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2114         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2115         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2116         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2117         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2118         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2119         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2120                         ns->mac_short_packet_dropped);
2121         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2122                     ns->checksum_error);
2123         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2124         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2125 }
2126
2127 static void
2128 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
2129 {
2130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2133
2134         /* The hw registers are cleared on read */
2135         pf->offset_loaded = false;
2136         i40e_read_stats_registers(pf, hw);
2137
2138         /* reset software counters */
2139         memset(hw_stats, 0, sizeof(*hw_stats));
2140 }
2141
2142 static int
2143 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2144                     unsigned n)
2145 {
2146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         unsigned i, count = 0;
2149         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2150
2151         if (n < I40E_NB_XSTATS)
2152                 return I40E_NB_XSTATS;
2153
2154         i40e_read_stats_registers(pf, hw);
2155
2156         /* Reset */
2157         if (xstats == NULL)
2158                 return 0;
2159
2160         /* Get stats from i40e_eth_stats struct */
2161         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2162                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2163                          "%s", rte_i40e_stats_strings[i].name);
2164                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2165                         rte_i40e_stats_strings[i].offset);
2166                 count++;
2167         }
2168
2169         /* Get individiual stats from i40e_hw_port struct */
2170         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2171                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2172                          "%s", rte_i40e_hw_port_strings[i].name);
2173                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2174                                 rte_i40e_hw_port_strings[i].offset);
2175                 count++;
2176         }
2177
2178         /* Get per-queue stats from i40e_hw_port struct */
2179         for (i = 0; i < 8; i++) {
2180                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2181                          "rx_q%u_xon_priority_packets", i);
2182                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2183                                 offsetof(struct i40e_hw_port_stats,
2184                                          priority_xon_rx[i]));
2185                 count++;
2186
2187                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2188                          "rx_q%u_xoff_priority_packets", i);
2189                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2190                                 offsetof(struct i40e_hw_port_stats,
2191                                          priority_xoff_rx[i]));
2192                 count++;
2193
2194                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2195                          "tx_q%u_xon_priority_packets", i);
2196                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2197                                 offsetof(struct i40e_hw_port_stats,
2198                                          priority_xon_tx[i]));
2199                 count++;
2200
2201                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2202                          "tx_q%u_xoff_priority_packets", i);
2203                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2204                                 offsetof(struct i40e_hw_port_stats,
2205                                          priority_xoff_tx[i]));
2206                 count++;
2207
2208                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2209                          "xx_q%u_xon_to_xoff_priority_packets", i);
2210                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2211                                 offsetof(struct i40e_hw_port_stats,
2212                                          priority_xon_2_xoff[i]));
2213                 count++;
2214         }
2215
2216         return I40E_NB_XSTATS;
2217 }
2218
2219 /* Reset the statistics */
2220 static void
2221 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2222 {
2223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2224
2225         /* It results in reloading the start point of each counter */
2226         pf->offset_loaded = false;
2227 }
2228
2229 static int
2230 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2231                                  __rte_unused uint16_t queue_id,
2232                                  __rte_unused uint8_t stat_idx,
2233                                  __rte_unused uint8_t is_rx)
2234 {
2235         PMD_INIT_FUNC_TRACE();
2236
2237         return -ENOSYS;
2238 }
2239
2240 static void
2241 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2242 {
2243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244         struct i40e_vsi *vsi = pf->main_vsi;
2245
2246         dev_info->max_rx_queues = vsi->nb_qps;
2247         dev_info->max_tx_queues = vsi->nb_qps;
2248         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2249         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2250         dev_info->max_mac_addrs = vsi->max_macaddrs;
2251         dev_info->max_vfs = dev->pci_dev->max_vfs;
2252         dev_info->rx_offload_capa =
2253                 DEV_RX_OFFLOAD_VLAN_STRIP |
2254                 DEV_RX_OFFLOAD_QINQ_STRIP |
2255                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2256                 DEV_RX_OFFLOAD_UDP_CKSUM |
2257                 DEV_RX_OFFLOAD_TCP_CKSUM;
2258         dev_info->tx_offload_capa =
2259                 DEV_TX_OFFLOAD_VLAN_INSERT |
2260                 DEV_TX_OFFLOAD_QINQ_INSERT |
2261                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2262                 DEV_TX_OFFLOAD_UDP_CKSUM |
2263                 DEV_TX_OFFLOAD_TCP_CKSUM |
2264                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2265                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2266                 DEV_TX_OFFLOAD_TCP_TSO;
2267         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2268                                                 sizeof(uint32_t);
2269         dev_info->reta_size = pf->hash_lut_size;
2270         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2271
2272         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2273                 .rx_thresh = {
2274                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2275                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2276                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2277                 },
2278                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2279                 .rx_drop_en = 0,
2280         };
2281
2282         dev_info->default_txconf = (struct rte_eth_txconf) {
2283                 .tx_thresh = {
2284                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2285                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2286                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2287                 },
2288                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2289                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2290                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2291                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2292         };
2293
2294         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2295                 .nb_max = I40E_MAX_RING_DESC,
2296                 .nb_min = I40E_MIN_RING_DESC,
2297                 .nb_align = I40E_ALIGN_RING_DESC,
2298         };
2299
2300         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2301                 .nb_max = I40E_MAX_RING_DESC,
2302                 .nb_min = I40E_MIN_RING_DESC,
2303                 .nb_align = I40E_ALIGN_RING_DESC,
2304         };
2305
2306         if (pf->flags & I40E_FLAG_VMDQ) {
2307                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2308                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2309                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2310                                                 pf->max_nb_vmdq_vsi;
2311                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2312                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2313                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2314         }
2315 }
2316
2317 static int
2318 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2319 {
2320         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2321         struct i40e_vsi *vsi = pf->main_vsi;
2322         PMD_INIT_FUNC_TRACE();
2323
2324         if (on)
2325                 return i40e_vsi_add_vlan(vsi, vlan_id);
2326         else
2327                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2328 }
2329
2330 static void
2331 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2332                    __rte_unused uint16_t tpid)
2333 {
2334         PMD_INIT_FUNC_TRACE();
2335 }
2336
2337 static void
2338 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2339 {
2340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2341         struct i40e_vsi *vsi = pf->main_vsi;
2342
2343         if (mask & ETH_VLAN_STRIP_MASK) {
2344                 /* Enable or disable VLAN stripping */
2345                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2346                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2347                 else
2348                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2349         }
2350
2351         if (mask & ETH_VLAN_EXTEND_MASK) {
2352                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2353                         i40e_vsi_config_double_vlan(vsi, TRUE);
2354                 else
2355                         i40e_vsi_config_double_vlan(vsi, FALSE);
2356         }
2357 }
2358
2359 static void
2360 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2361                           __rte_unused uint16_t queue,
2362                           __rte_unused int on)
2363 {
2364         PMD_INIT_FUNC_TRACE();
2365 }
2366
2367 static int
2368 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2369 {
2370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2371         struct i40e_vsi *vsi = pf->main_vsi;
2372         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2373         struct i40e_vsi_vlan_pvid_info info;
2374
2375         memset(&info, 0, sizeof(info));
2376         info.on = on;
2377         if (info.on)
2378                 info.config.pvid = pvid;
2379         else {
2380                 info.config.reject.tagged =
2381                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2382                 info.config.reject.untagged =
2383                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2384         }
2385
2386         return i40e_vsi_vlan_pvid_set(vsi, &info);
2387 }
2388
2389 static int
2390 i40e_dev_led_on(struct rte_eth_dev *dev)
2391 {
2392         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393         uint32_t mode = i40e_led_get(hw);
2394
2395         if (mode == 0)
2396                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2397
2398         return 0;
2399 }
2400
2401 static int
2402 i40e_dev_led_off(struct rte_eth_dev *dev)
2403 {
2404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         uint32_t mode = i40e_led_get(hw);
2406
2407         if (mode != 0)
2408                 i40e_led_set(hw, 0, false);
2409
2410         return 0;
2411 }
2412
2413 static int
2414 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2415 {
2416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2418
2419         fc_conf->pause_time = pf->fc_conf.pause_time;
2420         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2421         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2422
2423          /* Return current mode according to actual setting*/
2424         switch (hw->fc.current_mode) {
2425         case I40E_FC_FULL:
2426                 fc_conf->mode = RTE_FC_FULL;
2427                 break;
2428         case I40E_FC_TX_PAUSE:
2429                 fc_conf->mode = RTE_FC_TX_PAUSE;
2430                 break;
2431         case I40E_FC_RX_PAUSE:
2432                 fc_conf->mode = RTE_FC_RX_PAUSE;
2433                 break;
2434         case I40E_FC_NONE:
2435         default:
2436                 fc_conf->mode = RTE_FC_NONE;
2437         };
2438
2439         return 0;
2440 }
2441
2442 static int
2443 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2444 {
2445         uint32_t mflcn_reg, fctrl_reg, reg;
2446         uint32_t max_high_water;
2447         uint8_t i, aq_failure;
2448         int err;
2449         struct i40e_hw *hw;
2450         struct i40e_pf *pf;
2451         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2452                 [RTE_FC_NONE] = I40E_FC_NONE,
2453                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2454                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2455                 [RTE_FC_FULL] = I40E_FC_FULL
2456         };
2457
2458         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2459
2460         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2461         if ((fc_conf->high_water > max_high_water) ||
2462                         (fc_conf->high_water < fc_conf->low_water)) {
2463                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2464                         "High_water must <= %d.", max_high_water);
2465                 return -EINVAL;
2466         }
2467
2468         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2471
2472         pf->fc_conf.pause_time = fc_conf->pause_time;
2473         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2474         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2475
2476         PMD_INIT_FUNC_TRACE();
2477
2478         /* All the link flow control related enable/disable register
2479          * configuration is handle by the F/W
2480          */
2481         err = i40e_set_fc(hw, &aq_failure, true);
2482         if (err < 0)
2483                 return -ENOSYS;
2484
2485         if (i40e_is_40G_device(hw->device_id)) {
2486                 /* Configure flow control refresh threshold,
2487                  * the value for stat_tx_pause_refresh_timer[8]
2488                  * is used for global pause operation.
2489                  */
2490
2491                 I40E_WRITE_REG(hw,
2492                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2493                                pf->fc_conf.pause_time);
2494
2495                 /* configure the timer value included in transmitted pause
2496                  * frame,
2497                  * the value for stat_tx_pause_quanta[8] is used for global
2498                  * pause operation
2499                  */
2500                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2501                                pf->fc_conf.pause_time);
2502
2503                 fctrl_reg = I40E_READ_REG(hw,
2504                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2505
2506                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2507                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2508                 else
2509                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2510
2511                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2512                                fctrl_reg);
2513         } else {
2514                 /* Configure pause time (2 TCs per register) */
2515                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2516                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2517                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2518
2519                 /* Configure flow control refresh threshold value */
2520                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2521                                pf->fc_conf.pause_time / 2);
2522
2523                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2524
2525                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2526                  *depending on configuration
2527                  */
2528                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2529                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2530                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2531                 } else {
2532                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2533                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2534                 }
2535
2536                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2537         }
2538
2539         /* config the water marker both based on the packets and bytes */
2540         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2541                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2542                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2543         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2544                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2545                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2546         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2547                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2548                        << I40E_KILOSHIFT);
2549         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2550                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2551                        << I40E_KILOSHIFT);
2552
2553         I40E_WRITE_FLUSH(hw);
2554
2555         return 0;
2556 }
2557
2558 static int
2559 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2560                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2561 {
2562         PMD_INIT_FUNC_TRACE();
2563
2564         return -ENOSYS;
2565 }
2566
2567 /* Add a MAC address, and update filters */
2568 static void
2569 i40e_macaddr_add(struct rte_eth_dev *dev,
2570                  struct ether_addr *mac_addr,
2571                  __rte_unused uint32_t index,
2572                  uint32_t pool)
2573 {
2574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575         struct i40e_mac_filter_info mac_filter;
2576         struct i40e_vsi *vsi;
2577         int ret;
2578
2579         /* If VMDQ not enabled or configured, return */
2580         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2581                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2582                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2583                         pool);
2584                 return;
2585         }
2586
2587         if (pool > pf->nb_cfg_vmdq_vsi) {
2588                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2589                                 pool, pf->nb_cfg_vmdq_vsi);
2590                 return;
2591         }
2592
2593         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2594         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2595
2596         if (pool == 0)
2597                 vsi = pf->main_vsi;
2598         else
2599                 vsi = pf->vmdq[pool - 1].vsi;
2600
2601         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2602         if (ret != I40E_SUCCESS) {
2603                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2604                 return;
2605         }
2606 }
2607
2608 /* Remove a MAC address, and update filters */
2609 static void
2610 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2611 {
2612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2613         struct i40e_vsi *vsi;
2614         struct rte_eth_dev_data *data = dev->data;
2615         struct ether_addr *macaddr;
2616         int ret;
2617         uint32_t i;
2618         uint64_t pool_sel;
2619
2620         macaddr = &(data->mac_addrs[index]);
2621
2622         pool_sel = dev->data->mac_pool_sel[index];
2623
2624         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2625                 if (pool_sel & (1ULL << i)) {
2626                         if (i == 0)
2627                                 vsi = pf->main_vsi;
2628                         else {
2629                                 /* No VMDQ pool enabled or configured */
2630                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2631                                         (i > pf->nb_cfg_vmdq_vsi)) {
2632                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2633                                                         "/configured");
2634                                         return;
2635                                 }
2636                                 vsi = pf->vmdq[i - 1].vsi;
2637                         }
2638                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2639
2640                         if (ret) {
2641                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2642                                 return;
2643                         }
2644                 }
2645         }
2646 }
2647
2648 /* Set perfect match or hash match of MAC and VLAN for a VF */
2649 static int
2650 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2651                  struct rte_eth_mac_filter *filter,
2652                  bool add)
2653 {
2654         struct i40e_hw *hw;
2655         struct i40e_mac_filter_info mac_filter;
2656         struct ether_addr old_mac;
2657         struct ether_addr *new_mac;
2658         struct i40e_pf_vf *vf = NULL;
2659         uint16_t vf_id;
2660         int ret;
2661
2662         if (pf == NULL) {
2663                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2664                 return -EINVAL;
2665         }
2666         hw = I40E_PF_TO_HW(pf);
2667
2668         if (filter == NULL) {
2669                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2670                 return -EINVAL;
2671         }
2672
2673         new_mac = &filter->mac_addr;
2674
2675         if (is_zero_ether_addr(new_mac)) {
2676                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2677                 return -EINVAL;
2678         }
2679
2680         vf_id = filter->dst_id;
2681
2682         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2683                 PMD_DRV_LOG(ERR, "Invalid argument.");
2684                 return -EINVAL;
2685         }
2686         vf = &pf->vfs[vf_id];
2687
2688         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2689                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2690                 return -EINVAL;
2691         }
2692
2693         if (add) {
2694                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2695                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2696                                 ETHER_ADDR_LEN);
2697                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2698                                  ETHER_ADDR_LEN);
2699
2700                 mac_filter.filter_type = filter->filter_type;
2701                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2702                 if (ret != I40E_SUCCESS) {
2703                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2704                         return -1;
2705                 }
2706                 ether_addr_copy(new_mac, &pf->dev_addr);
2707         } else {
2708                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2709                                 ETHER_ADDR_LEN);
2710                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2711                 if (ret != I40E_SUCCESS) {
2712                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2713                         return -1;
2714                 }
2715
2716                 /* Clear device address as it has been removed */
2717                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2718                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2719         }
2720
2721         return 0;
2722 }
2723
2724 /* MAC filter handle */
2725 static int
2726 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2727                 void *arg)
2728 {
2729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2730         struct rte_eth_mac_filter *filter;
2731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2732         int ret = I40E_NOT_SUPPORTED;
2733
2734         filter = (struct rte_eth_mac_filter *)(arg);
2735
2736         switch (filter_op) {
2737         case RTE_ETH_FILTER_NOP:
2738                 ret = I40E_SUCCESS;
2739                 break;
2740         case RTE_ETH_FILTER_ADD:
2741                 i40e_pf_disable_irq0(hw);
2742                 if (filter->is_vf)
2743                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2744                 i40e_pf_enable_irq0(hw);
2745                 break;
2746         case RTE_ETH_FILTER_DELETE:
2747                 i40e_pf_disable_irq0(hw);
2748                 if (filter->is_vf)
2749                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2750                 i40e_pf_enable_irq0(hw);
2751                 break;
2752         default:
2753                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2754                 ret = I40E_ERR_PARAM;
2755                 break;
2756         }
2757
2758         return ret;
2759 }
2760
2761 static int
2762 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2763 {
2764         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2765         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2766         int ret;
2767
2768         if (!lut)
2769                 return -EINVAL;
2770
2771         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2772                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2773                                           lut, lut_size);
2774                 if (ret) {
2775                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2776                         return ret;
2777                 }
2778         } else {
2779                 uint32_t *lut_dw = (uint32_t *)lut;
2780                 uint16_t i, lut_size_dw = lut_size / 4;
2781
2782                 for (i = 0; i < lut_size_dw; i++)
2783                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2784         }
2785
2786         return 0;
2787 }
2788
2789 static int
2790 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2791 {
2792         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2793         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2794         int ret;
2795
2796         if (!vsi || !lut)
2797                 return -EINVAL;
2798
2799         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2800                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2801                                           lut, lut_size);
2802                 if (ret) {
2803                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2804                         return ret;
2805                 }
2806         } else {
2807                 uint32_t *lut_dw = (uint32_t *)lut;
2808                 uint16_t i, lut_size_dw = lut_size / 4;
2809
2810                 for (i = 0; i < lut_size_dw; i++)
2811                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2812                 I40E_WRITE_FLUSH(hw);
2813         }
2814
2815         return 0;
2816 }
2817
2818 static int
2819 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2820                          struct rte_eth_rss_reta_entry64 *reta_conf,
2821                          uint16_t reta_size)
2822 {
2823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2824         uint16_t i, lut_size = pf->hash_lut_size;
2825         uint16_t idx, shift;
2826         uint8_t *lut;
2827         int ret;
2828
2829         if (reta_size != lut_size ||
2830                 reta_size > ETH_RSS_RETA_SIZE_512) {
2831                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2832                         "(%d) doesn't match the number hardware can supported "
2833                                         "(%d)\n", reta_size, lut_size);
2834                 return -EINVAL;
2835         }
2836
2837         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2838         if (!lut) {
2839                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2840                 return -ENOMEM;
2841         }
2842         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2843         if (ret)
2844                 goto out;
2845         for (i = 0; i < reta_size; i++) {
2846                 idx = i / RTE_RETA_GROUP_SIZE;
2847                 shift = i % RTE_RETA_GROUP_SIZE;
2848                 if (reta_conf[idx].mask & (1ULL << shift))
2849                         lut[i] = reta_conf[idx].reta[shift];
2850         }
2851         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2852
2853 out:
2854         rte_free(lut);
2855
2856         return ret;
2857 }
2858
2859 static int
2860 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2861                         struct rte_eth_rss_reta_entry64 *reta_conf,
2862                         uint16_t reta_size)
2863 {
2864         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2865         uint16_t i, lut_size = pf->hash_lut_size;
2866         uint16_t idx, shift;
2867         uint8_t *lut;
2868         int ret;
2869
2870         if (reta_size != lut_size ||
2871                 reta_size > ETH_RSS_RETA_SIZE_512) {
2872                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2873                         "(%d) doesn't match the number hardware can supported "
2874                                         "(%d)\n", reta_size, lut_size);
2875                 return -EINVAL;
2876         }
2877
2878         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2879         if (!lut) {
2880                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2881                 return -ENOMEM;
2882         }
2883
2884         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2885         if (ret)
2886                 goto out;
2887         for (i = 0; i < reta_size; i++) {
2888                 idx = i / RTE_RETA_GROUP_SIZE;
2889                 shift = i % RTE_RETA_GROUP_SIZE;
2890                 if (reta_conf[idx].mask & (1ULL << shift))
2891                         reta_conf[idx].reta[shift] = lut[i];
2892         }
2893
2894 out:
2895         rte_free(lut);
2896
2897         return ret;
2898 }
2899
2900 /**
2901  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2902  * @hw:   pointer to the HW structure
2903  * @mem:  pointer to mem struct to fill out
2904  * @size: size of memory requested
2905  * @alignment: what to align the allocation to
2906  **/
2907 enum i40e_status_code
2908 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2909                         struct i40e_dma_mem *mem,
2910                         u64 size,
2911                         u32 alignment)
2912 {
2913         const struct rte_memzone *mz = NULL;
2914         char z_name[RTE_MEMZONE_NAMESIZE];
2915
2916         if (!mem)
2917                 return I40E_ERR_PARAM;
2918
2919         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2920 #ifdef RTE_LIBRTE_XEN_DOM0
2921         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2922                                          alignment, RTE_PGSIZE_2M);
2923 #else
2924         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2925                                          alignment);
2926 #endif
2927         if (!mz)
2928                 return I40E_ERR_NO_MEMORY;
2929
2930         mem->size = size;
2931         mem->va = mz->addr;
2932 #ifdef RTE_LIBRTE_XEN_DOM0
2933         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2934 #else
2935         mem->pa = mz->phys_addr;
2936 #endif
2937         mem->zone = (const void *)mz;
2938         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2939                     "%"PRIu64, mz->name, mem->pa);
2940
2941         return I40E_SUCCESS;
2942 }
2943
2944 /**
2945  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2946  * @hw:   pointer to the HW structure
2947  * @mem:  ptr to mem struct to free
2948  **/
2949 enum i40e_status_code
2950 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2951                     struct i40e_dma_mem *mem)
2952 {
2953         if (!mem)
2954                 return I40E_ERR_PARAM;
2955
2956         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2957                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2958                     mem->pa);
2959         rte_memzone_free((const struct rte_memzone *)mem->zone);
2960         mem->zone = NULL;
2961         mem->va = NULL;
2962         mem->pa = (u64)0;
2963
2964         return I40E_SUCCESS;
2965 }
2966
2967 /**
2968  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2969  * @hw:   pointer to the HW structure
2970  * @mem:  pointer to mem struct to fill out
2971  * @size: size of memory requested
2972  **/
2973 enum i40e_status_code
2974 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2975                          struct i40e_virt_mem *mem,
2976                          u32 size)
2977 {
2978         if (!mem)
2979                 return I40E_ERR_PARAM;
2980
2981         mem->size = size;
2982         mem->va = rte_zmalloc("i40e", size, 0);
2983
2984         if (mem->va)
2985                 return I40E_SUCCESS;
2986         else
2987                 return I40E_ERR_NO_MEMORY;
2988 }
2989
2990 /**
2991  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2992  * @hw:   pointer to the HW structure
2993  * @mem:  pointer to mem struct to free
2994  **/
2995 enum i40e_status_code
2996 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2997                      struct i40e_virt_mem *mem)
2998 {
2999         if (!mem)
3000                 return I40E_ERR_PARAM;
3001
3002         rte_free(mem->va);
3003         mem->va = NULL;
3004
3005         return I40E_SUCCESS;
3006 }
3007
3008 void
3009 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3010 {
3011         rte_spinlock_init(&sp->spinlock);
3012 }
3013
3014 void
3015 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3016 {
3017         rte_spinlock_lock(&sp->spinlock);
3018 }
3019
3020 void
3021 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3022 {
3023         rte_spinlock_unlock(&sp->spinlock);
3024 }
3025
3026 void
3027 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3028 {
3029         return;
3030 }
3031
3032 /**
3033  * Get the hardware capabilities, which will be parsed
3034  * and saved into struct i40e_hw.
3035  */
3036 static int
3037 i40e_get_cap(struct i40e_hw *hw)
3038 {
3039         struct i40e_aqc_list_capabilities_element_resp *buf;
3040         uint16_t len, size = 0;
3041         int ret;
3042
3043         /* Calculate a huge enough buff for saving response data temporarily */
3044         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3045                                                 I40E_MAX_CAP_ELE_NUM;
3046         buf = rte_zmalloc("i40e", len, 0);
3047         if (!buf) {
3048                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3049                 return I40E_ERR_NO_MEMORY;
3050         }
3051
3052         /* Get, parse the capabilities and save it to hw */
3053         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3054                         i40e_aqc_opc_list_func_capabilities, NULL);
3055         if (ret != I40E_SUCCESS)
3056                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3057
3058         /* Free the temporary buffer after being used */
3059         rte_free(buf);
3060
3061         return ret;
3062 }
3063
3064 static int
3065 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3066 {
3067         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3068         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3069         uint16_t qp_count = 0, vsi_count = 0;
3070
3071         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3072                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3073                 return -EINVAL;
3074         }
3075         /* Add the parameter init for LFC */
3076         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3077         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3078         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3079
3080         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3081         pf->max_num_vsi = hw->func_caps.num_vsis;
3082         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3083         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3084         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3085
3086         /* FDir queue/VSI allocation */
3087         pf->fdir_qp_offset = 0;
3088         if (hw->func_caps.fd) {
3089                 pf->flags |= I40E_FLAG_FDIR;
3090                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3091         } else {
3092                 pf->fdir_nb_qps = 0;
3093         }
3094         qp_count += pf->fdir_nb_qps;
3095         vsi_count += 1;
3096
3097         /* LAN queue/VSI allocation */
3098         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3099         if (!hw->func_caps.rss) {
3100                 pf->lan_nb_qps = 1;
3101         } else {
3102                 pf->flags |= I40E_FLAG_RSS;
3103                 if (hw->mac.type == I40E_MAC_X722)
3104                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3105                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3106         }
3107         qp_count += pf->lan_nb_qps;
3108         vsi_count += 1;
3109
3110         /* VF queue/VSI allocation */
3111         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3112         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3113                 pf->flags |= I40E_FLAG_SRIOV;
3114                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3115                 pf->vf_num = dev->pci_dev->max_vfs;
3116                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3117                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3118                             pf->vf_nb_qps * pf->vf_num);
3119         } else {
3120                 pf->vf_nb_qps = 0;
3121                 pf->vf_num = 0;
3122         }
3123         qp_count += pf->vf_nb_qps * pf->vf_num;
3124         vsi_count += pf->vf_num;
3125
3126         /* VMDq queue/VSI allocation */
3127         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3128         pf->vmdq_nb_qps = 0;
3129         pf->max_nb_vmdq_vsi = 0;
3130         if (hw->func_caps.vmdq) {
3131                 if (qp_count < hw->func_caps.num_tx_qp) {
3132                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3133                                 qp_count) / pf->vmdq_nb_qp_max;
3134
3135                         /* Limit the maximum number of VMDq vsi to the maximum
3136                          * ethdev can support
3137                          */
3138                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3139                                 ETH_64_POOLS);
3140                         if (pf->max_nb_vmdq_vsi) {
3141                                 pf->flags |= I40E_FLAG_VMDQ;
3142                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3143                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3144                                             "per VMDQ VSI, in total %u queues",
3145                                             pf->max_nb_vmdq_vsi,
3146                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3147                                             pf->max_nb_vmdq_vsi);
3148                         } else {
3149                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3150                                             "VMDq");
3151                         }
3152                 } else {
3153                         PMD_DRV_LOG(INFO, "No queue left for VMDq");
3154                 }
3155         }
3156         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3157         vsi_count += pf->max_nb_vmdq_vsi;
3158
3159         if (hw->func_caps.dcb)
3160                 pf->flags |= I40E_FLAG_DCB;
3161
3162         if (qp_count > hw->func_caps.num_tx_qp) {
3163                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3164                             "the hardware maximum %u", qp_count,
3165                             hw->func_caps.num_tx_qp);
3166                 return -EINVAL;
3167         }
3168         if (vsi_count > hw->func_caps.num_vsis) {
3169                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3170                             "the hardware maximum %u", vsi_count,
3171                             hw->func_caps.num_vsis);
3172                 return -EINVAL;
3173         }
3174
3175         return 0;
3176 }
3177
3178 static int
3179 i40e_pf_get_switch_config(struct i40e_pf *pf)
3180 {
3181         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3182         struct i40e_aqc_get_switch_config_resp *switch_config;
3183         struct i40e_aqc_switch_config_element_resp *element;
3184         uint16_t start_seid = 0, num_reported;
3185         int ret;
3186
3187         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3188                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3189         if (!switch_config) {
3190                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3191                 return -ENOMEM;
3192         }
3193
3194         /* Get the switch configurations */
3195         ret = i40e_aq_get_switch_config(hw, switch_config,
3196                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3197         if (ret != I40E_SUCCESS) {
3198                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3199                 goto fail;
3200         }
3201         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3202         if (num_reported != 1) { /* The number should be 1 */
3203                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3204                 goto fail;
3205         }
3206
3207         /* Parse the switch configuration elements */
3208         element = &(switch_config->element[0]);
3209         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3210                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3211                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3212         } else
3213                 PMD_DRV_LOG(INFO, "Unknown element type");
3214
3215 fail:
3216         rte_free(switch_config);
3217
3218         return ret;
3219 }
3220
3221 static int
3222 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3223                         uint32_t num)
3224 {
3225         struct pool_entry *entry;
3226
3227         if (pool == NULL || num == 0)
3228                 return -EINVAL;
3229
3230         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3231         if (entry == NULL) {
3232                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3233                 return -ENOMEM;
3234         }
3235
3236         /* queue heap initialize */
3237         pool->num_free = num;
3238         pool->num_alloc = 0;
3239         pool->base = base;
3240         LIST_INIT(&pool->alloc_list);
3241         LIST_INIT(&pool->free_list);
3242
3243         /* Initialize element  */
3244         entry->base = 0;
3245         entry->len = num;
3246
3247         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3248         return 0;
3249 }
3250
3251 static void
3252 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3253 {
3254         struct pool_entry *entry;
3255
3256         if (pool == NULL)
3257                 return;
3258
3259         LIST_FOREACH(entry, &pool->alloc_list, next) {
3260                 LIST_REMOVE(entry, next);
3261                 rte_free(entry);
3262         }
3263
3264         LIST_FOREACH(entry, &pool->free_list, next) {
3265                 LIST_REMOVE(entry, next);
3266                 rte_free(entry);
3267         }
3268
3269         pool->num_free = 0;
3270         pool->num_alloc = 0;
3271         pool->base = 0;
3272         LIST_INIT(&pool->alloc_list);
3273         LIST_INIT(&pool->free_list);
3274 }
3275
3276 static int
3277 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3278                        uint32_t base)
3279 {
3280         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3281         uint32_t pool_offset;
3282         int insert;
3283
3284         if (pool == NULL) {
3285                 PMD_DRV_LOG(ERR, "Invalid parameter");
3286                 return -EINVAL;
3287         }
3288
3289         pool_offset = base - pool->base;
3290         /* Lookup in alloc list */
3291         LIST_FOREACH(entry, &pool->alloc_list, next) {
3292                 if (entry->base == pool_offset) {
3293                         valid_entry = entry;
3294                         LIST_REMOVE(entry, next);
3295                         break;
3296                 }
3297         }
3298
3299         /* Not find, return */
3300         if (valid_entry == NULL) {
3301                 PMD_DRV_LOG(ERR, "Failed to find entry");
3302                 return -EINVAL;
3303         }
3304
3305         /**
3306          * Found it, move it to free list  and try to merge.
3307          * In order to make merge easier, always sort it by qbase.
3308          * Find adjacent prev and last entries.
3309          */
3310         prev = next = NULL;
3311         LIST_FOREACH(entry, &pool->free_list, next) {
3312                 if (entry->base > valid_entry->base) {
3313                         next = entry;
3314                         break;
3315                 }
3316                 prev = entry;
3317         }
3318
3319         insert = 0;
3320         /* Try to merge with next one*/
3321         if (next != NULL) {
3322                 /* Merge with next one */
3323                 if (valid_entry->base + valid_entry->len == next->base) {
3324                         next->base = valid_entry->base;
3325                         next->len += valid_entry->len;
3326                         rte_free(valid_entry);
3327                         valid_entry = next;
3328                         insert = 1;
3329                 }
3330         }
3331
3332         if (prev != NULL) {
3333                 /* Merge with previous one */
3334                 if (prev->base + prev->len == valid_entry->base) {
3335                         prev->len += valid_entry->len;
3336                         /* If it merge with next one, remove next node */
3337                         if (insert == 1) {
3338                                 LIST_REMOVE(valid_entry, next);
3339                                 rte_free(valid_entry);
3340                         } else {
3341                                 rte_free(valid_entry);
3342                                 insert = 1;
3343                         }
3344                 }
3345         }
3346
3347         /* Not find any entry to merge, insert */
3348         if (insert == 0) {
3349                 if (prev != NULL)
3350                         LIST_INSERT_AFTER(prev, valid_entry, next);
3351                 else if (next != NULL)
3352                         LIST_INSERT_BEFORE(next, valid_entry, next);
3353                 else /* It's empty list, insert to head */
3354                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3355         }
3356
3357         pool->num_free += valid_entry->len;
3358         pool->num_alloc -= valid_entry->len;
3359
3360         return 0;
3361 }
3362
3363 static int
3364 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3365                        uint16_t num)
3366 {
3367         struct pool_entry *entry, *valid_entry;
3368
3369         if (pool == NULL || num == 0) {
3370                 PMD_DRV_LOG(ERR, "Invalid parameter");
3371                 return -EINVAL;
3372         }
3373
3374         if (pool->num_free < num) {
3375                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3376                             num, pool->num_free);
3377                 return -ENOMEM;
3378         }
3379
3380         valid_entry = NULL;
3381         /* Lookup  in free list and find most fit one */
3382         LIST_FOREACH(entry, &pool->free_list, next) {
3383                 if (entry->len >= num) {
3384                         /* Find best one */
3385                         if (entry->len == num) {
3386                                 valid_entry = entry;
3387                                 break;
3388                         }
3389                         if (valid_entry == NULL || valid_entry->len > entry->len)
3390                                 valid_entry = entry;
3391                 }
3392         }
3393
3394         /* Not find one to satisfy the request, return */
3395         if (valid_entry == NULL) {
3396                 PMD_DRV_LOG(ERR, "No valid entry found");
3397                 return -ENOMEM;
3398         }
3399         /**
3400          * The entry have equal queue number as requested,
3401          * remove it from alloc_list.
3402          */
3403         if (valid_entry->len == num) {
3404                 LIST_REMOVE(valid_entry, next);
3405         } else {
3406                 /**
3407                  * The entry have more numbers than requested,
3408                  * create a new entry for alloc_list and minus its
3409                  * queue base and number in free_list.
3410                  */
3411                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3412                 if (entry == NULL) {
3413                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3414                                     "resource pool");
3415                         return -ENOMEM;
3416                 }
3417                 entry->base = valid_entry->base;
3418                 entry->len = num;
3419                 valid_entry->base += num;
3420                 valid_entry->len -= num;
3421                 valid_entry = entry;
3422         }
3423
3424         /* Insert it into alloc list, not sorted */
3425         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3426
3427         pool->num_free -= valid_entry->len;
3428         pool->num_alloc += valid_entry->len;
3429
3430         return (valid_entry->base + pool->base);
3431 }
3432
3433 /**
3434  * bitmap_is_subset - Check whether src2 is subset of src1
3435  **/
3436 static inline int
3437 bitmap_is_subset(uint8_t src1, uint8_t src2)
3438 {
3439         return !((src1 ^ src2) & src2);
3440 }
3441
3442 static enum i40e_status_code
3443 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3444 {
3445         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3446
3447         /* If DCB is not supported, only default TC is supported */
3448         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3449                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3450                 return I40E_NOT_SUPPORTED;
3451         }
3452
3453         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3454                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3455                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3456                             enabled_tcmap);
3457                 return I40E_NOT_SUPPORTED;
3458         }
3459         return I40E_SUCCESS;
3460 }
3461
3462 int
3463 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3464                                 struct i40e_vsi_vlan_pvid_info *info)
3465 {
3466         struct i40e_hw *hw;
3467         struct i40e_vsi_context ctxt;
3468         uint8_t vlan_flags = 0;
3469         int ret;
3470
3471         if (vsi == NULL || info == NULL) {
3472                 PMD_DRV_LOG(ERR, "invalid parameters");
3473                 return I40E_ERR_PARAM;
3474         }
3475
3476         if (info->on) {
3477                 vsi->info.pvid = info->config.pvid;
3478                 /**
3479                  * If insert pvid is enabled, only tagged pkts are
3480                  * allowed to be sent out.
3481                  */
3482                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3483                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3484         } else {
3485                 vsi->info.pvid = 0;
3486                 if (info->config.reject.tagged == 0)
3487                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3488
3489                 if (info->config.reject.untagged == 0)
3490                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3491         }
3492         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3493                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3494         vsi->info.port_vlan_flags |= vlan_flags;
3495         vsi->info.valid_sections =
3496                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3497         memset(&ctxt, 0, sizeof(ctxt));
3498         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3499         ctxt.seid = vsi->seid;
3500
3501         hw = I40E_VSI_TO_HW(vsi);
3502         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3503         if (ret != I40E_SUCCESS)
3504                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3505
3506         return ret;
3507 }
3508
3509 static int
3510 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3511 {
3512         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3513         int i, ret;
3514         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3515
3516         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3517         if (ret != I40E_SUCCESS)
3518                 return ret;
3519
3520         if (!vsi->seid) {
3521                 PMD_DRV_LOG(ERR, "seid not valid");
3522                 return -EINVAL;
3523         }
3524
3525         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3526         tc_bw_data.tc_valid_bits = enabled_tcmap;
3527         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3528                 tc_bw_data.tc_bw_credits[i] =
3529                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3530
3531         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3532         if (ret != I40E_SUCCESS) {
3533                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3534                 return ret;
3535         }
3536
3537         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3538                                         sizeof(vsi->info.qs_handle));
3539         return I40E_SUCCESS;
3540 }
3541
3542 static enum i40e_status_code
3543 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3544                                  struct i40e_aqc_vsi_properties_data *info,
3545                                  uint8_t enabled_tcmap)
3546 {
3547         enum i40e_status_code ret;
3548         int i, total_tc = 0;
3549         uint16_t qpnum_per_tc, bsf, qp_idx;
3550
3551         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3552         if (ret != I40E_SUCCESS)
3553                 return ret;
3554
3555         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3556                 if (enabled_tcmap & (1 << i))
3557                         total_tc++;
3558         vsi->enabled_tc = enabled_tcmap;
3559
3560         /* Number of queues per enabled TC */
3561         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3562         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3563         bsf = rte_bsf32(qpnum_per_tc);
3564
3565         /* Adjust the queue number to actual queues that can be applied */
3566         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3567                 vsi->nb_qps = qpnum_per_tc * total_tc;
3568
3569         /**
3570          * Configure TC and queue mapping parameters, for enabled TC,
3571          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3572          * default queue will serve it.
3573          */
3574         qp_idx = 0;
3575         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3576                 if (vsi->enabled_tc & (1 << i)) {
3577                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3578                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3579                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3580                         qp_idx += qpnum_per_tc;
3581                 } else
3582                         info->tc_mapping[i] = 0;
3583         }
3584
3585         /* Associate queue number with VSI */
3586         if (vsi->type == I40E_VSI_SRIOV) {
3587                 info->mapping_flags |=
3588                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3589                 for (i = 0; i < vsi->nb_qps; i++)
3590                         info->queue_mapping[i] =
3591                                 rte_cpu_to_le_16(vsi->base_queue + i);
3592         } else {
3593                 info->mapping_flags |=
3594                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3595                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3596         }
3597         info->valid_sections |=
3598                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3599
3600         return I40E_SUCCESS;
3601 }
3602
3603 static int
3604 i40e_veb_release(struct i40e_veb *veb)
3605 {
3606         struct i40e_vsi *vsi;
3607         struct i40e_hw *hw;
3608
3609         if (veb == NULL || veb->associate_vsi == NULL)
3610                 return -EINVAL;
3611
3612         if (!TAILQ_EMPTY(&veb->head)) {
3613                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3614                 return -EACCES;
3615         }
3616
3617         vsi = veb->associate_vsi;
3618         hw = I40E_VSI_TO_HW(vsi);
3619
3620         vsi->uplink_seid = veb->uplink_seid;
3621         i40e_aq_delete_element(hw, veb->seid, NULL);
3622         rte_free(veb);
3623         vsi->veb = NULL;
3624         return I40E_SUCCESS;
3625 }
3626
3627 /* Setup a veb */
3628 static struct i40e_veb *
3629 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3630 {
3631         struct i40e_veb *veb;
3632         int ret;
3633         struct i40e_hw *hw;
3634
3635         if (NULL == pf || vsi == NULL) {
3636                 PMD_DRV_LOG(ERR, "veb setup failed, "
3637                             "associated VSI shouldn't null");
3638                 return NULL;
3639         }
3640         hw = I40E_PF_TO_HW(pf);
3641
3642         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3643         if (!veb) {
3644                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3645                 goto fail;
3646         }
3647
3648         veb->associate_vsi = vsi;
3649         TAILQ_INIT(&veb->head);
3650         veb->uplink_seid = vsi->uplink_seid;
3651
3652         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3653                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3654
3655         if (ret != I40E_SUCCESS) {
3656                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3657                             hw->aq.asq_last_status);
3658                 goto fail;
3659         }
3660
3661         /* get statistics index */
3662         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3663                                 &veb->stats_idx, NULL, NULL, NULL);
3664         if (ret != I40E_SUCCESS) {
3665                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3666                             hw->aq.asq_last_status);
3667                 goto fail;
3668         }
3669
3670         /* Get VEB bandwidth, to be implemented */
3671         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3672         vsi->uplink_seid = veb->seid;
3673
3674         return veb;
3675 fail:
3676         rte_free(veb);
3677         return NULL;
3678 }
3679
3680 int
3681 i40e_vsi_release(struct i40e_vsi *vsi)
3682 {
3683         struct i40e_pf *pf;
3684         struct i40e_hw *hw;
3685         struct i40e_vsi_list *vsi_list;
3686         int ret;
3687         struct i40e_mac_filter *f;
3688
3689         if (!vsi)
3690                 return I40E_SUCCESS;
3691
3692         pf = I40E_VSI_TO_PF(vsi);
3693         hw = I40E_VSI_TO_HW(vsi);
3694
3695         /* VSI has child to attach, release child first */
3696         if (vsi->veb) {
3697                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3698                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3699                                 return -1;
3700                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3701                 }
3702                 i40e_veb_release(vsi->veb);
3703         }
3704
3705         /* Remove all macvlan filters of the VSI */
3706         i40e_vsi_remove_all_macvlan_filter(vsi);
3707         TAILQ_FOREACH(f, &vsi->mac_list, next)
3708                 rte_free(f);
3709
3710         if (vsi->type != I40E_VSI_MAIN) {
3711                 /* Remove vsi from parent's sibling list */
3712                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3713                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3714                         return I40E_ERR_PARAM;
3715                 }
3716                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3717                                 &vsi->sib_vsi_list, list);
3718
3719                 /* Remove all switch element of the VSI */
3720                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3721                 if (ret != I40E_SUCCESS)
3722                         PMD_DRV_LOG(ERR, "Failed to delete element");
3723         }
3724         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3725
3726         if (vsi->type != I40E_VSI_SRIOV)
3727                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3728         rte_free(vsi);
3729
3730         return I40E_SUCCESS;
3731 }
3732
3733 static int
3734 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3735 {
3736         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3737         struct i40e_aqc_remove_macvlan_element_data def_filter;
3738         struct i40e_mac_filter_info filter;
3739         int ret;
3740
3741         if (vsi->type != I40E_VSI_MAIN)
3742                 return I40E_ERR_CONFIG;
3743         memset(&def_filter, 0, sizeof(def_filter));
3744         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3745                                         ETH_ADDR_LEN);
3746         def_filter.vlan_tag = 0;
3747         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3748                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3749         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3750         if (ret != I40E_SUCCESS) {
3751                 struct i40e_mac_filter *f;
3752                 struct ether_addr *mac;
3753
3754                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3755                             "macvlan filter");
3756                 /* It needs to add the permanent mac into mac list */
3757                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3758                 if (f == NULL) {
3759                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3760                         return I40E_ERR_NO_MEMORY;
3761                 }
3762                 mac = &f->mac_info.mac_addr;
3763                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3764                                 ETH_ADDR_LEN);
3765                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3766                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3767                 vsi->mac_num++;
3768
3769                 return ret;
3770         }
3771         (void)rte_memcpy(&filter.mac_addr,
3772                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3773         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3774         return i40e_vsi_add_mac(vsi, &filter);
3775 }
3776
3777 static int
3778 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3779 {
3780         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3781         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3782         struct i40e_hw *hw = &vsi->adapter->hw;
3783         i40e_status ret;
3784         int i;
3785
3786         memset(&bw_config, 0, sizeof(bw_config));
3787         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3788         if (ret != I40E_SUCCESS) {
3789                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3790                             hw->aq.asq_last_status);
3791                 return ret;
3792         }
3793
3794         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3795         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3796                                         &ets_sla_config, NULL);
3797         if (ret != I40E_SUCCESS) {
3798                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3799                             "configuration %u", hw->aq.asq_last_status);
3800                 return ret;
3801         }
3802
3803         /* Not store the info yet, just print out */
3804         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3805         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3806         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3807                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3808                             ets_sla_config.share_credits[i]);
3809                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3810                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3811                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3812                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3813                             (i * 4));
3814         }
3815
3816         return 0;
3817 }
3818
3819 /* Setup a VSI */
3820 struct i40e_vsi *
3821 i40e_vsi_setup(struct i40e_pf *pf,
3822                enum i40e_vsi_type type,
3823                struct i40e_vsi *uplink_vsi,
3824                uint16_t user_param)
3825 {
3826         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3827         struct i40e_vsi *vsi;
3828         struct i40e_mac_filter_info filter;
3829         int ret;
3830         struct i40e_vsi_context ctxt;
3831         struct ether_addr broadcast =
3832                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3833
3834         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3835                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3836                             "VSI link shouldn't be NULL");
3837                 return NULL;
3838         }
3839
3840         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3841                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3842                             "uplink VSI should be NULL");
3843                 return NULL;
3844         }
3845
3846         /* If uplink vsi didn't setup VEB, create one first */
3847         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3848                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3849
3850                 if (NULL == uplink_vsi->veb) {
3851                         PMD_DRV_LOG(ERR, "VEB setup failed");
3852                         return NULL;
3853                 }
3854         }
3855
3856         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3857         if (!vsi) {
3858                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3859                 return NULL;
3860         }
3861         TAILQ_INIT(&vsi->mac_list);
3862         vsi->type = type;
3863         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3864         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3865         vsi->parent_vsi = uplink_vsi;
3866         vsi->user_param = user_param;
3867         /* Allocate queues */
3868         switch (vsi->type) {
3869         case I40E_VSI_MAIN  :
3870                 vsi->nb_qps = pf->lan_nb_qps;
3871                 break;
3872         case I40E_VSI_SRIOV :
3873                 vsi->nb_qps = pf->vf_nb_qps;
3874                 break;
3875         case I40E_VSI_VMDQ2:
3876                 vsi->nb_qps = pf->vmdq_nb_qps;
3877                 break;
3878         case I40E_VSI_FDIR:
3879                 vsi->nb_qps = pf->fdir_nb_qps;
3880                 break;
3881         default:
3882                 goto fail_mem;
3883         }
3884         /*
3885          * The filter status descriptor is reported in rx queue 0,
3886          * while the tx queue for fdir filter programming has no
3887          * such constraints, can be non-zero queues.
3888          * To simplify it, choose FDIR vsi use queue 0 pair.
3889          * To make sure it will use queue 0 pair, queue allocation
3890          * need be done before this function is called
3891          */
3892         if (type != I40E_VSI_FDIR) {
3893                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3894                         if (ret < 0) {
3895                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3896                                                 vsi->seid, ret);
3897                                 goto fail_mem;
3898                         }
3899                         vsi->base_queue = ret;
3900         } else
3901                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3902
3903         /* VF has MSIX interrupt in VF range, don't allocate here */
3904         if (type == I40E_VSI_MAIN) {
3905                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3906                                           RTE_MIN(vsi->nb_qps,
3907                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3908                 if (ret < 0) {
3909                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3910                                     vsi->seid, ret);
3911                         goto fail_queue_alloc;
3912                 }
3913                 vsi->msix_intr = ret;
3914                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3915         } else if (type != I40E_VSI_SRIOV) {
3916                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3917                 if (ret < 0) {
3918                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3919                         goto fail_queue_alloc;
3920                 }
3921                 vsi->msix_intr = ret;
3922                 vsi->nb_msix = 1;
3923         } else {
3924                 vsi->msix_intr = 0;
3925                 vsi->nb_msix = 0;
3926         }
3927
3928         /* Add VSI */
3929         if (type == I40E_VSI_MAIN) {
3930                 /* For main VSI, no need to add since it's default one */
3931                 vsi->uplink_seid = pf->mac_seid;
3932                 vsi->seid = pf->main_vsi_seid;
3933                 /* Bind queues with specific MSIX interrupt */
3934                 /**
3935                  * Needs 2 interrupt at least, one for misc cause which will
3936                  * enabled from OS side, Another for queues binding the
3937                  * interrupt from device side only.
3938                  */
3939
3940                 /* Get default VSI parameters from hardware */
3941                 memset(&ctxt, 0, sizeof(ctxt));
3942                 ctxt.seid = vsi->seid;
3943                 ctxt.pf_num = hw->pf_id;
3944                 ctxt.uplink_seid = vsi->uplink_seid;
3945                 ctxt.vf_num = 0;
3946                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3947                 if (ret != I40E_SUCCESS) {
3948                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3949                         goto fail_msix_alloc;
3950                 }
3951                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3952                         sizeof(struct i40e_aqc_vsi_properties_data));
3953                 vsi->vsi_id = ctxt.vsi_number;
3954                 vsi->info.valid_sections = 0;
3955
3956                 /* Configure tc, enabled TC0 only */
3957                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3958                         I40E_SUCCESS) {
3959                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3960                         goto fail_msix_alloc;
3961                 }
3962
3963                 /* TC, queue mapping */
3964                 memset(&ctxt, 0, sizeof(ctxt));
3965                 vsi->info.valid_sections |=
3966                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3967                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3968                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3969                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3970                         sizeof(struct i40e_aqc_vsi_properties_data));
3971                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3972                                                 I40E_DEFAULT_TCMAP);
3973                 if (ret != I40E_SUCCESS) {
3974                         PMD_DRV_LOG(ERR, "Failed to configure "
3975                                     "TC queue mapping");
3976                         goto fail_msix_alloc;
3977                 }
3978                 ctxt.seid = vsi->seid;
3979                 ctxt.pf_num = hw->pf_id;
3980                 ctxt.uplink_seid = vsi->uplink_seid;
3981                 ctxt.vf_num = 0;
3982
3983                 /* Update VSI parameters */
3984                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3985                 if (ret != I40E_SUCCESS) {
3986                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3987                         goto fail_msix_alloc;
3988                 }
3989
3990                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3991                                                 sizeof(vsi->info.tc_mapping));
3992                 (void)rte_memcpy(&vsi->info.queue_mapping,
3993                                 &ctxt.info.queue_mapping,
3994                         sizeof(vsi->info.queue_mapping));
3995                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3996                 vsi->info.valid_sections = 0;
3997
3998                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3999                                 ETH_ADDR_LEN);
4000
4001                 /**
4002                  * Updating default filter settings are necessary to prevent
4003                  * reception of tagged packets.
4004                  * Some old firmware configurations load a default macvlan
4005                  * filter which accepts both tagged and untagged packets.
4006                  * The updating is to use a normal filter instead if needed.
4007                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4008                  * The firmware with correct configurations load the default
4009                  * macvlan filter which is expected and cannot be removed.
4010                  */
4011                 i40e_update_default_filter_setting(vsi);
4012                 i40e_config_qinq(hw, vsi);
4013         } else if (type == I40E_VSI_SRIOV) {
4014                 memset(&ctxt, 0, sizeof(ctxt));
4015                 /**
4016                  * For other VSI, the uplink_seid equals to uplink VSI's
4017                  * uplink_seid since they share same VEB
4018                  */
4019                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4020                 ctxt.pf_num = hw->pf_id;
4021                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4022                 ctxt.uplink_seid = vsi->uplink_seid;
4023                 ctxt.connection_type = 0x1;
4024                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4025
4026                 /**
4027                  * Do not configure switch ID to enable VEB switch by
4028                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4029                  * if the source mac address of packet sent from VF is not
4030                  * listed in the VEB's mac table, the VEB will switch the
4031                  * packet back to the VF. Need to enable it when HW issue
4032                  * is fixed.
4033                  */
4034
4035                 /* Configure port/vlan */
4036                 ctxt.info.valid_sections |=
4037                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4038                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4039                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4040                                                 I40E_DEFAULT_TCMAP);
4041                 if (ret != I40E_SUCCESS) {
4042                         PMD_DRV_LOG(ERR, "Failed to configure "
4043                                     "TC queue mapping");
4044                         goto fail_msix_alloc;
4045                 }
4046                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4047                 ctxt.info.valid_sections |=
4048                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4049                 /**
4050                  * Since VSI is not created yet, only configure parameter,
4051                  * will add vsi below.
4052                  */
4053
4054                 i40e_config_qinq(hw, vsi);
4055         } else if (type == I40E_VSI_VMDQ2) {
4056                 memset(&ctxt, 0, sizeof(ctxt));
4057                 /*
4058                  * For other VSI, the uplink_seid equals to uplink VSI's
4059                  * uplink_seid since they share same VEB
4060                  */
4061                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4062                 ctxt.pf_num = hw->pf_id;
4063                 ctxt.vf_num = 0;
4064                 ctxt.uplink_seid = vsi->uplink_seid;
4065                 ctxt.connection_type = 0x1;
4066                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4067
4068                 ctxt.info.valid_sections |=
4069                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4070                 /* user_param carries flag to enable loop back */
4071                 if (user_param) {
4072                         ctxt.info.switch_id =
4073                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4074                         ctxt.info.switch_id |=
4075                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4076                 }
4077
4078                 /* Configure port/vlan */
4079                 ctxt.info.valid_sections |=
4080                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4081                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4082                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4083                                                 I40E_DEFAULT_TCMAP);
4084                 if (ret != I40E_SUCCESS) {
4085                         PMD_DRV_LOG(ERR, "Failed to configure "
4086                                         "TC queue mapping");
4087                         goto fail_msix_alloc;
4088                 }
4089                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4090                 ctxt.info.valid_sections |=
4091                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4092         } else if (type == I40E_VSI_FDIR) {
4093                 memset(&ctxt, 0, sizeof(ctxt));
4094                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4095                 ctxt.pf_num = hw->pf_id;
4096                 ctxt.vf_num = 0;
4097                 ctxt.uplink_seid = vsi->uplink_seid;
4098                 ctxt.connection_type = 0x1;     /* regular data port */
4099                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4100                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4101                                                 I40E_DEFAULT_TCMAP);
4102                 if (ret != I40E_SUCCESS) {
4103                         PMD_DRV_LOG(ERR, "Failed to configure "
4104                                         "TC queue mapping.");
4105                         goto fail_msix_alloc;
4106                 }
4107                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4108                 ctxt.info.valid_sections |=
4109                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4110         } else {
4111                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4112                 goto fail_msix_alloc;
4113         }
4114
4115         if (vsi->type != I40E_VSI_MAIN) {
4116                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4117                 if (ret != I40E_SUCCESS) {
4118                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4119                                     hw->aq.asq_last_status);
4120                         goto fail_msix_alloc;
4121                 }
4122                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4123                 vsi->info.valid_sections = 0;
4124                 vsi->seid = ctxt.seid;
4125                 vsi->vsi_id = ctxt.vsi_number;
4126                 vsi->sib_vsi_list.vsi = vsi;
4127                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4128                                 &vsi->sib_vsi_list, list);
4129         }
4130
4131         /* MAC/VLAN configuration */
4132         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4133         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4134
4135         ret = i40e_vsi_add_mac(vsi, &filter);
4136         if (ret != I40E_SUCCESS) {
4137                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4138                 goto fail_msix_alloc;
4139         }
4140
4141         /* Get VSI BW information */
4142         i40e_vsi_dump_bw_config(vsi);
4143         return vsi;
4144 fail_msix_alloc:
4145         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4146 fail_queue_alloc:
4147         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4148 fail_mem:
4149         rte_free(vsi);
4150         return NULL;
4151 }
4152
4153 /* Configure vlan stripping on or off */
4154 int
4155 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4156 {
4157         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4158         struct i40e_vsi_context ctxt;
4159         uint8_t vlan_flags;
4160         int ret = I40E_SUCCESS;
4161
4162         /* Check if it has been already on or off */
4163         if (vsi->info.valid_sections &
4164                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4165                 if (on) {
4166                         if ((vsi->info.port_vlan_flags &
4167                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4168                                 return 0; /* already on */
4169                 } else {
4170                         if ((vsi->info.port_vlan_flags &
4171                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4172                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4173                                 return 0; /* already off */
4174                 }
4175         }
4176
4177         if (on)
4178                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4179         else
4180                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4181         vsi->info.valid_sections =
4182                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4183         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4184         vsi->info.port_vlan_flags |= vlan_flags;
4185         ctxt.seid = vsi->seid;
4186         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4187         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4188         if (ret)
4189                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4190                             on ? "enable" : "disable");
4191
4192         return ret;
4193 }
4194
4195 static int
4196 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4197 {
4198         struct rte_eth_dev_data *data = dev->data;
4199         int ret;
4200
4201         /* Apply vlan offload setting */
4202         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4203
4204         /* Apply double-vlan setting, not implemented yet */
4205
4206         /* Apply pvid setting */
4207         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4208                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4209         if (ret)
4210                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4211
4212         return ret;
4213 }
4214
4215 static int
4216 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4217 {
4218         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4219
4220         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4221 }
4222
4223 static int
4224 i40e_update_flow_control(struct i40e_hw *hw)
4225 {
4226 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4227         struct i40e_link_status link_status;
4228         uint32_t rxfc = 0, txfc = 0, reg;
4229         uint8_t an_info;
4230         int ret;
4231
4232         memset(&link_status, 0, sizeof(link_status));
4233         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4234         if (ret != I40E_SUCCESS) {
4235                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4236                 goto write_reg; /* Disable flow control */
4237         }
4238
4239         an_info = hw->phy.link_info.an_info;
4240         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4241                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4242                 ret = I40E_ERR_NOT_READY;
4243                 goto write_reg; /* Disable flow control */
4244         }
4245         /**
4246          * If link auto negotiation is enabled, flow control needs to
4247          * be configured according to it
4248          */
4249         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4250         case I40E_LINK_PAUSE_RXTX:
4251                 rxfc = 1;
4252                 txfc = 1;
4253                 hw->fc.current_mode = I40E_FC_FULL;
4254                 break;
4255         case I40E_AQ_LINK_PAUSE_RX:
4256                 rxfc = 1;
4257                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4258                 break;
4259         case I40E_AQ_LINK_PAUSE_TX:
4260                 txfc = 1;
4261                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4262                 break;
4263         default:
4264                 hw->fc.current_mode = I40E_FC_NONE;
4265                 break;
4266         }
4267
4268 write_reg:
4269         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4270                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4271         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4272         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4273         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4274         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4275
4276         return ret;
4277 }
4278
4279 /* PF setup */
4280 static int
4281 i40e_pf_setup(struct i40e_pf *pf)
4282 {
4283         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4284         struct i40e_filter_control_settings settings;
4285         struct i40e_vsi *vsi;
4286         int ret;
4287
4288         /* Clear all stats counters */
4289         pf->offset_loaded = FALSE;
4290         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4291         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4292
4293         ret = i40e_pf_get_switch_config(pf);
4294         if (ret != I40E_SUCCESS) {
4295                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4296                 return ret;
4297         }
4298         if (pf->flags & I40E_FLAG_FDIR) {
4299                 /* make queue allocated first, let FDIR use queue pair 0*/
4300                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4301                 if (ret != I40E_FDIR_QUEUE_ID) {
4302                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4303                                     " ret =%d", ret);
4304                         pf->flags &= ~I40E_FLAG_FDIR;
4305                 }
4306         }
4307         /*  main VSI setup */
4308         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4309         if (!vsi) {
4310                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4311                 return I40E_ERR_NOT_READY;
4312         }
4313         pf->main_vsi = vsi;
4314
4315         /* Configure filter control */
4316         memset(&settings, 0, sizeof(settings));
4317         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4318                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4319         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4320                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4321         else {
4322                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4323                                                 hw->func_caps.rss_table_size);
4324                 return I40E_ERR_PARAM;
4325         }
4326         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4327                         "size: %u\n", hw->func_caps.rss_table_size);
4328         pf->hash_lut_size = hw->func_caps.rss_table_size;
4329
4330         /* Enable ethtype and macvlan filters */
4331         settings.enable_ethtype = TRUE;
4332         settings.enable_macvlan = TRUE;
4333         ret = i40e_set_filter_control(hw, &settings);
4334         if (ret)
4335                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4336                                                                 ret);
4337
4338         /* Update flow control according to the auto negotiation */
4339         i40e_update_flow_control(hw);
4340
4341         return I40E_SUCCESS;
4342 }
4343
4344 int
4345 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4346 {
4347         uint32_t reg;
4348         uint16_t j;
4349
4350         /**
4351          * Set or clear TX Queue Disable flags,
4352          * which is required by hardware.
4353          */
4354         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4355         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4356
4357         /* Wait until the request is finished */
4358         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4359                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4360                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4361                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4362                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4363                                                         & 0x1))) {
4364                         break;
4365                 }
4366         }
4367         if (on) {
4368                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4369                         return I40E_SUCCESS; /* already on, skip next steps */
4370
4371                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4372                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4373         } else {
4374                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4375                         return I40E_SUCCESS; /* already off, skip next steps */
4376                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4377         }
4378         /* Write the register */
4379         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4380         /* Check the result */
4381         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4382                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4383                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4384                 if (on) {
4385                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4386                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4387                                 break;
4388                 } else {
4389                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4390                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4391                                 break;
4392                 }
4393         }
4394         /* Check if it is timeout */
4395         if (j >= I40E_CHK_Q_ENA_COUNT) {
4396                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4397                             (on ? "enable" : "disable"), q_idx);
4398                 return I40E_ERR_TIMEOUT;
4399         }
4400
4401         return I40E_SUCCESS;
4402 }
4403
4404 /* Swith on or off the tx queues */
4405 static int
4406 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4407 {
4408         struct rte_eth_dev_data *dev_data = pf->dev_data;
4409         struct i40e_tx_queue *txq;
4410         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4411         uint16_t i;
4412         int ret;
4413
4414         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4415                 txq = dev_data->tx_queues[i];
4416                 /* Don't operate the queue if not configured or
4417                  * if starting only per queue */
4418                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4419                         continue;
4420                 if (on)
4421                         ret = i40e_dev_tx_queue_start(dev, i);
4422                 else
4423                         ret = i40e_dev_tx_queue_stop(dev, i);
4424                 if ( ret != I40E_SUCCESS)
4425                         return ret;
4426         }
4427
4428         return I40E_SUCCESS;
4429 }
4430
4431 int
4432 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4433 {
4434         uint32_t reg;
4435         uint16_t j;
4436
4437         /* Wait until the request is finished */
4438         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4439                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4440                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4441                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4442                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4443                         break;
4444         }
4445
4446         if (on) {
4447                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4448                         return I40E_SUCCESS; /* Already on, skip next steps */
4449                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4450         } else {
4451                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4452                         return I40E_SUCCESS; /* Already off, skip next steps */
4453                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4454         }
4455
4456         /* Write the register */
4457         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4458         /* Check the result */
4459         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4460                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4461                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4462                 if (on) {
4463                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4464                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4465                                 break;
4466                 } else {
4467                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4468                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4469                                 break;
4470                 }
4471         }
4472
4473         /* Check if it is timeout */
4474         if (j >= I40E_CHK_Q_ENA_COUNT) {
4475                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4476                             (on ? "enable" : "disable"), q_idx);
4477                 return I40E_ERR_TIMEOUT;
4478         }
4479
4480         return I40E_SUCCESS;
4481 }
4482 /* Switch on or off the rx queues */
4483 static int
4484 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4485 {
4486         struct rte_eth_dev_data *dev_data = pf->dev_data;
4487         struct i40e_rx_queue *rxq;
4488         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4489         uint16_t i;
4490         int ret;
4491
4492         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4493                 rxq = dev_data->rx_queues[i];
4494                 /* Don't operate the queue if not configured or
4495                  * if starting only per queue */
4496                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4497                         continue;
4498                 if (on)
4499                         ret = i40e_dev_rx_queue_start(dev, i);
4500                 else
4501                         ret = i40e_dev_rx_queue_stop(dev, i);
4502                 if (ret != I40E_SUCCESS)
4503                         return ret;
4504         }
4505
4506         return I40E_SUCCESS;
4507 }
4508
4509 /* Switch on or off all the rx/tx queues */
4510 int
4511 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4512 {
4513         int ret;
4514
4515         if (on) {
4516                 /* enable rx queues before enabling tx queues */
4517                 ret = i40e_dev_switch_rx_queues(pf, on);
4518                 if (ret) {
4519                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4520                         return ret;
4521                 }
4522                 ret = i40e_dev_switch_tx_queues(pf, on);
4523         } else {
4524                 /* Stop tx queues before stopping rx queues */
4525                 ret = i40e_dev_switch_tx_queues(pf, on);
4526                 if (ret) {
4527                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4528                         return ret;
4529                 }
4530                 ret = i40e_dev_switch_rx_queues(pf, on);
4531         }
4532
4533         return ret;
4534 }
4535
4536 /* Initialize VSI for TX */
4537 static int
4538 i40e_dev_tx_init(struct i40e_pf *pf)
4539 {
4540         struct rte_eth_dev_data *data = pf->dev_data;
4541         uint16_t i;
4542         uint32_t ret = I40E_SUCCESS;
4543         struct i40e_tx_queue *txq;
4544
4545         for (i = 0; i < data->nb_tx_queues; i++) {
4546                 txq = data->tx_queues[i];
4547                 if (!txq || !txq->q_set)
4548                         continue;
4549                 ret = i40e_tx_queue_init(txq);
4550                 if (ret != I40E_SUCCESS)
4551                         break;
4552         }
4553         if (ret == I40E_SUCCESS)
4554                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4555                                      ->eth_dev);
4556
4557         return ret;
4558 }
4559
4560 /* Initialize VSI for RX */
4561 static int
4562 i40e_dev_rx_init(struct i40e_pf *pf)
4563 {
4564         struct rte_eth_dev_data *data = pf->dev_data;
4565         int ret = I40E_SUCCESS;
4566         uint16_t i;
4567         struct i40e_rx_queue *rxq;
4568
4569         i40e_pf_config_mq_rx(pf);
4570         for (i = 0; i < data->nb_rx_queues; i++) {
4571                 rxq = data->rx_queues[i];
4572                 if (!rxq || !rxq->q_set)
4573                         continue;
4574
4575                 ret = i40e_rx_queue_init(rxq);
4576                 if (ret != I40E_SUCCESS) {
4577                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4578                                     "initialization");
4579                         break;
4580                 }
4581         }
4582         if (ret == I40E_SUCCESS)
4583                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4584                                      ->eth_dev);
4585
4586         return ret;
4587 }
4588
4589 static int
4590 i40e_dev_rxtx_init(struct i40e_pf *pf)
4591 {
4592         int err;
4593
4594         err = i40e_dev_tx_init(pf);
4595         if (err) {
4596                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4597                 return err;
4598         }
4599         err = i40e_dev_rx_init(pf);
4600         if (err) {
4601                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4602                 return err;
4603         }
4604
4605         return err;
4606 }
4607
4608 static int
4609 i40e_vmdq_setup(struct rte_eth_dev *dev)
4610 {
4611         struct rte_eth_conf *conf = &dev->data->dev_conf;
4612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4613         int i, err, conf_vsis, j, loop;
4614         struct i40e_vsi *vsi;
4615         struct i40e_vmdq_info *vmdq_info;
4616         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4617         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4618
4619         /*
4620          * Disable interrupt to avoid message from VF. Furthermore, it will
4621          * avoid race condition in VSI creation/destroy.
4622          */
4623         i40e_pf_disable_irq0(hw);
4624
4625         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4626                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4627                 return -ENOTSUP;
4628         }
4629
4630         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4631         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4632                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4633                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4634                         pf->max_nb_vmdq_vsi);
4635                 return -ENOTSUP;
4636         }
4637
4638         if (pf->vmdq != NULL) {
4639                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4640                 return 0;
4641         }
4642
4643         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4644                                 sizeof(*vmdq_info) * conf_vsis, 0);
4645
4646         if (pf->vmdq == NULL) {
4647                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4648                 return -ENOMEM;
4649         }
4650
4651         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4652
4653         /* Create VMDQ VSI */
4654         for (i = 0; i < conf_vsis; i++) {
4655                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4656                                 vmdq_conf->enable_loop_back);
4657                 if (vsi == NULL) {
4658                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4659                         err = -1;
4660                         goto err_vsi_setup;
4661                 }
4662                 vmdq_info = &pf->vmdq[i];
4663                 vmdq_info->pf = pf;
4664                 vmdq_info->vsi = vsi;
4665         }
4666         pf->nb_cfg_vmdq_vsi = conf_vsis;
4667
4668         /* Configure Vlan */
4669         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4670         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4671                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4672                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4673                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4674                                         vmdq_conf->pool_map[i].vlan_id, j);
4675
4676                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4677                                                 vmdq_conf->pool_map[i].vlan_id);
4678                                 if (err) {
4679                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4680                                         err = -1;
4681                                         goto err_vsi_setup;
4682                                 }
4683                         }
4684                 }
4685         }
4686
4687         i40e_pf_enable_irq0(hw);
4688
4689         return 0;
4690
4691 err_vsi_setup:
4692         for (i = 0; i < conf_vsis; i++)
4693                 if (pf->vmdq[i].vsi == NULL)
4694                         break;
4695                 else
4696                         i40e_vsi_release(pf->vmdq[i].vsi);
4697
4698         rte_free(pf->vmdq);
4699         pf->vmdq = NULL;
4700         i40e_pf_enable_irq0(hw);
4701         return err;
4702 }
4703
4704 static void
4705 i40e_stat_update_32(struct i40e_hw *hw,
4706                    uint32_t reg,
4707                    bool offset_loaded,
4708                    uint64_t *offset,
4709                    uint64_t *stat)
4710 {
4711         uint64_t new_data;
4712
4713         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4714         if (!offset_loaded)
4715                 *offset = new_data;
4716
4717         if (new_data >= *offset)
4718                 *stat = (uint64_t)(new_data - *offset);
4719         else
4720                 *stat = (uint64_t)((new_data +
4721                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4722 }
4723
4724 static void
4725 i40e_stat_update_48(struct i40e_hw *hw,
4726                    uint32_t hireg,
4727                    uint32_t loreg,
4728                    bool offset_loaded,
4729                    uint64_t *offset,
4730                    uint64_t *stat)
4731 {
4732         uint64_t new_data;
4733
4734         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4735         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4736                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4737
4738         if (!offset_loaded)
4739                 *offset = new_data;
4740
4741         if (new_data >= *offset)
4742                 *stat = new_data - *offset;
4743         else
4744                 *stat = (uint64_t)((new_data +
4745                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4746
4747         *stat &= I40E_48_BIT_MASK;
4748 }
4749
4750 /* Disable IRQ0 */
4751 void
4752 i40e_pf_disable_irq0(struct i40e_hw *hw)
4753 {
4754         /* Disable all interrupt types */
4755         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4756         I40E_WRITE_FLUSH(hw);
4757 }
4758
4759 /* Enable IRQ0 */
4760 void
4761 i40e_pf_enable_irq0(struct i40e_hw *hw)
4762 {
4763         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4764                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4765                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4766                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4767         I40E_WRITE_FLUSH(hw);
4768 }
4769
4770 static void
4771 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4772 {
4773         /* read pending request and disable first */
4774         i40e_pf_disable_irq0(hw);
4775         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4776         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4777                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4778
4779         if (no_queue)
4780                 /* Link no queues with irq0 */
4781                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4782                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4783 }
4784
4785 static void
4786 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4787 {
4788         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4790         int i;
4791         uint16_t abs_vf_id;
4792         uint32_t index, offset, val;
4793
4794         if (!pf->vfs)
4795                 return;
4796         /**
4797          * Try to find which VF trigger a reset, use absolute VF id to access
4798          * since the reg is global register.
4799          */
4800         for (i = 0; i < pf->vf_num; i++) {
4801                 abs_vf_id = hw->func_caps.vf_base_id + i;
4802                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4803                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4804                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4805                 /* VFR event occured */
4806                 if (val & (0x1 << offset)) {
4807                         int ret;
4808
4809                         /* Clear the event first */
4810                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4811                                                         (0x1 << offset));
4812                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4813                         /**
4814                          * Only notify a VF reset event occured,
4815                          * don't trigger another SW reset
4816                          */
4817                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4818                         if (ret != I40E_SUCCESS)
4819                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4820                 }
4821         }
4822 }
4823
4824 static void
4825 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4826 {
4827         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828         struct i40e_arq_event_info info;
4829         uint16_t pending, opcode;
4830         int ret;
4831
4832         info.buf_len = I40E_AQ_BUF_SZ;
4833         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4834         if (!info.msg_buf) {
4835                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4836                 return;
4837         }
4838
4839         pending = 1;
4840         while (pending) {
4841                 ret = i40e_clean_arq_element(hw, &info, &pending);
4842
4843                 if (ret != I40E_SUCCESS) {
4844                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4845                                     "aq_err: %u", hw->aq.asq_last_status);
4846                         break;
4847                 }
4848                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4849
4850                 switch (opcode) {
4851                 case i40e_aqc_opc_send_msg_to_pf:
4852                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4853                         i40e_pf_host_handle_vf_msg(dev,
4854                                         rte_le_to_cpu_16(info.desc.retval),
4855                                         rte_le_to_cpu_32(info.desc.cookie_high),
4856                                         rte_le_to_cpu_32(info.desc.cookie_low),
4857                                         info.msg_buf,
4858                                         info.msg_len);
4859                         break;
4860                 default:
4861                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4862                                     opcode);
4863                         break;
4864                 }
4865         }
4866         rte_free(info.msg_buf);
4867 }
4868
4869 /*
4870  * Interrupt handler is registered as the alarm callback for handling LSC
4871  * interrupt in a definite of time, in order to wait the NIC into a stable
4872  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4873  * no need for link down interrupt.
4874  */
4875 static void
4876 i40e_dev_interrupt_delayed_handler(void *param)
4877 {
4878         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4879         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4880         uint32_t icr0;
4881
4882         /* read interrupt causes again */
4883         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4884
4885 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4886         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4887                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4888         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4889                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4890         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4891                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4892         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4893                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4894         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4895                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4896                                                                 "state\n");
4897         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4898                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4899         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4900                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4901 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4902
4903         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4904                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4905                 i40e_dev_handle_vfr_event(dev);
4906         }
4907         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4908                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4909                 i40e_dev_handle_aq_msg(dev);
4910         }
4911
4912         /* handle the link up interrupt in an alarm callback */
4913         i40e_dev_link_update(dev, 0);
4914         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4915
4916         i40e_pf_enable_irq0(hw);
4917         rte_intr_enable(&(dev->pci_dev->intr_handle));
4918 }
4919
4920 /**
4921  * Interrupt handler triggered by NIC  for handling
4922  * specific interrupt.
4923  *
4924  * @param handle
4925  *  Pointer to interrupt handle.
4926  * @param param
4927  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4928  *
4929  * @return
4930  *  void
4931  */
4932 static void
4933 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4934                            void *param)
4935 {
4936         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4938         uint32_t icr0;
4939
4940         /* Disable interrupt */
4941         i40e_pf_disable_irq0(hw);
4942
4943         /* read out interrupt causes */
4944         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4945
4946         /* No interrupt event indicated */
4947         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4948                 PMD_DRV_LOG(INFO, "No interrupt event");
4949                 goto done;
4950         }
4951 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4952         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4953                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4954         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4955                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4956         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4957                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4958         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4959                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4960         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4961                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4962         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4963                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4964         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4965                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4966 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4967
4968         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4969                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4970                 i40e_dev_handle_vfr_event(dev);
4971         }
4972         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4973                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4974                 i40e_dev_handle_aq_msg(dev);
4975         }
4976
4977         /* Link Status Change interrupt */
4978         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4979 #define I40E_US_PER_SECOND 1000000
4980                 struct rte_eth_link link;
4981
4982                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4983                 memset(&link, 0, sizeof(link));
4984                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4985                 i40e_dev_link_update(dev, 0);
4986
4987                 /*
4988                  * For link up interrupt, it needs to wait 1 second to let the
4989                  * hardware be a stable state. Otherwise several consecutive
4990                  * interrupts can be observed.
4991                  * For link down interrupt, no need to wait.
4992                  */
4993                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4994                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4995                         return;
4996                 else
4997                         _rte_eth_dev_callback_process(dev,
4998                                 RTE_ETH_EVENT_INTR_LSC);
4999         }
5000
5001 done:
5002         /* Enable interrupt */
5003         i40e_pf_enable_irq0(hw);
5004         rte_intr_enable(&(dev->pci_dev->intr_handle));
5005 }
5006
5007 static int
5008 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5009                          struct i40e_macvlan_filter *filter,
5010                          int total)
5011 {
5012         int ele_num, ele_buff_size;
5013         int num, actual_num, i;
5014         uint16_t flags;
5015         int ret = I40E_SUCCESS;
5016         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5017         struct i40e_aqc_add_macvlan_element_data *req_list;
5018
5019         if (filter == NULL  || total == 0)
5020                 return I40E_ERR_PARAM;
5021         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5022         ele_buff_size = hw->aq.asq_buf_size;
5023
5024         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5025         if (req_list == NULL) {
5026                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5027                 return I40E_ERR_NO_MEMORY;
5028         }
5029
5030         num = 0;
5031         do {
5032                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5033                 memset(req_list, 0, ele_buff_size);
5034
5035                 for (i = 0; i < actual_num; i++) {
5036                         (void)rte_memcpy(req_list[i].mac_addr,
5037                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5038                         req_list[i].vlan_tag =
5039                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5040
5041                         switch (filter[num + i].filter_type) {
5042                         case RTE_MAC_PERFECT_MATCH:
5043                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5044                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5045                                 break;
5046                         case RTE_MACVLAN_PERFECT_MATCH:
5047                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5048                                 break;
5049                         case RTE_MAC_HASH_MATCH:
5050                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5051                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5052                                 break;
5053                         case RTE_MACVLAN_HASH_MATCH:
5054                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5055                                 break;
5056                         default:
5057                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5058                                 ret = I40E_ERR_PARAM;
5059                                 goto DONE;
5060                         }
5061
5062                         req_list[i].queue_number = 0;
5063
5064                         req_list[i].flags = rte_cpu_to_le_16(flags);
5065                 }
5066
5067                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5068                                                 actual_num, NULL);
5069                 if (ret != I40E_SUCCESS) {
5070                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5071                         goto DONE;
5072                 }
5073                 num += actual_num;
5074         } while (num < total);
5075
5076 DONE:
5077         rte_free(req_list);
5078         return ret;
5079 }
5080
5081 static int
5082 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5083                             struct i40e_macvlan_filter *filter,
5084                             int total)
5085 {
5086         int ele_num, ele_buff_size;
5087         int num, actual_num, i;
5088         uint16_t flags;
5089         int ret = I40E_SUCCESS;
5090         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5091         struct i40e_aqc_remove_macvlan_element_data *req_list;
5092
5093         if (filter == NULL  || total == 0)
5094                 return I40E_ERR_PARAM;
5095
5096         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5097         ele_buff_size = hw->aq.asq_buf_size;
5098
5099         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5100         if (req_list == NULL) {
5101                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5102                 return I40E_ERR_NO_MEMORY;
5103         }
5104
5105         num = 0;
5106         do {
5107                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5108                 memset(req_list, 0, ele_buff_size);
5109
5110                 for (i = 0; i < actual_num; i++) {
5111                         (void)rte_memcpy(req_list[i].mac_addr,
5112                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5113                         req_list[i].vlan_tag =
5114                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5115
5116                         switch (filter[num + i].filter_type) {
5117                         case RTE_MAC_PERFECT_MATCH:
5118                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5119                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5120                                 break;
5121                         case RTE_MACVLAN_PERFECT_MATCH:
5122                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5123                                 break;
5124                         case RTE_MAC_HASH_MATCH:
5125                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5126                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5127                                 break;
5128                         case RTE_MACVLAN_HASH_MATCH:
5129                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5130                                 break;
5131                         default:
5132                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5133                                 ret = I40E_ERR_PARAM;
5134                                 goto DONE;
5135                         }
5136                         req_list[i].flags = rte_cpu_to_le_16(flags);
5137                 }
5138
5139                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5140                                                 actual_num, NULL);
5141                 if (ret != I40E_SUCCESS) {
5142                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5143                         goto DONE;
5144                 }
5145                 num += actual_num;
5146         } while (num < total);
5147
5148 DONE:
5149         rte_free(req_list);
5150         return ret;
5151 }
5152
5153 /* Find out specific MAC filter */
5154 static struct i40e_mac_filter *
5155 i40e_find_mac_filter(struct i40e_vsi *vsi,
5156                          struct ether_addr *macaddr)
5157 {
5158         struct i40e_mac_filter *f;
5159
5160         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5161                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5162                         return f;
5163         }
5164
5165         return NULL;
5166 }
5167
5168 static bool
5169 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5170                          uint16_t vlan_id)
5171 {
5172         uint32_t vid_idx, vid_bit;
5173
5174         if (vlan_id > ETH_VLAN_ID_MAX)
5175                 return 0;
5176
5177         vid_idx = I40E_VFTA_IDX(vlan_id);
5178         vid_bit = I40E_VFTA_BIT(vlan_id);
5179
5180         if (vsi->vfta[vid_idx] & vid_bit)
5181                 return 1;
5182         else
5183                 return 0;
5184 }
5185
5186 static void
5187 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5188                          uint16_t vlan_id, bool on)
5189 {
5190         uint32_t vid_idx, vid_bit;
5191
5192         if (vlan_id > ETH_VLAN_ID_MAX)
5193                 return;
5194
5195         vid_idx = I40E_VFTA_IDX(vlan_id);
5196         vid_bit = I40E_VFTA_BIT(vlan_id);
5197
5198         if (on)
5199                 vsi->vfta[vid_idx] |= vid_bit;
5200         else
5201                 vsi->vfta[vid_idx] &= ~vid_bit;
5202 }
5203
5204 /**
5205  * Find all vlan options for specific mac addr,
5206  * return with actual vlan found.
5207  */
5208 static inline int
5209 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5210                            struct i40e_macvlan_filter *mv_f,
5211                            int num, struct ether_addr *addr)
5212 {
5213         int i;
5214         uint32_t j, k;
5215
5216         /**
5217          * Not to use i40e_find_vlan_filter to decrease the loop time,
5218          * although the code looks complex.
5219           */
5220         if (num < vsi->vlan_num)
5221                 return I40E_ERR_PARAM;
5222
5223         i = 0;
5224         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5225                 if (vsi->vfta[j]) {
5226                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5227                                 if (vsi->vfta[j] & (1 << k)) {
5228                                         if (i > num - 1) {
5229                                                 PMD_DRV_LOG(ERR, "vlan number "
5230                                                             "not match");
5231                                                 return I40E_ERR_PARAM;
5232                                         }
5233                                         (void)rte_memcpy(&mv_f[i].macaddr,
5234                                                         addr, ETH_ADDR_LEN);
5235                                         mv_f[i].vlan_id =
5236                                                 j * I40E_UINT32_BIT_SIZE + k;
5237                                         i++;
5238                                 }
5239                         }
5240                 }
5241         }
5242         return I40E_SUCCESS;
5243 }
5244
5245 static inline int
5246 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5247                            struct i40e_macvlan_filter *mv_f,
5248                            int num,
5249                            uint16_t vlan)
5250 {
5251         int i = 0;
5252         struct i40e_mac_filter *f;
5253
5254         if (num < vsi->mac_num)
5255                 return I40E_ERR_PARAM;
5256
5257         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5258                 if (i > num - 1) {
5259                         PMD_DRV_LOG(ERR, "buffer number not match");
5260                         return I40E_ERR_PARAM;
5261                 }
5262                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5263                                 ETH_ADDR_LEN);
5264                 mv_f[i].vlan_id = vlan;
5265                 mv_f[i].filter_type = f->mac_info.filter_type;
5266                 i++;
5267         }
5268
5269         return I40E_SUCCESS;
5270 }
5271
5272 static int
5273 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5274 {
5275         int i, num;
5276         struct i40e_mac_filter *f;
5277         struct i40e_macvlan_filter *mv_f;
5278         int ret = I40E_SUCCESS;
5279
5280         if (vsi == NULL || vsi->mac_num == 0)
5281                 return I40E_ERR_PARAM;
5282
5283         /* Case that no vlan is set */
5284         if (vsi->vlan_num == 0)
5285                 num = vsi->mac_num;
5286         else
5287                 num = vsi->mac_num * vsi->vlan_num;
5288
5289         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5290         if (mv_f == NULL) {
5291                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5292                 return I40E_ERR_NO_MEMORY;
5293         }
5294
5295         i = 0;
5296         if (vsi->vlan_num == 0) {
5297                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5298                         (void)rte_memcpy(&mv_f[i].macaddr,
5299                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5300                         mv_f[i].vlan_id = 0;
5301                         i++;
5302                 }
5303         } else {
5304                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5305                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5306                                         vsi->vlan_num, &f->mac_info.mac_addr);
5307                         if (ret != I40E_SUCCESS)
5308                                 goto DONE;
5309                         i += vsi->vlan_num;
5310                 }
5311         }
5312
5313         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5314 DONE:
5315         rte_free(mv_f);
5316
5317         return ret;
5318 }
5319
5320 int
5321 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5322 {
5323         struct i40e_macvlan_filter *mv_f;
5324         int mac_num;
5325         int ret = I40E_SUCCESS;
5326
5327         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5328                 return I40E_ERR_PARAM;
5329
5330         /* If it's already set, just return */
5331         if (i40e_find_vlan_filter(vsi,vlan))
5332                 return I40E_SUCCESS;
5333
5334         mac_num = vsi->mac_num;
5335
5336         if (mac_num == 0) {
5337                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5338                 return I40E_ERR_PARAM;
5339         }
5340
5341         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5342
5343         if (mv_f == NULL) {
5344                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5345                 return I40E_ERR_NO_MEMORY;
5346         }
5347
5348         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5349
5350         if (ret != I40E_SUCCESS)
5351                 goto DONE;
5352
5353         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5354
5355         if (ret != I40E_SUCCESS)
5356                 goto DONE;
5357
5358         i40e_set_vlan_filter(vsi, vlan, 1);
5359
5360         vsi->vlan_num++;
5361         ret = I40E_SUCCESS;
5362 DONE:
5363         rte_free(mv_f);
5364         return ret;
5365 }
5366
5367 int
5368 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5369 {
5370         struct i40e_macvlan_filter *mv_f;
5371         int mac_num;
5372         int ret = I40E_SUCCESS;
5373
5374         /**
5375          * Vlan 0 is the generic filter for untagged packets
5376          * and can't be removed.
5377          */
5378         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5379                 return I40E_ERR_PARAM;
5380
5381         /* If can't find it, just return */
5382         if (!i40e_find_vlan_filter(vsi, vlan))
5383                 return I40E_ERR_PARAM;
5384
5385         mac_num = vsi->mac_num;
5386
5387         if (mac_num == 0) {
5388                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5389                 return I40E_ERR_PARAM;
5390         }
5391
5392         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5393
5394         if (mv_f == NULL) {
5395                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5396                 return I40E_ERR_NO_MEMORY;
5397         }
5398
5399         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5400
5401         if (ret != I40E_SUCCESS)
5402                 goto DONE;
5403
5404         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5405
5406         if (ret != I40E_SUCCESS)
5407                 goto DONE;
5408
5409         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5410         if (vsi->vlan_num == 1) {
5411                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5412                 if (ret != I40E_SUCCESS)
5413                         goto DONE;
5414
5415                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5416                 if (ret != I40E_SUCCESS)
5417                         goto DONE;
5418         }
5419
5420         i40e_set_vlan_filter(vsi, vlan, 0);
5421
5422         vsi->vlan_num--;
5423         ret = I40E_SUCCESS;
5424 DONE:
5425         rte_free(mv_f);
5426         return ret;
5427 }
5428
5429 int
5430 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5431 {
5432         struct i40e_mac_filter *f;
5433         struct i40e_macvlan_filter *mv_f;
5434         int i, vlan_num = 0;
5435         int ret = I40E_SUCCESS;
5436
5437         /* If it's add and we've config it, return */
5438         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5439         if (f != NULL)
5440                 return I40E_SUCCESS;
5441         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5442                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5443
5444                 /**
5445                  * If vlan_num is 0, that's the first time to add mac,
5446                  * set mask for vlan_id 0.
5447                  */
5448                 if (vsi->vlan_num == 0) {
5449                         i40e_set_vlan_filter(vsi, 0, 1);
5450                         vsi->vlan_num = 1;
5451                 }
5452                 vlan_num = vsi->vlan_num;
5453         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5454                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5455                 vlan_num = 1;
5456
5457         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5458         if (mv_f == NULL) {
5459                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5460                 return I40E_ERR_NO_MEMORY;
5461         }
5462
5463         for (i = 0; i < vlan_num; i++) {
5464                 mv_f[i].filter_type = mac_filter->filter_type;
5465                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5466                                 ETH_ADDR_LEN);
5467         }
5468
5469         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5470                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5471                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5472                                         &mac_filter->mac_addr);
5473                 if (ret != I40E_SUCCESS)
5474                         goto DONE;
5475         }
5476
5477         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5478         if (ret != I40E_SUCCESS)
5479                 goto DONE;
5480
5481         /* Add the mac addr into mac list */
5482         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5483         if (f == NULL) {
5484                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5485                 ret = I40E_ERR_NO_MEMORY;
5486                 goto DONE;
5487         }
5488         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5489                         ETH_ADDR_LEN);
5490         f->mac_info.filter_type = mac_filter->filter_type;
5491         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5492         vsi->mac_num++;
5493
5494         ret = I40E_SUCCESS;
5495 DONE:
5496         rte_free(mv_f);
5497
5498         return ret;
5499 }
5500
5501 int
5502 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5503 {
5504         struct i40e_mac_filter *f;
5505         struct i40e_macvlan_filter *mv_f;
5506         int i, vlan_num;
5507         enum rte_mac_filter_type filter_type;
5508         int ret = I40E_SUCCESS;
5509
5510         /* Can't find it, return an error */
5511         f = i40e_find_mac_filter(vsi, addr);
5512         if (f == NULL)
5513                 return I40E_ERR_PARAM;
5514
5515         vlan_num = vsi->vlan_num;
5516         filter_type = f->mac_info.filter_type;
5517         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5518                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5519                 if (vlan_num == 0) {
5520                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5521                         return I40E_ERR_PARAM;
5522                 }
5523         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5524                         filter_type == RTE_MAC_HASH_MATCH)
5525                 vlan_num = 1;
5526
5527         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5528         if (mv_f == NULL) {
5529                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5530                 return I40E_ERR_NO_MEMORY;
5531         }
5532
5533         for (i = 0; i < vlan_num; i++) {
5534                 mv_f[i].filter_type = filter_type;
5535                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5536                                 ETH_ADDR_LEN);
5537         }
5538         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5539                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5540                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5541                 if (ret != I40E_SUCCESS)
5542                         goto DONE;
5543         }
5544
5545         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5546         if (ret != I40E_SUCCESS)
5547                 goto DONE;
5548
5549         /* Remove the mac addr into mac list */
5550         TAILQ_REMOVE(&vsi->mac_list, f, next);
5551         rte_free(f);
5552         vsi->mac_num--;
5553
5554         ret = I40E_SUCCESS;
5555 DONE:
5556         rte_free(mv_f);
5557         return ret;
5558 }
5559
5560 /* Configure hash enable flags for RSS */
5561 uint64_t
5562 i40e_config_hena(uint64_t flags)
5563 {
5564         uint64_t hena = 0;
5565
5566         if (!flags)
5567                 return hena;
5568
5569         if (flags & ETH_RSS_FRAG_IPV4)
5570                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5571         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5572                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5573         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5574                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5575         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5576                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5577         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5578                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5579         if (flags & ETH_RSS_FRAG_IPV6)
5580                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5581         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5582                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5583         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5584                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5585         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5586                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5587         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5588                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5589         if (flags & ETH_RSS_L2_PAYLOAD)
5590                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5591
5592         return hena;
5593 }
5594
5595 /* Parse the hash enable flags */
5596 uint64_t
5597 i40e_parse_hena(uint64_t flags)
5598 {
5599         uint64_t rss_hf = 0;
5600
5601         if (!flags)
5602                 return rss_hf;
5603         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5604                 rss_hf |= ETH_RSS_FRAG_IPV4;
5605         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5606                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5607         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5608                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5609         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5610                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5611         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5612                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5613         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5614                 rss_hf |= ETH_RSS_FRAG_IPV6;
5615         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5616                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5617         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5618                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5619         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5620                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5621         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5622                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5623         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5624                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5625
5626         return rss_hf;
5627 }
5628
5629 /* Disable RSS */
5630 static void
5631 i40e_pf_disable_rss(struct i40e_pf *pf)
5632 {
5633         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5634         uint64_t hena;
5635
5636         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5637         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5638         hena &= ~I40E_RSS_HENA_ALL;
5639         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5640         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5641         I40E_WRITE_FLUSH(hw);
5642 }
5643
5644 static int
5645 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5646 {
5647         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5648         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5649         int ret = 0;
5650
5651         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5652                 sizeof(uint32_t)))
5653                 return -EINVAL;
5654
5655         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5656                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5657                         (struct i40e_aqc_get_set_rss_key_data *)key;
5658
5659                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5660                 if (ret)
5661                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5662                                      "via AQ");
5663         } else {
5664                 uint32_t *hash_key = (uint32_t *)key;
5665                 uint16_t i;
5666
5667                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5668                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5669                 I40E_WRITE_FLUSH(hw);
5670         }
5671
5672         return ret;
5673 }
5674
5675 static int
5676 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5677 {
5678         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5679         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5680         int ret;
5681
5682         if (!key || !key_len)
5683                 return -EINVAL;
5684
5685         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5686                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5687                         (struct i40e_aqc_get_set_rss_key_data *)key);
5688                 if (ret) {
5689                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5690                         return ret;
5691                 }
5692         } else {
5693                 uint32_t *key_dw = (uint32_t *)key;
5694                 uint16_t i;
5695
5696                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5697                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5698         }
5699         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5700
5701         return 0;
5702 }
5703
5704 static int
5705 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5706 {
5707         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5708         uint64_t rss_hf;
5709         uint64_t hena;
5710         int ret;
5711
5712         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5713                                rss_conf->rss_key_len);
5714         if (ret)
5715                 return ret;
5716
5717         rss_hf = rss_conf->rss_hf;
5718         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5719         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5720         hena &= ~I40E_RSS_HENA_ALL;
5721         hena |= i40e_config_hena(rss_hf);
5722         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5723         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5724         I40E_WRITE_FLUSH(hw);
5725
5726         return 0;
5727 }
5728
5729 static int
5730 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5731                          struct rte_eth_rss_conf *rss_conf)
5732 {
5733         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5735         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5736         uint64_t hena;
5737
5738         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5739         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5740         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5741                 if (rss_hf != 0) /* Enable RSS */
5742                         return -EINVAL;
5743                 return 0; /* Nothing to do */
5744         }
5745         /* RSS enabled */
5746         if (rss_hf == 0) /* Disable RSS */
5747                 return -EINVAL;
5748
5749         return i40e_hw_rss_hash_set(pf, rss_conf);
5750 }
5751
5752 static int
5753 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5754                            struct rte_eth_rss_conf *rss_conf)
5755 {
5756         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5757         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5758         uint64_t hena;
5759
5760         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5761                          &rss_conf->rss_key_len);
5762
5763         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5764         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5765         rss_conf->rss_hf = i40e_parse_hena(hena);
5766
5767         return 0;
5768 }
5769
5770 static int
5771 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5772 {
5773         switch (filter_type) {
5774         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5775                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5776                 break;
5777         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5778                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5779                 break;
5780         case RTE_TUNNEL_FILTER_IMAC_TENID:
5781                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5782                 break;
5783         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5784                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5785                 break;
5786         case ETH_TUNNEL_FILTER_IMAC:
5787                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5788                 break;
5789         default:
5790                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5791                 return -EINVAL;
5792         }
5793
5794         return 0;
5795 }
5796
5797 static int
5798 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5799                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5800                         uint8_t add)
5801 {
5802         uint16_t ip_type;
5803         uint8_t tun_type = 0;
5804         int val, ret = 0;
5805         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5806         struct i40e_vsi *vsi = pf->main_vsi;
5807         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5808         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5809
5810         cld_filter = rte_zmalloc("tunnel_filter",
5811                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5812                 0);
5813
5814         if (NULL == cld_filter) {
5815                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5816                 return -EINVAL;
5817         }
5818         pfilter = cld_filter;
5819
5820         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5821                         sizeof(struct ether_addr));
5822         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5823                         sizeof(struct ether_addr));
5824
5825         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5826         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5827                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5828                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5829                                 &tunnel_filter->ip_addr,
5830                                 sizeof(pfilter->ipaddr.v4.data));
5831         } else {
5832                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5833                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5834                                 &tunnel_filter->ip_addr,
5835                                 sizeof(pfilter->ipaddr.v6.data));
5836         }
5837
5838         /* check tunneled type */
5839         switch (tunnel_filter->tunnel_type) {
5840         case RTE_TUNNEL_TYPE_VXLAN:
5841                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5842                 break;
5843         case RTE_TUNNEL_TYPE_NVGRE:
5844                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5845                 break;
5846         default:
5847                 /* Other tunnel types is not supported. */
5848                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5849                 rte_free(cld_filter);
5850                 return -EINVAL;
5851         }
5852
5853         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5854                                                 &pfilter->flags);
5855         if (val < 0) {
5856                 rte_free(cld_filter);
5857                 return -EINVAL;
5858         }
5859
5860         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5861                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5862         pfilter->tenant_id = tunnel_filter->tenant_id;
5863         pfilter->queue_number = tunnel_filter->queue_id;
5864
5865         if (add)
5866                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5867         else
5868                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5869                                                 cld_filter, 1);
5870
5871         rte_free(cld_filter);
5872         return ret;
5873 }
5874
5875 static int
5876 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5877 {
5878         uint8_t i;
5879
5880         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5881                 if (pf->vxlan_ports[i] == port)
5882                         return i;
5883         }
5884
5885         return -1;
5886 }
5887
5888 static int
5889 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5890 {
5891         int  idx, ret;
5892         uint8_t filter_idx;
5893         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5894
5895         idx = i40e_get_vxlan_port_idx(pf, port);
5896
5897         /* Check if port already exists */
5898         if (idx >= 0) {
5899                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5900                 return -EINVAL;
5901         }
5902
5903         /* Now check if there is space to add the new port */
5904         idx = i40e_get_vxlan_port_idx(pf, 0);
5905         if (idx < 0) {
5906                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5907                         "not adding port %d", port);
5908                 return -ENOSPC;
5909         }
5910
5911         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5912                                         &filter_idx, NULL);
5913         if (ret < 0) {
5914                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5915                 return -1;
5916         }
5917
5918         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5919                          port,  filter_idx);
5920
5921         /* New port: add it and mark its index in the bitmap */
5922         pf->vxlan_ports[idx] = port;
5923         pf->vxlan_bitmap |= (1 << idx);
5924
5925         if (!(pf->flags & I40E_FLAG_VXLAN))
5926                 pf->flags |= I40E_FLAG_VXLAN;
5927
5928         return 0;
5929 }
5930
5931 static int
5932 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5933 {
5934         int idx;
5935         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5936
5937         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5938                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5939                 return -EINVAL;
5940         }
5941
5942         idx = i40e_get_vxlan_port_idx(pf, port);
5943
5944         if (idx < 0) {
5945                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5946                 return -EINVAL;
5947         }
5948
5949         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5950                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5951                 return -1;
5952         }
5953
5954         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5955                         port, idx);
5956
5957         pf->vxlan_ports[idx] = 0;
5958         pf->vxlan_bitmap &= ~(1 << idx);
5959
5960         if (!pf->vxlan_bitmap)
5961                 pf->flags &= ~I40E_FLAG_VXLAN;
5962
5963         return 0;
5964 }
5965
5966 /* Add UDP tunneling port */
5967 static int
5968 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5969                         struct rte_eth_udp_tunnel *udp_tunnel)
5970 {
5971         int ret = 0;
5972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5973
5974         if (udp_tunnel == NULL)
5975                 return -EINVAL;
5976
5977         switch (udp_tunnel->prot_type) {
5978         case RTE_TUNNEL_TYPE_VXLAN:
5979                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5980                 break;
5981
5982         case RTE_TUNNEL_TYPE_GENEVE:
5983         case RTE_TUNNEL_TYPE_TEREDO:
5984                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5985                 ret = -1;
5986                 break;
5987
5988         default:
5989                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5990                 ret = -1;
5991                 break;
5992         }
5993
5994         return ret;
5995 }
5996
5997 /* Remove UDP tunneling port */
5998 static int
5999 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6000                         struct rte_eth_udp_tunnel *udp_tunnel)
6001 {
6002         int ret = 0;
6003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6004
6005         if (udp_tunnel == NULL)
6006                 return -EINVAL;
6007
6008         switch (udp_tunnel->prot_type) {
6009         case RTE_TUNNEL_TYPE_VXLAN:
6010                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6011                 break;
6012         case RTE_TUNNEL_TYPE_GENEVE:
6013         case RTE_TUNNEL_TYPE_TEREDO:
6014                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6015                 ret = -1;
6016                 break;
6017         default:
6018                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6019                 ret = -1;
6020                 break;
6021         }
6022
6023         return ret;
6024 }
6025
6026 /* Calculate the maximum number of contiguous PF queues that are configured */
6027 static int
6028 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6029 {
6030         struct rte_eth_dev_data *data = pf->dev_data;
6031         int i, num;
6032         struct i40e_rx_queue *rxq;
6033
6034         num = 0;
6035         for (i = 0; i < pf->lan_nb_qps; i++) {
6036                 rxq = data->rx_queues[i];
6037                 if (rxq && rxq->q_set)
6038                         num++;
6039                 else
6040                         break;
6041         }
6042
6043         return num;
6044 }
6045
6046 /* Configure RSS */
6047 static int
6048 i40e_pf_config_rss(struct i40e_pf *pf)
6049 {
6050         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6051         struct rte_eth_rss_conf rss_conf;
6052         uint32_t i, lut = 0;
6053         uint16_t j, num;
6054
6055         /*
6056          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6057          * It's necessary to calulate the actual PF queues that are configured.
6058          */
6059         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6060                 num = i40e_pf_calc_configured_queues_num(pf);
6061         else
6062                 num = pf->dev_data->nb_rx_queues;
6063
6064         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6065         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6066                         num);
6067
6068         if (num == 0) {
6069                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6070                 return -ENOTSUP;
6071         }
6072
6073         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6074                 if (j == num)
6075                         j = 0;
6076                 lut = (lut << 8) | (j & ((0x1 <<
6077                         hw->func_caps.rss_table_entry_width) - 1));
6078                 if ((i & 3) == 3)
6079                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6080         }
6081
6082         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6083         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6084                 i40e_pf_disable_rss(pf);
6085                 return 0;
6086         }
6087         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6088                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6089                 /* Random default keys */
6090                 static uint32_t rss_key_default[] = {0x6b793944,
6091                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6092                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6093                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6094
6095                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6096                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6097                                                         sizeof(uint32_t);
6098         }
6099
6100         return i40e_hw_rss_hash_set(pf, &rss_conf);
6101 }
6102
6103 static int
6104 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6105                                struct rte_eth_tunnel_filter_conf *filter)
6106 {
6107         if (pf == NULL || filter == NULL) {
6108                 PMD_DRV_LOG(ERR, "Invalid parameter");
6109                 return -EINVAL;
6110         }
6111
6112         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6113                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6114                 return -EINVAL;
6115         }
6116
6117         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6118                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6119                 return -EINVAL;
6120         }
6121
6122         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6123                 (is_zero_ether_addr(filter->outer_mac))) {
6124                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6125                 return -EINVAL;
6126         }
6127
6128         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6129                 (is_zero_ether_addr(filter->inner_mac))) {
6130                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6131                 return -EINVAL;
6132         }
6133
6134         return 0;
6135 }
6136
6137 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6138 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6139 static int
6140 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6141 {
6142         uint32_t val, reg;
6143         int ret = -EINVAL;
6144
6145         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6146         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6147
6148         if (len == 3) {
6149                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6150         } else if (len == 4) {
6151                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6152         } else {
6153                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6154                 return ret;
6155         }
6156
6157         if (reg != val) {
6158                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6159                                                    reg, NULL);
6160                 if (ret != 0)
6161                         return ret;
6162         } else {
6163                 ret = 0;
6164         }
6165         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6166                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6167
6168         return ret;
6169 }
6170
6171 static int
6172 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6173 {
6174         int ret = -EINVAL;
6175
6176         if (!hw || !cfg)
6177                 return -EINVAL;
6178
6179         switch (cfg->cfg_type) {
6180         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6181                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6182                 break;
6183         default:
6184                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6185                 break;
6186         }
6187
6188         return ret;
6189 }
6190
6191 static int
6192 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6193                                enum rte_filter_op filter_op,
6194                                void *arg)
6195 {
6196         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6197         int ret = I40E_ERR_PARAM;
6198
6199         switch (filter_op) {
6200         case RTE_ETH_FILTER_SET:
6201                 ret = i40e_dev_global_config_set(hw,
6202                         (struct rte_eth_global_cfg *)arg);
6203                 break;
6204         default:
6205                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6206                 break;
6207         }
6208
6209         return ret;
6210 }
6211
6212 static int
6213 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6214                           enum rte_filter_op filter_op,
6215                           void *arg)
6216 {
6217         struct rte_eth_tunnel_filter_conf *filter;
6218         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6219         int ret = I40E_SUCCESS;
6220
6221         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6222
6223         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6224                 return I40E_ERR_PARAM;
6225
6226         switch (filter_op) {
6227         case RTE_ETH_FILTER_NOP:
6228                 if (!(pf->flags & I40E_FLAG_VXLAN))
6229                         ret = I40E_NOT_SUPPORTED;
6230                 break;
6231         case RTE_ETH_FILTER_ADD:
6232                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6233                 break;
6234         case RTE_ETH_FILTER_DELETE:
6235                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6236                 break;
6237         default:
6238                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6239                 ret = I40E_ERR_PARAM;
6240                 break;
6241         }
6242
6243         return ret;
6244 }
6245
6246 static int
6247 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6248 {
6249         int ret = 0;
6250         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6251
6252         /* RSS setup */
6253         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6254                 ret = i40e_pf_config_rss(pf);
6255         else
6256                 i40e_pf_disable_rss(pf);
6257
6258         return ret;
6259 }
6260
6261 /* Get the symmetric hash enable configurations per port */
6262 static void
6263 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6264 {
6265         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6266
6267         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6268 }
6269
6270 /* Set the symmetric hash enable configurations per port */
6271 static void
6272 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6273 {
6274         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6275
6276         if (enable > 0) {
6277                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6278                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6279                                                         "been enabled");
6280                         return;
6281                 }
6282                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6283         } else {
6284                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6285                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6286                                                         "been disabled");
6287                         return;
6288                 }
6289                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6290         }
6291         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6292         I40E_WRITE_FLUSH(hw);
6293 }
6294
6295 /*
6296  * Get global configurations of hash function type and symmetric hash enable
6297  * per flow type (pctype). Note that global configuration means it affects all
6298  * the ports on the same NIC.
6299  */
6300 static int
6301 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6302                                    struct rte_eth_hash_global_conf *g_cfg)
6303 {
6304         uint32_t reg, mask = I40E_FLOW_TYPES;
6305         uint16_t i;
6306         enum i40e_filter_pctype pctype;
6307
6308         memset(g_cfg, 0, sizeof(*g_cfg));
6309         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6310         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6311                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6312         else
6313                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6314         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6315                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6316
6317         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6318                 if (!(mask & (1UL << i)))
6319                         continue;
6320                 mask &= ~(1UL << i);
6321                 /* Bit set indicats the coresponding flow type is supported */
6322                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6323                 pctype = i40e_flowtype_to_pctype(i);
6324                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6325                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6326                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6327         }
6328
6329         return 0;
6330 }
6331
6332 static int
6333 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6334 {
6335         uint32_t i;
6336         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6337
6338         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6339                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6340                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6341                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6342                                                 g_cfg->hash_func);
6343                 return -EINVAL;
6344         }
6345
6346         /*
6347          * As i40e supports less than 32 flow types, only first 32 bits need to
6348          * be checked.
6349          */
6350         mask0 = g_cfg->valid_bit_mask[0];
6351         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6352                 if (i == 0) {
6353                         /* Check if any unsupported flow type configured */
6354                         if ((mask0 | i40e_mask) ^ i40e_mask)
6355                                 goto mask_err;
6356                 } else {
6357                         if (g_cfg->valid_bit_mask[i])
6358                                 goto mask_err;
6359                 }
6360         }
6361
6362         return 0;
6363
6364 mask_err:
6365         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6366
6367         return -EINVAL;
6368 }
6369
6370 /*
6371  * Set global configurations of hash function type and symmetric hash enable
6372  * per flow type (pctype). Note any modifying global configuration will affect
6373  * all the ports on the same NIC.
6374  */
6375 static int
6376 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6377                                    struct rte_eth_hash_global_conf *g_cfg)
6378 {
6379         int ret;
6380         uint16_t i;
6381         uint32_t reg;
6382         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6383         enum i40e_filter_pctype pctype;
6384
6385         /* Check the input parameters */
6386         ret = i40e_hash_global_config_check(g_cfg);
6387         if (ret < 0)
6388                 return ret;
6389
6390         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6391                 if (!(mask0 & (1UL << i)))
6392                         continue;
6393                 mask0 &= ~(1UL << i);
6394                 pctype = i40e_flowtype_to_pctype(i);
6395                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6396                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6397                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6398         }
6399
6400         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6401         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6402                 /* Toeplitz */
6403                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6404                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6405                                                                 "Toeplitz");
6406                         goto out;
6407                 }
6408                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6409         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6410                 /* Simple XOR */
6411                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6412                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6413                                                         "Simple XOR");
6414                         goto out;
6415                 }
6416                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6417         } else
6418                 /* Use the default, and keep it as it is */
6419                 goto out;
6420
6421         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6422
6423 out:
6424         I40E_WRITE_FLUSH(hw);
6425
6426         return 0;
6427 }
6428
6429 /**
6430  * Valid input sets for hash and flow director filters per PCTYPE
6431  */
6432 static uint64_t
6433 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6434                 enum rte_filter_type filter)
6435 {
6436         uint64_t valid;
6437
6438         static const uint64_t valid_hash_inset_table[] = {
6439                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6440                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6441                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6442                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6443                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6444                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6445                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6446                         I40E_INSET_FLEX_PAYLOAD,
6447                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6448                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6449                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6450                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6451                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6452                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6453                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6454                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6455                         I40E_INSET_FLEX_PAYLOAD,
6456                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6457                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6458                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6459                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6460                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6461                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6462                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6463                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6464                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6465                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6466                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6467                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6468                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6469                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6470                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6471                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6472                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6473                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6474                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6475                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6476                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6477                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6478                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6479                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6480                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6481                         I40E_INSET_FLEX_PAYLOAD,
6482                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6483                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6484                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6485                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6486                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6487                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6488                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6489                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6490                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6491                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6492                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6493                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6494                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6495                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6496                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6497                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6498                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6499                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6500                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6501                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6502                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6503                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6504                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6505                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6506                         I40E_INSET_FLEX_PAYLOAD,
6507                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6508                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6509                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6510                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6511                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6512                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6513                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6514                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6515                         I40E_INSET_FLEX_PAYLOAD,
6516                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6517                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6518                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6519                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6520                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6521                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6522                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6523                         I40E_INSET_FLEX_PAYLOAD,
6524                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6525                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6526                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6527                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6528                         I40E_INSET_FLEX_PAYLOAD,
6529         };
6530
6531         /**
6532          * Flow director supports only fields defined in
6533          * union rte_eth_fdir_flow.
6534          */
6535         static const uint64_t valid_fdir_inset_table[] = {
6536                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6537                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6538                 I40E_INSET_FLEX_PAYLOAD,
6539                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6540                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6541                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6542                 I40E_INSET_FLEX_PAYLOAD,
6543                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6544                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6545                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6546                 I40E_INSET_FLEX_PAYLOAD,
6547                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6548                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6549                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6550                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6551                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6552                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6553                 I40E_INSET_FLEX_PAYLOAD,
6554                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6555                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6556                 I40E_INSET_FLEX_PAYLOAD,
6557                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6558                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6559                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6560                 I40E_INSET_FLEX_PAYLOAD,
6561                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6562                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6563                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6564                 I40E_INSET_FLEX_PAYLOAD,
6565                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6566                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6567                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6568                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6569                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6570                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6571                 I40E_INSET_FLEX_PAYLOAD,
6572                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6573                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6574         };
6575
6576         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6577                 return 0;
6578         if (filter == RTE_ETH_FILTER_HASH)
6579                 valid = valid_hash_inset_table[pctype];
6580         else
6581                 valid = valid_fdir_inset_table[pctype];
6582
6583         return valid;
6584 }
6585
6586 /**
6587  * Validate if the input set is allowed for a specific PCTYPE
6588  */
6589 static int
6590 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6591                 enum rte_filter_type filter, uint64_t inset)
6592 {
6593         uint64_t valid;
6594
6595         valid = i40e_get_valid_input_set(pctype, filter);
6596         if (inset & (~valid))
6597                 return -EINVAL;
6598
6599         return 0;
6600 }
6601
6602 /* default input set fields combination per pctype */
6603 static uint64_t
6604 i40e_get_default_input_set(uint16_t pctype)
6605 {
6606         static const uint64_t default_inset_table[] = {
6607                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6608                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6609                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6610                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6611                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6612                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6613                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6614                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6615                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6616                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6617                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6618                         I40E_INSET_SCTP_VT,
6619                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6620                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6621                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6622                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6623                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6624                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6625                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6626                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6627                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6628                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6629                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6630                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6631                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6632                         I40E_INSET_SCTP_VT,
6633                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6634                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6635                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6636                         I40E_INSET_LAST_ETHER_TYPE,
6637         };
6638
6639         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6640                 return 0;
6641
6642         return default_inset_table[pctype];
6643 }
6644
6645 /**
6646  * Parse the input set from index to logical bit masks
6647  */
6648 static int
6649 i40e_parse_input_set(uint64_t *inset,
6650                      enum i40e_filter_pctype pctype,
6651                      enum rte_eth_input_set_field *field,
6652                      uint16_t size)
6653 {
6654         uint16_t i, j;
6655         int ret = -EINVAL;
6656
6657         static const struct {
6658                 enum rte_eth_input_set_field field;
6659                 uint64_t inset;
6660         } inset_convert_table[] = {
6661                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6662                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6663                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6664                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6665                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6666                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6667                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6668                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6669                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6670                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6671                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6672                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6673                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6674                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6675                         I40E_INSET_IPV6_NEXT_HDR},
6676                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6677                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6678                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6679                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6680                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6681                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6682                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6683                         I40E_INSET_SCTP_VT},
6684                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6685                         I40E_INSET_TUNNEL_DMAC},
6686                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6687                         I40E_INSET_VLAN_TUNNEL},
6688                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6689                         I40E_INSET_TUNNEL_ID},
6690                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6691                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6692                         I40E_INSET_FLEX_PAYLOAD_W1},
6693                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6694                         I40E_INSET_FLEX_PAYLOAD_W2},
6695                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6696                         I40E_INSET_FLEX_PAYLOAD_W3},
6697                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6698                         I40E_INSET_FLEX_PAYLOAD_W4},
6699                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6700                         I40E_INSET_FLEX_PAYLOAD_W5},
6701                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6702                         I40E_INSET_FLEX_PAYLOAD_W6},
6703                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6704                         I40E_INSET_FLEX_PAYLOAD_W7},
6705                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6706                         I40E_INSET_FLEX_PAYLOAD_W8},
6707         };
6708
6709         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6710                 return ret;
6711
6712         /* Only one item allowed for default or all */
6713         if (size == 1) {
6714                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6715                         *inset = i40e_get_default_input_set(pctype);
6716                         return 0;
6717                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6718                         *inset = I40E_INSET_NONE;
6719                         return 0;
6720                 }
6721         }
6722
6723         for (i = 0, *inset = 0; i < size; i++) {
6724                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6725                         if (field[i] == inset_convert_table[j].field) {
6726                                 *inset |= inset_convert_table[j].inset;
6727                                 break;
6728                         }
6729                 }
6730
6731                 /* It contains unsupported input set, return immediately */
6732                 if (j == RTE_DIM(inset_convert_table))
6733                         return ret;
6734         }
6735
6736         return 0;
6737 }
6738
6739 /**
6740  * Translate the input set from bit masks to register aware bit masks
6741  * and vice versa
6742  */
6743 static uint64_t
6744 i40e_translate_input_set_reg(uint64_t input)
6745 {
6746         uint64_t val = 0;
6747         uint16_t i;
6748
6749         static const struct {
6750                 uint64_t inset;
6751                 uint64_t inset_reg;
6752         } inset_map[] = {
6753                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6754                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6755                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6756                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6757                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6758                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6759                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6760                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6761                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6762                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6763                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6764                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6765                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6766                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6767                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6768                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6769                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6770                 {I40E_INSET_TUNNEL_DMAC,
6771                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6772                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6773                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6774                 {I40E_INSET_TUNNEL_SRC_PORT,
6775                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6776                 {I40E_INSET_TUNNEL_DST_PORT,
6777                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6778                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6779                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6780                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6781                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6782                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6783                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6784                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6785                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6786                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6787         };
6788
6789         if (input == 0)
6790                 return val;
6791
6792         /* Translate input set to register aware inset */
6793         for (i = 0; i < RTE_DIM(inset_map); i++) {
6794                 if (input & inset_map[i].inset)
6795                         val |= inset_map[i].inset_reg;
6796         }
6797
6798         return val;
6799 }
6800
6801 static uint8_t
6802 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6803 {
6804         uint8_t i, idx = 0;
6805
6806         static const struct {
6807                 uint64_t inset;
6808                 uint32_t mask;
6809         } inset_mask_map[] = {
6810                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6811                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6812                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6813                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6814         };
6815
6816         if (!inset || !mask || !nb_elem)
6817                 return 0;
6818
6819         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6820                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6821                         mask[i] = 0;
6822                 return I40E_INSET_MASK_NUM_REG;
6823         }
6824
6825         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6826                 if (idx >= nb_elem)
6827                         break;
6828                 if (inset & inset_mask_map[i].inset) {
6829                         mask[idx] = inset_mask_map[i].mask;
6830                         idx++;
6831                 }
6832         }
6833
6834         return idx;
6835 }
6836
6837 static uint64_t
6838 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6839                             enum i40e_filter_pctype pctype)
6840 {
6841         uint64_t reg = 0;
6842
6843         if (filter == RTE_ETH_FILTER_HASH) {
6844                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6845                 reg <<= I40E_32_BIT_WIDTH;
6846                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6847         } else if (filter == RTE_ETH_FILTER_FDIR) {
6848                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6849                 reg <<= I40E_32_BIT_WIDTH;
6850                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6851         }
6852
6853         return reg;
6854 }
6855
6856 static void
6857 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6858 {
6859         uint32_t reg = I40E_READ_REG(hw, addr);
6860
6861         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6862         if (reg != val)
6863                 I40E_WRITE_REG(hw, addr, val);
6864         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6865                     (uint32_t)I40E_READ_REG(hw, addr));
6866 }
6867
6868 static int
6869 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6870                          enum i40e_filter_pctype pctype,
6871                          enum rte_filter_input_set_op op,
6872                          uint32_t *mask_reg,
6873                          uint8_t num)
6874 {
6875         uint32_t reg;
6876         uint8_t i;
6877
6878         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6879                 return -EINVAL;
6880
6881         if (op == RTE_ETH_INPUT_SET_SELECT) {
6882                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6883                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6884                                              0);
6885                         if (i >= num)
6886                                 continue;
6887                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6888                                              mask_reg[i]);
6889                 }
6890         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6891                 uint8_t j, count = 0;
6892
6893                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6894                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6895                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6896                                 count++;
6897                 }
6898                 if (count + num > I40E_INSET_MASK_NUM_REG)
6899                         return -EINVAL;
6900
6901                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6902                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6903                                              mask_reg[j]);
6904         }
6905
6906         return 0;
6907 }
6908
6909 static int
6910 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6911                        enum i40e_filter_pctype pctype,
6912                        enum rte_filter_input_set_op op,
6913                        uint32_t *mask_reg,
6914                        uint8_t num)
6915 {
6916         uint32_t reg;
6917         uint8_t i;
6918
6919         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6920                 return -EINVAL;
6921
6922         if (op == RTE_ETH_INPUT_SET_SELECT) {
6923                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6924                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6925                                              0);
6926                         if (i >= num)
6927                                 continue;
6928                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6929                                              mask_reg[i]);
6930                 }
6931         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6932                 uint8_t j, count = 0;
6933
6934                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6935                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6936                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6937                                 count++;
6938                 }
6939                 if (count + num > I40E_INSET_MASK_NUM_REG)
6940                         return -EINVAL;
6941
6942                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6943                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6944                                              mask_reg[j]);
6945         }
6946
6947         return 0;
6948 }
6949
6950 int
6951 i40e_filter_inset_select(struct i40e_hw *hw,
6952                          struct rte_eth_input_set_conf *conf,
6953                          enum rte_filter_type filter)
6954 {
6955         enum i40e_filter_pctype pctype;
6956         uint64_t inset_reg = 0, input_set;
6957         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6958         uint8_t num;
6959         int ret;
6960
6961         if (!hw || !conf) {
6962                 PMD_DRV_LOG(ERR, "Invalid pointer");
6963                 return -EFAULT;
6964         }
6965
6966         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6967         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6968                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6969                             conf->flow_type);
6970                 return -EINVAL;
6971         }
6972         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6973                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6974                 return -EINVAL;
6975         }
6976
6977         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6978                                    conf->inset_size);
6979         if (ret) {
6980                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6981                 return -EINVAL;
6982         }
6983         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6984                 PMD_DRV_LOG(ERR, "Invalid input set");
6985                 return -EINVAL;
6986         }
6987
6988         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6989                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6990         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6991                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6992                 return -EINVAL;
6993         }
6994         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6995                                            I40E_INSET_MASK_NUM_REG);
6996         inset_reg |= i40e_translate_input_set_reg(input_set);
6997
6998         if (filter == RTE_ETH_FILTER_HASH) {
6999                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7000                                                num);
7001                 if (ret)
7002                         return -EINVAL;
7003
7004                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7005                                       (uint32_t)(inset_reg & UINT32_MAX));
7006                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7007                                      (uint32_t)((inset_reg >>
7008                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7009         } else if (filter == RTE_ETH_FILTER_FDIR) {
7010                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7011                                              num);
7012                 if (ret)
7013                         return -EINVAL;
7014
7015                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7016                                       (uint32_t)(inset_reg & UINT32_MAX));
7017                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7018                                      (uint32_t)((inset_reg >>
7019                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7020         } else {
7021                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7022                 return -EINVAL;
7023         }
7024         I40E_WRITE_FLUSH(hw);
7025
7026         return 0;
7027 }
7028
7029 static int
7030 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7031 {
7032         int ret = 0;
7033
7034         if (!hw || !info) {
7035                 PMD_DRV_LOG(ERR, "Invalid pointer");
7036                 return -EFAULT;
7037         }
7038
7039         switch (info->info_type) {
7040         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7041                 i40e_get_symmetric_hash_enable_per_port(hw,
7042                                         &(info->info.enable));
7043                 break;
7044         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7045                 ret = i40e_get_hash_filter_global_config(hw,
7046                                 &(info->info.global_conf));
7047                 break;
7048         default:
7049                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7050                                                         info->info_type);
7051                 ret = -EINVAL;
7052                 break;
7053         }
7054
7055         return ret;
7056 }
7057
7058 static int
7059 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7060 {
7061         int ret = 0;
7062
7063         if (!hw || !info) {
7064                 PMD_DRV_LOG(ERR, "Invalid pointer");
7065                 return -EFAULT;
7066         }
7067
7068         switch (info->info_type) {
7069         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7070                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7071                 break;
7072         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7073                 ret = i40e_set_hash_filter_global_config(hw,
7074                                 &(info->info.global_conf));
7075                 break;
7076         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7077                 ret = i40e_filter_inset_select(hw,
7078                                                &(info->info.input_set_conf),
7079                                                RTE_ETH_FILTER_HASH);
7080                 break;
7081
7082         default:
7083                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7084                                                         info->info_type);
7085                 ret = -EINVAL;
7086                 break;
7087         }
7088
7089         return ret;
7090 }
7091
7092 /* Operations for hash function */
7093 static int
7094 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7095                       enum rte_filter_op filter_op,
7096                       void *arg)
7097 {
7098         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7099         int ret = 0;
7100
7101         switch (filter_op) {
7102         case RTE_ETH_FILTER_NOP:
7103                 break;
7104         case RTE_ETH_FILTER_GET:
7105                 ret = i40e_hash_filter_get(hw,
7106                         (struct rte_eth_hash_filter_info *)arg);
7107                 break;
7108         case RTE_ETH_FILTER_SET:
7109                 ret = i40e_hash_filter_set(hw,
7110                         (struct rte_eth_hash_filter_info *)arg);
7111                 break;
7112         default:
7113                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7114                                                                 filter_op);
7115                 ret = -ENOTSUP;
7116                 break;
7117         }
7118
7119         return ret;
7120 }
7121
7122 /*
7123  * Configure ethertype filter, which can director packet by filtering
7124  * with mac address and ether_type or only ether_type
7125  */
7126 static int
7127 i40e_ethertype_filter_set(struct i40e_pf *pf,
7128                         struct rte_eth_ethertype_filter *filter,
7129                         bool add)
7130 {
7131         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7132         struct i40e_control_filter_stats stats;
7133         uint16_t flags = 0;
7134         int ret;
7135
7136         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7137                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7138                 return -EINVAL;
7139         }
7140         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7141                 filter->ether_type == ETHER_TYPE_IPv6) {
7142                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7143                         " control packet filter.", filter->ether_type);
7144                 return -EINVAL;
7145         }
7146         if (filter->ether_type == ETHER_TYPE_VLAN)
7147                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7148                         " not supported.");
7149
7150         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7151                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7152         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7153                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7154         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7155
7156         memset(&stats, 0, sizeof(stats));
7157         ret = i40e_aq_add_rem_control_packet_filter(hw,
7158                         filter->mac_addr.addr_bytes,
7159                         filter->ether_type, flags,
7160                         pf->main_vsi->seid,
7161                         filter->queue, add, &stats, NULL);
7162
7163         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7164                          " mac_etype_used = %u, etype_used = %u,"
7165                          " mac_etype_free = %u, etype_free = %u\n",
7166                          ret, stats.mac_etype_used, stats.etype_used,
7167                          stats.mac_etype_free, stats.etype_free);
7168         if (ret < 0)
7169                 return -ENOSYS;
7170         return 0;
7171 }
7172
7173 /*
7174  * Handle operations for ethertype filter.
7175  */
7176 static int
7177 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7178                                 enum rte_filter_op filter_op,
7179                                 void *arg)
7180 {
7181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7182         int ret = 0;
7183
7184         if (filter_op == RTE_ETH_FILTER_NOP)
7185                 return ret;
7186
7187         if (arg == NULL) {
7188                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7189                             filter_op);
7190                 return -EINVAL;
7191         }
7192
7193         switch (filter_op) {
7194         case RTE_ETH_FILTER_ADD:
7195                 ret = i40e_ethertype_filter_set(pf,
7196                         (struct rte_eth_ethertype_filter *)arg,
7197                         TRUE);
7198                 break;
7199         case RTE_ETH_FILTER_DELETE:
7200                 ret = i40e_ethertype_filter_set(pf,
7201                         (struct rte_eth_ethertype_filter *)arg,
7202                         FALSE);
7203                 break;
7204         default:
7205                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7206                 ret = -ENOSYS;
7207                 break;
7208         }
7209         return ret;
7210 }
7211
7212 static int
7213 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7214                      enum rte_filter_type filter_type,
7215                      enum rte_filter_op filter_op,
7216                      void *arg)
7217 {
7218         int ret = 0;
7219
7220         if (dev == NULL)
7221                 return -EINVAL;
7222
7223         switch (filter_type) {
7224         case RTE_ETH_FILTER_NONE:
7225                 /* For global configuration */
7226                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7227                 break;
7228         case RTE_ETH_FILTER_HASH:
7229                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7230                 break;
7231         case RTE_ETH_FILTER_MACVLAN:
7232                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7233                 break;
7234         case RTE_ETH_FILTER_ETHERTYPE:
7235                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7236                 break;
7237         case RTE_ETH_FILTER_TUNNEL:
7238                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7239                 break;
7240         case RTE_ETH_FILTER_FDIR:
7241                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7242                 break;
7243         default:
7244                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7245                                                         filter_type);
7246                 ret = -EINVAL;
7247                 break;
7248         }
7249
7250         return ret;
7251 }
7252
7253 /*
7254  * As some registers wouldn't be reset unless a global hardware reset,
7255  * hardware initialization is needed to put those registers into an
7256  * expected initial state.
7257  */
7258 static void
7259 i40e_hw_init(struct i40e_hw *hw)
7260 {
7261         /* clear the PF Queue Filter control register */
7262         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7263
7264         /* Disable symmetric hash per port */
7265         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7266 }
7267
7268 enum i40e_filter_pctype
7269 i40e_flowtype_to_pctype(uint16_t flow_type)
7270 {
7271         static const enum i40e_filter_pctype pctype_table[] = {
7272                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7273                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7274                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7275                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7276                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7277                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7278                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7279                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7280                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7281                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7282                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7283                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7284                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7285                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7286                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7287                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7288                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7289                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7290                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7291         };
7292
7293         return pctype_table[flow_type];
7294 }
7295
7296 uint16_t
7297 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7298 {
7299         static const uint16_t flowtype_table[] = {
7300                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7301                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7302                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7303                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7304                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7305                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7306                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7307                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7308                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7309                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7310                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7311                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7312                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7313                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7314                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7315                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7316                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7317                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7318                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7319         };
7320
7321         return flowtype_table[pctype];
7322 }
7323
7324 /*
7325  * On X710, performance number is far from the expectation on recent firmware
7326  * versions; on XL710, performance number is also far from the expectation on
7327  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7328  * mode is enabled and port MAC address is equal to the packet destination MAC
7329  * address. The fix for this issue may not be integrated in the following
7330  * firmware version. So the workaround in software driver is needed. It needs
7331  * to modify the initial values of 3 internal only registers for both X710 and
7332  * XL710. Note that the values for X710 or XL710 could be different, and the
7333  * workaround can be removed when it is fixed in firmware in the future.
7334  */
7335
7336 /* For both X710 and XL710 */
7337 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7338 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7339
7340 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7341 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7342
7343 /* For X710 */
7344 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7345 /* For XL710 */
7346 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7347 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7348
7349 static void
7350 i40e_configure_registers(struct i40e_hw *hw)
7351 {
7352         static struct {
7353                 uint32_t addr;
7354                 uint64_t val;
7355         } reg_table[] = {
7356                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7357                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7358                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7359         };
7360         uint64_t reg;
7361         uint32_t i;
7362         int ret;
7363
7364         for (i = 0; i < RTE_DIM(reg_table); i++) {
7365                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7366                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7367                                 reg_table[i].val =
7368                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7369                         else /* For X710 */
7370                                 reg_table[i].val =
7371                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7372                 }
7373
7374                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7375                                                         &reg, NULL);
7376                 if (ret < 0) {
7377                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7378                                                         reg_table[i].addr);
7379                         break;
7380                 }
7381                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7382                                                 reg_table[i].addr, reg);
7383                 if (reg == reg_table[i].val)
7384                         continue;
7385
7386                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7387                                                 reg_table[i].val, NULL);
7388                 if (ret < 0) {
7389                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7390                                 "address of 0x%"PRIx32, reg_table[i].val,
7391                                                         reg_table[i].addr);
7392                         break;
7393                 }
7394                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7395                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7396         }
7397 }
7398
7399 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7400 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7401 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7402 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7403 static int
7404 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7405 {
7406         uint32_t reg;
7407         int ret;
7408
7409         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7410                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7411                 return -EINVAL;
7412         }
7413
7414         /* Configure for double VLAN RX stripping */
7415         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7416         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7417                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7418                 ret = i40e_aq_debug_write_register(hw,
7419                                                    I40E_VSI_TSR(vsi->vsi_id),
7420                                                    reg, NULL);
7421                 if (ret < 0) {
7422                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7423                                     vsi->vsi_id);
7424                         return I40E_ERR_CONFIG;
7425                 }
7426         }
7427
7428         /* Configure for double VLAN TX insertion */
7429         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7430         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7431                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7432                 ret = i40e_aq_debug_write_register(hw,
7433                                                    I40E_VSI_L2TAGSTXVALID(
7434                                                    vsi->vsi_id), reg, NULL);
7435                 if (ret < 0) {
7436                         PMD_DRV_LOG(ERR, "Failed to update "
7437                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7438                         return I40E_ERR_CONFIG;
7439                 }
7440         }
7441
7442         return 0;
7443 }
7444
7445 /**
7446  * i40e_aq_add_mirror_rule
7447  * @hw: pointer to the hardware structure
7448  * @seid: VEB seid to add mirror rule to
7449  * @dst_id: destination vsi seid
7450  * @entries: Buffer which contains the entities to be mirrored
7451  * @count: number of entities contained in the buffer
7452  * @rule_id:the rule_id of the rule to be added
7453  *
7454  * Add a mirror rule for a given veb.
7455  *
7456  **/
7457 static enum i40e_status_code
7458 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7459                         uint16_t seid, uint16_t dst_id,
7460                         uint16_t rule_type, uint16_t *entries,
7461                         uint16_t count, uint16_t *rule_id)
7462 {
7463         struct i40e_aq_desc desc;
7464         struct i40e_aqc_add_delete_mirror_rule cmd;
7465         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7466                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7467                 &desc.params.raw;
7468         uint16_t buff_len;
7469         enum i40e_status_code status;
7470
7471         i40e_fill_default_direct_cmd_desc(&desc,
7472                                           i40e_aqc_opc_add_mirror_rule);
7473         memset(&cmd, 0, sizeof(cmd));
7474
7475         buff_len = sizeof(uint16_t) * count;
7476         desc.datalen = rte_cpu_to_le_16(buff_len);
7477         if (buff_len > 0)
7478                 desc.flags |= rte_cpu_to_le_16(
7479                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7480         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7481                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7482         cmd.num_entries = rte_cpu_to_le_16(count);
7483         cmd.seid = rte_cpu_to_le_16(seid);
7484         cmd.destination = rte_cpu_to_le_16(dst_id);
7485
7486         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7487         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7488         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7489                          "rule_id = %u"
7490                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7491                          hw->aq.asq_last_status, resp->rule_id,
7492                          resp->mirror_rules_used, resp->mirror_rules_free);
7493         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7494
7495         return status;
7496 }
7497
7498 /**
7499  * i40e_aq_del_mirror_rule
7500  * @hw: pointer to the hardware structure
7501  * @seid: VEB seid to add mirror rule to
7502  * @entries: Buffer which contains the entities to be mirrored
7503  * @count: number of entities contained in the buffer
7504  * @rule_id:the rule_id of the rule to be delete
7505  *
7506  * Delete a mirror rule for a given veb.
7507  *
7508  **/
7509 static enum i40e_status_code
7510 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7511                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7512                 uint16_t count, uint16_t rule_id)
7513 {
7514         struct i40e_aq_desc desc;
7515         struct i40e_aqc_add_delete_mirror_rule cmd;
7516         uint16_t buff_len = 0;
7517         enum i40e_status_code status;
7518         void *buff = NULL;
7519
7520         i40e_fill_default_direct_cmd_desc(&desc,
7521                                           i40e_aqc_opc_delete_mirror_rule);
7522         memset(&cmd, 0, sizeof(cmd));
7523         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7524                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7525                                                           I40E_AQ_FLAG_RD));
7526                 cmd.num_entries = count;
7527                 buff_len = sizeof(uint16_t) * count;
7528                 desc.datalen = rte_cpu_to_le_16(buff_len);
7529                 buff = (void *)entries;
7530         } else
7531                 /* rule id is filled in destination field for deleting mirror rule */
7532                 cmd.destination = rte_cpu_to_le_16(rule_id);
7533
7534         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7535                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7536         cmd.seid = rte_cpu_to_le_16(seid);
7537
7538         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7539         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7540
7541         return status;
7542 }
7543
7544 /**
7545  * i40e_mirror_rule_set
7546  * @dev: pointer to the hardware structure
7547  * @mirror_conf: mirror rule info
7548  * @sw_id: mirror rule's sw_id
7549  * @on: enable/disable
7550  *
7551  * set a mirror rule.
7552  *
7553  **/
7554 static int
7555 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7556                         struct rte_eth_mirror_conf *mirror_conf,
7557                         uint8_t sw_id, uint8_t on)
7558 {
7559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7560         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7561         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7562         struct i40e_mirror_rule *parent = NULL;
7563         uint16_t seid, dst_seid, rule_id;
7564         uint16_t i, j = 0;
7565         int ret;
7566
7567         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7568
7569         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7570                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7571                         " without veb or vfs.");
7572                 return -ENOSYS;
7573         }
7574         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7575                 PMD_DRV_LOG(ERR, "mirror table is full.");
7576                 return -ENOSPC;
7577         }
7578         if (mirror_conf->dst_pool > pf->vf_num) {
7579                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7580                                  mirror_conf->dst_pool);
7581                 return -EINVAL;
7582         }
7583
7584         seid = pf->main_vsi->veb->seid;
7585
7586         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7587                 if (sw_id <= it->index) {
7588                         mirr_rule = it;
7589                         break;
7590                 }
7591                 parent = it;
7592         }
7593         if (mirr_rule && sw_id == mirr_rule->index) {
7594                 if (on) {
7595                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7596                         return -EEXIST;
7597                 } else {
7598                         ret = i40e_aq_del_mirror_rule(hw, seid,
7599                                         mirr_rule->rule_type,
7600                                         mirr_rule->entries,
7601                                         mirr_rule->num_entries, mirr_rule->id);
7602                         if (ret < 0) {
7603                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7604                                                    " ret = %d, aq_err = %d.",
7605                                                    ret, hw->aq.asq_last_status);
7606                                 return -ENOSYS;
7607                         }
7608                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7609                         rte_free(mirr_rule);
7610                         pf->nb_mirror_rule--;
7611                         return 0;
7612                 }
7613         } else if (!on) {
7614                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7615                 return -ENOENT;
7616         }
7617
7618         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7619                                 sizeof(struct i40e_mirror_rule) , 0);
7620         if (!mirr_rule) {
7621                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7622                 return I40E_ERR_NO_MEMORY;
7623         }
7624         switch (mirror_conf->rule_type) {
7625         case ETH_MIRROR_VLAN:
7626                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7627                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7628                                 mirr_rule->entries[j] =
7629                                         mirror_conf->vlan.vlan_id[i];
7630                                 j++;
7631                         }
7632                 }
7633                 if (j == 0) {
7634                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7635                         rte_free(mirr_rule);
7636                         return -EINVAL;
7637                 }
7638                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7639                 break;
7640         case ETH_MIRROR_VIRTUAL_POOL_UP:
7641         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7642                 /* check if the specified pool bit is out of range */
7643                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7644                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7645                         rte_free(mirr_rule);
7646                         return -EINVAL;
7647                 }
7648                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7649                         if (mirror_conf->pool_mask & (1ULL << i)) {
7650                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7651                                 j++;
7652                         }
7653                 }
7654                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7655                         /* add pf vsi to entries */
7656                         mirr_rule->entries[j] = pf->main_vsi_seid;
7657                         j++;
7658                 }
7659                 if (j == 0) {
7660                         PMD_DRV_LOG(ERR, "pool is not specified.");
7661                         rte_free(mirr_rule);
7662                         return -EINVAL;
7663                 }
7664                 /* egress and ingress in aq commands means from switch but not port */
7665                 mirr_rule->rule_type =
7666                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7667                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7668                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7669                 break;
7670         case ETH_MIRROR_UPLINK_PORT:
7671                 /* egress and ingress in aq commands means from switch but not port*/
7672                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7673                 break;
7674         case ETH_MIRROR_DOWNLINK_PORT:
7675                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7676                 break;
7677         default:
7678                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7679                         mirror_conf->rule_type);
7680                 rte_free(mirr_rule);
7681                 return -EINVAL;
7682         }
7683
7684         /* If the dst_pool is equal to vf_num, consider it as PF */
7685         if (mirror_conf->dst_pool == pf->vf_num)
7686                 dst_seid = pf->main_vsi_seid;
7687         else
7688                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7689
7690         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7691                                       mirr_rule->rule_type, mirr_rule->entries,
7692                                       j, &rule_id);
7693         if (ret < 0) {
7694                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7695                                    " ret = %d, aq_err = %d.",
7696                                    ret, hw->aq.asq_last_status);
7697                 rte_free(mirr_rule);
7698                 return -ENOSYS;
7699         }
7700
7701         mirr_rule->index = sw_id;
7702         mirr_rule->num_entries = j;
7703         mirr_rule->id = rule_id;
7704         mirr_rule->dst_vsi_seid = dst_seid;
7705
7706         if (parent)
7707                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7708         else
7709                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7710
7711         pf->nb_mirror_rule++;
7712         return 0;
7713 }
7714
7715 /**
7716  * i40e_mirror_rule_reset
7717  * @dev: pointer to the device
7718  * @sw_id: mirror rule's sw_id
7719  *
7720  * reset a mirror rule.
7721  *
7722  **/
7723 static int
7724 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7725 {
7726         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7728         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7729         uint16_t seid;
7730         int ret;
7731
7732         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7733
7734         seid = pf->main_vsi->veb->seid;
7735
7736         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7737                 if (sw_id == it->index) {
7738                         mirr_rule = it;
7739                         break;
7740                 }
7741         }
7742         if (mirr_rule) {
7743                 ret = i40e_aq_del_mirror_rule(hw, seid,
7744                                 mirr_rule->rule_type,
7745                                 mirr_rule->entries,
7746                                 mirr_rule->num_entries, mirr_rule->id);
7747                 if (ret < 0) {
7748                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7749                                            " status = %d, aq_err = %d.",
7750                                            ret, hw->aq.asq_last_status);
7751                         return -ENOSYS;
7752                 }
7753                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7754                 rte_free(mirr_rule);
7755                 pf->nb_mirror_rule--;
7756         } else {
7757                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7758                 return -ENOENT;
7759         }
7760         return 0;
7761 }
7762
7763 static int
7764 i40e_timesync_enable(struct rte_eth_dev *dev)
7765 {
7766         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7767         struct rte_eth_link *link = &dev->data->dev_link;
7768         uint32_t tsync_ctl_l;
7769         uint32_t tsync_ctl_h;
7770         uint32_t tsync_inc_l;
7771         uint32_t tsync_inc_h;
7772
7773         switch (link->link_speed) {
7774         case ETH_LINK_SPEED_40G:
7775                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7776                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7777                 break;
7778         case ETH_LINK_SPEED_10G:
7779                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7780                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7781                 break;
7782         case ETH_LINK_SPEED_1000:
7783                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7784                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7785                 break;
7786         default:
7787                 tsync_inc_l = 0x0;
7788                 tsync_inc_h = 0x0;
7789         }
7790
7791         /* Clear timesync registers. */
7792         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7793         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7794         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7795         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7796         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7797         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7798         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7799
7800         /* Set the timesync increment value. */
7801         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7802         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7803
7804         /* Enable timestamping of PTP packets. */
7805         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7806         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7807
7808         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7809         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7810         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7811
7812         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7813         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7814
7815         return 0;
7816 }
7817
7818 static int
7819 i40e_timesync_disable(struct rte_eth_dev *dev)
7820 {
7821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7822         uint32_t tsync_ctl_l;
7823         uint32_t tsync_ctl_h;
7824
7825         /* Disable timestamping of transmitted PTP packets. */
7826         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7827         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7828
7829         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7830         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7831
7832         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7833         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7834
7835         /* Set the timesync increment value. */
7836         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7837         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7838
7839         return 0;
7840 }
7841
7842 static int
7843 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7844                                 struct timespec *timestamp, uint32_t flags)
7845 {
7846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7847         uint32_t sync_status;
7848         uint32_t rx_stmpl;
7849         uint32_t rx_stmph;
7850         uint32_t index = flags & 0x03;
7851
7852         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7853         if ((sync_status & (1 << index)) == 0)
7854                 return -EINVAL;
7855
7856         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7857         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7858
7859         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7860         timestamp->tv_nsec = 0;
7861
7862         return  0;
7863 }
7864
7865 static int
7866 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7867                                 struct timespec *timestamp)
7868 {
7869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7870         uint32_t sync_status;
7871         uint32_t tx_stmpl;
7872         uint32_t tx_stmph;
7873
7874         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7875         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7876                 return -EINVAL;
7877
7878         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7879         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7880
7881         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7882         timestamp->tv_nsec = 0;
7883
7884         return  0;
7885 }
7886
7887 /*
7888  * i40e_parse_dcb_configure - parse dcb configure from user
7889  * @dev: the device being configured
7890  * @dcb_cfg: pointer of the result of parse
7891  * @*tc_map: bit map of enabled traffic classes
7892  *
7893  * Returns 0 on success, negative value on failure
7894  */
7895 static int
7896 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7897                          struct i40e_dcbx_config *dcb_cfg,
7898                          uint8_t *tc_map)
7899 {
7900         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7901         uint8_t i, tc_bw, bw_lf;
7902
7903         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7904
7905         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7906         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7907                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7908                 return -EINVAL;
7909         }
7910
7911         /* assume each tc has the same bw */
7912         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7913         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7914                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7915         /* to ensure the sum of tcbw is equal to 100 */
7916         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7917         for (i = 0; i < bw_lf; i++)
7918                 dcb_cfg->etscfg.tcbwtable[i]++;
7919
7920         /* assume each tc has the same Transmission Selection Algorithm */
7921         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7922                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7923
7924         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7925                 dcb_cfg->etscfg.prioritytable[i] =
7926                                 dcb_rx_conf->dcb_tc[i];
7927
7928         /* FW needs one App to configure HW */
7929         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7930         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7931         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7932         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7933
7934         if (dcb_rx_conf->nb_tcs == 0)
7935                 *tc_map = 1; /* tc0 only */
7936         else
7937                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7938
7939         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7940                 dcb_cfg->pfc.willing = 0;
7941                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7942                 dcb_cfg->pfc.pfcenable = *tc_map;
7943         }
7944         return 0;
7945 }
7946
7947 /*
7948  * i40e_vsi_get_bw_info - Query VSI BW Information
7949  * @vsi: the VSI being queried
7950  *
7951  * Returns 0 on success, negative value on failure
7952  */
7953 static enum i40e_status_code
7954 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7955 {
7956         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7957         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7958         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7959         enum i40e_status_code ret;
7960         int i;
7961         uint32_t tc_bw_max;
7962
7963         /* Get the VSI level BW configuration */
7964         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7965         if (ret) {
7966                 PMD_INIT_LOG(ERR,
7967                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
7968                          i40e_stat_str(hw, ret),
7969                          i40e_aq_str(hw, hw->aq.asq_last_status));
7970                 return ret;
7971         }
7972
7973         /* Get the VSI level BW configuration per TC */
7974         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7975                                                   NULL);
7976         if (ret) {
7977                 PMD_INIT_LOG(ERR,
7978                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7979                          i40e_stat_str(hw, ret),
7980                          i40e_aq_str(hw, hw->aq.asq_last_status));
7981                 return ret;
7982         }
7983
7984         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7985                 PMD_INIT_LOG(WARNING,
7986                          "Enabled TCs mismatch from querying VSI BW info"
7987                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7988                          bw_ets_config.tc_valid_bits);
7989                 /* Still continuing */
7990         }
7991
7992         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
7993         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
7994         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
7995                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
7996         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7997                 vsi->bw_info.bw_ets_share_credits[i] =
7998                                 bw_ets_config.share_credits[i];
7999                 vsi->bw_info.bw_ets_limit_credits[i] =
8000                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
8001                 /* 3 bits out of 4 for each TC */
8002                 vsi->bw_info.bw_ets_max_quanta[i] =
8003                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
8004                 PMD_INIT_LOG(DEBUG,
8005                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
8006                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
8007         }
8008
8009         return ret;
8010 }
8011
8012 static enum i40e_status_code
8013 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8014                               struct i40e_aqc_vsi_properties_data *info,
8015                               uint8_t enabled_tcmap)
8016 {
8017         enum i40e_status_code ret;
8018         int i, total_tc = 0;
8019         uint16_t qpnum_per_tc, bsf, qp_idx;
8020         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8021
8022         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8023         if (ret != I40E_SUCCESS)
8024                 return ret;
8025
8026         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8027                 if (enabled_tcmap & (1 << i))
8028                         total_tc++;
8029         }
8030         if (total_tc == 0)
8031                 total_tc = 1;
8032         vsi->enabled_tc = enabled_tcmap;
8033
8034         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8035         /* Number of queues per enabled TC */
8036         if (qpnum_per_tc == 0) {
8037                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8038                 return I40E_ERR_INVALID_QP_ID;
8039         }
8040         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8041                                 I40E_MAX_Q_PER_TC);
8042         bsf = rte_bsf32(qpnum_per_tc);
8043
8044         /**
8045          * Configure TC and queue mapping parameters, for enabled TC,
8046          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8047          * default queue will serve it.
8048          */
8049         qp_idx = 0;
8050         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8051                 if (vsi->enabled_tc & (1 << i)) {
8052                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8053                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8054                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8055                         qp_idx += qpnum_per_tc;
8056                 } else
8057                         info->tc_mapping[i] = 0;
8058         }
8059
8060         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8061         if (vsi->type == I40E_VSI_SRIOV) {
8062                 info->mapping_flags |=
8063                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8064                 for (i = 0; i < vsi->nb_qps; i++)
8065                         info->queue_mapping[i] =
8066                                 rte_cpu_to_le_16(vsi->base_queue + i);
8067         } else {
8068                 info->mapping_flags |=
8069                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8070                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8071         }
8072         info->valid_sections |=
8073                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8074
8075         return I40E_SUCCESS;
8076 }
8077
8078 /*
8079  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8080  * @vsi: VSI to be configured
8081  * @tc_map: enabled TC bitmap
8082  *
8083  * Returns 0 on success, negative value on failure
8084  */
8085 static enum i40e_status_code
8086 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8087 {
8088         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8089         struct i40e_vsi_context ctxt;
8090         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8091         enum i40e_status_code ret = I40E_SUCCESS;
8092         int i;
8093
8094         /* Check if enabled_tc is same as existing or new TCs */
8095         if (vsi->enabled_tc == tc_map)
8096                 return ret;
8097
8098         /* configure tc bandwidth */
8099         memset(&bw_data, 0, sizeof(bw_data));
8100         bw_data.tc_valid_bits = tc_map;
8101         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8102         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8103                 if (tc_map & BIT_ULL(i))
8104                         bw_data.tc_bw_credits[i] = 1;
8105         }
8106         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8107         if (ret) {
8108                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8109                         " per TC failed = %d",
8110                         hw->aq.asq_last_status);
8111                 goto out;
8112         }
8113         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8114                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8115
8116         /* Update Queue Pairs Mapping for currently enabled UPs */
8117         ctxt.seid = vsi->seid;
8118         ctxt.pf_num = hw->pf_id;
8119         ctxt.vf_num = 0;
8120         ctxt.uplink_seid = vsi->uplink_seid;
8121         ctxt.info = vsi->info;
8122         i40e_get_cap(hw);
8123         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8124         if (ret)
8125                 goto out;
8126
8127         /* Update the VSI after updating the VSI queue-mapping information */
8128         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8129         if (ret) {
8130                 PMD_INIT_LOG(ERR, "Failed to configure "
8131                             "TC queue mapping = %d",
8132                             hw->aq.asq_last_status);
8133                 goto out;
8134         }
8135         /* update the local VSI info with updated queue map */
8136         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8137                                         sizeof(vsi->info.tc_mapping));
8138         (void)rte_memcpy(&vsi->info.queue_mapping,
8139                         &ctxt.info.queue_mapping,
8140                 sizeof(vsi->info.queue_mapping));
8141         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8142         vsi->info.valid_sections = 0;
8143
8144         /* Update current VSI BW information */
8145         ret = i40e_vsi_get_bw_info(vsi);
8146         if (ret) {
8147                 PMD_INIT_LOG(ERR,
8148                          "Failed updating vsi bw info, err %s aq_err %s",
8149                          i40e_stat_str(hw, ret),
8150                          i40e_aq_str(hw, hw->aq.asq_last_status));
8151                 goto out;
8152         }
8153
8154         vsi->enabled_tc = tc_map;
8155
8156 out:
8157         return ret;
8158 }
8159
8160 /*
8161  * i40e_dcb_hw_configure - program the dcb setting to hw
8162  * @pf: pf the configuration is taken on
8163  * @new_cfg: new configuration
8164  * @tc_map: enabled TC bitmap
8165  *
8166  * Returns 0 on success, negative value on failure
8167  */
8168 static enum i40e_status_code
8169 i40e_dcb_hw_configure(struct i40e_pf *pf,
8170                       struct i40e_dcbx_config *new_cfg,
8171                       uint8_t tc_map)
8172 {
8173         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8174         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8175         struct i40e_vsi *main_vsi = pf->main_vsi;
8176         struct i40e_vsi_list *vsi_list;
8177         enum i40e_status_code ret;
8178         int i;
8179         uint32_t val;
8180
8181         /* Use the FW API if FW > v4.4*/
8182         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8183                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8184                                   " to configure DCB");
8185                 return I40E_ERR_FIRMWARE_API_VERSION;
8186         }
8187
8188         /* Check if need reconfiguration */
8189         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8190                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8191                 return I40E_SUCCESS;
8192         }
8193
8194         /* Copy the new config to the current config */
8195         *old_cfg = *new_cfg;
8196         old_cfg->etsrec = old_cfg->etscfg;
8197         ret = i40e_set_dcb_config(hw);
8198         if (ret) {
8199                 PMD_INIT_LOG(ERR,
8200                          "Set DCB Config failed, err %s aq_err %s\n",
8201                          i40e_stat_str(hw, ret),
8202                          i40e_aq_str(hw, hw->aq.asq_last_status));
8203                 return ret;
8204         }
8205         /* set receive Arbiter to RR mode and ETS scheme by default */
8206         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8207                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8208                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8209                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8210                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8211                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8212                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8213                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8214                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8215                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8216                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8217                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8218                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8219         }
8220         /* get local mib to check whether it is configured correctly */
8221         /* IEEE mode */
8222         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8223         /* Get Local DCB Config */
8224         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8225                                      &hw->local_dcbx_config);
8226
8227         /* Update each VSI */
8228         i40e_vsi_config_tc(main_vsi, tc_map);
8229         if (main_vsi->veb) {
8230                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8231                         /* Beside main VSI, only enable default
8232                          * TC for other VSIs
8233                          */
8234                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8235                                                 I40E_DEFAULT_TCMAP);
8236                         if (ret)
8237                                 PMD_INIT_LOG(WARNING,
8238                                          "Failed configuring TC for VSI seid=%d\n",
8239                                          vsi_list->vsi->seid);
8240                         /* continue */
8241                 }
8242         }
8243         return I40E_SUCCESS;
8244 }
8245
8246 /*
8247  * i40e_dcb_init_configure - initial dcb config
8248  * @dev: device being configured
8249  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8250  *
8251  * Returns 0 on success, negative value on failure
8252  */
8253 static int
8254 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8255 {
8256         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8257         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8258         int ret = 0;
8259
8260         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8261                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8262                 return -ENOTSUP;
8263         }
8264
8265         /* DCB initialization:
8266          * Update DCB configuration from the Firmware and configure
8267          * LLDP MIB change event.
8268          */
8269         if (sw_dcb == TRUE) {
8270                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8271                 if (ret != I40E_SUCCESS)
8272                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8273
8274                 ret = i40e_init_dcb(hw);
8275                 /* if sw_dcb, lldp agent is stopped, the return from
8276                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8277                  * adminq status.
8278                  */
8279                 if (ret != I40E_SUCCESS &&
8280                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8281                         memset(&hw->local_dcbx_config, 0,
8282                                 sizeof(struct i40e_dcbx_config));
8283                         /* set dcb default configuration */
8284                         hw->local_dcbx_config.etscfg.willing = 0;
8285                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8286                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8287                         hw->local_dcbx_config.etscfg.tsatable[0] =
8288                                                 I40E_IEEE_TSA_ETS;
8289                         hw->local_dcbx_config.etsrec =
8290                                 hw->local_dcbx_config.etscfg;
8291                         hw->local_dcbx_config.pfc.willing = 0;
8292                         hw->local_dcbx_config.pfc.pfccap =
8293                                                 I40E_MAX_TRAFFIC_CLASS;
8294                         /* FW needs one App to configure HW */
8295                         hw->local_dcbx_config.numapps = 1;
8296                         hw->local_dcbx_config.app[0].selector =
8297                                                 I40E_APP_SEL_ETHTYPE;
8298                         hw->local_dcbx_config.app[0].priority = 3;
8299                         hw->local_dcbx_config.app[0].protocolid =
8300                                                 I40E_APP_PROTOID_FCOE;
8301                         ret = i40e_set_dcb_config(hw);
8302                         if (ret) {
8303                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8304                                         " err = %d, aq_err = %d.", ret,
8305                                           hw->aq.asq_last_status);
8306                                 return -ENOSYS;
8307                         }
8308                 } else {
8309                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8310                                           " aq_err = %d.", ret,
8311                                           hw->aq.asq_last_status);
8312                         return -ENOTSUP;
8313                 }
8314         } else {
8315                 ret = i40e_aq_start_lldp(hw, NULL);
8316                 if (ret != I40E_SUCCESS)
8317                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8318
8319                 ret = i40e_init_dcb(hw);
8320                 if (!ret) {
8321                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8322                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8323                                                   " DCBX offload.");
8324                                 return -ENOTSUP;
8325                         }
8326                 } else {
8327                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8328                                           " aq_err = %d.", ret,
8329                                           hw->aq.asq_last_status);
8330                         return -ENOTSUP;
8331                 }
8332         }
8333         return 0;
8334 }
8335
8336 /*
8337  * i40e_dcb_setup - setup dcb related config
8338  * @dev: device being configured
8339  *
8340  * Returns 0 on success, negative value on failure
8341  */
8342 static int
8343 i40e_dcb_setup(struct rte_eth_dev *dev)
8344 {
8345         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8346         struct i40e_dcbx_config dcb_cfg;
8347         uint8_t tc_map = 0;
8348         int ret = 0;
8349
8350         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8351                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8352                 return -ENOTSUP;
8353         }
8354
8355         if (pf->vf_num != 0 ||
8356             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8357                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8358
8359         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8360         if (ret) {
8361                 PMD_INIT_LOG(ERR, "invalid dcb config");
8362                 return -EINVAL;
8363         }
8364         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8365         if (ret) {
8366                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8367                 return -ENOSYS;
8368         }
8369
8370         return 0;
8371 }
8372
8373 static int
8374 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8375                       struct rte_eth_dcb_info *dcb_info)
8376 {
8377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8379         struct i40e_vsi *vsi = pf->main_vsi;
8380         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8381         uint16_t bsf, tc_mapping;
8382         int i;
8383
8384         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8385                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8386         else
8387                 dcb_info->nb_tcs = 1;
8388         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8389                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8390         for (i = 0; i < dcb_info->nb_tcs; i++)
8391                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8392
8393         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8394                 if (vsi->enabled_tc & (1 << i)) {
8395                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8396                         /* only main vsi support multi TCs */
8397                         dcb_info->tc_queue.tc_rxq[0][i].base =
8398                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8399                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8400                         dcb_info->tc_queue.tc_txq[0][i].base =
8401                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8402                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8403                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8404                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8405                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8406                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8407                 }
8408         }
8409
8410         return 0;
8411 }
8412
8413 static int
8414 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8415 {
8416         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8417         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8418         uint16_t interval =
8419                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8420         uint16_t msix_intr;
8421
8422         msix_intr = intr_handle->intr_vec[queue_id];
8423         if (msix_intr == I40E_MISC_VEC_ID)
8424                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8425                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8426                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8427                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8428                                (interval <<
8429                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8430         else
8431                 I40E_WRITE_REG(hw,
8432                                I40E_PFINT_DYN_CTLN(msix_intr -
8433                                                    I40E_RX_VEC_START),
8434                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8435                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8436                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8437                                (interval <<
8438                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8439
8440         I40E_WRITE_FLUSH(hw);
8441         rte_intr_enable(&dev->pci_dev->intr_handle);
8442
8443         return 0;
8444 }
8445
8446 static int
8447 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8448 {
8449         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8451         uint16_t msix_intr;
8452
8453         msix_intr = intr_handle->intr_vec[queue_id];
8454         if (msix_intr == I40E_MISC_VEC_ID)
8455                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8456         else
8457                 I40E_WRITE_REG(hw,
8458                                I40E_PFINT_DYN_CTLN(msix_intr -
8459                                                    I40E_RX_VEC_START),
8460                                0);
8461         I40E_WRITE_FLUSH(hw);
8462
8463         return 0;
8464 }