drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  49
  50 #define I40E_CLEAR_PXE_WAIT_MS     200
  51 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  52 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  53
  54 /* Maximun number of capability elements */
  55 #define I40E_MAX_CAP_ELE_NUM       128
  56
  57 /* Wait count and interval */
  58 #define I40E_CHK_Q_ENA_COUNT       1000
  59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  60
  61 /* Maximun number of VSI */
  62 #define I40E_MAX_NUM_VSIS          (384UL)
  63
  64 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  65
  66 /* Flow control default timer */
  67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  68
  69 /* Flow control enable fwd bit */
  70 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  71
  72 /* Receive Packet Buffer size */
  73 #define I40E_RXPBSIZE (968 * 1024)
  74
  75 /* Kilobytes shift */
  76 #define I40E_KILOSHIFT 10
  77
  78 /* Flow control default high water */
  79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Flow control default low water */
  82 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  83
  84 /* Receive Average Packet Size in Byte*/
  85 #define I40E_PACKET_AVERAGE_SIZE 128
  86
  87 /* Mask of PF interrupt causes */
  88 #define I40E_PFINT_ICR0_ENA_MASK ( \
  89                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  93                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  94                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  98
  99 #define I40E_FLOW_TYPES ( \
 100         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 105         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 110         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 111
 112 /* Additional timesync values. */
 113 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 114 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 115 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 116 #define I40E_PRTTSYN_TSYNENA     0x80000000
 117 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 118 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 119
 120 /**
 121  * Below are values for writing un-exposed registers suggested
 122  * by silicon experts
 123  */
 124 /* Destination MAC address */
 125 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 126 /* Source MAC address */
 127 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 129 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 131 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 132 /* Single VLAN tag in the inner L2 header */
 133 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 134 /* Source IPv4 address */
 135 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 136 /* Destination IPv4 address */
 137 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 138 /* Source IPv4 address for X722 */
 139 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 140 /* Destination IPv4 address for X722 */
 141 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 142 /* IPv4 Protocol for X722 */
 143 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 144 /* IPv4 Time to Live for X722 */
 145 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 146 /* IPv4 Type of Service (TOS) */
 147 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 148 /* IPv4 Protocol */
 149 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 150 /* IPv4 Time to Live */
 151 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 152 /* Source IPv6 address */
 153 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 154 /* Destination IPv6 address */
 155 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 156 /* IPv6 Traffic Class (TC) */
 157 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 158 /* IPv6 Next Header */
 159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 160 /* IPv6 Hop Limit */
 161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 162 /* Source L4 port */
 163 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 164 /* Destination L4 port */
 165 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 166 /* SCTP verification tag */
 167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 170 /* Source port of tunneling UDP */
 171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 172 /* Destination port of tunneling UDP */
 173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 174 /* UDP Tunneling ID, NVGRE/GRE key */
 175 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 176 /* Last ether type */
 177 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 178 /* Tunneling outer destination IPv4 address */
 179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 180 /* Tunneling outer destination IPv6 address */
 181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 182 /* 1st word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 184 /* 2nd word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 186 /* 3rd word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 188 /* 4th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 190 /* 5th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 192 /* 6th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 194 /* 7th word of flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 196 /* 8th word of flex payload */
 197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 198 /* all 8 words flex payload */
 199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 200 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 201
 202 #define I40E_TRANSLATE_INSET 0
 203 #define I40E_TRANSLATE_REG   1
 204
 205 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 206 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 207 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 208 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 210 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 211
 212 /* PCI offset for querying capability */
 213 #define PCI_DEV_CAP_REG            0xA4
 214 /* PCI offset for enabling/disabling Extended Tag */
 215 #define PCI_DEV_CTRL_REG           0xA8
 216 /* Bit mask of Extended Tag capability */
 217 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 218 /* Bit shift of Extended Tag enable/disable */
 219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 220 /* Bit mask of Extended Tag enable/disable */
 221 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 222
 223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 225 static int i40e_dev_configure(struct rte_eth_dev *dev);
 226 static int i40e_dev_start(struct rte_eth_dev *dev);
 227 static void i40e_dev_stop(struct rte_eth_dev *dev);
 228 static void i40e_dev_close(struct rte_eth_dev *dev);
 229 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_stats *stats);
 238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 239                                struct rte_eth_xstat *xstats, unsigned n);
 240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 241                                      struct rte_eth_xstat_name *xstats_names,
 242                                      unsigned limit);
 243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 247                              struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct rte_ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 309                                              struct i40e_macvlan_filter *mv_f,
 310                                              int num,
 311                                              uint16_t vlan);
 312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 314                                     struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 316                                       struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 322 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 326                                 enum rte_filter_type filter_type,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                   struct rte_eth_dcb_info *dcb_info);
 331 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 332 static void i40e_configure_registers(struct i40e_hw *hw);
 333 static void i40e_hw_init(struct rte_eth_dev *dev);
 334 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 335 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 336                                                      uint16_t seid,
 337                                                      uint16_t rule_type,
 338                                                      uint16_t *entries,
 339                                                      uint16_t count,
 340                                                      uint16_t rule_id);
 341 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 342                         struct rte_eth_mirror_conf *mirror_conf,
 343                         uint8_t sw_id, uint8_t on);
 344 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 345
 346 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 347 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 348 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp,
 350                                            uint32_t flags);
 351 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 352                                            struct timespec *timestamp);
 353 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 354
 355 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 356
 357 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 358                                    struct timespec *timestamp);
 359 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 360                                     const struct timespec *timestamp);
 361
 362 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 363                                          uint16_t queue_id);
 364 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 365                                           uint16_t queue_id);
 366
 367 static int i40e_get_regs(struct rte_eth_dev *dev,
 368                          struct rte_dev_reg_info *regs);
 369
 370 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 371
 372 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 373                            struct rte_dev_eeprom_info *eeprom);
 374
 375 static int i40e_get_module_info(struct rte_eth_dev *dev,
 376                                 struct rte_eth_dev_module_info *modinfo);
 377 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 378                                   struct rte_dev_eeprom_info *info);
 379
 380 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 381                                       struct rte_ether_addr *mac_addr);
 382
 383 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 384
 385 static int i40e_ethertype_filter_convert(
 386         const struct rte_eth_ethertype_filter *input,
 387         struct i40e_ethertype_filter *filter);
 388 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 389                                    struct i40e_ethertype_filter *filter);
 390
 391 static int i40e_tunnel_filter_convert(
 392         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 393         struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 395                                 struct i40e_tunnel_filter *tunnel_filter);
 396 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 397
 398 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 399 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 400 static void i40e_filter_restore(struct i40e_pf *pf);
 401 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 402 static int i40e_pf_config_rss(struct i40e_pf *pf);
 403
 404 static const char *const valid_keys[] = {
 405         ETH_I40E_FLOATING_VEB_ARG,
 406         ETH_I40E_FLOATING_VEB_LIST_ARG,
 407         ETH_I40E_SUPPORT_MULTI_DRIVER,
 408         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 409         ETH_I40E_USE_LATEST_VEC,
 410         ETH_I40E_VF_MSG_CFG,
 411         NULL};
 412
 413 static const struct rte_pci_id pci_id_i40e_map[] = {
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 440         { .vendor_id = 0, /* sentinel */ },
 441 };
 442
 443 static const struct eth_dev_ops i40e_eth_dev_ops = {
 444         .dev_configure                = i40e_dev_configure,
 445         .dev_start                    = i40e_dev_start,
 446         .dev_stop                     = i40e_dev_stop,
 447         .dev_close                    = i40e_dev_close,
 448         .dev_reset                    = i40e_dev_reset,
 449         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 450         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 451         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 452         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 453         .dev_set_link_up              = i40e_dev_set_link_up,
 454         .dev_set_link_down            = i40e_dev_set_link_down,
 455         .link_update                  = i40e_dev_link_update,
 456         .stats_get                    = i40e_dev_stats_get,
 457         .xstats_get                   = i40e_dev_xstats_get,
 458         .xstats_get_names             = i40e_dev_xstats_get_names,
 459         .stats_reset                  = i40e_dev_stats_reset,
 460         .xstats_reset                 = i40e_dev_stats_reset,
 461         .fw_version_get               = i40e_fw_version_get,
 462         .dev_infos_get                = i40e_dev_info_get,
 463         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 464         .vlan_filter_set              = i40e_vlan_filter_set,
 465         .vlan_tpid_set                = i40e_vlan_tpid_set,
 466         .vlan_offload_set             = i40e_vlan_offload_set,
 467         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 468         .vlan_pvid_set                = i40e_vlan_pvid_set,
 469         .rx_queue_start               = i40e_dev_rx_queue_start,
 470         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 471         .tx_queue_start               = i40e_dev_tx_queue_start,
 472         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 473         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 474         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 475         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 476         .rx_queue_release             = i40e_dev_rx_queue_release,
 477         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 478         .tx_queue_release             = i40e_dev_tx_queue_release,
 479         .dev_led_on                   = i40e_dev_led_on,
 480         .dev_led_off                  = i40e_dev_led_off,
 481         .flow_ctrl_get                = i40e_flow_ctrl_get,
 482         .flow_ctrl_set                = i40e_flow_ctrl_set,
 483         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 484         .mac_addr_add                 = i40e_macaddr_add,
 485         .mac_addr_remove              = i40e_macaddr_remove,
 486         .reta_update                  = i40e_dev_rss_reta_update,
 487         .reta_query                   = i40e_dev_rss_reta_query,
 488         .rss_hash_update              = i40e_dev_rss_hash_update,
 489         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 490         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 491         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 492         .filter_ctrl                  = i40e_dev_filter_ctrl,
 493         .rxq_info_get                 = i40e_rxq_info_get,
 494         .txq_info_get                 = i40e_txq_info_get,
 495         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 496         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 497         .mirror_rule_set              = i40e_mirror_rule_set,
 498         .mirror_rule_reset            = i40e_mirror_rule_reset,
 499         .timesync_enable              = i40e_timesync_enable,
 500         .timesync_disable             = i40e_timesync_disable,
 501         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 502         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 503         .get_dcb_info                 = i40e_dev_get_dcb_info,
 504         .timesync_adjust_time         = i40e_timesync_adjust_time,
 505         .timesync_read_time           = i40e_timesync_read_time,
 506         .timesync_write_time          = i40e_timesync_write_time,
 507         .get_reg                      = i40e_get_regs,
 508         .get_eeprom_length            = i40e_get_eeprom_length,
 509         .get_eeprom                   = i40e_get_eeprom,
 510         .get_module_info              = i40e_get_module_info,
 511         .get_module_eeprom            = i40e_get_module_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514         .tm_ops_get                   = i40e_tm_ops_get,
 515         .tx_done_cleanup              = i40e_tx_done_cleanup,
 516 };
 517
 518 /* store statistics names and its offset in stats structure */
 519 struct rte_i40e_xstats_name_off {
 520         char name[RTE_ETH_XSTATS_NAME_SIZE];
 521         unsigned offset;
 522 };
 523
 524 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 525         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 526         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 527         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 528         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 529         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 530                 rx_unknown_protocol)},
 531         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 532         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 533         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 534         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 535 };
 536
 537 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 538                 sizeof(rte_i40e_stats_strings[0]))
 539
 540 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 541         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 542                 tx_dropped_link_down)},
 543         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 544         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 545                 illegal_bytes)},
 546         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 547         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 548                 mac_local_faults)},
 549         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_remote_faults)},
 551         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_length_errors)},
 553         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 554         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 555         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 556         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 557         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 558         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_127)},
 560         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_255)},
 562         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_511)},
 564         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_1023)},
 566         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1522)},
 568         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_big)},
 570         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 571                 rx_undersize)},
 572         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_oversize)},
 574         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 575                 mac_short_packet_dropped)},
 576         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 577                 rx_fragments)},
 578         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 579         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 580         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_127)},
 582         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_255)},
 584         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_511)},
 586         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_1023)},
 588         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1522)},
 590         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_big)},
 592         {"rx_flow_director_atr_match_packets",
 593                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 594         {"rx_flow_director_sb_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 596         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 597                 tx_lpi_status)},
 598         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 rx_lpi_status)},
 600         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 601                 tx_lpi_count)},
 602         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 rx_lpi_count)},
 604 };
 605
 606 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 607                 sizeof(rte_i40e_hw_port_strings[0]))
 608
 609 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 610         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 611                 priority_xon_rx)},
 612         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xoff_rx)},
 614 };
 615
 616 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 617                 sizeof(rte_i40e_rxq_prio_strings[0]))
 618
 619 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 620         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xon_tx)},
 622         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xoff_tx)},
 624         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_2_xoff)},
 626 };
 627
 628 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 629                 sizeof(rte_i40e_txq_prio_strings[0]))
 630
 631 static int
 632 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 633         struct rte_pci_device *pci_dev)
 634 {
 635         char name[RTE_ETH_NAME_MAX_LEN];
 636         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 637         int i, retval;
 638
 639         if (pci_dev->device.devargs) {
 640                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 641                                 &eth_da);
 642                 if (retval)
 643                         return retval;
 644         }
 645
 646         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 647                 sizeof(struct i40e_adapter),
 648                 eth_dev_pci_specific_init, pci_dev,
 649                 eth_i40e_dev_init, NULL);
 650
 651         if (retval || eth_da.nb_representor_ports < 1)
 652                 return retval;
 653
 654         /* probe VF representor ports */
 655         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 656                 pci_dev->device.name);
 657
 658         if (pf_ethdev == NULL)
 659                 return -ENODEV;
 660
 661         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 662                 struct i40e_vf_representor representor = {
 663                         .vf_id = eth_da.representor_ports[i],
 664                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 665                                 pf_ethdev->data->dev_private)->switch_domain_id,
 666                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 667                                 pf_ethdev->data->dev_private)
 668                 };
 669
 670                 /* representor port net_bdf_port */
 671                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 672                         pci_dev->device.name, eth_da.representor_ports[i]);
 673
 674                 retval = rte_eth_dev_create(&pci_dev->device, name,
 675                         sizeof(struct i40e_vf_representor), NULL, NULL,
 676                         i40e_vf_representor_init, &representor);
 677
 678                 if (retval)
 679                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 680                                 "representor %s.", name);
 681         }
 682
 683         return 0;
 684 }
 685
 686 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 687 {
 688         struct rte_eth_dev *ethdev;
 689
 690         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 691         if (!ethdev)
 692                 return 0;
 693
 694         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 695                 return rte_eth_dev_pci_generic_remove(pci_dev,
 696                                         i40e_vf_representor_uninit);
 697         else
 698                 return rte_eth_dev_pci_generic_remove(pci_dev,
 699                                                 eth_i40e_dev_uninit);
 700 }
 701
 702 static struct rte_pci_driver rte_i40e_pmd = {
 703         .id_table = pci_id_i40e_map,
 704         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 705         .probe = eth_i40e_pci_probe,
 706         .remove = eth_i40e_pci_remove,
 707 };
 708
 709 static inline void
 710 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 711                          uint32_t reg_val)
 712 {
 713         uint32_t ori_reg_val;
 714         struct rte_eth_dev *dev;
 715
 716         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 717         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 718         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 719         if (ori_reg_val != reg_val)
 720                 PMD_DRV_LOG(WARNING,
 721                             "i40e device %s changed global register [0x%08x]."
 722                             " original: 0x%08x, new: 0x%08x",
 723                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 724 }
 725
 726 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 727 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 728 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 729
 730 #ifndef I40E_GLQF_ORT
 731 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 732 #endif
 733 #ifndef I40E_GLQF_PIT
 734 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 735 #endif
 736 #ifndef I40E_GLQF_L3_MAP
 737 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 738 #endif
 739
 740 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 741 {
 742         /*
 743          * Initialize registers for parsing packet type of QinQ
 744          * This should be removed from code once proper
 745          * configuration API is added to avoid configuration conflicts
 746          * between ports of the same device.
 747          */
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 750 }
 751
 752 static inline void i40e_config_automask(struct i40e_pf *pf)
 753 {
 754         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 755         uint32_t val;
 756
 757         /* INTENA flag is not auto-cleared for interrupt */
 758         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 759         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 760                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 761
 762         /* If support multi-driver, PF will use INT0. */
 763         if (!pf->support_multi_driver)
 764                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 765
 766         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 767 }
 768
 769 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 770
 771 /*
 772  * Add a ethertype filter to drop all flow control frames transmitted
 773  * from VSIs.
 774 */
 775 static void
 776 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 777 {
 778         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 779         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 780                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 781                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 782         int ret;
 783
 784         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 785                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 786                                 pf->main_vsi_seid, 0,
 787                                 TRUE, NULL, NULL);
 788         if (ret)
 789                 PMD_INIT_LOG(ERR,
 790                         "Failed to add filter to drop flow control frames from VSIs.");
 791 }
 792
 793 static int
 794 floating_veb_list_handler(__rte_unused const char *key,
 795                           const char *floating_veb_value,
 796                           void *opaque)
 797 {
 798         int idx = 0;
 799         unsigned int count = 0;
 800         char *end = NULL;
 801         int min, max;
 802         bool *vf_floating_veb = opaque;
 803
 804         while (isblank(*floating_veb_value))
 805                 floating_veb_value++;
 806
 807         /* Reset floating VEB configuration for VFs */
 808         for (idx = 0; idx < I40E_MAX_VF; idx++)
 809                 vf_floating_veb[idx] = false;
 810
 811         min = I40E_MAX_VF;
 812         do {
 813                 while (isblank(*floating_veb_value))
 814                         floating_veb_value++;
 815                 if (*floating_veb_value == '\0')
 816                         return -1;
 817                 errno = 0;
 818                 idx = strtoul(floating_veb_value, &end, 10);
 819                 if (errno || end == NULL)
 820                         return -1;
 821                 while (isblank(*end))
 822                         end++;
 823                 if (*end == '-') {
 824                         min = idx;
 825                 } else if ((*end == ';') || (*end == '\0')) {
 826                         max = idx;
 827                         if (min == I40E_MAX_VF)
 828                                 min = idx;
 829                         if (max >= I40E_MAX_VF)
 830                                 max = I40E_MAX_VF - 1;
 831                         for (idx = min; idx <= max; idx++) {
 832                                 vf_floating_veb[idx] = true;
 833                                 count++;
 834                         }
 835                         min = I40E_MAX_VF;
 836                 } else {
 837                         return -1;
 838                 }
 839                 floating_veb_value = end + 1;
 840         } while (*end != '\0');
 841
 842         if (count == 0)
 843                 return -1;
 844
 845         return 0;
 846 }
 847
 848 static void
 849 config_vf_floating_veb(struct rte_devargs *devargs,
 850                        uint16_t floating_veb,
 851                        bool *vf_floating_veb)
 852 {
 853         struct rte_kvargs *kvlist;
 854         int i;
 855         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 856
 857         if (!floating_veb)
 858                 return;
 859         /* All the VFs attach to the floating VEB by default
 860          * when the floating VEB is enabled.
 861          */
 862         for (i = 0; i < I40E_MAX_VF; i++)
 863                 vf_floating_veb[i] = true;
 864
 865         if (devargs == NULL)
 866                 return;
 867
 868         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 869         if (kvlist == NULL)
 870                 return;
 871
 872         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 873                 rte_kvargs_free(kvlist);
 874                 return;
 875         }
 876         /* When the floating_veb_list parameter exists, all the VFs
 877          * will attach to the legacy VEB firstly, then configure VFs
 878          * to the floating VEB according to the floating_veb_list.
 879          */
 880         if (rte_kvargs_process(kvlist, floating_veb_list,
 881                                floating_veb_list_handler,
 882                                vf_floating_veb) < 0) {
 883                 rte_kvargs_free(kvlist);
 884                 return;
 885         }
 886         rte_kvargs_free(kvlist);
 887 }
 888
 889 static int
 890 i40e_check_floating_handler(__rte_unused const char *key,
 891                             const char *value,
 892                             __rte_unused void *opaque)
 893 {
 894         if (strcmp(value, "1"))
 895                 return -1;
 896
 897         return 0;
 898 }
 899
 900 static int
 901 is_floating_veb_supported(struct rte_devargs *devargs)
 902 {
 903         struct rte_kvargs *kvlist;
 904         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 905
 906         if (devargs == NULL)
 907                 return 0;
 908
 909         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 910         if (kvlist == NULL)
 911                 return 0;
 912
 913         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 914                 rte_kvargs_free(kvlist);
 915                 return 0;
 916         }
 917         /* Floating VEB is enabled when there's key-value:
 918          * enable_floating_veb=1
 919          */
 920         if (rte_kvargs_process(kvlist, floating_veb_key,
 921                                i40e_check_floating_handler, NULL) < 0) {
 922                 rte_kvargs_free(kvlist);
 923                 return 0;
 924         }
 925         rte_kvargs_free(kvlist);
 926
 927         return 1;
 928 }
 929
 930 static void
 931 config_floating_veb(struct rte_eth_dev *dev)
 932 {
 933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 934         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 936
 937         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 938
 939         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 940                 pf->floating_veb =
 941                         is_floating_veb_supported(pci_dev->device.devargs);
 942                 config_vf_floating_veb(pci_dev->device.devargs,
 943                                        pf->floating_veb,
 944                                        pf->floating_veb_list);
 945         } else {
 946                 pf->floating_veb = false;
 947         }
 948 }
 949
 950 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 951 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 952
 953 static int
 954 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 955 {
 956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 957         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 958         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 959         int ret;
 960
 961         struct rte_hash_parameters ethertype_hash_params = {
 962                 .name = ethertype_hash_name,
 963                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 964                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 965                 .hash_func = rte_hash_crc,
 966                 .hash_func_init_val = 0,
 967                 .socket_id = rte_socket_id(),
 968         };
 969
 970         /* Initialize ethertype filter rule list and hash */
 971         TAILQ_INIT(&ethertype_rule->ethertype_list);
 972         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 973                  "ethertype_%s", dev->device->name);
 974         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 975         if (!ethertype_rule->hash_table) {
 976                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 977                 return -EINVAL;
 978         }
 979         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 980                                        sizeof(struct i40e_ethertype_filter *) *
 981                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 982                                        0);
 983         if (!ethertype_rule->hash_map) {
 984                 PMD_INIT_LOG(ERR,
 985                              "Failed to allocate memory for ethertype hash map!");
 986                 ret = -ENOMEM;
 987                 goto err_ethertype_hash_map_alloc;
 988         }
 989
 990         return 0;
 991
 992 err_ethertype_hash_map_alloc:
 993         rte_hash_free(ethertype_rule->hash_table);
 994
 995         return ret;
 996 }
 997
 998 static int
 999 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 {
1001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1003         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1004         int ret;
1005
1006         struct rte_hash_parameters tunnel_hash_params = {
1007                 .name = tunnel_hash_name,
1008                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1009                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1010                 .hash_func = rte_hash_crc,
1011                 .hash_func_init_val = 0,
1012                 .socket_id = rte_socket_id(),
1013         };
1014
1015         /* Initialize tunnel filter rule list and hash */
1016         TAILQ_INIT(&tunnel_rule->tunnel_list);
1017         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1018                  "tunnel_%s", dev->device->name);
1019         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1020         if (!tunnel_rule->hash_table) {
1021                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1022                 return -EINVAL;
1023         }
1024         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1025                                     sizeof(struct i40e_tunnel_filter *) *
1026                                     I40E_MAX_TUNNEL_FILTER_NUM,
1027                                     0);
1028         if (!tunnel_rule->hash_map) {
1029                 PMD_INIT_LOG(ERR,
1030                              "Failed to allocate memory for tunnel hash map!");
1031                 ret = -ENOMEM;
1032                 goto err_tunnel_hash_map_alloc;
1033         }
1034
1035         return 0;
1036
1037 err_tunnel_hash_map_alloc:
1038         rte_hash_free(tunnel_rule->hash_table);
1039
1040         return ret;
1041 }
1042
1043 static int
1044 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 {
1046         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1048         struct i40e_fdir_info *fdir_info = &pf->fdir;
1049         char fdir_hash_name[RTE_HASH_NAMESIZE];
1050         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1051         uint32_t best = hw->func_caps.fd_filters_best_effort;
1052         struct rte_bitmap *bmp = NULL;
1053         uint32_t bmp_size;
1054         void *mem = NULL;
1055         uint32_t i = 0;
1056         int ret;
1057
1058         struct rte_hash_parameters fdir_hash_params = {
1059                 .name = fdir_hash_name,
1060                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1061                 .key_len = sizeof(struct i40e_fdir_input),
1062                 .hash_func = rte_hash_crc,
1063                 .hash_func_init_val = 0,
1064                 .socket_id = rte_socket_id(),
1065         };
1066
1067         /* Initialize flow director filter rule list and hash */
1068         TAILQ_INIT(&fdir_info->fdir_list);
1069         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1070                  "fdir_%s", dev->device->name);
1071         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1072         if (!fdir_info->hash_table) {
1073                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1074                 return -EINVAL;
1075         }
1076
1077         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078                                           sizeof(struct i40e_fdir_filter *) *
1079                                           I40E_MAX_FDIR_FILTER_NUM,
1080                                           0);
1081         if (!fdir_info->hash_map) {
1082                 PMD_INIT_LOG(ERR,
1083                              "Failed to allocate memory for fdir hash map!");
1084                 ret = -ENOMEM;
1085                 goto err_fdir_hash_map_alloc;
1086         }
1087
1088         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1089                         sizeof(struct i40e_fdir_filter) *
1090                         I40E_MAX_FDIR_FILTER_NUM,
1091                         0);
1092
1093         if (!fdir_info->fdir_filter_array) {
1094                 PMD_INIT_LOG(ERR,
1095                              "Failed to allocate memory for fdir filter array!");
1096                 ret = -ENOMEM;
1097                 goto err_fdir_filter_array_alloc;
1098         }
1099
1100         fdir_info->fdir_space_size = alloc + best;
1101         fdir_info->fdir_actual_cnt = 0;
1102         fdir_info->fdir_guarantee_total_space = alloc;
1103         fdir_info->fdir_guarantee_free_space =
1104                 fdir_info->fdir_guarantee_total_space;
1105
1106         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1107
1108         fdir_info->fdir_flow_pool.pool =
1109                         rte_zmalloc("i40e_fdir_entry",
1110                                 sizeof(struct i40e_fdir_entry) *
1111                                 fdir_info->fdir_space_size,
1112                                 0);
1113
1114         if (!fdir_info->fdir_flow_pool.pool) {
1115                 PMD_INIT_LOG(ERR,
1116                              "Failed to allocate memory for bitmap flow!");
1117                 ret = -ENOMEM;
1118                 goto err_fdir_bitmap_flow_alloc;
1119         }
1120
1121         for (i = 0; i < fdir_info->fdir_space_size; i++)
1122                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1123
1124         bmp_size =
1125                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1126         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1127         if (mem == NULL) {
1128                 PMD_INIT_LOG(ERR,
1129                              "Failed to allocate memory for fdir bitmap!");
1130                 ret = -ENOMEM;
1131                 goto err_fdir_mem_alloc;
1132         }
1133         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1134         if (bmp == NULL) {
1135                 PMD_INIT_LOG(ERR,
1136                              "Failed to initialization fdir bitmap!");
1137                 ret = -ENOMEM;
1138                 goto err_fdir_bmp_alloc;
1139         }
1140         for (i = 0; i < fdir_info->fdir_space_size; i++)
1141                 rte_bitmap_set(bmp, i);
1142
1143         fdir_info->fdir_flow_pool.bitmap = bmp;
1144
1145         return 0;
1146
1147 err_fdir_bmp_alloc:
1148         rte_free(mem);
1149 err_fdir_mem_alloc:
1150         rte_free(fdir_info->fdir_flow_pool.pool);
1151 err_fdir_bitmap_flow_alloc:
1152         rte_free(fdir_info->fdir_filter_array);
1153 err_fdir_filter_array_alloc:
1154         rte_free(fdir_info->hash_map);
1155 err_fdir_hash_map_alloc:
1156         rte_hash_free(fdir_info->hash_table);
1157
1158         return ret;
1159 }
1160
1161 static void
1162 i40e_init_customized_info(struct i40e_pf *pf)
1163 {
1164         int i;
1165
1166         /* Initialize customized pctype */
1167         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1168                 pf->customized_pctype[i].index = i;
1169                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1170                 pf->customized_pctype[i].valid = false;
1171         }
1172
1173         pf->gtp_support = false;
1174         pf->esp_support = false;
1175 }
1176
1177 static void
1178 i40e_init_filter_invalidation(struct i40e_pf *pf)
1179 {
1180         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1181         struct i40e_fdir_info *fdir_info = &pf->fdir;
1182         uint32_t glqf_ctl_reg = 0;
1183
1184         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1185         if (!pf->support_multi_driver) {
1186                 fdir_info->fdir_invalprio = 1;
1187                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1188                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1189                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1190         } else {
1191                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1192                         fdir_info->fdir_invalprio = 1;
1193                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1194                 } else {
1195                         fdir_info->fdir_invalprio = 0;
1196                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1197                 }
1198         }
1199 }
1200
1201 void
1202 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1203 {
1204         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1206         struct i40e_queue_regions *info = &pf->queue_region;
1207         uint16_t i;
1208
1209         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1210                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1211
1212         memset(info, 0, sizeof(struct i40e_queue_regions));
1213 }
1214
1215 static int
1216 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1217                                const char *value,
1218                                void *opaque)
1219 {
1220         struct i40e_pf *pf;
1221         unsigned long support_multi_driver;
1222         char *end;
1223
1224         pf = (struct i40e_pf *)opaque;
1225
1226         errno = 0;
1227         support_multi_driver = strtoul(value, &end, 10);
1228         if (errno != 0 || end == value || *end != 0) {
1229                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1230                 return -(EINVAL);
1231         }
1232
1233         if (support_multi_driver == 1 || support_multi_driver == 0)
1234                 pf->support_multi_driver = (bool)support_multi_driver;
1235         else
1236                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1237                             "enable global configuration by default."
1238                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1239         return 0;
1240 }
1241
1242 static int
1243 i40e_support_multi_driver(struct rte_eth_dev *dev)
1244 {
1245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1246         struct rte_kvargs *kvlist;
1247         int kvargs_count;
1248
1249         /* Enable global configuration by default */
1250         pf->support_multi_driver = false;
1251
1252         if (!dev->device->devargs)
1253                 return 0;
1254
1255         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1256         if (!kvlist)
1257                 return -EINVAL;
1258
1259         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1260         if (!kvargs_count) {
1261                 rte_kvargs_free(kvlist);
1262                 return 0;
1263         }
1264
1265         if (kvargs_count > 1)
1266                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1267                             "the first invalid or last valid one is used !",
1268                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1269
1270         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1271                                i40e_parse_multi_drv_handler, pf) < 0) {
1272                 rte_kvargs_free(kvlist);
1273                 return -EINVAL;
1274         }
1275
1276         rte_kvargs_free(kvlist);
1277         return 0;
1278 }
1279
1280 static int
1281 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1282                                     uint32_t reg_addr, uint64_t reg_val,
1283                                     struct i40e_asq_cmd_details *cmd_details)
1284 {
1285         uint64_t ori_reg_val;
1286         struct rte_eth_dev *dev;
1287         int ret;
1288
1289         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1290         if (ret != I40E_SUCCESS) {
1291                 PMD_DRV_LOG(ERR,
1292                             "Fail to debug read from 0x%08x",
1293                             reg_addr);
1294                 return -EIO;
1295         }
1296         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1297
1298         if (ori_reg_val != reg_val)
1299                 PMD_DRV_LOG(WARNING,
1300                             "i40e device %s changed global register [0x%08x]."
1301                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1302                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1303
1304         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1305 }
1306
1307 static int
1308 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1309                                 const char *value,
1310                                 void *opaque)
1311 {
1312         struct i40e_adapter *ad = opaque;
1313         int use_latest_vec;
1314
1315         use_latest_vec = atoi(value);
1316
1317         if (use_latest_vec != 0 && use_latest_vec != 1)
1318                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1319
1320         ad->use_latest_vec = (uint8_t)use_latest_vec;
1321
1322         return 0;
1323 }
1324
1325 static int
1326 i40e_use_latest_vec(struct rte_eth_dev *dev)
1327 {
1328         struct i40e_adapter *ad =
1329                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1330         struct rte_kvargs *kvlist;
1331         int kvargs_count;
1332
1333         ad->use_latest_vec = false;
1334
1335         if (!dev->device->devargs)
1336                 return 0;
1337
1338         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1339         if (!kvlist)
1340                 return -EINVAL;
1341
1342         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1343         if (!kvargs_count) {
1344                 rte_kvargs_free(kvlist);
1345                 return 0;
1346         }
1347
1348         if (kvargs_count > 1)
1349                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1350                             "the first invalid or last valid one is used !",
1351                             ETH_I40E_USE_LATEST_VEC);
1352
1353         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1354                                 i40e_parse_latest_vec_handler, ad) < 0) {
1355                 rte_kvargs_free(kvlist);
1356                 return -EINVAL;
1357         }
1358
1359         rte_kvargs_free(kvlist);
1360         return 0;
1361 }
1362
1363 static int
1364 read_vf_msg_config(__rte_unused const char *key,
1365                                const char *value,
1366                                void *opaque)
1367 {
1368         struct i40e_vf_msg_cfg *cfg = opaque;
1369
1370         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1371                         &cfg->ignore_second) != 3) {
1372                 memset(cfg, 0, sizeof(*cfg));
1373                 PMD_DRV_LOG(ERR, "format error! example: "
1374                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1375                 return -EINVAL;
1376         }
1377
1378         /*
1379          * If the message validation function been enabled, the 'period'
1380          * and 'ignore_second' must greater than 0.
1381          */
1382         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1383                 memset(cfg, 0, sizeof(*cfg));
1384                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1385                                 " number must be greater than 0!",
1386                                 ETH_I40E_VF_MSG_CFG);
1387                 return -EINVAL;
1388         }
1389
1390         return 0;
1391 }
1392
1393 static int
1394 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1395                 struct i40e_vf_msg_cfg *msg_cfg)
1396 {
1397         struct rte_kvargs *kvlist;
1398         int kvargs_count;
1399         int ret = 0;
1400
1401         memset(msg_cfg, 0, sizeof(*msg_cfg));
1402
1403         if (!dev->device->devargs)
1404                 return ret;
1405
1406         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1407         if (!kvlist)
1408                 return -EINVAL;
1409
1410         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1411         if (!kvargs_count)
1412                 goto free_end;
1413
1414         if (kvargs_count > 1) {
1415                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1416                                 ETH_I40E_VF_MSG_CFG);
1417                 ret = -EINVAL;
1418                 goto free_end;
1419         }
1420
1421         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1422                         read_vf_msg_config, msg_cfg) < 0)
1423                 ret = -EINVAL;
1424
1425 free_end:
1426         rte_kvargs_free(kvlist);
1427         return ret;
1428 }
1429
1430 #define I40E_ALARM_INTERVAL 50000 /* us */
1431
1432 static int
1433 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1434 {
1435         struct rte_pci_device *pci_dev;
1436         struct rte_intr_handle *intr_handle;
1437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1439         struct i40e_vsi *vsi;
1440         int ret;
1441         uint32_t len, val;
1442         uint8_t aq_fail = 0;
1443
1444         PMD_INIT_FUNC_TRACE();
1445
1446         dev->dev_ops = &i40e_eth_dev_ops;
1447         dev->rx_queue_count = i40e_dev_rx_queue_count;
1448         dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1449         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1450         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1451         dev->rx_pkt_burst = i40e_recv_pkts;
1452         dev->tx_pkt_burst = i40e_xmit_pkts;
1453         dev->tx_pkt_prepare = i40e_prep_pkts;
1454
1455         /* for secondary processes, we don't initialise any further as primary
1456          * has already done this work. Only check we don't need a different
1457          * RX function */
1458         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459                 i40e_set_rx_function(dev);
1460                 i40e_set_tx_function(dev);
1461                 return 0;
1462         }
1463         i40e_set_default_ptype_table(dev);
1464         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1465         intr_handle = &pci_dev->intr_handle;
1466
1467         rte_eth_copy_pci_info(dev, pci_dev);
1468
1469         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1470         pf->adapter->eth_dev = dev;
1471         pf->dev_data = dev->data;
1472
1473         hw->back = I40E_PF_TO_ADAPTER(pf);
1474         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1475         if (!hw->hw_addr) {
1476                 PMD_INIT_LOG(ERR,
1477                         "Hardware is not available, as address is NULL");
1478                 return -ENODEV;
1479         }
1480
1481         hw->vendor_id = pci_dev->id.vendor_id;
1482         hw->device_id = pci_dev->id.device_id;
1483         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1484         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1485         hw->bus.device = pci_dev->addr.devid;
1486         hw->bus.func = pci_dev->addr.function;
1487         hw->adapter_stopped = 0;
1488         hw->adapter_closed = 0;
1489
1490         /* Init switch device pointer */
1491         hw->switch_dev = NULL;
1492
1493         /*
1494          * Switch Tag value should not be identical to either the First Tag
1495          * or Second Tag values. So set something other than common Ethertype
1496          * for internal switching.
1497          */
1498         hw->switch_tag = 0xffff;
1499
1500         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1501         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1502                 PMD_INIT_LOG(ERR, "\nERROR: "
1503                         "Firmware recovery mode detected. Limiting functionality.\n"
1504                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1505                         "User Guide for details on firmware recovery mode.");
1506                 return -EIO;
1507         }
1508
1509         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1510         /* Check if need to support multi-driver */
1511         i40e_support_multi_driver(dev);
1512         /* Check if users want the latest supported vec path */
1513         i40e_use_latest_vec(dev);
1514
1515         /* Make sure all is clean before doing PF reset */
1516         i40e_clear_hw(hw);
1517
1518         /* Reset here to make sure all is clean for each PF */
1519         ret = i40e_pf_reset(hw);
1520         if (ret) {
1521                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1522                 return ret;
1523         }
1524
1525         /* Initialize the shared code (base driver) */
1526         ret = i40e_init_shared_code(hw);
1527         if (ret) {
1528                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1529                 return ret;
1530         }
1531
1532         /* Initialize the parameters for adminq */
1533         i40e_init_adminq_parameter(hw);
1534         ret = i40e_init_adminq(hw);
1535         if (ret != I40E_SUCCESS) {
1536                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1537                 return -EIO;
1538         }
1539         /* Firmware of SFP x722 does not support adminq option */
1540         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1541                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1542
1543         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1544                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1545                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1546                      ((hw->nvm.version >> 12) & 0xf),
1547                      ((hw->nvm.version >> 4) & 0xff),
1548                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1549
1550         /* Initialize the hardware */
1551         i40e_hw_init(dev);
1552
1553         i40e_config_automask(pf);
1554
1555         i40e_set_default_pctype_table(dev);
1556
1557         /*
1558          * To work around the NVM issue, initialize registers
1559          * for packet type of QinQ by software.
1560          * It should be removed once issues are fixed in NVM.
1561          */
1562         if (!pf->support_multi_driver)
1563                 i40e_GLQF_reg_init(hw);
1564
1565         /* Initialize the input set for filters (hash and fd) to default value */
1566         i40e_filter_input_set_init(pf);
1567
1568         /* initialise the L3_MAP register */
1569         if (!pf->support_multi_driver) {
1570                 ret = i40e_aq_debug_write_global_register(hw,
1571                                                    I40E_GLQF_L3_MAP(40),
1572                                                    0x00000028,  NULL);
1573                 if (ret)
1574                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1575                                      ret);
1576                 PMD_INIT_LOG(DEBUG,
1577                              "Global register 0x%08x is changed with 0x28",
1578                              I40E_GLQF_L3_MAP(40));
1579         }
1580
1581         /* Need the special FW version to support floating VEB */
1582         config_floating_veb(dev);
1583         /* Clear PXE mode */
1584         i40e_clear_pxe_mode(hw);
1585         i40e_dev_sync_phy_type(hw);
1586
1587         /*
1588          * On X710, performance number is far from the expectation on recent
1589          * firmware versions. The fix for this issue may not be integrated in
1590          * the following firmware version. So the workaround in software driver
1591          * is needed. It needs to modify the initial values of 3 internal only
1592          * registers. Note that the workaround can be removed when it is fixed
1593          * in firmware in the future.
1594          */
1595         i40e_configure_registers(hw);
1596
1597         /* Get hw capabilities */
1598         ret = i40e_get_cap(hw);
1599         if (ret != I40E_SUCCESS) {
1600                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1601                 goto err_get_capabilities;
1602         }
1603
1604         /* Initialize parameters for PF */
1605         ret = i40e_pf_parameter_init(dev);
1606         if (ret != 0) {
1607                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1608                 goto err_parameter_init;
1609         }
1610
1611         /* Initialize the queue management */
1612         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1613         if (ret < 0) {
1614                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1615                 goto err_qp_pool_init;
1616         }
1617         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1618                                 hw->func_caps.num_msix_vectors - 1);
1619         if (ret < 0) {
1620                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1621                 goto err_msix_pool_init;
1622         }
1623
1624         /* Initialize lan hmc */
1625         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1626                                 hw->func_caps.num_rx_qp, 0, 0);
1627         if (ret != I40E_SUCCESS) {
1628                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1629                 goto err_init_lan_hmc;
1630         }
1631
1632         /* Configure lan hmc */
1633         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1634         if (ret != I40E_SUCCESS) {
1635                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1636                 goto err_configure_lan_hmc;
1637         }
1638
1639         /* Get and check the mac address */
1640         i40e_get_mac_addr(hw, hw->mac.addr);
1641         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1642                 PMD_INIT_LOG(ERR, "mac address is not valid");
1643                 ret = -EIO;
1644                 goto err_get_mac_addr;
1645         }
1646         /* Copy the permanent MAC address */
1647         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1648                         (struct rte_ether_addr *)hw->mac.perm_addr);
1649
1650         /* Disable flow control */
1651         hw->fc.requested_mode = I40E_FC_NONE;
1652         i40e_set_fc(hw, &aq_fail, TRUE);
1653
1654         /* Set the global registers with default ether type value */
1655         if (!pf->support_multi_driver) {
1656                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1657                                          RTE_ETHER_TYPE_VLAN);
1658                 if (ret != I40E_SUCCESS) {
1659                         PMD_INIT_LOG(ERR,
1660                                      "Failed to set the default outer "
1661                                      "VLAN ether type");
1662                         goto err_setup_pf_switch;
1663                 }
1664         }
1665
1666         /* PF setup, which includes VSI setup */
1667         ret = i40e_pf_setup(pf);
1668         if (ret) {
1669                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1670                 goto err_setup_pf_switch;
1671         }
1672
1673         vsi = pf->main_vsi;
1674
1675         /* Disable double vlan by default */
1676         i40e_vsi_config_double_vlan(vsi, FALSE);
1677
1678         /* Disable S-TAG identification when floating_veb is disabled */
1679         if (!pf->floating_veb) {
1680                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1681                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1682                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1683                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1684                 }
1685         }
1686
1687         if (!vsi->max_macaddrs)
1688                 len = RTE_ETHER_ADDR_LEN;
1689         else
1690                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1691
1692         /* Should be after VSI initialized */
1693         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1694         if (!dev->data->mac_addrs) {
1695                 PMD_INIT_LOG(ERR,
1696                         "Failed to allocated memory for storing mac address");
1697                 goto err_mac_alloc;
1698         }
1699         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1700                                         &dev->data->mac_addrs[0]);
1701
1702         /* Pass the information to the rte_eth_dev_close() that it should also
1703          * release the private port resources.
1704          */
1705         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1706
1707         /* Init dcb to sw mode by default */
1708         ret = i40e_dcb_init_configure(dev, TRUE);
1709         if (ret != I40E_SUCCESS) {
1710                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1711                 pf->flags &= ~I40E_FLAG_DCB;
1712         }
1713         /* Update HW struct after DCB configuration */
1714         i40e_get_cap(hw);
1715
1716         /* initialize pf host driver to setup SRIOV resource if applicable */
1717         i40e_pf_host_init(dev);
1718
1719         /* register callback func to eal lib */
1720         rte_intr_callback_register(intr_handle,
1721                                    i40e_dev_interrupt_handler, dev);
1722
1723         /* configure and enable device interrupt */
1724         i40e_pf_config_irq0(hw, TRUE);
1725         i40e_pf_enable_irq0(hw);
1726
1727         /* enable uio intr after callback register */
1728         rte_intr_enable(intr_handle);
1729
1730         /* By default disable flexible payload in global configuration */
1731         if (!pf->support_multi_driver)
1732                 i40e_flex_payload_reg_set_default(hw);
1733
1734         /*
1735          * Add an ethertype filter to drop all flow control frames transmitted
1736          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1737          * frames to wire.
1738          */
1739         i40e_add_tx_flow_control_drop_filter(pf);
1740
1741         /* Set the max frame size to 0x2600 by default,
1742          * in case other drivers changed the default value.
1743          */
1744         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1745
1746         /* initialize mirror rule list */
1747         TAILQ_INIT(&pf->mirror_list);
1748
1749         /* initialize RSS rule list */
1750         TAILQ_INIT(&pf->rss_config_list);
1751
1752         /* initialize Traffic Manager configuration */
1753         i40e_tm_conf_init(dev);
1754
1755         /* Initialize customized information */
1756         i40e_init_customized_info(pf);
1757
1758         /* Initialize the filter invalidation configuration */
1759         i40e_init_filter_invalidation(pf);
1760
1761         ret = i40e_init_ethtype_filter_list(dev);
1762         if (ret < 0)
1763                 goto err_init_ethtype_filter_list;
1764         ret = i40e_init_tunnel_filter_list(dev);
1765         if (ret < 0)
1766                 goto err_init_tunnel_filter_list;
1767         ret = i40e_init_fdir_filter_list(dev);
1768         if (ret < 0)
1769                 goto err_init_fdir_filter_list;
1770
1771         /* initialize queue region configuration */
1772         i40e_init_queue_region_conf(dev);
1773
1774         /* initialize RSS configuration from rte_flow */
1775         memset(&pf->rss_info, 0,
1776                 sizeof(struct i40e_rte_flow_rss_conf));
1777
1778         /* reset all stats of the device, including pf and main vsi */
1779         i40e_dev_stats_reset(dev);
1780
1781         return 0;
1782
1783 err_init_fdir_filter_list:
1784         rte_free(pf->tunnel.hash_table);
1785         rte_free(pf->tunnel.hash_map);
1786 err_init_tunnel_filter_list:
1787         rte_free(pf->ethertype.hash_table);
1788         rte_free(pf->ethertype.hash_map);
1789 err_init_ethtype_filter_list:
1790         rte_free(dev->data->mac_addrs);
1791         dev->data->mac_addrs = NULL;
1792 err_mac_alloc:
1793         i40e_vsi_release(pf->main_vsi);
1794 err_setup_pf_switch:
1795 err_get_mac_addr:
1796 err_configure_lan_hmc:
1797         (void)i40e_shutdown_lan_hmc(hw);
1798 err_init_lan_hmc:
1799         i40e_res_pool_destroy(&pf->msix_pool);
1800 err_msix_pool_init:
1801         i40e_res_pool_destroy(&pf->qp_pool);
1802 err_qp_pool_init:
1803 err_parameter_init:
1804 err_get_capabilities:
1805         (void)i40e_shutdown_adminq(hw);
1806
1807         return ret;
1808 }
1809
1810 static void
1811 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1812 {
1813         struct i40e_ethertype_filter *p_ethertype;
1814         struct i40e_ethertype_rule *ethertype_rule;
1815
1816         ethertype_rule = &pf->ethertype;
1817         /* Remove all ethertype filter rules and hash */
1818         if (ethertype_rule->hash_map)
1819                 rte_free(ethertype_rule->hash_map);
1820         if (ethertype_rule->hash_table)
1821                 rte_hash_free(ethertype_rule->hash_table);
1822
1823         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1824                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1825                              p_ethertype, rules);
1826                 rte_free(p_ethertype);
1827         }
1828 }
1829
1830 static void
1831 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1832 {
1833         struct i40e_tunnel_filter *p_tunnel;
1834         struct i40e_tunnel_rule *tunnel_rule;
1835
1836         tunnel_rule = &pf->tunnel;
1837         /* Remove all tunnel director rules and hash */
1838         if (tunnel_rule->hash_map)
1839                 rte_free(tunnel_rule->hash_map);
1840         if (tunnel_rule->hash_table)
1841                 rte_hash_free(tunnel_rule->hash_table);
1842
1843         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1844                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1845                 rte_free(p_tunnel);
1846         }
1847 }
1848
1849 static void
1850 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1851 {
1852         struct i40e_fdir_filter *p_fdir;
1853         struct i40e_fdir_info *fdir_info;
1854
1855         fdir_info = &pf->fdir;
1856
1857         /* Remove all flow director rules */
1858         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1859                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1860 }
1861
1862 static void
1863 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1864 {
1865         struct i40e_fdir_info *fdir_info;
1866
1867         fdir_info = &pf->fdir;
1868
1869         /* flow director memory cleanup */
1870         if (fdir_info->hash_map)
1871                 rte_free(fdir_info->hash_map);
1872         if (fdir_info->hash_table)
1873                 rte_hash_free(fdir_info->hash_table);
1874         if (fdir_info->fdir_flow_pool.bitmap)
1875                 rte_free(fdir_info->fdir_flow_pool.bitmap);
1876         if (fdir_info->fdir_flow_pool.pool)
1877                 rte_free(fdir_info->fdir_flow_pool.pool);
1878         if (fdir_info->fdir_filter_array)
1879                 rte_free(fdir_info->fdir_filter_array);
1880 }
1881
1882 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1883 {
1884         /*
1885          * Disable by default flexible payload
1886          * for corresponding L2/L3/L4 layers.
1887          */
1888         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1889         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1890         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1891 }
1892
1893 static int
1894 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1895 {
1896         struct i40e_hw *hw;
1897
1898         PMD_INIT_FUNC_TRACE();
1899
1900         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1901                 return 0;
1902
1903         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904
1905         if (hw->adapter_closed == 0)
1906                 i40e_dev_close(dev);
1907
1908         return 0;
1909 }
1910
1911 static int
1912 i40e_dev_configure(struct rte_eth_dev *dev)
1913 {
1914         struct i40e_adapter *ad =
1915                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1919         int i, ret;
1920
1921         ret = i40e_dev_sync_phy_type(hw);
1922         if (ret)
1923                 return ret;
1924
1925         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1926          * bulk allocation or vector Rx preconditions we will reset it.
1927          */
1928         ad->rx_bulk_alloc_allowed = true;
1929         ad->rx_vec_allowed = true;
1930         ad->tx_simple_allowed = true;
1931         ad->tx_vec_allowed = true;
1932
1933         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1934                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1935
1936         /* Only legacy filter API needs the following fdir config. So when the
1937          * legacy filter API is deprecated, the following codes should also be
1938          * removed.
1939          */
1940         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1941                 ret = i40e_fdir_setup(pf);
1942                 if (ret != I40E_SUCCESS) {
1943                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1944                         return -ENOTSUP;
1945                 }
1946                 ret = i40e_fdir_configure(dev);
1947                 if (ret < 0) {
1948                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1949                         goto err;
1950                 }
1951         } else
1952                 i40e_fdir_teardown(pf);
1953
1954         ret = i40e_dev_init_vlan(dev);
1955         if (ret < 0)
1956                 goto err;
1957
1958         /* VMDQ setup.
1959          *  General PMD driver call sequence are NIC init, configure,
1960          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1961          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1962          *  applicable. So, VMDQ setting has to be done before
1963          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1964          *  For RSS setting, it will try to calculate actual configured RX queue
1965          *  number, which will be available after rx_queue_setup(). dev_start()
1966          *  function is good to place RSS setup.
1967          */
1968         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1969                 ret = i40e_vmdq_setup(dev);
1970                 if (ret)
1971                         goto err;
1972         }
1973
1974         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1975                 ret = i40e_dcb_setup(dev);
1976                 if (ret) {
1977                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1978                         goto err_dcb;
1979                 }
1980         }
1981
1982         TAILQ_INIT(&pf->flow_list);
1983
1984         return 0;
1985
1986 err_dcb:
1987         /* need to release vmdq resource if exists */
1988         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989                 i40e_vsi_release(pf->vmdq[i].vsi);
1990                 pf->vmdq[i].vsi = NULL;
1991         }
1992         rte_free(pf->vmdq);
1993         pf->vmdq = NULL;
1994 err:
1995         /* Need to release fdir resource if exists.
1996          * Only legacy filter API needs the following fdir config. So when the
1997          * legacy filter API is deprecated, the following code should also be
1998          * removed.
1999          */
2000         i40e_fdir_teardown(pf);
2001         return ret;
2002 }
2003
2004 void
2005 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2006 {
2007         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011         uint16_t msix_vect = vsi->msix_intr;
2012         uint16_t i;
2013
2014         for (i = 0; i < vsi->nb_qps; i++) {
2015                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2017                 rte_wmb();
2018         }
2019
2020         if (vsi->type != I40E_VSI_SRIOV) {
2021                 if (!rte_intr_allow_others(intr_handle)) {
2022                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2023                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2024                         I40E_WRITE_REG(hw,
2025                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2026                                        0);
2027                 } else {
2028                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2029                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2030                         I40E_WRITE_REG(hw,
2031                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2032                                                        msix_vect - 1), 0);
2033                 }
2034         } else {
2035                 uint32_t reg;
2036                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2037                         vsi->user_param + (msix_vect - 1);
2038
2039                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2040                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2041         }
2042         I40E_WRITE_FLUSH(hw);
2043 }
2044
2045 static void
2046 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2047                        int base_queue, int nb_queue,
2048                        uint16_t itr_idx)
2049 {
2050         int i;
2051         uint32_t val;
2052         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2054
2055         /* Bind all RX queues to allocated MSIX interrupt */
2056         for (i = 0; i < nb_queue; i++) {
2057                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2058                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2059                         ((base_queue + i + 1) <<
2060                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2061                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2062                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2063
2064                 if (i == nb_queue - 1)
2065                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2066                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2067         }
2068
2069         /* Write first RX queue to Link list register as the head element */
2070         if (vsi->type != I40E_VSI_SRIOV) {
2071                 uint16_t interval =
2072                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2073
2074                 if (msix_vect == I40E_MISC_VEC_ID) {
2075                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2076                                        (base_queue <<
2077                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2078                                        (0x0 <<
2079                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2080                         I40E_WRITE_REG(hw,
2081                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2082                                        interval);
2083                 } else {
2084                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2085                                        (base_queue <<
2086                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2087                                        (0x0 <<
2088                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2089                         I40E_WRITE_REG(hw,
2090                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2091                                                        msix_vect - 1),
2092                                        interval);
2093                 }
2094         } else {
2095                 uint32_t reg;
2096
2097                 if (msix_vect == I40E_MISC_VEC_ID) {
2098                         I40E_WRITE_REG(hw,
2099                                        I40E_VPINT_LNKLST0(vsi->user_param),
2100                                        (base_queue <<
2101                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2102                                        (0x0 <<
2103                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2104                 } else {
2105                         /* num_msix_vectors_vf needs to minus irq0 */
2106                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2107                                 vsi->user_param + (msix_vect - 1);
2108
2109                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2110                                        (base_queue <<
2111                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2112                                        (0x0 <<
2113                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2114                 }
2115         }
2116
2117         I40E_WRITE_FLUSH(hw);
2118 }
2119
2120 int
2121 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2122 {
2123         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2124         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2126         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2127         uint16_t msix_vect = vsi->msix_intr;
2128         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2129         uint16_t queue_idx = 0;
2130         int record = 0;
2131         int i;
2132
2133         for (i = 0; i < vsi->nb_qps; i++) {
2134                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2135                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2136         }
2137
2138         /* VF bind interrupt */
2139         if (vsi->type == I40E_VSI_SRIOV) {
2140                 if (vsi->nb_msix == 0) {
2141                         PMD_DRV_LOG(ERR, "No msix resource");
2142                         return -EINVAL;
2143                 }
2144                 __vsi_queues_bind_intr(vsi, msix_vect,
2145                                        vsi->base_queue, vsi->nb_qps,
2146                                        itr_idx);
2147                 return 0;
2148         }
2149
2150         /* PF & VMDq bind interrupt */
2151         if (rte_intr_dp_is_en(intr_handle)) {
2152                 if (vsi->type == I40E_VSI_MAIN) {
2153                         queue_idx = 0;
2154                         record = 1;
2155                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2156                         struct i40e_vsi *main_vsi =
2157                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2158                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2159                         record = 1;
2160                 }
2161         }
2162
2163         for (i = 0; i < vsi->nb_used_qps; i++) {
2164                 if (vsi->nb_msix == 0) {
2165                         PMD_DRV_LOG(ERR, "No msix resource");
2166                         return -EINVAL;
2167                 } else if (nb_msix <= 1) {
2168                         if (!rte_intr_allow_others(intr_handle))
2169                                 /* allow to share MISC_VEC_ID */
2170                                 msix_vect = I40E_MISC_VEC_ID;
2171
2172                         /* no enough msix_vect, map all to one */
2173                         __vsi_queues_bind_intr(vsi, msix_vect,
2174                                                vsi->base_queue + i,
2175                                                vsi->nb_used_qps - i,
2176                                                itr_idx);
2177                         for (; !!record && i < vsi->nb_used_qps; i++)
2178                                 intr_handle->intr_vec[queue_idx + i] =
2179                                         msix_vect;
2180                         break;
2181                 }
2182                 /* 1:1 queue/msix_vect mapping */
2183                 __vsi_queues_bind_intr(vsi, msix_vect,
2184                                        vsi->base_queue + i, 1,
2185                                        itr_idx);
2186                 if (!!record)
2187                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2188
2189                 msix_vect++;
2190                 nb_msix--;
2191         }
2192
2193         return 0;
2194 }
2195
2196 void
2197 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2198 {
2199         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2200         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2202         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2203         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2204         uint16_t msix_intr, i;
2205
2206         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2207                 for (i = 0; i < vsi->nb_msix; i++) {
2208                         msix_intr = vsi->msix_intr + i;
2209                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2210                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2211                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2212                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2213                 }
2214         else
2215                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2216                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2217                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2218                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2219
2220         I40E_WRITE_FLUSH(hw);
2221 }
2222
2223 void
2224 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2225 {
2226         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2227         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2228         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2229         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2230         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2231         uint16_t msix_intr, i;
2232
2233         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2234                 for (i = 0; i < vsi->nb_msix; i++) {
2235                         msix_intr = vsi->msix_intr + i;
2236                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2237                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2238                 }
2239         else
2240                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2241                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2242
2243         I40E_WRITE_FLUSH(hw);
2244 }
2245
2246 static inline uint8_t
2247 i40e_parse_link_speeds(uint16_t link_speeds)
2248 {
2249         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2250
2251         if (link_speeds & ETH_LINK_SPEED_40G)
2252                 link_speed |= I40E_LINK_SPEED_40GB;
2253         if (link_speeds & ETH_LINK_SPEED_25G)
2254                 link_speed |= I40E_LINK_SPEED_25GB;
2255         if (link_speeds & ETH_LINK_SPEED_20G)
2256                 link_speed |= I40E_LINK_SPEED_20GB;
2257         if (link_speeds & ETH_LINK_SPEED_10G)
2258                 link_speed |= I40E_LINK_SPEED_10GB;
2259         if (link_speeds & ETH_LINK_SPEED_1G)
2260                 link_speed |= I40E_LINK_SPEED_1GB;
2261         if (link_speeds & ETH_LINK_SPEED_100M)
2262                 link_speed |= I40E_LINK_SPEED_100MB;
2263
2264         return link_speed;
2265 }
2266
2267 static int
2268 i40e_phy_conf_link(struct i40e_hw *hw,
2269                    uint8_t abilities,
2270                    uint8_t force_speed,
2271                    bool is_up)
2272 {
2273         enum i40e_status_code status;
2274         struct i40e_aq_get_phy_abilities_resp phy_ab;
2275         struct i40e_aq_set_phy_config phy_conf;
2276         enum i40e_aq_phy_type cnt;
2277         uint8_t avail_speed;
2278         uint32_t phy_type_mask = 0;
2279
2280         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2281                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2282                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2283                         I40E_AQ_PHY_FLAG_LOW_POWER;
2284         int ret = -ENOTSUP;
2285
2286         /* To get phy capabilities of available speeds. */
2287         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2288                                               NULL);
2289         if (status) {
2290                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2291                                 status);
2292                 return ret;
2293         }
2294         avail_speed = phy_ab.link_speed;
2295
2296         /* To get the current phy config. */
2297         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2298                                               NULL);
2299         if (status) {
2300                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2301                                 status);
2302                 return ret;
2303         }
2304
2305         /* If link needs to go up and it is in autoneg mode the speed is OK,
2306          * no need to set up again.
2307          */
2308         if (is_up && phy_ab.phy_type != 0 &&
2309                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2310                      phy_ab.link_speed != 0)
2311                 return I40E_SUCCESS;
2312
2313         memset(&phy_conf, 0, sizeof(phy_conf));
2314
2315         /* bits 0-2 use the values from get_phy_abilities_resp */
2316         abilities &= ~mask;
2317         abilities |= phy_ab.abilities & mask;
2318
2319         phy_conf.abilities = abilities;
2320
2321         /* If link needs to go up, but the force speed is not supported,
2322          * Warn users and config the default available speeds.
2323          */
2324         if (is_up && !(force_speed & avail_speed)) {
2325                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2326                 phy_conf.link_speed = avail_speed;
2327         } else {
2328                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2329         }
2330
2331         /* PHY type mask needs to include each type except PHY type extension */
2332         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2333                 phy_type_mask |= 1 << cnt;
2334
2335         /* use get_phy_abilities_resp value for the rest */
2336         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2337         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2338                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2339                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2340         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2341         phy_conf.eee_capability = phy_ab.eee_capability;
2342         phy_conf.eeer = phy_ab.eeer_val;
2343         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2344
2345         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2346                     phy_ab.abilities, phy_ab.link_speed);
2347         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2348                     phy_conf.abilities, phy_conf.link_speed);
2349
2350         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2351         if (status)
2352                 return ret;
2353
2354         return I40E_SUCCESS;
2355 }
2356
2357 static int
2358 i40e_apply_link_speed(struct rte_eth_dev *dev)
2359 {
2360         uint8_t speed;
2361         uint8_t abilities = 0;
2362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363         struct rte_eth_conf *conf = &dev->data->dev_conf;
2364
2365         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2366                      I40E_AQ_PHY_LINK_ENABLED;
2367
2368         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2369                 conf->link_speeds = ETH_LINK_SPEED_40G |
2370                                     ETH_LINK_SPEED_25G |
2371                                     ETH_LINK_SPEED_20G |
2372                                     ETH_LINK_SPEED_10G |
2373                                     ETH_LINK_SPEED_1G |
2374                                     ETH_LINK_SPEED_100M;
2375
2376                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2377         } else {
2378                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2379         }
2380         speed = i40e_parse_link_speeds(conf->link_speeds);
2381
2382         return i40e_phy_conf_link(hw, abilities, speed, true);
2383 }
2384
2385 static int
2386 i40e_dev_start(struct rte_eth_dev *dev)
2387 {
2388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2390         struct i40e_vsi *main_vsi = pf->main_vsi;
2391         int ret, i;
2392         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2393         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2394         uint32_t intr_vector = 0;
2395         struct i40e_vsi *vsi;
2396         uint16_t nb_rxq, nb_txq;
2397
2398         hw->adapter_stopped = 0;
2399
2400         rte_intr_disable(intr_handle);
2401
2402         if ((rte_intr_cap_multiple(intr_handle) ||
2403              !RTE_ETH_DEV_SRIOV(dev).active) &&
2404             dev->data->dev_conf.intr_conf.rxq != 0) {
2405                 intr_vector = dev->data->nb_rx_queues;
2406                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2407                 if (ret)
2408                         return ret;
2409         }
2410
2411         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2412                 intr_handle->intr_vec =
2413                         rte_zmalloc("intr_vec",
2414                                     dev->data->nb_rx_queues * sizeof(int),
2415                                     0);
2416                 if (!intr_handle->intr_vec) {
2417                         PMD_INIT_LOG(ERR,
2418                                 "Failed to allocate %d rx_queues intr_vec",
2419                                 dev->data->nb_rx_queues);
2420                         return -ENOMEM;
2421                 }
2422         }
2423
2424         /* Initialize VSI */
2425         ret = i40e_dev_rxtx_init(pf);
2426         if (ret != I40E_SUCCESS) {
2427                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2428                 return ret;
2429         }
2430
2431         /* Map queues with MSIX interrupt */
2432         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2433                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2434         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2435         if (ret < 0)
2436                 return ret;
2437         i40e_vsi_enable_queues_intr(main_vsi);
2438
2439         /* Map VMDQ VSI queues with MSIX interrupt */
2440         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2441                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2442                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2443                                                 I40E_ITR_INDEX_DEFAULT);
2444                 if (ret < 0)
2445                         return ret;
2446                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2447         }
2448
2449         /* Enable all queues which have been configured */
2450         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2451                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2452                 if (ret)
2453                         goto rx_err;
2454         }
2455
2456         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2457                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2458                 if (ret)
2459                         goto tx_err;
2460         }
2461
2462         /* Enable receiving broadcast packets */
2463         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2464         if (ret != I40E_SUCCESS)
2465                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2466
2467         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2468                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2469                                                 true, NULL);
2470                 if (ret != I40E_SUCCESS)
2471                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2472         }
2473
2474         /* Enable the VLAN promiscuous mode. */
2475         if (pf->vfs) {
2476                 for (i = 0; i < pf->vf_num; i++) {
2477                         vsi = pf->vfs[i].vsi;
2478                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2479                                                      true, NULL);
2480                 }
2481         }
2482
2483         /* Enable mac loopback mode */
2484         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2485             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2486                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2487                 if (ret != I40E_SUCCESS) {
2488                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2489                         goto tx_err;
2490                 }
2491         }
2492
2493         /* Apply link configure */
2494         ret = i40e_apply_link_speed(dev);
2495         if (I40E_SUCCESS != ret) {
2496                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2497                 goto tx_err;
2498         }
2499
2500         if (!rte_intr_allow_others(intr_handle)) {
2501                 rte_intr_callback_unregister(intr_handle,
2502                                              i40e_dev_interrupt_handler,
2503                                              (void *)dev);
2504                 /* configure and enable device interrupt */
2505                 i40e_pf_config_irq0(hw, FALSE);
2506                 i40e_pf_enable_irq0(hw);
2507
2508                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2509                         PMD_INIT_LOG(INFO,
2510                                 "lsc won't enable because of no intr multiplex");
2511         } else {
2512                 ret = i40e_aq_set_phy_int_mask(hw,
2513                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2514                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2515                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2516                 if (ret != I40E_SUCCESS)
2517                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2518
2519                 /* Call get_link_info aq commond to enable/disable LSE */
2520                 i40e_dev_link_update(dev, 0);
2521         }
2522
2523         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2524                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2525                                   i40e_dev_alarm_handler, dev);
2526         } else {
2527                 /* enable uio intr after callback register */
2528                 rte_intr_enable(intr_handle);
2529         }
2530
2531         i40e_filter_restore(pf);
2532
2533         if (pf->tm_conf.root && !pf->tm_conf.committed)
2534                 PMD_DRV_LOG(WARNING,
2535                             "please call hierarchy_commit() "
2536                             "before starting the port");
2537
2538         return I40E_SUCCESS;
2539
2540 tx_err:
2541         for (i = 0; i < nb_txq; i++)
2542                 i40e_dev_tx_queue_stop(dev, i);
2543 rx_err:
2544         for (i = 0; i < nb_rxq; i++)
2545                 i40e_dev_rx_queue_stop(dev, i);
2546
2547         return ret;
2548 }
2549
2550 static void
2551 i40e_dev_stop(struct rte_eth_dev *dev)
2552 {
2553         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         struct i40e_vsi *main_vsi = pf->main_vsi;
2556         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2557         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2558         int i;
2559
2560         if (hw->adapter_stopped == 1)
2561                 return;
2562
2563         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2564                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2565                 rte_intr_enable(intr_handle);
2566         }
2567
2568         /* Disable all queues */
2569         for (i = 0; i < dev->data->nb_tx_queues; i++)
2570                 i40e_dev_tx_queue_stop(dev, i);
2571
2572         for (i = 0; i < dev->data->nb_rx_queues; i++)
2573                 i40e_dev_rx_queue_stop(dev, i);
2574
2575         /* un-map queues with interrupt registers */
2576         i40e_vsi_disable_queues_intr(main_vsi);
2577         i40e_vsi_queues_unbind_intr(main_vsi);
2578
2579         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2580                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2581                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2582         }
2583
2584         /* Clear all queues and release memory */
2585         i40e_dev_clear_queues(dev);
2586
2587         /* Set link down */
2588         i40e_dev_set_link_down(dev);
2589
2590         if (!rte_intr_allow_others(intr_handle))
2591                 /* resume to the default handler */
2592                 rte_intr_callback_register(intr_handle,
2593                                            i40e_dev_interrupt_handler,
2594                                            (void *)dev);
2595
2596         /* Clean datapath event and queue/vec mapping */
2597         rte_intr_efd_disable(intr_handle);
2598         if (intr_handle->intr_vec) {
2599                 rte_free(intr_handle->intr_vec);
2600                 intr_handle->intr_vec = NULL;
2601         }
2602
2603         /* reset hierarchy commit */
2604         pf->tm_conf.committed = false;
2605
2606         hw->adapter_stopped = 1;
2607
2608         pf->adapter->rss_reta_updated = 0;
2609 }
2610
2611 static void
2612 i40e_dev_close(struct rte_eth_dev *dev)
2613 {
2614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2618         struct i40e_mirror_rule *p_mirror;
2619         struct i40e_filter_control_settings settings;
2620         struct rte_flow *p_flow;
2621         uint32_t reg;
2622         int i;
2623         int ret;
2624         uint8_t aq_fail = 0;
2625         int retries = 0;
2626
2627         PMD_INIT_FUNC_TRACE();
2628
2629         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2630         if (ret)
2631                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2632
2633
2634         i40e_dev_stop(dev);
2635
2636         /* Remove all mirror rules */
2637         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2638                 ret = i40e_aq_del_mirror_rule(hw,
2639                                               pf->main_vsi->veb->seid,
2640                                               p_mirror->rule_type,
2641                                               p_mirror->entries,
2642                                               p_mirror->num_entries,
2643                                               p_mirror->id);
2644                 if (ret < 0)
2645                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2646                                     "status = %d, aq_err = %d.", ret,
2647                                     hw->aq.asq_last_status);
2648
2649                 /* remove mirror software resource anyway */
2650                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2651                 rte_free(p_mirror);
2652                 pf->nb_mirror_rule--;
2653         }
2654
2655         i40e_dev_free_queues(dev);
2656
2657         /* Disable interrupt */
2658         i40e_pf_disable_irq0(hw);
2659         rte_intr_disable(intr_handle);
2660
2661         /*
2662          * Only legacy filter API needs the following fdir config. So when the
2663          * legacy filter API is deprecated, the following code should also be
2664          * removed.
2665          */
2666         i40e_fdir_teardown(pf);
2667
2668         /* shutdown and destroy the HMC */
2669         i40e_shutdown_lan_hmc(hw);
2670
2671         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2672                 i40e_vsi_release(pf->vmdq[i].vsi);
2673                 pf->vmdq[i].vsi = NULL;
2674         }
2675         rte_free(pf->vmdq);
2676         pf->vmdq = NULL;
2677
2678         /* release all the existing VSIs and VEBs */
2679         i40e_vsi_release(pf->main_vsi);
2680
2681         /* shutdown the adminq */
2682         i40e_aq_queue_shutdown(hw, true);
2683         i40e_shutdown_adminq(hw);
2684
2685         i40e_res_pool_destroy(&pf->qp_pool);
2686         i40e_res_pool_destroy(&pf->msix_pool);
2687
2688         /* Disable flexible payload in global configuration */
2689         if (!pf->support_multi_driver)
2690                 i40e_flex_payload_reg_set_default(hw);
2691
2692         /* force a PF reset to clean anything leftover */
2693         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2694         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2695                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2696         I40E_WRITE_FLUSH(hw);
2697
2698         dev->dev_ops = NULL;
2699         dev->rx_pkt_burst = NULL;
2700         dev->tx_pkt_burst = NULL;
2701
2702         /* Clear PXE mode */
2703         i40e_clear_pxe_mode(hw);
2704
2705         /* Unconfigure filter control */
2706         memset(&settings, 0, sizeof(settings));
2707         ret = i40e_set_filter_control(hw, &settings);
2708         if (ret)
2709                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2710                                         ret);
2711
2712         /* Disable flow control */
2713         hw->fc.requested_mode = I40E_FC_NONE;
2714         i40e_set_fc(hw, &aq_fail, TRUE);
2715
2716         /* uninitialize pf host driver */
2717         i40e_pf_host_uninit(dev);
2718
2719         do {
2720                 ret = rte_intr_callback_unregister(intr_handle,
2721                                 i40e_dev_interrupt_handler, dev);
2722                 if (ret >= 0 || ret == -ENOENT) {
2723                         break;
2724                 } else if (ret != -EAGAIN) {
2725                         PMD_INIT_LOG(ERR,
2726                                  "intr callback unregister failed: %d",
2727                                  ret);
2728                 }
2729                 i40e_msec_delay(500);
2730         } while (retries++ < 5);
2731
2732         i40e_rm_ethtype_filter_list(pf);
2733         i40e_rm_tunnel_filter_list(pf);
2734         i40e_rm_fdir_filter_list(pf);
2735
2736         /* Remove all flows */
2737         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2738                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2739                 /* Do not free FDIR flows since they are static allocated */
2740                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2741                         rte_free(p_flow);
2742         }
2743
2744         /* release the fdir static allocated memory */
2745         i40e_fdir_memory_cleanup(pf);
2746
2747         /* Remove all Traffic Manager configuration */
2748         i40e_tm_conf_uninit(dev);
2749
2750         hw->adapter_closed = 1;
2751 }
2752
2753 /*
2754  * Reset PF device only to re-initialize resources in PMD layer
2755  */
2756 static int
2757 i40e_dev_reset(struct rte_eth_dev *dev)
2758 {
2759         int ret;
2760
2761         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2762          * its VF to make them align with it. The detailed notification
2763          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2764          * To avoid unexpected behavior in VF, currently reset of PF with
2765          * SR-IOV activation is not supported. It might be supported later.
2766          */
2767         if (dev->data->sriov.active)
2768                 return -ENOTSUP;
2769
2770         ret = eth_i40e_dev_uninit(dev);
2771         if (ret)
2772                 return ret;
2773
2774         ret = eth_i40e_dev_init(dev, NULL);
2775
2776         return ret;
2777 }
2778
2779 static int
2780 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2781 {
2782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         struct i40e_vsi *vsi = pf->main_vsi;
2785         int status;
2786
2787         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2788                                                      true, NULL, true);
2789         if (status != I40E_SUCCESS) {
2790                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2791                 return -EAGAIN;
2792         }
2793
2794         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2795                                                         TRUE, NULL);
2796         if (status != I40E_SUCCESS) {
2797                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2798                 /* Rollback unicast promiscuous mode */
2799                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2800                                                     false, NULL, true);
2801                 return -EAGAIN;
2802         }
2803
2804         return 0;
2805 }
2806
2807 static int
2808 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2809 {
2810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812         struct i40e_vsi *vsi = pf->main_vsi;
2813         int status;
2814
2815         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2816                                                      false, NULL, true);
2817         if (status != I40E_SUCCESS) {
2818                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2819                 return -EAGAIN;
2820         }
2821
2822         /* must remain in all_multicast mode */
2823         if (dev->data->all_multicast == 1)
2824                 return 0;
2825
2826         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2827                                                         false, NULL);
2828         if (status != I40E_SUCCESS) {
2829                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2830                 /* Rollback unicast promiscuous mode */
2831                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2832                                                     true, NULL, true);
2833                 return -EAGAIN;
2834         }
2835
2836         return 0;
2837 }
2838
2839 static int
2840 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2841 {
2842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         struct i40e_vsi *vsi = pf->main_vsi;
2845         int ret;
2846
2847         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2848         if (ret != I40E_SUCCESS) {
2849                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2850                 return -EAGAIN;
2851         }
2852
2853         return 0;
2854 }
2855
2856 static int
2857 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2858 {
2859         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861         struct i40e_vsi *vsi = pf->main_vsi;
2862         int ret;
2863
2864         if (dev->data->promiscuous == 1)
2865                 return 0; /* must remain in all_multicast mode */
2866
2867         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2868                                 vsi->seid, FALSE, NULL);
2869         if (ret != I40E_SUCCESS) {
2870                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2871                 return -EAGAIN;
2872         }
2873
2874         return 0;
2875 }
2876
2877 /*
2878  * Set device link up.
2879  */
2880 static int
2881 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2882 {
2883         /* re-apply link speed setting */
2884         return i40e_apply_link_speed(dev);
2885 }
2886
2887 /*
2888  * Set device link down.
2889  */
2890 static int
2891 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2892 {
2893         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2894         uint8_t abilities = 0;
2895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896
2897         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2898         return i40e_phy_conf_link(hw, abilities, speed, false);
2899 }
2900
2901 static __rte_always_inline void
2902 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2903 {
2904 /* Link status registers and values*/
2905 #define I40E_PRTMAC_LINKSTA             0x001E2420
2906 #define I40E_REG_LINK_UP                0x40000080
2907 #define I40E_PRTMAC_MACC                0x001E24E0
2908 #define I40E_REG_MACC_25GB              0x00020000
2909 #define I40E_REG_SPEED_MASK             0x38000000
2910 #define I40E_REG_SPEED_0                0x00000000
2911 #define I40E_REG_SPEED_1                0x08000000
2912 #define I40E_REG_SPEED_2                0x10000000
2913 #define I40E_REG_SPEED_3                0x18000000
2914 #define I40E_REG_SPEED_4                0x20000000
2915         uint32_t link_speed;
2916         uint32_t reg_val;
2917
2918         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2919         link_speed = reg_val & I40E_REG_SPEED_MASK;
2920         reg_val &= I40E_REG_LINK_UP;
2921         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2922
2923         if (unlikely(link->link_status == 0))
2924                 return;
2925
2926         /* Parse the link status */
2927         switch (link_speed) {
2928         case I40E_REG_SPEED_0:
2929                 link->link_speed = ETH_SPEED_NUM_100M;
2930                 break;
2931         case I40E_REG_SPEED_1:
2932                 link->link_speed = ETH_SPEED_NUM_1G;
2933                 break;
2934         case I40E_REG_SPEED_2:
2935                 if (hw->mac.type == I40E_MAC_X722)
2936                         link->link_speed = ETH_SPEED_NUM_2_5G;
2937                 else
2938                         link->link_speed = ETH_SPEED_NUM_10G;
2939                 break;
2940         case I40E_REG_SPEED_3:
2941                 if (hw->mac.type == I40E_MAC_X722) {
2942                         link->link_speed = ETH_SPEED_NUM_5G;
2943                 } else {
2944                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2945
2946                         if (reg_val & I40E_REG_MACC_25GB)
2947                                 link->link_speed = ETH_SPEED_NUM_25G;
2948                         else
2949                                 link->link_speed = ETH_SPEED_NUM_40G;
2950                 }
2951                 break;
2952         case I40E_REG_SPEED_4:
2953                 if (hw->mac.type == I40E_MAC_X722)
2954                         link->link_speed = ETH_SPEED_NUM_10G;
2955                 else
2956                         link->link_speed = ETH_SPEED_NUM_20G;
2957                 break;
2958         default:
2959                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2960                 break;
2961         }
2962 }
2963
2964 static __rte_always_inline void
2965 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2966         bool enable_lse, int wait_to_complete)
2967 {
2968 #define CHECK_INTERVAL             100  /* 100ms */
2969 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2970         uint32_t rep_cnt = MAX_REPEAT_TIME;
2971         struct i40e_link_status link_status;
2972         int status;
2973
2974         memset(&link_status, 0, sizeof(link_status));
2975
2976         do {
2977                 memset(&link_status, 0, sizeof(link_status));
2978
2979                 /* Get link status information from hardware */
2980                 status = i40e_aq_get_link_info(hw, enable_lse,
2981                                                 &link_status, NULL);
2982                 if (unlikely(status != I40E_SUCCESS)) {
2983                         link->link_speed = ETH_SPEED_NUM_NONE;
2984                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2985                         PMD_DRV_LOG(ERR, "Failed to get link info");
2986                         return;
2987                 }
2988
2989                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2990                 if (!wait_to_complete || link->link_status)
2991                         break;
2992
2993                 rte_delay_ms(CHECK_INTERVAL);
2994         } while (--rep_cnt);
2995
2996         /* Parse the link status */
2997         switch (link_status.link_speed) {
2998         case I40E_LINK_SPEED_100MB:
2999                 link->link_speed = ETH_SPEED_NUM_100M;
3000                 break;
3001         case I40E_LINK_SPEED_1GB:
3002                 link->link_speed = ETH_SPEED_NUM_1G;
3003                 break;
3004         case I40E_LINK_SPEED_10GB:
3005                 link->link_speed = ETH_SPEED_NUM_10G;
3006                 break;
3007         case I40E_LINK_SPEED_20GB:
3008                 link->link_speed = ETH_SPEED_NUM_20G;
3009                 break;
3010         case I40E_LINK_SPEED_25GB:
3011                 link->link_speed = ETH_SPEED_NUM_25G;
3012                 break;
3013         case I40E_LINK_SPEED_40GB:
3014                 link->link_speed = ETH_SPEED_NUM_40G;
3015                 break;
3016         default:
3017                 if (link->link_status)
3018                         link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3019                 else
3020                         link->link_speed = ETH_SPEED_NUM_NONE;
3021                 break;
3022         }
3023 }
3024
3025 int
3026 i40e_dev_link_update(struct rte_eth_dev *dev,
3027                      int wait_to_complete)
3028 {
3029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030         struct rte_eth_link link;
3031         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3032         int ret;
3033
3034         memset(&link, 0, sizeof(link));
3035
3036         /* i40e uses full duplex only */
3037         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3038         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3039                         ETH_LINK_SPEED_FIXED);
3040
3041         if (!wait_to_complete && !enable_lse)
3042                 update_link_reg(hw, &link);
3043         else
3044                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3045
3046         if (hw->switch_dev)
3047                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3048
3049         ret = rte_eth_linkstatus_set(dev, &link);
3050         i40e_notify_all_vfs_link_status(dev);
3051
3052         return ret;
3053 }
3054
3055 /* Get all the statistics of a VSI */
3056 void
3057 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3058 {
3059         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3060         struct i40e_eth_stats *nes = &vsi->eth_stats;
3061         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3062         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3063
3064         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3065                             vsi->offset_loaded, &oes->rx_bytes,
3066                             &nes->rx_bytes);
3067         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3068                             vsi->offset_loaded, &oes->rx_unicast,
3069                             &nes->rx_unicast);
3070         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3071                             vsi->offset_loaded, &oes->rx_multicast,
3072                             &nes->rx_multicast);
3073         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3074                             vsi->offset_loaded, &oes->rx_broadcast,
3075                             &nes->rx_broadcast);
3076         /* exclude CRC bytes */
3077         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3078                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3079
3080         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3081                             &oes->rx_discards, &nes->rx_discards);
3082         /* GLV_REPC not supported */
3083         /* GLV_RMPC not supported */
3084         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3085                             &oes->rx_unknown_protocol,
3086                             &nes->rx_unknown_protocol);
3087         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3088                             vsi->offset_loaded, &oes->tx_bytes,
3089                             &nes->tx_bytes);
3090         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3091                             vsi->offset_loaded, &oes->tx_unicast,
3092                             &nes->tx_unicast);
3093         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3094                             vsi->offset_loaded, &oes->tx_multicast,
3095                             &nes->tx_multicast);
3096         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3097                             vsi->offset_loaded,  &oes->tx_broadcast,
3098                             &nes->tx_broadcast);
3099         /* GLV_TDPC not supported */
3100         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3101                             &oes->tx_errors, &nes->tx_errors);
3102         vsi->offset_loaded = true;
3103
3104         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3105                     vsi->vsi_id);
3106         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3107         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3108         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3109         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3110         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3111         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3112                     nes->rx_unknown_protocol);
3113         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3114         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3115         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3116         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3117         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3118         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3119         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3120                     vsi->vsi_id);
3121 }
3122
3123 static void
3124 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3125 {
3126         unsigned int i;
3127         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3128         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3129
3130         /* Get rx/tx bytes of internal transfer packets */
3131         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3132                         I40E_GLV_GORCL(hw->port),
3133                         pf->offset_loaded,
3134                         &pf->internal_stats_offset.rx_bytes,
3135                         &pf->internal_stats.rx_bytes);
3136
3137         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3138                         I40E_GLV_GOTCL(hw->port),
3139                         pf->offset_loaded,
3140                         &pf->internal_stats_offset.tx_bytes,
3141                         &pf->internal_stats.tx_bytes);
3142         /* Get total internal rx packet count */
3143         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3144                             I40E_GLV_UPRCL(hw->port),
3145                             pf->offset_loaded,
3146                             &pf->internal_stats_offset.rx_unicast,
3147                             &pf->internal_stats.rx_unicast);
3148         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3149                             I40E_GLV_MPRCL(hw->port),
3150                             pf->offset_loaded,
3151                             &pf->internal_stats_offset.rx_multicast,
3152                             &pf->internal_stats.rx_multicast);
3153         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3154                             I40E_GLV_BPRCL(hw->port),
3155                             pf->offset_loaded,
3156                             &pf->internal_stats_offset.rx_broadcast,
3157                             &pf->internal_stats.rx_broadcast);
3158         /* Get total internal tx packet count */
3159         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3160                             I40E_GLV_UPTCL(hw->port),
3161                             pf->offset_loaded,
3162                             &pf->internal_stats_offset.tx_unicast,
3163                             &pf->internal_stats.tx_unicast);
3164         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3165                             I40E_GLV_MPTCL(hw->port),
3166                             pf->offset_loaded,
3167                             &pf->internal_stats_offset.tx_multicast,
3168                             &pf->internal_stats.tx_multicast);
3169         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3170                             I40E_GLV_BPTCL(hw->port),
3171                             pf->offset_loaded,
3172                             &pf->internal_stats_offset.tx_broadcast,
3173                             &pf->internal_stats.tx_broadcast);
3174
3175         /* exclude CRC size */
3176         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3177                 pf->internal_stats.rx_multicast +
3178                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3179
3180         /* Get statistics of struct i40e_eth_stats */
3181         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3182                             I40E_GLPRT_GORCL(hw->port),
3183                             pf->offset_loaded, &os->eth.rx_bytes,
3184                             &ns->eth.rx_bytes);
3185         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3186                             I40E_GLPRT_UPRCL(hw->port),
3187                             pf->offset_loaded, &os->eth.rx_unicast,
3188                             &ns->eth.rx_unicast);
3189         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3190                             I40E_GLPRT_MPRCL(hw->port),
3191                             pf->offset_loaded, &os->eth.rx_multicast,
3192                             &ns->eth.rx_multicast);
3193         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3194                             I40E_GLPRT_BPRCL(hw->port),
3195                             pf->offset_loaded, &os->eth.rx_broadcast,
3196                             &ns->eth.rx_broadcast);
3197         /* Workaround: CRC size should not be included in byte statistics,
3198          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3199          * packet.
3200          */
3201         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3202                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3203
3204         /* exclude internal rx bytes
3205          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3206          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3207          * value.
3208          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3209          */
3210         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3211                 ns->eth.rx_bytes = 0;
3212         else
3213                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3214
3215         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3216                 ns->eth.rx_unicast = 0;
3217         else
3218                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3219
3220         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3221                 ns->eth.rx_multicast = 0;
3222         else
3223                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3224
3225         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3226                 ns->eth.rx_broadcast = 0;
3227         else
3228                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3229
3230         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3231                             pf->offset_loaded, &os->eth.rx_discards,
3232                             &ns->eth.rx_discards);
3233         /* GLPRT_REPC not supported */
3234         /* GLPRT_RMPC not supported */
3235         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3236                             pf->offset_loaded,
3237                             &os->eth.rx_unknown_protocol,
3238                             &ns->eth.rx_unknown_protocol);
3239         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3240                             I40E_GLPRT_GOTCL(hw->port),
3241                             pf->offset_loaded, &os->eth.tx_bytes,
3242                             &ns->eth.tx_bytes);
3243         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3244                             I40E_GLPRT_UPTCL(hw->port),
3245                             pf->offset_loaded, &os->eth.tx_unicast,
3246                             &ns->eth.tx_unicast);
3247         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3248                             I40E_GLPRT_MPTCL(hw->port),
3249                             pf->offset_loaded, &os->eth.tx_multicast,
3250                             &ns->eth.tx_multicast);
3251         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3252                             I40E_GLPRT_BPTCL(hw->port),
3253                             pf->offset_loaded, &os->eth.tx_broadcast,
3254                             &ns->eth.tx_broadcast);
3255         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3256                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3257
3258         /* exclude internal tx bytes
3259          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3260          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3261          * value.
3262          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3263          */
3264         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3265                 ns->eth.tx_bytes = 0;
3266         else
3267                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3268
3269         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3270                 ns->eth.tx_unicast = 0;
3271         else
3272                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3273
3274         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3275                 ns->eth.tx_multicast = 0;
3276         else
3277                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3278
3279         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3280                 ns->eth.tx_broadcast = 0;
3281         else
3282                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3283
3284         /* GLPRT_TEPC not supported */
3285
3286         /* additional port specific stats */
3287         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3288                             pf->offset_loaded, &os->tx_dropped_link_down,
3289                             &ns->tx_dropped_link_down);
3290         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3291                             pf->offset_loaded, &os->crc_errors,
3292                             &ns->crc_errors);
3293         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3294                             pf->offset_loaded, &os->illegal_bytes,
3295                             &ns->illegal_bytes);
3296         /* GLPRT_ERRBC not supported */
3297         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3298                             pf->offset_loaded, &os->mac_local_faults,
3299                             &ns->mac_local_faults);
3300         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3301                             pf->offset_loaded, &os->mac_remote_faults,
3302                             &ns->mac_remote_faults);
3303         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3304                             pf->offset_loaded, &os->rx_length_errors,
3305                             &ns->rx_length_errors);
3306         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3307                             pf->offset_loaded, &os->link_xon_rx,
3308                             &ns->link_xon_rx);
3309         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3310                             pf->offset_loaded, &os->link_xoff_rx,
3311                             &ns->link_xoff_rx);
3312         for (i = 0; i < 8; i++) {
3313                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3314                                     pf->offset_loaded,
3315                                     &os->priority_xon_rx[i],
3316                                     &ns->priority_xon_rx[i]);
3317                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3318                                     pf->offset_loaded,
3319                                     &os->priority_xoff_rx[i],
3320                                     &ns->priority_xoff_rx[i]);
3321         }
3322         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3323                             pf->offset_loaded, &os->link_xon_tx,
3324                             &ns->link_xon_tx);
3325         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3326                             pf->offset_loaded, &os->link_xoff_tx,
3327                             &ns->link_xoff_tx);
3328         for (i = 0; i < 8; i++) {
3329                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3330                                     pf->offset_loaded,
3331                                     &os->priority_xon_tx[i],
3332                                     &ns->priority_xon_tx[i]);
3333                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3334                                     pf->offset_loaded,
3335                                     &os->priority_xoff_tx[i],
3336                                     &ns->priority_xoff_tx[i]);
3337                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3338                                     pf->offset_loaded,
3339                                     &os->priority_xon_2_xoff[i],
3340                                     &ns->priority_xon_2_xoff[i]);
3341         }
3342         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3343                             I40E_GLPRT_PRC64L(hw->port),
3344                             pf->offset_loaded, &os->rx_size_64,
3345                             &ns->rx_size_64);
3346         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3347                             I40E_GLPRT_PRC127L(hw->port),
3348                             pf->offset_loaded, &os->rx_size_127,
3349                             &ns->rx_size_127);
3350         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3351                             I40E_GLPRT_PRC255L(hw->port),
3352                             pf->offset_loaded, &os->rx_size_255,
3353                             &ns->rx_size_255);
3354         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3355                             I40E_GLPRT_PRC511L(hw->port),
3356                             pf->offset_loaded, &os->rx_size_511,
3357                             &ns->rx_size_511);
3358         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3359                             I40E_GLPRT_PRC1023L(hw->port),
3360                             pf->offset_loaded, &os->rx_size_1023,
3361                             &ns->rx_size_1023);
3362         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3363                             I40E_GLPRT_PRC1522L(hw->port),
3364                             pf->offset_loaded, &os->rx_size_1522,
3365                             &ns->rx_size_1522);
3366         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3367                             I40E_GLPRT_PRC9522L(hw->port),
3368                             pf->offset_loaded, &os->rx_size_big,
3369                             &ns->rx_size_big);
3370         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3371                             pf->offset_loaded, &os->rx_undersize,
3372                             &ns->rx_undersize);
3373         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3374                             pf->offset_loaded, &os->rx_fragments,
3375                             &ns->rx_fragments);
3376         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3377                             pf->offset_loaded, &os->rx_oversize,
3378                             &ns->rx_oversize);
3379         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3380                             pf->offset_loaded, &os->rx_jabber,
3381                             &ns->rx_jabber);
3382         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3383                             I40E_GLPRT_PTC64L(hw->port),
3384                             pf->offset_loaded, &os->tx_size_64,
3385                             &ns->tx_size_64);
3386         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3387                             I40E_GLPRT_PTC127L(hw->port),
3388                             pf->offset_loaded, &os->tx_size_127,
3389                             &ns->tx_size_127);
3390         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3391                             I40E_GLPRT_PTC255L(hw->port),
3392                             pf->offset_loaded, &os->tx_size_255,
3393                             &ns->tx_size_255);
3394         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3395                             I40E_GLPRT_PTC511L(hw->port),
3396                             pf->offset_loaded, &os->tx_size_511,
3397                             &ns->tx_size_511);
3398         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3399                             I40E_GLPRT_PTC1023L(hw->port),
3400                             pf->offset_loaded, &os->tx_size_1023,
3401                             &ns->tx_size_1023);
3402         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3403                             I40E_GLPRT_PTC1522L(hw->port),
3404                             pf->offset_loaded, &os->tx_size_1522,
3405                             &ns->tx_size_1522);
3406         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3407                             I40E_GLPRT_PTC9522L(hw->port),
3408                             pf->offset_loaded, &os->tx_size_big,
3409                             &ns->tx_size_big);
3410         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3411                            pf->offset_loaded,
3412                            &os->fd_sb_match, &ns->fd_sb_match);
3413         /* GLPRT_MSPDC not supported */
3414         /* GLPRT_XEC not supported */
3415
3416         pf->offset_loaded = true;
3417
3418         if (pf->main_vsi)
3419                 i40e_update_vsi_stats(pf->main_vsi);
3420 }
3421
3422 /* Get all statistics of a port */
3423 static int
3424 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3425 {
3426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3429         struct i40e_vsi *vsi;
3430         unsigned i;
3431
3432         /* call read registers - updates values, now write them to struct */
3433         i40e_read_stats_registers(pf, hw);
3434
3435         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3436                         pf->main_vsi->eth_stats.rx_multicast +
3437                         pf->main_vsi->eth_stats.rx_broadcast -
3438                         pf->main_vsi->eth_stats.rx_discards;
3439         stats->opackets = ns->eth.tx_unicast +
3440                         ns->eth.tx_multicast +
3441                         ns->eth.tx_broadcast;
3442         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3443         stats->obytes   = ns->eth.tx_bytes;
3444         stats->oerrors  = ns->eth.tx_errors +
3445                         pf->main_vsi->eth_stats.tx_errors;
3446
3447         /* Rx Errors */
3448         stats->imissed  = ns->eth.rx_discards +
3449                         pf->main_vsi->eth_stats.rx_discards;
3450         stats->ierrors  = ns->crc_errors +
3451                         ns->rx_length_errors + ns->rx_undersize +
3452                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3453
3454         if (pf->vfs) {
3455                 for (i = 0; i < pf->vf_num; i++) {
3456                         vsi = pf->vfs[i].vsi;
3457                         i40e_update_vsi_stats(vsi);
3458
3459                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3460                                         vsi->eth_stats.rx_multicast +
3461                                         vsi->eth_stats.rx_broadcast -
3462                                         vsi->eth_stats.rx_discards);
3463                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3464                         stats->oerrors  += vsi->eth_stats.tx_errors;
3465                         stats->imissed  += vsi->eth_stats.rx_discards;
3466                 }
3467         }
3468
3469         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3470         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3471         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3472         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3473         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3474         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3475         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3476                     ns->eth.rx_unknown_protocol);
3477         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3478         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3479         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3480         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3481         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3482         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3483
3484         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3485                     ns->tx_dropped_link_down);
3486         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3487         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3488                     ns->illegal_bytes);
3489         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3490         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3491                     ns->mac_local_faults);
3492         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3493                     ns->mac_remote_faults);
3494         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3495                     ns->rx_length_errors);
3496         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3497         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3498         for (i = 0; i < 8; i++) {
3499                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3500                                 i, ns->priority_xon_rx[i]);
3501                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3502                                 i, ns->priority_xoff_rx[i]);
3503         }
3504         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3505         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3506         for (i = 0; i < 8; i++) {
3507                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3508                                 i, ns->priority_xon_tx[i]);
3509                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3510                                 i, ns->priority_xoff_tx[i]);
3511                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3512                                 i, ns->priority_xon_2_xoff[i]);
3513         }
3514         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3515         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3516         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3517         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3518         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3519         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3520         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3521         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3522         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3523         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3524         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3525         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3526         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3527         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3528         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3529         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3530         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3531         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3532         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3533                         ns->mac_short_packet_dropped);
3534         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3535                     ns->checksum_error);
3536         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3537         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3538         return 0;
3539 }
3540
3541 /* Reset the statistics */
3542 static int
3543 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3544 {
3545         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3546         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3547
3548         /* Mark PF and VSI stats to update the offset, aka "reset" */
3549         pf->offset_loaded = false;
3550         if (pf->main_vsi)
3551                 pf->main_vsi->offset_loaded = false;
3552
3553         /* read the stats, reading current register values into offset */
3554         i40e_read_stats_registers(pf, hw);
3555
3556         return 0;
3557 }
3558
3559 static uint32_t
3560 i40e_xstats_calc_num(void)
3561 {
3562         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3563                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3564                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3565 }
3566
3567 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3568                                      struct rte_eth_xstat_name *xstats_names,
3569                                      __rte_unused unsigned limit)
3570 {
3571         unsigned count = 0;
3572         unsigned i, prio;
3573
3574         if (xstats_names == NULL)
3575                 return i40e_xstats_calc_num();
3576
3577         /* Note: limit checked in rte_eth_xstats_names() */
3578
3579         /* Get stats from i40e_eth_stats struct */
3580         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3581                 strlcpy(xstats_names[count].name,
3582                         rte_i40e_stats_strings[i].name,
3583                         sizeof(xstats_names[count].name));
3584                 count++;
3585         }
3586
3587         /* Get individiual stats from i40e_hw_port struct */
3588         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3589                 strlcpy(xstats_names[count].name,
3590                         rte_i40e_hw_port_strings[i].name,
3591                         sizeof(xstats_names[count].name));
3592                 count++;
3593         }
3594
3595         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3596                 for (prio = 0; prio < 8; prio++) {
3597                         snprintf(xstats_names[count].name,
3598                                  sizeof(xstats_names[count].name),
3599                                  "rx_priority%u_%s", prio,
3600                                  rte_i40e_rxq_prio_strings[i].name);
3601                         count++;
3602                 }
3603         }
3604
3605         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3606                 for (prio = 0; prio < 8; prio++) {
3607                         snprintf(xstats_names[count].name,
3608                                  sizeof(xstats_names[count].name),
3609                                  "tx_priority%u_%s", prio,
3610                                  rte_i40e_txq_prio_strings[i].name);
3611                         count++;
3612                 }
3613         }
3614         return count;
3615 }
3616
3617 static int
3618 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3619                     unsigned n)
3620 {
3621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3622         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623         unsigned i, count, prio;
3624         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3625
3626         count = i40e_xstats_calc_num();
3627         if (n < count)
3628                 return count;
3629
3630         i40e_read_stats_registers(pf, hw);
3631
3632         if (xstats == NULL)
3633                 return 0;
3634
3635         count = 0;
3636
3637         /* Get stats from i40e_eth_stats struct */
3638         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3639                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3640                         rte_i40e_stats_strings[i].offset);
3641                 xstats[count].id = count;
3642                 count++;
3643         }
3644
3645         /* Get individiual stats from i40e_hw_port struct */
3646         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3647                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3648                         rte_i40e_hw_port_strings[i].offset);
3649                 xstats[count].id = count;
3650                 count++;
3651         }
3652
3653         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3654                 for (prio = 0; prio < 8; prio++) {
3655                         xstats[count].value =
3656                                 *(uint64_t *)(((char *)hw_stats) +
3657                                 rte_i40e_rxq_prio_strings[i].offset +
3658                                 (sizeof(uint64_t) * prio));
3659                         xstats[count].id = count;
3660                         count++;
3661                 }
3662         }
3663
3664         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3665                 for (prio = 0; prio < 8; prio++) {
3666                         xstats[count].value =
3667                                 *(uint64_t *)(((char *)hw_stats) +
3668                                 rte_i40e_txq_prio_strings[i].offset +
3669                                 (sizeof(uint64_t) * prio));
3670                         xstats[count].id = count;
3671                         count++;
3672                 }
3673         }
3674
3675         return count;
3676 }
3677
3678 static int
3679 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3680 {
3681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682         u32 full_ver;
3683         u8 ver, patch;
3684         u16 build;
3685         int ret;
3686
3687         full_ver = hw->nvm.oem_ver;
3688         ver = (u8)(full_ver >> 24);
3689         build = (u16)((full_ver >> 8) & 0xffff);
3690         patch = (u8)(full_ver & 0xff);
3691
3692         ret = snprintf(fw_version, fw_size,
3693                  "%d.%d%d 0x%08x %d.%d.%d",
3694                  ((hw->nvm.version >> 12) & 0xf),
3695                  ((hw->nvm.version >> 4) & 0xff),
3696                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3697                  ver, build, patch);
3698
3699         ret += 1; /* add the size of '\0' */
3700         if (fw_size < (u32)ret)
3701                 return ret;
3702         else
3703                 return 0;
3704 }
3705
3706 /*
3707  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3708  * the Rx data path does not hang if the FW LLDP is stopped.
3709  * return true if lldp need to stop
3710  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3711  */
3712 static bool
3713 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3714 {
3715         double nvm_ver;
3716         char ver_str[64] = {0};
3717         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3718
3719         i40e_fw_version_get(dev, ver_str, 64);
3720         nvm_ver = atof(ver_str);
3721         if ((hw->mac.type == I40E_MAC_X722 ||
3722              hw->mac.type == I40E_MAC_X722_VF) &&
3723              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3724                 return true;
3725         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3726                 return true;
3727
3728         return false;
3729 }
3730
3731 static int
3732 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3733 {
3734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3736         struct i40e_vsi *vsi = pf->main_vsi;
3737         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3738
3739         dev_info->max_rx_queues = vsi->nb_qps;
3740         dev_info->max_tx_queues = vsi->nb_qps;
3741         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3742         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3743         dev_info->max_mac_addrs = vsi->max_macaddrs;
3744         dev_info->max_vfs = pci_dev->max_vfs;
3745         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3746         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3747         dev_info->rx_queue_offload_capa = 0;
3748         dev_info->rx_offload_capa =
3749                 DEV_RX_OFFLOAD_VLAN_STRIP |
3750                 DEV_RX_OFFLOAD_QINQ_STRIP |
3751                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3752                 DEV_RX_OFFLOAD_UDP_CKSUM |
3753                 DEV_RX_OFFLOAD_TCP_CKSUM |
3754                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3755                 DEV_RX_OFFLOAD_KEEP_CRC |
3756                 DEV_RX_OFFLOAD_SCATTER |
3757                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3758                 DEV_RX_OFFLOAD_VLAN_FILTER |
3759                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3760                 DEV_RX_OFFLOAD_RSS_HASH;
3761
3762         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3763         dev_info->tx_offload_capa =
3764                 DEV_TX_OFFLOAD_VLAN_INSERT |
3765                 DEV_TX_OFFLOAD_QINQ_INSERT |
3766                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3767                 DEV_TX_OFFLOAD_UDP_CKSUM |
3768                 DEV_TX_OFFLOAD_TCP_CKSUM |
3769                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3770                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3771                 DEV_TX_OFFLOAD_TCP_TSO |
3772                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3773                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3774                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3775                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3776                 DEV_TX_OFFLOAD_MULTI_SEGS |
3777                 dev_info->tx_queue_offload_capa;
3778         dev_info->dev_capa =
3779                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3780                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3781
3782         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3783                                                 sizeof(uint32_t);
3784         dev_info->reta_size = pf->hash_lut_size;
3785         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3786
3787         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3788                 .rx_thresh = {
3789                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3790                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3791                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3792                 },
3793                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3794                 .rx_drop_en = 0,
3795                 .offloads = 0,
3796         };
3797
3798         dev_info->default_txconf = (struct rte_eth_txconf) {
3799                 .tx_thresh = {
3800                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3801                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3802                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3803                 },
3804                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3805                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3806                 .offloads = 0,
3807         };
3808
3809         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3810                 .nb_max = I40E_MAX_RING_DESC,
3811                 .nb_min = I40E_MIN_RING_DESC,
3812                 .nb_align = I40E_ALIGN_RING_DESC,
3813         };
3814
3815         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3816                 .nb_max = I40E_MAX_RING_DESC,
3817                 .nb_min = I40E_MIN_RING_DESC,
3818                 .nb_align = I40E_ALIGN_RING_DESC,
3819                 .nb_seg_max = I40E_TX_MAX_SEG,
3820                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3821         };
3822
3823         if (pf->flags & I40E_FLAG_VMDQ) {
3824                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3825                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3826                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3827                                                 pf->max_nb_vmdq_vsi;
3828                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3829                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3830                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3831         }
3832
3833         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3834                 /* For XL710 */
3835                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3836                 dev_info->default_rxportconf.nb_queues = 2;
3837                 dev_info->default_txportconf.nb_queues = 2;
3838                 if (dev->data->nb_rx_queues == 1)
3839                         dev_info->default_rxportconf.ring_size = 2048;
3840                 else
3841                         dev_info->default_rxportconf.ring_size = 1024;
3842                 if (dev->data->nb_tx_queues == 1)
3843                         dev_info->default_txportconf.ring_size = 1024;
3844                 else
3845                         dev_info->default_txportconf.ring_size = 512;
3846
3847         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3848                 /* For XXV710 */
3849                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3850                 dev_info->default_rxportconf.nb_queues = 1;
3851                 dev_info->default_txportconf.nb_queues = 1;
3852                 dev_info->default_rxportconf.ring_size = 256;
3853                 dev_info->default_txportconf.ring_size = 256;
3854         } else {
3855                 /* For X710 */
3856                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3857                 dev_info->default_rxportconf.nb_queues = 1;
3858                 dev_info->default_txportconf.nb_queues = 1;
3859                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3860                         dev_info->default_rxportconf.ring_size = 512;
3861                         dev_info->default_txportconf.ring_size = 256;
3862                 } else {
3863                         dev_info->default_rxportconf.ring_size = 256;
3864                         dev_info->default_txportconf.ring_size = 256;
3865                 }
3866         }
3867         dev_info->default_rxportconf.burst_size = 32;
3868         dev_info->default_txportconf.burst_size = 32;
3869
3870         return 0;
3871 }
3872
3873 static int
3874 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3875 {
3876         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3877         struct i40e_vsi *vsi = pf->main_vsi;
3878         PMD_INIT_FUNC_TRACE();
3879
3880         if (on)
3881                 return i40e_vsi_add_vlan(vsi, vlan_id);
3882         else
3883                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3884 }
3885
3886 static int
3887 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3888                                 enum rte_vlan_type vlan_type,
3889                                 uint16_t tpid, int qinq)
3890 {
3891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3892         uint64_t reg_r = 0;
3893         uint64_t reg_w = 0;
3894         uint16_t reg_id = 3;
3895         int ret;
3896
3897         if (qinq) {
3898                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3899                         reg_id = 2;
3900         }
3901
3902         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3903                                           &reg_r, NULL);
3904         if (ret != I40E_SUCCESS) {
3905                 PMD_DRV_LOG(ERR,
3906                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3907                            reg_id);
3908                 return -EIO;
3909         }
3910         PMD_DRV_LOG(DEBUG,
3911                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3912                     reg_id, reg_r);
3913
3914         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3915         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3916         if (reg_r == reg_w) {
3917                 PMD_DRV_LOG(DEBUG, "No need to write");
3918                 return 0;
3919         }
3920
3921         ret = i40e_aq_debug_write_global_register(hw,
3922                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3923                                            reg_w, NULL);
3924         if (ret != I40E_SUCCESS) {
3925                 PMD_DRV_LOG(ERR,
3926                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3927                             reg_id);
3928                 return -EIO;
3929         }
3930         PMD_DRV_LOG(DEBUG,
3931                     "Global register 0x%08x is changed with value 0x%08x",
3932                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3933
3934         return 0;
3935 }
3936
3937 static int
3938 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3939                    enum rte_vlan_type vlan_type,
3940                    uint16_t tpid)
3941 {
3942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3944         int qinq = dev->data->dev_conf.rxmode.offloads &
3945                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3946         int ret = 0;
3947
3948         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3949              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3950             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3951                 PMD_DRV_LOG(ERR,
3952                             "Unsupported vlan type.");
3953                 return -EINVAL;
3954         }
3955
3956         if (pf->support_multi_driver) {
3957                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3958                 return -ENOTSUP;
3959         }
3960
3961         /* 802.1ad frames ability is added in NVM API 1.7*/
3962         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3963                 if (qinq) {
3964                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3965                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3966                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3967                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3968                 } else {
3969                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3970                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3971                 }
3972                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3973                 if (ret != I40E_SUCCESS) {
3974                         PMD_DRV_LOG(ERR,
3975                                     "Set switch config failed aq_err: %d",
3976                                     hw->aq.asq_last_status);
3977                         ret = -EIO;
3978                 }
3979         } else
3980                 /* If NVM API < 1.7, keep the register setting */
3981                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3982                                                       tpid, qinq);
3983
3984         return ret;
3985 }
3986
3987 /* Configure outer vlan stripping on or off in QinQ mode */
3988 static int
3989 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3990 {
3991         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3992         int ret = I40E_SUCCESS;
3993         uint32_t reg;
3994
3995         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3996                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3997                 return -EINVAL;
3998         }
3999
4000         /* Configure for outer VLAN RX stripping */
4001         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4002
4003         if (on)
4004                 reg |= I40E_VSI_TSR_QINQ_STRIP;
4005         else
4006                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4007
4008         ret = i40e_aq_debug_write_register(hw,
4009                                                    I40E_VSI_TSR(vsi->vsi_id),
4010                                                    reg, NULL);
4011         if (ret < 0) {
4012                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4013                                     vsi->vsi_id);
4014                 return I40E_ERR_CONFIG;
4015         }
4016
4017         return ret;
4018 }
4019
4020 static int
4021 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4022 {
4023         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4024         struct i40e_vsi *vsi = pf->main_vsi;
4025         struct rte_eth_rxmode *rxmode;
4026
4027         rxmode = &dev->data->dev_conf.rxmode;
4028         if (mask & ETH_VLAN_FILTER_MASK) {
4029                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4030                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4031                 else
4032                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4033         }
4034
4035         if (mask & ETH_VLAN_STRIP_MASK) {
4036                 /* Enable or disable VLAN stripping */
4037                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4038                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4039                 else
4040                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4041         }
4042
4043         if (mask & ETH_VLAN_EXTEND_MASK) {
4044                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4045                         i40e_vsi_config_double_vlan(vsi, TRUE);
4046                         /* Set global registers with default ethertype. */
4047                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4048                                            RTE_ETHER_TYPE_VLAN);
4049                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4050                                            RTE_ETHER_TYPE_VLAN);
4051                 }
4052                 else
4053                         i40e_vsi_config_double_vlan(vsi, FALSE);
4054         }
4055
4056         if (mask & ETH_QINQ_STRIP_MASK) {
4057                 /* Enable or disable outer VLAN stripping */
4058                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4059                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4060                 else
4061                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4062         }
4063
4064         return 0;
4065 }
4066
4067 static void
4068 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4069                           __rte_unused uint16_t queue,
4070                           __rte_unused int on)
4071 {
4072         PMD_INIT_FUNC_TRACE();
4073 }
4074
4075 static int
4076 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4077 {
4078         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4079         struct i40e_vsi *vsi = pf->main_vsi;
4080         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4081         struct i40e_vsi_vlan_pvid_info info;
4082
4083         memset(&info, 0, sizeof(info));
4084         info.on = on;
4085         if (info.on)
4086                 info.config.pvid = pvid;
4087         else {
4088                 info.config.reject.tagged =
4089                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4090                 info.config.reject.untagged =
4091                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4092         }
4093
4094         return i40e_vsi_vlan_pvid_set(vsi, &info);
4095 }
4096
4097 static int
4098 i40e_dev_led_on(struct rte_eth_dev *dev)
4099 {
4100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4101         uint32_t mode = i40e_led_get(hw);
4102
4103         if (mode == 0)
4104                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4105
4106         return 0;
4107 }
4108
4109 static int
4110 i40e_dev_led_off(struct rte_eth_dev *dev)
4111 {
4112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4113         uint32_t mode = i40e_led_get(hw);
4114
4115         if (mode != 0)
4116                 i40e_led_set(hw, 0, false);
4117
4118         return 0;
4119 }
4120
4121 static int
4122 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4123 {
4124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4126
4127         fc_conf->pause_time = pf->fc_conf.pause_time;
4128
4129         /* read out from register, in case they are modified by other port */
4130         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4131                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4132         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4133                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4134
4135         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4136         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4137
4138          /* Return current mode according to actual setting*/
4139         switch (hw->fc.current_mode) {
4140         case I40E_FC_FULL:
4141                 fc_conf->mode = RTE_FC_FULL;
4142                 break;
4143         case I40E_FC_TX_PAUSE:
4144                 fc_conf->mode = RTE_FC_TX_PAUSE;
4145                 break;
4146         case I40E_FC_RX_PAUSE:
4147                 fc_conf->mode = RTE_FC_RX_PAUSE;
4148                 break;
4149         case I40E_FC_NONE:
4150         default:
4151                 fc_conf->mode = RTE_FC_NONE;
4152         };
4153
4154         return 0;
4155 }
4156
4157 static int
4158 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4159 {
4160         uint32_t mflcn_reg, fctrl_reg, reg;
4161         uint32_t max_high_water;
4162         uint8_t i, aq_failure;
4163         int err;
4164         struct i40e_hw *hw;
4165         struct i40e_pf *pf;
4166         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4167                 [RTE_FC_NONE] = I40E_FC_NONE,
4168                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4169                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4170                 [RTE_FC_FULL] = I40E_FC_FULL
4171         };
4172
4173         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4174
4175         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4176         if ((fc_conf->high_water > max_high_water) ||
4177                         (fc_conf->high_water < fc_conf->low_water)) {
4178                 PMD_INIT_LOG(ERR,
4179                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4180                         max_high_water);
4181                 return -EINVAL;
4182         }
4183
4184         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4185         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4186         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4187
4188         pf->fc_conf.pause_time = fc_conf->pause_time;
4189         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4190         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4191
4192         PMD_INIT_FUNC_TRACE();
4193
4194         /* All the link flow control related enable/disable register
4195          * configuration is handle by the F/W
4196          */
4197         err = i40e_set_fc(hw, &aq_failure, true);
4198         if (err < 0)
4199                 return -ENOSYS;
4200
4201         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4202                 /* Configure flow control refresh threshold,
4203                  * the value for stat_tx_pause_refresh_timer[8]
4204                  * is used for global pause operation.
4205                  */
4206
4207                 I40E_WRITE_REG(hw,
4208                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4209                                pf->fc_conf.pause_time);
4210
4211                 /* configure the timer value included in transmitted pause
4212                  * frame,
4213                  * the value for stat_tx_pause_quanta[8] is used for global
4214                  * pause operation
4215                  */
4216                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4217                                pf->fc_conf.pause_time);
4218
4219                 fctrl_reg = I40E_READ_REG(hw,
4220                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4221
4222                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4223                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4224                 else
4225                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4226
4227                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4228                                fctrl_reg);
4229         } else {
4230                 /* Configure pause time (2 TCs per register) */
4231                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4232                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4233                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4234
4235                 /* Configure flow control refresh threshold value */
4236                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4237                                pf->fc_conf.pause_time / 2);
4238
4239                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4240
4241                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4242                  *depending on configuration
4243                  */
4244                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4245                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4246                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4247                 } else {
4248                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4249                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4250                 }
4251
4252                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4253         }
4254
4255         if (!pf->support_multi_driver) {
4256                 /* config water marker both based on the packets and bytes */
4257                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4258                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4259                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4260                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4261                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4262                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4263                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4264                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4265                                   << I40E_KILOSHIFT);
4266                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4267                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4268                                    << I40E_KILOSHIFT);
4269         } else {
4270                 PMD_DRV_LOG(ERR,
4271                             "Water marker configuration is not supported.");
4272         }
4273
4274         I40E_WRITE_FLUSH(hw);
4275
4276         return 0;
4277 }
4278
4279 static int
4280 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4281                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4282 {
4283         PMD_INIT_FUNC_TRACE();
4284
4285         return -ENOSYS;
4286 }
4287
4288 /* Add a MAC address, and update filters */
4289 static int
4290 i40e_macaddr_add(struct rte_eth_dev *dev,
4291                  struct rte_ether_addr *mac_addr,
4292                  __rte_unused uint32_t index,
4293                  uint32_t pool)
4294 {
4295         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4296         struct i40e_mac_filter_info mac_filter;
4297         struct i40e_vsi *vsi;
4298         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4299         int ret;
4300
4301         /* If VMDQ not enabled or configured, return */
4302         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4303                           !pf->nb_cfg_vmdq_vsi)) {
4304                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4305                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4306                         pool);
4307                 return -ENOTSUP;
4308         }
4309
4310         if (pool > pf->nb_cfg_vmdq_vsi) {
4311                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4312                                 pool, pf->nb_cfg_vmdq_vsi);
4313                 return -EINVAL;
4314         }
4315
4316         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4317         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4318                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4319         else
4320                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4321
4322         if (pool == 0)
4323                 vsi = pf->main_vsi;
4324         else
4325                 vsi = pf->vmdq[pool - 1].vsi;
4326
4327         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4328         if (ret != I40E_SUCCESS) {
4329                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4330                 return -ENODEV;
4331         }
4332         return 0;
4333 }
4334
4335 /* Remove a MAC address, and update filters */
4336 static void
4337 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4338 {
4339         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4340         struct i40e_vsi *vsi;
4341         struct rte_eth_dev_data *data = dev->data;
4342         struct rte_ether_addr *macaddr;
4343         int ret;
4344         uint32_t i;
4345         uint64_t pool_sel;
4346
4347         macaddr = &(data->mac_addrs[index]);
4348
4349         pool_sel = dev->data->mac_pool_sel[index];
4350
4351         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4352                 if (pool_sel & (1ULL << i)) {
4353                         if (i == 0)
4354                                 vsi = pf->main_vsi;
4355                         else {
4356                                 /* No VMDQ pool enabled or configured */
4357                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4358                                         (i > pf->nb_cfg_vmdq_vsi)) {
4359                                         PMD_DRV_LOG(ERR,
4360                                                 "No VMDQ pool enabled/configured");
4361                                         return;
4362                                 }
4363                                 vsi = pf->vmdq[i - 1].vsi;
4364                         }
4365                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4366
4367                         if (ret) {
4368                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4369                                 return;
4370                         }
4371                 }
4372         }
4373 }
4374
4375 /* Set perfect match or hash match of MAC and VLAN for a VF */
4376 static int
4377 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4378                  struct rte_eth_mac_filter *filter,
4379                  bool add)
4380 {
4381         struct i40e_hw *hw;
4382         struct i40e_mac_filter_info mac_filter;
4383         struct rte_ether_addr old_mac;
4384         struct rte_ether_addr *new_mac;
4385         struct i40e_pf_vf *vf = NULL;
4386         uint16_t vf_id;
4387         int ret;
4388
4389         if (pf == NULL) {
4390                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4391                 return -EINVAL;
4392         }
4393         hw = I40E_PF_TO_HW(pf);
4394
4395         if (filter == NULL) {
4396                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4397                 return -EINVAL;
4398         }
4399
4400         new_mac = &filter->mac_addr;
4401
4402         if (rte_is_zero_ether_addr(new_mac)) {
4403                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4404                 return -EINVAL;
4405         }
4406
4407         vf_id = filter->dst_id;
4408
4409         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4410                 PMD_DRV_LOG(ERR, "Invalid argument.");
4411                 return -EINVAL;
4412         }
4413         vf = &pf->vfs[vf_id];
4414
4415         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4416                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4417                 return -EINVAL;
4418         }
4419
4420         if (add) {
4421                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4422                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4423                                 RTE_ETHER_ADDR_LEN);
4424                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4425                                  RTE_ETHER_ADDR_LEN);
4426
4427                 mac_filter.filter_type = filter->filter_type;
4428                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4429                 if (ret != I40E_SUCCESS) {
4430                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4431                         return -1;
4432                 }
4433                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4434         } else {
4435                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4436                                 RTE_ETHER_ADDR_LEN);
4437                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4438                 if (ret != I40E_SUCCESS) {
4439                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4440                         return -1;
4441                 }
4442
4443                 /* Clear device address as it has been removed */
4444                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4445                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4446         }
4447
4448         return 0;
4449 }
4450
4451 /* MAC filter handle */
4452 static int
4453 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4454                 void *arg)
4455 {
4456         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4457         struct rte_eth_mac_filter *filter;
4458         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4459         int ret = I40E_NOT_SUPPORTED;
4460
4461         filter = (struct rte_eth_mac_filter *)(arg);
4462
4463         switch (filter_op) {
4464         case RTE_ETH_FILTER_NOP:
4465                 ret = I40E_SUCCESS;
4466                 break;
4467         case RTE_ETH_FILTER_ADD:
4468                 i40e_pf_disable_irq0(hw);
4469                 if (filter->is_vf)
4470                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4471                 i40e_pf_enable_irq0(hw);
4472                 break;
4473         case RTE_ETH_FILTER_DELETE:
4474                 i40e_pf_disable_irq0(hw);
4475                 if (filter->is_vf)
4476                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4477                 i40e_pf_enable_irq0(hw);
4478                 break;
4479         default:
4480                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4481                 ret = I40E_ERR_PARAM;
4482                 break;
4483         }
4484
4485         return ret;
4486 }
4487
4488 static int
4489 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4490 {
4491         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4492         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4493         uint32_t reg;
4494         int ret;
4495
4496         if (!lut)
4497                 return -EINVAL;
4498
4499         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4500                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4501                                           vsi->type != I40E_VSI_SRIOV,
4502                                           lut, lut_size);
4503                 if (ret) {
4504                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4505                         return ret;
4506                 }
4507         } else {
4508                 uint32_t *lut_dw = (uint32_t *)lut;
4509                 uint16_t i, lut_size_dw = lut_size / 4;
4510
4511                 if (vsi->type == I40E_VSI_SRIOV) {
4512                         for (i = 0; i <= lut_size_dw; i++) {
4513                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4514                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4515                         }
4516                 } else {
4517                         for (i = 0; i < lut_size_dw; i++)
4518                                 lut_dw[i] = I40E_READ_REG(hw,
4519                                                           I40E_PFQF_HLUT(i));
4520                 }
4521         }
4522
4523         return 0;
4524 }
4525
4526 int
4527 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4528 {
4529         struct i40e_pf *pf;
4530         struct i40e_hw *hw;
4531         int ret;
4532
4533         if (!vsi || !lut)
4534                 return -EINVAL;
4535
4536         pf = I40E_VSI_TO_PF(vsi);
4537         hw = I40E_VSI_TO_HW(vsi);
4538
4539         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4540                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4541                                           vsi->type != I40E_VSI_SRIOV,
4542                                           lut, lut_size);
4543                 if (ret) {
4544                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4545                         return ret;
4546                 }
4547         } else {
4548                 uint32_t *lut_dw = (uint32_t *)lut;
4549                 uint16_t i, lut_size_dw = lut_size / 4;
4550
4551                 if (vsi->type == I40E_VSI_SRIOV) {
4552                         for (i = 0; i < lut_size_dw; i++)
4553                                 I40E_WRITE_REG(
4554                                         hw,
4555                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4556                                         lut_dw[i]);
4557                 } else {
4558                         for (i = 0; i < lut_size_dw; i++)
4559                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4560                                                lut_dw[i]);
4561                 }
4562                 I40E_WRITE_FLUSH(hw);
4563         }
4564
4565         return 0;
4566 }
4567
4568 static int
4569 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4570                          struct rte_eth_rss_reta_entry64 *reta_conf,
4571                          uint16_t reta_size)
4572 {
4573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4574         uint16_t i, lut_size = pf->hash_lut_size;
4575         uint16_t idx, shift;
4576         uint8_t *lut;
4577         int ret;
4578
4579         if (reta_size != lut_size ||
4580                 reta_size > ETH_RSS_RETA_SIZE_512) {
4581                 PMD_DRV_LOG(ERR,
4582                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4583                         reta_size, lut_size);
4584                 return -EINVAL;
4585         }
4586
4587         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4588         if (!lut) {
4589                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4590                 return -ENOMEM;
4591         }
4592         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4593         if (ret)
4594                 goto out;
4595         for (i = 0; i < reta_size; i++) {
4596                 idx = i / RTE_RETA_GROUP_SIZE;
4597                 shift = i % RTE_RETA_GROUP_SIZE;
4598                 if (reta_conf[idx].mask & (1ULL << shift))
4599                         lut[i] = reta_conf[idx].reta[shift];
4600         }
4601         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4602
4603         pf->adapter->rss_reta_updated = 1;
4604
4605 out:
4606         rte_free(lut);
4607
4608         return ret;
4609 }
4610
4611 static int
4612 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4613                         struct rte_eth_rss_reta_entry64 *reta_conf,
4614                         uint16_t reta_size)
4615 {
4616         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4617         uint16_t i, lut_size = pf->hash_lut_size;
4618         uint16_t idx, shift;
4619         uint8_t *lut;
4620         int ret;
4621
4622         if (reta_size != lut_size ||
4623                 reta_size > ETH_RSS_RETA_SIZE_512) {
4624                 PMD_DRV_LOG(ERR,
4625                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4626                         reta_size, lut_size);
4627                 return -EINVAL;
4628         }
4629
4630         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4631         if (!lut) {
4632                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4633                 return -ENOMEM;
4634         }
4635
4636         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4637         if (ret)
4638                 goto out;
4639         for (i = 0; i < reta_size; i++) {
4640                 idx = i / RTE_RETA_GROUP_SIZE;
4641                 shift = i % RTE_RETA_GROUP_SIZE;
4642                 if (reta_conf[idx].mask & (1ULL << shift))
4643                         reta_conf[idx].reta[shift] = lut[i];
4644         }
4645
4646 out:
4647         rte_free(lut);
4648
4649         return ret;
4650 }
4651
4652 /**
4653  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4654  * @hw:   pointer to the HW structure
4655  * @mem:  pointer to mem struct to fill out
4656  * @size: size of memory requested
4657  * @alignment: what to align the allocation to
4658  **/
4659 enum i40e_status_code
4660 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4661                         struct i40e_dma_mem *mem,
4662                         u64 size,
4663                         u32 alignment)
4664 {
4665         const struct rte_memzone *mz = NULL;
4666         char z_name[RTE_MEMZONE_NAMESIZE];
4667
4668         if (!mem)
4669                 return I40E_ERR_PARAM;
4670
4671         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4672         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4673                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4674         if (!mz)
4675                 return I40E_ERR_NO_MEMORY;
4676
4677         mem->size = size;
4678         mem->va = mz->addr;
4679         mem->pa = mz->iova;
4680         mem->zone = (const void *)mz;
4681         PMD_DRV_LOG(DEBUG,
4682                 "memzone %s allocated with physical address: %"PRIu64,
4683                 mz->name, mem->pa);
4684
4685         return I40E_SUCCESS;
4686 }
4687
4688 /**
4689  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4690  * @hw:   pointer to the HW structure
4691  * @mem:  ptr to mem struct to free
4692  **/
4693 enum i40e_status_code
4694 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4695                     struct i40e_dma_mem *mem)
4696 {
4697         if (!mem)
4698                 return I40E_ERR_PARAM;
4699
4700         PMD_DRV_LOG(DEBUG,
4701                 "memzone %s to be freed with physical address: %"PRIu64,
4702                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4703         rte_memzone_free((const struct rte_memzone *)mem->zone);
4704         mem->zone = NULL;
4705         mem->va = NULL;
4706         mem->pa = (u64)0;
4707
4708         return I40E_SUCCESS;
4709 }
4710
4711 /**
4712  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4713  * @hw:   pointer to the HW structure
4714  * @mem:  pointer to mem struct to fill out
4715  * @size: size of memory requested
4716  **/
4717 enum i40e_status_code
4718 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4719                          struct i40e_virt_mem *mem,
4720                          u32 size)
4721 {
4722         if (!mem)
4723                 return I40E_ERR_PARAM;
4724
4725         mem->size = size;
4726         mem->va = rte_zmalloc("i40e", size, 0);
4727
4728         if (mem->va)
4729                 return I40E_SUCCESS;
4730         else
4731                 return I40E_ERR_NO_MEMORY;
4732 }
4733
4734 /**
4735  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4736  * @hw:   pointer to the HW structure
4737  * @mem:  pointer to mem struct to free
4738  **/
4739 enum i40e_status_code
4740 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4741                      struct i40e_virt_mem *mem)
4742 {
4743         if (!mem)
4744                 return I40E_ERR_PARAM;
4745
4746         rte_free(mem->va);
4747         mem->va = NULL;
4748
4749         return I40E_SUCCESS;
4750 }
4751
4752 void
4753 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4754 {
4755         rte_spinlock_init(&sp->spinlock);
4756 }
4757
4758 void
4759 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4760 {
4761         rte_spinlock_lock(&sp->spinlock);
4762 }
4763
4764 void
4765 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4766 {
4767         rte_spinlock_unlock(&sp->spinlock);
4768 }
4769
4770 void
4771 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4772 {
4773         return;
4774 }
4775
4776 /**
4777  * Get the hardware capabilities, which will be parsed
4778  * and saved into struct i40e_hw.
4779  */
4780 static int
4781 i40e_get_cap(struct i40e_hw *hw)
4782 {
4783         struct i40e_aqc_list_capabilities_element_resp *buf;
4784         uint16_t len, size = 0;
4785         int ret;
4786
4787         /* Calculate a huge enough buff for saving response data temporarily */
4788         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4789                                                 I40E_MAX_CAP_ELE_NUM;
4790         buf = rte_zmalloc("i40e", len, 0);
4791         if (!buf) {
4792                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4793                 return I40E_ERR_NO_MEMORY;
4794         }
4795
4796         /* Get, parse the capabilities and save it to hw */
4797         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4798                         i40e_aqc_opc_list_func_capabilities, NULL);
4799         if (ret != I40E_SUCCESS)
4800                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4801
4802         /* Free the temporary buffer after being used */
4803         rte_free(buf);
4804
4805         return ret;
4806 }
4807
4808 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4809
4810 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4811                 const char *value,
4812                 void *opaque)
4813 {
4814         struct i40e_pf *pf;
4815         unsigned long num;
4816         char *end;
4817
4818         pf = (struct i40e_pf *)opaque;
4819         RTE_SET_USED(key);
4820
4821         errno = 0;
4822         num = strtoul(value, &end, 0);
4823         if (errno != 0 || end == value || *end != 0) {
4824                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4825                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4826                 return -(EINVAL);
4827         }
4828
4829         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4830                 pf->vf_nb_qp_max = (uint16_t)num;
4831         else
4832                 /* here return 0 to make next valid same argument work */
4833                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4834                             "power of 2 and equal or less than 16 !, Now it is "
4835                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4836
4837         return 0;
4838 }
4839
4840 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4841 {
4842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4843         struct rte_kvargs *kvlist;
4844         int kvargs_count;
4845
4846         /* set default queue number per VF as 4 */
4847         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4848
4849         if (dev->device->devargs == NULL)
4850                 return 0;
4851
4852         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4853         if (kvlist == NULL)
4854                 return -(EINVAL);
4855
4856         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4857         if (!kvargs_count) {
4858                 rte_kvargs_free(kvlist);
4859                 return 0;
4860         }
4861
4862         if (kvargs_count > 1)
4863                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4864                             "the first invalid or last valid one is used !",
4865                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4866
4867         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4868                            i40e_pf_parse_vf_queue_number_handler, pf);
4869
4870         rte_kvargs_free(kvlist);
4871
4872         return 0;
4873 }
4874
4875 static int
4876 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4877 {
4878         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4879         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4880         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4881         uint16_t qp_count = 0, vsi_count = 0;
4882
4883         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4884                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4885                 return -EINVAL;
4886         }
4887
4888         i40e_pf_config_vf_rxq_number(dev);
4889
4890         /* Add the parameter init for LFC */
4891         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4892         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4893         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4894
4895         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4896         pf->max_num_vsi = hw->func_caps.num_vsis;
4897         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4898         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4899
4900         /* FDir queue/VSI allocation */
4901         pf->fdir_qp_offset = 0;
4902         if (hw->func_caps.fd) {
4903                 pf->flags |= I40E_FLAG_FDIR;
4904                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4905         } else {
4906                 pf->fdir_nb_qps = 0;
4907         }
4908         qp_count += pf->fdir_nb_qps;
4909         vsi_count += 1;
4910
4911         /* LAN queue/VSI allocation */
4912         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4913         if (!hw->func_caps.rss) {
4914                 pf->lan_nb_qps = 1;
4915         } else {
4916                 pf->flags |= I40E_FLAG_RSS;
4917                 if (hw->mac.type == I40E_MAC_X722)
4918                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4919                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4920         }
4921         qp_count += pf->lan_nb_qps;
4922         vsi_count += 1;
4923
4924         /* VF queue/VSI allocation */
4925         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4926         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4927                 pf->flags |= I40E_FLAG_SRIOV;
4928                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4929                 pf->vf_num = pci_dev->max_vfs;
4930                 PMD_DRV_LOG(DEBUG,
4931                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4932                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4933         } else {
4934                 pf->vf_nb_qps = 0;
4935                 pf->vf_num = 0;
4936         }
4937         qp_count += pf->vf_nb_qps * pf->vf_num;
4938         vsi_count += pf->vf_num;
4939
4940         /* VMDq queue/VSI allocation */
4941         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4942         pf->vmdq_nb_qps = 0;
4943         pf->max_nb_vmdq_vsi = 0;
4944         if (hw->func_caps.vmdq) {
4945                 if (qp_count < hw->func_caps.num_tx_qp &&
4946                         vsi_count < hw->func_caps.num_vsis) {
4947                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4948                                 qp_count) / pf->vmdq_nb_qp_max;
4949
4950                         /* Limit the maximum number of VMDq vsi to the maximum
4951                          * ethdev can support
4952                          */
4953                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4954                                 hw->func_caps.num_vsis - vsi_count);
4955                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4956                                 ETH_64_POOLS);
4957                         if (pf->max_nb_vmdq_vsi) {
4958                                 pf->flags |= I40E_FLAG_VMDQ;
4959                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4960                                 PMD_DRV_LOG(DEBUG,
4961                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4962                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4963                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4964                         } else {
4965                                 PMD_DRV_LOG(INFO,
4966                                         "No enough queues left for VMDq");
4967                         }
4968                 } else {
4969                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4970                 }
4971         }
4972         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4973         vsi_count += pf->max_nb_vmdq_vsi;
4974
4975         if (hw->func_caps.dcb)
4976                 pf->flags |= I40E_FLAG_DCB;
4977
4978         if (qp_count > hw->func_caps.num_tx_qp) {
4979                 PMD_DRV_LOG(ERR,
4980                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4981                         qp_count, hw->func_caps.num_tx_qp);
4982                 return -EINVAL;
4983         }
4984         if (vsi_count > hw->func_caps.num_vsis) {
4985                 PMD_DRV_LOG(ERR,
4986                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4987                         vsi_count, hw->func_caps.num_vsis);
4988                 return -EINVAL;
4989         }
4990
4991         return 0;
4992 }
4993
4994 static int
4995 i40e_pf_get_switch_config(struct i40e_pf *pf)
4996 {
4997         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4998         struct i40e_aqc_get_switch_config_resp *switch_config;
4999         struct i40e_aqc_switch_config_element_resp *element;
5000         uint16_t start_seid = 0, num_reported;
5001         int ret;
5002
5003         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
5004                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
5005         if (!switch_config) {
5006                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
5007                 return -ENOMEM;
5008         }
5009
5010         /* Get the switch configurations */
5011         ret = i40e_aq_get_switch_config(hw, switch_config,
5012                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
5013         if (ret != I40E_SUCCESS) {
5014                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
5015                 goto fail;
5016         }
5017         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
5018         if (num_reported != 1) { /* The number should be 1 */
5019                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
5020                 goto fail;
5021         }
5022
5023         /* Parse the switch configuration elements */
5024         element = &(switch_config->element[0]);
5025         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
5026                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
5027                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
5028         } else
5029                 PMD_DRV_LOG(INFO, "Unknown element type");
5030
5031 fail:
5032         rte_free(switch_config);
5033
5034         return ret;
5035 }
5036
5037 static int
5038 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
5039                         uint32_t num)
5040 {
5041         struct pool_entry *entry;
5042
5043         if (pool == NULL || num == 0)
5044                 return -EINVAL;
5045
5046         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5047         if (entry == NULL) {
5048                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5049                 return -ENOMEM;
5050         }
5051
5052         /* queue heap initialize */
5053         pool->num_free = num;
5054         pool->num_alloc = 0;
5055         pool->base = base;
5056         LIST_INIT(&pool->alloc_list);
5057         LIST_INIT(&pool->free_list);
5058
5059         /* Initialize element  */
5060         entry->base = 0;
5061         entry->len = num;
5062
5063         LIST_INSERT_HEAD(&pool->free_list, entry, next);
5064         return 0;
5065 }
5066
5067 static void
5068 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5069 {
5070         struct pool_entry *entry, *next_entry;
5071
5072         if (pool == NULL)
5073                 return;
5074
5075         for (entry = LIST_FIRST(&pool->alloc_list);
5076                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5077                         entry = next_entry) {
5078                 LIST_REMOVE(entry, next);
5079                 rte_free(entry);
5080         }
5081
5082         for (entry = LIST_FIRST(&pool->free_list);
5083                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5084                         entry = next_entry) {
5085                 LIST_REMOVE(entry, next);
5086                 rte_free(entry);
5087         }
5088
5089         pool->num_free = 0;
5090         pool->num_alloc = 0;
5091         pool->base = 0;
5092         LIST_INIT(&pool->alloc_list);
5093         LIST_INIT(&pool->free_list);
5094 }
5095
5096 static int
5097 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5098                        uint32_t base)
5099 {
5100         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5101         uint32_t pool_offset;
5102         uint16_t len;
5103         int insert;
5104
5105         if (pool == NULL) {
5106                 PMD_DRV_LOG(ERR, "Invalid parameter");
5107                 return -EINVAL;
5108         }
5109
5110         pool_offset = base - pool->base;
5111         /* Lookup in alloc list */
5112         LIST_FOREACH(entry, &pool->alloc_list, next) {
5113                 if (entry->base == pool_offset) {
5114                         valid_entry = entry;
5115                         LIST_REMOVE(entry, next);
5116                         break;
5117                 }
5118         }
5119
5120         /* Not find, return */
5121         if (valid_entry == NULL) {
5122                 PMD_DRV_LOG(ERR, "Failed to find entry");
5123                 return -EINVAL;
5124         }
5125
5126         /**
5127          * Found it, move it to free list  and try to merge.
5128          * In order to make merge easier, always sort it by qbase.
5129          * Find adjacent prev and last entries.
5130          */
5131         prev = next = NULL;
5132         LIST_FOREACH(entry, &pool->free_list, next) {
5133                 if (entry->base > valid_entry->base) {
5134                         next = entry;
5135                         break;
5136                 }
5137                 prev = entry;
5138         }
5139
5140         insert = 0;
5141         len = valid_entry->len;
5142         /* Try to merge with next one*/
5143         if (next != NULL) {
5144                 /* Merge with next one */
5145                 if (valid_entry->base + len == next->base) {
5146                         next->base = valid_entry->base;
5147                         next->len += len;
5148                         rte_free(valid_entry);
5149                         valid_entry = next;
5150                         insert = 1;
5151                 }
5152         }
5153
5154         if (prev != NULL) {
5155                 /* Merge with previous one */
5156                 if (prev->base + prev->len == valid_entry->base) {
5157                         prev->len += len;
5158                         /* If it merge with next one, remove next node */
5159                         if (insert == 1) {
5160                                 LIST_REMOVE(valid_entry, next);
5161                                 rte_free(valid_entry);
5162                                 valid_entry = NULL;
5163                         } else {
5164                                 rte_free(valid_entry);
5165                                 valid_entry = NULL;
5166                                 insert = 1;
5167                         }
5168                 }
5169         }
5170
5171         /* Not find any entry to merge, insert */
5172         if (insert == 0) {
5173                 if (prev != NULL)
5174                         LIST_INSERT_AFTER(prev, valid_entry, next);
5175                 else if (next != NULL)
5176                         LIST_INSERT_BEFORE(next, valid_entry, next);
5177                 else /* It's empty list, insert to head */
5178                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5179         }
5180
5181         pool->num_free += len;
5182         pool->num_alloc -= len;
5183
5184         return 0;
5185 }
5186
5187 static int
5188 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5189                        uint16_t num)
5190 {
5191         struct pool_entry *entry, *valid_entry;
5192
5193         if (pool == NULL || num == 0) {
5194                 PMD_DRV_LOG(ERR, "Invalid parameter");
5195                 return -EINVAL;
5196         }
5197
5198         if (pool->num_free < num) {
5199                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5200                             num, pool->num_free);
5201                 return -ENOMEM;
5202         }
5203
5204         valid_entry = NULL;
5205         /* Lookup  in free list and find most fit one */
5206         LIST_FOREACH(entry, &pool->free_list, next) {
5207                 if (entry->len >= num) {
5208                         /* Find best one */
5209                         if (entry->len == num) {
5210                                 valid_entry = entry;
5211                                 break;
5212                         }
5213                         if (valid_entry == NULL || valid_entry->len > entry->len)
5214                                 valid_entry = entry;
5215                 }
5216         }
5217
5218         /* Not find one to satisfy the request, return */
5219         if (valid_entry == NULL) {
5220                 PMD_DRV_LOG(ERR, "No valid entry found");
5221                 return -ENOMEM;
5222         }
5223         /**
5224          * The entry have equal queue number as requested,
5225          * remove it from alloc_list.
5226          */
5227         if (valid_entry->len == num) {
5228                 LIST_REMOVE(valid_entry, next);
5229         } else {
5230                 /**
5231                  * The entry have more numbers than requested,
5232                  * create a new entry for alloc_list and minus its
5233                  * queue base and number in free_list.
5234                  */
5235                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5236                 if (entry == NULL) {
5237                         PMD_DRV_LOG(ERR,
5238                                 "Failed to allocate memory for resource pool");
5239                         return -ENOMEM;
5240                 }
5241                 entry->base = valid_entry->base;
5242                 entry->len = num;
5243                 valid_entry->base += num;
5244                 valid_entry->len -= num;
5245                 valid_entry = entry;
5246         }
5247
5248         /* Insert it into alloc list, not sorted */
5249         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5250
5251         pool->num_free -= valid_entry->len;
5252         pool->num_alloc += valid_entry->len;
5253
5254         return valid_entry->base + pool->base;
5255 }
5256
5257 /**
5258  * bitmap_is_subset - Check whether src2 is subset of src1
5259  **/
5260 static inline int
5261 bitmap_is_subset(uint8_t src1, uint8_t src2)
5262 {
5263         return !((src1 ^ src2) & src2);
5264 }
5265
5266 static enum i40e_status_code
5267 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5268 {
5269         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5270
5271         /* If DCB is not supported, only default TC is supported */
5272         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5273                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5274                 return I40E_NOT_SUPPORTED;
5275         }
5276
5277         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5278                 PMD_DRV_LOG(ERR,
5279                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5280                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5281                 return I40E_NOT_SUPPORTED;
5282         }
5283         return I40E_SUCCESS;
5284 }
5285
5286 int
5287 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5288                                 struct i40e_vsi_vlan_pvid_info *info)
5289 {
5290         struct i40e_hw *hw;
5291         struct i40e_vsi_context ctxt;
5292         uint8_t vlan_flags = 0;
5293         int ret;
5294
5295         if (vsi == NULL || info == NULL) {
5296                 PMD_DRV_LOG(ERR, "invalid parameters");
5297                 return I40E_ERR_PARAM;
5298         }
5299
5300         if (info->on) {
5301                 vsi->info.pvid = info->config.pvid;
5302                 /**
5303                  * If insert pvid is enabled, only tagged pkts are
5304                  * allowed to be sent out.
5305                  */
5306                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5307                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5308         } else {
5309                 vsi->info.pvid = 0;
5310                 if (info->config.reject.tagged == 0)
5311                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5312
5313                 if (info->config.reject.untagged == 0)
5314                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5315         }
5316         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5317                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5318         vsi->info.port_vlan_flags |= vlan_flags;
5319         vsi->info.valid_sections =
5320                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5321         memset(&ctxt, 0, sizeof(ctxt));
5322         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5323         ctxt.seid = vsi->seid;
5324
5325         hw = I40E_VSI_TO_HW(vsi);
5326         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5327         if (ret != I40E_SUCCESS)
5328                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5329
5330         return ret;
5331 }
5332
5333 static int
5334 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5335 {
5336         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5337         int i, ret;
5338         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5339
5340         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5341         if (ret != I40E_SUCCESS)
5342                 return ret;
5343
5344         if (!vsi->seid) {
5345                 PMD_DRV_LOG(ERR, "seid not valid");
5346                 return -EINVAL;
5347         }
5348
5349         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5350         tc_bw_data.tc_valid_bits = enabled_tcmap;
5351         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5352                 tc_bw_data.tc_bw_credits[i] =
5353                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5354
5355         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5356         if (ret != I40E_SUCCESS) {
5357                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5358                 return ret;
5359         }
5360
5361         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5362                                         sizeof(vsi->info.qs_handle));
5363         return I40E_SUCCESS;
5364 }
5365
5366 static enum i40e_status_code
5367 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5368                                  struct i40e_aqc_vsi_properties_data *info,
5369                                  uint8_t enabled_tcmap)
5370 {
5371         enum i40e_status_code ret;
5372         int i, total_tc = 0;
5373         uint16_t qpnum_per_tc, bsf, qp_idx;
5374
5375         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5376         if (ret != I40E_SUCCESS)
5377                 return ret;
5378
5379         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5380                 if (enabled_tcmap & (1 << i))
5381                         total_tc++;
5382         if (total_tc == 0)
5383                 total_tc = 1;
5384         vsi->enabled_tc = enabled_tcmap;
5385
5386         /* Number of queues per enabled TC */
5387         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5388         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5389         bsf = rte_bsf32(qpnum_per_tc);
5390
5391         /* Adjust the queue number to actual queues that can be applied */
5392         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5393                 vsi->nb_qps = qpnum_per_tc * total_tc;
5394
5395         /**
5396          * Configure TC and queue mapping parameters, for enabled TC,
5397          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5398          * default queue will serve it.
5399          */
5400         qp_idx = 0;
5401         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5402                 if (vsi->enabled_tc & (1 << i)) {
5403                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5404                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5405                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5406                         qp_idx += qpnum_per_tc;
5407                 } else
5408                         info->tc_mapping[i] = 0;
5409         }
5410
5411         /* Associate queue number with VSI */
5412         if (vsi->type == I40E_VSI_SRIOV) {
5413                 info->mapping_flags |=
5414                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5415                 for (i = 0; i < vsi->nb_qps; i++)
5416                         info->queue_mapping[i] =
5417                                 rte_cpu_to_le_16(vsi->base_queue + i);
5418         } else {
5419                 info->mapping_flags |=
5420                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5421                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5422         }
5423         info->valid_sections |=
5424                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5425
5426         return I40E_SUCCESS;
5427 }
5428
5429 static int
5430 i40e_veb_release(struct i40e_veb *veb)
5431 {
5432         struct i40e_vsi *vsi;
5433         struct i40e_hw *hw;
5434
5435         if (veb == NULL)
5436                 return -EINVAL;
5437
5438         if (!TAILQ_EMPTY(&veb->head)) {
5439                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5440                 return -EACCES;
5441         }
5442         /* associate_vsi field is NULL for floating VEB */
5443         if (veb->associate_vsi != NULL) {
5444                 vsi = veb->associate_vsi;
5445                 hw = I40E_VSI_TO_HW(vsi);
5446
5447                 vsi->uplink_seid = veb->uplink_seid;
5448                 vsi->veb = NULL;
5449         } else {
5450                 veb->associate_pf->main_vsi->floating_veb = NULL;
5451                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5452         }
5453
5454         i40e_aq_delete_element(hw, veb->seid, NULL);
5455         rte_free(veb);
5456         return I40E_SUCCESS;
5457 }
5458
5459 /* Setup a veb */
5460 static struct i40e_veb *
5461 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5462 {
5463         struct i40e_veb *veb;
5464         int ret;
5465         struct i40e_hw *hw;
5466
5467         if (pf == NULL) {
5468                 PMD_DRV_LOG(ERR,
5469                             "veb setup failed, associated PF shouldn't null");
5470                 return NULL;
5471         }
5472         hw = I40E_PF_TO_HW(pf);
5473
5474         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5475         if (!veb) {
5476                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5477                 goto fail;
5478         }
5479
5480         veb->associate_vsi = vsi;
5481         veb->associate_pf = pf;
5482         TAILQ_INIT(&veb->head);
5483         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5484
5485         /* create floating veb if vsi is NULL */
5486         if (vsi != NULL) {
5487                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5488                                       I40E_DEFAULT_TCMAP, false,
5489                                       &veb->seid, false, NULL);
5490         } else {
5491                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5492                                       true, &veb->seid, false, NULL);
5493         }
5494
5495         if (ret != I40E_SUCCESS) {
5496                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5497                             hw->aq.asq_last_status);
5498                 goto fail;
5499         }
5500         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5501
5502         /* get statistics index */
5503         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5504                                 &veb->stats_idx, NULL, NULL, NULL);
5505         if (ret != I40E_SUCCESS) {
5506                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5507                             hw->aq.asq_last_status);
5508                 goto fail;
5509         }
5510         /* Get VEB bandwidth, to be implemented */
5511         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5512         if (vsi)
5513                 vsi->uplink_seid = veb->seid;
5514
5515         return veb;
5516 fail:
5517         rte_free(veb);
5518         return NULL;
5519 }
5520
5521 int
5522 i40e_vsi_release(struct i40e_vsi *vsi)
5523 {
5524         struct i40e_pf *pf;
5525         struct i40e_hw *hw;
5526         struct i40e_vsi_list *vsi_list;
5527         void *temp;
5528         int ret;
5529         struct i40e_mac_filter *f;
5530         uint16_t user_param;
5531
5532         if (!vsi)
5533                 return I40E_SUCCESS;
5534
5535         if (!vsi->adapter)
5536                 return -EFAULT;
5537
5538         user_param = vsi->user_param;
5539
5540         pf = I40E_VSI_TO_PF(vsi);
5541         hw = I40E_VSI_TO_HW(vsi);
5542
5543         /* VSI has child to attach, release child first */
5544         if (vsi->veb) {
5545                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5546                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5547                                 return -1;
5548                 }
5549                 i40e_veb_release(vsi->veb);
5550         }
5551
5552         if (vsi->floating_veb) {
5553                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5554                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5555                                 return -1;
5556                 }
5557         }
5558
5559         /* Remove all macvlan filters of the VSI */
5560         i40e_vsi_remove_all_macvlan_filter(vsi);
5561         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5562                 rte_free(f);
5563
5564         if (vsi->type != I40E_VSI_MAIN &&
5565             ((vsi->type != I40E_VSI_SRIOV) ||
5566             !pf->floating_veb_list[user_param])) {
5567                 /* Remove vsi from parent's sibling list */
5568                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5569                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5570                         return I40E_ERR_PARAM;
5571                 }
5572                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5573                                 &vsi->sib_vsi_list, list);
5574
5575                 /* Remove all switch element of the VSI */
5576                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5577                 if (ret != I40E_SUCCESS)
5578                         PMD_DRV_LOG(ERR, "Failed to delete element");
5579         }
5580
5581         if ((vsi->type == I40E_VSI_SRIOV) &&
5582             pf->floating_veb_list[user_param]) {
5583                 /* Remove vsi from parent's sibling list */
5584                 if (vsi->parent_vsi == NULL ||
5585                     vsi->parent_vsi->floating_veb == NULL) {
5586                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5587                         return I40E_ERR_PARAM;
5588                 }
5589                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5590                              &vsi->sib_vsi_list, list);
5591
5592                 /* Remove all switch element of the VSI */
5593                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5594                 if (ret != I40E_SUCCESS)
5595                         PMD_DRV_LOG(ERR, "Failed to delete element");
5596         }
5597
5598         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5599
5600         if (vsi->type != I40E_VSI_SRIOV)
5601                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5602         rte_free(vsi);
5603
5604         return I40E_SUCCESS;
5605 }
5606
5607 static int
5608 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5609 {
5610         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5611         struct i40e_aqc_remove_macvlan_element_data def_filter;
5612         struct i40e_mac_filter_info filter;
5613         int ret;
5614
5615         if (vsi->type != I40E_VSI_MAIN)
5616                 return I40E_ERR_CONFIG;
5617         memset(&def_filter, 0, sizeof(def_filter));
5618         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5619                                         ETH_ADDR_LEN);
5620         def_filter.vlan_tag = 0;
5621         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5622                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5623         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5624         if (ret != I40E_SUCCESS) {
5625                 struct i40e_mac_filter *f;
5626                 struct rte_ether_addr *mac;
5627
5628                 PMD_DRV_LOG(DEBUG,
5629                             "Cannot remove the default macvlan filter");
5630                 /* It needs to add the permanent mac into mac list */
5631                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5632                 if (f == NULL) {
5633                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5634                         return I40E_ERR_NO_MEMORY;
5635                 }
5636                 mac = &f->mac_info.mac_addr;
5637                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5638                                 ETH_ADDR_LEN);
5639                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5640                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5641                 vsi->mac_num++;
5642
5643                 return ret;
5644         }
5645         rte_memcpy(&filter.mac_addr,
5646                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5647         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5648         return i40e_vsi_add_mac(vsi, &filter);
5649 }
5650
5651 /*
5652  * i40e_vsi_get_bw_config - Query VSI BW Information
5653  * @vsi: the VSI to be queried
5654  *
5655  * Returns 0 on success, negative value on failure
5656  */
5657 static enum i40e_status_code
5658 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5659 {
5660         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5661         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5662         struct i40e_hw *hw = &vsi->adapter->hw;
5663         i40e_status ret;
5664         int i;
5665         uint32_t bw_max;
5666
5667         memset(&bw_config, 0, sizeof(bw_config));
5668         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5669         if (ret != I40E_SUCCESS) {
5670                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5671                             hw->aq.asq_last_status);
5672                 return ret;
5673         }
5674
5675         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5676         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5677                                         &ets_sla_config, NULL);
5678         if (ret != I40E_SUCCESS) {
5679                 PMD_DRV_LOG(ERR,
5680                         "VSI failed to get TC bandwdith configuration %u",
5681                         hw->aq.asq_last_status);
5682                 return ret;
5683         }
5684
5685         /* store and print out BW info */
5686         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5687         vsi->bw_info.bw_max = bw_config.max_bw;
5688         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5689         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5690         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5691                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5692                      I40E_16_BIT_WIDTH);
5693         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5694                 vsi->bw_info.bw_ets_share_credits[i] =
5695                                 ets_sla_config.share_credits[i];
5696                 vsi->bw_info.bw_ets_credits[i] =
5697                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5698                 /* 4 bits per TC, 4th bit is reserved */
5699                 vsi->bw_info.bw_ets_max[i] =
5700                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5701                                   RTE_LEN2MASK(3, uint8_t));
5702                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5703                             vsi->bw_info.bw_ets_share_credits[i]);
5704                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5705                             vsi->bw_info.bw_ets_credits[i]);
5706                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5707                             vsi->bw_info.bw_ets_max[i]);
5708         }
5709
5710         return I40E_SUCCESS;
5711 }
5712
5713 /* i40e_enable_pf_lb
5714  * @pf: pointer to the pf structure
5715  *
5716  * allow loopback on pf
5717  */
5718 static inline void
5719 i40e_enable_pf_lb(struct i40e_pf *pf)
5720 {
5721         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5722         struct i40e_vsi_context ctxt;
5723         int ret;
5724
5725         /* Use the FW API if FW >= v5.0 */
5726         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5727                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5728                 return;
5729         }
5730
5731         memset(&ctxt, 0, sizeof(ctxt));
5732         ctxt.seid = pf->main_vsi_seid;
5733         ctxt.pf_num = hw->pf_id;
5734         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5735         if (ret) {
5736                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5737                             ret, hw->aq.asq_last_status);
5738                 return;
5739         }
5740         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5741         ctxt.info.valid_sections =
5742                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5743         ctxt.info.switch_id |=
5744                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5745
5746         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5747         if (ret)
5748                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5749                             hw->aq.asq_last_status);
5750 }
5751
5752 /* Setup a VSI */
5753 struct i40e_vsi *
5754 i40e_vsi_setup(struct i40e_pf *pf,
5755                enum i40e_vsi_type type,
5756                struct i40e_vsi *uplink_vsi,
5757                uint16_t user_param)
5758 {
5759         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5760         struct i40e_vsi *vsi;
5761         struct i40e_mac_filter_info filter;
5762         int ret;
5763         struct i40e_vsi_context ctxt;
5764         struct rte_ether_addr broadcast =
5765                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5766
5767         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5768             uplink_vsi == NULL) {
5769                 PMD_DRV_LOG(ERR,
5770                         "VSI setup failed, VSI link shouldn't be NULL");
5771                 return NULL;
5772         }
5773
5774         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5775                 PMD_DRV_LOG(ERR,
5776                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5777                 return NULL;
5778         }
5779
5780         /* two situations
5781          * 1.type is not MAIN and uplink vsi is not NULL
5782          * If uplink vsi didn't setup VEB, create one first under veb field
5783          * 2.type is SRIOV and the uplink is NULL
5784          * If floating VEB is NULL, create one veb under floating veb field
5785          */
5786
5787         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5788             uplink_vsi->veb == NULL) {
5789                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5790
5791                 if (uplink_vsi->veb == NULL) {
5792                         PMD_DRV_LOG(ERR, "VEB setup failed");
5793                         return NULL;
5794                 }
5795                 /* set ALLOWLOOPBACk on pf, when veb is created */
5796                 i40e_enable_pf_lb(pf);
5797         }
5798
5799         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5800             pf->main_vsi->floating_veb == NULL) {
5801                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5802
5803                 if (pf->main_vsi->floating_veb == NULL) {
5804                         PMD_DRV_LOG(ERR, "VEB setup failed");
5805                         return NULL;
5806                 }
5807         }
5808
5809         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5810         if (!vsi) {
5811                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5812                 return NULL;
5813         }
5814         TAILQ_INIT(&vsi->mac_list);
5815         vsi->type = type;
5816         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5817         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5818         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5819         vsi->user_param = user_param;
5820         vsi->vlan_anti_spoof_on = 0;
5821         vsi->vlan_filter_on = 0;
5822         /* Allocate queues */
5823         switch (vsi->type) {
5824         case I40E_VSI_MAIN  :
5825                 vsi->nb_qps = pf->lan_nb_qps;
5826                 break;
5827         case I40E_VSI_SRIOV :
5828                 vsi->nb_qps = pf->vf_nb_qps;
5829                 break;
5830         case I40E_VSI_VMDQ2:
5831                 vsi->nb_qps = pf->vmdq_nb_qps;
5832                 break;
5833         case I40E_VSI_FDIR:
5834                 vsi->nb_qps = pf->fdir_nb_qps;
5835                 break;
5836         default:
5837                 goto fail_mem;
5838         }
5839         /*
5840          * The filter status descriptor is reported in rx queue 0,
5841          * while the tx queue for fdir filter programming has no
5842          * such constraints, can be non-zero queues.
5843          * To simplify it, choose FDIR vsi use queue 0 pair.
5844          * To make sure it will use queue 0 pair, queue allocation
5845          * need be done before this function is called
5846          */
5847         if (type != I40E_VSI_FDIR) {
5848                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5849                         if (ret < 0) {
5850                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5851                                                 vsi->seid, ret);
5852                                 goto fail_mem;
5853                         }
5854                         vsi->base_queue = ret;
5855         } else
5856                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5857
5858         /* VF has MSIX interrupt in VF range, don't allocate here */
5859         if (type == I40E_VSI_MAIN) {
5860                 if (pf->support_multi_driver) {
5861                         /* If support multi-driver, need to use INT0 instead of
5862                          * allocating from msix pool. The Msix pool is init from
5863                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5864                          * to 1 without calling i40e_res_pool_alloc.
5865                          */
5866                         vsi->msix_intr = 0;
5867                         vsi->nb_msix = 1;
5868                 } else {
5869                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5870                                                   RTE_MIN(vsi->nb_qps,
5871                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5872                         if (ret < 0) {
5873                                 PMD_DRV_LOG(ERR,
5874                                             "VSI MAIN %d get heap failed %d",
5875                                             vsi->seid, ret);
5876                                 goto fail_queue_alloc;
5877                         }
5878                         vsi->msix_intr = ret;
5879                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5880                                                RTE_MAX_RXTX_INTR_VEC_ID);
5881                 }
5882         } else if (type != I40E_VSI_SRIOV) {
5883                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5884                 if (ret < 0) {
5885                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5886                         if (type != I40E_VSI_FDIR)
5887                                 goto fail_queue_alloc;
5888                         vsi->msix_intr = 0;
5889                         vsi->nb_msix = 0;
5890                 } else {
5891                         vsi->msix_intr = ret;
5892                         vsi->nb_msix = 1;
5893                 }
5894         } else {
5895                 vsi->msix_intr = 0;
5896                 vsi->nb_msix = 0;
5897         }
5898
5899         /* Add VSI */
5900         if (type == I40E_VSI_MAIN) {
5901                 /* For main VSI, no need to add since it's default one */
5902                 vsi->uplink_seid = pf->mac_seid;
5903                 vsi->seid = pf->main_vsi_seid;
5904                 /* Bind queues with specific MSIX interrupt */
5905                 /**
5906                  * Needs 2 interrupt at least, one for misc cause which will
5907                  * enabled from OS side, Another for queues binding the
5908                  * interrupt from device side only.
5909                  */
5910
5911                 /* Get default VSI parameters from hardware */
5912                 memset(&ctxt, 0, sizeof(ctxt));
5913                 ctxt.seid = vsi->seid;
5914                 ctxt.pf_num = hw->pf_id;
5915                 ctxt.uplink_seid = vsi->uplink_seid;
5916                 ctxt.vf_num = 0;
5917                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5918                 if (ret != I40E_SUCCESS) {
5919                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5920                         goto fail_msix_alloc;
5921                 }
5922                 rte_memcpy(&vsi->info, &ctxt.info,
5923                         sizeof(struct i40e_aqc_vsi_properties_data));
5924                 vsi->vsi_id = ctxt.vsi_number;
5925                 vsi->info.valid_sections = 0;
5926
5927                 /* Configure tc, enabled TC0 only */
5928                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5929                         I40E_SUCCESS) {
5930                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5931                         goto fail_msix_alloc;
5932                 }
5933
5934                 /* TC, queue mapping */
5935                 memset(&ctxt, 0, sizeof(ctxt));
5936                 vsi->info.valid_sections |=
5937                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5938                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5939                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5940                 rte_memcpy(&ctxt.info, &vsi->info,
5941                         sizeof(struct i40e_aqc_vsi_properties_data));
5942                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5943                                                 I40E_DEFAULT_TCMAP);
5944                 if (ret != I40E_SUCCESS) {
5945                         PMD_DRV_LOG(ERR,
5946                                 "Failed to configure TC queue mapping");
5947                         goto fail_msix_alloc;
5948                 }
5949                 ctxt.seid = vsi->seid;
5950                 ctxt.pf_num = hw->pf_id;
5951                 ctxt.uplink_seid = vsi->uplink_seid;
5952                 ctxt.vf_num = 0;
5953
5954                 /* Update VSI parameters */
5955                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5956                 if (ret != I40E_SUCCESS) {
5957                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5958                         goto fail_msix_alloc;
5959                 }
5960
5961                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5962                                                 sizeof(vsi->info.tc_mapping));
5963                 rte_memcpy(&vsi->info.queue_mapping,
5964                                 &ctxt.info.queue_mapping,
5965                         sizeof(vsi->info.queue_mapping));
5966                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5967                 vsi->info.valid_sections = 0;
5968
5969                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5970                                 ETH_ADDR_LEN);
5971
5972                 /**
5973                  * Updating default filter settings are necessary to prevent
5974                  * reception of tagged packets.
5975                  * Some old firmware configurations load a default macvlan
5976                  * filter which accepts both tagged and untagged packets.
5977                  * The updating is to use a normal filter instead if needed.
5978                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5979                  * The firmware with correct configurations load the default
5980                  * macvlan filter which is expected and cannot be removed.
5981                  */
5982                 i40e_update_default_filter_setting(vsi);
5983                 i40e_config_qinq(hw, vsi);
5984         } else if (type == I40E_VSI_SRIOV) {
5985                 memset(&ctxt, 0, sizeof(ctxt));
5986                 /**
5987                  * For other VSI, the uplink_seid equals to uplink VSI's
5988                  * uplink_seid since they share same VEB
5989                  */
5990                 if (uplink_vsi == NULL)
5991                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5992                 else
5993                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5994                 ctxt.pf_num = hw->pf_id;
5995                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5996                 ctxt.uplink_seid = vsi->uplink_seid;
5997                 ctxt.connection_type = 0x1;
5998                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5999
6000                 /* Use the VEB configuration if FW >= v5.0 */
6001                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
6002                         /* Configure switch ID */
6003                         ctxt.info.valid_sections |=
6004                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6005                         ctxt.info.switch_id =
6006                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6007                 }
6008
6009                 /* Configure port/vlan */
6010                 ctxt.info.valid_sections |=
6011                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6012                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6013                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6014                                                 hw->func_caps.enabled_tcmap);
6015                 if (ret != I40E_SUCCESS) {
6016                         PMD_DRV_LOG(ERR,
6017                                 "Failed to configure TC queue mapping");
6018                         goto fail_msix_alloc;
6019                 }
6020
6021                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
6022                 ctxt.info.valid_sections |=
6023                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6024                 /**
6025                  * Since VSI is not created yet, only configure parameter,
6026                  * will add vsi below.
6027                  */
6028
6029                 i40e_config_qinq(hw, vsi);
6030         } else if (type == I40E_VSI_VMDQ2) {
6031                 memset(&ctxt, 0, sizeof(ctxt));
6032                 /*
6033                  * For other VSI, the uplink_seid equals to uplink VSI's
6034                  * uplink_seid since they share same VEB
6035                  */
6036                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6037                 ctxt.pf_num = hw->pf_id;
6038                 ctxt.vf_num = 0;
6039                 ctxt.uplink_seid = vsi->uplink_seid;
6040                 ctxt.connection_type = 0x1;
6041                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
6042
6043                 ctxt.info.valid_sections |=
6044                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6045                 /* user_param carries flag to enable loop back */
6046                 if (user_param) {
6047                         ctxt.info.switch_id =
6048                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6049                         ctxt.info.switch_id |=
6050                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6051                 }
6052
6053                 /* Configure port/vlan */
6054                 ctxt.info.valid_sections |=
6055                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6056                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6057                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6058                                                 I40E_DEFAULT_TCMAP);
6059                 if (ret != I40E_SUCCESS) {
6060                         PMD_DRV_LOG(ERR,
6061                                 "Failed to configure TC queue mapping");
6062                         goto fail_msix_alloc;
6063                 }
6064                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6065                 ctxt.info.valid_sections |=
6066                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6067         } else if (type == I40E_VSI_FDIR) {
6068                 memset(&ctxt, 0, sizeof(ctxt));
6069                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6070                 ctxt.pf_num = hw->pf_id;
6071                 ctxt.vf_num = 0;
6072                 ctxt.uplink_seid = vsi->uplink_seid;
6073                 ctxt.connection_type = 0x1;     /* regular data port */
6074                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6075                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6076                                                 I40E_DEFAULT_TCMAP);
6077                 if (ret != I40E_SUCCESS) {
6078                         PMD_DRV_LOG(ERR,
6079                                 "Failed to configure TC queue mapping.");
6080                         goto fail_msix_alloc;
6081                 }
6082                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6083                 ctxt.info.valid_sections |=
6084                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6085         } else {
6086                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6087                 goto fail_msix_alloc;
6088         }
6089
6090         if (vsi->type != I40E_VSI_MAIN) {
6091                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6092                 if (ret != I40E_SUCCESS) {
6093                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6094                                     hw->aq.asq_last_status);
6095                         goto fail_msix_alloc;
6096                 }
6097                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6098                 vsi->info.valid_sections = 0;
6099                 vsi->seid = ctxt.seid;
6100                 vsi->vsi_id = ctxt.vsi_number;
6101                 vsi->sib_vsi_list.vsi = vsi;
6102                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6103                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6104                                           &vsi->sib_vsi_list, list);
6105                 } else {
6106                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6107                                           &vsi->sib_vsi_list, list);
6108                 }
6109         }
6110
6111         /* MAC/VLAN configuration */
6112         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6113         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6114
6115         ret = i40e_vsi_add_mac(vsi, &filter);
6116         if (ret != I40E_SUCCESS) {
6117                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6118                 goto fail_msix_alloc;
6119         }
6120
6121         /* Get VSI BW information */
6122         i40e_vsi_get_bw_config(vsi);
6123         return vsi;
6124 fail_msix_alloc:
6125         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6126 fail_queue_alloc:
6127         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6128 fail_mem:
6129         rte_free(vsi);
6130         return NULL;
6131 }
6132
6133 /* Configure vlan filter on or off */
6134 int
6135 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6136 {
6137         int i, num;
6138         struct i40e_mac_filter *f;
6139         void *temp;
6140         struct i40e_mac_filter_info *mac_filter;
6141         enum rte_mac_filter_type desired_filter;
6142         int ret = I40E_SUCCESS;
6143
6144         if (on) {
6145                 /* Filter to match MAC and VLAN */
6146                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6147         } else {
6148                 /* Filter to match only MAC */
6149                 desired_filter = RTE_MAC_PERFECT_MATCH;
6150         }
6151
6152         num = vsi->mac_num;
6153
6154         mac_filter = rte_zmalloc("mac_filter_info_data",
6155                                  num * sizeof(*mac_filter), 0);
6156         if (mac_filter == NULL) {
6157                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6158                 return I40E_ERR_NO_MEMORY;
6159         }
6160
6161         i = 0;
6162
6163         /* Remove all existing mac */
6164         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6165                 mac_filter[i] = f->mac_info;
6166                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6167                 if (ret) {
6168                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6169                                     on ? "enable" : "disable");
6170                         goto DONE;
6171                 }
6172                 i++;
6173         }
6174
6175         /* Override with new filter */
6176         for (i = 0; i < num; i++) {
6177                 mac_filter[i].filter_type = desired_filter;
6178                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6179                 if (ret) {
6180                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6181                                     on ? "enable" : "disable");
6182                         goto DONE;
6183                 }
6184         }
6185
6186 DONE:
6187         rte_free(mac_filter);
6188         return ret;
6189 }
6190
6191 /* Configure vlan stripping on or off */
6192 int
6193 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6194 {
6195         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6196         struct i40e_vsi_context ctxt;
6197         uint8_t vlan_flags;
6198         int ret = I40E_SUCCESS;
6199
6200         /* Check if it has been already on or off */
6201         if (vsi->info.valid_sections &
6202                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6203                 if (on) {
6204                         if ((vsi->info.port_vlan_flags &
6205                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6206                                 return 0; /* already on */
6207                 } else {
6208                         if ((vsi->info.port_vlan_flags &
6209                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6210                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6211                                 return 0; /* already off */
6212                 }
6213         }
6214
6215         if (on)
6216                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6217         else
6218                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6219         vsi->info.valid_sections =
6220                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6221         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6222         vsi->info.port_vlan_flags |= vlan_flags;
6223         ctxt.seid = vsi->seid;
6224         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6225         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6226         if (ret)
6227                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6228                             on ? "enable" : "disable");
6229
6230         return ret;
6231 }
6232
6233 static int
6234 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6235 {
6236         struct rte_eth_dev_data *data = dev->data;
6237         int ret;
6238         int mask = 0;
6239
6240         /* Apply vlan offload setting */
6241         mask = ETH_VLAN_STRIP_MASK |
6242                ETH_QINQ_STRIP_MASK |
6243                ETH_VLAN_FILTER_MASK |
6244                ETH_VLAN_EXTEND_MASK;
6245         ret = i40e_vlan_offload_set(dev, mask);
6246         if (ret) {
6247                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6248                 return ret;
6249         }
6250
6251         /* Apply pvid setting */
6252         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6253                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6254         if (ret)
6255                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6256
6257         return ret;
6258 }
6259
6260 static int
6261 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6262 {
6263         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6264
6265         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6266 }
6267
6268 static int
6269 i40e_update_flow_control(struct i40e_hw *hw)
6270 {
6271 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6272         struct i40e_link_status link_status;
6273         uint32_t rxfc = 0, txfc = 0, reg;
6274         uint8_t an_info;
6275         int ret;
6276
6277         memset(&link_status, 0, sizeof(link_status));
6278         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6279         if (ret != I40E_SUCCESS) {
6280                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6281                 goto write_reg; /* Disable flow control */
6282         }
6283
6284         an_info = hw->phy.link_info.an_info;
6285         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6286                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6287                 ret = I40E_ERR_NOT_READY;
6288                 goto write_reg; /* Disable flow control */
6289         }
6290         /**
6291          * If link auto negotiation is enabled, flow control needs to
6292          * be configured according to it
6293          */
6294         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6295         case I40E_LINK_PAUSE_RXTX:
6296                 rxfc = 1;
6297                 txfc = 1;
6298                 hw->fc.current_mode = I40E_FC_FULL;
6299                 break;
6300         case I40E_AQ_LINK_PAUSE_RX:
6301                 rxfc = 1;
6302                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6303                 break;
6304         case I40E_AQ_LINK_PAUSE_TX:
6305                 txfc = 1;
6306                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6307                 break;
6308         default:
6309                 hw->fc.current_mode = I40E_FC_NONE;
6310                 break;
6311         }
6312
6313 write_reg:
6314         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6315                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6316         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6317         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6318         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6319         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6320
6321         return ret;
6322 }
6323
6324 /* PF setup */
6325 static int
6326 i40e_pf_setup(struct i40e_pf *pf)
6327 {
6328         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6329         struct i40e_filter_control_settings settings;
6330         struct i40e_vsi *vsi;
6331         int ret;
6332
6333         /* Clear all stats counters */
6334         pf->offset_loaded = FALSE;
6335         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6336         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6337         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6338         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6339
6340         ret = i40e_pf_get_switch_config(pf);
6341         if (ret != I40E_SUCCESS) {
6342                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6343                 return ret;
6344         }
6345
6346         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6347         if (ret)
6348                 PMD_INIT_LOG(WARNING,
6349                         "failed to allocate switch domain for device %d", ret);
6350
6351         if (pf->flags & I40E_FLAG_FDIR) {
6352                 /* make queue allocated first, let FDIR use queue pair 0*/
6353                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6354                 if (ret != I40E_FDIR_QUEUE_ID) {
6355                         PMD_DRV_LOG(ERR,
6356                                 "queue allocation fails for FDIR: ret =%d",
6357                                 ret);
6358                         pf->flags &= ~I40E_FLAG_FDIR;
6359                 }
6360         }
6361         /*  main VSI setup */
6362         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6363         if (!vsi) {
6364                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6365                 return I40E_ERR_NOT_READY;
6366         }
6367         pf->main_vsi = vsi;
6368
6369         /* Configure filter control */
6370         memset(&settings, 0, sizeof(settings));
6371         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6372                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6373         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6374                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6375         else {
6376                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6377                         hw->func_caps.rss_table_size);
6378                 return I40E_ERR_PARAM;
6379         }
6380         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6381                 hw->func_caps.rss_table_size);
6382         pf->hash_lut_size = hw->func_caps.rss_table_size;
6383
6384         /* Enable ethtype and macvlan filters */
6385         settings.enable_ethtype = TRUE;
6386         settings.enable_macvlan = TRUE;
6387         ret = i40e_set_filter_control(hw, &settings);
6388         if (ret)
6389                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6390                                                                 ret);
6391
6392         /* Update flow control according to the auto negotiation */
6393         i40e_update_flow_control(hw);
6394
6395         return I40E_SUCCESS;
6396 }
6397
6398 int
6399 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6400 {
6401         uint32_t reg;
6402         uint16_t j;
6403
6404         /**
6405          * Set or clear TX Queue Disable flags,
6406          * which is required by hardware.
6407          */
6408         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6409         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6410
6411         /* Wait until the request is finished */
6412         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6413                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6414                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6415                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6416                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6417                                                         & 0x1))) {
6418                         break;
6419                 }
6420         }
6421         if (on) {
6422                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6423                         return I40E_SUCCESS; /* already on, skip next steps */
6424
6425                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6426                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6427         } else {
6428                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6429                         return I40E_SUCCESS; /* already off, skip next steps */
6430                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6431         }
6432         /* Write the register */
6433         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6434         /* Check the result */
6435         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6436                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6437                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6438                 if (on) {
6439                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6440                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6441                                 break;
6442                 } else {
6443                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6444                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6445                                 break;
6446                 }
6447         }
6448         /* Check if it is timeout */
6449         if (j >= I40E_CHK_Q_ENA_COUNT) {
6450                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6451                             (on ? "enable" : "disable"), q_idx);
6452                 return I40E_ERR_TIMEOUT;
6453         }
6454
6455         return I40E_SUCCESS;
6456 }
6457
6458 int
6459 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6460 {
6461         uint32_t reg;
6462         uint16_t j;
6463
6464         /* Wait until the request is finished */
6465         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6466                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6467                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6468                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6469                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6470                         break;
6471         }
6472
6473         if (on) {
6474                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6475                         return I40E_SUCCESS; /* Already on, skip next steps */
6476                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6477         } else {
6478                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6479                         return I40E_SUCCESS; /* Already off, skip next steps */
6480                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6481         }
6482
6483         /* Write the register */
6484         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6485         /* Check the result */
6486         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6487                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6488                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6489                 if (on) {
6490                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6491                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6492                                 break;
6493                 } else {
6494                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6495                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6496                                 break;
6497                 }
6498         }
6499
6500         /* Check if it is timeout */
6501         if (j >= I40E_CHK_Q_ENA_COUNT) {
6502                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6503                             (on ? "enable" : "disable"), q_idx);
6504                 return I40E_ERR_TIMEOUT;
6505         }
6506
6507         return I40E_SUCCESS;
6508 }
6509
6510 /* Initialize VSI for TX */
6511 static int
6512 i40e_dev_tx_init(struct i40e_pf *pf)
6513 {
6514         struct rte_eth_dev_data *data = pf->dev_data;
6515         uint16_t i;
6516         uint32_t ret = I40E_SUCCESS;
6517         struct i40e_tx_queue *txq;
6518
6519         for (i = 0; i < data->nb_tx_queues; i++) {
6520                 txq = data->tx_queues[i];
6521                 if (!txq || !txq->q_set)
6522                         continue;
6523                 ret = i40e_tx_queue_init(txq);
6524                 if (ret != I40E_SUCCESS)
6525                         break;
6526         }
6527         if (ret == I40E_SUCCESS)
6528                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6529                                      ->eth_dev);
6530
6531         return ret;
6532 }
6533
6534 /* Initialize VSI for RX */
6535 static int
6536 i40e_dev_rx_init(struct i40e_pf *pf)
6537 {
6538         struct rte_eth_dev_data *data = pf->dev_data;
6539         int ret = I40E_SUCCESS;
6540         uint16_t i;
6541         struct i40e_rx_queue *rxq;
6542
6543         i40e_pf_config_rss(pf);
6544         for (i = 0; i < data->nb_rx_queues; i++) {
6545                 rxq = data->rx_queues[i];
6546                 if (!rxq || !rxq->q_set)
6547                         continue;
6548
6549                 ret = i40e_rx_queue_init(rxq);
6550                 if (ret != I40E_SUCCESS) {
6551                         PMD_DRV_LOG(ERR,
6552                                 "Failed to do RX queue initialization");
6553                         break;
6554                 }
6555         }
6556         if (ret == I40E_SUCCESS)
6557                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6558                                      ->eth_dev);
6559
6560         return ret;
6561 }
6562
6563 static int
6564 i40e_dev_rxtx_init(struct i40e_pf *pf)
6565 {
6566         int err;
6567
6568         err = i40e_dev_tx_init(pf);
6569         if (err) {
6570                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6571                 return err;
6572         }
6573         err = i40e_dev_rx_init(pf);
6574         if (err) {
6575                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6576                 return err;
6577         }
6578
6579         return err;
6580 }
6581
6582 static int
6583 i40e_vmdq_setup(struct rte_eth_dev *dev)
6584 {
6585         struct rte_eth_conf *conf = &dev->data->dev_conf;
6586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6587         int i, err, conf_vsis, j, loop;
6588         struct i40e_vsi *vsi;
6589         struct i40e_vmdq_info *vmdq_info;
6590         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6591         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6592
6593         /*
6594          * Disable interrupt to avoid message from VF. Furthermore, it will
6595          * avoid race condition in VSI creation/destroy.
6596          */
6597         i40e_pf_disable_irq0(hw);
6598
6599         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6600                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6601                 return -ENOTSUP;
6602         }
6603
6604         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6605         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6606                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6607                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6608                         pf->max_nb_vmdq_vsi);
6609                 return -ENOTSUP;
6610         }
6611
6612         if (pf->vmdq != NULL) {
6613                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6614                 return 0;
6615         }
6616
6617         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6618                                 sizeof(*vmdq_info) * conf_vsis, 0);
6619
6620         if (pf->vmdq == NULL) {
6621                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6622                 return -ENOMEM;
6623         }
6624
6625         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6626
6627         /* Create VMDQ VSI */
6628         for (i = 0; i < conf_vsis; i++) {
6629                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6630                                 vmdq_conf->enable_loop_back);
6631                 if (vsi == NULL) {
6632                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6633                         err = -1;
6634                         goto err_vsi_setup;
6635                 }
6636                 vmdq_info = &pf->vmdq[i];
6637                 vmdq_info->pf = pf;
6638                 vmdq_info->vsi = vsi;
6639         }
6640         pf->nb_cfg_vmdq_vsi = conf_vsis;
6641
6642         /* Configure Vlan */
6643         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6644         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6645                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6646                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6647                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6648                                         vmdq_conf->pool_map[i].vlan_id, j);
6649
6650                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6651                                                 vmdq_conf->pool_map[i].vlan_id);
6652                                 if (err) {
6653                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6654                                         err = -1;
6655                                         goto err_vsi_setup;
6656                                 }
6657                         }
6658                 }
6659         }
6660
6661         i40e_pf_enable_irq0(hw);
6662
6663         return 0;
6664
6665 err_vsi_setup:
6666         for (i = 0; i < conf_vsis; i++)
6667                 if (pf->vmdq[i].vsi == NULL)
6668                         break;
6669                 else
6670                         i40e_vsi_release(pf->vmdq[i].vsi);
6671
6672         rte_free(pf->vmdq);
6673         pf->vmdq = NULL;
6674         i40e_pf_enable_irq0(hw);
6675         return err;
6676 }
6677
6678 static void
6679 i40e_stat_update_32(struct i40e_hw *hw,
6680                    uint32_t reg,
6681                    bool offset_loaded,
6682                    uint64_t *offset,
6683                    uint64_t *stat)
6684 {
6685         uint64_t new_data;
6686
6687         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6688         if (!offset_loaded)
6689                 *offset = new_data;
6690
6691         if (new_data >= *offset)
6692                 *stat = (uint64_t)(new_data - *offset);
6693         else
6694                 *stat = (uint64_t)((new_data +
6695                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6696 }
6697
6698 static void
6699 i40e_stat_update_48(struct i40e_hw *hw,
6700                    uint32_t hireg,
6701                    uint32_t loreg,
6702                    bool offset_loaded,
6703                    uint64_t *offset,
6704                    uint64_t *stat)
6705 {
6706         uint64_t new_data;
6707
6708         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6709         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6710                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6711
6712         if (!offset_loaded)
6713                 *offset = new_data;
6714
6715         if (new_data >= *offset)
6716                 *stat = new_data - *offset;
6717         else
6718                 *stat = (uint64_t)((new_data +
6719                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6720
6721         *stat &= I40E_48_BIT_MASK;
6722 }
6723
6724 /* Disable IRQ0 */
6725 void
6726 i40e_pf_disable_irq0(struct i40e_hw *hw)
6727 {
6728         /* Disable all interrupt types */
6729         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6730                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6731         I40E_WRITE_FLUSH(hw);
6732 }
6733
6734 /* Enable IRQ0 */
6735 void
6736 i40e_pf_enable_irq0(struct i40e_hw *hw)
6737 {
6738         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6739                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6740                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6741                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6742         I40E_WRITE_FLUSH(hw);
6743 }
6744
6745 static void
6746 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6747 {
6748         /* read pending request and disable first */
6749         i40e_pf_disable_irq0(hw);
6750         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6751         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6752                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6753
6754         if (no_queue)
6755                 /* Link no queues with irq0 */
6756                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6757                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6758 }
6759
6760 static void
6761 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6762 {
6763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6765         int i;
6766         uint16_t abs_vf_id;
6767         uint32_t index, offset, val;
6768
6769         if (!pf->vfs)
6770                 return;
6771         /**
6772          * Try to find which VF trigger a reset, use absolute VF id to access
6773          * since the reg is global register.
6774          */
6775         for (i = 0; i < pf->vf_num; i++) {
6776                 abs_vf_id = hw->func_caps.vf_base_id + i;
6777                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6778                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6779                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6780                 /* VFR event occurred */
6781                 if (val & (0x1 << offset)) {
6782                         int ret;
6783
6784                         /* Clear the event first */
6785                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6786                                                         (0x1 << offset));
6787                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6788                         /**
6789                          * Only notify a VF reset event occurred,
6790                          * don't trigger another SW reset
6791                          */
6792                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6793                         if (ret != I40E_SUCCESS)
6794                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6795                 }
6796         }
6797 }
6798
6799 static void
6800 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6801 {
6802         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6803         int i;
6804
6805         for (i = 0; i < pf->vf_num; i++)
6806                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6807 }
6808
6809 static void
6810 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6811 {
6812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6813         struct i40e_arq_event_info info;
6814         uint16_t pending, opcode;
6815         int ret;
6816
6817         info.buf_len = I40E_AQ_BUF_SZ;
6818         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6819         if (!info.msg_buf) {
6820                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6821                 return;
6822         }
6823
6824         pending = 1;
6825         while (pending) {
6826                 ret = i40e_clean_arq_element(hw, &info, &pending);
6827
6828                 if (ret != I40E_SUCCESS) {
6829                         PMD_DRV_LOG(INFO,
6830                                 "Failed to read msg from AdminQ, aq_err: %u",
6831                                 hw->aq.asq_last_status);
6832                         break;
6833                 }
6834                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6835
6836                 switch (opcode) {
6837                 case i40e_aqc_opc_send_msg_to_pf:
6838                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6839                         i40e_pf_host_handle_vf_msg(dev,
6840                                         rte_le_to_cpu_16(info.desc.retval),
6841                                         rte_le_to_cpu_32(info.desc.cookie_high),
6842                                         rte_le_to_cpu_32(info.desc.cookie_low),
6843                                         info.msg_buf,
6844                                         info.msg_len);
6845                         break;
6846                 case i40e_aqc_opc_get_link_status:
6847                         ret = i40e_dev_link_update(dev, 0);
6848                         if (!ret)
6849                                 rte_eth_dev_callback_process(dev,
6850                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6851                         break;
6852                 default:
6853                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6854                                     opcode);
6855                         break;
6856                 }
6857         }
6858         rte_free(info.msg_buf);
6859 }
6860
6861 static void
6862 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6863 {
6864 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6865 #define I40E_MDD_CLEAR16 0xFFFF
6866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6867         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6868         bool mdd_detected = false;
6869         struct i40e_pf_vf *vf;
6870         uint32_t reg;
6871         int i;
6872
6873         /* find what triggered the MDD event */
6874         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6875         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6876                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6877                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6878                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6879                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6880                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6881                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6882                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6883                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6884                                         hw->func_caps.base_queue;
6885                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6886                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6887                                 event, queue, pf_num, vf_num, dev->data->name);
6888                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6889                 mdd_detected = true;
6890         }
6891         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6892         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6893                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6894                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6895                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6896                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6897                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6898                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6899                                         hw->func_caps.base_queue;
6900
6901                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6902                                 "queue %d of function 0x%02x device %s\n",
6903                                         event, queue, func, dev->data->name);
6904                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6905                 mdd_detected = true;
6906         }
6907
6908         if (mdd_detected) {
6909                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6910                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6911                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6912                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6913                 }
6914                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6915                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6916                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6917                                         I40E_MDD_CLEAR16);
6918                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6919                 }
6920         }
6921
6922         /* see if one of the VFs needs its hand slapped */
6923         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6924                 vf = &pf->vfs[i];
6925                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6926                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6927                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6928                                         I40E_MDD_CLEAR16);
6929                         vf->num_mdd_events++;
6930                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6931                                         PRIu64 "times\n",
6932                                         i, vf->num_mdd_events);
6933                 }
6934
6935                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6936                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6937                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6938                                         I40E_MDD_CLEAR16);
6939                         vf->num_mdd_events++;
6940                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6941                                         PRIu64 "times\n",
6942                                         i, vf->num_mdd_events);
6943                 }
6944         }
6945 }
6946
6947 /**
6948  * Interrupt handler triggered by NIC  for handling
6949  * specific interrupt.
6950  *
6951  * @param handle
6952  *  Pointer to interrupt handle.
6953  * @param param
6954  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6955  *
6956  * @return
6957  *  void
6958  */
6959 static void
6960 i40e_dev_interrupt_handler(void *param)
6961 {
6962         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964         uint32_t icr0;
6965
6966         /* Disable interrupt */
6967         i40e_pf_disable_irq0(hw);
6968
6969         /* read out interrupt causes */
6970         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6971
6972         /* No interrupt event indicated */
6973         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6974                 PMD_DRV_LOG(INFO, "No interrupt event");
6975                 goto done;
6976         }
6977         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6978                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6979         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6980                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6981                 i40e_handle_mdd_event(dev);
6982         }
6983         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6984                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6985         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6986                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6987         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6988                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6989         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6990                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6991         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6992                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6993
6994         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6995                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6996                 i40e_dev_handle_vfr_event(dev);
6997         }
6998         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6999                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7000                 i40e_dev_handle_aq_msg(dev);
7001         }
7002
7003 done:
7004         /* Enable interrupt */
7005         i40e_pf_enable_irq0(hw);
7006 }
7007
7008 static void
7009 i40e_dev_alarm_handler(void *param)
7010 {
7011         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7012         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7013         uint32_t icr0;
7014
7015         /* Disable interrupt */
7016         i40e_pf_disable_irq0(hw);
7017
7018         /* read out interrupt causes */
7019         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
7020
7021         /* No interrupt event indicated */
7022         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
7023                 goto done;
7024         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
7025                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
7026         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
7027                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
7028                 i40e_handle_mdd_event(dev);
7029         }
7030         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
7031                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
7032         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
7033                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
7034         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
7035                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
7036         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
7037                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
7038         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
7039                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
7040
7041         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
7042                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
7043                 i40e_dev_handle_vfr_event(dev);
7044         }
7045         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
7046                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7047                 i40e_dev_handle_aq_msg(dev);
7048         }
7049
7050 done:
7051         /* Enable interrupt */
7052         i40e_pf_enable_irq0(hw);
7053         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7054                           i40e_dev_alarm_handler, dev);
7055 }
7056
7057 int
7058 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7059                          struct i40e_macvlan_filter *filter,
7060                          int total)
7061 {
7062         int ele_num, ele_buff_size;
7063         int num, actual_num, i;
7064         uint16_t flags;
7065         int ret = I40E_SUCCESS;
7066         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7067         struct i40e_aqc_add_macvlan_element_data *req_list;
7068
7069         if (filter == NULL  || total == 0)
7070                 return I40E_ERR_PARAM;
7071         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7072         ele_buff_size = hw->aq.asq_buf_size;
7073
7074         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7075         if (req_list == NULL) {
7076                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7077                 return I40E_ERR_NO_MEMORY;
7078         }
7079
7080         num = 0;
7081         do {
7082                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7083                 memset(req_list, 0, ele_buff_size);
7084
7085                 for (i = 0; i < actual_num; i++) {
7086                         rte_memcpy(req_list[i].mac_addr,
7087                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7088                         req_list[i].vlan_tag =
7089                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7090
7091                         switch (filter[num + i].filter_type) {
7092                         case RTE_MAC_PERFECT_MATCH:
7093                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7094                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7095                                 break;
7096                         case RTE_MACVLAN_PERFECT_MATCH:
7097                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7098                                 break;
7099                         case RTE_MAC_HASH_MATCH:
7100                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7101                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7102                                 break;
7103                         case RTE_MACVLAN_HASH_MATCH:
7104                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7105                                 break;
7106                         default:
7107                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7108                                 ret = I40E_ERR_PARAM;
7109                                 goto DONE;
7110                         }
7111
7112                         req_list[i].queue_number = 0;
7113
7114                         req_list[i].flags = rte_cpu_to_le_16(flags);
7115                 }
7116
7117                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7118                                                 actual_num, NULL);
7119                 if (ret != I40E_SUCCESS) {
7120                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7121                         goto DONE;
7122                 }
7123                 num += actual_num;
7124         } while (num < total);
7125
7126 DONE:
7127         rte_free(req_list);
7128         return ret;
7129 }
7130
7131 int
7132 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7133                             struct i40e_macvlan_filter *filter,
7134                             int total)
7135 {
7136         int ele_num, ele_buff_size;
7137         int num, actual_num, i;
7138         uint16_t flags;
7139         int ret = I40E_SUCCESS;
7140         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7141         struct i40e_aqc_remove_macvlan_element_data *req_list;
7142
7143         if (filter == NULL  || total == 0)
7144                 return I40E_ERR_PARAM;
7145
7146         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7147         ele_buff_size = hw->aq.asq_buf_size;
7148
7149         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7150         if (req_list == NULL) {
7151                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7152                 return I40E_ERR_NO_MEMORY;
7153         }
7154
7155         num = 0;
7156         do {
7157                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7158                 memset(req_list, 0, ele_buff_size);
7159
7160                 for (i = 0; i < actual_num; i++) {
7161                         rte_memcpy(req_list[i].mac_addr,
7162                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7163                         req_list[i].vlan_tag =
7164                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7165
7166                         switch (filter[num + i].filter_type) {
7167                         case RTE_MAC_PERFECT_MATCH:
7168                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7169                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7170                                 break;
7171                         case RTE_MACVLAN_PERFECT_MATCH:
7172                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7173                                 break;
7174                         case RTE_MAC_HASH_MATCH:
7175                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7176                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7177                                 break;
7178                         case RTE_MACVLAN_HASH_MATCH:
7179                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7180                                 break;
7181                         default:
7182                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7183                                 ret = I40E_ERR_PARAM;
7184                                 goto DONE;
7185                         }
7186                         req_list[i].flags = rte_cpu_to_le_16(flags);
7187                 }
7188
7189                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7190                                                 actual_num, NULL);
7191                 if (ret != I40E_SUCCESS) {
7192                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7193                         goto DONE;
7194                 }
7195                 num += actual_num;
7196         } while (num < total);
7197
7198 DONE:
7199         rte_free(req_list);
7200         return ret;
7201 }
7202
7203 /* Find out specific MAC filter */
7204 static struct i40e_mac_filter *
7205 i40e_find_mac_filter(struct i40e_vsi *vsi,
7206                          struct rte_ether_addr *macaddr)
7207 {
7208         struct i40e_mac_filter *f;
7209
7210         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7211                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7212                         return f;
7213         }
7214
7215         return NULL;
7216 }
7217
7218 static bool
7219 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7220                          uint16_t vlan_id)
7221 {
7222         uint32_t vid_idx, vid_bit;
7223
7224         if (vlan_id > ETH_VLAN_ID_MAX)
7225                 return 0;
7226
7227         vid_idx = I40E_VFTA_IDX(vlan_id);
7228         vid_bit = I40E_VFTA_BIT(vlan_id);
7229
7230         if (vsi->vfta[vid_idx] & vid_bit)
7231                 return 1;
7232         else
7233                 return 0;
7234 }
7235
7236 static void
7237 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7238                        uint16_t vlan_id, bool on)
7239 {
7240         uint32_t vid_idx, vid_bit;
7241
7242         vid_idx = I40E_VFTA_IDX(vlan_id);
7243         vid_bit = I40E_VFTA_BIT(vlan_id);
7244
7245         if (on)
7246                 vsi->vfta[vid_idx] |= vid_bit;
7247         else
7248                 vsi->vfta[vid_idx] &= ~vid_bit;
7249 }
7250
7251 void
7252 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7253                      uint16_t vlan_id, bool on)
7254 {
7255         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7256         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7257         int ret;
7258
7259         if (vlan_id > ETH_VLAN_ID_MAX)
7260                 return;
7261
7262         i40e_store_vlan_filter(vsi, vlan_id, on);
7263
7264         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7265                 return;
7266
7267         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7268
7269         if (on) {
7270                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7271                                        &vlan_data, 1, NULL);
7272                 if (ret != I40E_SUCCESS)
7273                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7274         } else {
7275                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7276                                           &vlan_data, 1, NULL);
7277                 if (ret != I40E_SUCCESS)
7278                         PMD_DRV_LOG(ERR,
7279                                     "Failed to remove vlan filter");
7280         }
7281 }
7282
7283 /**
7284  * Find all vlan options for specific mac addr,
7285  * return with actual vlan found.
7286  */
7287 int
7288 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7289                            struct i40e_macvlan_filter *mv_f,
7290                            int num, struct rte_ether_addr *addr)
7291 {
7292         int i;
7293         uint32_t j, k;
7294
7295         /**
7296          * Not to use i40e_find_vlan_filter to decrease the loop time,
7297          * although the code looks complex.
7298           */
7299         if (num < vsi->vlan_num)
7300                 return I40E_ERR_PARAM;
7301
7302         i = 0;
7303         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7304                 if (vsi->vfta[j]) {
7305                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7306                                 if (vsi->vfta[j] & (1 << k)) {
7307                                         if (i > num - 1) {
7308                                                 PMD_DRV_LOG(ERR,
7309                                                         "vlan number doesn't match");
7310                                                 return I40E_ERR_PARAM;
7311                                         }
7312                                         rte_memcpy(&mv_f[i].macaddr,
7313                                                         addr, ETH_ADDR_LEN);
7314                                         mv_f[i].vlan_id =
7315                                                 j * I40E_UINT32_BIT_SIZE + k;
7316                                         i++;
7317                                 }
7318                         }
7319                 }
7320         }
7321         return I40E_SUCCESS;
7322 }
7323
7324 static inline int
7325 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7326                            struct i40e_macvlan_filter *mv_f,
7327                            int num,
7328                            uint16_t vlan)
7329 {
7330         int i = 0;
7331         struct i40e_mac_filter *f;
7332
7333         if (num < vsi->mac_num)
7334                 return I40E_ERR_PARAM;
7335
7336         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7337                 if (i > num - 1) {
7338                         PMD_DRV_LOG(ERR, "buffer number not match");
7339                         return I40E_ERR_PARAM;
7340                 }
7341                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7342                                 ETH_ADDR_LEN);
7343                 mv_f[i].vlan_id = vlan;
7344                 mv_f[i].filter_type = f->mac_info.filter_type;
7345                 i++;
7346         }
7347
7348         return I40E_SUCCESS;
7349 }
7350
7351 static int
7352 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7353 {
7354         int i, j, num;
7355         struct i40e_mac_filter *f;
7356         struct i40e_macvlan_filter *mv_f;
7357         int ret = I40E_SUCCESS;
7358
7359         if (vsi == NULL || vsi->mac_num == 0)
7360                 return I40E_ERR_PARAM;
7361
7362         /* Case that no vlan is set */
7363         if (vsi->vlan_num == 0)
7364                 num = vsi->mac_num;
7365         else
7366                 num = vsi->mac_num * vsi->vlan_num;
7367
7368         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7369         if (mv_f == NULL) {
7370                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7371                 return I40E_ERR_NO_MEMORY;
7372         }
7373
7374         i = 0;
7375         if (vsi->vlan_num == 0) {
7376                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7377                         rte_memcpy(&mv_f[i].macaddr,
7378                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7379                         mv_f[i].filter_type = f->mac_info.filter_type;
7380                         mv_f[i].vlan_id = 0;
7381                         i++;
7382                 }
7383         } else {
7384                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7385                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7386                                         vsi->vlan_num, &f->mac_info.mac_addr);
7387                         if (ret != I40E_SUCCESS)
7388                                 goto DONE;
7389                         for (j = i; j < i + vsi->vlan_num; j++)
7390                                 mv_f[j].filter_type = f->mac_info.filter_type;
7391                         i += vsi->vlan_num;
7392                 }
7393         }
7394
7395         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7396 DONE:
7397         rte_free(mv_f);
7398
7399         return ret;
7400 }
7401
7402 int
7403 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7404 {
7405         struct i40e_macvlan_filter *mv_f;
7406         int mac_num;
7407         int ret = I40E_SUCCESS;
7408
7409         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7410                 return I40E_ERR_PARAM;
7411
7412         /* If it's already set, just return */
7413         if (i40e_find_vlan_filter(vsi,vlan))
7414                 return I40E_SUCCESS;
7415
7416         mac_num = vsi->mac_num;
7417
7418         if (mac_num == 0) {
7419                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7420                 return I40E_ERR_PARAM;
7421         }
7422
7423         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7424
7425         if (mv_f == NULL) {
7426                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7427                 return I40E_ERR_NO_MEMORY;
7428         }
7429
7430         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7431
7432         if (ret != I40E_SUCCESS)
7433                 goto DONE;
7434
7435         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7436
7437         if (ret != I40E_SUCCESS)
7438                 goto DONE;
7439
7440         i40e_set_vlan_filter(vsi, vlan, 1);
7441
7442         vsi->vlan_num++;
7443         ret = I40E_SUCCESS;
7444 DONE:
7445         rte_free(mv_f);
7446         return ret;
7447 }
7448
7449 int
7450 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7451 {
7452         struct i40e_macvlan_filter *mv_f;
7453         int mac_num;
7454         int ret = I40E_SUCCESS;
7455
7456         /**
7457          * Vlan 0 is the generic filter for untagged packets
7458          * and can't be removed.
7459          */
7460         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7461                 return I40E_ERR_PARAM;
7462
7463         /* If can't find it, just return */
7464         if (!i40e_find_vlan_filter(vsi, vlan))
7465                 return I40E_ERR_PARAM;
7466
7467         mac_num = vsi->mac_num;
7468
7469         if (mac_num == 0) {
7470                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7471                 return I40E_ERR_PARAM;
7472         }
7473
7474         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7475
7476         if (mv_f == NULL) {
7477                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7478                 return I40E_ERR_NO_MEMORY;
7479         }
7480
7481         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7482
7483         if (ret != I40E_SUCCESS)
7484                 goto DONE;
7485
7486         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7487
7488         if (ret != I40E_SUCCESS)
7489                 goto DONE;
7490
7491         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7492         if (vsi->vlan_num == 1) {
7493                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7494                 if (ret != I40E_SUCCESS)
7495                         goto DONE;
7496
7497                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7498                 if (ret != I40E_SUCCESS)
7499                         goto DONE;
7500         }
7501
7502         i40e_set_vlan_filter(vsi, vlan, 0);
7503
7504         vsi->vlan_num--;
7505         ret = I40E_SUCCESS;
7506 DONE:
7507         rte_free(mv_f);
7508         return ret;
7509 }
7510
7511 int
7512 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7513 {
7514         struct i40e_mac_filter *f;
7515         struct i40e_macvlan_filter *mv_f;
7516         int i, vlan_num = 0;
7517         int ret = I40E_SUCCESS;
7518
7519         /* If it's add and we've config it, return */
7520         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7521         if (f != NULL)
7522                 return I40E_SUCCESS;
7523         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7524                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7525
7526                 /**
7527                  * If vlan_num is 0, that's the first time to add mac,
7528                  * set mask for vlan_id 0.
7529                  */
7530                 if (vsi->vlan_num == 0) {
7531                         i40e_set_vlan_filter(vsi, 0, 1);
7532                         vsi->vlan_num = 1;
7533                 }
7534                 vlan_num = vsi->vlan_num;
7535         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7536                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7537                 vlan_num = 1;
7538
7539         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7540         if (mv_f == NULL) {
7541                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7542                 return I40E_ERR_NO_MEMORY;
7543         }
7544
7545         for (i = 0; i < vlan_num; i++) {
7546                 mv_f[i].filter_type = mac_filter->filter_type;
7547                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7548                                 ETH_ADDR_LEN);
7549         }
7550
7551         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7552                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7553                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7554                                         &mac_filter->mac_addr);
7555                 if (ret != I40E_SUCCESS)
7556                         goto DONE;
7557         }
7558
7559         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7560         if (ret != I40E_SUCCESS)
7561                 goto DONE;
7562
7563         /* Add the mac addr into mac list */
7564         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7565         if (f == NULL) {
7566                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7567                 ret = I40E_ERR_NO_MEMORY;
7568                 goto DONE;
7569         }
7570         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7571                         ETH_ADDR_LEN);
7572         f->mac_info.filter_type = mac_filter->filter_type;
7573         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7574         vsi->mac_num++;
7575
7576         ret = I40E_SUCCESS;
7577 DONE:
7578         rte_free(mv_f);
7579
7580         return ret;
7581 }
7582
7583 int
7584 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7585 {
7586         struct i40e_mac_filter *f;
7587         struct i40e_macvlan_filter *mv_f;
7588         int i, vlan_num;
7589         enum rte_mac_filter_type filter_type;
7590         int ret = I40E_SUCCESS;
7591
7592         /* Can't find it, return an error */
7593         f = i40e_find_mac_filter(vsi, addr);
7594         if (f == NULL)
7595                 return I40E_ERR_PARAM;
7596
7597         vlan_num = vsi->vlan_num;
7598         filter_type = f->mac_info.filter_type;
7599         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7600                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7601                 if (vlan_num == 0) {
7602                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7603                         return I40E_ERR_PARAM;
7604                 }
7605         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7606                         filter_type == RTE_MAC_HASH_MATCH)
7607                 vlan_num = 1;
7608
7609         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7610         if (mv_f == NULL) {
7611                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7612                 return I40E_ERR_NO_MEMORY;
7613         }
7614
7615         for (i = 0; i < vlan_num; i++) {
7616                 mv_f[i].filter_type = filter_type;
7617                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7618                                 ETH_ADDR_LEN);
7619         }
7620         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7621                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7622                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7623                 if (ret != I40E_SUCCESS)
7624                         goto DONE;
7625         }
7626
7627         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7628         if (ret != I40E_SUCCESS)
7629                 goto DONE;
7630
7631         /* Remove the mac addr into mac list */
7632         TAILQ_REMOVE(&vsi->mac_list, f, next);
7633         rte_free(f);
7634         vsi->mac_num--;
7635
7636         ret = I40E_SUCCESS;
7637 DONE:
7638         rte_free(mv_f);
7639         return ret;
7640 }
7641
7642 /* Configure hash enable flags for RSS */
7643 uint64_t
7644 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7645 {
7646         uint64_t hena = 0;
7647         int i;
7648
7649         if (!flags)
7650                 return hena;
7651
7652         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7653                 if (flags & (1ULL << i))
7654                         hena |= adapter->pctypes_tbl[i];
7655         }
7656
7657         return hena;
7658 }
7659
7660 /* Parse the hash enable flags */
7661 uint64_t
7662 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7663 {
7664         uint64_t rss_hf = 0;
7665
7666         if (!flags)
7667                 return rss_hf;
7668         int i;
7669
7670         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7671                 if (flags & adapter->pctypes_tbl[i])
7672                         rss_hf |= (1ULL << i);
7673         }
7674         return rss_hf;
7675 }
7676
7677 /* Disable RSS */
7678 static void
7679 i40e_pf_disable_rss(struct i40e_pf *pf)
7680 {
7681         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7682
7683         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7684         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7685         I40E_WRITE_FLUSH(hw);
7686 }
7687
7688 int
7689 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7690 {
7691         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7692         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7693         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7694                            I40E_VFQF_HKEY_MAX_INDEX :
7695                            I40E_PFQF_HKEY_MAX_INDEX;
7696         int ret = 0;
7697
7698         if (!key || key_len == 0) {
7699                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7700                 return 0;
7701         } else if (key_len != (key_idx + 1) *
7702                 sizeof(uint32_t)) {
7703                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7704                 return -EINVAL;
7705         }
7706
7707         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7708                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7709                         (struct i40e_aqc_get_set_rss_key_data *)key;
7710
7711                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7712                 if (ret)
7713                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7714         } else {
7715                 uint32_t *hash_key = (uint32_t *)key;
7716                 uint16_t i;
7717
7718                 if (vsi->type == I40E_VSI_SRIOV) {
7719                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7720                                 I40E_WRITE_REG(
7721                                         hw,
7722                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7723                                         hash_key[i]);
7724
7725                 } else {
7726                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7727                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7728                                                hash_key[i]);
7729                 }
7730                 I40E_WRITE_FLUSH(hw);
7731         }
7732
7733         return ret;
7734 }
7735
7736 static int
7737 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7738 {
7739         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7740         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7741         uint32_t reg;
7742         int ret;
7743
7744         if (!key || !key_len)
7745                 return 0;
7746
7747         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7748                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7749                         (struct i40e_aqc_get_set_rss_key_data *)key);
7750                 if (ret) {
7751                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7752                         return ret;
7753                 }
7754         } else {
7755                 uint32_t *key_dw = (uint32_t *)key;
7756                 uint16_t i;
7757
7758                 if (vsi->type == I40E_VSI_SRIOV) {
7759                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7760                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7761                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7762                         }
7763                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7764                                    sizeof(uint32_t);
7765                 } else {
7766                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7767                                 reg = I40E_PFQF_HKEY(i);
7768                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7769                         }
7770                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7771                                    sizeof(uint32_t);
7772                 }
7773         }
7774         return 0;
7775 }
7776
7777 static int
7778 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7779 {
7780         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7781         uint64_t hena;
7782         int ret;
7783
7784         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7785                                rss_conf->rss_key_len);
7786         if (ret)
7787                 return ret;
7788
7789         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7790         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7791         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7792         I40E_WRITE_FLUSH(hw);
7793
7794         return 0;
7795 }
7796
7797 static int
7798 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7799                          struct rte_eth_rss_conf *rss_conf)
7800 {
7801         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7802         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7803         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7804         uint64_t hena;
7805
7806         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7807         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7808
7809         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7810                 if (rss_hf != 0) /* Enable RSS */
7811                         return -EINVAL;
7812                 return 0; /* Nothing to do */
7813         }
7814         /* RSS enabled */
7815         if (rss_hf == 0) /* Disable RSS */
7816                 return -EINVAL;
7817
7818         return i40e_hw_rss_hash_set(pf, rss_conf);
7819 }
7820
7821 static int
7822 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7823                            struct rte_eth_rss_conf *rss_conf)
7824 {
7825         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7826         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7827         uint64_t hena;
7828         int ret;
7829
7830         if (!rss_conf)
7831                 return -EINVAL;
7832
7833         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7834                          &rss_conf->rss_key_len);
7835         if (ret)
7836                 return ret;
7837
7838         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7839         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7840         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7841
7842         return 0;
7843 }
7844
7845 static int
7846 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7847 {
7848         switch (filter_type) {
7849         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7850                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7851                 break;
7852         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7853                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7854                 break;
7855         case RTE_TUNNEL_FILTER_IMAC_TENID:
7856                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7857                 break;
7858         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7859                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7860                 break;
7861         case ETH_TUNNEL_FILTER_IMAC:
7862                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7863                 break;
7864         case ETH_TUNNEL_FILTER_OIP:
7865                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7866                 break;
7867         case ETH_TUNNEL_FILTER_IIP:
7868                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7869                 break;
7870         default:
7871                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7872                 return -EINVAL;
7873         }
7874
7875         return 0;
7876 }
7877
7878 /* Convert tunnel filter structure */
7879 static int
7880 i40e_tunnel_filter_convert(
7881         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7882         struct i40e_tunnel_filter *tunnel_filter)
7883 {
7884         rte_ether_addr_copy((struct rte_ether_addr *)
7885                         &cld_filter->element.outer_mac,
7886                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7887         rte_ether_addr_copy((struct rte_ether_addr *)
7888                         &cld_filter->element.inner_mac,
7889                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7890         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7891         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7892              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7893             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7894                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7895         else
7896                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7897         tunnel_filter->input.flags = cld_filter->element.flags;
7898         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7899         tunnel_filter->queue = cld_filter->element.queue_number;
7900         rte_memcpy(tunnel_filter->input.general_fields,
7901                    cld_filter->general_fields,
7902                    sizeof(cld_filter->general_fields));
7903
7904         return 0;
7905 }
7906
7907 /* Check if there exists the tunnel filter */
7908 struct i40e_tunnel_filter *
7909 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7910                              const struct i40e_tunnel_filter_input *input)
7911 {
7912         int ret;
7913
7914         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7915         if (ret < 0)
7916                 return NULL;
7917
7918         return tunnel_rule->hash_map[ret];
7919 }
7920
7921 /* Add a tunnel filter into the SW list */
7922 static int
7923 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7924                              struct i40e_tunnel_filter *tunnel_filter)
7925 {
7926         struct i40e_tunnel_rule *rule = &pf->tunnel;
7927         int ret;
7928
7929         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7930         if (ret < 0) {
7931                 PMD_DRV_LOG(ERR,
7932                             "Failed to insert tunnel filter to hash table %d!",
7933                             ret);
7934                 return ret;
7935         }
7936         rule->hash_map[ret] = tunnel_filter;
7937
7938         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7939
7940         return 0;
7941 }
7942
7943 /* Delete a tunnel filter from the SW list */
7944 int
7945 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7946                           struct i40e_tunnel_filter_input *input)
7947 {
7948         struct i40e_tunnel_rule *rule = &pf->tunnel;
7949         struct i40e_tunnel_filter *tunnel_filter;
7950         int ret;
7951
7952         ret = rte_hash_del_key(rule->hash_table, input);
7953         if (ret < 0) {
7954                 PMD_DRV_LOG(ERR,
7955                             "Failed to delete tunnel filter to hash table %d!",
7956                             ret);
7957                 return ret;
7958         }
7959         tunnel_filter = rule->hash_map[ret];
7960         rule->hash_map[ret] = NULL;
7961
7962         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7963         rte_free(tunnel_filter);
7964
7965         return 0;
7966 }
7967
7968 int
7969 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7970                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7971                         uint8_t add)
7972 {
7973         uint16_t ip_type;
7974         uint32_t ipv4_addr, ipv4_addr_le;
7975         uint8_t i, tun_type = 0;
7976         /* internal varialbe to convert ipv6 byte order */
7977         uint32_t convert_ipv6[4];
7978         int val, ret = 0;
7979         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7980         struct i40e_vsi *vsi = pf->main_vsi;
7981         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7982         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7983         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7984         struct i40e_tunnel_filter *tunnel, *node;
7985         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7986
7987         cld_filter = rte_zmalloc("tunnel_filter",
7988                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7989         0);
7990
7991         if (NULL == cld_filter) {
7992                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7993                 return -ENOMEM;
7994         }
7995         pfilter = cld_filter;
7996
7997         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7998                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7999         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8000                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8001
8002         pfilter->element.inner_vlan =
8003                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8004         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
8005                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8006                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8007                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8008                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8009                                 &ipv4_addr_le,
8010                                 sizeof(pfilter->element.ipaddr.v4.data));
8011         } else {
8012                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8013                 for (i = 0; i < 4; i++) {
8014                         convert_ipv6[i] =
8015                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
8016                 }
8017                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8018                            &convert_ipv6,
8019                            sizeof(pfilter->element.ipaddr.v6.data));
8020         }
8021
8022         /* check tunneled type */
8023         switch (tunnel_filter->tunnel_type) {
8024         case RTE_TUNNEL_TYPE_VXLAN:
8025                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8026                 break;
8027         case RTE_TUNNEL_TYPE_NVGRE:
8028                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8029                 break;
8030         case RTE_TUNNEL_TYPE_IP_IN_GRE:
8031                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8032                 break;
8033         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8034                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
8035                 break;
8036         default:
8037                 /* Other tunnel types is not supported. */
8038                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8039                 rte_free(cld_filter);
8040                 return -EINVAL;
8041         }
8042
8043         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8044                                        &pfilter->element.flags);
8045         if (val < 0) {
8046                 rte_free(cld_filter);
8047                 return -EINVAL;
8048         }
8049
8050         pfilter->element.flags |= rte_cpu_to_le_16(
8051                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8052                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8053         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8054         pfilter->element.queue_number =
8055                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8056
8057         /* Check if there is the filter in SW list */
8058         memset(&check_filter, 0, sizeof(check_filter));
8059         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8060         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8061         if (add && node) {
8062                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8063                 rte_free(cld_filter);
8064                 return -EINVAL;
8065         }
8066
8067         if (!add && !node) {
8068                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8069                 rte_free(cld_filter);
8070                 return -EINVAL;
8071         }
8072
8073         if (add) {
8074                 ret = i40e_aq_add_cloud_filters(hw,
8075                                         vsi->seid, &cld_filter->element, 1);
8076                 if (ret < 0) {
8077                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8078                         rte_free(cld_filter);
8079                         return -ENOTSUP;
8080                 }
8081                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8082                 if (tunnel == NULL) {
8083                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8084                         rte_free(cld_filter);
8085                         return -ENOMEM;
8086                 }
8087
8088                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8089                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8090                 if (ret < 0)
8091                         rte_free(tunnel);
8092         } else {
8093                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8094                                                    &cld_filter->element, 1);
8095                 if (ret < 0) {
8096                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8097                         rte_free(cld_filter);
8098                         return -ENOTSUP;
8099                 }
8100                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8101         }
8102
8103         rte_free(cld_filter);
8104         return ret;
8105 }
8106
8107 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8108 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
8109 #define I40E_TR_GENEVE_KEY_MASK                 0x8
8110 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
8111 #define I40E_TR_GRE_KEY_MASK                    0x400
8112 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
8113 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
8114 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8115 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8116 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8117 #define I40E_DIRECTION_INGRESS_KEY              0x8000
8118 #define I40E_TR_L4_TYPE_TCP                     0x2
8119 #define I40E_TR_L4_TYPE_UDP                     0x4
8120 #define I40E_TR_L4_TYPE_SCTP                    0x8
8121
8122 static enum
8123 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8124 {
8125         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8126         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8127         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8128         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8129         enum i40e_status_code status = I40E_SUCCESS;
8130
8131         if (pf->support_multi_driver) {
8132                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8133                 return I40E_NOT_SUPPORTED;
8134         }
8135
8136         memset(&filter_replace, 0,
8137                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8138         memset(&filter_replace_buf, 0,
8139                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8140
8141         /* create L1 filter */
8142         filter_replace.old_filter_type =
8143                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8144         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8145         filter_replace.tr_bit = 0;
8146
8147         /* Prepare the buffer, 3 entries */
8148         filter_replace_buf.data[0] =
8149                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8150         filter_replace_buf.data[0] |=
8151                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8152         filter_replace_buf.data[2] = 0xFF;
8153         filter_replace_buf.data[3] = 0xFF;
8154         filter_replace_buf.data[4] =
8155                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8156         filter_replace_buf.data[4] |=
8157                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8158         filter_replace_buf.data[7] = 0xF0;
8159         filter_replace_buf.data[8]
8160                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8161         filter_replace_buf.data[8] |=
8162                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8163         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8164                 I40E_TR_GENEVE_KEY_MASK |
8165                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8166         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8167                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8168                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8169
8170         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8171                                                &filter_replace_buf);
8172         if (!status && (filter_replace.old_filter_type !=
8173                         filter_replace.new_filter_type))
8174                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8175                             " original: 0x%x, new: 0x%x",
8176                             dev->device->name,
8177                             filter_replace.old_filter_type,
8178                             filter_replace.new_filter_type);
8179
8180         return status;
8181 }
8182
8183 static enum
8184 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8185 {
8186         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8187         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8188         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8189         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8190         enum i40e_status_code status = I40E_SUCCESS;
8191
8192         if (pf->support_multi_driver) {
8193                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8194                 return I40E_NOT_SUPPORTED;
8195         }
8196
8197         /* For MPLSoUDP */
8198         memset(&filter_replace, 0,
8199                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8200         memset(&filter_replace_buf, 0,
8201                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8202         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8203                 I40E_AQC_MIRROR_CLOUD_FILTER;
8204         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8205         filter_replace.new_filter_type =
8206                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8207         /* Prepare the buffer, 2 entries */
8208         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8209         filter_replace_buf.data[0] |=
8210                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8211         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8212         filter_replace_buf.data[4] |=
8213                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8214         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8215                                                &filter_replace_buf);
8216         if (status < 0)
8217                 return status;
8218         if (filter_replace.old_filter_type !=
8219             filter_replace.new_filter_type)
8220                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8221                             " original: 0x%x, new: 0x%x",
8222                             dev->device->name,
8223                             filter_replace.old_filter_type,
8224                             filter_replace.new_filter_type);
8225
8226         /* For MPLSoGRE */
8227         memset(&filter_replace, 0,
8228                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8229         memset(&filter_replace_buf, 0,
8230                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8231
8232         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8233                 I40E_AQC_MIRROR_CLOUD_FILTER;
8234         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8235         filter_replace.new_filter_type =
8236                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8237         /* Prepare the buffer, 2 entries */
8238         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8239         filter_replace_buf.data[0] |=
8240                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8241         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8242         filter_replace_buf.data[4] |=
8243                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8244
8245         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8246                                                &filter_replace_buf);
8247         if (!status && (filter_replace.old_filter_type !=
8248                         filter_replace.new_filter_type))
8249                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8250                             " original: 0x%x, new: 0x%x",
8251                             dev->device->name,
8252                             filter_replace.old_filter_type,
8253                             filter_replace.new_filter_type);
8254
8255         return status;
8256 }
8257
8258 static enum i40e_status_code
8259 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8260 {
8261         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8262         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8263         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8264         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8265         enum i40e_status_code status = I40E_SUCCESS;
8266
8267         if (pf->support_multi_driver) {
8268                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8269                 return I40E_NOT_SUPPORTED;
8270         }
8271
8272         /* For GTP-C */
8273         memset(&filter_replace, 0,
8274                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8275         memset(&filter_replace_buf, 0,
8276                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8277         /* create L1 filter */
8278         filter_replace.old_filter_type =
8279                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8280         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8281         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8282                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8283         /* Prepare the buffer, 2 entries */
8284         filter_replace_buf.data[0] =
8285                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8286         filter_replace_buf.data[0] |=
8287                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8288         filter_replace_buf.data[2] = 0xFF;
8289         filter_replace_buf.data[3] = 0xFF;
8290         filter_replace_buf.data[4] =
8291                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8292         filter_replace_buf.data[4] |=
8293                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8294         filter_replace_buf.data[6] = 0xFF;
8295         filter_replace_buf.data[7] = 0xFF;
8296         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8297                                                &filter_replace_buf);
8298         if (status < 0)
8299                 return status;
8300         if (filter_replace.old_filter_type !=
8301             filter_replace.new_filter_type)
8302                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8303                             " original: 0x%x, new: 0x%x",
8304                             dev->device->name,
8305                             filter_replace.old_filter_type,
8306                             filter_replace.new_filter_type);
8307
8308         /* for GTP-U */
8309         memset(&filter_replace, 0,
8310                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8311         memset(&filter_replace_buf, 0,
8312                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8313         /* create L1 filter */
8314         filter_replace.old_filter_type =
8315                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8316         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8317         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8318                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8319         /* Prepare the buffer, 2 entries */
8320         filter_replace_buf.data[0] =
8321                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8322         filter_replace_buf.data[0] |=
8323                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8324         filter_replace_buf.data[2] = 0xFF;
8325         filter_replace_buf.data[3] = 0xFF;
8326         filter_replace_buf.data[4] =
8327                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8328         filter_replace_buf.data[4] |=
8329                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8330         filter_replace_buf.data[6] = 0xFF;
8331         filter_replace_buf.data[7] = 0xFF;
8332
8333         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8334                                                &filter_replace_buf);
8335         if (!status && (filter_replace.old_filter_type !=
8336                         filter_replace.new_filter_type))
8337                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8338                             " original: 0x%x, new: 0x%x",
8339                             dev->device->name,
8340                             filter_replace.old_filter_type,
8341                             filter_replace.new_filter_type);
8342
8343         return status;
8344 }
8345
8346 static enum
8347 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8348 {
8349         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8350         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8351         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8352         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8353         enum i40e_status_code status = I40E_SUCCESS;
8354
8355         if (pf->support_multi_driver) {
8356                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8357                 return I40E_NOT_SUPPORTED;
8358         }
8359
8360         /* for GTP-C */
8361         memset(&filter_replace, 0,
8362                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8363         memset(&filter_replace_buf, 0,
8364                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8365         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8366         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8367         filter_replace.new_filter_type =
8368                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8369         /* Prepare the buffer, 2 entries */
8370         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8371         filter_replace_buf.data[0] |=
8372                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8373         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8374         filter_replace_buf.data[4] |=
8375                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8376         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8377                                                &filter_replace_buf);
8378         if (status < 0)
8379                 return status;
8380         if (filter_replace.old_filter_type !=
8381             filter_replace.new_filter_type)
8382                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8383                             " original: 0x%x, new: 0x%x",
8384                             dev->device->name,
8385                             filter_replace.old_filter_type,
8386                             filter_replace.new_filter_type);
8387
8388         /* for GTP-U */
8389         memset(&filter_replace, 0,
8390                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8391         memset(&filter_replace_buf, 0,
8392                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8393         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8394         filter_replace.old_filter_type =
8395                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8396         filter_replace.new_filter_type =
8397                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8398         /* Prepare the buffer, 2 entries */
8399         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8400         filter_replace_buf.data[0] |=
8401                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8402         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8403         filter_replace_buf.data[4] |=
8404                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8405
8406         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8407                                                &filter_replace_buf);
8408         if (!status && (filter_replace.old_filter_type !=
8409                         filter_replace.new_filter_type))
8410                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8411                             " original: 0x%x, new: 0x%x",
8412                             dev->device->name,
8413                             filter_replace.old_filter_type,
8414                             filter_replace.new_filter_type);
8415
8416         return status;
8417 }
8418
8419 static enum i40e_status_code
8420 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8421                             enum i40e_l4_port_type l4_port_type)
8422 {
8423         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8424         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8425         enum i40e_status_code status = I40E_SUCCESS;
8426         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8427         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8428
8429         if (pf->support_multi_driver) {
8430                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8431                 return I40E_NOT_SUPPORTED;
8432         }
8433
8434         memset(&filter_replace, 0,
8435                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8436         memset(&filter_replace_buf, 0,
8437                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8438
8439         /* create L1 filter */
8440         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8441                 filter_replace.old_filter_type =
8442                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8443                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8444                 filter_replace_buf.data[8] =
8445                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8446         } else {
8447                 filter_replace.old_filter_type =
8448                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8449                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8450                 filter_replace_buf.data[8] =
8451                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8452         }
8453
8454         filter_replace.tr_bit = 0;
8455         /* Prepare the buffer, 3 entries */
8456         filter_replace_buf.data[0] =
8457                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8458         filter_replace_buf.data[0] |=
8459                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8460         filter_replace_buf.data[2] = 0x00;
8461         filter_replace_buf.data[3] =
8462                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8463         filter_replace_buf.data[4] =
8464                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8465         filter_replace_buf.data[4] |=
8466                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8467         filter_replace_buf.data[5] = 0x00;
8468         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8469                 I40E_TR_L4_TYPE_TCP |
8470                 I40E_TR_L4_TYPE_SCTP;
8471         filter_replace_buf.data[7] = 0x00;
8472         filter_replace_buf.data[8] |=
8473                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8474         filter_replace_buf.data[9] = 0x00;
8475         filter_replace_buf.data[10] = 0xFF;
8476         filter_replace_buf.data[11] = 0xFF;
8477
8478         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8479                                                &filter_replace_buf);
8480         if (!status && filter_replace.old_filter_type !=
8481             filter_replace.new_filter_type)
8482                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8483                             " original: 0x%x, new: 0x%x",
8484                             dev->device->name,
8485                             filter_replace.old_filter_type,
8486                             filter_replace.new_filter_type);
8487
8488         return status;
8489 }
8490
8491 static enum i40e_status_code
8492 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8493                                enum i40e_l4_port_type l4_port_type)
8494 {
8495         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8496         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8497         enum i40e_status_code status = I40E_SUCCESS;
8498         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8499         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8500
8501         if (pf->support_multi_driver) {
8502                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8503                 return I40E_NOT_SUPPORTED;
8504         }
8505
8506         memset(&filter_replace, 0,
8507                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8508         memset(&filter_replace_buf, 0,
8509                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8510
8511         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8512                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8513                 filter_replace.new_filter_type =
8514                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8515                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8516         } else {
8517                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8518                 filter_replace.new_filter_type =
8519                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8520                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8521         }
8522
8523         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8524         filter_replace.tr_bit = 0;
8525         /* Prepare the buffer, 2 entries */
8526         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8527         filter_replace_buf.data[0] |=
8528                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8529         filter_replace_buf.data[4] |=
8530                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8531         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8532                                                &filter_replace_buf);
8533
8534         if (!status && filter_replace.old_filter_type !=
8535             filter_replace.new_filter_type)
8536                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8537                             " original: 0x%x, new: 0x%x",
8538                             dev->device->name,
8539                             filter_replace.old_filter_type,
8540                             filter_replace.new_filter_type);
8541
8542         return status;
8543 }
8544
8545 int
8546 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8547                       struct i40e_tunnel_filter_conf *tunnel_filter,
8548                       uint8_t add)
8549 {
8550         uint16_t ip_type;
8551         uint32_t ipv4_addr, ipv4_addr_le;
8552         uint8_t i, tun_type = 0;
8553         /* internal variable to convert ipv6 byte order */
8554         uint32_t convert_ipv6[4];
8555         int val, ret = 0;
8556         struct i40e_pf_vf *vf = NULL;
8557         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8558         struct i40e_vsi *vsi;
8559         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8560         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8561         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8562         struct i40e_tunnel_filter *tunnel, *node;
8563         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8564         uint32_t teid_le;
8565         bool big_buffer = 0;
8566
8567         cld_filter = rte_zmalloc("tunnel_filter",
8568                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8569                          0);
8570
8571         if (cld_filter == NULL) {
8572                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8573                 return -ENOMEM;
8574         }
8575         pfilter = cld_filter;
8576
8577         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8578                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8579         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8580                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8581
8582         pfilter->element.inner_vlan =
8583                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8584         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8585                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8586                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8587                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8588                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8589                                 &ipv4_addr_le,
8590                                 sizeof(pfilter->element.ipaddr.v4.data));
8591         } else {
8592                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8593                 for (i = 0; i < 4; i++) {
8594                         convert_ipv6[i] =
8595                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8596                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8597                 }
8598                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8599                            &convert_ipv6,
8600                            sizeof(pfilter->element.ipaddr.v6.data));
8601         }
8602
8603         /* check tunneled type */
8604         switch (tunnel_filter->tunnel_type) {
8605         case I40E_TUNNEL_TYPE_VXLAN:
8606                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8607                 break;
8608         case I40E_TUNNEL_TYPE_NVGRE:
8609                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8610                 break;
8611         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8612                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8613                 break;
8614         case I40E_TUNNEL_TYPE_MPLSoUDP:
8615                 if (!pf->mpls_replace_flag) {
8616                         i40e_replace_mpls_l1_filter(pf);
8617                         i40e_replace_mpls_cloud_filter(pf);
8618                         pf->mpls_replace_flag = 1;
8619                 }
8620                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8621                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8622                         teid_le >> 4;
8623                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8624                         (teid_le & 0xF) << 12;
8625                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8626                         0x40;
8627                 big_buffer = 1;
8628                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8629                 break;
8630         case I40E_TUNNEL_TYPE_MPLSoGRE:
8631                 if (!pf->mpls_replace_flag) {
8632                         i40e_replace_mpls_l1_filter(pf);
8633                         i40e_replace_mpls_cloud_filter(pf);
8634                         pf->mpls_replace_flag = 1;
8635                 }
8636                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8637                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8638                         teid_le >> 4;
8639                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8640                         (teid_le & 0xF) << 12;
8641                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8642                         0x0;
8643                 big_buffer = 1;
8644                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8645                 break;
8646         case I40E_TUNNEL_TYPE_GTPC:
8647                 if (!pf->gtp_replace_flag) {
8648                         i40e_replace_gtp_l1_filter(pf);
8649                         i40e_replace_gtp_cloud_filter(pf);
8650                         pf->gtp_replace_flag = 1;
8651                 }
8652                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8653                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8654                         (teid_le >> 16) & 0xFFFF;
8655                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8656                         teid_le & 0xFFFF;
8657                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8658                         0x0;
8659                 big_buffer = 1;
8660                 break;
8661         case I40E_TUNNEL_TYPE_GTPU:
8662                 if (!pf->gtp_replace_flag) {
8663                         i40e_replace_gtp_l1_filter(pf);
8664                         i40e_replace_gtp_cloud_filter(pf);
8665                         pf->gtp_replace_flag = 1;
8666                 }
8667                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8668                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8669                         (teid_le >> 16) & 0xFFFF;
8670                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8671                         teid_le & 0xFFFF;
8672                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8673                         0x0;
8674                 big_buffer = 1;
8675                 break;
8676         case I40E_TUNNEL_TYPE_QINQ:
8677                 if (!pf->qinq_replace_flag) {
8678                         ret = i40e_cloud_filter_qinq_create(pf);
8679                         if (ret < 0)
8680                                 PMD_DRV_LOG(DEBUG,
8681                                             "QinQ tunnel filter already created.");
8682                         pf->qinq_replace_flag = 1;
8683                 }
8684                 /*      Add in the General fields the values of
8685                  *      the Outer and Inner VLAN
8686                  *      Big Buffer should be set, see changes in
8687                  *      i40e_aq_add_cloud_filters
8688                  */
8689                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8690                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8691                 big_buffer = 1;
8692                 break;
8693         case I40E_CLOUD_TYPE_UDP:
8694         case I40E_CLOUD_TYPE_TCP:
8695         case I40E_CLOUD_TYPE_SCTP:
8696                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8697                         if (!pf->sport_replace_flag) {
8698                                 i40e_replace_port_l1_filter(pf,
8699                                                 tunnel_filter->l4_port_type);
8700                                 i40e_replace_port_cloud_filter(pf,
8701                                                 tunnel_filter->l4_port_type);
8702                                 pf->sport_replace_flag = 1;
8703                         }
8704                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8705                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8706                                 I40E_DIRECTION_INGRESS_KEY;
8707
8708                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8709                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8710                                         I40E_TR_L4_TYPE_UDP;
8711                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8712                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8713                                         I40E_TR_L4_TYPE_TCP;
8714                         else
8715                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8716                                         I40E_TR_L4_TYPE_SCTP;
8717
8718                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8719                                 (teid_le >> 16) & 0xFFFF;
8720                         big_buffer = 1;
8721                 } else {
8722                         if (!pf->dport_replace_flag) {
8723                                 i40e_replace_port_l1_filter(pf,
8724                                                 tunnel_filter->l4_port_type);
8725                                 i40e_replace_port_cloud_filter(pf,
8726                                                 tunnel_filter->l4_port_type);
8727                                 pf->dport_replace_flag = 1;
8728                         }
8729                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8730                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8731                                 I40E_DIRECTION_INGRESS_KEY;
8732
8733                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8734                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8735                                         I40E_TR_L4_TYPE_UDP;
8736                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8737                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8738                                         I40E_TR_L4_TYPE_TCP;
8739                         else
8740                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8741                                         I40E_TR_L4_TYPE_SCTP;
8742
8743                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8744                                 (teid_le >> 16) & 0xFFFF;
8745                         big_buffer = 1;
8746                 }
8747
8748                 break;
8749         default:
8750                 /* Other tunnel types is not supported. */
8751                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8752                 rte_free(cld_filter);
8753                 return -EINVAL;
8754         }
8755
8756         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8757                 pfilter->element.flags =
8758                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8759         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8760                 pfilter->element.flags =
8761                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8762         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8763                 pfilter->element.flags =
8764                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8765         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8766                 pfilter->element.flags =
8767                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8768         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8769                 pfilter->element.flags |=
8770                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8771         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8772                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8773                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8774                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8775                         pfilter->element.flags |=
8776                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8777                 else
8778                         pfilter->element.flags |=
8779                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8780         } else {
8781                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8782                                                 &pfilter->element.flags);
8783                 if (val < 0) {
8784                         rte_free(cld_filter);
8785                         return -EINVAL;
8786                 }
8787         }
8788
8789         pfilter->element.flags |= rte_cpu_to_le_16(
8790                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8791                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8792         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8793         pfilter->element.queue_number =
8794                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8795
8796         if (!tunnel_filter->is_to_vf)
8797                 vsi = pf->main_vsi;
8798         else {
8799                 if (tunnel_filter->vf_id >= pf->vf_num) {
8800                         PMD_DRV_LOG(ERR, "Invalid argument.");
8801                         rte_free(cld_filter);
8802                         return -EINVAL;
8803                 }
8804                 vf = &pf->vfs[tunnel_filter->vf_id];
8805                 vsi = vf->vsi;
8806         }
8807
8808         /* Check if there is the filter in SW list */
8809         memset(&check_filter, 0, sizeof(check_filter));
8810         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8811         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8812         check_filter.vf_id = tunnel_filter->vf_id;
8813         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8814         if (add && node) {
8815                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8816                 rte_free(cld_filter);
8817                 return -EINVAL;
8818         }
8819
8820         if (!add && !node) {
8821                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8822                 rte_free(cld_filter);
8823                 return -EINVAL;
8824         }
8825
8826         if (add) {
8827                 if (big_buffer)
8828                         ret = i40e_aq_add_cloud_filters_bb(hw,
8829                                                    vsi->seid, cld_filter, 1);
8830                 else
8831                         ret = i40e_aq_add_cloud_filters(hw,
8832                                         vsi->seid, &cld_filter->element, 1);
8833                 if (ret < 0) {
8834                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8835                         rte_free(cld_filter);
8836                         return -ENOTSUP;
8837                 }
8838                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8839                 if (tunnel == NULL) {
8840                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8841                         rte_free(cld_filter);
8842                         return -ENOMEM;
8843                 }
8844
8845                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8846                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8847                 if (ret < 0)
8848                         rte_free(tunnel);
8849         } else {
8850                 if (big_buffer)
8851                         ret = i40e_aq_rem_cloud_filters_bb(
8852                                 hw, vsi->seid, cld_filter, 1);
8853                 else
8854                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8855                                                 &cld_filter->element, 1);
8856                 if (ret < 0) {
8857                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8858                         rte_free(cld_filter);
8859                         return -ENOTSUP;
8860                 }
8861                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8862         }
8863
8864         rte_free(cld_filter);
8865         return ret;
8866 }
8867
8868 static int
8869 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8870 {
8871         uint8_t i;
8872
8873         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8874                 if (pf->vxlan_ports[i] == port)
8875                         return i;
8876         }
8877
8878         return -1;
8879 }
8880
8881 static int
8882 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8883 {
8884         int  idx, ret;
8885         uint8_t filter_idx = 0;
8886         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8887
8888         idx = i40e_get_vxlan_port_idx(pf, port);
8889
8890         /* Check if port already exists */
8891         if (idx >= 0) {
8892                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8893                 return -EINVAL;
8894         }
8895
8896         /* Now check if there is space to add the new port */
8897         idx = i40e_get_vxlan_port_idx(pf, 0);
8898         if (idx < 0) {
8899                 PMD_DRV_LOG(ERR,
8900                         "Maximum number of UDP ports reached, not adding port %d",
8901                         port);
8902                 return -ENOSPC;
8903         }
8904
8905         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8906                                         &filter_idx, NULL);
8907         if (ret < 0) {
8908                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8909                 return -1;
8910         }
8911
8912         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8913                          port,  filter_idx);
8914
8915         /* New port: add it and mark its index in the bitmap */
8916         pf->vxlan_ports[idx] = port;
8917         pf->vxlan_bitmap |= (1 << idx);
8918
8919         if (!(pf->flags & I40E_FLAG_VXLAN))
8920                 pf->flags |= I40E_FLAG_VXLAN;
8921
8922         return 0;
8923 }
8924
8925 static int
8926 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8927 {
8928         int idx;
8929         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8930
8931         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8932                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8933                 return -EINVAL;
8934         }
8935
8936         idx = i40e_get_vxlan_port_idx(pf, port);
8937
8938         if (idx < 0) {
8939                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8940                 return -EINVAL;
8941         }
8942
8943         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8944                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8945                 return -1;
8946         }
8947
8948         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8949                         port, idx);
8950
8951         pf->vxlan_ports[idx] = 0;
8952         pf->vxlan_bitmap &= ~(1 << idx);
8953
8954         if (!pf->vxlan_bitmap)
8955                 pf->flags &= ~I40E_FLAG_VXLAN;
8956
8957         return 0;
8958 }
8959
8960 /* Add UDP tunneling port */
8961 static int
8962 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8963                              struct rte_eth_udp_tunnel *udp_tunnel)
8964 {
8965         int ret = 0;
8966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8967
8968         if (udp_tunnel == NULL)
8969                 return -EINVAL;
8970
8971         switch (udp_tunnel->prot_type) {
8972         case RTE_TUNNEL_TYPE_VXLAN:
8973                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8974                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8975                 break;
8976         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8977                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8978                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8979                 break;
8980         case RTE_TUNNEL_TYPE_GENEVE:
8981         case RTE_TUNNEL_TYPE_TEREDO:
8982                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8983                 ret = -1;
8984                 break;
8985
8986         default:
8987                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8988                 ret = -1;
8989                 break;
8990         }
8991
8992         return ret;
8993 }
8994
8995 /* Remove UDP tunneling port */
8996 static int
8997 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8998                              struct rte_eth_udp_tunnel *udp_tunnel)
8999 {
9000         int ret = 0;
9001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9002
9003         if (udp_tunnel == NULL)
9004                 return -EINVAL;
9005
9006         switch (udp_tunnel->prot_type) {
9007         case RTE_TUNNEL_TYPE_VXLAN:
9008         case RTE_TUNNEL_TYPE_VXLAN_GPE:
9009                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
9010                 break;
9011         case RTE_TUNNEL_TYPE_GENEVE:
9012         case RTE_TUNNEL_TYPE_TEREDO:
9013                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
9014                 ret = -1;
9015                 break;
9016         default:
9017                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
9018                 ret = -1;
9019                 break;
9020         }
9021
9022         return ret;
9023 }
9024
9025 /* Calculate the maximum number of contiguous PF queues that are configured */
9026 static int
9027 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
9028 {
9029         struct rte_eth_dev_data *data = pf->dev_data;
9030         int i, num;
9031         struct i40e_rx_queue *rxq;
9032
9033         num = 0;
9034         for (i = 0; i < pf->lan_nb_qps; i++) {
9035                 rxq = data->rx_queues[i];
9036                 if (rxq && rxq->q_set)
9037                         num++;
9038                 else
9039                         break;
9040         }
9041
9042         return num;
9043 }
9044
9045 /* Configure RSS */
9046 static int
9047 i40e_pf_config_rss(struct i40e_pf *pf)
9048 {
9049         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9050         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9051         struct rte_eth_rss_conf rss_conf;
9052         uint32_t i, lut = 0;
9053         uint16_t j, num;
9054
9055         /*
9056          * If both VMDQ and RSS enabled, not all of PF queues are configured.
9057          * It's necessary to calculate the actual PF queues that are configured.
9058          */
9059         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9060                 num = i40e_pf_calc_configured_queues_num(pf);
9061         else
9062                 num = pf->dev_data->nb_rx_queues;
9063
9064         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9065         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9066                         num);
9067
9068         if (num == 0) {
9069                 PMD_INIT_LOG(ERR,
9070                         "No PF queues are configured to enable RSS for port %u",
9071                         pf->dev_data->port_id);
9072                 return -ENOTSUP;
9073         }
9074
9075         if (pf->adapter->rss_reta_updated == 0) {
9076                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9077                         if (j == num)
9078                                 j = 0;
9079                         lut = (lut << 8) | (j & ((0x1 <<
9080                                 hw->func_caps.rss_table_entry_width) - 1));
9081                         if ((i & 3) == 3)
9082                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9083                                                rte_bswap32(lut));
9084                 }
9085         }
9086
9087         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9088         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
9089             !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
9090                 i40e_pf_disable_rss(pf);
9091                 return 0;
9092         }
9093         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9094                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9095                 /* Random default keys */
9096                 static uint32_t rss_key_default[] = {0x6b793944,
9097                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9098                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9099                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9100
9101                 rss_conf.rss_key = (uint8_t *)rss_key_default;
9102                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9103                                                         sizeof(uint32_t);
9104         }
9105
9106         return i40e_hw_rss_hash_set(pf, &rss_conf);
9107 }
9108
9109 static int
9110 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9111                                struct rte_eth_tunnel_filter_conf *filter)
9112 {
9113         if (pf == NULL || filter == NULL) {
9114                 PMD_DRV_LOG(ERR, "Invalid parameter");
9115                 return -EINVAL;
9116         }
9117
9118         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9119                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9120                 return -EINVAL;
9121         }
9122
9123         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9124                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9125                 return -EINVAL;
9126         }
9127
9128         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9129                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9130                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9131                 return -EINVAL;
9132         }
9133
9134         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9135                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9136                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9137                 return -EINVAL;
9138         }
9139
9140         return 0;
9141 }
9142
9143 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9144 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
9145 int
9146 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9147 {
9148         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9149         uint32_t val, reg;
9150         int ret = -EINVAL;
9151
9152         if (pf->support_multi_driver) {
9153                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9154                 return -ENOTSUP;
9155         }
9156
9157         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9158         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9159
9160         if (len == 3) {
9161                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9162         } else if (len == 4) {
9163                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9164         } else {
9165                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9166                 return ret;
9167         }
9168
9169         if (reg != val) {
9170                 ret = i40e_aq_debug_write_global_register(hw,
9171                                                    I40E_GL_PRS_FVBM(2),
9172                                                    reg, NULL);
9173                 if (ret != 0)
9174                         return ret;
9175                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9176                             "with value 0x%08x",
9177                             I40E_GL_PRS_FVBM(2), reg);
9178         } else {
9179                 ret = 0;
9180         }
9181         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9182                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9183
9184         return ret;
9185 }
9186
9187 static int
9188 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9189 {
9190         int ret = -EINVAL;
9191
9192         if (!hw || !cfg)
9193                 return -EINVAL;
9194
9195         switch (cfg->cfg_type) {
9196         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9197                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9198                 break;
9199         default:
9200                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9201                 break;
9202         }
9203
9204         return ret;
9205 }
9206
9207 static int
9208 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9209                                enum rte_filter_op filter_op,
9210                                void *arg)
9211 {
9212         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9213         int ret = I40E_ERR_PARAM;
9214
9215         switch (filter_op) {
9216         case RTE_ETH_FILTER_SET:
9217                 ret = i40e_dev_global_config_set(hw,
9218                         (struct rte_eth_global_cfg *)arg);
9219                 break;
9220         default:
9221                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9222                 break;
9223         }
9224
9225         return ret;
9226 }
9227
9228 static int
9229 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9230                           enum rte_filter_op filter_op,
9231                           void *arg)
9232 {
9233         struct rte_eth_tunnel_filter_conf *filter;
9234         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9235         int ret = I40E_SUCCESS;
9236
9237         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9238
9239         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9240                 return I40E_ERR_PARAM;
9241
9242         switch (filter_op) {
9243         case RTE_ETH_FILTER_NOP:
9244                 if (!(pf->flags & I40E_FLAG_VXLAN))
9245                         ret = I40E_NOT_SUPPORTED;
9246                 break;
9247         case RTE_ETH_FILTER_ADD:
9248                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9249                 break;
9250         case RTE_ETH_FILTER_DELETE:
9251                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9252                 break;
9253         default:
9254                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9255                 ret = I40E_ERR_PARAM;
9256                 break;
9257         }
9258
9259         return ret;
9260 }
9261
9262 /* Get the symmetric hash enable configurations per port */
9263 static void
9264 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9265 {
9266         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9267
9268         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9269 }
9270
9271 /* Set the symmetric hash enable configurations per port */
9272 static void
9273 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9274 {
9275         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9276
9277         if (enable > 0) {
9278                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9279                         PMD_DRV_LOG(INFO,
9280                                 "Symmetric hash has already been enabled");
9281                         return;
9282                 }
9283                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9284         } else {
9285                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9286                         PMD_DRV_LOG(INFO,
9287                                 "Symmetric hash has already been disabled");
9288                         return;
9289                 }
9290                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9291         }
9292         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9293         I40E_WRITE_FLUSH(hw);
9294 }
9295
9296 /*
9297  * Get global configurations of hash function type and symmetric hash enable
9298  * per flow type (pctype). Note that global configuration means it affects all
9299  * the ports on the same NIC.
9300  */
9301 static int
9302 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9303                                    struct rte_eth_hash_global_conf *g_cfg)
9304 {
9305         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9306         uint32_t reg;
9307         uint16_t i, j;
9308
9309         memset(g_cfg, 0, sizeof(*g_cfg));
9310         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9311         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9312                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9313         else
9314                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9315         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9316                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9317
9318         /*
9319          * As i40e supports less than 64 flow types, only first 64 bits need to
9320          * be checked.
9321          */
9322         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9323                 g_cfg->valid_bit_mask[i] = 0ULL;
9324                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9325         }
9326
9327         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9328
9329         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9330                 if (!adapter->pctypes_tbl[i])
9331                         continue;
9332                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9333                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9334                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9335                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9336                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9337                                         g_cfg->sym_hash_enable_mask[0] |=
9338                                                                 (1ULL << i);
9339                                 }
9340                         }
9341                 }
9342         }
9343
9344         return 0;
9345 }
9346
9347 static int
9348 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9349                               const struct rte_eth_hash_global_conf *g_cfg)
9350 {
9351         uint32_t i;
9352         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9353
9354         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9355                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9356                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9357                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9358                                                 g_cfg->hash_func);
9359                 return -EINVAL;
9360         }
9361
9362         /*
9363          * As i40e supports less than 64 flow types, only first 64 bits need to
9364          * be checked.
9365          */
9366         mask0 = g_cfg->valid_bit_mask[0];
9367         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9368                 if (i == 0) {
9369                         /* Check if any unsupported flow type configured */
9370                         if ((mask0 | i40e_mask) ^ i40e_mask)
9371                                 goto mask_err;
9372                 } else {
9373                         if (g_cfg->valid_bit_mask[i])
9374                                 goto mask_err;
9375                 }
9376         }
9377
9378         return 0;
9379
9380 mask_err:
9381         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9382
9383         return -EINVAL;
9384 }
9385
9386 /*
9387  * Set global configurations of hash function type and symmetric hash enable
9388  * per flow type (pctype). Note any modifying global configuration will affect
9389  * all the ports on the same NIC.
9390  */
9391 static int
9392 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9393                                    struct rte_eth_hash_global_conf *g_cfg)
9394 {
9395         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9396         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9397         int ret;
9398         uint16_t i, j;
9399         uint32_t reg;
9400         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9401
9402         if (pf->support_multi_driver) {
9403                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9404                 return -ENOTSUP;
9405         }
9406
9407         /* Check the input parameters */
9408         ret = i40e_hash_global_config_check(adapter, g_cfg);
9409         if (ret < 0)
9410                 return ret;
9411
9412         /*
9413          * As i40e supports less than 64 flow types, only first 64 bits need to
9414          * be configured.
9415          */
9416         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9417                 if (mask0 & (1UL << i)) {
9418                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9419                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9420
9421                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9422                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9423                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9424                                         i40e_write_global_rx_ctl(hw,
9425                                                           I40E_GLQF_HSYM(j),
9426                                                           reg);
9427                         }
9428                 }
9429         }
9430
9431         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9432         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9433                 /* Toeplitz */
9434                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9435                         PMD_DRV_LOG(DEBUG,
9436                                 "Hash function already set to Toeplitz");
9437                         goto out;
9438                 }
9439                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9440         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9441                 /* Simple XOR */
9442                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9443                         PMD_DRV_LOG(DEBUG,
9444                                 "Hash function already set to Simple XOR");
9445                         goto out;
9446                 }
9447                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9448         } else
9449                 /* Use the default, and keep it as it is */
9450                 goto out;
9451
9452         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9453
9454 out:
9455         I40E_WRITE_FLUSH(hw);
9456
9457         return 0;
9458 }
9459
9460 /**
9461  * Valid input sets for hash and flow director filters per PCTYPE
9462  */
9463 static uint64_t
9464 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9465                 enum rte_filter_type filter)
9466 {
9467         uint64_t valid;
9468
9469         static const uint64_t valid_hash_inset_table[] = {
9470                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9471                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9472                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9473                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9474                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9475                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9476                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9477                         I40E_INSET_FLEX_PAYLOAD,
9478                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9479                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9480                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9481                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9482                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9483                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9484                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9485                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9486                         I40E_INSET_FLEX_PAYLOAD,
9487                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9488                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9489                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9490                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9491                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9492                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9493                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9494                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9495                         I40E_INSET_FLEX_PAYLOAD,
9496                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9497                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9498                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9499                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9500                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9501                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9502                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9503                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9504                         I40E_INSET_FLEX_PAYLOAD,
9505                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9506                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9507                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9508                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9509                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9510                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9511                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9512                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9513                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9514                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9515                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9516                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9517                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9518                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9519                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9520                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9521                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9522                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9523                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9524                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9525                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9526                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9527                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9528                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9529                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9530                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9531                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9532                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9533                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9534                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9535                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9536                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9537                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9538                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9539                         I40E_INSET_FLEX_PAYLOAD,
9540                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9541                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9542                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9543                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9544                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9545                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9546                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9547                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9548                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9549                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9550                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9551                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9552                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9553                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9554                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9555                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9556                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9557                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9558                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9559                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9560                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9561                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9562                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9563                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9564                         I40E_INSET_FLEX_PAYLOAD,
9565                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9566                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9567                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9568                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9569                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9570                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9571                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9572                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9573                         I40E_INSET_FLEX_PAYLOAD,
9574                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9575                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9576                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9577                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9578                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9579                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9580                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9581                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9582                         I40E_INSET_FLEX_PAYLOAD,
9583                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9584                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9585                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9586                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9587                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9588                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9589                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9590                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9591                         I40E_INSET_FLEX_PAYLOAD,
9592                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9593                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9594                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9595                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9596                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9597                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9598                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9599                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9600                         I40E_INSET_FLEX_PAYLOAD,
9601                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9602                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9603                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9604                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9605                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9606                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9607                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9608                         I40E_INSET_FLEX_PAYLOAD,
9609                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9610                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9611                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9612                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9613                         I40E_INSET_FLEX_PAYLOAD,
9614         };
9615
9616         /**
9617          * Flow director supports only fields defined in
9618          * union rte_eth_fdir_flow.
9619          */
9620         static const uint64_t valid_fdir_inset_table[] = {
9621                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9622                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9623                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9624                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9625                 I40E_INSET_IPV4_TTL,
9626                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9627                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9628                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9629                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9630                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9631                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9632                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9633                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9634                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9635                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9636                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9637                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9638                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9639                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9640                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9641                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9642                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9643                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9644                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9645                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9646                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9647                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9648                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9649                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9650                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9651                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9652                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9653                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9654                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9655                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9656                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9657                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9658                 I40E_INSET_SCTP_VT,
9659                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9660                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9661                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9662                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9663                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9664                 I40E_INSET_IPV4_TTL,
9665                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9666                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9667                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9668                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9669                 I40E_INSET_IPV6_HOP_LIMIT,
9670                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9671                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9672                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9673                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9674                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9675                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9676                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9677                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9678                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9679                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9680                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9681                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9682                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9683                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9684                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9685                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9686                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9687                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9688                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9689                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9690                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9691                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9692                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9693                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9694                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9695                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9696                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9697                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9698                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9699                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9700                 I40E_INSET_SCTP_VT,
9701                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9702                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9703                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9704                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9705                 I40E_INSET_IPV6_HOP_LIMIT,
9706                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9707                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9708                 I40E_INSET_LAST_ETHER_TYPE,
9709         };
9710
9711         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9712                 return 0;
9713         if (filter == RTE_ETH_FILTER_HASH)
9714                 valid = valid_hash_inset_table[pctype];
9715         else
9716                 valid = valid_fdir_inset_table[pctype];
9717
9718         return valid;
9719 }
9720
9721 /**
9722  * Validate if the input set is allowed for a specific PCTYPE
9723  */
9724 int
9725 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9726                 enum rte_filter_type filter, uint64_t inset)
9727 {
9728         uint64_t valid;
9729
9730         valid = i40e_get_valid_input_set(pctype, filter);
9731         if (inset & (~valid))
9732                 return -EINVAL;
9733
9734         return 0;
9735 }
9736
9737 /* default input set fields combination per pctype */
9738 uint64_t
9739 i40e_get_default_input_set(uint16_t pctype)
9740 {
9741         static const uint64_t default_inset_table[] = {
9742                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9743                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9744                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9745                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9746                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9747                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9748                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9749                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9750                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9751                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9752                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9753                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9754                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9756                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9757                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9759                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9760                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9761                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9762                         I40E_INSET_SCTP_VT,
9763                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9764                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9765                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9766                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9767                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9768                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9769                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9770                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9771                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9772                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9773                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9774                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9775                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9776                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9777                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9779                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9780                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9782                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9783                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9784                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9785                         I40E_INSET_SCTP_VT,
9786                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9787                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9788                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9789                         I40E_INSET_LAST_ETHER_TYPE,
9790         };
9791
9792         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9793                 return 0;
9794
9795         return default_inset_table[pctype];
9796 }
9797
9798 /**
9799  * Parse the input set from index to logical bit masks
9800  */
9801 static int
9802 i40e_parse_input_set(uint64_t *inset,
9803                      enum i40e_filter_pctype pctype,
9804                      enum rte_eth_input_set_field *field,
9805                      uint16_t size)
9806 {
9807         uint16_t i, j;
9808         int ret = -EINVAL;
9809
9810         static const struct {
9811                 enum rte_eth_input_set_field field;
9812                 uint64_t inset;
9813         } inset_convert_table[] = {
9814                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9815                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9816                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9817                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9818                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9819                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9820                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9821                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9822                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9823                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9824                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9825                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9826                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9827                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9828                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9829                         I40E_INSET_IPV6_NEXT_HDR},
9830                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9831                         I40E_INSET_IPV6_HOP_LIMIT},
9832                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9833                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9834                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9835                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9836                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9837                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9838                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9839                         I40E_INSET_SCTP_VT},
9840                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9841                         I40E_INSET_TUNNEL_DMAC},
9842                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9843                         I40E_INSET_VLAN_TUNNEL},
9844                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9845                         I40E_INSET_TUNNEL_ID},
9846                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9847                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9848                         I40E_INSET_FLEX_PAYLOAD_W1},
9849                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9850                         I40E_INSET_FLEX_PAYLOAD_W2},
9851                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9852                         I40E_INSET_FLEX_PAYLOAD_W3},
9853                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9854                         I40E_INSET_FLEX_PAYLOAD_W4},
9855                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9856                         I40E_INSET_FLEX_PAYLOAD_W5},
9857                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9858                         I40E_INSET_FLEX_PAYLOAD_W6},
9859                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9860                         I40E_INSET_FLEX_PAYLOAD_W7},
9861                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9862                         I40E_INSET_FLEX_PAYLOAD_W8},
9863         };
9864
9865         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9866                 return ret;
9867
9868         /* Only one item allowed for default or all */
9869         if (size == 1) {
9870                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9871                         *inset = i40e_get_default_input_set(pctype);
9872                         return 0;
9873                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9874                         *inset = I40E_INSET_NONE;
9875                         return 0;
9876                 }
9877         }
9878
9879         for (i = 0, *inset = 0; i < size; i++) {
9880                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9881                         if (field[i] == inset_convert_table[j].field) {
9882                                 *inset |= inset_convert_table[j].inset;
9883                                 break;
9884                         }
9885                 }
9886
9887                 /* It contains unsupported input set, return immediately */
9888                 if (j == RTE_DIM(inset_convert_table))
9889                         return ret;
9890         }
9891
9892         return 0;
9893 }
9894
9895 /**
9896  * Translate the input set from bit masks to register aware bit masks
9897  * and vice versa
9898  */
9899 uint64_t
9900 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9901 {
9902         uint64_t val = 0;
9903         uint16_t i;
9904
9905         struct inset_map {
9906                 uint64_t inset;
9907                 uint64_t inset_reg;
9908         };
9909
9910         static const struct inset_map inset_map_common[] = {
9911                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9912                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9913                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9914                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9915                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9916                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9917                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9918                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9919                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9920                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9921                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9922                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9923                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9924                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9925                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9926                 {I40E_INSET_TUNNEL_DMAC,
9927                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9928                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9929                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9930                 {I40E_INSET_TUNNEL_SRC_PORT,
9931                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9932                 {I40E_INSET_TUNNEL_DST_PORT,
9933                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9934                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9935                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9936                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9937                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9938                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9939                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9940                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9941                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9942                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9943         };
9944
9945     /* some different registers map in x722*/
9946         static const struct inset_map inset_map_diff_x722[] = {
9947                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9948                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9949                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9950                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9951         };
9952
9953         static const struct inset_map inset_map_diff_not_x722[] = {
9954                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9955                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9956                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9957                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9958         };
9959
9960         if (input == 0)
9961                 return val;
9962
9963         /* Translate input set to register aware inset */
9964         if (type == I40E_MAC_X722) {
9965                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9966                         if (input & inset_map_diff_x722[i].inset)
9967                                 val |= inset_map_diff_x722[i].inset_reg;
9968                 }
9969         } else {
9970                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9971                         if (input & inset_map_diff_not_x722[i].inset)
9972                                 val |= inset_map_diff_not_x722[i].inset_reg;
9973                 }
9974         }
9975
9976         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9977                 if (input & inset_map_common[i].inset)
9978                         val |= inset_map_common[i].inset_reg;
9979         }
9980
9981         return val;
9982 }
9983
9984 int
9985 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9986 {
9987         uint8_t i, idx = 0;
9988         uint64_t inset_need_mask = inset;
9989
9990         static const struct {
9991                 uint64_t inset;
9992                 uint32_t mask;
9993         } inset_mask_map[] = {
9994                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9995                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9996                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9997                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9998                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9999                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
10000                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
10001                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
10002         };
10003
10004         if (!inset || !mask || !nb_elem)
10005                 return 0;
10006
10007         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10008                 /* Clear the inset bit, if no MASK is required,
10009                  * for example proto + ttl
10010                  */
10011                 if ((inset & inset_mask_map[i].inset) ==
10012                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
10013                         inset_need_mask &= ~inset_mask_map[i].inset;
10014                 if (!inset_need_mask)
10015                         return 0;
10016         }
10017         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
10018                 if ((inset_need_mask & inset_mask_map[i].inset) ==
10019                     inset_mask_map[i].inset) {
10020                         if (idx >= nb_elem) {
10021                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
10022                                 return -EINVAL;
10023                         }
10024                         mask[idx] = inset_mask_map[i].mask;
10025                         idx++;
10026                 }
10027         }
10028
10029         return idx;
10030 }
10031
10032 void
10033 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10034 {
10035         uint32_t reg = i40e_read_rx_ctl(hw, addr);
10036
10037         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
10038         if (reg != val)
10039                 i40e_write_rx_ctl(hw, addr, val);
10040         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
10041                     (uint32_t)i40e_read_rx_ctl(hw, addr));
10042 }
10043
10044 void
10045 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
10046 {
10047         uint32_t reg = i40e_read_rx_ctl(hw, addr);
10048         struct rte_eth_dev *dev;
10049
10050         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10051         if (reg != val) {
10052                 i40e_write_rx_ctl(hw, addr, val);
10053                 PMD_DRV_LOG(WARNING,
10054                             "i40e device %s changed global register [0x%08x]."
10055                             " original: 0x%08x, new: 0x%08x",
10056                             dev->device->name, addr, reg,
10057                             (uint32_t)i40e_read_rx_ctl(hw, addr));
10058         }
10059 }
10060
10061 static void
10062 i40e_filter_input_set_init(struct i40e_pf *pf)
10063 {
10064         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10065         enum i40e_filter_pctype pctype;
10066         uint64_t input_set, inset_reg;
10067         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10068         int num, i;
10069         uint16_t flow_type;
10070
10071         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10072              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10073                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10074
10075                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10076                         continue;
10077
10078                 input_set = i40e_get_default_input_set(pctype);
10079
10080                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10081                                                    I40E_INSET_MASK_NUM_REG);
10082                 if (num < 0)
10083                         return;
10084                 if (pf->support_multi_driver && num > 0) {
10085                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10086                         return;
10087                 }
10088                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10089                                         input_set);
10090
10091                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10092                                       (uint32_t)(inset_reg & UINT32_MAX));
10093                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10094                                      (uint32_t)((inset_reg >>
10095                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
10096                 if (!pf->support_multi_driver) {
10097                         i40e_check_write_global_reg(hw,
10098                                             I40E_GLQF_HASH_INSET(0, pctype),
10099                                             (uint32_t)(inset_reg & UINT32_MAX));
10100                         i40e_check_write_global_reg(hw,
10101                                              I40E_GLQF_HASH_INSET(1, pctype),
10102                                              (uint32_t)((inset_reg >>
10103                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
10104
10105                         for (i = 0; i < num; i++) {
10106                                 i40e_check_write_global_reg(hw,
10107                                                     I40E_GLQF_FD_MSK(i, pctype),
10108                                                     mask_reg[i]);
10109                                 i40e_check_write_global_reg(hw,
10110                                                   I40E_GLQF_HASH_MSK(i, pctype),
10111                                                   mask_reg[i]);
10112                         }
10113                         /*clear unused mask registers of the pctype */
10114                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10115                                 i40e_check_write_global_reg(hw,
10116                                                     I40E_GLQF_FD_MSK(i, pctype),
10117                                                     0);
10118                                 i40e_check_write_global_reg(hw,
10119                                                   I40E_GLQF_HASH_MSK(i, pctype),
10120                                                   0);
10121                         }
10122                 } else {
10123                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10124                 }
10125                 I40E_WRITE_FLUSH(hw);
10126
10127                 /* store the default input set */
10128                 if (!pf->support_multi_driver)
10129                         pf->hash_input_set[pctype] = input_set;
10130                 pf->fdir.input_set[pctype] = input_set;
10131         }
10132 }
10133
10134 int
10135 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10136                          struct rte_eth_input_set_conf *conf)
10137 {
10138         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10139         enum i40e_filter_pctype pctype;
10140         uint64_t input_set, inset_reg = 0;
10141         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10142         int ret, i, num;
10143
10144         if (!conf) {
10145                 PMD_DRV_LOG(ERR, "Invalid pointer");
10146                 return -EFAULT;
10147         }
10148         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10149             conf->op != RTE_ETH_INPUT_SET_ADD) {
10150                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10151                 return -EINVAL;
10152         }
10153
10154         if (pf->support_multi_driver) {
10155                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10156                 return -ENOTSUP;
10157         }
10158
10159         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10160         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10161                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10162                 return -EINVAL;
10163         }
10164
10165         if (hw->mac.type == I40E_MAC_X722) {
10166                 /* get translated pctype value in fd pctype register */
10167                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10168                         I40E_GLQF_FD_PCTYPES((int)pctype));
10169         }
10170
10171         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10172                                    conf->inset_size);
10173         if (ret) {
10174                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10175                 return -EINVAL;
10176         }
10177
10178         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10179                 /* get inset value in register */
10180                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10181                 inset_reg <<= I40E_32_BIT_WIDTH;
10182                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10183                 input_set |= pf->hash_input_set[pctype];
10184         }
10185         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10186                                            I40E_INSET_MASK_NUM_REG);
10187         if (num < 0)
10188                 return -EINVAL;
10189
10190         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10191
10192         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10193                                     (uint32_t)(inset_reg & UINT32_MAX));
10194         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10195                                     (uint32_t)((inset_reg >>
10196                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
10197
10198         for (i = 0; i < num; i++)
10199                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10200                                             mask_reg[i]);
10201         /*clear unused mask registers of the pctype */
10202         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10203                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10204                                             0);
10205         I40E_WRITE_FLUSH(hw);
10206
10207         pf->hash_input_set[pctype] = input_set;
10208         return 0;
10209 }
10210
10211 int
10212 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10213                          struct rte_eth_input_set_conf *conf)
10214 {
10215         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10216         enum i40e_filter_pctype pctype;
10217         uint64_t input_set, inset_reg = 0;
10218         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10219         int ret, i, num;
10220
10221         if (!hw || !conf) {
10222                 PMD_DRV_LOG(ERR, "Invalid pointer");
10223                 return -EFAULT;
10224         }
10225         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10226             conf->op != RTE_ETH_INPUT_SET_ADD) {
10227                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10228                 return -EINVAL;
10229         }
10230
10231         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10232
10233         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10234                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10235                 return -EINVAL;
10236         }
10237
10238         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10239                                    conf->inset_size);
10240         if (ret) {
10241                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10242                 return -EINVAL;
10243         }
10244
10245         /* get inset value in register */
10246         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10247         inset_reg <<= I40E_32_BIT_WIDTH;
10248         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10249
10250         /* Can not change the inset reg for flex payload for fdir,
10251          * it is done by writing I40E_PRTQF_FD_FLXINSET
10252          * in i40e_set_flex_mask_on_pctype.
10253          */
10254         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10255                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10256         else
10257                 input_set |= pf->fdir.input_set[pctype];
10258         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10259                                            I40E_INSET_MASK_NUM_REG);
10260         if (num < 0)
10261                 return -EINVAL;
10262         if (pf->support_multi_driver && num > 0) {
10263                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10264                 return -ENOTSUP;
10265         }
10266
10267         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10268
10269         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10270                               (uint32_t)(inset_reg & UINT32_MAX));
10271         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10272                              (uint32_t)((inset_reg >>
10273                              I40E_32_BIT_WIDTH) & UINT32_MAX));
10274
10275         if (!pf->support_multi_driver) {
10276                 for (i = 0; i < num; i++)
10277                         i40e_check_write_global_reg(hw,
10278                                                     I40E_GLQF_FD_MSK(i, pctype),
10279                                                     mask_reg[i]);
10280                 /*clear unused mask registers of the pctype */
10281                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10282                         i40e_check_write_global_reg(hw,
10283                                                     I40E_GLQF_FD_MSK(i, pctype),
10284                                                     0);
10285         } else {
10286                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10287         }
10288         I40E_WRITE_FLUSH(hw);
10289
10290         pf->fdir.input_set[pctype] = input_set;
10291         return 0;
10292 }
10293
10294 static int
10295 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10296 {
10297         int ret = 0;
10298
10299         if (!hw || !info) {
10300                 PMD_DRV_LOG(ERR, "Invalid pointer");
10301                 return -EFAULT;
10302         }
10303
10304         switch (info->info_type) {
10305         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10306                 i40e_get_symmetric_hash_enable_per_port(hw,
10307                                         &(info->info.enable));
10308                 break;
10309         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10310                 ret = i40e_get_hash_filter_global_config(hw,
10311                                 &(info->info.global_conf));
10312                 break;
10313         default:
10314                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10315                                                         info->info_type);
10316                 ret = -EINVAL;
10317                 break;
10318         }
10319
10320         return ret;
10321 }
10322
10323 static int
10324 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10325 {
10326         int ret = 0;
10327
10328         if (!hw || !info) {
10329                 PMD_DRV_LOG(ERR, "Invalid pointer");
10330                 return -EFAULT;
10331         }
10332
10333         switch (info->info_type) {
10334         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10335                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10336                 break;
10337         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10338                 ret = i40e_set_hash_filter_global_config(hw,
10339                                 &(info->info.global_conf));
10340                 break;
10341         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10342                 ret = i40e_hash_filter_inset_select(hw,
10343                                                &(info->info.input_set_conf));
10344                 break;
10345
10346         default:
10347                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10348                                                         info->info_type);
10349                 ret = -EINVAL;
10350                 break;
10351         }
10352
10353         return ret;
10354 }
10355
10356 /* Operations for hash function */
10357 static int
10358 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10359                       enum rte_filter_op filter_op,
10360                       void *arg)
10361 {
10362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10363         int ret = 0;
10364
10365         switch (filter_op) {
10366         case RTE_ETH_FILTER_NOP:
10367                 break;
10368         case RTE_ETH_FILTER_GET:
10369                 ret = i40e_hash_filter_get(hw,
10370                         (struct rte_eth_hash_filter_info *)arg);
10371                 break;
10372         case RTE_ETH_FILTER_SET:
10373                 ret = i40e_hash_filter_set(hw,
10374                         (struct rte_eth_hash_filter_info *)arg);
10375                 break;
10376         default:
10377                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10378                                                                 filter_op);
10379                 ret = -ENOTSUP;
10380                 break;
10381         }
10382
10383         return ret;
10384 }
10385
10386 /* Convert ethertype filter structure */
10387 static int
10388 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10389                               struct i40e_ethertype_filter *filter)
10390 {
10391         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10392                 RTE_ETHER_ADDR_LEN);
10393         filter->input.ether_type = input->ether_type;
10394         filter->flags = input->flags;
10395         filter->queue = input->queue;
10396
10397         return 0;
10398 }
10399
10400 /* Check if there exists the ehtertype filter */
10401 struct i40e_ethertype_filter *
10402 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10403                                 const struct i40e_ethertype_filter_input *input)
10404 {
10405         int ret;
10406
10407         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10408         if (ret < 0)
10409                 return NULL;
10410
10411         return ethertype_rule->hash_map[ret];
10412 }
10413
10414 /* Add ethertype filter in SW list */
10415 static int
10416 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10417                                 struct i40e_ethertype_filter *filter)
10418 {
10419         struct i40e_ethertype_rule *rule = &pf->ethertype;
10420         int ret;
10421
10422         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10423         if (ret < 0) {
10424                 PMD_DRV_LOG(ERR,
10425                             "Failed to insert ethertype filter"
10426                             " to hash table %d!",
10427                             ret);
10428                 return ret;
10429         }
10430         rule->hash_map[ret] = filter;
10431
10432         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10433
10434         return 0;
10435 }
10436
10437 /* Delete ethertype filter in SW list */
10438 int
10439 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10440                              struct i40e_ethertype_filter_input *input)
10441 {
10442         struct i40e_ethertype_rule *rule = &pf->ethertype;
10443         struct i40e_ethertype_filter *filter;
10444         int ret;
10445
10446         ret = rte_hash_del_key(rule->hash_table, input);
10447         if (ret < 0) {
10448                 PMD_DRV_LOG(ERR,
10449                             "Failed to delete ethertype filter"
10450                             " to hash table %d!",
10451                             ret);
10452                 return ret;
10453         }
10454         filter = rule->hash_map[ret];
10455         rule->hash_map[ret] = NULL;
10456
10457         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10458         rte_free(filter);
10459
10460         return 0;
10461 }
10462
10463 /*
10464  * Configure ethertype filter, which can director packet by filtering
10465  * with mac address and ether_type or only ether_type
10466  */
10467 int
10468 i40e_ethertype_filter_set(struct i40e_pf *pf,
10469                         struct rte_eth_ethertype_filter *filter,
10470                         bool add)
10471 {
10472         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10473         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10474         struct i40e_ethertype_filter *ethertype_filter, *node;
10475         struct i40e_ethertype_filter check_filter;
10476         struct i40e_control_filter_stats stats;
10477         uint16_t flags = 0;
10478         int ret;
10479
10480         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10481                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10482                 return -EINVAL;
10483         }
10484         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10485                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10486                 PMD_DRV_LOG(ERR,
10487                         "unsupported ether_type(0x%04x) in control packet filter.",
10488                         filter->ether_type);
10489                 return -EINVAL;
10490         }
10491         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10492                 PMD_DRV_LOG(WARNING,
10493                         "filter vlan ether_type in first tag is not supported.");
10494
10495         /* Check if there is the filter in SW list */
10496         memset(&check_filter, 0, sizeof(check_filter));
10497         i40e_ethertype_filter_convert(filter, &check_filter);
10498         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10499                                                &check_filter.input);
10500         if (add && node) {
10501                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10502                 return -EINVAL;
10503         }
10504
10505         if (!add && !node) {
10506                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10507                 return -EINVAL;
10508         }
10509
10510         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10511                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10512         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10513                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10514         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10515
10516         memset(&stats, 0, sizeof(stats));
10517         ret = i40e_aq_add_rem_control_packet_filter(hw,
10518                         filter->mac_addr.addr_bytes,
10519                         filter->ether_type, flags,
10520                         pf->main_vsi->seid,
10521                         filter->queue, add, &stats, NULL);
10522
10523         PMD_DRV_LOG(INFO,
10524                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10525                 ret, stats.mac_etype_used, stats.etype_used,
10526                 stats.mac_etype_free, stats.etype_free);
10527         if (ret < 0)
10528                 return -ENOSYS;
10529
10530         /* Add or delete a filter in SW list */
10531         if (add) {
10532                 ethertype_filter = rte_zmalloc("ethertype_filter",
10533                                        sizeof(*ethertype_filter), 0);
10534                 if (ethertype_filter == NULL) {
10535                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10536                         return -ENOMEM;
10537                 }
10538
10539                 rte_memcpy(ethertype_filter, &check_filter,
10540                            sizeof(check_filter));
10541                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10542                 if (ret < 0)
10543                         rte_free(ethertype_filter);
10544         } else {
10545                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10546         }
10547
10548         return ret;
10549 }
10550
10551 /*
10552  * Handle operations for ethertype filter.
10553  */
10554 static int
10555 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10556                                 enum rte_filter_op filter_op,
10557                                 void *arg)
10558 {
10559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10560         int ret = 0;
10561
10562         if (filter_op == RTE_ETH_FILTER_NOP)
10563                 return ret;
10564
10565         if (arg == NULL) {
10566                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10567                             filter_op);
10568                 return -EINVAL;
10569         }
10570
10571         switch (filter_op) {
10572         case RTE_ETH_FILTER_ADD:
10573                 ret = i40e_ethertype_filter_set(pf,
10574                         (struct rte_eth_ethertype_filter *)arg,
10575                         TRUE);
10576                 break;
10577         case RTE_ETH_FILTER_DELETE:
10578                 ret = i40e_ethertype_filter_set(pf,
10579                         (struct rte_eth_ethertype_filter *)arg,
10580                         FALSE);
10581                 break;
10582         default:
10583                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10584                 ret = -ENOSYS;
10585                 break;
10586         }
10587         return ret;
10588 }
10589
10590 static int
10591 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10592                      enum rte_filter_type filter_type,
10593                      enum rte_filter_op filter_op,
10594                      void *arg)
10595 {
10596         int ret = 0;
10597
10598         if (dev == NULL)
10599                 return -EINVAL;
10600
10601         switch (filter_type) {
10602         case RTE_ETH_FILTER_NONE:
10603                 /* For global configuration */
10604                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10605                 break;
10606         case RTE_ETH_FILTER_HASH:
10607                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10608                 break;
10609         case RTE_ETH_FILTER_MACVLAN:
10610                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10611                 break;
10612         case RTE_ETH_FILTER_ETHERTYPE:
10613                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10614                 break;
10615         case RTE_ETH_FILTER_TUNNEL:
10616                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10617                 break;
10618         case RTE_ETH_FILTER_FDIR:
10619                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10620                 break;
10621         case RTE_ETH_FILTER_GENERIC:
10622                 if (filter_op != RTE_ETH_FILTER_GET)
10623                         return -EINVAL;
10624                 *(const void **)arg = &i40e_flow_ops;
10625                 break;
10626         default:
10627                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10628                                                         filter_type);
10629                 ret = -EINVAL;
10630                 break;
10631         }
10632
10633         return ret;
10634 }
10635
10636 /*
10637  * Check and enable Extended Tag.
10638  * Enabling Extended Tag is important for 40G performance.
10639  */
10640 static void
10641 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10642 {
10643         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10644         uint32_t buf = 0;
10645         int ret;
10646
10647         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10648                                       PCI_DEV_CAP_REG);
10649         if (ret < 0) {
10650                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10651                             PCI_DEV_CAP_REG);
10652                 return;
10653         }
10654         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10655                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10656                 return;
10657         }
10658
10659         buf = 0;
10660         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10661                                       PCI_DEV_CTRL_REG);
10662         if (ret < 0) {
10663                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10664                             PCI_DEV_CTRL_REG);
10665                 return;
10666         }
10667         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10668                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10669                 return;
10670         }
10671         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10672         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10673                                        PCI_DEV_CTRL_REG);
10674         if (ret < 0) {
10675                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10676                             PCI_DEV_CTRL_REG);
10677                 return;
10678         }
10679 }
10680
10681 /*
10682  * As some registers wouldn't be reset unless a global hardware reset,
10683  * hardware initialization is needed to put those registers into an
10684  * expected initial state.
10685  */
10686 static void
10687 i40e_hw_init(struct rte_eth_dev *dev)
10688 {
10689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10690
10691         i40e_enable_extended_tag(dev);
10692
10693         /* clear the PF Queue Filter control register */
10694         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10695
10696         /* Disable symmetric hash per port */
10697         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10698 }
10699
10700 /*
10701  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10702  * however this function will return only one highest pctype index,
10703  * which is not quite correct. This is known problem of i40e driver
10704  * and needs to be fixed later.
10705  */
10706 enum i40e_filter_pctype
10707 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10708 {
10709         int i;
10710         uint64_t pctype_mask;
10711
10712         if (flow_type < I40E_FLOW_TYPE_MAX) {
10713                 pctype_mask = adapter->pctypes_tbl[flow_type];
10714                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10715                         if (pctype_mask & (1ULL << i))
10716                                 return (enum i40e_filter_pctype)i;
10717                 }
10718         }
10719         return I40E_FILTER_PCTYPE_INVALID;
10720 }
10721
10722 uint16_t
10723 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10724                         enum i40e_filter_pctype pctype)
10725 {
10726         uint16_t flowtype;
10727         uint64_t pctype_mask = 1ULL << pctype;
10728
10729         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10730              flowtype++) {
10731                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10732                         return flowtype;
10733         }
10734
10735         return RTE_ETH_FLOW_UNKNOWN;
10736 }
10737
10738 /*
10739  * On X710, performance number is far from the expectation on recent firmware
10740  * versions; on XL710, performance number is also far from the expectation on
10741  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10742  * mode is enabled and port MAC address is equal to the packet destination MAC
10743  * address. The fix for this issue may not be integrated in the following
10744  * firmware version. So the workaround in software driver is needed. It needs
10745  * to modify the initial values of 3 internal only registers for both X710 and
10746  * XL710. Note that the values for X710 or XL710 could be different, and the
10747  * workaround can be removed when it is fixed in firmware in the future.
10748  */
10749
10750 /* For both X710 and XL710 */
10751 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10752 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10753 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10754
10755 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10756 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10757
10758 /* For X722 */
10759 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10760 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10761
10762 /* For X710 */
10763 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10764 /* For XL710 */
10765 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10766 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10767
10768 /*
10769  * GL_SWR_PM_UP_THR:
10770  * The value is not impacted from the link speed, its value is set according
10771  * to the total number of ports for a better pipe-monitor configuration.
10772  */
10773 static bool
10774 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10775 {
10776 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10777                 .device_id = (dev),   \
10778                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10779
10780 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10781                 .device_id = (dev),   \
10782                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10783
10784         static const struct {
10785                 uint16_t device_id;
10786                 uint32_t val;
10787         } swr_pm_table[] = {
10788                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10789                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10790                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10791                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10792                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10793
10794                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10795                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10796                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10797                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10798                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10799                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10800                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10801         };
10802         uint32_t i;
10803
10804         if (value == NULL) {
10805                 PMD_DRV_LOG(ERR, "value is NULL");
10806                 return false;
10807         }
10808
10809         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10810                 if (hw->device_id == swr_pm_table[i].device_id) {
10811                         *value = swr_pm_table[i].val;
10812
10813                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10814                                     "value - 0x%08x",
10815                                     hw->device_id, *value);
10816                         return true;
10817                 }
10818         }
10819
10820         return false;
10821 }
10822
10823 static int
10824 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10825 {
10826         enum i40e_status_code status;
10827         struct i40e_aq_get_phy_abilities_resp phy_ab;
10828         int ret = -ENOTSUP;
10829         int retries = 0;
10830
10831         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10832                                               NULL);
10833
10834         while (status) {
10835                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10836                         status);
10837                 retries++;
10838                 rte_delay_us(100000);
10839                 if  (retries < 5)
10840                         status = i40e_aq_get_phy_capabilities(hw, false,
10841                                         true, &phy_ab, NULL);
10842                 else
10843                         return ret;
10844         }
10845         return 0;
10846 }
10847
10848 static void
10849 i40e_configure_registers(struct i40e_hw *hw)
10850 {
10851         static struct {
10852                 uint32_t addr;
10853                 uint64_t val;
10854         } reg_table[] = {
10855                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10856                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10857                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10858         };
10859         uint64_t reg;
10860         uint32_t i;
10861         int ret;
10862
10863         for (i = 0; i < RTE_DIM(reg_table); i++) {
10864                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10865                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10866                                 reg_table[i].val =
10867                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10868                         else /* For X710/XL710/XXV710 */
10869                                 if (hw->aq.fw_maj_ver < 6)
10870                                         reg_table[i].val =
10871                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10872                                 else
10873                                         reg_table[i].val =
10874                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10875                 }
10876
10877                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10878                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10879                                 reg_table[i].val =
10880                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10881                         else /* For X710/XL710/XXV710 */
10882                                 reg_table[i].val =
10883                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10884                 }
10885
10886                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10887                         uint32_t cfg_val;
10888
10889                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10890                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10891                                             "GL_SWR_PM_UP_THR value fixup",
10892                                             hw->device_id);
10893                                 continue;
10894                         }
10895
10896                         reg_table[i].val = cfg_val;
10897                 }
10898
10899                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10900                                                         &reg, NULL);
10901                 if (ret < 0) {
10902                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10903                                                         reg_table[i].addr);
10904                         break;
10905                 }
10906                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10907                                                 reg_table[i].addr, reg);
10908                 if (reg == reg_table[i].val)
10909                         continue;
10910
10911                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10912                                                 reg_table[i].val, NULL);
10913                 if (ret < 0) {
10914                         PMD_DRV_LOG(ERR,
10915                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10916                                 reg_table[i].val, reg_table[i].addr);
10917                         break;
10918                 }
10919                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10920                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10921         }
10922 }
10923
10924 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10925 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10926 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10927 static int
10928 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10929 {
10930         uint32_t reg;
10931         int ret;
10932
10933         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10934                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10935                 return -EINVAL;
10936         }
10937
10938         /* Configure for double VLAN RX stripping */
10939         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10940         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10941                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10942                 ret = i40e_aq_debug_write_register(hw,
10943                                                    I40E_VSI_TSR(vsi->vsi_id),
10944                                                    reg, NULL);
10945                 if (ret < 0) {
10946                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10947                                     vsi->vsi_id);
10948                         return I40E_ERR_CONFIG;
10949                 }
10950         }
10951
10952         /* Configure for double VLAN TX insertion */
10953         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10954         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10955                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10956                 ret = i40e_aq_debug_write_register(hw,
10957                                                    I40E_VSI_L2TAGSTXVALID(
10958                                                    vsi->vsi_id), reg, NULL);
10959                 if (ret < 0) {
10960                         PMD_DRV_LOG(ERR,
10961                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10962                                 vsi->vsi_id);
10963                         return I40E_ERR_CONFIG;
10964                 }
10965         }
10966
10967         return 0;
10968 }
10969
10970 /**
10971  * i40e_aq_add_mirror_rule
10972  * @hw: pointer to the hardware structure
10973  * @seid: VEB seid to add mirror rule to
10974  * @dst_id: destination vsi seid
10975  * @entries: Buffer which contains the entities to be mirrored
10976  * @count: number of entities contained in the buffer
10977  * @rule_id:the rule_id of the rule to be added
10978  *
10979  * Add a mirror rule for a given veb.
10980  *
10981  **/
10982 static enum i40e_status_code
10983 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10984                         uint16_t seid, uint16_t dst_id,
10985                         uint16_t rule_type, uint16_t *entries,
10986                         uint16_t count, uint16_t *rule_id)
10987 {
10988         struct i40e_aq_desc desc;
10989         struct i40e_aqc_add_delete_mirror_rule cmd;
10990         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10991                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10992                 &desc.params.raw;
10993         uint16_t buff_len;
10994         enum i40e_status_code status;
10995
10996         i40e_fill_default_direct_cmd_desc(&desc,
10997                                           i40e_aqc_opc_add_mirror_rule);
10998         memset(&cmd, 0, sizeof(cmd));
10999
11000         buff_len = sizeof(uint16_t) * count;
11001         desc.datalen = rte_cpu_to_le_16(buff_len);
11002         if (buff_len > 0)
11003                 desc.flags |= rte_cpu_to_le_16(
11004                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
11005         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11006                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11007         cmd.num_entries = rte_cpu_to_le_16(count);
11008         cmd.seid = rte_cpu_to_le_16(seid);
11009         cmd.destination = rte_cpu_to_le_16(dst_id);
11010
11011         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11012         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
11013         PMD_DRV_LOG(INFO,
11014                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
11015                 hw->aq.asq_last_status, resp->rule_id,
11016                 resp->mirror_rules_used, resp->mirror_rules_free);
11017         *rule_id = rte_le_to_cpu_16(resp->rule_id);
11018
11019         return status;
11020 }
11021
11022 /**
11023  * i40e_aq_del_mirror_rule
11024  * @hw: pointer to the hardware structure
11025  * @seid: VEB seid to add mirror rule to
11026  * @entries: Buffer which contains the entities to be mirrored
11027  * @count: number of entities contained in the buffer
11028  * @rule_id:the rule_id of the rule to be delete
11029  *
11030  * Delete a mirror rule for a given veb.
11031  *
11032  **/
11033 static enum i40e_status_code
11034 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
11035                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
11036                 uint16_t count, uint16_t rule_id)
11037 {
11038         struct i40e_aq_desc desc;
11039         struct i40e_aqc_add_delete_mirror_rule cmd;
11040         uint16_t buff_len = 0;
11041         enum i40e_status_code status;
11042         void *buff = NULL;
11043
11044         i40e_fill_default_direct_cmd_desc(&desc,
11045                                           i40e_aqc_opc_delete_mirror_rule);
11046         memset(&cmd, 0, sizeof(cmd));
11047         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11048                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11049                                                           I40E_AQ_FLAG_RD));
11050                 cmd.num_entries = count;
11051                 buff_len = sizeof(uint16_t) * count;
11052                 desc.datalen = rte_cpu_to_le_16(buff_len);
11053                 buff = (void *)entries;
11054         } else
11055                 /* rule id is filled in destination field for deleting mirror rule */
11056                 cmd.destination = rte_cpu_to_le_16(rule_id);
11057
11058         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11059                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11060         cmd.seid = rte_cpu_to_le_16(seid);
11061
11062         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11063         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11064
11065         return status;
11066 }
11067
11068 /**
11069  * i40e_mirror_rule_set
11070  * @dev: pointer to the hardware structure
11071  * @mirror_conf: mirror rule info
11072  * @sw_id: mirror rule's sw_id
11073  * @on: enable/disable
11074  *
11075  * set a mirror rule.
11076  *
11077  **/
11078 static int
11079 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11080                         struct rte_eth_mirror_conf *mirror_conf,
11081                         uint8_t sw_id, uint8_t on)
11082 {
11083         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11085         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11086         struct i40e_mirror_rule *parent = NULL;
11087         uint16_t seid, dst_seid, rule_id;
11088         uint16_t i, j = 0;
11089         int ret;
11090
11091         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11092
11093         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11094                 PMD_DRV_LOG(ERR,
11095                         "mirror rule can not be configured without veb or vfs.");
11096                 return -ENOSYS;
11097         }
11098         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11099                 PMD_DRV_LOG(ERR, "mirror table is full.");
11100                 return -ENOSPC;
11101         }
11102         if (mirror_conf->dst_pool > pf->vf_num) {
11103                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11104                                  mirror_conf->dst_pool);
11105                 return -EINVAL;
11106         }
11107
11108         seid = pf->main_vsi->veb->seid;
11109
11110         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11111                 if (sw_id <= it->index) {
11112                         mirr_rule = it;
11113                         break;
11114                 }
11115                 parent = it;
11116         }
11117         if (mirr_rule && sw_id == mirr_rule->index) {
11118                 if (on) {
11119                         PMD_DRV_LOG(ERR, "mirror rule exists.");
11120                         return -EEXIST;
11121                 } else {
11122                         ret = i40e_aq_del_mirror_rule(hw, seid,
11123                                         mirr_rule->rule_type,
11124                                         mirr_rule->entries,
11125                                         mirr_rule->num_entries, mirr_rule->id);
11126                         if (ret < 0) {
11127                                 PMD_DRV_LOG(ERR,
11128                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
11129                                         ret, hw->aq.asq_last_status);
11130                                 return -ENOSYS;
11131                         }
11132                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11133                         rte_free(mirr_rule);
11134                         pf->nb_mirror_rule--;
11135                         return 0;
11136                 }
11137         } else if (!on) {
11138                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11139                 return -ENOENT;
11140         }
11141
11142         mirr_rule = rte_zmalloc("i40e_mirror_rule",
11143                                 sizeof(struct i40e_mirror_rule) , 0);
11144         if (!mirr_rule) {
11145                 PMD_DRV_LOG(ERR, "failed to allocate memory");
11146                 return I40E_ERR_NO_MEMORY;
11147         }
11148         switch (mirror_conf->rule_type) {
11149         case ETH_MIRROR_VLAN:
11150                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11151                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11152                                 mirr_rule->entries[j] =
11153                                         mirror_conf->vlan.vlan_id[i];
11154                                 j++;
11155                         }
11156                 }
11157                 if (j == 0) {
11158                         PMD_DRV_LOG(ERR, "vlan is not specified.");
11159                         rte_free(mirr_rule);
11160                         return -EINVAL;
11161                 }
11162                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11163                 break;
11164         case ETH_MIRROR_VIRTUAL_POOL_UP:
11165         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11166                 /* check if the specified pool bit is out of range */
11167                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11168                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
11169                         rte_free(mirr_rule);
11170                         return -EINVAL;
11171                 }
11172                 for (i = 0, j = 0; i < pf->vf_num; i++) {
11173                         if (mirror_conf->pool_mask & (1ULL << i)) {
11174                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11175                                 j++;
11176                         }
11177                 }
11178                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11179                         /* add pf vsi to entries */
11180                         mirr_rule->entries[j] = pf->main_vsi_seid;
11181                         j++;
11182                 }
11183                 if (j == 0) {
11184                         PMD_DRV_LOG(ERR, "pool is not specified.");
11185                         rte_free(mirr_rule);
11186                         return -EINVAL;
11187                 }
11188                 /* egress and ingress in aq commands means from switch but not port */
11189                 mirr_rule->rule_type =
11190                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11191                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11192                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11193                 break;
11194         case ETH_MIRROR_UPLINK_PORT:
11195                 /* egress and ingress in aq commands means from switch but not port*/
11196                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11197                 break;
11198         case ETH_MIRROR_DOWNLINK_PORT:
11199                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11200                 break;
11201         default:
11202                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11203                         mirror_conf->rule_type);
11204                 rte_free(mirr_rule);
11205                 return -EINVAL;
11206         }
11207
11208         /* If the dst_pool is equal to vf_num, consider it as PF */
11209         if (mirror_conf->dst_pool == pf->vf_num)
11210                 dst_seid = pf->main_vsi_seid;
11211         else
11212                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11213
11214         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11215                                       mirr_rule->rule_type, mirr_rule->entries,
11216                                       j, &rule_id);
11217         if (ret < 0) {
11218                 PMD_DRV_LOG(ERR,
11219                         "failed to add mirror rule: ret = %d, aq_err = %d.",
11220                         ret, hw->aq.asq_last_status);
11221                 rte_free(mirr_rule);
11222                 return -ENOSYS;
11223         }
11224
11225         mirr_rule->index = sw_id;
11226         mirr_rule->num_entries = j;
11227         mirr_rule->id = rule_id;
11228         mirr_rule->dst_vsi_seid = dst_seid;
11229
11230         if (parent)
11231                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11232         else
11233                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11234
11235         pf->nb_mirror_rule++;
11236         return 0;
11237 }
11238
11239 /**
11240  * i40e_mirror_rule_reset
11241  * @dev: pointer to the device
11242  * @sw_id: mirror rule's sw_id
11243  *
11244  * reset a mirror rule.
11245  *
11246  **/
11247 static int
11248 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11249 {
11250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11251         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11252         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11253         uint16_t seid;
11254         int ret;
11255
11256         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11257
11258         seid = pf->main_vsi->veb->seid;
11259
11260         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11261                 if (sw_id == it->index) {
11262                         mirr_rule = it;
11263                         break;
11264                 }
11265         }
11266         if (mirr_rule) {
11267                 ret = i40e_aq_del_mirror_rule(hw, seid,
11268                                 mirr_rule->rule_type,
11269                                 mirr_rule->entries,
11270                                 mirr_rule->num_entries, mirr_rule->id);
11271                 if (ret < 0) {
11272                         PMD_DRV_LOG(ERR,
11273                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
11274                                 ret, hw->aq.asq_last_status);
11275                         return -ENOSYS;
11276                 }
11277                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11278                 rte_free(mirr_rule);
11279                 pf->nb_mirror_rule--;
11280         } else {
11281                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11282                 return -ENOENT;
11283         }
11284         return 0;
11285 }
11286
11287 static uint64_t
11288 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11289 {
11290         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11291         uint64_t systim_cycles;
11292
11293         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11294         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11295                         << 32;
11296
11297         return systim_cycles;
11298 }
11299
11300 static uint64_t
11301 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11302 {
11303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11304         uint64_t rx_tstamp;
11305
11306         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11307         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11308                         << 32;
11309
11310         return rx_tstamp;
11311 }
11312
11313 static uint64_t
11314 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11315 {
11316         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11317         uint64_t tx_tstamp;
11318
11319         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11320         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11321                         << 32;
11322
11323         return tx_tstamp;
11324 }
11325
11326 static void
11327 i40e_start_timecounters(struct rte_eth_dev *dev)
11328 {
11329         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11330         struct i40e_adapter *adapter = dev->data->dev_private;
11331         struct rte_eth_link link;
11332         uint32_t tsync_inc_l;
11333         uint32_t tsync_inc_h;
11334
11335         /* Get current link speed. */
11336         i40e_dev_link_update(dev, 1);
11337         rte_eth_linkstatus_get(dev, &link);
11338
11339         switch (link.link_speed) {
11340         case ETH_SPEED_NUM_40G:
11341         case ETH_SPEED_NUM_25G:
11342                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11343                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11344                 break;
11345         case ETH_SPEED_NUM_10G:
11346                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11347                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11348                 break;
11349         case ETH_SPEED_NUM_1G:
11350                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11351                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11352                 break;
11353         default:
11354                 tsync_inc_l = 0x0;
11355                 tsync_inc_h = 0x0;
11356         }
11357
11358         /* Set the timesync increment value. */
11359         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11360         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11361
11362         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11363         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11364         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11365
11366         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11367         adapter->systime_tc.cc_shift = 0;
11368         adapter->systime_tc.nsec_mask = 0;
11369
11370         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11371         adapter->rx_tstamp_tc.cc_shift = 0;
11372         adapter->rx_tstamp_tc.nsec_mask = 0;
11373
11374         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11375         adapter->tx_tstamp_tc.cc_shift = 0;
11376         adapter->tx_tstamp_tc.nsec_mask = 0;
11377 }
11378
11379 static int
11380 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11381 {
11382         struct i40e_adapter *adapter = dev->data->dev_private;
11383
11384         adapter->systime_tc.nsec += delta;
11385         adapter->rx_tstamp_tc.nsec += delta;
11386         adapter->tx_tstamp_tc.nsec += delta;
11387
11388         return 0;
11389 }
11390
11391 static int
11392 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11393 {
11394         uint64_t ns;
11395         struct i40e_adapter *adapter = dev->data->dev_private;
11396
11397         ns = rte_timespec_to_ns(ts);
11398
11399         /* Set the timecounters to a new value. */
11400         adapter->systime_tc.nsec = ns;
11401         adapter->rx_tstamp_tc.nsec = ns;
11402         adapter->tx_tstamp_tc.nsec = ns;
11403
11404         return 0;
11405 }
11406
11407 static int
11408 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11409 {
11410         uint64_t ns, systime_cycles;
11411         struct i40e_adapter *adapter = dev->data->dev_private;
11412
11413         systime_cycles = i40e_read_systime_cyclecounter(dev);
11414         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11415         *ts = rte_ns_to_timespec(ns);
11416
11417         return 0;
11418 }
11419
11420 static int
11421 i40e_timesync_enable(struct rte_eth_dev *dev)
11422 {
11423         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11424         uint32_t tsync_ctl_l;
11425         uint32_t tsync_ctl_h;
11426
11427         /* Stop the timesync system time. */
11428         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11429         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11430         /* Reset the timesync system time value. */
11431         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11432         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11433
11434         i40e_start_timecounters(dev);
11435
11436         /* Clear timesync registers. */
11437         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11438         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11439         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11440         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11441         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11442         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11443
11444         /* Enable timestamping of PTP packets. */
11445         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11446         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11447
11448         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11449         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11450         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11451
11452         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11453         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11454
11455         return 0;
11456 }
11457
11458 static int
11459 i40e_timesync_disable(struct rte_eth_dev *dev)
11460 {
11461         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11462         uint32_t tsync_ctl_l;
11463         uint32_t tsync_ctl_h;
11464
11465         /* Disable timestamping of transmitted PTP packets. */
11466         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11467         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11468
11469         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11470         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11471
11472         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11473         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11474
11475         /* Reset the timesync increment value. */
11476         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11477         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11478
11479         return 0;
11480 }
11481
11482 static int
11483 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11484                                 struct timespec *timestamp, uint32_t flags)
11485 {
11486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11487         struct i40e_adapter *adapter = dev->data->dev_private;
11488         uint32_t sync_status;
11489         uint32_t index = flags & 0x03;
11490         uint64_t rx_tstamp_cycles;
11491         uint64_t ns;
11492
11493         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11494         if ((sync_status & (1 << index)) == 0)
11495                 return -EINVAL;
11496
11497         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11498         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11499         *timestamp = rte_ns_to_timespec(ns);
11500
11501         return 0;
11502 }
11503
11504 static int
11505 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11506                                 struct timespec *timestamp)
11507 {
11508         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11509         struct i40e_adapter *adapter = dev->data->dev_private;
11510         uint32_t sync_status;
11511         uint64_t tx_tstamp_cycles;
11512         uint64_t ns;
11513
11514         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11515         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11516                 return -EINVAL;
11517
11518         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11519         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11520         *timestamp = rte_ns_to_timespec(ns);
11521
11522         return 0;
11523 }
11524
11525 /*
11526  * i40e_parse_dcb_configure - parse dcb configure from user
11527  * @dev: the device being configured
11528  * @dcb_cfg: pointer of the result of parse
11529  * @*tc_map: bit map of enabled traffic classes
11530  *
11531  * Returns 0 on success, negative value on failure
11532  */
11533 static int
11534 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11535                          struct i40e_dcbx_config *dcb_cfg,
11536                          uint8_t *tc_map)
11537 {
11538         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11539         uint8_t i, tc_bw, bw_lf;
11540
11541         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11542
11543         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11544         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11545                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11546                 return -EINVAL;
11547         }
11548
11549         /* assume each tc has the same bw */
11550         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11551         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11552                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11553         /* to ensure the sum of tcbw is equal to 100 */
11554         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11555         for (i = 0; i < bw_lf; i++)
11556                 dcb_cfg->etscfg.tcbwtable[i]++;
11557
11558         /* assume each tc has the same Transmission Selection Algorithm */
11559         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11560                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11561
11562         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11563                 dcb_cfg->etscfg.prioritytable[i] =
11564                                 dcb_rx_conf->dcb_tc[i];
11565
11566         /* FW needs one App to configure HW */
11567         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11568         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11569         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11570         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11571
11572         if (dcb_rx_conf->nb_tcs == 0)
11573                 *tc_map = 1; /* tc0 only */
11574         else
11575                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11576
11577         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11578                 dcb_cfg->pfc.willing = 0;
11579                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11580                 dcb_cfg->pfc.pfcenable = *tc_map;
11581         }
11582         return 0;
11583 }
11584
11585
11586 static enum i40e_status_code
11587 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11588                               struct i40e_aqc_vsi_properties_data *info,
11589                               uint8_t enabled_tcmap)
11590 {
11591         enum i40e_status_code ret;
11592         int i, total_tc = 0;
11593         uint16_t qpnum_per_tc, bsf, qp_idx;
11594         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11595         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11596         uint16_t used_queues;
11597
11598         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11599         if (ret != I40E_SUCCESS)
11600                 return ret;
11601
11602         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11603                 if (enabled_tcmap & (1 << i))
11604                         total_tc++;
11605         }
11606         if (total_tc == 0)
11607                 total_tc = 1;
11608         vsi->enabled_tc = enabled_tcmap;
11609
11610         /* different VSI has different queues assigned */
11611         if (vsi->type == I40E_VSI_MAIN)
11612                 used_queues = dev_data->nb_rx_queues -
11613                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11614         else if (vsi->type == I40E_VSI_VMDQ2)
11615                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11616         else {
11617                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11618                 return I40E_ERR_NO_AVAILABLE_VSI;
11619         }
11620
11621         qpnum_per_tc = used_queues / total_tc;
11622         /* Number of queues per enabled TC */
11623         if (qpnum_per_tc == 0) {
11624                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11625                 return I40E_ERR_INVALID_QP_ID;
11626         }
11627         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11628                                 I40E_MAX_Q_PER_TC);
11629         bsf = rte_bsf32(qpnum_per_tc);
11630
11631         /**
11632          * Configure TC and queue mapping parameters, for enabled TC,
11633          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11634          * default queue will serve it.
11635          */
11636         qp_idx = 0;
11637         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11638                 if (vsi->enabled_tc & (1 << i)) {
11639                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11640                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11641                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11642                         qp_idx += qpnum_per_tc;
11643                 } else
11644                         info->tc_mapping[i] = 0;
11645         }
11646
11647         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11648         if (vsi->type == I40E_VSI_SRIOV) {
11649                 info->mapping_flags |=
11650                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11651                 for (i = 0; i < vsi->nb_qps; i++)
11652                         info->queue_mapping[i] =
11653                                 rte_cpu_to_le_16(vsi->base_queue + i);
11654         } else {
11655                 info->mapping_flags |=
11656                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11657                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11658         }
11659         info->valid_sections |=
11660                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11661
11662         return I40E_SUCCESS;
11663 }
11664
11665 /*
11666  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11667  * @veb: VEB to be configured
11668  * @tc_map: enabled TC bitmap
11669  *
11670  * Returns 0 on success, negative value on failure
11671  */
11672 static enum i40e_status_code
11673 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11674 {
11675         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11676         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11677         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11678         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11679         enum i40e_status_code ret = I40E_SUCCESS;
11680         int i;
11681         uint32_t bw_max;
11682
11683         /* Check if enabled_tc is same as existing or new TCs */
11684         if (veb->enabled_tc == tc_map)
11685                 return ret;
11686
11687         /* configure tc bandwidth */
11688         memset(&veb_bw, 0, sizeof(veb_bw));
11689         veb_bw.tc_valid_bits = tc_map;
11690         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11691         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11692                 if (tc_map & BIT_ULL(i))
11693                         veb_bw.tc_bw_share_credits[i] = 1;
11694         }
11695         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11696                                                    &veb_bw, NULL);
11697         if (ret) {
11698                 PMD_INIT_LOG(ERR,
11699                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11700                         hw->aq.asq_last_status);
11701                 return ret;
11702         }
11703
11704         memset(&ets_query, 0, sizeof(ets_query));
11705         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11706                                                    &ets_query, NULL);
11707         if (ret != I40E_SUCCESS) {
11708                 PMD_DRV_LOG(ERR,
11709                         "Failed to get switch_comp ETS configuration %u",
11710                         hw->aq.asq_last_status);
11711                 return ret;
11712         }
11713         memset(&bw_query, 0, sizeof(bw_query));
11714         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11715                                                   &bw_query, NULL);
11716         if (ret != I40E_SUCCESS) {
11717                 PMD_DRV_LOG(ERR,
11718                         "Failed to get switch_comp bandwidth configuration %u",
11719                         hw->aq.asq_last_status);
11720                 return ret;
11721         }
11722
11723         /* store and print out BW info */
11724         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11725         veb->bw_info.bw_max = ets_query.tc_bw_max;
11726         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11727         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11728         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11729                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11730                      I40E_16_BIT_WIDTH);
11731         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11732                 veb->bw_info.bw_ets_share_credits[i] =
11733                                 bw_query.tc_bw_share_credits[i];
11734                 veb->bw_info.bw_ets_credits[i] =
11735                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11736                 /* 4 bits per TC, 4th bit is reserved */
11737                 veb->bw_info.bw_ets_max[i] =
11738                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11739                                   RTE_LEN2MASK(3, uint8_t));
11740                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11741                             veb->bw_info.bw_ets_share_credits[i]);
11742                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11743                             veb->bw_info.bw_ets_credits[i]);
11744                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11745                             veb->bw_info.bw_ets_max[i]);
11746         }
11747
11748         veb->enabled_tc = tc_map;
11749
11750         return ret;
11751 }
11752
11753
11754 /*
11755  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11756  * @vsi: VSI to be configured
11757  * @tc_map: enabled TC bitmap
11758  *
11759  * Returns 0 on success, negative value on failure
11760  */
11761 static enum i40e_status_code
11762 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11763 {
11764         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11765         struct i40e_vsi_context ctxt;
11766         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11767         enum i40e_status_code ret = I40E_SUCCESS;
11768         int i;
11769
11770         /* Check if enabled_tc is same as existing or new TCs */
11771         if (vsi->enabled_tc == tc_map)
11772                 return ret;
11773
11774         /* configure tc bandwidth */
11775         memset(&bw_data, 0, sizeof(bw_data));
11776         bw_data.tc_valid_bits = tc_map;
11777         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11778         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11779                 if (tc_map & BIT_ULL(i))
11780                         bw_data.tc_bw_credits[i] = 1;
11781         }
11782         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11783         if (ret) {
11784                 PMD_INIT_LOG(ERR,
11785                         "AQ command Config VSI BW allocation per TC failed = %d",
11786                         hw->aq.asq_last_status);
11787                 goto out;
11788         }
11789         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11790                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11791
11792         /* Update Queue Pairs Mapping for currently enabled UPs */
11793         ctxt.seid = vsi->seid;
11794         ctxt.pf_num = hw->pf_id;
11795         ctxt.vf_num = 0;
11796         ctxt.uplink_seid = vsi->uplink_seid;
11797         ctxt.info = vsi->info;
11798         i40e_get_cap(hw);
11799         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11800         if (ret)
11801                 goto out;
11802
11803         /* Update the VSI after updating the VSI queue-mapping information */
11804         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11805         if (ret) {
11806                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11807                         hw->aq.asq_last_status);
11808                 goto out;
11809         }
11810         /* update the local VSI info with updated queue map */
11811         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11812                                         sizeof(vsi->info.tc_mapping));
11813         rte_memcpy(&vsi->info.queue_mapping,
11814                         &ctxt.info.queue_mapping,
11815                 sizeof(vsi->info.queue_mapping));
11816         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11817         vsi->info.valid_sections = 0;
11818
11819         /* query and update current VSI BW information */
11820         ret = i40e_vsi_get_bw_config(vsi);
11821         if (ret) {
11822                 PMD_INIT_LOG(ERR,
11823                          "Failed updating vsi bw info, err %s aq_err %s",
11824                          i40e_stat_str(hw, ret),
11825                          i40e_aq_str(hw, hw->aq.asq_last_status));
11826                 goto out;
11827         }
11828
11829         vsi->enabled_tc = tc_map;
11830
11831 out:
11832         return ret;
11833 }
11834
11835 /*
11836  * i40e_dcb_hw_configure - program the dcb setting to hw
11837  * @pf: pf the configuration is taken on
11838  * @new_cfg: new configuration
11839  * @tc_map: enabled TC bitmap
11840  *
11841  * Returns 0 on success, negative value on failure
11842  */
11843 static enum i40e_status_code
11844 i40e_dcb_hw_configure(struct i40e_pf *pf,
11845                       struct i40e_dcbx_config *new_cfg,
11846                       uint8_t tc_map)
11847 {
11848         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11849         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11850         struct i40e_vsi *main_vsi = pf->main_vsi;
11851         struct i40e_vsi_list *vsi_list;
11852         enum i40e_status_code ret;
11853         int i;
11854         uint32_t val;
11855
11856         /* Use the FW API if FW > v4.4*/
11857         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11858               (hw->aq.fw_maj_ver >= 5))) {
11859                 PMD_INIT_LOG(ERR,
11860                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11861                 return I40E_ERR_FIRMWARE_API_VERSION;
11862         }
11863
11864         /* Check if need reconfiguration */
11865         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11866                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11867                 return I40E_SUCCESS;
11868         }
11869
11870         /* Copy the new config to the current config */
11871         *old_cfg = *new_cfg;
11872         old_cfg->etsrec = old_cfg->etscfg;
11873         ret = i40e_set_dcb_config(hw);
11874         if (ret) {
11875                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11876                          i40e_stat_str(hw, ret),
11877                          i40e_aq_str(hw, hw->aq.asq_last_status));
11878                 return ret;
11879         }
11880         /* set receive Arbiter to RR mode and ETS scheme by default */
11881         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11882                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11883                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11884                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11885                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11886                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11887                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11888                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11889                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11890                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11891                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11892                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11893                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11894         }
11895         /* get local mib to check whether it is configured correctly */
11896         /* IEEE mode */
11897         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11898         /* Get Local DCB Config */
11899         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11900                                      &hw->local_dcbx_config);
11901
11902         /* if Veb is created, need to update TC of it at first */
11903         if (main_vsi->veb) {
11904                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11905                 if (ret)
11906                         PMD_INIT_LOG(WARNING,
11907                                  "Failed configuring TC for VEB seid=%d",
11908                                  main_vsi->veb->seid);
11909         }
11910         /* Update each VSI */
11911         i40e_vsi_config_tc(main_vsi, tc_map);
11912         if (main_vsi->veb) {
11913                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11914                         /* Beside main VSI and VMDQ VSIs, only enable default
11915                          * TC for other VSIs
11916                          */
11917                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11918                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11919                                                          tc_map);
11920                         else
11921                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11922                                                          I40E_DEFAULT_TCMAP);
11923                         if (ret)
11924                                 PMD_INIT_LOG(WARNING,
11925                                         "Failed configuring TC for VSI seid=%d",
11926                                         vsi_list->vsi->seid);
11927                         /* continue */
11928                 }
11929         }
11930         return I40E_SUCCESS;
11931 }
11932
11933 /*
11934  * i40e_dcb_init_configure - initial dcb config
11935  * @dev: device being configured
11936  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11937  *
11938  * Returns 0 on success, negative value on failure
11939  */
11940 int
11941 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11942 {
11943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11945         int i, ret = 0;
11946
11947         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11948                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11949                 return -ENOTSUP;
11950         }
11951
11952         /* DCB initialization:
11953          * Update DCB configuration from the Firmware and configure
11954          * LLDP MIB change event.
11955          */
11956         if (sw_dcb == TRUE) {
11957                 /* Stopping lldp is necessary for DPDK, but it will cause
11958                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11959                  * for successful initialization of DCB is that LLDP is
11960                  * enabled. So it is needed to start lldp before DCB init
11961                  * and stop it after initialization.
11962                  */
11963                 ret = i40e_aq_start_lldp(hw, true, NULL);
11964                 if (ret != I40E_SUCCESS)
11965                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11966
11967                 ret = i40e_init_dcb(hw, true);
11968                 /* If lldp agent is stopped, the return value from
11969                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11970                  * adminq status. Otherwise, it should return success.
11971                  */
11972                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11973                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11974                         memset(&hw->local_dcbx_config, 0,
11975                                 sizeof(struct i40e_dcbx_config));
11976                         /* set dcb default configuration */
11977                         hw->local_dcbx_config.etscfg.willing = 0;
11978                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11979                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11980                         hw->local_dcbx_config.etscfg.tsatable[0] =
11981                                                 I40E_IEEE_TSA_ETS;
11982                         /* all UPs mapping to TC0 */
11983                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11984                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11985                         hw->local_dcbx_config.etsrec =
11986                                 hw->local_dcbx_config.etscfg;
11987                         hw->local_dcbx_config.pfc.willing = 0;
11988                         hw->local_dcbx_config.pfc.pfccap =
11989                                                 I40E_MAX_TRAFFIC_CLASS;
11990                         /* FW needs one App to configure HW */
11991                         hw->local_dcbx_config.numapps = 1;
11992                         hw->local_dcbx_config.app[0].selector =
11993                                                 I40E_APP_SEL_ETHTYPE;
11994                         hw->local_dcbx_config.app[0].priority = 3;
11995                         hw->local_dcbx_config.app[0].protocolid =
11996                                                 I40E_APP_PROTOID_FCOE;
11997                         ret = i40e_set_dcb_config(hw);
11998                         if (ret) {
11999                                 PMD_INIT_LOG(ERR,
12000                                         "default dcb config fails. err = %d, aq_err = %d.",
12001                                         ret, hw->aq.asq_last_status);
12002                                 return -ENOSYS;
12003                         }
12004                 } else {
12005                         PMD_INIT_LOG(ERR,
12006                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
12007                                 ret, hw->aq.asq_last_status);
12008                         return -ENOTSUP;
12009                 }
12010
12011                 if (i40e_need_stop_lldp(dev)) {
12012                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
12013                         if (ret != I40E_SUCCESS)
12014                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
12015                 }
12016         } else {
12017                 ret = i40e_aq_start_lldp(hw, true, NULL);
12018                 if (ret != I40E_SUCCESS)
12019                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
12020
12021                 ret = i40e_init_dcb(hw, true);
12022                 if (!ret) {
12023                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
12024                                 PMD_INIT_LOG(ERR,
12025                                         "HW doesn't support DCBX offload.");
12026                                 return -ENOTSUP;
12027                         }
12028                 } else {
12029                         PMD_INIT_LOG(ERR,
12030                                 "DCBX configuration failed, err = %d, aq_err = %d.",
12031                                 ret, hw->aq.asq_last_status);
12032                         return -ENOTSUP;
12033                 }
12034         }
12035         return 0;
12036 }
12037
12038 /*
12039  * i40e_dcb_setup - setup dcb related config
12040  * @dev: device being configured
12041  *
12042  * Returns 0 on success, negative value on failure
12043  */
12044 static int
12045 i40e_dcb_setup(struct rte_eth_dev *dev)
12046 {
12047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12048         struct i40e_dcbx_config dcb_cfg;
12049         uint8_t tc_map = 0;
12050         int ret = 0;
12051
12052         if ((pf->flags & I40E_FLAG_DCB) == 0) {
12053                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12054                 return -ENOTSUP;
12055         }
12056
12057         if (pf->vf_num != 0)
12058                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12059
12060         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12061         if (ret) {
12062                 PMD_INIT_LOG(ERR, "invalid dcb config");
12063                 return -EINVAL;
12064         }
12065         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12066         if (ret) {
12067                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12068                 return -ENOSYS;
12069         }
12070
12071         return 0;
12072 }
12073
12074 static int
12075 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12076                       struct rte_eth_dcb_info *dcb_info)
12077 {
12078         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12080         struct i40e_vsi *vsi = pf->main_vsi;
12081         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12082         uint16_t bsf, tc_mapping;
12083         int i, j = 0;
12084
12085         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12086                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12087         else
12088                 dcb_info->nb_tcs = 1;
12089         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12090                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12091         for (i = 0; i < dcb_info->nb_tcs; i++)
12092                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12093
12094         /* get queue mapping if vmdq is disabled */
12095         if (!pf->nb_cfg_vmdq_vsi) {
12096                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12097                         if (!(vsi->enabled_tc & (1 << i)))
12098                                 continue;
12099                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12100                         dcb_info->tc_queue.tc_rxq[j][i].base =
12101                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12102                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12103                         dcb_info->tc_queue.tc_txq[j][i].base =
12104                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12105                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12106                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12107                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12108                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12109                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12110                 }
12111                 return 0;
12112         }
12113
12114         /* get queue mapping if vmdq is enabled */
12115         do {
12116                 vsi = pf->vmdq[j].vsi;
12117                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12118                         if (!(vsi->enabled_tc & (1 << i)))
12119                                 continue;
12120                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12121                         dcb_info->tc_queue.tc_rxq[j][i].base =
12122                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12123                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12124                         dcb_info->tc_queue.tc_txq[j][i].base =
12125                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12126                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12127                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12128                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12129                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12130                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12131                 }
12132                 j++;
12133         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12134         return 0;
12135 }
12136
12137 static int
12138 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12139 {
12140         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12141         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12142         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12143         uint16_t msix_intr;
12144
12145         msix_intr = intr_handle->intr_vec[queue_id];
12146         if (msix_intr == I40E_MISC_VEC_ID)
12147                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12148                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
12149                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12150                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12151         else
12152                 I40E_WRITE_REG(hw,
12153                                I40E_PFINT_DYN_CTLN(msix_intr -
12154                                                    I40E_RX_VEC_START),
12155                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
12156                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12157                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12158
12159         I40E_WRITE_FLUSH(hw);
12160         rte_intr_ack(&pci_dev->intr_handle);
12161
12162         return 0;
12163 }
12164
12165 static int
12166 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12167 {
12168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12169         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12171         uint16_t msix_intr;
12172
12173         msix_intr = intr_handle->intr_vec[queue_id];
12174         if (msix_intr == I40E_MISC_VEC_ID)
12175                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12176                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12177         else
12178                 I40E_WRITE_REG(hw,
12179                                I40E_PFINT_DYN_CTLN(msix_intr -
12180                                                    I40E_RX_VEC_START),
12181                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12182         I40E_WRITE_FLUSH(hw);
12183
12184         return 0;
12185 }
12186
12187 /**
12188  * This function is used to check if the register is valid.
12189  * Below is the valid registers list for X722 only:
12190  * 0x2b800--0x2bb00
12191  * 0x38700--0x38a00
12192  * 0x3d800--0x3db00
12193  * 0x208e00--0x209000
12194  * 0x20be00--0x20c000
12195  * 0x263c00--0x264000
12196  * 0x265c00--0x266000
12197  */
12198 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12199 {
12200         if ((type != I40E_MAC_X722) &&
12201             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12202              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12203              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12204              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12205              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12206              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12207              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12208                 return 0;
12209         else
12210                 return 1;
12211 }
12212
12213 static int i40e_get_regs(struct rte_eth_dev *dev,
12214                          struct rte_dev_reg_info *regs)
12215 {
12216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12217         uint32_t *ptr_data = regs->data;
12218         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12219         const struct i40e_reg_info *reg_info;
12220
12221         if (ptr_data == NULL) {
12222                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12223                 regs->width = sizeof(uint32_t);
12224                 return 0;
12225         }
12226
12227         /* The first few registers have to be read using AQ operations */
12228         reg_idx = 0;
12229         while (i40e_regs_adminq[reg_idx].name) {
12230                 reg_info = &i40e_regs_adminq[reg_idx++];
12231                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12232                         for (arr_idx2 = 0;
12233                                         arr_idx2 <= reg_info->count2;
12234                                         arr_idx2++) {
12235                                 reg_offset = arr_idx * reg_info->stride1 +
12236                                         arr_idx2 * reg_info->stride2;
12237                                 reg_offset += reg_info->base_addr;
12238                                 ptr_data[reg_offset >> 2] =
12239                                         i40e_read_rx_ctl(hw, reg_offset);
12240                         }
12241         }
12242
12243         /* The remaining registers can be read using primitives */
12244         reg_idx = 0;
12245         while (i40e_regs_others[reg_idx].name) {
12246                 reg_info = &i40e_regs_others[reg_idx++];
12247                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12248                         for (arr_idx2 = 0;
12249                                         arr_idx2 <= reg_info->count2;
12250                                         arr_idx2++) {
12251                                 reg_offset = arr_idx * reg_info->stride1 +
12252                                         arr_idx2 * reg_info->stride2;
12253                                 reg_offset += reg_info->base_addr;
12254                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12255                                         ptr_data[reg_offset >> 2] = 0;
12256                                 else
12257                                         ptr_data[reg_offset >> 2] =
12258                                                 I40E_READ_REG(hw, reg_offset);
12259                         }
12260         }
12261
12262         return 0;
12263 }
12264
12265 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12266 {
12267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12268
12269         /* Convert word count to byte count */
12270         return hw->nvm.sr_size << 1;
12271 }
12272
12273 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12274                            struct rte_dev_eeprom_info *eeprom)
12275 {
12276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12277         uint16_t *data = eeprom->data;
12278         uint16_t offset, length, cnt_words;
12279         int ret_code;
12280
12281         offset = eeprom->offset >> 1;
12282         length = eeprom->length >> 1;
12283         cnt_words = length;
12284
12285         if (offset > hw->nvm.sr_size ||
12286                 offset + length > hw->nvm.sr_size) {
12287                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12288                 return -EINVAL;
12289         }
12290
12291         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12292
12293         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12294         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12295                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12296                 return -EIO;
12297         }
12298
12299         return 0;
12300 }
12301
12302 static int i40e_get_module_info(struct rte_eth_dev *dev,
12303                                 struct rte_eth_dev_module_info *modinfo)
12304 {
12305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12306         uint32_t sff8472_comp = 0;
12307         uint32_t sff8472_swap = 0;
12308         uint32_t sff8636_rev = 0;
12309         i40e_status status;
12310         uint32_t type = 0;
12311
12312         /* Check if firmware supports reading module EEPROM. */
12313         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12314                 PMD_DRV_LOG(ERR,
12315                             "Module EEPROM memory read not supported. "
12316                             "Please update the NVM image.\n");
12317                 return -EINVAL;
12318         }
12319
12320         status = i40e_update_link_info(hw);
12321         if (status)
12322                 return -EIO;
12323
12324         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12325                 PMD_DRV_LOG(ERR,
12326                             "Cannot read module EEPROM memory. "
12327                             "No module connected.\n");
12328                 return -EINVAL;
12329         }
12330
12331         type = hw->phy.link_info.module_type[0];
12332
12333         switch (type) {
12334         case I40E_MODULE_TYPE_SFP:
12335                 status = i40e_aq_get_phy_register(hw,
12336                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12337                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12338                                 I40E_MODULE_SFF_8472_COMP,
12339                                 &sff8472_comp, NULL);
12340                 if (status)
12341                         return -EIO;
12342
12343                 status = i40e_aq_get_phy_register(hw,
12344                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12345                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12346                                 I40E_MODULE_SFF_8472_SWAP,
12347                                 &sff8472_swap, NULL);
12348                 if (status)
12349                         return -EIO;
12350
12351                 /* Check if the module requires address swap to access
12352                  * the other EEPROM memory page.
12353                  */
12354                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12355                         PMD_DRV_LOG(WARNING,
12356                                     "Module address swap to access "
12357                                     "page 0xA2 is not supported.\n");
12358                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12359                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12360                 } else if (sff8472_comp == 0x00) {
12361                         /* Module is not SFF-8472 compliant */
12362                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12363                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12364                 } else {
12365                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12366                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12367                 }
12368                 break;
12369         case I40E_MODULE_TYPE_QSFP_PLUS:
12370                 /* Read from memory page 0. */
12371                 status = i40e_aq_get_phy_register(hw,
12372                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12373                                 0, 1,
12374                                 I40E_MODULE_REVISION_ADDR,
12375                                 &sff8636_rev, NULL);
12376                 if (status)
12377                         return -EIO;
12378                 /* Determine revision compliance byte */
12379                 if (sff8636_rev > 0x02) {
12380                         /* Module is SFF-8636 compliant */
12381                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12382                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12383                 } else {
12384                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12385                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12386                 }
12387                 break;
12388         case I40E_MODULE_TYPE_QSFP28:
12389                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12390                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12391                 break;
12392         default:
12393                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12394                 return -EINVAL;
12395         }
12396         return 0;
12397 }
12398
12399 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12400                                   struct rte_dev_eeprom_info *info)
12401 {
12402         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12403         bool is_sfp = false;
12404         i40e_status status;
12405         uint8_t *data;
12406         uint32_t value = 0;
12407         uint32_t i;
12408
12409         if (!info || !info->length || !info->data)
12410                 return -EINVAL;
12411
12412         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12413                 is_sfp = true;
12414
12415         data = info->data;
12416         for (i = 0; i < info->length; i++) {
12417                 u32 offset = i + info->offset;
12418                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12419
12420                 /* Check if we need to access the other memory page */
12421                 if (is_sfp) {
12422                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12423                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12424                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12425                         }
12426                 } else {
12427                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12428                                 /* Compute memory page number and offset. */
12429                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12430                                 addr++;
12431                         }
12432                 }
12433                 status = i40e_aq_get_phy_register(hw,
12434                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12435                                 addr, 1, offset, &value, NULL);
12436                 if (status)
12437                         return -EIO;
12438                 data[i] = (uint8_t)value;
12439         }
12440         return 0;
12441 }
12442
12443 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12444                                      struct rte_ether_addr *mac_addr)
12445 {
12446         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12447         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12448         struct i40e_vsi *vsi = pf->main_vsi;
12449         struct i40e_mac_filter_info mac_filter;
12450         struct i40e_mac_filter *f;
12451         int ret;
12452
12453         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12454                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12455                 return -EINVAL;
12456         }
12457
12458         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12459                 if (rte_is_same_ether_addr(&pf->dev_addr,
12460                                                 &f->mac_info.mac_addr))
12461                         break;
12462         }
12463
12464         if (f == NULL) {
12465                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12466                 return -EIO;
12467         }
12468
12469         mac_filter = f->mac_info;
12470         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12471         if (ret != I40E_SUCCESS) {
12472                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12473                 return -EIO;
12474         }
12475         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12476         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12477         if (ret != I40E_SUCCESS) {
12478                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12479                 return -EIO;
12480         }
12481         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12482
12483         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12484                                         mac_addr->addr_bytes, NULL);
12485         if (ret != I40E_SUCCESS) {
12486                 PMD_DRV_LOG(ERR, "Failed to change mac");
12487                 return -EIO;
12488         }
12489
12490         return 0;
12491 }
12492
12493 static int
12494 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12495 {
12496         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12497         struct rte_eth_dev_data *dev_data = pf->dev_data;
12498         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12499         int ret = 0;
12500
12501         /* check if mtu is within the allowed range */
12502         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12503                 return -EINVAL;
12504
12505         /* mtu setting is forbidden if port is start */
12506         if (dev_data->dev_started) {
12507                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12508                             dev_data->port_id);
12509                 return -EBUSY;
12510         }
12511
12512         if (frame_size > RTE_ETHER_MAX_LEN)
12513                 dev_data->dev_conf.rxmode.offloads |=
12514                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12515         else
12516                 dev_data->dev_conf.rxmode.offloads &=
12517                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12518
12519         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12520
12521         return ret;
12522 }
12523
12524 /* Restore ethertype filter */
12525 static void
12526 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12527 {
12528         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12529         struct i40e_ethertype_filter_list
12530                 *ethertype_list = &pf->ethertype.ethertype_list;
12531         struct i40e_ethertype_filter *f;
12532         struct i40e_control_filter_stats stats;
12533         uint16_t flags;
12534
12535         TAILQ_FOREACH(f, ethertype_list, rules) {
12536                 flags = 0;
12537                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12538                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12539                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12540                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12541                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12542
12543                 memset(&stats, 0, sizeof(stats));
12544                 i40e_aq_add_rem_control_packet_filter(hw,
12545                                             f->input.mac_addr.addr_bytes,
12546                                             f->input.ether_type,
12547                                             flags, pf->main_vsi->seid,
12548                                             f->queue, 1, &stats, NULL);
12549         }
12550         PMD_DRV_LOG(INFO, "Ethertype filter:"
12551                     " mac_etype_used = %u, etype_used = %u,"
12552                     " mac_etype_free = %u, etype_free = %u",
12553                     stats.mac_etype_used, stats.etype_used,
12554                     stats.mac_etype_free, stats.etype_free);
12555 }
12556
12557 /* Restore tunnel filter */
12558 static void
12559 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12560 {
12561         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12562         struct i40e_vsi *vsi;
12563         struct i40e_pf_vf *vf;
12564         struct i40e_tunnel_filter_list
12565                 *tunnel_list = &pf->tunnel.tunnel_list;
12566         struct i40e_tunnel_filter *f;
12567         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12568         bool big_buffer = 0;
12569
12570         TAILQ_FOREACH(f, tunnel_list, rules) {
12571                 if (!f->is_to_vf)
12572                         vsi = pf->main_vsi;
12573                 else {
12574                         vf = &pf->vfs[f->vf_id];
12575                         vsi = vf->vsi;
12576                 }
12577                 memset(&cld_filter, 0, sizeof(cld_filter));
12578                 rte_ether_addr_copy((struct rte_ether_addr *)
12579                                 &f->input.outer_mac,
12580                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12581                 rte_ether_addr_copy((struct rte_ether_addr *)
12582                                 &f->input.inner_mac,
12583                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12584                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12585                 cld_filter.element.flags = f->input.flags;
12586                 cld_filter.element.tenant_id = f->input.tenant_id;
12587                 cld_filter.element.queue_number = f->queue;
12588                 rte_memcpy(cld_filter.general_fields,
12589                            f->input.general_fields,
12590                            sizeof(f->input.general_fields));
12591
12592                 if (((f->input.flags &
12593                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12594                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12595                     ((f->input.flags &
12596                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12597                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12598                     ((f->input.flags &
12599                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12600                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12601                         big_buffer = 1;
12602
12603                 if (big_buffer)
12604                         i40e_aq_add_cloud_filters_bb(hw,
12605                                         vsi->seid, &cld_filter, 1);
12606                 else
12607                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12608                                                   &cld_filter.element, 1);
12609         }
12610 }
12611
12612 /* Restore RSS filter */
12613 static inline void
12614 i40e_rss_filter_restore(struct i40e_pf *pf)
12615 {
12616         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12617         struct i40e_rss_filter *filter;
12618
12619         TAILQ_FOREACH(filter, list, next) {
12620                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12621         }
12622 }
12623
12624 static void
12625 i40e_filter_restore(struct i40e_pf *pf)
12626 {
12627         i40e_ethertype_filter_restore(pf);
12628         i40e_tunnel_filter_restore(pf);
12629         i40e_fdir_filter_restore(pf);
12630         i40e_rss_filter_restore(pf);
12631 }
12632
12633 bool
12634 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12635 {
12636         if (strcmp(dev->device->driver->name, drv->driver.name))
12637                 return false;
12638
12639         return true;
12640 }
12641
12642 bool
12643 is_i40e_supported(struct rte_eth_dev *dev)
12644 {
12645         return is_device_supported(dev, &rte_i40e_pmd);
12646 }
12647
12648 struct i40e_customized_pctype*
12649 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12650 {
12651         int i;
12652
12653         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12654                 if (pf->customized_pctype[i].index == index)
12655                         return &pf->customized_pctype[i];
12656         }
12657         return NULL;
12658 }
12659
12660 static int
12661 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12662                               uint32_t pkg_size, uint32_t proto_num,
12663                               struct rte_pmd_i40e_proto_info *proto,
12664                               enum rte_pmd_i40e_package_op op)
12665 {
12666         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12667         uint32_t pctype_num;
12668         struct rte_pmd_i40e_ptype_info *pctype;
12669         uint32_t buff_size;
12670         struct i40e_customized_pctype *new_pctype = NULL;
12671         uint8_t proto_id;
12672         uint8_t pctype_value;
12673         char name[64];
12674         uint32_t i, j, n;
12675         int ret;
12676
12677         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12678             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12679                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12680                 return -1;
12681         }
12682
12683         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12684                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12685                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12686         if (ret) {
12687                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12688                 return -1;
12689         }
12690         if (!pctype_num) {
12691                 PMD_DRV_LOG(INFO, "No new pctype added");
12692                 return -1;
12693         }
12694
12695         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12696         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12697         if (!pctype) {
12698                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12699                 return -1;
12700         }
12701         /* get information about new pctype list */
12702         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12703                                         (uint8_t *)pctype, buff_size,
12704                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12705         if (ret) {
12706                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12707                 rte_free(pctype);
12708                 return -1;
12709         }
12710
12711         /* Update customized pctype. */
12712         for (i = 0; i < pctype_num; i++) {
12713                 pctype_value = pctype[i].ptype_id;
12714                 memset(name, 0, sizeof(name));
12715                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12716                         proto_id = pctype[i].protocols[j];
12717                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12718                                 continue;
12719                         for (n = 0; n < proto_num; n++) {
12720                                 if (proto[n].proto_id != proto_id)
12721                                         continue;
12722                                 strlcat(name, proto[n].name, sizeof(name));
12723                                 strlcat(name, "_", sizeof(name));
12724                                 break;
12725                         }
12726                 }
12727                 name[strlen(name) - 1] = '\0';
12728                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12729                 if (!strcmp(name, "GTPC"))
12730                         new_pctype =
12731                                 i40e_find_customized_pctype(pf,
12732                                                       I40E_CUSTOMIZED_GTPC);
12733                 else if (!strcmp(name, "GTPU_IPV4"))
12734                         new_pctype =
12735                                 i40e_find_customized_pctype(pf,
12736                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12737                 else if (!strcmp(name, "GTPU_IPV6"))
12738                         new_pctype =
12739                                 i40e_find_customized_pctype(pf,
12740                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12741                 else if (!strcmp(name, "GTPU"))
12742                         new_pctype =
12743                                 i40e_find_customized_pctype(pf,
12744                                                       I40E_CUSTOMIZED_GTPU);
12745                 else if (!strcmp(name, "IPV4_L2TPV3"))
12746                         new_pctype =
12747                                 i40e_find_customized_pctype(pf,
12748                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12749                 else if (!strcmp(name, "IPV6_L2TPV3"))
12750                         new_pctype =
12751                                 i40e_find_customized_pctype(pf,
12752                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12753                 else if (!strcmp(name, "IPV4_ESP"))
12754                         new_pctype =
12755                                 i40e_find_customized_pctype(pf,
12756                                                 I40E_CUSTOMIZED_ESP_IPV4);
12757                 else if (!strcmp(name, "IPV6_ESP"))
12758                         new_pctype =
12759                                 i40e_find_customized_pctype(pf,
12760                                                 I40E_CUSTOMIZED_ESP_IPV6);
12761                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12762                         new_pctype =
12763                                 i40e_find_customized_pctype(pf,
12764                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12765                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12766                         new_pctype =
12767                                 i40e_find_customized_pctype(pf,
12768                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12769                 else if (!strcmp(name, "IPV4_AH"))
12770                         new_pctype =
12771                                 i40e_find_customized_pctype(pf,
12772                                                 I40E_CUSTOMIZED_AH_IPV4);
12773                 else if (!strcmp(name, "IPV6_AH"))
12774                         new_pctype =
12775                                 i40e_find_customized_pctype(pf,
12776                                                 I40E_CUSTOMIZED_AH_IPV6);
12777                 if (new_pctype) {
12778                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12779                                 new_pctype->pctype = pctype_value;
12780                                 new_pctype->valid = true;
12781                         } else {
12782                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12783                                 new_pctype->valid = false;
12784                         }
12785                 }
12786         }
12787
12788         rte_free(pctype);
12789         return 0;
12790 }
12791
12792 static int
12793 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12794                              uint32_t pkg_size, uint32_t proto_num,
12795                              struct rte_pmd_i40e_proto_info *proto,
12796                              enum rte_pmd_i40e_package_op op)
12797 {
12798         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12799         uint16_t port_id = dev->data->port_id;
12800         uint32_t ptype_num;
12801         struct rte_pmd_i40e_ptype_info *ptype;
12802         uint32_t buff_size;
12803         uint8_t proto_id;
12804         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12805         uint32_t i, j, n;
12806         bool in_tunnel;
12807         int ret;
12808
12809         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12810             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12811                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12812                 return -1;
12813         }
12814
12815         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12816                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12817                 return 0;
12818         }
12819
12820         /* get information about new ptype num */
12821         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12822                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12823                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12824         if (ret) {
12825                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12826                 return ret;
12827         }
12828         if (!ptype_num) {
12829                 PMD_DRV_LOG(INFO, "No new ptype added");
12830                 return -1;
12831         }
12832
12833         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12834         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12835         if (!ptype) {
12836                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12837                 return -1;
12838         }
12839
12840         /* get information about new ptype list */
12841         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12842                                         (uint8_t *)ptype, buff_size,
12843                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12844         if (ret) {
12845                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12846                 rte_free(ptype);
12847                 return ret;
12848         }
12849
12850         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12851         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12852         if (!ptype_mapping) {
12853                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12854                 rte_free(ptype);
12855                 return -1;
12856         }
12857
12858         /* Update ptype mapping table. */
12859         for (i = 0; i < ptype_num; i++) {
12860                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12861                 ptype_mapping[i].sw_ptype = 0;
12862                 in_tunnel = false;
12863                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12864                         proto_id = ptype[i].protocols[j];
12865                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12866                                 continue;
12867                         for (n = 0; n < proto_num; n++) {
12868                                 if (proto[n].proto_id != proto_id)
12869                                         continue;
12870                                 memset(name, 0, sizeof(name));
12871                                 strcpy(name, proto[n].name);
12872                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12873                                 if (!strncasecmp(name, "PPPOE", 5))
12874                                         ptype_mapping[i].sw_ptype |=
12875                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12876                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12877                                          !in_tunnel) {
12878                                         ptype_mapping[i].sw_ptype |=
12879                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12880                                         ptype_mapping[i].sw_ptype |=
12881                                                 RTE_PTYPE_L4_FRAG;
12882                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12883                                            in_tunnel) {
12884                                         ptype_mapping[i].sw_ptype |=
12885                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12886                                         ptype_mapping[i].sw_ptype |=
12887                                                 RTE_PTYPE_INNER_L4_FRAG;
12888                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12889                                         ptype_mapping[i].sw_ptype |=
12890                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12891                                         in_tunnel = true;
12892                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12893                                            !in_tunnel)
12894                                         ptype_mapping[i].sw_ptype |=
12895                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12896                                 else if (!strncasecmp(name, "IPV4", 4) &&
12897                                          in_tunnel)
12898                                         ptype_mapping[i].sw_ptype |=
12899                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12900                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12901                                          !in_tunnel) {
12902                                         ptype_mapping[i].sw_ptype |=
12903                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12904                                         ptype_mapping[i].sw_ptype |=
12905                                                 RTE_PTYPE_L4_FRAG;
12906                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12907                                            in_tunnel) {
12908                                         ptype_mapping[i].sw_ptype |=
12909                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12910                                         ptype_mapping[i].sw_ptype |=
12911                                                 RTE_PTYPE_INNER_L4_FRAG;
12912                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12913                                         ptype_mapping[i].sw_ptype |=
12914                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12915                                         in_tunnel = true;
12916                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12917                                            !in_tunnel)
12918                                         ptype_mapping[i].sw_ptype |=
12919                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12920                                 else if (!strncasecmp(name, "IPV6", 4) &&
12921                                          in_tunnel)
12922                                         ptype_mapping[i].sw_ptype |=
12923                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12924                                 else if (!strncasecmp(name, "UDP", 3) &&
12925                                          !in_tunnel)
12926                                         ptype_mapping[i].sw_ptype |=
12927                                                 RTE_PTYPE_L4_UDP;
12928                                 else if (!strncasecmp(name, "UDP", 3) &&
12929                                          in_tunnel)
12930                                         ptype_mapping[i].sw_ptype |=
12931                                                 RTE_PTYPE_INNER_L4_UDP;
12932                                 else if (!strncasecmp(name, "TCP", 3) &&
12933                                          !in_tunnel)
12934                                         ptype_mapping[i].sw_ptype |=
12935                                                 RTE_PTYPE_L4_TCP;
12936                                 else if (!strncasecmp(name, "TCP", 3) &&
12937                                          in_tunnel)
12938                                         ptype_mapping[i].sw_ptype |=
12939                                                 RTE_PTYPE_INNER_L4_TCP;
12940                                 else if (!strncasecmp(name, "SCTP", 4) &&
12941                                          !in_tunnel)
12942                                         ptype_mapping[i].sw_ptype |=
12943                                                 RTE_PTYPE_L4_SCTP;
12944                                 else if (!strncasecmp(name, "SCTP", 4) &&
12945                                          in_tunnel)
12946                                         ptype_mapping[i].sw_ptype |=
12947                                                 RTE_PTYPE_INNER_L4_SCTP;
12948                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12949                                           !strncasecmp(name, "ICMPV6", 6)) &&
12950                                          !in_tunnel)
12951                                         ptype_mapping[i].sw_ptype |=
12952                                                 RTE_PTYPE_L4_ICMP;
12953                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12954                                           !strncasecmp(name, "ICMPV6", 6)) &&
12955                                          in_tunnel)
12956                                         ptype_mapping[i].sw_ptype |=
12957                                                 RTE_PTYPE_INNER_L4_ICMP;
12958                                 else if (!strncasecmp(name, "GTPC", 4)) {
12959                                         ptype_mapping[i].sw_ptype |=
12960                                                 RTE_PTYPE_TUNNEL_GTPC;
12961                                         in_tunnel = true;
12962                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12963                                         ptype_mapping[i].sw_ptype |=
12964                                                 RTE_PTYPE_TUNNEL_GTPU;
12965                                         in_tunnel = true;
12966                                 } else if (!strncasecmp(name, "ESP", 3)) {
12967                                         ptype_mapping[i].sw_ptype |=
12968                                                 RTE_PTYPE_TUNNEL_ESP;
12969                                         in_tunnel = true;
12970                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12971                                         ptype_mapping[i].sw_ptype |=
12972                                                 RTE_PTYPE_TUNNEL_GRENAT;
12973                                         in_tunnel = true;
12974                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12975                                            !strncasecmp(name, "L2TPV2", 6) ||
12976                                            !strncasecmp(name, "L2TPV3", 6)) {
12977                                         ptype_mapping[i].sw_ptype |=
12978                                                 RTE_PTYPE_TUNNEL_L2TP;
12979                                         in_tunnel = true;
12980                                 }
12981
12982                                 break;
12983                         }
12984                 }
12985         }
12986
12987         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12988                                                 ptype_num, 0);
12989         if (ret)
12990                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12991
12992         rte_free(ptype_mapping);
12993         rte_free(ptype);
12994         return ret;
12995 }
12996
12997 void
12998 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12999                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
13000 {
13001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
13002         uint32_t proto_num;
13003         struct rte_pmd_i40e_proto_info *proto;
13004         uint32_t buff_size;
13005         uint32_t i;
13006         int ret;
13007
13008         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
13009             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
13010                 PMD_DRV_LOG(ERR, "Unsupported operation.");
13011                 return;
13012         }
13013
13014         /* get information about protocol number */
13015         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13016                                        (uint8_t *)&proto_num, sizeof(proto_num),
13017                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
13018         if (ret) {
13019                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
13020                 return;
13021         }
13022         if (!proto_num) {
13023                 PMD_DRV_LOG(INFO, "No new protocol added");
13024                 return;
13025         }
13026
13027         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
13028         proto = rte_zmalloc("new_proto", buff_size, 0);
13029         if (!proto) {
13030                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
13031                 return;
13032         }
13033
13034         /* get information about protocol list */
13035         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
13036                                         (uint8_t *)proto, buff_size,
13037                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
13038         if (ret) {
13039                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
13040                 rte_free(proto);
13041                 return;
13042         }
13043
13044         /* Check if GTP is supported. */
13045         for (i = 0; i < proto_num; i++) {
13046                 if (!strncmp(proto[i].name, "GTP", 3)) {
13047                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13048                                 pf->gtp_support = true;
13049                         else
13050                                 pf->gtp_support = false;
13051                         break;
13052                 }
13053         }
13054
13055         /* Check if ESP is supported. */
13056         for (i = 0; i < proto_num; i++) {
13057                 if (!strncmp(proto[i].name, "ESP", 3)) {
13058                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13059                                 pf->esp_support = true;
13060                         else
13061                                 pf->esp_support = false;
13062                         break;
13063                 }
13064         }
13065
13066         /* Update customized pctype info */
13067         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13068                                             proto_num, proto, op);
13069         if (ret)
13070                 PMD_DRV_LOG(INFO, "No pctype is updated.");
13071
13072         /* Update customized ptype info */
13073         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13074                                            proto_num, proto, op);
13075         if (ret)
13076                 PMD_DRV_LOG(INFO, "No ptype is updated.");
13077
13078         rte_free(proto);
13079 }
13080
13081 /* Create a QinQ cloud filter
13082  *
13083  * The Fortville NIC has limited resources for tunnel filters,
13084  * so we can only reuse existing filters.
13085  *
13086  * In step 1 we define which Field Vector fields can be used for
13087  * filter types.
13088  * As we do not have the inner tag defined as a field,
13089  * we have to define it first, by reusing one of L1 entries.
13090  *
13091  * In step 2 we are replacing one of existing filter types with
13092  * a new one for QinQ.
13093  * As we reusing L1 and replacing L2, some of the default filter
13094  * types will disappear,which depends on L1 and L2 entries we reuse.
13095  *
13096  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13097  *
13098  * 1.   Create L1 filter of outer vlan (12b) which will be in use
13099  *              later when we define the cloud filter.
13100  *      a.      Valid_flags.replace_cloud = 0
13101  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
13102  *      c.      New_filter = 0x10
13103  *      d.      TR bit = 0xff (optional, not used here)
13104  *      e.      Buffer – 2 entries:
13105  *              i.      Byte 0 = 8 (outer vlan FV index).
13106  *                      Byte 1 = 0 (rsv)
13107  *                      Byte 2-3 = 0x0fff
13108  *              ii.     Byte 0 = 37 (inner vlan FV index).
13109  *                      Byte 1 =0 (rsv)
13110  *                      Byte 2-3 = 0x0fff
13111  *
13112  * Step 2:
13113  * 2.   Create cloud filter using two L1 filters entries: stag and
13114  *              new filter(outer vlan+ inner vlan)
13115  *      a.      Valid_flags.replace_cloud = 1
13116  *      b.      Old_filter = 1 (instead of outer IP)
13117  *      c.      New_filter = 0x10
13118  *      d.      Buffer – 2 entries:
13119  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
13120  *                      Byte 1-3 = 0 (rsv)
13121  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13122  *                      Byte 9-11 = 0 (rsv)
13123  */
13124 static int
13125 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13126 {
13127         int ret = -ENOTSUP;
13128         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
13129         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
13130         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13131         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13132
13133         if (pf->support_multi_driver) {
13134                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13135                 return ret;
13136         }
13137
13138         /* Init */
13139         memset(&filter_replace, 0,
13140                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13141         memset(&filter_replace_buf, 0,
13142                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13143
13144         /* create L1 filter */
13145         filter_replace.old_filter_type =
13146                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13147         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13148         filter_replace.tr_bit = 0;
13149
13150         /* Prepare the buffer, 2 entries */
13151         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13152         filter_replace_buf.data[0] |=
13153                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13154         /* Field Vector 12b mask */
13155         filter_replace_buf.data[2] = 0xff;
13156         filter_replace_buf.data[3] = 0x0f;
13157         filter_replace_buf.data[4] =
13158                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13159         filter_replace_buf.data[4] |=
13160                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13161         /* Field Vector 12b mask */
13162         filter_replace_buf.data[6] = 0xff;
13163         filter_replace_buf.data[7] = 0x0f;
13164         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13165                         &filter_replace_buf);
13166         if (ret != I40E_SUCCESS)
13167                 return ret;
13168
13169         if (filter_replace.old_filter_type !=
13170             filter_replace.new_filter_type)
13171                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13172                             " original: 0x%x, new: 0x%x",
13173                             dev->device->name,
13174                             filter_replace.old_filter_type,
13175                             filter_replace.new_filter_type);
13176
13177         /* Apply the second L2 cloud filter */
13178         memset(&filter_replace, 0,
13179                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13180         memset(&filter_replace_buf, 0,
13181                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13182
13183         /* create L2 filter, input for L2 filter will be L1 filter  */
13184         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13185         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13186         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13187
13188         /* Prepare the buffer, 2 entries */
13189         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13190         filter_replace_buf.data[0] |=
13191                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13192         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13193         filter_replace_buf.data[4] |=
13194                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13195         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13196                         &filter_replace_buf);
13197         if (!ret && (filter_replace.old_filter_type !=
13198                      filter_replace.new_filter_type))
13199                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13200                             " original: 0x%x, new: 0x%x",
13201                             dev->device->name,
13202                             filter_replace.old_filter_type,
13203                             filter_replace.new_filter_type);
13204
13205         return ret;
13206 }
13207
13208 int
13209 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13210                    const struct rte_flow_action_rss *in)
13211 {
13212         if (in->key_len > RTE_DIM(out->key) ||
13213             in->queue_num > RTE_DIM(out->queue))
13214                 return -EINVAL;
13215         if (!in->key && in->key_len)
13216                 return -EINVAL;
13217         out->conf = (struct rte_flow_action_rss){
13218                 .func = in->func,
13219                 .level = in->level,
13220                 .types = in->types,
13221                 .key_len = in->key_len,
13222                 .queue_num = in->queue_num,
13223                 .queue = memcpy(out->queue, in->queue,
13224                                 sizeof(*in->queue) * in->queue_num),
13225         };
13226         if (in->key)
13227                 out->conf.key = memcpy(out->key, in->key, in->key_len);
13228         return 0;
13229 }
13230
13231 /* Write HENA register to enable hash */
13232 static int
13233 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13234 {
13235         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13236         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13237         uint64_t hena;
13238         int ret;
13239
13240         ret = i40e_set_rss_key(pf->main_vsi, key,
13241                                rss_conf->conf.key_len);
13242         if (ret)
13243                 return ret;
13244
13245         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13246         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13247         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13248         I40E_WRITE_FLUSH(hw);
13249
13250         return 0;
13251 }
13252
13253 /* Configure hash input set */
13254 static int
13255 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13256 {
13257         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13258         struct rte_eth_input_set_conf conf;
13259         uint64_t mask0;
13260         int ret = 0;
13261         uint32_t j;
13262         int i;
13263         static const struct {
13264                 uint64_t type;
13265                 enum rte_eth_input_set_field field;
13266         } inset_match_table[] = {
13267                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13268                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13269                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13270                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13271                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13272                         RTE_ETH_INPUT_SET_UNKNOWN},
13273                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13274                         RTE_ETH_INPUT_SET_UNKNOWN},
13275
13276                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13277                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13278                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13279                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13280                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13281                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13282                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13283                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13284
13285                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13286                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13287                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13288                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13289                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13290                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13291                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13292                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13293
13294                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13295                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13296                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13297                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13298                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13299                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13300                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13301                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13302
13303                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13304                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13305                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13306                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13307                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13308                         RTE_ETH_INPUT_SET_UNKNOWN},
13309                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13310                         RTE_ETH_INPUT_SET_UNKNOWN},
13311
13312                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13313                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13314                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13315                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13316                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13317                         RTE_ETH_INPUT_SET_UNKNOWN},
13318                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13319                         RTE_ETH_INPUT_SET_UNKNOWN},
13320
13321                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13322                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13323                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13324                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13325                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13326                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13327                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13328                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13329
13330                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13331                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13332                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13333                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13334                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13335                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13336                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13337                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13338
13339                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13340                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13341                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13342                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13343                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13344                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13345                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13346                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13347
13348                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13349                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13350                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13351                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13352                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13353                         RTE_ETH_INPUT_SET_UNKNOWN},
13354                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13355                         RTE_ETH_INPUT_SET_UNKNOWN},
13356         };
13357
13358         mask0 = types & pf->adapter->flow_types_mask;
13359         conf.op = RTE_ETH_INPUT_SET_SELECT;
13360         conf.inset_size = 0;
13361         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13362                 if (mask0 & (1ULL << i)) {
13363                         conf.flow_type = i;
13364                         break;
13365                 }
13366         }
13367
13368         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13369                 if ((types & inset_match_table[j].type) ==
13370                     inset_match_table[j].type) {
13371                         if (inset_match_table[j].field ==
13372                             RTE_ETH_INPUT_SET_UNKNOWN)
13373                                 return -EINVAL;
13374
13375                         conf.field[conf.inset_size] =
13376                                 inset_match_table[j].field;
13377                         conf.inset_size++;
13378                 }
13379         }
13380
13381         if (conf.inset_size) {
13382                 ret = i40e_hash_filter_inset_select(hw, &conf);
13383                 if (ret)
13384                         return ret;
13385         }
13386
13387         return ret;
13388 }
13389
13390 /* Look up the conflicted rule then mark it as invalid */
13391 static void
13392 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13393                 struct i40e_rte_flow_rss_conf *conf)
13394 {
13395         struct i40e_rss_filter *rss_item;
13396         uint64_t rss_inset;
13397
13398         /* Clear input set bits before comparing the pctype */
13399         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13400                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13401
13402         /* Look up the conflicted rule then mark it as invalid */
13403         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13404                 if (!rss_item->rss_filter_info.valid)
13405                         continue;
13406
13407                 if (conf->conf.queue_num &&
13408                     rss_item->rss_filter_info.conf.queue_num)
13409                         rss_item->rss_filter_info.valid = false;
13410
13411                 if (conf->conf.types &&
13412                     (rss_item->rss_filter_info.conf.types &
13413                     rss_inset) ==
13414                     (conf->conf.types & rss_inset))
13415                         rss_item->rss_filter_info.valid = false;
13416
13417                 if (conf->conf.func ==
13418                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13419                     rss_item->rss_filter_info.conf.func ==
13420                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13421                         rss_item->rss_filter_info.valid = false;
13422         }
13423 }
13424
13425 /* Configure RSS hash function */
13426 static int
13427 i40e_rss_config_hash_function(struct i40e_pf *pf,
13428                 struct i40e_rte_flow_rss_conf *conf)
13429 {
13430         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13431         uint32_t reg, i;
13432         uint64_t mask0;
13433         uint16_t j;
13434
13435         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13436                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13437                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13438                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13439                         I40E_WRITE_FLUSH(hw);
13440                         i40e_rss_mark_invalid_rule(pf, conf);
13441
13442                         return 0;
13443                 }
13444                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13445
13446                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13447                 I40E_WRITE_FLUSH(hw);
13448                 i40e_rss_mark_invalid_rule(pf, conf);
13449         } else if (conf->conf.func ==
13450                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13451                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13452
13453                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13454                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13455                         if (mask0 & (1UL << i))
13456                                 break;
13457                 }
13458
13459                 if (i == UINT64_BIT)
13460                         return -EINVAL;
13461
13462                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13463                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13464                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13465                                 i40e_write_global_rx_ctl(hw,
13466                                         I40E_GLQF_HSYM(j),
13467                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13468                 }
13469         }
13470
13471         return 0;
13472 }
13473
13474 /* Enable RSS according to the configuration */
13475 static int
13476 i40e_rss_enable_hash(struct i40e_pf *pf,
13477                 struct i40e_rte_flow_rss_conf *conf)
13478 {
13479         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13480         struct i40e_rte_flow_rss_conf rss_conf;
13481
13482         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13483                 return -ENOTSUP;
13484
13485         memset(&rss_conf, 0, sizeof(rss_conf));
13486         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13487
13488         /* Configure hash input set */
13489         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13490                 return -EINVAL;
13491
13492         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13493             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13494                 /* Random default keys */
13495                 static uint32_t rss_key_default[] = {0x6b793944,
13496                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13497                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13498                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13499
13500                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13501                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13502                                 sizeof(uint32_t);
13503                 PMD_DRV_LOG(INFO,
13504                         "No valid RSS key config for i40e, using default\n");
13505         }
13506
13507         rss_conf.conf.types |= rss_info->conf.types;
13508         i40e_rss_hash_set(pf, &rss_conf);
13509
13510         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13511                 i40e_rss_config_hash_function(pf, conf);
13512
13513         i40e_rss_mark_invalid_rule(pf, conf);
13514
13515         return 0;
13516 }
13517
13518 /* Configure RSS queue region */
13519 static int
13520 i40e_rss_config_queue_region(struct i40e_pf *pf,
13521                 struct i40e_rte_flow_rss_conf *conf)
13522 {
13523         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13524         uint32_t lut = 0;
13525         uint16_t j, num;
13526         uint32_t i;
13527
13528         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13529          * It's necessary to calculate the actual PF queues that are configured.
13530          */
13531         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13532                 num = i40e_pf_calc_configured_queues_num(pf);
13533         else
13534                 num = pf->dev_data->nb_rx_queues;
13535
13536         num = RTE_MIN(num, conf->conf.queue_num);
13537         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13538                         num);
13539
13540         if (num == 0) {
13541                 PMD_DRV_LOG(ERR,
13542                         "No PF queues are configured to enable RSS for port %u",
13543                         pf->dev_data->port_id);
13544                 return -ENOTSUP;
13545         }
13546
13547         /* Fill in redirection table */
13548         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13549                 if (j == num)
13550                         j = 0;
13551                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13552                         hw->func_caps.rss_table_entry_width) - 1));
13553                 if ((i & 3) == 3)
13554                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13555         }
13556
13557         i40e_rss_mark_invalid_rule(pf, conf);
13558
13559         return 0;
13560 }
13561
13562 /* Configure RSS hash function to default */
13563 static int
13564 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13565                 struct i40e_rte_flow_rss_conf *conf)
13566 {
13567         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13568         uint32_t i, reg;
13569         uint64_t mask0;
13570         uint16_t j;
13571
13572         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13573                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13574                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13575                         PMD_DRV_LOG(DEBUG,
13576                                 "Hash function already set to Toeplitz");
13577                         I40E_WRITE_FLUSH(hw);
13578
13579                         return 0;
13580                 }
13581                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13582
13583                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13584                 I40E_WRITE_FLUSH(hw);
13585         } else if (conf->conf.func ==
13586                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13587                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13588
13589                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13590                         if (mask0 & (1UL << i))
13591                                 break;
13592                 }
13593
13594                 if (i == UINT64_BIT)
13595                         return -EINVAL;
13596
13597                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13598                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13599                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13600                                 i40e_write_global_rx_ctl(hw,
13601                                         I40E_GLQF_HSYM(j),
13602                                         0);
13603                 }
13604         }
13605
13606         return 0;
13607 }
13608
13609 /* Disable RSS hash and configure default input set */
13610 static int
13611 i40e_rss_disable_hash(struct i40e_pf *pf,
13612                 struct i40e_rte_flow_rss_conf *conf)
13613 {
13614         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13615         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13616         struct i40e_rte_flow_rss_conf rss_conf;
13617         uint32_t i;
13618
13619         memset(&rss_conf, 0, sizeof(rss_conf));
13620         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13621
13622         /* Disable RSS hash */
13623         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13624         i40e_rss_hash_set(pf, &rss_conf);
13625
13626         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13627                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13628                     !(conf->conf.types & (1ULL << i)))
13629                         continue;
13630
13631                 /* Configure default input set */
13632                 struct rte_eth_input_set_conf input_conf = {
13633                         .op = RTE_ETH_INPUT_SET_SELECT,
13634                         .flow_type = i,
13635                         .inset_size = 1,
13636                 };
13637                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13638                 i40e_hash_filter_inset_select(hw, &input_conf);
13639         }
13640
13641         rss_info->conf.types = rss_conf.conf.types;
13642
13643         i40e_rss_clear_hash_function(pf, conf);
13644
13645         return 0;
13646 }
13647
13648 /* Configure RSS queue region to default */
13649 static int
13650 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13651 {
13652         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13653         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13654         uint16_t queue[I40E_MAX_Q_PER_TC];
13655         uint32_t num_rxq, i;
13656         uint32_t lut = 0;
13657         uint16_t j, num;
13658
13659         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13660
13661         for (j = 0; j < num_rxq; j++)
13662                 queue[j] = j;
13663
13664         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13665          * It's necessary to calculate the actual PF queues that are configured.
13666          */
13667         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13668                 num = i40e_pf_calc_configured_queues_num(pf);
13669         else
13670                 num = pf->dev_data->nb_rx_queues;
13671
13672         num = RTE_MIN(num, num_rxq);
13673         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13674                         num);
13675
13676         if (num == 0) {
13677                 PMD_DRV_LOG(ERR,
13678                         "No PF queues are configured to enable RSS for port %u",
13679                         pf->dev_data->port_id);
13680                 return -ENOTSUP;
13681         }
13682
13683         /* Fill in redirection table */
13684         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13685                 if (j == num)
13686                         j = 0;
13687                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13688                         hw->func_caps.rss_table_entry_width) - 1));
13689                 if ((i & 3) == 3)
13690                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13691         }
13692
13693         rss_info->conf.queue_num = 0;
13694         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13695
13696         return 0;
13697 }
13698
13699 int
13700 i40e_config_rss_filter(struct i40e_pf *pf,
13701                 struct i40e_rte_flow_rss_conf *conf, bool add)
13702 {
13703         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13704         struct rte_flow_action_rss update_conf = rss_info->conf;
13705         int ret = 0;
13706
13707         if (add) {
13708                 if (conf->conf.queue_num) {
13709                         /* Configure RSS queue region */
13710                         ret = i40e_rss_config_queue_region(pf, conf);
13711                         if (ret)
13712                                 return ret;
13713
13714                         update_conf.queue_num = conf->conf.queue_num;
13715                         update_conf.queue = conf->conf.queue;
13716                 } else if (conf->conf.func ==
13717                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13718                         /* Configure hash function */
13719                         ret = i40e_rss_config_hash_function(pf, conf);
13720                         if (ret)
13721                                 return ret;
13722
13723                         update_conf.func = conf->conf.func;
13724                 } else {
13725                         /* Configure hash enable and input set */
13726                         ret = i40e_rss_enable_hash(pf, conf);
13727                         if (ret)
13728                                 return ret;
13729
13730                         update_conf.types |= conf->conf.types;
13731                         update_conf.key = conf->conf.key;
13732                         update_conf.key_len = conf->conf.key_len;
13733                 }
13734
13735                 /* Update RSS info in pf */
13736                 if (i40e_rss_conf_init(rss_info, &update_conf))
13737                         return -EINVAL;
13738         } else {
13739                 if (!conf->valid)
13740                         return 0;
13741
13742                 if (conf->conf.queue_num)
13743                         i40e_rss_clear_queue_region(pf);
13744                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13745                         i40e_rss_clear_hash_function(pf, conf);
13746                 else
13747                         i40e_rss_disable_hash(pf, conf);
13748         }
13749
13750         return 0;
13751 }
13752
13753 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13754 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13755 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13756 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13757 #endif
13758 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13759 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13760 #endif
13761 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13762 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13763 #endif
13764
13765 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13766                               ETH_I40E_FLOATING_VEB_ARG "=1"
13767                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13768                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13769                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13770                               ETH_I40E_USE_LATEST_VEC "=0|1");