drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA  0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 133
 134 #define I40E_MAX_PERCENT            100
 135 #define I40E_DEFAULT_DCB_APP_NUM    1
 136 #define I40E_DEFAULT_DCB_APP_PRIO   3
 137
 138 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 139 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 140 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 141 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 143 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 144
 145 #define I40E_INSET_NONE            0x00000000000000000ULL
 146
 147 /* bit0 ~ bit 7 */
 148 #define I40E_INSET_DMAC            0x0000000000000001ULL
 149 #define I40E_INSET_SMAC            0x0000000000000002ULL
 150 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 151 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 152 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 153
 154 /* bit 8 ~ bit 15 */
 155 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 156 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 157 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 158 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 159 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 160 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 161 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 162
 163 /* bit 16 ~ bit 31 */
 164 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 165 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 166 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 167 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 168 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 169 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 170 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 171 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 172
 173 /* bit 32 ~ bit 47, tunnel fields */
 174 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 175 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 176 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 177 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 178 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 179 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 180
 181 /* bit 48 ~ bit 55 */
 182 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 183
 184 /* bit 56 ~ bit 63, Flex Payload */
 185 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD \
 194         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 195         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 196         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 197         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 198
 199 /**
 200  * Below are values for writing un-exposed registers suggested
 201  * by silicon experts
 202  */
 203 /* Destination MAC address */
 204 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 205 /* Source MAC address */
 206 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 207 /* VLAN tag in the outer L2 header */
 208 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 209 /* VLAN tag in the inner L2 header */
 210 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 211 /* Source IPv4 address */
 212 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 213 /* Destination IPv4 address */
 214 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 215 /* IPv4 Type of Service (TOS) */
 216 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 217 /* IPv4 Protocol */
 218 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 219 /* Source IPv6 address */
 220 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 221 /* Destination IPv6 address */
 222 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 223 /* IPv6 Traffic Class (TC) */
 224 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 225 /* IPv6 Next Header */
 226 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263
 264 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 265
 266 #define I40E_TRANSLATE_INSET 0
 267 #define I40E_TRANSLATE_REG   1
 268
 269 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 270 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 271 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 272 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 273
 274 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 275 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 276 static int i40e_dev_configure(struct rte_eth_dev *dev);
 277 static int i40e_dev_start(struct rte_eth_dev *dev);
 278 static void i40e_dev_stop(struct rte_eth_dev *dev);
 279 static void i40e_dev_close(struct rte_eth_dev *dev);
 280 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 281 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 282 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 284 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 285 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 286 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 287                                struct rte_eth_stats *stats);
 288 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_xstats *xstats, unsigned n);
 290 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 291 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 292                                             uint16_t queue_id,
 293                                             uint8_t stat_idx,
 294                                             uint8_t is_rx);
 295 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 296                               struct rte_eth_dev_info *dev_info);
 297 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 298                                 uint16_t vlan_id,
 299                                 int on);
 300 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 301 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 302 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 303                                       uint16_t queue,
 304                                       int on);
 305 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 306 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 307 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 308 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 309                               struct rte_eth_fc_conf *fc_conf);
 310 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 311                               struct rte_eth_fc_conf *fc_conf);
 312 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 313                                        struct rte_eth_pfc_conf *pfc_conf);
 314 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 315                           struct ether_addr *mac_addr,
 316                           uint32_t index,
 317                           uint32_t pool);
 318 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 319 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 320                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 321                                     uint16_t reta_size);
 322 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 323                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 324                                    uint16_t reta_size);
 325
 326 static int i40e_get_cap(struct i40e_hw *hw);
 327 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 328 static int i40e_pf_setup(struct i40e_pf *pf);
 329 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 330 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 331 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 332 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 333 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 334                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 335 static void i40e_stat_update_48(struct i40e_hw *hw,
 336                                uint32_t hireg,
 337                                uint32_t loreg,
 338                                bool offset_loaded,
 339                                uint64_t *offset,
 340                                uint64_t *stat);
 341 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 342 static void i40e_dev_interrupt_handler(
 343                 __rte_unused struct rte_intr_handle *handle, void *param);
 344 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 345                                 uint32_t base, uint32_t num);
 346 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 347 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 348                         uint32_t base);
 349 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 350                         uint16_t num);
 351 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 352 static int i40e_veb_release(struct i40e_veb *veb);
 353 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 354                                                 struct i40e_vsi *vsi);
 355 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 356 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 357 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 358                                              struct i40e_macvlan_filter *mv_f,
 359                                              int num,
 360                                              struct ether_addr *addr);
 361 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 362                                              struct i40e_macvlan_filter *mv_f,
 363                                              int num,
 364                                              uint16_t vlan);
 365 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 366 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 367                                     struct rte_eth_rss_conf *rss_conf);
 368 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 369                                       struct rte_eth_rss_conf *rss_conf);
 370 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 371                                 struct rte_eth_udp_tunnel *udp_tunnel);
 372 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 373                                 struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 375                         struct rte_eth_ethertype_filter *filter,
 376                         bool add);
 377 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 378                                 enum rte_filter_op filter_op,
 379                                 void *arg);
 380 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 381                                 enum rte_filter_type filter_type,
 382                                 enum rte_filter_op filter_op,
 383                                 void *arg);
 384 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 385                                   struct rte_eth_dcb_info *dcb_info);
 386 static void i40e_configure_registers(struct i40e_hw *hw);
 387 static void i40e_hw_init(struct i40e_hw *hw);
 388 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 389 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 390                         struct rte_eth_mirror_conf *mirror_conf,
 391                         uint8_t sw_id, uint8_t on);
 392 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 393
 394 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 395 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 396 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 397                                            struct timespec *timestamp,
 398                                            uint32_t flags);
 399 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 400                                            struct timespec *timestamp);
 401 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 402 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 403                                          uint16_t queue_id);
 404 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 405                                           uint16_t queue_id);
 406
 407 static const struct rte_pci_id pci_id_i40e_map[] = {
 408 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 409 #include "rte_pci_dev_ids.h"
 410 { .vendor_id = 0, /* sentinel */ },
 411 };
 412
 413 static const struct eth_dev_ops i40e_eth_dev_ops = {
 414         .dev_configure                = i40e_dev_configure,
 415         .dev_start                    = i40e_dev_start,
 416         .dev_stop                     = i40e_dev_stop,
 417         .dev_close                    = i40e_dev_close,
 418         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 419         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 420         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 421         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 422         .dev_set_link_up              = i40e_dev_set_link_up,
 423         .dev_set_link_down            = i40e_dev_set_link_down,
 424         .link_update                  = i40e_dev_link_update,
 425         .stats_get                    = i40e_dev_stats_get,
 426         .xstats_get                   = i40e_dev_xstats_get,
 427         .stats_reset                  = i40e_dev_stats_reset,
 428         .xstats_reset                 = i40e_dev_stats_reset,
 429         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 430         .dev_infos_get                = i40e_dev_info_get,
 431         .vlan_filter_set              = i40e_vlan_filter_set,
 432         .vlan_tpid_set                = i40e_vlan_tpid_set,
 433         .vlan_offload_set             = i40e_vlan_offload_set,
 434         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 435         .vlan_pvid_set                = i40e_vlan_pvid_set,
 436         .rx_queue_start               = i40e_dev_rx_queue_start,
 437         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 438         .tx_queue_start               = i40e_dev_tx_queue_start,
 439         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 440         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 441         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 442         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 443         .rx_queue_release             = i40e_dev_rx_queue_release,
 444         .rx_queue_count               = i40e_dev_rx_queue_count,
 445         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 446         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 447         .tx_queue_release             = i40e_dev_tx_queue_release,
 448         .dev_led_on                   = i40e_dev_led_on,
 449         .dev_led_off                  = i40e_dev_led_off,
 450         .flow_ctrl_get                = i40e_flow_ctrl_get,
 451         .flow_ctrl_set                = i40e_flow_ctrl_set,
 452         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 453         .mac_addr_add                 = i40e_macaddr_add,
 454         .mac_addr_remove              = i40e_macaddr_remove,
 455         .reta_update                  = i40e_dev_rss_reta_update,
 456         .reta_query                   = i40e_dev_rss_reta_query,
 457         .rss_hash_update              = i40e_dev_rss_hash_update,
 458         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 459         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 460         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 461         .filter_ctrl                  = i40e_dev_filter_ctrl,
 462         .rxq_info_get                 = i40e_rxq_info_get,
 463         .txq_info_get                 = i40e_txq_info_get,
 464         .mirror_rule_set              = i40e_mirror_rule_set,
 465         .mirror_rule_reset            = i40e_mirror_rule_reset,
 466         .timesync_enable              = i40e_timesync_enable,
 467         .timesync_disable             = i40e_timesync_disable,
 468         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 469         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 470         .get_dcb_info                 = i40e_dev_get_dcb_info,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_i40e_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 480         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 481         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 482         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 483         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 484         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 485                 rx_unknown_protocol)},
 486         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 487         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 488         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 489         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 490 };
 491
 492 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 493                 sizeof(rte_i40e_stats_strings[0]))
 494
 495 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 496         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 497                 tx_dropped_link_down)},
 498         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 499         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 500                 illegal_bytes)},
 501         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 502         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 503                 mac_local_faults)},
 504         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 505                 mac_remote_faults)},
 506         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 507                 rx_length_errors)},
 508         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 509         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 510         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 511         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 512         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 513         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 514                 rx_size_127)},
 515         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 516                 rx_size_255)},
 517         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 518                 rx_size_511)},
 519         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 520                 rx_size_1023)},
 521         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 522                 rx_size_1522)},
 523         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 524                 rx_size_big)},
 525         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 526                 rx_undersize)},
 527         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 528                 rx_oversize)},
 529         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 530                 mac_short_packet_dropped)},
 531         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_fragments)},
 533         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 534         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 535         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 536                 tx_size_127)},
 537         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 538                 tx_size_255)},
 539         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 540                 tx_size_511)},
 541         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 542                 tx_size_1023)},
 543         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 544                 tx_size_1522)},
 545         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 546                 tx_size_big)},
 547         {"rx_flow_director_atr_match_packets",
 548                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 549         {"rx_flow_director_sb_match_packets",
 550                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 551         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 552                 tx_lpi_status)},
 553         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 554                 rx_lpi_status)},
 555         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 556                 tx_lpi_count)},
 557         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 558                 rx_lpi_count)},
 559 };
 560
 561 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 562                 sizeof(rte_i40e_hw_port_strings[0]))
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 565         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 566                 priority_xon_rx)},
 567         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 568                 priority_xoff_rx)},
 569 };
 570
 571 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 572                 sizeof(rte_i40e_rxq_prio_strings[0]))
 573
 574 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 575         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 576                 priority_xon_tx)},
 577         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 578                 priority_xoff_tx)},
 579         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 580                 priority_xon_2_xoff)},
 581 };
 582
 583 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 584                 sizeof(rte_i40e_txq_prio_strings[0]))
 585
 586 static struct eth_driver rte_i40e_pmd = {
 587         .pci_drv = {
 588                 .name = "rte_i40e_pmd",
 589                 .id_table = pci_id_i40e_map,
 590                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 591                         RTE_PCI_DRV_DETACHABLE,
 592         },
 593         .eth_dev_init = eth_i40e_dev_init,
 594         .eth_dev_uninit = eth_i40e_dev_uninit,
 595         .dev_private_size = sizeof(struct i40e_adapter),
 596 };
 597
 598 static inline int
 599 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 600                                      struct rte_eth_link *link)
 601 {
 602         struct rte_eth_link *dst = link;
 603         struct rte_eth_link *src = &(dev->data->dev_link);
 604
 605         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 606                                         *(uint64_t *)src) == 0)
 607                 return -1;
 608
 609         return 0;
 610 }
 611
 612 static inline int
 613 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 614                                       struct rte_eth_link *link)
 615 {
 616         struct rte_eth_link *dst = &(dev->data->dev_link);
 617         struct rte_eth_link *src = link;
 618
 619         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 620                                         *(uint64_t *)src) == 0)
 621                 return -1;
 622
 623         return 0;
 624 }
 625
 626 /*
 627  * Driver initialization routine.
 628  * Invoked once at EAL init time.
 629  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 630  */
 631 static int
 632 rte_i40e_pmd_init(const char *name __rte_unused,
 633                   const char *params __rte_unused)
 634 {
 635         PMD_INIT_FUNC_TRACE();
 636         rte_eth_driver_register(&rte_i40e_pmd);
 637
 638         return 0;
 639 }
 640
 641 static struct rte_driver rte_i40e_driver = {
 642         .type = PMD_PDEV,
 643         .init = rte_i40e_pmd_init,
 644 };
 645
 646 PMD_REGISTER_DRIVER(rte_i40e_driver);
 647
 648 /*
 649  * Initialize registers for flexible payload, which should be set by NVM.
 650  * This should be removed from code once it is fixed in NVM.
 651  */
 652 #ifndef I40E_GLQF_ORT
 653 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 654 #endif
 655 #ifndef I40E_GLQF_PIT
 656 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 657 #endif
 658
 659 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 660 {
 661         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 662         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 663         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 664         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 665         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 666         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 667         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 668         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 669         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 670         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 671
 672         /* GLQF_PIT Registers */
 673         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 674         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 675 }
 676
 677 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 678
 679 /*
 680  * Add a ethertype filter to drop all flow control frames transmitted
 681  * from VSIs.
 682 */
 683 static void
 684 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 685 {
 686         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 687         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 688                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 689                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 690         int ret;
 691
 692         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 693                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 694                                 pf->main_vsi_seid, 0,
 695                                 TRUE, NULL, NULL);
 696         if (ret)
 697                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 698                                   " frames from VSIs.");
 699 }
 700
 701 static int
 702 eth_i40e_dev_init(struct rte_eth_dev *dev)
 703 {
 704         struct rte_pci_device *pci_dev;
 705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 707         struct i40e_vsi *vsi;
 708         int ret;
 709         uint32_t len;
 710         uint8_t aq_fail = 0;
 711
 712         PMD_INIT_FUNC_TRACE();
 713
 714         dev->dev_ops = &i40e_eth_dev_ops;
 715         dev->rx_pkt_burst = i40e_recv_pkts;
 716         dev->tx_pkt_burst = i40e_xmit_pkts;
 717
 718         /* for secondary processes, we don't initialise any further as primary
 719          * has already done this work. Only check we don't need a different
 720          * RX function */
 721         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 722                 i40e_set_rx_function(dev);
 723                 i40e_set_tx_function(dev);
 724                 return 0;
 725         }
 726         pci_dev = dev->pci_dev;
 727
 728         rte_eth_copy_pci_info(dev, pci_dev);
 729
 730         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 731         pf->adapter->eth_dev = dev;
 732         pf->dev_data = dev->data;
 733
 734         hw->back = I40E_PF_TO_ADAPTER(pf);
 735         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 736         if (!hw->hw_addr) {
 737                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 738                              "as address is NULL");
 739                 return -ENODEV;
 740         }
 741
 742         hw->vendor_id = pci_dev->id.vendor_id;
 743         hw->device_id = pci_dev->id.device_id;
 744         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 745         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 746         hw->bus.device = pci_dev->addr.devid;
 747         hw->bus.func = pci_dev->addr.function;
 748         hw->adapter_stopped = 0;
 749
 750         /* Make sure all is clean before doing PF reset */
 751         i40e_clear_hw(hw);
 752
 753         /* Initialize the hardware */
 754         i40e_hw_init(hw);
 755
 756         /* Reset here to make sure all is clean for each PF */
 757         ret = i40e_pf_reset(hw);
 758         if (ret) {
 759                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 760                 return ret;
 761         }
 762
 763         /* Initialize the shared code (base driver) */
 764         ret = i40e_init_shared_code(hw);
 765         if (ret) {
 766                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 767                 return ret;
 768         }
 769
 770         /*
 771          * To work around the NVM issue,initialize registers
 772          * for flexible payload by software.
 773          * It should be removed once issues are fixed in NVM.
 774          */
 775         i40e_flex_payload_reg_init(hw);
 776
 777         /* Initialize the parameters for adminq */
 778         i40e_init_adminq_parameter(hw);
 779         ret = i40e_init_adminq(hw);
 780         if (ret != I40E_SUCCESS) {
 781                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 782                 return -EIO;
 783         }
 784         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 785                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 786                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 787                      ((hw->nvm.version >> 12) & 0xf),
 788                      ((hw->nvm.version >> 4) & 0xff),
 789                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 790
 791         /* Clear PXE mode */
 792         i40e_clear_pxe_mode(hw);
 793
 794         /*
 795          * On X710, performance number is far from the expectation on recent
 796          * firmware versions. The fix for this issue may not be integrated in
 797          * the following firmware version. So the workaround in software driver
 798          * is needed. It needs to modify the initial values of 3 internal only
 799          * registers. Note that the workaround can be removed when it is fixed
 800          * in firmware in the future.
 801          */
 802         i40e_configure_registers(hw);
 803
 804         /* Get hw capabilities */
 805         ret = i40e_get_cap(hw);
 806         if (ret != I40E_SUCCESS) {
 807                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 808                 goto err_get_capabilities;
 809         }
 810
 811         /* Initialize parameters for PF */
 812         ret = i40e_pf_parameter_init(dev);
 813         if (ret != 0) {
 814                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 815                 goto err_parameter_init;
 816         }
 817
 818         /* Initialize the queue management */
 819         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 820         if (ret < 0) {
 821                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 822                 goto err_qp_pool_init;
 823         }
 824         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 825                                 hw->func_caps.num_msix_vectors - 1);
 826         if (ret < 0) {
 827                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 828                 goto err_msix_pool_init;
 829         }
 830
 831         /* Initialize lan hmc */
 832         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 833                                 hw->func_caps.num_rx_qp, 0, 0);
 834         if (ret != I40E_SUCCESS) {
 835                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 836                 goto err_init_lan_hmc;
 837         }
 838
 839         /* Configure lan hmc */
 840         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 841         if (ret != I40E_SUCCESS) {
 842                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 843                 goto err_configure_lan_hmc;
 844         }
 845
 846         /* Get and check the mac address */
 847         i40e_get_mac_addr(hw, hw->mac.addr);
 848         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "mac address is not valid");
 850                 ret = -EIO;
 851                 goto err_get_mac_addr;
 852         }
 853         /* Copy the permanent MAC address */
 854         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 855                         (struct ether_addr *) hw->mac.perm_addr);
 856
 857         /* Disable flow control */
 858         hw->fc.requested_mode = I40E_FC_NONE;
 859         i40e_set_fc(hw, &aq_fail, TRUE);
 860
 861         /* PF setup, which includes VSI setup */
 862         ret = i40e_pf_setup(pf);
 863         if (ret) {
 864                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 865                 goto err_setup_pf_switch;
 866         }
 867
 868         vsi = pf->main_vsi;
 869
 870         /* Disable double vlan by default */
 871         i40e_vsi_config_double_vlan(vsi, FALSE);
 872
 873         if (!vsi->max_macaddrs)
 874                 len = ETHER_ADDR_LEN;
 875         else
 876                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 877
 878         /* Should be after VSI initialized */
 879         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 880         if (!dev->data->mac_addrs) {
 881                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 882                                         "for storing mac address");
 883                 goto err_mac_alloc;
 884         }
 885         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 886                                         &dev->data->mac_addrs[0]);
 887
 888         /* initialize pf host driver to setup SRIOV resource if applicable */
 889         i40e_pf_host_init(dev);
 890
 891         /* register callback func to eal lib */
 892         rte_intr_callback_register(&(pci_dev->intr_handle),
 893                 i40e_dev_interrupt_handler, (void *)dev);
 894
 895         /* configure and enable device interrupt */
 896         i40e_pf_config_irq0(hw, TRUE);
 897         i40e_pf_enable_irq0(hw);
 898
 899         /* enable uio intr after callback register */
 900         rte_intr_enable(&(pci_dev->intr_handle));
 901         /*
 902          * Add an ethertype filter to drop all flow control frames transmitted
 903          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 904          * frames to wire.
 905          */
 906         i40e_add_tx_flow_control_drop_filter(pf);
 907
 908         /* initialize mirror rule list */
 909         TAILQ_INIT(&pf->mirror_list);
 910
 911         /* Init dcb to sw mode by default */
 912         ret = i40e_dcb_init_configure(dev, TRUE);
 913         if (ret != I40E_SUCCESS) {
 914                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 915                 pf->flags &= ~I40E_FLAG_DCB;
 916         }
 917
 918         return 0;
 919
 920 err_mac_alloc:
 921         i40e_vsi_release(pf->main_vsi);
 922 err_setup_pf_switch:
 923 err_get_mac_addr:
 924 err_configure_lan_hmc:
 925         (void)i40e_shutdown_lan_hmc(hw);
 926 err_init_lan_hmc:
 927         i40e_res_pool_destroy(&pf->msix_pool);
 928 err_msix_pool_init:
 929         i40e_res_pool_destroy(&pf->qp_pool);
 930 err_qp_pool_init:
 931 err_parameter_init:
 932 err_get_capabilities:
 933         (void)i40e_shutdown_adminq(hw);
 934
 935         return ret;
 936 }
 937
 938 static int
 939 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 940 {
 941         struct rte_pci_device *pci_dev;
 942         struct i40e_hw *hw;
 943         struct i40e_filter_control_settings settings;
 944         int ret;
 945         uint8_t aq_fail = 0;
 946
 947         PMD_INIT_FUNC_TRACE();
 948
 949         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 950                 return 0;
 951
 952         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 953         pci_dev = dev->pci_dev;
 954
 955         if (hw->adapter_stopped == 0)
 956                 i40e_dev_close(dev);
 957
 958         dev->dev_ops = NULL;
 959         dev->rx_pkt_burst = NULL;
 960         dev->tx_pkt_burst = NULL;
 961
 962         /* Disable LLDP */
 963         ret = i40e_aq_stop_lldp(hw, true, NULL);
 964         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 965                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 966
 967         /* Clear PXE mode */
 968         i40e_clear_pxe_mode(hw);
 969
 970         /* Unconfigure filter control */
 971         memset(&settings, 0, sizeof(settings));
 972         ret = i40e_set_filter_control(hw, &settings);
 973         if (ret)
 974                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 975                                         ret);
 976
 977         /* Disable flow control */
 978         hw->fc.requested_mode = I40E_FC_NONE;
 979         i40e_set_fc(hw, &aq_fail, TRUE);
 980
 981         /* uninitialize pf host driver */
 982         i40e_pf_host_uninit(dev);
 983
 984         rte_free(dev->data->mac_addrs);
 985         dev->data->mac_addrs = NULL;
 986
 987         /* disable uio intr before callback unregister */
 988         rte_intr_disable(&(pci_dev->intr_handle));
 989
 990         /* register callback func to eal lib */
 991         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 992                 i40e_dev_interrupt_handler, (void *)dev);
 993
 994         return 0;
 995 }
 996
 997 static int
 998 i40e_dev_configure(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_adapter *ad =
1001                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1004         int i, ret;
1005
1006         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1007          * bulk allocation or vector Rx preconditions we will reset it.
1008          */
1009         ad->rx_bulk_alloc_allowed = true;
1010         ad->rx_vec_allowed = true;
1011         ad->tx_simple_allowed = true;
1012         ad->tx_vec_allowed = true;
1013
1014         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1015                 ret = i40e_fdir_setup(pf);
1016                 if (ret != I40E_SUCCESS) {
1017                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1018                         return -ENOTSUP;
1019                 }
1020                 ret = i40e_fdir_configure(dev);
1021                 if (ret < 0) {
1022                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1023                         goto err;
1024                 }
1025         } else
1026                 i40e_fdir_teardown(pf);
1027
1028         ret = i40e_dev_init_vlan(dev);
1029         if (ret < 0)
1030                 goto err;
1031
1032         /* VMDQ setup.
1033          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1034          *  RSS setting have different requirements.
1035          *  General PMD driver call sequence are NIC init, configure,
1036          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1037          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1038          *  applicable. So, VMDQ setting has to be done before
1039          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1040          *  For RSS setting, it will try to calculate actual configured RX queue
1041          *  number, which will be available after rx_queue_setup(). dev_start()
1042          *  function is good to place RSS setup.
1043          */
1044         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1045                 ret = i40e_vmdq_setup(dev);
1046                 if (ret)
1047                         goto err;
1048         }
1049
1050         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1051                 ret = i40e_dcb_setup(dev);
1052                 if (ret) {
1053                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1054                         goto err_dcb;
1055                 }
1056         }
1057
1058         return 0;
1059
1060 err_dcb:
1061         /* need to release vmdq resource if exists */
1062         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1063                 i40e_vsi_release(pf->vmdq[i].vsi);
1064                 pf->vmdq[i].vsi = NULL;
1065         }
1066         rte_free(pf->vmdq);
1067         pf->vmdq = NULL;
1068 err:
1069         /* need to release fdir resource if exists */
1070         i40e_fdir_teardown(pf);
1071         return ret;
1072 }
1073
1074 void
1075 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1076 {
1077         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1078         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1079         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1080         uint16_t msix_vect = vsi->msix_intr;
1081         uint16_t i;
1082
1083         for (i = 0; i < vsi->nb_qps; i++) {
1084                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1085                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1086                 rte_wmb();
1087         }
1088
1089         if (vsi->type != I40E_VSI_SRIOV) {
1090                 if (!rte_intr_allow_others(intr_handle)) {
1091                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1092                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1093                         I40E_WRITE_REG(hw,
1094                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1095                                        0);
1096                 } else {
1097                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1098                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1099                         I40E_WRITE_REG(hw,
1100                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1101                                                        msix_vect - 1), 0);
1102                 }
1103         } else {
1104                 uint32_t reg;
1105                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1106                         vsi->user_param + (msix_vect - 1);
1107
1108                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1109                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1110         }
1111         I40E_WRITE_FLUSH(hw);
1112 }
1113
1114 static void
1115 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1116                        int base_queue, int nb_queue)
1117 {
1118         int i;
1119         uint32_t val;
1120         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1121
1122         /* Bind all RX queues to allocated MSIX interrupt */
1123         for (i = 0; i < nb_queue; i++) {
1124                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1125                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1126                         ((base_queue + i + 1) <<
1127                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1128                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1129                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1130
1131                 if (i == nb_queue - 1)
1132                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1133                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1134         }
1135
1136         /* Write first RX queue to Link list register as the head element */
1137         if (vsi->type != I40E_VSI_SRIOV) {
1138                 uint16_t interval =
1139                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1140
1141                 if (msix_vect == I40E_MISC_VEC_ID) {
1142                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1143                                        (base_queue <<
1144                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1145                                        (0x0 <<
1146                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1147                         I40E_WRITE_REG(hw,
1148                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1149                                        interval);
1150                 } else {
1151                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1152                                        (base_queue <<
1153                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1154                                        (0x0 <<
1155                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1156                         I40E_WRITE_REG(hw,
1157                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1158                                                        msix_vect - 1),
1159                                        interval);
1160                 }
1161         } else {
1162                 uint32_t reg;
1163
1164                 if (msix_vect == I40E_MISC_VEC_ID) {
1165                         I40E_WRITE_REG(hw,
1166                                        I40E_VPINT_LNKLST0(vsi->user_param),
1167                                        (base_queue <<
1168                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1169                                        (0x0 <<
1170                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1171                 } else {
1172                         /* num_msix_vectors_vf needs to minus irq0 */
1173                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1174                                 vsi->user_param + (msix_vect - 1);
1175
1176                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1177                                        (base_queue <<
1178                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1179                                        (0x0 <<
1180                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1181                 }
1182         }
1183
1184         I40E_WRITE_FLUSH(hw);
1185 }
1186
1187 void
1188 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1189 {
1190         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1191         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1192         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1193         uint16_t msix_vect = vsi->msix_intr;
1194         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1195         uint16_t queue_idx = 0;
1196         int record = 0;
1197         uint32_t val;
1198         int i;
1199
1200         for (i = 0; i < vsi->nb_qps; i++) {
1201                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1202                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1203         }
1204
1205         /* INTENA flag is not auto-cleared for interrupt */
1206         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1207         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1208                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1209                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1210         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1211
1212         /* VF bind interrupt */
1213         if (vsi->type == I40E_VSI_SRIOV) {
1214                 __vsi_queues_bind_intr(vsi, msix_vect,
1215                                        vsi->base_queue, vsi->nb_qps);
1216                 return;
1217         }
1218
1219         /* PF & VMDq bind interrupt */
1220         if (rte_intr_dp_is_en(intr_handle)) {
1221                 if (vsi->type == I40E_VSI_MAIN) {
1222                         queue_idx = 0;
1223                         record = 1;
1224                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1225                         struct i40e_vsi *main_vsi =
1226                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1227                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1228                         record = 1;
1229                 }
1230         }
1231
1232         for (i = 0; i < vsi->nb_used_qps; i++) {
1233                 if (nb_msix <= 1) {
1234                         if (!rte_intr_allow_others(intr_handle))
1235                                 /* allow to share MISC_VEC_ID */
1236                                 msix_vect = I40E_MISC_VEC_ID;
1237
1238                         /* no enough msix_vect, map all to one */
1239                         __vsi_queues_bind_intr(vsi, msix_vect,
1240                                                vsi->base_queue + i,
1241                                                vsi->nb_used_qps - i);
1242                         for (; !!record && i < vsi->nb_used_qps; i++)
1243                                 intr_handle->intr_vec[queue_idx + i] =
1244                                         msix_vect;
1245                         break;
1246                 }
1247                 /* 1:1 queue/msix_vect mapping */
1248                 __vsi_queues_bind_intr(vsi, msix_vect,
1249                                        vsi->base_queue + i, 1);
1250                 if (!!record)
1251                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1252
1253                 msix_vect++;
1254                 nb_msix--;
1255         }
1256 }
1257
1258 static void
1259 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1260 {
1261         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1262         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1263         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1264         uint16_t interval = i40e_calc_itr_interval(\
1265                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1266         uint16_t msix_intr, i;
1267
1268         if (rte_intr_allow_others(intr_handle))
1269                 for (i = 0; i < vsi->nb_msix; i++) {
1270                         msix_intr = vsi->msix_intr + i;
1271                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1272                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1273                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1274                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1275                                 (interval <<
1276                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1277                 }
1278         else
1279                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1280                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1281                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1282                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1283                                (interval <<
1284                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1285
1286         I40E_WRITE_FLUSH(hw);
1287 }
1288
1289 static void
1290 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1291 {
1292         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1293         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1294         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1295         uint16_t msix_intr, i;
1296
1297         if (rte_intr_allow_others(intr_handle))
1298                 for (i = 0; i < vsi->nb_msix; i++) {
1299                         msix_intr = vsi->msix_intr + i;
1300                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1301                                        0);
1302                 }
1303         else
1304                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1305
1306         I40E_WRITE_FLUSH(hw);
1307 }
1308
1309 static inline uint8_t
1310 i40e_parse_link_speed(uint16_t eth_link_speed)
1311 {
1312         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1313
1314         switch (eth_link_speed) {
1315         case ETH_LINK_SPEED_40G:
1316                 link_speed = I40E_LINK_SPEED_40GB;
1317                 break;
1318         case ETH_LINK_SPEED_20G:
1319                 link_speed = I40E_LINK_SPEED_20GB;
1320                 break;
1321         case ETH_LINK_SPEED_10G:
1322                 link_speed = I40E_LINK_SPEED_10GB;
1323                 break;
1324         case ETH_LINK_SPEED_1000:
1325                 link_speed = I40E_LINK_SPEED_1GB;
1326                 break;
1327         case ETH_LINK_SPEED_100:
1328                 link_speed = I40E_LINK_SPEED_100MB;
1329                 break;
1330         }
1331
1332         return link_speed;
1333 }
1334
1335 static int
1336 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1337 {
1338         enum i40e_status_code status;
1339         struct i40e_aq_get_phy_abilities_resp phy_ab;
1340         struct i40e_aq_set_phy_config phy_conf;
1341         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1342                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1343                         I40E_AQ_PHY_FLAG_LOW_POWER;
1344         const uint8_t advt = I40E_LINK_SPEED_40GB |
1345                         I40E_LINK_SPEED_10GB |
1346                         I40E_LINK_SPEED_1GB |
1347                         I40E_LINK_SPEED_100MB;
1348         int ret = -ENOTSUP;
1349
1350         /* Skip it on 40G interfaces, as a workaround for the link issue */
1351         if (i40e_is_40G_device(hw->device_id))
1352                 return I40E_SUCCESS;
1353
1354         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1355                                               NULL);
1356         if (status)
1357                 return ret;
1358
1359         memset(&phy_conf, 0, sizeof(phy_conf));
1360
1361         /* bits 0-2 use the values from get_phy_abilities_resp */
1362         abilities &= ~mask;
1363         abilities |= phy_ab.abilities & mask;
1364
1365         /* update ablities and speed */
1366         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1367                 phy_conf.link_speed = advt;
1368         else
1369                 phy_conf.link_speed = force_speed;
1370
1371         phy_conf.abilities = abilities;
1372
1373         /* use get_phy_abilities_resp value for the rest */
1374         phy_conf.phy_type = phy_ab.phy_type;
1375         phy_conf.eee_capability = phy_ab.eee_capability;
1376         phy_conf.eeer = phy_ab.eeer_val;
1377         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1378
1379         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1380                     phy_ab.abilities, phy_ab.link_speed);
1381         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1382                     phy_conf.abilities, phy_conf.link_speed);
1383
1384         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1385         if (status)
1386                 return ret;
1387
1388         return I40E_SUCCESS;
1389 }
1390
1391 static int
1392 i40e_apply_link_speed(struct rte_eth_dev *dev)
1393 {
1394         uint8_t speed;
1395         uint8_t abilities = 0;
1396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         struct rte_eth_conf *conf = &dev->data->dev_conf;
1398
1399         speed = i40e_parse_link_speed(conf->link_speed);
1400         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1401         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1402                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1403         else
1404                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1405
1406         return i40e_phy_conf_link(hw, abilities, speed);
1407 }
1408
1409 static int
1410 i40e_dev_start(struct rte_eth_dev *dev)
1411 {
1412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414         struct i40e_vsi *main_vsi = pf->main_vsi;
1415         int ret, i;
1416         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1417         uint32_t intr_vector = 0;
1418
1419         hw->adapter_stopped = 0;
1420
1421         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1422                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1423                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1424                              dev->data->dev_conf.link_duplex,
1425                              dev->data->port_id);
1426                 return -EINVAL;
1427         }
1428
1429         rte_intr_disable(intr_handle);
1430
1431         if ((rte_intr_cap_multiple(intr_handle) ||
1432              !RTE_ETH_DEV_SRIOV(dev).active) &&
1433             dev->data->dev_conf.intr_conf.rxq != 0) {
1434                 intr_vector = dev->data->nb_rx_queues;
1435                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1436                         return -1;
1437         }
1438
1439         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1440                 intr_handle->intr_vec =
1441                         rte_zmalloc("intr_vec",
1442                                     dev->data->nb_rx_queues * sizeof(int),
1443                                     0);
1444                 if (!intr_handle->intr_vec) {
1445                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1446                                      " intr_vec\n", dev->data->nb_rx_queues);
1447                         return -ENOMEM;
1448                 }
1449         }
1450
1451         /* Initialize VSI */
1452         ret = i40e_dev_rxtx_init(pf);
1453         if (ret != I40E_SUCCESS) {
1454                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1455                 goto err_up;
1456         }
1457
1458         /* Map queues with MSIX interrupt */
1459         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1460                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1461         i40e_vsi_queues_bind_intr(main_vsi);
1462         i40e_vsi_enable_queues_intr(main_vsi);
1463
1464         /* Map VMDQ VSI queues with MSIX interrupt */
1465         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1466                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1467                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1468                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1469         }
1470
1471         /* enable FDIR MSIX interrupt */
1472         if (pf->fdir.fdir_vsi) {
1473                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1474                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1475         }
1476
1477         /* Enable all queues which have been configured */
1478         ret = i40e_dev_switch_queues(pf, TRUE);
1479         if (ret != I40E_SUCCESS) {
1480                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1481                 goto err_up;
1482         }
1483
1484         /* Enable receiving broadcast packets */
1485         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1486         if (ret != I40E_SUCCESS)
1487                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1488
1489         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1490                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1491                                                 true, NULL);
1492                 if (ret != I40E_SUCCESS)
1493                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1494         }
1495
1496         /* Apply link configure */
1497         ret = i40e_apply_link_speed(dev);
1498         if (I40E_SUCCESS != ret) {
1499                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1500                 goto err_up;
1501         }
1502
1503         if (!rte_intr_allow_others(intr_handle)) {
1504                 rte_intr_callback_unregister(intr_handle,
1505                                              i40e_dev_interrupt_handler,
1506                                              (void *)dev);
1507                 /* configure and enable device interrupt */
1508                 i40e_pf_config_irq0(hw, FALSE);
1509                 i40e_pf_enable_irq0(hw);
1510
1511                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1512                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1513                                      " no intr multiplex\n");
1514         }
1515
1516         /* enable uio intr after callback register */
1517         rte_intr_enable(intr_handle);
1518
1519         return I40E_SUCCESS;
1520
1521 err_up:
1522         i40e_dev_switch_queues(pf, FALSE);
1523         i40e_dev_clear_queues(dev);
1524
1525         return ret;
1526 }
1527
1528 static void
1529 i40e_dev_stop(struct rte_eth_dev *dev)
1530 {
1531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1532         struct i40e_vsi *main_vsi = pf->main_vsi;
1533         struct i40e_mirror_rule *p_mirror;
1534         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1535         int i;
1536
1537         /* Disable all queues */
1538         i40e_dev_switch_queues(pf, FALSE);
1539
1540         /* un-map queues with interrupt registers */
1541         i40e_vsi_disable_queues_intr(main_vsi);
1542         i40e_vsi_queues_unbind_intr(main_vsi);
1543
1544         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1545                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1546                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1547         }
1548
1549         if (pf->fdir.fdir_vsi) {
1550                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1551                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1552         }
1553         /* Clear all queues and release memory */
1554         i40e_dev_clear_queues(dev);
1555
1556         /* Set link down */
1557         i40e_dev_set_link_down(dev);
1558
1559         /* Remove all mirror rules */
1560         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1561                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1562                 rte_free(p_mirror);
1563         }
1564         pf->nb_mirror_rule = 0;
1565
1566         if (!rte_intr_allow_others(intr_handle))
1567                 /* resume to the default handler */
1568                 rte_intr_callback_register(intr_handle,
1569                                            i40e_dev_interrupt_handler,
1570                                            (void *)dev);
1571
1572         /* Clean datapath event and queue/vec mapping */
1573         rte_intr_efd_disable(intr_handle);
1574         if (intr_handle->intr_vec) {
1575                 rte_free(intr_handle->intr_vec);
1576                 intr_handle->intr_vec = NULL;
1577         }
1578 }
1579
1580 static void
1581 i40e_dev_close(struct rte_eth_dev *dev)
1582 {
1583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         uint32_t reg;
1586         int i;
1587
1588         PMD_INIT_FUNC_TRACE();
1589
1590         i40e_dev_stop(dev);
1591         hw->adapter_stopped = 1;
1592         i40e_dev_free_queues(dev);
1593
1594         /* Disable interrupt */
1595         i40e_pf_disable_irq0(hw);
1596         rte_intr_disable(&(dev->pci_dev->intr_handle));
1597
1598         /* shutdown and destroy the HMC */
1599         i40e_shutdown_lan_hmc(hw);
1600
1601         /* release all the existing VSIs and VEBs */
1602         i40e_fdir_teardown(pf);
1603         i40e_vsi_release(pf->main_vsi);
1604
1605         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1606                 i40e_vsi_release(pf->vmdq[i].vsi);
1607                 pf->vmdq[i].vsi = NULL;
1608         }
1609
1610         rte_free(pf->vmdq);
1611         pf->vmdq = NULL;
1612
1613         /* shutdown the adminq */
1614         i40e_aq_queue_shutdown(hw, true);
1615         i40e_shutdown_adminq(hw);
1616
1617         i40e_res_pool_destroy(&pf->qp_pool);
1618         i40e_res_pool_destroy(&pf->msix_pool);
1619
1620         /* force a PF reset to clean anything leftover */
1621         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1622         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1623                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1624         I40E_WRITE_FLUSH(hw);
1625 }
1626
1627 static void
1628 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1629 {
1630         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1631         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632         struct i40e_vsi *vsi = pf->main_vsi;
1633         int status;
1634
1635         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1636                                                         true, NULL);
1637         if (status != I40E_SUCCESS)
1638                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1639
1640         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1641                                                         TRUE, NULL);
1642         if (status != I40E_SUCCESS)
1643                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1644
1645 }
1646
1647 static void
1648 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1649 {
1650         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1651         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652         struct i40e_vsi *vsi = pf->main_vsi;
1653         int status;
1654
1655         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1656                                                         false, NULL);
1657         if (status != I40E_SUCCESS)
1658                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1659
1660         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1661                                                         false, NULL);
1662         if (status != I40E_SUCCESS)
1663                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1664 }
1665
1666 static void
1667 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1668 {
1669         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1670         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1671         struct i40e_vsi *vsi = pf->main_vsi;
1672         int ret;
1673
1674         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1675         if (ret != I40E_SUCCESS)
1676                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1677 }
1678
1679 static void
1680 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1681 {
1682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         struct i40e_vsi *vsi = pf->main_vsi;
1685         int ret;
1686
1687         if (dev->data->promiscuous == 1)
1688                 return; /* must remain in all_multicast mode */
1689
1690         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1691                                 vsi->seid, FALSE, NULL);
1692         if (ret != I40E_SUCCESS)
1693                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1694 }
1695
1696 /*
1697  * Set device link up.
1698  */
1699 static int
1700 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1701 {
1702         /* re-apply link speed setting */
1703         return i40e_apply_link_speed(dev);
1704 }
1705
1706 /*
1707  * Set device link down.
1708  */
1709 static int
1710 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1711 {
1712         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1713         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715
1716         return i40e_phy_conf_link(hw, abilities, speed);
1717 }
1718
1719 int
1720 i40e_dev_link_update(struct rte_eth_dev *dev,
1721                      int wait_to_complete)
1722 {
1723 #define CHECK_INTERVAL 100  /* 100ms */
1724 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         struct i40e_link_status link_status;
1727         struct rte_eth_link link, old;
1728         int status;
1729         unsigned rep_cnt = MAX_REPEAT_TIME;
1730
1731         memset(&link, 0, sizeof(link));
1732         memset(&old, 0, sizeof(old));
1733         memset(&link_status, 0, sizeof(link_status));
1734         rte_i40e_dev_atomic_read_link_status(dev, &old);
1735
1736         do {
1737                 /* Get link status information from hardware */
1738                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1739                 if (status != I40E_SUCCESS) {
1740                         link.link_speed = ETH_LINK_SPEED_100;
1741                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1742                         PMD_DRV_LOG(ERR, "Failed to get link info");
1743                         goto out;
1744                 }
1745
1746                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1747                 if (!wait_to_complete)
1748                         break;
1749
1750                 rte_delay_ms(CHECK_INTERVAL);
1751         } while (!link.link_status && rep_cnt--);
1752
1753         if (!link.link_status)
1754                 goto out;
1755
1756         /* i40e uses full duplex only */
1757         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1758
1759         /* Parse the link status */
1760         switch (link_status.link_speed) {
1761         case I40E_LINK_SPEED_100MB:
1762                 link.link_speed = ETH_LINK_SPEED_100;
1763                 break;
1764         case I40E_LINK_SPEED_1GB:
1765                 link.link_speed = ETH_LINK_SPEED_1000;
1766                 break;
1767         case I40E_LINK_SPEED_10GB:
1768                 link.link_speed = ETH_LINK_SPEED_10G;
1769                 break;
1770         case I40E_LINK_SPEED_20GB:
1771                 link.link_speed = ETH_LINK_SPEED_20G;
1772                 break;
1773         case I40E_LINK_SPEED_40GB:
1774                 link.link_speed = ETH_LINK_SPEED_40G;
1775                 break;
1776         default:
1777                 link.link_speed = ETH_LINK_SPEED_100;
1778                 break;
1779         }
1780
1781 out:
1782         rte_i40e_dev_atomic_write_link_status(dev, &link);
1783         if (link.link_status == old.link_status)
1784                 return -1;
1785
1786         return 0;
1787 }
1788
1789 /* Get all the statistics of a VSI */
1790 void
1791 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1792 {
1793         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1794         struct i40e_eth_stats *nes = &vsi->eth_stats;
1795         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1796         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1797
1798         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1799                             vsi->offset_loaded, &oes->rx_bytes,
1800                             &nes->rx_bytes);
1801         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1802                             vsi->offset_loaded, &oes->rx_unicast,
1803                             &nes->rx_unicast);
1804         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1805                             vsi->offset_loaded, &oes->rx_multicast,
1806                             &nes->rx_multicast);
1807         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1808                             vsi->offset_loaded, &oes->rx_broadcast,
1809                             &nes->rx_broadcast);
1810         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1811                             &oes->rx_discards, &nes->rx_discards);
1812         /* GLV_REPC not supported */
1813         /* GLV_RMPC not supported */
1814         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1815                             &oes->rx_unknown_protocol,
1816                             &nes->rx_unknown_protocol);
1817         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1818                             vsi->offset_loaded, &oes->tx_bytes,
1819                             &nes->tx_bytes);
1820         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1821                             vsi->offset_loaded, &oes->tx_unicast,
1822                             &nes->tx_unicast);
1823         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1824                             vsi->offset_loaded, &oes->tx_multicast,
1825                             &nes->tx_multicast);
1826         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1827                             vsi->offset_loaded,  &oes->tx_broadcast,
1828                             &nes->tx_broadcast);
1829         /* GLV_TDPC not supported */
1830         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1831                             &oes->tx_errors, &nes->tx_errors);
1832         vsi->offset_loaded = true;
1833
1834         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1835                     vsi->vsi_id);
1836         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1837         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1838         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1839         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1840         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1841         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1842                     nes->rx_unknown_protocol);
1843         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1844         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1845         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1846         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1847         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1848         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1849         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1850                     vsi->vsi_id);
1851 }
1852
1853 static void
1854 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1855 {
1856         unsigned int i;
1857         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1858         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1859         /* Get statistics of struct i40e_eth_stats */
1860         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1861                             I40E_GLPRT_GORCL(hw->port),
1862                             pf->offset_loaded, &os->eth.rx_bytes,
1863                             &ns->eth.rx_bytes);
1864         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1865                             I40E_GLPRT_UPRCL(hw->port),
1866                             pf->offset_loaded, &os->eth.rx_unicast,
1867                             &ns->eth.rx_unicast);
1868         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1869                             I40E_GLPRT_MPRCL(hw->port),
1870                             pf->offset_loaded, &os->eth.rx_multicast,
1871                             &ns->eth.rx_multicast);
1872         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1873                             I40E_GLPRT_BPRCL(hw->port),
1874                             pf->offset_loaded, &os->eth.rx_broadcast,
1875                             &ns->eth.rx_broadcast);
1876         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1877                             pf->offset_loaded, &os->eth.rx_discards,
1878                             &ns->eth.rx_discards);
1879         /* GLPRT_REPC not supported */
1880         /* GLPRT_RMPC not supported */
1881         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1882                             pf->offset_loaded,
1883                             &os->eth.rx_unknown_protocol,
1884                             &ns->eth.rx_unknown_protocol);
1885         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1886                             I40E_GLPRT_GOTCL(hw->port),
1887                             pf->offset_loaded, &os->eth.tx_bytes,
1888                             &ns->eth.tx_bytes);
1889         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1890                             I40E_GLPRT_UPTCL(hw->port),
1891                             pf->offset_loaded, &os->eth.tx_unicast,
1892                             &ns->eth.tx_unicast);
1893         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1894                             I40E_GLPRT_MPTCL(hw->port),
1895                             pf->offset_loaded, &os->eth.tx_multicast,
1896                             &ns->eth.tx_multicast);
1897         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1898                             I40E_GLPRT_BPTCL(hw->port),
1899                             pf->offset_loaded, &os->eth.tx_broadcast,
1900                             &ns->eth.tx_broadcast);
1901         /* GLPRT_TEPC not supported */
1902
1903         /* additional port specific stats */
1904         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1905                             pf->offset_loaded, &os->tx_dropped_link_down,
1906                             &ns->tx_dropped_link_down);
1907         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1908                             pf->offset_loaded, &os->crc_errors,
1909                             &ns->crc_errors);
1910         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1911                             pf->offset_loaded, &os->illegal_bytes,
1912                             &ns->illegal_bytes);
1913         /* GLPRT_ERRBC not supported */
1914         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1915                             pf->offset_loaded, &os->mac_local_faults,
1916                             &ns->mac_local_faults);
1917         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1918                             pf->offset_loaded, &os->mac_remote_faults,
1919                             &ns->mac_remote_faults);
1920         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1921                             pf->offset_loaded, &os->rx_length_errors,
1922                             &ns->rx_length_errors);
1923         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1924                             pf->offset_loaded, &os->link_xon_rx,
1925                             &ns->link_xon_rx);
1926         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1927                             pf->offset_loaded, &os->link_xoff_rx,
1928                             &ns->link_xoff_rx);
1929         for (i = 0; i < 8; i++) {
1930                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1931                                     pf->offset_loaded,
1932                                     &os->priority_xon_rx[i],
1933                                     &ns->priority_xon_rx[i]);
1934                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1935                                     pf->offset_loaded,
1936                                     &os->priority_xoff_rx[i],
1937                                     &ns->priority_xoff_rx[i]);
1938         }
1939         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1940                             pf->offset_loaded, &os->link_xon_tx,
1941                             &ns->link_xon_tx);
1942         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1943                             pf->offset_loaded, &os->link_xoff_tx,
1944                             &ns->link_xoff_tx);
1945         for (i = 0; i < 8; i++) {
1946                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1947                                     pf->offset_loaded,
1948                                     &os->priority_xon_tx[i],
1949                                     &ns->priority_xon_tx[i]);
1950                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1951                                     pf->offset_loaded,
1952                                     &os->priority_xoff_tx[i],
1953                                     &ns->priority_xoff_tx[i]);
1954                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1955                                     pf->offset_loaded,
1956                                     &os->priority_xon_2_xoff[i],
1957                                     &ns->priority_xon_2_xoff[i]);
1958         }
1959         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1960                             I40E_GLPRT_PRC64L(hw->port),
1961                             pf->offset_loaded, &os->rx_size_64,
1962                             &ns->rx_size_64);
1963         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1964                             I40E_GLPRT_PRC127L(hw->port),
1965                             pf->offset_loaded, &os->rx_size_127,
1966                             &ns->rx_size_127);
1967         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1968                             I40E_GLPRT_PRC255L(hw->port),
1969                             pf->offset_loaded, &os->rx_size_255,
1970                             &ns->rx_size_255);
1971         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1972                             I40E_GLPRT_PRC511L(hw->port),
1973                             pf->offset_loaded, &os->rx_size_511,
1974                             &ns->rx_size_511);
1975         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1976                             I40E_GLPRT_PRC1023L(hw->port),
1977                             pf->offset_loaded, &os->rx_size_1023,
1978                             &ns->rx_size_1023);
1979         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1980                             I40E_GLPRT_PRC1522L(hw->port),
1981                             pf->offset_loaded, &os->rx_size_1522,
1982                             &ns->rx_size_1522);
1983         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1984                             I40E_GLPRT_PRC9522L(hw->port),
1985                             pf->offset_loaded, &os->rx_size_big,
1986                             &ns->rx_size_big);
1987         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1988                             pf->offset_loaded, &os->rx_undersize,
1989                             &ns->rx_undersize);
1990         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1991                             pf->offset_loaded, &os->rx_fragments,
1992                             &ns->rx_fragments);
1993         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1994                             pf->offset_loaded, &os->rx_oversize,
1995                             &ns->rx_oversize);
1996         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1997                             pf->offset_loaded, &os->rx_jabber,
1998                             &ns->rx_jabber);
1999         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2000                             I40E_GLPRT_PTC64L(hw->port),
2001                             pf->offset_loaded, &os->tx_size_64,
2002                             &ns->tx_size_64);
2003         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2004                             I40E_GLPRT_PTC127L(hw->port),
2005                             pf->offset_loaded, &os->tx_size_127,
2006                             &ns->tx_size_127);
2007         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2008                             I40E_GLPRT_PTC255L(hw->port),
2009                             pf->offset_loaded, &os->tx_size_255,
2010                             &ns->tx_size_255);
2011         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2012                             I40E_GLPRT_PTC511L(hw->port),
2013                             pf->offset_loaded, &os->tx_size_511,
2014                             &ns->tx_size_511);
2015         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2016                             I40E_GLPRT_PTC1023L(hw->port),
2017                             pf->offset_loaded, &os->tx_size_1023,
2018                             &ns->tx_size_1023);
2019         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2020                             I40E_GLPRT_PTC1522L(hw->port),
2021                             pf->offset_loaded, &os->tx_size_1522,
2022                             &ns->tx_size_1522);
2023         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2024                             I40E_GLPRT_PTC9522L(hw->port),
2025                             pf->offset_loaded, &os->tx_size_big,
2026                             &ns->tx_size_big);
2027         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2028                            pf->offset_loaded,
2029                            &os->fd_sb_match, &ns->fd_sb_match);
2030         /* GLPRT_MSPDC not supported */
2031         /* GLPRT_XEC not supported */
2032
2033         pf->offset_loaded = true;
2034
2035         if (pf->main_vsi)
2036                 i40e_update_vsi_stats(pf->main_vsi);
2037 }
2038
2039 /* Get all statistics of a port */
2040 static void
2041 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2042 {
2043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2046         unsigned i;
2047
2048         /* call read registers - updates values, now write them to struct */
2049         i40e_read_stats_registers(pf, hw);
2050
2051         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2052                         pf->main_vsi->eth_stats.rx_multicast +
2053                         pf->main_vsi->eth_stats.rx_broadcast -
2054                         pf->main_vsi->eth_stats.rx_discards;
2055         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2056                         pf->main_vsi->eth_stats.tx_multicast +
2057                         pf->main_vsi->eth_stats.tx_broadcast;
2058         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
2059         stats->obytes   = pf->main_vsi->eth_stats.tx_bytes;
2060         stats->oerrors  = ns->eth.tx_errors +
2061                         pf->main_vsi->eth_stats.tx_errors;
2062         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2063         stats->fdirmatch = ns->fd_sb_match;
2064
2065         /* Rx Errors */
2066         stats->ibadcrc  = ns->crc_errors;
2067         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
2068                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2069         stats->imissed  = ns->eth.rx_discards +
2070                         pf->main_vsi->eth_stats.rx_discards;
2071         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
2072
2073         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2074         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2075         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2076         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2077         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2078         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2079         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2080                     ns->eth.rx_unknown_protocol);
2081         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2082         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2083         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2084         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2085         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2086         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2087
2088         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2089                     ns->tx_dropped_link_down);
2090         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2091         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2092                     ns->illegal_bytes);
2093         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2094         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2095                     ns->mac_local_faults);
2096         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2097                     ns->mac_remote_faults);
2098         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2099                     ns->rx_length_errors);
2100         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2101         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2102         for (i = 0; i < 8; i++) {
2103                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2104                                 i, ns->priority_xon_rx[i]);
2105                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2106                                 i, ns->priority_xoff_rx[i]);
2107         }
2108         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2109         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2110         for (i = 0; i < 8; i++) {
2111                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2112                                 i, ns->priority_xon_tx[i]);
2113                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2114                                 i, ns->priority_xoff_tx[i]);
2115                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2116                                 i, ns->priority_xon_2_xoff[i]);
2117         }
2118         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2119         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2120         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2121         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2122         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2123         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2124         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2125         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2126         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2127         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2128         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2129         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2130         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2131         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2132         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2133         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2134         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2135         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2136         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2137                         ns->mac_short_packet_dropped);
2138         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2139                     ns->checksum_error);
2140         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2141         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2142 }
2143
2144 /* Reset the statistics */
2145 static void
2146 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2147 {
2148         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2149         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150
2151         /* Mark PF and VSI stats to update the offset, aka "reset" */
2152         pf->offset_loaded = false;
2153         if (pf->main_vsi)
2154                 pf->main_vsi->offset_loaded = false;
2155
2156         /* read the stats, reading current register values into offset */
2157         i40e_read_stats_registers(pf, hw);
2158 }
2159
2160 static uint32_t
2161 i40e_xstats_calc_num(void)
2162 {
2163         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2164                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2165                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2166 }
2167
2168 static int
2169 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2170                     unsigned n)
2171 {
2172         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2173         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2174         unsigned i, count, prio;
2175         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2176
2177         count = i40e_xstats_calc_num();
2178         if (n < count)
2179                 return count;
2180
2181         i40e_read_stats_registers(pf, hw);
2182
2183         if (xstats == NULL)
2184                 return 0;
2185
2186         count = 0;
2187
2188         /* Get stats from i40e_eth_stats struct */
2189         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2190                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2191                          "%s", rte_i40e_stats_strings[i].name);
2192                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2193                         rte_i40e_stats_strings[i].offset);
2194                 count++;
2195         }
2196
2197         /* Get individiual stats from i40e_hw_port struct */
2198         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2199                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2200                          "%s", rte_i40e_hw_port_strings[i].name);
2201                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2202                                 rte_i40e_hw_port_strings[i].offset);
2203                 count++;
2204         }
2205
2206         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2207                 for (prio = 0; prio < 8; prio++) {
2208                         snprintf(xstats[count].name,
2209                                  sizeof(xstats[count].name),
2210                                  "rx_priority%u_%s", prio,
2211                                  rte_i40e_rxq_prio_strings[i].name);
2212                         xstats[count].value =
2213                                 *(uint64_t *)(((char *)hw_stats) +
2214                                 rte_i40e_rxq_prio_strings[i].offset +
2215                                 (sizeof(uint64_t) * prio));
2216                         count++;
2217                 }
2218         }
2219
2220         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2221                 for (prio = 0; prio < 8; prio++) {
2222                         snprintf(xstats[count].name,
2223                                  sizeof(xstats[count].name),
2224                                  "tx_priority%u_%s", prio,
2225                                  rte_i40e_txq_prio_strings[i].name);
2226                         xstats[count].value =
2227                                 *(uint64_t *)(((char *)hw_stats) +
2228                                 rte_i40e_txq_prio_strings[i].offset +
2229                                 (sizeof(uint64_t) * prio));
2230                         count++;
2231                 }
2232         }
2233
2234         return count;
2235 }
2236
2237 static int
2238 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2239                                  __rte_unused uint16_t queue_id,
2240                                  __rte_unused uint8_t stat_idx,
2241                                  __rte_unused uint8_t is_rx)
2242 {
2243         PMD_INIT_FUNC_TRACE();
2244
2245         return -ENOSYS;
2246 }
2247
2248 static void
2249 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2250 {
2251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2252         struct i40e_vsi *vsi = pf->main_vsi;
2253
2254         dev_info->max_rx_queues = vsi->nb_qps;
2255         dev_info->max_tx_queues = vsi->nb_qps;
2256         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2257         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2258         dev_info->max_mac_addrs = vsi->max_macaddrs;
2259         dev_info->max_vfs = dev->pci_dev->max_vfs;
2260         dev_info->rx_offload_capa =
2261                 DEV_RX_OFFLOAD_VLAN_STRIP |
2262                 DEV_RX_OFFLOAD_QINQ_STRIP |
2263                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2264                 DEV_RX_OFFLOAD_UDP_CKSUM |
2265                 DEV_RX_OFFLOAD_TCP_CKSUM;
2266         dev_info->tx_offload_capa =
2267                 DEV_TX_OFFLOAD_VLAN_INSERT |
2268                 DEV_TX_OFFLOAD_QINQ_INSERT |
2269                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2270                 DEV_TX_OFFLOAD_UDP_CKSUM |
2271                 DEV_TX_OFFLOAD_TCP_CKSUM |
2272                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2273                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2274                 DEV_TX_OFFLOAD_TCP_TSO;
2275         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2276                                                 sizeof(uint32_t);
2277         dev_info->reta_size = pf->hash_lut_size;
2278         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2279
2280         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2281                 .rx_thresh = {
2282                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2283                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2284                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2285                 },
2286                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2287                 .rx_drop_en = 0,
2288         };
2289
2290         dev_info->default_txconf = (struct rte_eth_txconf) {
2291                 .tx_thresh = {
2292                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2293                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2294                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2295                 },
2296                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2297                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2298                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2299                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2300         };
2301
2302         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2303                 .nb_max = I40E_MAX_RING_DESC,
2304                 .nb_min = I40E_MIN_RING_DESC,
2305                 .nb_align = I40E_ALIGN_RING_DESC,
2306         };
2307
2308         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2309                 .nb_max = I40E_MAX_RING_DESC,
2310                 .nb_min = I40E_MIN_RING_DESC,
2311                 .nb_align = I40E_ALIGN_RING_DESC,
2312         };
2313
2314         if (pf->flags & I40E_FLAG_VMDQ) {
2315                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2316                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2317                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2318                                                 pf->max_nb_vmdq_vsi;
2319                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2320                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2321                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2322         }
2323 }
2324
2325 static int
2326 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2327 {
2328         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2329         struct i40e_vsi *vsi = pf->main_vsi;
2330         PMD_INIT_FUNC_TRACE();
2331
2332         if (on)
2333                 return i40e_vsi_add_vlan(vsi, vlan_id);
2334         else
2335                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2336 }
2337
2338 static void
2339 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2340                    __rte_unused uint16_t tpid)
2341 {
2342         PMD_INIT_FUNC_TRACE();
2343 }
2344
2345 static void
2346 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2347 {
2348         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2349         struct i40e_vsi *vsi = pf->main_vsi;
2350
2351         if (mask & ETH_VLAN_STRIP_MASK) {
2352                 /* Enable or disable VLAN stripping */
2353                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2354                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2355                 else
2356                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2357         }
2358
2359         if (mask & ETH_VLAN_EXTEND_MASK) {
2360                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2361                         i40e_vsi_config_double_vlan(vsi, TRUE);
2362                 else
2363                         i40e_vsi_config_double_vlan(vsi, FALSE);
2364         }
2365 }
2366
2367 static void
2368 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2369                           __rte_unused uint16_t queue,
2370                           __rte_unused int on)
2371 {
2372         PMD_INIT_FUNC_TRACE();
2373 }
2374
2375 static int
2376 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2377 {
2378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2379         struct i40e_vsi *vsi = pf->main_vsi;
2380         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2381         struct i40e_vsi_vlan_pvid_info info;
2382
2383         memset(&info, 0, sizeof(info));
2384         info.on = on;
2385         if (info.on)
2386                 info.config.pvid = pvid;
2387         else {
2388                 info.config.reject.tagged =
2389                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2390                 info.config.reject.untagged =
2391                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2392         }
2393
2394         return i40e_vsi_vlan_pvid_set(vsi, &info);
2395 }
2396
2397 static int
2398 i40e_dev_led_on(struct rte_eth_dev *dev)
2399 {
2400         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2401         uint32_t mode = i40e_led_get(hw);
2402
2403         if (mode == 0)
2404                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2405
2406         return 0;
2407 }
2408
2409 static int
2410 i40e_dev_led_off(struct rte_eth_dev *dev)
2411 {
2412         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413         uint32_t mode = i40e_led_get(hw);
2414
2415         if (mode != 0)
2416                 i40e_led_set(hw, 0, false);
2417
2418         return 0;
2419 }
2420
2421 static int
2422 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2423 {
2424         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2426
2427         fc_conf->pause_time = pf->fc_conf.pause_time;
2428         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2429         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2430
2431          /* Return current mode according to actual setting*/
2432         switch (hw->fc.current_mode) {
2433         case I40E_FC_FULL:
2434                 fc_conf->mode = RTE_FC_FULL;
2435                 break;
2436         case I40E_FC_TX_PAUSE:
2437                 fc_conf->mode = RTE_FC_TX_PAUSE;
2438                 break;
2439         case I40E_FC_RX_PAUSE:
2440                 fc_conf->mode = RTE_FC_RX_PAUSE;
2441                 break;
2442         case I40E_FC_NONE:
2443         default:
2444                 fc_conf->mode = RTE_FC_NONE;
2445         };
2446
2447         return 0;
2448 }
2449
2450 static int
2451 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2452 {
2453         uint32_t mflcn_reg, fctrl_reg, reg;
2454         uint32_t max_high_water;
2455         uint8_t i, aq_failure;
2456         int err;
2457         struct i40e_hw *hw;
2458         struct i40e_pf *pf;
2459         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2460                 [RTE_FC_NONE] = I40E_FC_NONE,
2461                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2462                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2463                 [RTE_FC_FULL] = I40E_FC_FULL
2464         };
2465
2466         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2467
2468         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2469         if ((fc_conf->high_water > max_high_water) ||
2470                         (fc_conf->high_water < fc_conf->low_water)) {
2471                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2472                         "High_water must <= %d.", max_high_water);
2473                 return -EINVAL;
2474         }
2475
2476         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2478         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2479
2480         pf->fc_conf.pause_time = fc_conf->pause_time;
2481         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2482         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2483
2484         PMD_INIT_FUNC_TRACE();
2485
2486         /* All the link flow control related enable/disable register
2487          * configuration is handle by the F/W
2488          */
2489         err = i40e_set_fc(hw, &aq_failure, true);
2490         if (err < 0)
2491                 return -ENOSYS;
2492
2493         if (i40e_is_40G_device(hw->device_id)) {
2494                 /* Configure flow control refresh threshold,
2495                  * the value for stat_tx_pause_refresh_timer[8]
2496                  * is used for global pause operation.
2497                  */
2498
2499                 I40E_WRITE_REG(hw,
2500                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2501                                pf->fc_conf.pause_time);
2502
2503                 /* configure the timer value included in transmitted pause
2504                  * frame,
2505                  * the value for stat_tx_pause_quanta[8] is used for global
2506                  * pause operation
2507                  */
2508                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2509                                pf->fc_conf.pause_time);
2510
2511                 fctrl_reg = I40E_READ_REG(hw,
2512                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2513
2514                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2515                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2516                 else
2517                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2518
2519                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2520                                fctrl_reg);
2521         } else {
2522                 /* Configure pause time (2 TCs per register) */
2523                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2524                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2525                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2526
2527                 /* Configure flow control refresh threshold value */
2528                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2529                                pf->fc_conf.pause_time / 2);
2530
2531                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2532
2533                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2534                  *depending on configuration
2535                  */
2536                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2537                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2538                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2539                 } else {
2540                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2541                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2542                 }
2543
2544                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2545         }
2546
2547         /* config the water marker both based on the packets and bytes */
2548         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2549                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2550                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2551         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2552                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2553                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2554         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2555                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2556                        << I40E_KILOSHIFT);
2557         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2558                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2559                        << I40E_KILOSHIFT);
2560
2561         I40E_WRITE_FLUSH(hw);
2562
2563         return 0;
2564 }
2565
2566 static int
2567 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2568                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2569 {
2570         PMD_INIT_FUNC_TRACE();
2571
2572         return -ENOSYS;
2573 }
2574
2575 /* Add a MAC address, and update filters */
2576 static void
2577 i40e_macaddr_add(struct rte_eth_dev *dev,
2578                  struct ether_addr *mac_addr,
2579                  __rte_unused uint32_t index,
2580                  uint32_t pool)
2581 {
2582         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2583         struct i40e_mac_filter_info mac_filter;
2584         struct i40e_vsi *vsi;
2585         int ret;
2586
2587         /* If VMDQ not enabled or configured, return */
2588         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2589                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2590                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2591                         pool);
2592                 return;
2593         }
2594
2595         if (pool > pf->nb_cfg_vmdq_vsi) {
2596                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2597                                 pool, pf->nb_cfg_vmdq_vsi);
2598                 return;
2599         }
2600
2601         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2602         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2603
2604         if (pool == 0)
2605                 vsi = pf->main_vsi;
2606         else
2607                 vsi = pf->vmdq[pool - 1].vsi;
2608
2609         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2610         if (ret != I40E_SUCCESS) {
2611                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2612                 return;
2613         }
2614 }
2615
2616 /* Remove a MAC address, and update filters */
2617 static void
2618 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2619 {
2620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2621         struct i40e_vsi *vsi;
2622         struct rte_eth_dev_data *data = dev->data;
2623         struct ether_addr *macaddr;
2624         int ret;
2625         uint32_t i;
2626         uint64_t pool_sel;
2627
2628         macaddr = &(data->mac_addrs[index]);
2629
2630         pool_sel = dev->data->mac_pool_sel[index];
2631
2632         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2633                 if (pool_sel & (1ULL << i)) {
2634                         if (i == 0)
2635                                 vsi = pf->main_vsi;
2636                         else {
2637                                 /* No VMDQ pool enabled or configured */
2638                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2639                                         (i > pf->nb_cfg_vmdq_vsi)) {
2640                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2641                                                         "/configured");
2642                                         return;
2643                                 }
2644                                 vsi = pf->vmdq[i - 1].vsi;
2645                         }
2646                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2647
2648                         if (ret) {
2649                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2650                                 return;
2651                         }
2652                 }
2653         }
2654 }
2655
2656 /* Set perfect match or hash match of MAC and VLAN for a VF */
2657 static int
2658 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2659                  struct rte_eth_mac_filter *filter,
2660                  bool add)
2661 {
2662         struct i40e_hw *hw;
2663         struct i40e_mac_filter_info mac_filter;
2664         struct ether_addr old_mac;
2665         struct ether_addr *new_mac;
2666         struct i40e_pf_vf *vf = NULL;
2667         uint16_t vf_id;
2668         int ret;
2669
2670         if (pf == NULL) {
2671                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2672                 return -EINVAL;
2673         }
2674         hw = I40E_PF_TO_HW(pf);
2675
2676         if (filter == NULL) {
2677                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2678                 return -EINVAL;
2679         }
2680
2681         new_mac = &filter->mac_addr;
2682
2683         if (is_zero_ether_addr(new_mac)) {
2684                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2685                 return -EINVAL;
2686         }
2687
2688         vf_id = filter->dst_id;
2689
2690         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2691                 PMD_DRV_LOG(ERR, "Invalid argument.");
2692                 return -EINVAL;
2693         }
2694         vf = &pf->vfs[vf_id];
2695
2696         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2697                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2698                 return -EINVAL;
2699         }
2700
2701         if (add) {
2702                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2703                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2704                                 ETHER_ADDR_LEN);
2705                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2706                                  ETHER_ADDR_LEN);
2707
2708                 mac_filter.filter_type = filter->filter_type;
2709                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2710                 if (ret != I40E_SUCCESS) {
2711                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2712                         return -1;
2713                 }
2714                 ether_addr_copy(new_mac, &pf->dev_addr);
2715         } else {
2716                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2717                                 ETHER_ADDR_LEN);
2718                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2719                 if (ret != I40E_SUCCESS) {
2720                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2721                         return -1;
2722                 }
2723
2724                 /* Clear device address as it has been removed */
2725                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2726                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2727         }
2728
2729         return 0;
2730 }
2731
2732 /* MAC filter handle */
2733 static int
2734 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2735                 void *arg)
2736 {
2737         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2738         struct rte_eth_mac_filter *filter;
2739         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2740         int ret = I40E_NOT_SUPPORTED;
2741
2742         filter = (struct rte_eth_mac_filter *)(arg);
2743
2744         switch (filter_op) {
2745         case RTE_ETH_FILTER_NOP:
2746                 ret = I40E_SUCCESS;
2747                 break;
2748         case RTE_ETH_FILTER_ADD:
2749                 i40e_pf_disable_irq0(hw);
2750                 if (filter->is_vf)
2751                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2752                 i40e_pf_enable_irq0(hw);
2753                 break;
2754         case RTE_ETH_FILTER_DELETE:
2755                 i40e_pf_disable_irq0(hw);
2756                 if (filter->is_vf)
2757                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2758                 i40e_pf_enable_irq0(hw);
2759                 break;
2760         default:
2761                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2762                 ret = I40E_ERR_PARAM;
2763                 break;
2764         }
2765
2766         return ret;
2767 }
2768
2769 static int
2770 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2771 {
2772         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2773         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2774         int ret;
2775
2776         if (!lut)
2777                 return -EINVAL;
2778
2779         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2780                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2781                                           lut, lut_size);
2782                 if (ret) {
2783                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2784                         return ret;
2785                 }
2786         } else {
2787                 uint32_t *lut_dw = (uint32_t *)lut;
2788                 uint16_t i, lut_size_dw = lut_size / 4;
2789
2790                 for (i = 0; i < lut_size_dw; i++)
2791                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2792         }
2793
2794         return 0;
2795 }
2796
2797 static int
2798 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2799 {
2800         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2801         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2802         int ret;
2803
2804         if (!vsi || !lut)
2805                 return -EINVAL;
2806
2807         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2808                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2809                                           lut, lut_size);
2810                 if (ret) {
2811                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2812                         return ret;
2813                 }
2814         } else {
2815                 uint32_t *lut_dw = (uint32_t *)lut;
2816                 uint16_t i, lut_size_dw = lut_size / 4;
2817
2818                 for (i = 0; i < lut_size_dw; i++)
2819                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2820                 I40E_WRITE_FLUSH(hw);
2821         }
2822
2823         return 0;
2824 }
2825
2826 static int
2827 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2828                          struct rte_eth_rss_reta_entry64 *reta_conf,
2829                          uint16_t reta_size)
2830 {
2831         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2832         uint16_t i, lut_size = pf->hash_lut_size;
2833         uint16_t idx, shift;
2834         uint8_t *lut;
2835         int ret;
2836
2837         if (reta_size != lut_size ||
2838                 reta_size > ETH_RSS_RETA_SIZE_512) {
2839                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2840                         "(%d) doesn't match the number hardware can supported "
2841                                         "(%d)\n", reta_size, lut_size);
2842                 return -EINVAL;
2843         }
2844
2845         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2846         if (!lut) {
2847                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2848                 return -ENOMEM;
2849         }
2850         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2851         if (ret)
2852                 goto out;
2853         for (i = 0; i < reta_size; i++) {
2854                 idx = i / RTE_RETA_GROUP_SIZE;
2855                 shift = i % RTE_RETA_GROUP_SIZE;
2856                 if (reta_conf[idx].mask & (1ULL << shift))
2857                         lut[i] = reta_conf[idx].reta[shift];
2858         }
2859         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2860
2861 out:
2862         rte_free(lut);
2863
2864         return ret;
2865 }
2866
2867 static int
2868 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2869                         struct rte_eth_rss_reta_entry64 *reta_conf,
2870                         uint16_t reta_size)
2871 {
2872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2873         uint16_t i, lut_size = pf->hash_lut_size;
2874         uint16_t idx, shift;
2875         uint8_t *lut;
2876         int ret;
2877
2878         if (reta_size != lut_size ||
2879                 reta_size > ETH_RSS_RETA_SIZE_512) {
2880                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2881                         "(%d) doesn't match the number hardware can supported "
2882                                         "(%d)\n", reta_size, lut_size);
2883                 return -EINVAL;
2884         }
2885
2886         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2887         if (!lut) {
2888                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2889                 return -ENOMEM;
2890         }
2891
2892         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2893         if (ret)
2894                 goto out;
2895         for (i = 0; i < reta_size; i++) {
2896                 idx = i / RTE_RETA_GROUP_SIZE;
2897                 shift = i % RTE_RETA_GROUP_SIZE;
2898                 if (reta_conf[idx].mask & (1ULL << shift))
2899                         reta_conf[idx].reta[shift] = lut[i];
2900         }
2901
2902 out:
2903         rte_free(lut);
2904
2905         return ret;
2906 }
2907
2908 /**
2909  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2910  * @hw:   pointer to the HW structure
2911  * @mem:  pointer to mem struct to fill out
2912  * @size: size of memory requested
2913  * @alignment: what to align the allocation to
2914  **/
2915 enum i40e_status_code
2916 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2917                         struct i40e_dma_mem *mem,
2918                         u64 size,
2919                         u32 alignment)
2920 {
2921         const struct rte_memzone *mz = NULL;
2922         char z_name[RTE_MEMZONE_NAMESIZE];
2923
2924         if (!mem)
2925                 return I40E_ERR_PARAM;
2926
2927         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2928 #ifdef RTE_LIBRTE_XEN_DOM0
2929         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2930                                          alignment, RTE_PGSIZE_2M);
2931 #else
2932         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2933                                          alignment);
2934 #endif
2935         if (!mz)
2936                 return I40E_ERR_NO_MEMORY;
2937
2938         mem->size = size;
2939         mem->va = mz->addr;
2940 #ifdef RTE_LIBRTE_XEN_DOM0
2941         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2942 #else
2943         mem->pa = mz->phys_addr;
2944 #endif
2945         mem->zone = (const void *)mz;
2946         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2947                     "%"PRIu64, mz->name, mem->pa);
2948
2949         return I40E_SUCCESS;
2950 }
2951
2952 /**
2953  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2954  * @hw:   pointer to the HW structure
2955  * @mem:  ptr to mem struct to free
2956  **/
2957 enum i40e_status_code
2958 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2959                     struct i40e_dma_mem *mem)
2960 {
2961         if (!mem)
2962                 return I40E_ERR_PARAM;
2963
2964         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2965                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2966                     mem->pa);
2967         rte_memzone_free((const struct rte_memzone *)mem->zone);
2968         mem->zone = NULL;
2969         mem->va = NULL;
2970         mem->pa = (u64)0;
2971
2972         return I40E_SUCCESS;
2973 }
2974
2975 /**
2976  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2977  * @hw:   pointer to the HW structure
2978  * @mem:  pointer to mem struct to fill out
2979  * @size: size of memory requested
2980  **/
2981 enum i40e_status_code
2982 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2983                          struct i40e_virt_mem *mem,
2984                          u32 size)
2985 {
2986         if (!mem)
2987                 return I40E_ERR_PARAM;
2988
2989         mem->size = size;
2990         mem->va = rte_zmalloc("i40e", size, 0);
2991
2992         if (mem->va)
2993                 return I40E_SUCCESS;
2994         else
2995                 return I40E_ERR_NO_MEMORY;
2996 }
2997
2998 /**
2999  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3000  * @hw:   pointer to the HW structure
3001  * @mem:  pointer to mem struct to free
3002  **/
3003 enum i40e_status_code
3004 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3005                      struct i40e_virt_mem *mem)
3006 {
3007         if (!mem)
3008                 return I40E_ERR_PARAM;
3009
3010         rte_free(mem->va);
3011         mem->va = NULL;
3012
3013         return I40E_SUCCESS;
3014 }
3015
3016 void
3017 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3018 {
3019         rte_spinlock_init(&sp->spinlock);
3020 }
3021
3022 void
3023 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3024 {
3025         rte_spinlock_lock(&sp->spinlock);
3026 }
3027
3028 void
3029 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3030 {
3031         rte_spinlock_unlock(&sp->spinlock);
3032 }
3033
3034 void
3035 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3036 {
3037         return;
3038 }
3039
3040 /**
3041  * Get the hardware capabilities, which will be parsed
3042  * and saved into struct i40e_hw.
3043  */
3044 static int
3045 i40e_get_cap(struct i40e_hw *hw)
3046 {
3047         struct i40e_aqc_list_capabilities_element_resp *buf;
3048         uint16_t len, size = 0;
3049         int ret;
3050
3051         /* Calculate a huge enough buff for saving response data temporarily */
3052         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3053                                                 I40E_MAX_CAP_ELE_NUM;
3054         buf = rte_zmalloc("i40e", len, 0);
3055         if (!buf) {
3056                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3057                 return I40E_ERR_NO_MEMORY;
3058         }
3059
3060         /* Get, parse the capabilities and save it to hw */
3061         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3062                         i40e_aqc_opc_list_func_capabilities, NULL);
3063         if (ret != I40E_SUCCESS)
3064                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3065
3066         /* Free the temporary buffer after being used */
3067         rte_free(buf);
3068
3069         return ret;
3070 }
3071
3072 static int
3073 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3074 {
3075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3076         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3077         uint16_t qp_count = 0, vsi_count = 0;
3078
3079         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3080                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3081                 return -EINVAL;
3082         }
3083         /* Add the parameter init for LFC */
3084         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3085         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3086         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3087
3088         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3089         pf->max_num_vsi = hw->func_caps.num_vsis;
3090         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3091         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3092         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3093
3094         /* FDir queue/VSI allocation */
3095         pf->fdir_qp_offset = 0;
3096         if (hw->func_caps.fd) {
3097                 pf->flags |= I40E_FLAG_FDIR;
3098                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3099         } else {
3100                 pf->fdir_nb_qps = 0;
3101         }
3102         qp_count += pf->fdir_nb_qps;
3103         vsi_count += 1;
3104
3105         /* LAN queue/VSI allocation */
3106         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3107         if (!hw->func_caps.rss) {
3108                 pf->lan_nb_qps = 1;
3109         } else {
3110                 pf->flags |= I40E_FLAG_RSS;
3111                 if (hw->mac.type == I40E_MAC_X722)
3112                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3113                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3114         }
3115         qp_count += pf->lan_nb_qps;
3116         vsi_count += 1;
3117
3118         /* VF queue/VSI allocation */
3119         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3120         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3121                 pf->flags |= I40E_FLAG_SRIOV;
3122                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3123                 pf->vf_num = dev->pci_dev->max_vfs;
3124                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3125                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3126                             pf->vf_nb_qps * pf->vf_num);
3127         } else {
3128                 pf->vf_nb_qps = 0;
3129                 pf->vf_num = 0;
3130         }
3131         qp_count += pf->vf_nb_qps * pf->vf_num;
3132         vsi_count += pf->vf_num;
3133
3134         /* VMDq queue/VSI allocation */
3135         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3136         pf->vmdq_nb_qps = 0;
3137         pf->max_nb_vmdq_vsi = 0;
3138         if (hw->func_caps.vmdq) {
3139                 if (qp_count < hw->func_caps.num_tx_qp &&
3140                         vsi_count < hw->func_caps.num_vsis) {
3141                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3142                                 qp_count) / pf->vmdq_nb_qp_max;
3143
3144                         /* Limit the maximum number of VMDq vsi to the maximum
3145                          * ethdev can support
3146                          */
3147                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3148                                 hw->func_caps.num_vsis - vsi_count);
3149                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3150                                 ETH_64_POOLS);
3151                         if (pf->max_nb_vmdq_vsi) {
3152                                 pf->flags |= I40E_FLAG_VMDQ;
3153                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3154                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3155                                             "per VMDQ VSI, in total %u queues",
3156                                             pf->max_nb_vmdq_vsi,
3157                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3158                                             pf->max_nb_vmdq_vsi);
3159                         } else {
3160                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3161                                             "VMDq");
3162                         }
3163                 } else {
3164                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3165                 }
3166         }
3167         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3168         vsi_count += pf->max_nb_vmdq_vsi;
3169
3170         if (hw->func_caps.dcb)
3171                 pf->flags |= I40E_FLAG_DCB;
3172
3173         if (qp_count > hw->func_caps.num_tx_qp) {
3174                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3175                             "the hardware maximum %u", qp_count,
3176                             hw->func_caps.num_tx_qp);
3177                 return -EINVAL;
3178         }
3179         if (vsi_count > hw->func_caps.num_vsis) {
3180                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3181                             "the hardware maximum %u", vsi_count,
3182                             hw->func_caps.num_vsis);
3183                 return -EINVAL;
3184         }
3185
3186         return 0;
3187 }
3188
3189 static int
3190 i40e_pf_get_switch_config(struct i40e_pf *pf)
3191 {
3192         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3193         struct i40e_aqc_get_switch_config_resp *switch_config;
3194         struct i40e_aqc_switch_config_element_resp *element;
3195         uint16_t start_seid = 0, num_reported;
3196         int ret;
3197
3198         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3199                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3200         if (!switch_config) {
3201                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3202                 return -ENOMEM;
3203         }
3204
3205         /* Get the switch configurations */
3206         ret = i40e_aq_get_switch_config(hw, switch_config,
3207                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3208         if (ret != I40E_SUCCESS) {
3209                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3210                 goto fail;
3211         }
3212         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3213         if (num_reported != 1) { /* The number should be 1 */
3214                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3215                 goto fail;
3216         }
3217
3218         /* Parse the switch configuration elements */
3219         element = &(switch_config->element[0]);
3220         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3221                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3222                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3223         } else
3224                 PMD_DRV_LOG(INFO, "Unknown element type");
3225
3226 fail:
3227         rte_free(switch_config);
3228
3229         return ret;
3230 }
3231
3232 static int
3233 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3234                         uint32_t num)
3235 {
3236         struct pool_entry *entry;
3237
3238         if (pool == NULL || num == 0)
3239                 return -EINVAL;
3240
3241         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3242         if (entry == NULL) {
3243                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3244                 return -ENOMEM;
3245         }
3246
3247         /* queue heap initialize */
3248         pool->num_free = num;
3249         pool->num_alloc = 0;
3250         pool->base = base;
3251         LIST_INIT(&pool->alloc_list);
3252         LIST_INIT(&pool->free_list);
3253
3254         /* Initialize element  */
3255         entry->base = 0;
3256         entry->len = num;
3257
3258         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3259         return 0;
3260 }
3261
3262 static void
3263 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3264 {
3265         struct pool_entry *entry;
3266
3267         if (pool == NULL)
3268                 return;
3269
3270         LIST_FOREACH(entry, &pool->alloc_list, next) {
3271                 LIST_REMOVE(entry, next);
3272                 rte_free(entry);
3273         }
3274
3275         LIST_FOREACH(entry, &pool->free_list, next) {
3276                 LIST_REMOVE(entry, next);
3277                 rte_free(entry);
3278         }
3279
3280         pool->num_free = 0;
3281         pool->num_alloc = 0;
3282         pool->base = 0;
3283         LIST_INIT(&pool->alloc_list);
3284         LIST_INIT(&pool->free_list);
3285 }
3286
3287 static int
3288 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3289                        uint32_t base)
3290 {
3291         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3292         uint32_t pool_offset;
3293         int insert;
3294
3295         if (pool == NULL) {
3296                 PMD_DRV_LOG(ERR, "Invalid parameter");
3297                 return -EINVAL;
3298         }
3299
3300         pool_offset = base - pool->base;
3301         /* Lookup in alloc list */
3302         LIST_FOREACH(entry, &pool->alloc_list, next) {
3303                 if (entry->base == pool_offset) {
3304                         valid_entry = entry;
3305                         LIST_REMOVE(entry, next);
3306                         break;
3307                 }
3308         }
3309
3310         /* Not find, return */
3311         if (valid_entry == NULL) {
3312                 PMD_DRV_LOG(ERR, "Failed to find entry");
3313                 return -EINVAL;
3314         }
3315
3316         /**
3317          * Found it, move it to free list  and try to merge.
3318          * In order to make merge easier, always sort it by qbase.
3319          * Find adjacent prev and last entries.
3320          */
3321         prev = next = NULL;
3322         LIST_FOREACH(entry, &pool->free_list, next) {
3323                 if (entry->base > valid_entry->base) {
3324                         next = entry;
3325                         break;
3326                 }
3327                 prev = entry;
3328         }
3329
3330         insert = 0;
3331         /* Try to merge with next one*/
3332         if (next != NULL) {
3333                 /* Merge with next one */
3334                 if (valid_entry->base + valid_entry->len == next->base) {
3335                         next->base = valid_entry->base;
3336                         next->len += valid_entry->len;
3337                         rte_free(valid_entry);
3338                         valid_entry = next;
3339                         insert = 1;
3340                 }
3341         }
3342
3343         if (prev != NULL) {
3344                 /* Merge with previous one */
3345                 if (prev->base + prev->len == valid_entry->base) {
3346                         prev->len += valid_entry->len;
3347                         /* If it merge with next one, remove next node */
3348                         if (insert == 1) {
3349                                 LIST_REMOVE(valid_entry, next);
3350                                 rte_free(valid_entry);
3351                         } else {
3352                                 rte_free(valid_entry);
3353                                 insert = 1;
3354                         }
3355                 }
3356         }
3357
3358         /* Not find any entry to merge, insert */
3359         if (insert == 0) {
3360                 if (prev != NULL)
3361                         LIST_INSERT_AFTER(prev, valid_entry, next);
3362                 else if (next != NULL)
3363                         LIST_INSERT_BEFORE(next, valid_entry, next);
3364                 else /* It's empty list, insert to head */
3365                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3366         }
3367
3368         pool->num_free += valid_entry->len;
3369         pool->num_alloc -= valid_entry->len;
3370
3371         return 0;
3372 }
3373
3374 static int
3375 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3376                        uint16_t num)
3377 {
3378         struct pool_entry *entry, *valid_entry;
3379
3380         if (pool == NULL || num == 0) {
3381                 PMD_DRV_LOG(ERR, "Invalid parameter");
3382                 return -EINVAL;
3383         }
3384
3385         if (pool->num_free < num) {
3386                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3387                             num, pool->num_free);
3388                 return -ENOMEM;
3389         }
3390
3391         valid_entry = NULL;
3392         /* Lookup  in free list and find most fit one */
3393         LIST_FOREACH(entry, &pool->free_list, next) {
3394                 if (entry->len >= num) {
3395                         /* Find best one */
3396                         if (entry->len == num) {
3397                                 valid_entry = entry;
3398                                 break;
3399                         }
3400                         if (valid_entry == NULL || valid_entry->len > entry->len)
3401                                 valid_entry = entry;
3402                 }
3403         }
3404
3405         /* Not find one to satisfy the request, return */
3406         if (valid_entry == NULL) {
3407                 PMD_DRV_LOG(ERR, "No valid entry found");
3408                 return -ENOMEM;
3409         }
3410         /**
3411          * The entry have equal queue number as requested,
3412          * remove it from alloc_list.
3413          */
3414         if (valid_entry->len == num) {
3415                 LIST_REMOVE(valid_entry, next);
3416         } else {
3417                 /**
3418                  * The entry have more numbers than requested,
3419                  * create a new entry for alloc_list and minus its
3420                  * queue base and number in free_list.
3421                  */
3422                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3423                 if (entry == NULL) {
3424                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3425                                     "resource pool");
3426                         return -ENOMEM;
3427                 }
3428                 entry->base = valid_entry->base;
3429                 entry->len = num;
3430                 valid_entry->base += num;
3431                 valid_entry->len -= num;
3432                 valid_entry = entry;
3433         }
3434
3435         /* Insert it into alloc list, not sorted */
3436         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3437
3438         pool->num_free -= valid_entry->len;
3439         pool->num_alloc += valid_entry->len;
3440
3441         return (valid_entry->base + pool->base);
3442 }
3443
3444 /**
3445  * bitmap_is_subset - Check whether src2 is subset of src1
3446  **/
3447 static inline int
3448 bitmap_is_subset(uint8_t src1, uint8_t src2)
3449 {
3450         return !((src1 ^ src2) & src2);
3451 }
3452
3453 static enum i40e_status_code
3454 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3455 {
3456         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3457
3458         /* If DCB is not supported, only default TC is supported */
3459         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3460                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3461                 return I40E_NOT_SUPPORTED;
3462         }
3463
3464         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3465                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3466                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3467                             enabled_tcmap);
3468                 return I40E_NOT_SUPPORTED;
3469         }
3470         return I40E_SUCCESS;
3471 }
3472
3473 int
3474 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3475                                 struct i40e_vsi_vlan_pvid_info *info)
3476 {
3477         struct i40e_hw *hw;
3478         struct i40e_vsi_context ctxt;
3479         uint8_t vlan_flags = 0;
3480         int ret;
3481
3482         if (vsi == NULL || info == NULL) {
3483                 PMD_DRV_LOG(ERR, "invalid parameters");
3484                 return I40E_ERR_PARAM;
3485         }
3486
3487         if (info->on) {
3488                 vsi->info.pvid = info->config.pvid;
3489                 /**
3490                  * If insert pvid is enabled, only tagged pkts are
3491                  * allowed to be sent out.
3492                  */
3493                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3494                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3495         } else {
3496                 vsi->info.pvid = 0;
3497                 if (info->config.reject.tagged == 0)
3498                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3499
3500                 if (info->config.reject.untagged == 0)
3501                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3502         }
3503         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3504                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3505         vsi->info.port_vlan_flags |= vlan_flags;
3506         vsi->info.valid_sections =
3507                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3508         memset(&ctxt, 0, sizeof(ctxt));
3509         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3510         ctxt.seid = vsi->seid;
3511
3512         hw = I40E_VSI_TO_HW(vsi);
3513         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3514         if (ret != I40E_SUCCESS)
3515                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3516
3517         return ret;
3518 }
3519
3520 static int
3521 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3522 {
3523         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3524         int i, ret;
3525         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3526
3527         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3528         if (ret != I40E_SUCCESS)
3529                 return ret;
3530
3531         if (!vsi->seid) {
3532                 PMD_DRV_LOG(ERR, "seid not valid");
3533                 return -EINVAL;
3534         }
3535
3536         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3537         tc_bw_data.tc_valid_bits = enabled_tcmap;
3538         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3539                 tc_bw_data.tc_bw_credits[i] =
3540                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3541
3542         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3543         if (ret != I40E_SUCCESS) {
3544                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3545                 return ret;
3546         }
3547
3548         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3549                                         sizeof(vsi->info.qs_handle));
3550         return I40E_SUCCESS;
3551 }
3552
3553 static enum i40e_status_code
3554 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3555                                  struct i40e_aqc_vsi_properties_data *info,
3556                                  uint8_t enabled_tcmap)
3557 {
3558         enum i40e_status_code ret;
3559         int i, total_tc = 0;
3560         uint16_t qpnum_per_tc, bsf, qp_idx;
3561
3562         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3563         if (ret != I40E_SUCCESS)
3564                 return ret;
3565
3566         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3567                 if (enabled_tcmap & (1 << i))
3568                         total_tc++;
3569         vsi->enabled_tc = enabled_tcmap;
3570
3571         /* Number of queues per enabled TC */
3572         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3573         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3574         bsf = rte_bsf32(qpnum_per_tc);
3575
3576         /* Adjust the queue number to actual queues that can be applied */
3577         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3578                 vsi->nb_qps = qpnum_per_tc * total_tc;
3579
3580         /**
3581          * Configure TC and queue mapping parameters, for enabled TC,
3582          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3583          * default queue will serve it.
3584          */
3585         qp_idx = 0;
3586         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3587                 if (vsi->enabled_tc & (1 << i)) {
3588                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3589                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3590                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3591                         qp_idx += qpnum_per_tc;
3592                 } else
3593                         info->tc_mapping[i] = 0;
3594         }
3595
3596         /* Associate queue number with VSI */
3597         if (vsi->type == I40E_VSI_SRIOV) {
3598                 info->mapping_flags |=
3599                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3600                 for (i = 0; i < vsi->nb_qps; i++)
3601                         info->queue_mapping[i] =
3602                                 rte_cpu_to_le_16(vsi->base_queue + i);
3603         } else {
3604                 info->mapping_flags |=
3605                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3606                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3607         }
3608         info->valid_sections |=
3609                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3610
3611         return I40E_SUCCESS;
3612 }
3613
3614 static int
3615 i40e_veb_release(struct i40e_veb *veb)
3616 {
3617         struct i40e_vsi *vsi;
3618         struct i40e_hw *hw;
3619
3620         if (veb == NULL || veb->associate_vsi == NULL)
3621                 return -EINVAL;
3622
3623         if (!TAILQ_EMPTY(&veb->head)) {
3624                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3625                 return -EACCES;
3626         }
3627
3628         vsi = veb->associate_vsi;
3629         hw = I40E_VSI_TO_HW(vsi);
3630
3631         vsi->uplink_seid = veb->uplink_seid;
3632         i40e_aq_delete_element(hw, veb->seid, NULL);
3633         rte_free(veb);
3634         vsi->veb = NULL;
3635         return I40E_SUCCESS;
3636 }
3637
3638 /* Setup a veb */
3639 static struct i40e_veb *
3640 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3641 {
3642         struct i40e_veb *veb;
3643         int ret;
3644         struct i40e_hw *hw;
3645
3646         if (NULL == pf || vsi == NULL) {
3647                 PMD_DRV_LOG(ERR, "veb setup failed, "
3648                             "associated VSI shouldn't null");
3649                 return NULL;
3650         }
3651         hw = I40E_PF_TO_HW(pf);
3652
3653         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3654         if (!veb) {
3655                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3656                 goto fail;
3657         }
3658
3659         veb->associate_vsi = vsi;
3660         TAILQ_INIT(&veb->head);
3661         veb->uplink_seid = vsi->uplink_seid;
3662
3663         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3664                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3665
3666         if (ret != I40E_SUCCESS) {
3667                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3668                             hw->aq.asq_last_status);
3669                 goto fail;
3670         }
3671
3672         /* get statistics index */
3673         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3674                                 &veb->stats_idx, NULL, NULL, NULL);
3675         if (ret != I40E_SUCCESS) {
3676                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3677                             hw->aq.asq_last_status);
3678                 goto fail;
3679         }
3680
3681         /* Get VEB bandwidth, to be implemented */
3682         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3683         vsi->uplink_seid = veb->seid;
3684
3685         return veb;
3686 fail:
3687         rte_free(veb);
3688         return NULL;
3689 }
3690
3691 int
3692 i40e_vsi_release(struct i40e_vsi *vsi)
3693 {
3694         struct i40e_pf *pf;
3695         struct i40e_hw *hw;
3696         struct i40e_vsi_list *vsi_list;
3697         int ret;
3698         struct i40e_mac_filter *f;
3699
3700         if (!vsi)
3701                 return I40E_SUCCESS;
3702
3703         pf = I40E_VSI_TO_PF(vsi);
3704         hw = I40E_VSI_TO_HW(vsi);
3705
3706         /* VSI has child to attach, release child first */
3707         if (vsi->veb) {
3708                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3709                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3710                                 return -1;
3711                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3712                 }
3713                 i40e_veb_release(vsi->veb);
3714         }
3715
3716         /* Remove all macvlan filters of the VSI */
3717         i40e_vsi_remove_all_macvlan_filter(vsi);
3718         TAILQ_FOREACH(f, &vsi->mac_list, next)
3719                 rte_free(f);
3720
3721         if (vsi->type != I40E_VSI_MAIN) {
3722                 /* Remove vsi from parent's sibling list */
3723                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3724                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3725                         return I40E_ERR_PARAM;
3726                 }
3727                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3728                                 &vsi->sib_vsi_list, list);
3729
3730                 /* Remove all switch element of the VSI */
3731                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3732                 if (ret != I40E_SUCCESS)
3733                         PMD_DRV_LOG(ERR, "Failed to delete element");
3734         }
3735         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3736
3737         if (vsi->type != I40E_VSI_SRIOV)
3738                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3739         rte_free(vsi);
3740
3741         return I40E_SUCCESS;
3742 }
3743
3744 static int
3745 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3746 {
3747         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3748         struct i40e_aqc_remove_macvlan_element_data def_filter;
3749         struct i40e_mac_filter_info filter;
3750         int ret;
3751
3752         if (vsi->type != I40E_VSI_MAIN)
3753                 return I40E_ERR_CONFIG;
3754         memset(&def_filter, 0, sizeof(def_filter));
3755         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3756                                         ETH_ADDR_LEN);
3757         def_filter.vlan_tag = 0;
3758         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3759                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3760         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3761         if (ret != I40E_SUCCESS) {
3762                 struct i40e_mac_filter *f;
3763                 struct ether_addr *mac;
3764
3765                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3766                             "macvlan filter");
3767                 /* It needs to add the permanent mac into mac list */
3768                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3769                 if (f == NULL) {
3770                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3771                         return I40E_ERR_NO_MEMORY;
3772                 }
3773                 mac = &f->mac_info.mac_addr;
3774                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3775                                 ETH_ADDR_LEN);
3776                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3777                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3778                 vsi->mac_num++;
3779
3780                 return ret;
3781         }
3782         (void)rte_memcpy(&filter.mac_addr,
3783                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3784         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3785         return i40e_vsi_add_mac(vsi, &filter);
3786 }
3787
3788 static int
3789 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3790 {
3791         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3792         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3793         struct i40e_hw *hw = &vsi->adapter->hw;
3794         i40e_status ret;
3795         int i;
3796
3797         memset(&bw_config, 0, sizeof(bw_config));
3798         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3799         if (ret != I40E_SUCCESS) {
3800                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3801                             hw->aq.asq_last_status);
3802                 return ret;
3803         }
3804
3805         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3806         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3807                                         &ets_sla_config, NULL);
3808         if (ret != I40E_SUCCESS) {
3809                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3810                             "configuration %u", hw->aq.asq_last_status);
3811                 return ret;
3812         }
3813
3814         /* Not store the info yet, just print out */
3815         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3816         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3817         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3818                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3819                             ets_sla_config.share_credits[i]);
3820                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3821                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3822                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3823                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3824                             (i * 4));
3825         }
3826
3827         return 0;
3828 }
3829
3830 /* Setup a VSI */
3831 struct i40e_vsi *
3832 i40e_vsi_setup(struct i40e_pf *pf,
3833                enum i40e_vsi_type type,
3834                struct i40e_vsi *uplink_vsi,
3835                uint16_t user_param)
3836 {
3837         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3838         struct i40e_vsi *vsi;
3839         struct i40e_mac_filter_info filter;
3840         int ret;
3841         struct i40e_vsi_context ctxt;
3842         struct ether_addr broadcast =
3843                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3844
3845         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3846                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3847                             "VSI link shouldn't be NULL");
3848                 return NULL;
3849         }
3850
3851         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3852                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3853                             "uplink VSI should be NULL");
3854                 return NULL;
3855         }
3856
3857         /* If uplink vsi didn't setup VEB, create one first */
3858         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3859                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3860
3861                 if (NULL == uplink_vsi->veb) {
3862                         PMD_DRV_LOG(ERR, "VEB setup failed");
3863                         return NULL;
3864                 }
3865         }
3866
3867         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3868         if (!vsi) {
3869                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3870                 return NULL;
3871         }
3872         TAILQ_INIT(&vsi->mac_list);
3873         vsi->type = type;
3874         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3875         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3876         vsi->parent_vsi = uplink_vsi;
3877         vsi->user_param = user_param;
3878         /* Allocate queues */
3879         switch (vsi->type) {
3880         case I40E_VSI_MAIN  :
3881                 vsi->nb_qps = pf->lan_nb_qps;
3882                 break;
3883         case I40E_VSI_SRIOV :
3884                 vsi->nb_qps = pf->vf_nb_qps;
3885                 break;
3886         case I40E_VSI_VMDQ2:
3887                 vsi->nb_qps = pf->vmdq_nb_qps;
3888                 break;
3889         case I40E_VSI_FDIR:
3890                 vsi->nb_qps = pf->fdir_nb_qps;
3891                 break;
3892         default:
3893                 goto fail_mem;
3894         }
3895         /*
3896          * The filter status descriptor is reported in rx queue 0,
3897          * while the tx queue for fdir filter programming has no
3898          * such constraints, can be non-zero queues.
3899          * To simplify it, choose FDIR vsi use queue 0 pair.
3900          * To make sure it will use queue 0 pair, queue allocation
3901          * need be done before this function is called
3902          */
3903         if (type != I40E_VSI_FDIR) {
3904                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3905                         if (ret < 0) {
3906                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3907                                                 vsi->seid, ret);
3908                                 goto fail_mem;
3909                         }
3910                         vsi->base_queue = ret;
3911         } else
3912                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3913
3914         /* VF has MSIX interrupt in VF range, don't allocate here */
3915         if (type == I40E_VSI_MAIN) {
3916                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3917                                           RTE_MIN(vsi->nb_qps,
3918                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3919                 if (ret < 0) {
3920                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3921                                     vsi->seid, ret);
3922                         goto fail_queue_alloc;
3923                 }
3924                 vsi->msix_intr = ret;
3925                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3926         } else if (type != I40E_VSI_SRIOV) {
3927                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3928                 if (ret < 0) {
3929                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3930                         goto fail_queue_alloc;
3931                 }
3932                 vsi->msix_intr = ret;
3933                 vsi->nb_msix = 1;
3934         } else {
3935                 vsi->msix_intr = 0;
3936                 vsi->nb_msix = 0;
3937         }
3938
3939         /* Add VSI */
3940         if (type == I40E_VSI_MAIN) {
3941                 /* For main VSI, no need to add since it's default one */
3942                 vsi->uplink_seid = pf->mac_seid;
3943                 vsi->seid = pf->main_vsi_seid;
3944                 /* Bind queues with specific MSIX interrupt */
3945                 /**
3946                  * Needs 2 interrupt at least, one for misc cause which will
3947                  * enabled from OS side, Another for queues binding the
3948                  * interrupt from device side only.
3949                  */
3950
3951                 /* Get default VSI parameters from hardware */
3952                 memset(&ctxt, 0, sizeof(ctxt));
3953                 ctxt.seid = vsi->seid;
3954                 ctxt.pf_num = hw->pf_id;
3955                 ctxt.uplink_seid = vsi->uplink_seid;
3956                 ctxt.vf_num = 0;
3957                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3958                 if (ret != I40E_SUCCESS) {
3959                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3960                         goto fail_msix_alloc;
3961                 }
3962                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3963                         sizeof(struct i40e_aqc_vsi_properties_data));
3964                 vsi->vsi_id = ctxt.vsi_number;
3965                 vsi->info.valid_sections = 0;
3966
3967                 /* Configure tc, enabled TC0 only */
3968                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3969                         I40E_SUCCESS) {
3970                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3971                         goto fail_msix_alloc;
3972                 }
3973
3974                 /* TC, queue mapping */
3975                 memset(&ctxt, 0, sizeof(ctxt));
3976                 vsi->info.valid_sections |=
3977                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3978                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3979                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3980                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3981                         sizeof(struct i40e_aqc_vsi_properties_data));
3982                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3983                                                 I40E_DEFAULT_TCMAP);
3984                 if (ret != I40E_SUCCESS) {
3985                         PMD_DRV_LOG(ERR, "Failed to configure "
3986                                     "TC queue mapping");
3987                         goto fail_msix_alloc;
3988                 }
3989                 ctxt.seid = vsi->seid;
3990                 ctxt.pf_num = hw->pf_id;
3991                 ctxt.uplink_seid = vsi->uplink_seid;
3992                 ctxt.vf_num = 0;
3993
3994                 /* Update VSI parameters */
3995                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3996                 if (ret != I40E_SUCCESS) {
3997                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3998                         goto fail_msix_alloc;
3999                 }
4000
4001                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4002                                                 sizeof(vsi->info.tc_mapping));
4003                 (void)rte_memcpy(&vsi->info.queue_mapping,
4004                                 &ctxt.info.queue_mapping,
4005                         sizeof(vsi->info.queue_mapping));
4006                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4007                 vsi->info.valid_sections = 0;
4008
4009                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4010                                 ETH_ADDR_LEN);
4011
4012                 /**
4013                  * Updating default filter settings are necessary to prevent
4014                  * reception of tagged packets.
4015                  * Some old firmware configurations load a default macvlan
4016                  * filter which accepts both tagged and untagged packets.
4017                  * The updating is to use a normal filter instead if needed.
4018                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4019                  * The firmware with correct configurations load the default
4020                  * macvlan filter which is expected and cannot be removed.
4021                  */
4022                 i40e_update_default_filter_setting(vsi);
4023                 i40e_config_qinq(hw, vsi);
4024         } else if (type == I40E_VSI_SRIOV) {
4025                 memset(&ctxt, 0, sizeof(ctxt));
4026                 /**
4027                  * For other VSI, the uplink_seid equals to uplink VSI's
4028                  * uplink_seid since they share same VEB
4029                  */
4030                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4031                 ctxt.pf_num = hw->pf_id;
4032                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4033                 ctxt.uplink_seid = vsi->uplink_seid;
4034                 ctxt.connection_type = 0x1;
4035                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4036
4037                 /**
4038                  * Do not configure switch ID to enable VEB switch by
4039                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4040                  * if the source mac address of packet sent from VF is not
4041                  * listed in the VEB's mac table, the VEB will switch the
4042                  * packet back to the VF. Need to enable it when HW issue
4043                  * is fixed.
4044                  */
4045
4046                 /* Configure port/vlan */
4047                 ctxt.info.valid_sections |=
4048                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4049                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4050                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4051                                                 I40E_DEFAULT_TCMAP);
4052                 if (ret != I40E_SUCCESS) {
4053                         PMD_DRV_LOG(ERR, "Failed to configure "
4054                                     "TC queue mapping");
4055                         goto fail_msix_alloc;
4056                 }
4057                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4058                 ctxt.info.valid_sections |=
4059                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4060                 /**
4061                  * Since VSI is not created yet, only configure parameter,
4062                  * will add vsi below.
4063                  */
4064
4065                 i40e_config_qinq(hw, vsi);
4066         } else if (type == I40E_VSI_VMDQ2) {
4067                 memset(&ctxt, 0, sizeof(ctxt));
4068                 /*
4069                  * For other VSI, the uplink_seid equals to uplink VSI's
4070                  * uplink_seid since they share same VEB
4071                  */
4072                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4073                 ctxt.pf_num = hw->pf_id;
4074                 ctxt.vf_num = 0;
4075                 ctxt.uplink_seid = vsi->uplink_seid;
4076                 ctxt.connection_type = 0x1;
4077                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4078
4079                 ctxt.info.valid_sections |=
4080                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4081                 /* user_param carries flag to enable loop back */
4082                 if (user_param) {
4083                         ctxt.info.switch_id =
4084                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4085                         ctxt.info.switch_id |=
4086                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4087                 }
4088
4089                 /* Configure port/vlan */
4090                 ctxt.info.valid_sections |=
4091                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4092                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4093                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4094                                                 I40E_DEFAULT_TCMAP);
4095                 if (ret != I40E_SUCCESS) {
4096                         PMD_DRV_LOG(ERR, "Failed to configure "
4097                                         "TC queue mapping");
4098                         goto fail_msix_alloc;
4099                 }
4100                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4101                 ctxt.info.valid_sections |=
4102                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4103         } else if (type == I40E_VSI_FDIR) {
4104                 memset(&ctxt, 0, sizeof(ctxt));
4105                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4106                 ctxt.pf_num = hw->pf_id;
4107                 ctxt.vf_num = 0;
4108                 ctxt.uplink_seid = vsi->uplink_seid;
4109                 ctxt.connection_type = 0x1;     /* regular data port */
4110                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4111                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4112                                                 I40E_DEFAULT_TCMAP);
4113                 if (ret != I40E_SUCCESS) {
4114                         PMD_DRV_LOG(ERR, "Failed to configure "
4115                                         "TC queue mapping.");
4116                         goto fail_msix_alloc;
4117                 }
4118                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4119                 ctxt.info.valid_sections |=
4120                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4121         } else {
4122                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4123                 goto fail_msix_alloc;
4124         }
4125
4126         if (vsi->type != I40E_VSI_MAIN) {
4127                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4128                 if (ret != I40E_SUCCESS) {
4129                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4130                                     hw->aq.asq_last_status);
4131                         goto fail_msix_alloc;
4132                 }
4133                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4134                 vsi->info.valid_sections = 0;
4135                 vsi->seid = ctxt.seid;
4136                 vsi->vsi_id = ctxt.vsi_number;
4137                 vsi->sib_vsi_list.vsi = vsi;
4138                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4139                                 &vsi->sib_vsi_list, list);
4140         }
4141
4142         /* MAC/VLAN configuration */
4143         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4144         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4145
4146         ret = i40e_vsi_add_mac(vsi, &filter);
4147         if (ret != I40E_SUCCESS) {
4148                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4149                 goto fail_msix_alloc;
4150         }
4151
4152         /* Get VSI BW information */
4153         i40e_vsi_dump_bw_config(vsi);
4154         return vsi;
4155 fail_msix_alloc:
4156         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4157 fail_queue_alloc:
4158         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4159 fail_mem:
4160         rte_free(vsi);
4161         return NULL;
4162 }
4163
4164 /* Configure vlan stripping on or off */
4165 int
4166 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4167 {
4168         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4169         struct i40e_vsi_context ctxt;
4170         uint8_t vlan_flags;
4171         int ret = I40E_SUCCESS;
4172
4173         /* Check if it has been already on or off */
4174         if (vsi->info.valid_sections &
4175                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4176                 if (on) {
4177                         if ((vsi->info.port_vlan_flags &
4178                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4179                                 return 0; /* already on */
4180                 } else {
4181                         if ((vsi->info.port_vlan_flags &
4182                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4183                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4184                                 return 0; /* already off */
4185                 }
4186         }
4187
4188         if (on)
4189                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4190         else
4191                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4192         vsi->info.valid_sections =
4193                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4194         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4195         vsi->info.port_vlan_flags |= vlan_flags;
4196         ctxt.seid = vsi->seid;
4197         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4198         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4199         if (ret)
4200                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4201                             on ? "enable" : "disable");
4202
4203         return ret;
4204 }
4205
4206 static int
4207 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4208 {
4209         struct rte_eth_dev_data *data = dev->data;
4210         int ret;
4211
4212         /* Apply vlan offload setting */
4213         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4214
4215         /* Apply double-vlan setting, not implemented yet */
4216
4217         /* Apply pvid setting */
4218         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4219                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4220         if (ret)
4221                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4222
4223         return ret;
4224 }
4225
4226 static int
4227 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4228 {
4229         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4230
4231         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4232 }
4233
4234 static int
4235 i40e_update_flow_control(struct i40e_hw *hw)
4236 {
4237 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4238         struct i40e_link_status link_status;
4239         uint32_t rxfc = 0, txfc = 0, reg;
4240         uint8_t an_info;
4241         int ret;
4242
4243         memset(&link_status, 0, sizeof(link_status));
4244         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4245         if (ret != I40E_SUCCESS) {
4246                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4247                 goto write_reg; /* Disable flow control */
4248         }
4249
4250         an_info = hw->phy.link_info.an_info;
4251         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4252                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4253                 ret = I40E_ERR_NOT_READY;
4254                 goto write_reg; /* Disable flow control */
4255         }
4256         /**
4257          * If link auto negotiation is enabled, flow control needs to
4258          * be configured according to it
4259          */
4260         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4261         case I40E_LINK_PAUSE_RXTX:
4262                 rxfc = 1;
4263                 txfc = 1;
4264                 hw->fc.current_mode = I40E_FC_FULL;
4265                 break;
4266         case I40E_AQ_LINK_PAUSE_RX:
4267                 rxfc = 1;
4268                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4269                 break;
4270         case I40E_AQ_LINK_PAUSE_TX:
4271                 txfc = 1;
4272                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4273                 break;
4274         default:
4275                 hw->fc.current_mode = I40E_FC_NONE;
4276                 break;
4277         }
4278
4279 write_reg:
4280         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4281                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4282         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4283         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4284         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4285         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4286
4287         return ret;
4288 }
4289
4290 /* PF setup */
4291 static int
4292 i40e_pf_setup(struct i40e_pf *pf)
4293 {
4294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4295         struct i40e_filter_control_settings settings;
4296         struct i40e_vsi *vsi;
4297         int ret;
4298
4299         /* Clear all stats counters */
4300         pf->offset_loaded = FALSE;
4301         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4302         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4303
4304         ret = i40e_pf_get_switch_config(pf);
4305         if (ret != I40E_SUCCESS) {
4306                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4307                 return ret;
4308         }
4309         if (pf->flags & I40E_FLAG_FDIR) {
4310                 /* make queue allocated first, let FDIR use queue pair 0*/
4311                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4312                 if (ret != I40E_FDIR_QUEUE_ID) {
4313                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4314                                     " ret =%d", ret);
4315                         pf->flags &= ~I40E_FLAG_FDIR;
4316                 }
4317         }
4318         /*  main VSI setup */
4319         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4320         if (!vsi) {
4321                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4322                 return I40E_ERR_NOT_READY;
4323         }
4324         pf->main_vsi = vsi;
4325
4326         /* Configure filter control */
4327         memset(&settings, 0, sizeof(settings));
4328         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4329                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4330         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4331                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4332         else {
4333                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4334                                                 hw->func_caps.rss_table_size);
4335                 return I40E_ERR_PARAM;
4336         }
4337         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4338                         "size: %u\n", hw->func_caps.rss_table_size);
4339         pf->hash_lut_size = hw->func_caps.rss_table_size;
4340
4341         /* Enable ethtype and macvlan filters */
4342         settings.enable_ethtype = TRUE;
4343         settings.enable_macvlan = TRUE;
4344         ret = i40e_set_filter_control(hw, &settings);
4345         if (ret)
4346                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4347                                                                 ret);
4348
4349         /* Update flow control according to the auto negotiation */
4350         i40e_update_flow_control(hw);
4351
4352         return I40E_SUCCESS;
4353 }
4354
4355 int
4356 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4357 {
4358         uint32_t reg;
4359         uint16_t j;
4360
4361         /**
4362          * Set or clear TX Queue Disable flags,
4363          * which is required by hardware.
4364          */
4365         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4366         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4367
4368         /* Wait until the request is finished */
4369         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4370                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4371                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4372                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4373                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4374                                                         & 0x1))) {
4375                         break;
4376                 }
4377         }
4378         if (on) {
4379                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4380                         return I40E_SUCCESS; /* already on, skip next steps */
4381
4382                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4383                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4384         } else {
4385                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4386                         return I40E_SUCCESS; /* already off, skip next steps */
4387                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4388         }
4389         /* Write the register */
4390         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4391         /* Check the result */
4392         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4393                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4394                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4395                 if (on) {
4396                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4397                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4398                                 break;
4399                 } else {
4400                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4401                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4402                                 break;
4403                 }
4404         }
4405         /* Check if it is timeout */
4406         if (j >= I40E_CHK_Q_ENA_COUNT) {
4407                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4408                             (on ? "enable" : "disable"), q_idx);
4409                 return I40E_ERR_TIMEOUT;
4410         }
4411
4412         return I40E_SUCCESS;
4413 }
4414
4415 /* Swith on or off the tx queues */
4416 static int
4417 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4418 {
4419         struct rte_eth_dev_data *dev_data = pf->dev_data;
4420         struct i40e_tx_queue *txq;
4421         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4422         uint16_t i;
4423         int ret;
4424
4425         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4426                 txq = dev_data->tx_queues[i];
4427                 /* Don't operate the queue if not configured or
4428                  * if starting only per queue */
4429                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4430                         continue;
4431                 if (on)
4432                         ret = i40e_dev_tx_queue_start(dev, i);
4433                 else
4434                         ret = i40e_dev_tx_queue_stop(dev, i);
4435                 if ( ret != I40E_SUCCESS)
4436                         return ret;
4437         }
4438
4439         return I40E_SUCCESS;
4440 }
4441
4442 int
4443 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4444 {
4445         uint32_t reg;
4446         uint16_t j;
4447
4448         /* Wait until the request is finished */
4449         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4450                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4451                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4452                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4453                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4454                         break;
4455         }
4456
4457         if (on) {
4458                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4459                         return I40E_SUCCESS; /* Already on, skip next steps */
4460                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4461         } else {
4462                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4463                         return I40E_SUCCESS; /* Already off, skip next steps */
4464                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4465         }
4466
4467         /* Write the register */
4468         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4469         /* Check the result */
4470         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4471                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4472                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4473                 if (on) {
4474                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4475                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4476                                 break;
4477                 } else {
4478                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4479                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4480                                 break;
4481                 }
4482         }
4483
4484         /* Check if it is timeout */
4485         if (j >= I40E_CHK_Q_ENA_COUNT) {
4486                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4487                             (on ? "enable" : "disable"), q_idx);
4488                 return I40E_ERR_TIMEOUT;
4489         }
4490
4491         return I40E_SUCCESS;
4492 }
4493 /* Switch on or off the rx queues */
4494 static int
4495 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4496 {
4497         struct rte_eth_dev_data *dev_data = pf->dev_data;
4498         struct i40e_rx_queue *rxq;
4499         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4500         uint16_t i;
4501         int ret;
4502
4503         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4504                 rxq = dev_data->rx_queues[i];
4505                 /* Don't operate the queue if not configured or
4506                  * if starting only per queue */
4507                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4508                         continue;
4509                 if (on)
4510                         ret = i40e_dev_rx_queue_start(dev, i);
4511                 else
4512                         ret = i40e_dev_rx_queue_stop(dev, i);
4513                 if (ret != I40E_SUCCESS)
4514                         return ret;
4515         }
4516
4517         return I40E_SUCCESS;
4518 }
4519
4520 /* Switch on or off all the rx/tx queues */
4521 int
4522 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4523 {
4524         int ret;
4525
4526         if (on) {
4527                 /* enable rx queues before enabling tx queues */
4528                 ret = i40e_dev_switch_rx_queues(pf, on);
4529                 if (ret) {
4530                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4531                         return ret;
4532                 }
4533                 ret = i40e_dev_switch_tx_queues(pf, on);
4534         } else {
4535                 /* Stop tx queues before stopping rx queues */
4536                 ret = i40e_dev_switch_tx_queues(pf, on);
4537                 if (ret) {
4538                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4539                         return ret;
4540                 }
4541                 ret = i40e_dev_switch_rx_queues(pf, on);
4542         }
4543
4544         return ret;
4545 }
4546
4547 /* Initialize VSI for TX */
4548 static int
4549 i40e_dev_tx_init(struct i40e_pf *pf)
4550 {
4551         struct rte_eth_dev_data *data = pf->dev_data;
4552         uint16_t i;
4553         uint32_t ret = I40E_SUCCESS;
4554         struct i40e_tx_queue *txq;
4555
4556         for (i = 0; i < data->nb_tx_queues; i++) {
4557                 txq = data->tx_queues[i];
4558                 if (!txq || !txq->q_set)
4559                         continue;
4560                 ret = i40e_tx_queue_init(txq);
4561                 if (ret != I40E_SUCCESS)
4562                         break;
4563         }
4564         if (ret == I40E_SUCCESS)
4565                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4566                                      ->eth_dev);
4567
4568         return ret;
4569 }
4570
4571 /* Initialize VSI for RX */
4572 static int
4573 i40e_dev_rx_init(struct i40e_pf *pf)
4574 {
4575         struct rte_eth_dev_data *data = pf->dev_data;
4576         int ret = I40E_SUCCESS;
4577         uint16_t i;
4578         struct i40e_rx_queue *rxq;
4579
4580         i40e_pf_config_mq_rx(pf);
4581         for (i = 0; i < data->nb_rx_queues; i++) {
4582                 rxq = data->rx_queues[i];
4583                 if (!rxq || !rxq->q_set)
4584                         continue;
4585
4586                 ret = i40e_rx_queue_init(rxq);
4587                 if (ret != I40E_SUCCESS) {
4588                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4589                                     "initialization");
4590                         break;
4591                 }
4592         }
4593         if (ret == I40E_SUCCESS)
4594                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4595                                      ->eth_dev);
4596
4597         return ret;
4598 }
4599
4600 static int
4601 i40e_dev_rxtx_init(struct i40e_pf *pf)
4602 {
4603         int err;
4604
4605         err = i40e_dev_tx_init(pf);
4606         if (err) {
4607                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4608                 return err;
4609         }
4610         err = i40e_dev_rx_init(pf);
4611         if (err) {
4612                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4613                 return err;
4614         }
4615
4616         return err;
4617 }
4618
4619 static int
4620 i40e_vmdq_setup(struct rte_eth_dev *dev)
4621 {
4622         struct rte_eth_conf *conf = &dev->data->dev_conf;
4623         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4624         int i, err, conf_vsis, j, loop;
4625         struct i40e_vsi *vsi;
4626         struct i40e_vmdq_info *vmdq_info;
4627         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4628         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4629
4630         /*
4631          * Disable interrupt to avoid message from VF. Furthermore, it will
4632          * avoid race condition in VSI creation/destroy.
4633          */
4634         i40e_pf_disable_irq0(hw);
4635
4636         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4637                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4638                 return -ENOTSUP;
4639         }
4640
4641         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4642         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4643                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4644                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4645                         pf->max_nb_vmdq_vsi);
4646                 return -ENOTSUP;
4647         }
4648
4649         if (pf->vmdq != NULL) {
4650                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4651                 return 0;
4652         }
4653
4654         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4655                                 sizeof(*vmdq_info) * conf_vsis, 0);
4656
4657         if (pf->vmdq == NULL) {
4658                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4659                 return -ENOMEM;
4660         }
4661
4662         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4663
4664         /* Create VMDQ VSI */
4665         for (i = 0; i < conf_vsis; i++) {
4666                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4667                                 vmdq_conf->enable_loop_back);
4668                 if (vsi == NULL) {
4669                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4670                         err = -1;
4671                         goto err_vsi_setup;
4672                 }
4673                 vmdq_info = &pf->vmdq[i];
4674                 vmdq_info->pf = pf;
4675                 vmdq_info->vsi = vsi;
4676         }
4677         pf->nb_cfg_vmdq_vsi = conf_vsis;
4678
4679         /* Configure Vlan */
4680         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4681         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4682                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4683                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4684                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4685                                         vmdq_conf->pool_map[i].vlan_id, j);
4686
4687                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4688                                                 vmdq_conf->pool_map[i].vlan_id);
4689                                 if (err) {
4690                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4691                                         err = -1;
4692                                         goto err_vsi_setup;
4693                                 }
4694                         }
4695                 }
4696         }
4697
4698         i40e_pf_enable_irq0(hw);
4699
4700         return 0;
4701
4702 err_vsi_setup:
4703         for (i = 0; i < conf_vsis; i++)
4704                 if (pf->vmdq[i].vsi == NULL)
4705                         break;
4706                 else
4707                         i40e_vsi_release(pf->vmdq[i].vsi);
4708
4709         rte_free(pf->vmdq);
4710         pf->vmdq = NULL;
4711         i40e_pf_enable_irq0(hw);
4712         return err;
4713 }
4714
4715 static void
4716 i40e_stat_update_32(struct i40e_hw *hw,
4717                    uint32_t reg,
4718                    bool offset_loaded,
4719                    uint64_t *offset,
4720                    uint64_t *stat)
4721 {
4722         uint64_t new_data;
4723
4724         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4725         if (!offset_loaded)
4726                 *offset = new_data;
4727
4728         if (new_data >= *offset)
4729                 *stat = (uint64_t)(new_data - *offset);
4730         else
4731                 *stat = (uint64_t)((new_data +
4732                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4733 }
4734
4735 static void
4736 i40e_stat_update_48(struct i40e_hw *hw,
4737                    uint32_t hireg,
4738                    uint32_t loreg,
4739                    bool offset_loaded,
4740                    uint64_t *offset,
4741                    uint64_t *stat)
4742 {
4743         uint64_t new_data;
4744
4745         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4746         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4747                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4748
4749         if (!offset_loaded)
4750                 *offset = new_data;
4751
4752         if (new_data >= *offset)
4753                 *stat = new_data - *offset;
4754         else
4755                 *stat = (uint64_t)((new_data +
4756                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4757
4758         *stat &= I40E_48_BIT_MASK;
4759 }
4760
4761 /* Disable IRQ0 */
4762 void
4763 i40e_pf_disable_irq0(struct i40e_hw *hw)
4764 {
4765         /* Disable all interrupt types */
4766         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4767         I40E_WRITE_FLUSH(hw);
4768 }
4769
4770 /* Enable IRQ0 */
4771 void
4772 i40e_pf_enable_irq0(struct i40e_hw *hw)
4773 {
4774         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4775                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4776                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4777                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4778         I40E_WRITE_FLUSH(hw);
4779 }
4780
4781 static void
4782 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4783 {
4784         /* read pending request and disable first */
4785         i40e_pf_disable_irq0(hw);
4786         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4787         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4788                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4789
4790         if (no_queue)
4791                 /* Link no queues with irq0 */
4792                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4793                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4794 }
4795
4796 static void
4797 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4798 {
4799         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4801         int i;
4802         uint16_t abs_vf_id;
4803         uint32_t index, offset, val;
4804
4805         if (!pf->vfs)
4806                 return;
4807         /**
4808          * Try to find which VF trigger a reset, use absolute VF id to access
4809          * since the reg is global register.
4810          */
4811         for (i = 0; i < pf->vf_num; i++) {
4812                 abs_vf_id = hw->func_caps.vf_base_id + i;
4813                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4814                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4815                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4816                 /* VFR event occured */
4817                 if (val & (0x1 << offset)) {
4818                         int ret;
4819
4820                         /* Clear the event first */
4821                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4822                                                         (0x1 << offset));
4823                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4824                         /**
4825                          * Only notify a VF reset event occured,
4826                          * don't trigger another SW reset
4827                          */
4828                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4829                         if (ret != I40E_SUCCESS)
4830                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4831                 }
4832         }
4833 }
4834
4835 static void
4836 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4837 {
4838         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4839         struct i40e_arq_event_info info;
4840         uint16_t pending, opcode;
4841         int ret;
4842
4843         info.buf_len = I40E_AQ_BUF_SZ;
4844         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4845         if (!info.msg_buf) {
4846                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4847                 return;
4848         }
4849
4850         pending = 1;
4851         while (pending) {
4852                 ret = i40e_clean_arq_element(hw, &info, &pending);
4853
4854                 if (ret != I40E_SUCCESS) {
4855                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4856                                     "aq_err: %u", hw->aq.asq_last_status);
4857                         break;
4858                 }
4859                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4860
4861                 switch (opcode) {
4862                 case i40e_aqc_opc_send_msg_to_pf:
4863                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4864                         i40e_pf_host_handle_vf_msg(dev,
4865                                         rte_le_to_cpu_16(info.desc.retval),
4866                                         rte_le_to_cpu_32(info.desc.cookie_high),
4867                                         rte_le_to_cpu_32(info.desc.cookie_low),
4868                                         info.msg_buf,
4869                                         info.msg_len);
4870                         break;
4871                 default:
4872                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4873                                     opcode);
4874                         break;
4875                 }
4876         }
4877         rte_free(info.msg_buf);
4878 }
4879
4880 /*
4881  * Interrupt handler is registered as the alarm callback for handling LSC
4882  * interrupt in a definite of time, in order to wait the NIC into a stable
4883  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4884  * no need for link down interrupt.
4885  */
4886 static void
4887 i40e_dev_interrupt_delayed_handler(void *param)
4888 {
4889         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4890         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4891         uint32_t icr0;
4892
4893         /* read interrupt causes again */
4894         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4895
4896 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4897         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4898                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4899         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4900                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4901         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4902                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4903         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4904                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4905         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4906                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4907                                                                 "state\n");
4908         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4909                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4910         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4911                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4912 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4913
4914         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4915                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4916                 i40e_dev_handle_vfr_event(dev);
4917         }
4918         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4919                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4920                 i40e_dev_handle_aq_msg(dev);
4921         }
4922
4923         /* handle the link up interrupt in an alarm callback */
4924         i40e_dev_link_update(dev, 0);
4925         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4926
4927         i40e_pf_enable_irq0(hw);
4928         rte_intr_enable(&(dev->pci_dev->intr_handle));
4929 }
4930
4931 /**
4932  * Interrupt handler triggered by NIC  for handling
4933  * specific interrupt.
4934  *
4935  * @param handle
4936  *  Pointer to interrupt handle.
4937  * @param param
4938  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4939  *
4940  * @return
4941  *  void
4942  */
4943 static void
4944 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4945                            void *param)
4946 {
4947         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949         uint32_t icr0;
4950
4951         /* Disable interrupt */
4952         i40e_pf_disable_irq0(hw);
4953
4954         /* read out interrupt causes */
4955         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4956
4957         /* No interrupt event indicated */
4958         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4959                 PMD_DRV_LOG(INFO, "No interrupt event");
4960                 goto done;
4961         }
4962 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4963         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4964                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4965         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4966                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4967         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4968                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4969         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4970                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4971         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4972                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4973         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4974                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4975         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4976                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4977 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4978
4979         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4980                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4981                 i40e_dev_handle_vfr_event(dev);
4982         }
4983         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4984                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4985                 i40e_dev_handle_aq_msg(dev);
4986         }
4987
4988         /* Link Status Change interrupt */
4989         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4990 #define I40E_US_PER_SECOND 1000000
4991                 struct rte_eth_link link;
4992
4993                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4994                 memset(&link, 0, sizeof(link));
4995                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4996                 i40e_dev_link_update(dev, 0);
4997
4998                 /*
4999                  * For link up interrupt, it needs to wait 1 second to let the
5000                  * hardware be a stable state. Otherwise several consecutive
5001                  * interrupts can be observed.
5002                  * For link down interrupt, no need to wait.
5003                  */
5004                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5005                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5006                         return;
5007                 else
5008                         _rte_eth_dev_callback_process(dev,
5009                                 RTE_ETH_EVENT_INTR_LSC);
5010         }
5011
5012 done:
5013         /* Enable interrupt */
5014         i40e_pf_enable_irq0(hw);
5015         rte_intr_enable(&(dev->pci_dev->intr_handle));
5016 }
5017
5018 static int
5019 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5020                          struct i40e_macvlan_filter *filter,
5021                          int total)
5022 {
5023         int ele_num, ele_buff_size;
5024         int num, actual_num, i;
5025         uint16_t flags;
5026         int ret = I40E_SUCCESS;
5027         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5028         struct i40e_aqc_add_macvlan_element_data *req_list;
5029
5030         if (filter == NULL  || total == 0)
5031                 return I40E_ERR_PARAM;
5032         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5033         ele_buff_size = hw->aq.asq_buf_size;
5034
5035         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5036         if (req_list == NULL) {
5037                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5038                 return I40E_ERR_NO_MEMORY;
5039         }
5040
5041         num = 0;
5042         do {
5043                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5044                 memset(req_list, 0, ele_buff_size);
5045
5046                 for (i = 0; i < actual_num; i++) {
5047                         (void)rte_memcpy(req_list[i].mac_addr,
5048                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5049                         req_list[i].vlan_tag =
5050                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5051
5052                         switch (filter[num + i].filter_type) {
5053                         case RTE_MAC_PERFECT_MATCH:
5054                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5055                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5056                                 break;
5057                         case RTE_MACVLAN_PERFECT_MATCH:
5058                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5059                                 break;
5060                         case RTE_MAC_HASH_MATCH:
5061                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5062                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5063                                 break;
5064                         case RTE_MACVLAN_HASH_MATCH:
5065                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5066                                 break;
5067                         default:
5068                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5069                                 ret = I40E_ERR_PARAM;
5070                                 goto DONE;
5071                         }
5072
5073                         req_list[i].queue_number = 0;
5074
5075                         req_list[i].flags = rte_cpu_to_le_16(flags);
5076                 }
5077
5078                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5079                                                 actual_num, NULL);
5080                 if (ret != I40E_SUCCESS) {
5081                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5082                         goto DONE;
5083                 }
5084                 num += actual_num;
5085         } while (num < total);
5086
5087 DONE:
5088         rte_free(req_list);
5089         return ret;
5090 }
5091
5092 static int
5093 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5094                             struct i40e_macvlan_filter *filter,
5095                             int total)
5096 {
5097         int ele_num, ele_buff_size;
5098         int num, actual_num, i;
5099         uint16_t flags;
5100         int ret = I40E_SUCCESS;
5101         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5102         struct i40e_aqc_remove_macvlan_element_data *req_list;
5103
5104         if (filter == NULL  || total == 0)
5105                 return I40E_ERR_PARAM;
5106
5107         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5108         ele_buff_size = hw->aq.asq_buf_size;
5109
5110         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5111         if (req_list == NULL) {
5112                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5113                 return I40E_ERR_NO_MEMORY;
5114         }
5115
5116         num = 0;
5117         do {
5118                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5119                 memset(req_list, 0, ele_buff_size);
5120
5121                 for (i = 0; i < actual_num; i++) {
5122                         (void)rte_memcpy(req_list[i].mac_addr,
5123                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5124                         req_list[i].vlan_tag =
5125                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5126
5127                         switch (filter[num + i].filter_type) {
5128                         case RTE_MAC_PERFECT_MATCH:
5129                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5130                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5131                                 break;
5132                         case RTE_MACVLAN_PERFECT_MATCH:
5133                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5134                                 break;
5135                         case RTE_MAC_HASH_MATCH:
5136                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5137                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5138                                 break;
5139                         case RTE_MACVLAN_HASH_MATCH:
5140                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5141                                 break;
5142                         default:
5143                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5144                                 ret = I40E_ERR_PARAM;
5145                                 goto DONE;
5146                         }
5147                         req_list[i].flags = rte_cpu_to_le_16(flags);
5148                 }
5149
5150                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5151                                                 actual_num, NULL);
5152                 if (ret != I40E_SUCCESS) {
5153                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5154                         goto DONE;
5155                 }
5156                 num += actual_num;
5157         } while (num < total);
5158
5159 DONE:
5160         rte_free(req_list);
5161         return ret;
5162 }
5163
5164 /* Find out specific MAC filter */
5165 static struct i40e_mac_filter *
5166 i40e_find_mac_filter(struct i40e_vsi *vsi,
5167                          struct ether_addr *macaddr)
5168 {
5169         struct i40e_mac_filter *f;
5170
5171         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5172                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5173                         return f;
5174         }
5175
5176         return NULL;
5177 }
5178
5179 static bool
5180 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5181                          uint16_t vlan_id)
5182 {
5183         uint32_t vid_idx, vid_bit;
5184
5185         if (vlan_id > ETH_VLAN_ID_MAX)
5186                 return 0;
5187
5188         vid_idx = I40E_VFTA_IDX(vlan_id);
5189         vid_bit = I40E_VFTA_BIT(vlan_id);
5190
5191         if (vsi->vfta[vid_idx] & vid_bit)
5192                 return 1;
5193         else
5194                 return 0;
5195 }
5196
5197 static void
5198 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5199                          uint16_t vlan_id, bool on)
5200 {
5201         uint32_t vid_idx, vid_bit;
5202
5203         if (vlan_id > ETH_VLAN_ID_MAX)
5204                 return;
5205
5206         vid_idx = I40E_VFTA_IDX(vlan_id);
5207         vid_bit = I40E_VFTA_BIT(vlan_id);
5208
5209         if (on)
5210                 vsi->vfta[vid_idx] |= vid_bit;
5211         else
5212                 vsi->vfta[vid_idx] &= ~vid_bit;
5213 }
5214
5215 /**
5216  * Find all vlan options for specific mac addr,
5217  * return with actual vlan found.
5218  */
5219 static inline int
5220 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5221                            struct i40e_macvlan_filter *mv_f,
5222                            int num, struct ether_addr *addr)
5223 {
5224         int i;
5225         uint32_t j, k;
5226
5227         /**
5228          * Not to use i40e_find_vlan_filter to decrease the loop time,
5229          * although the code looks complex.
5230           */
5231         if (num < vsi->vlan_num)
5232                 return I40E_ERR_PARAM;
5233
5234         i = 0;
5235         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5236                 if (vsi->vfta[j]) {
5237                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5238                                 if (vsi->vfta[j] & (1 << k)) {
5239                                         if (i > num - 1) {
5240                                                 PMD_DRV_LOG(ERR, "vlan number "
5241                                                             "not match");
5242                                                 return I40E_ERR_PARAM;
5243                                         }
5244                                         (void)rte_memcpy(&mv_f[i].macaddr,
5245                                                         addr, ETH_ADDR_LEN);
5246                                         mv_f[i].vlan_id =
5247                                                 j * I40E_UINT32_BIT_SIZE + k;
5248                                         i++;
5249                                 }
5250                         }
5251                 }
5252         }
5253         return I40E_SUCCESS;
5254 }
5255
5256 static inline int
5257 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5258                            struct i40e_macvlan_filter *mv_f,
5259                            int num,
5260                            uint16_t vlan)
5261 {
5262         int i = 0;
5263         struct i40e_mac_filter *f;
5264
5265         if (num < vsi->mac_num)
5266                 return I40E_ERR_PARAM;
5267
5268         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5269                 if (i > num - 1) {
5270                         PMD_DRV_LOG(ERR, "buffer number not match");
5271                         return I40E_ERR_PARAM;
5272                 }
5273                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5274                                 ETH_ADDR_LEN);
5275                 mv_f[i].vlan_id = vlan;
5276                 mv_f[i].filter_type = f->mac_info.filter_type;
5277                 i++;
5278         }
5279
5280         return I40E_SUCCESS;
5281 }
5282
5283 static int
5284 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5285 {
5286         int i, num;
5287         struct i40e_mac_filter *f;
5288         struct i40e_macvlan_filter *mv_f;
5289         int ret = I40E_SUCCESS;
5290
5291         if (vsi == NULL || vsi->mac_num == 0)
5292                 return I40E_ERR_PARAM;
5293
5294         /* Case that no vlan is set */
5295         if (vsi->vlan_num == 0)
5296                 num = vsi->mac_num;
5297         else
5298                 num = vsi->mac_num * vsi->vlan_num;
5299
5300         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5301         if (mv_f == NULL) {
5302                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5303                 return I40E_ERR_NO_MEMORY;
5304         }
5305
5306         i = 0;
5307         if (vsi->vlan_num == 0) {
5308                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5309                         (void)rte_memcpy(&mv_f[i].macaddr,
5310                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5311                         mv_f[i].vlan_id = 0;
5312                         i++;
5313                 }
5314         } else {
5315                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5316                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5317                                         vsi->vlan_num, &f->mac_info.mac_addr);
5318                         if (ret != I40E_SUCCESS)
5319                                 goto DONE;
5320                         i += vsi->vlan_num;
5321                 }
5322         }
5323
5324         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5325 DONE:
5326         rte_free(mv_f);
5327
5328         return ret;
5329 }
5330
5331 int
5332 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5333 {
5334         struct i40e_macvlan_filter *mv_f;
5335         int mac_num;
5336         int ret = I40E_SUCCESS;
5337
5338         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5339                 return I40E_ERR_PARAM;
5340
5341         /* If it's already set, just return */
5342         if (i40e_find_vlan_filter(vsi,vlan))
5343                 return I40E_SUCCESS;
5344
5345         mac_num = vsi->mac_num;
5346
5347         if (mac_num == 0) {
5348                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5349                 return I40E_ERR_PARAM;
5350         }
5351
5352         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5353
5354         if (mv_f == NULL) {
5355                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5356                 return I40E_ERR_NO_MEMORY;
5357         }
5358
5359         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5360
5361         if (ret != I40E_SUCCESS)
5362                 goto DONE;
5363
5364         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5365
5366         if (ret != I40E_SUCCESS)
5367                 goto DONE;
5368
5369         i40e_set_vlan_filter(vsi, vlan, 1);
5370
5371         vsi->vlan_num++;
5372         ret = I40E_SUCCESS;
5373 DONE:
5374         rte_free(mv_f);
5375         return ret;
5376 }
5377
5378 int
5379 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5380 {
5381         struct i40e_macvlan_filter *mv_f;
5382         int mac_num;
5383         int ret = I40E_SUCCESS;
5384
5385         /**
5386          * Vlan 0 is the generic filter for untagged packets
5387          * and can't be removed.
5388          */
5389         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5390                 return I40E_ERR_PARAM;
5391
5392         /* If can't find it, just return */
5393         if (!i40e_find_vlan_filter(vsi, vlan))
5394                 return I40E_ERR_PARAM;
5395
5396         mac_num = vsi->mac_num;
5397
5398         if (mac_num == 0) {
5399                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5400                 return I40E_ERR_PARAM;
5401         }
5402
5403         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5404
5405         if (mv_f == NULL) {
5406                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5407                 return I40E_ERR_NO_MEMORY;
5408         }
5409
5410         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5411
5412         if (ret != I40E_SUCCESS)
5413                 goto DONE;
5414
5415         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5416
5417         if (ret != I40E_SUCCESS)
5418                 goto DONE;
5419
5420         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5421         if (vsi->vlan_num == 1) {
5422                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5423                 if (ret != I40E_SUCCESS)
5424                         goto DONE;
5425
5426                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5427                 if (ret != I40E_SUCCESS)
5428                         goto DONE;
5429         }
5430
5431         i40e_set_vlan_filter(vsi, vlan, 0);
5432
5433         vsi->vlan_num--;
5434         ret = I40E_SUCCESS;
5435 DONE:
5436         rte_free(mv_f);
5437         return ret;
5438 }
5439
5440 int
5441 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5442 {
5443         struct i40e_mac_filter *f;
5444         struct i40e_macvlan_filter *mv_f;
5445         int i, vlan_num = 0;
5446         int ret = I40E_SUCCESS;
5447
5448         /* If it's add and we've config it, return */
5449         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5450         if (f != NULL)
5451                 return I40E_SUCCESS;
5452         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5453                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5454
5455                 /**
5456                  * If vlan_num is 0, that's the first time to add mac,
5457                  * set mask for vlan_id 0.
5458                  */
5459                 if (vsi->vlan_num == 0) {
5460                         i40e_set_vlan_filter(vsi, 0, 1);
5461                         vsi->vlan_num = 1;
5462                 }
5463                 vlan_num = vsi->vlan_num;
5464         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5465                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5466                 vlan_num = 1;
5467
5468         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5469         if (mv_f == NULL) {
5470                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5471                 return I40E_ERR_NO_MEMORY;
5472         }
5473
5474         for (i = 0; i < vlan_num; i++) {
5475                 mv_f[i].filter_type = mac_filter->filter_type;
5476                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5477                                 ETH_ADDR_LEN);
5478         }
5479
5480         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5481                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5482                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5483                                         &mac_filter->mac_addr);
5484                 if (ret != I40E_SUCCESS)
5485                         goto DONE;
5486         }
5487
5488         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5489         if (ret != I40E_SUCCESS)
5490                 goto DONE;
5491
5492         /* Add the mac addr into mac list */
5493         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5494         if (f == NULL) {
5495                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5496                 ret = I40E_ERR_NO_MEMORY;
5497                 goto DONE;
5498         }
5499         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5500                         ETH_ADDR_LEN);
5501         f->mac_info.filter_type = mac_filter->filter_type;
5502         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5503         vsi->mac_num++;
5504
5505         ret = I40E_SUCCESS;
5506 DONE:
5507         rte_free(mv_f);
5508
5509         return ret;
5510 }
5511
5512 int
5513 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5514 {
5515         struct i40e_mac_filter *f;
5516         struct i40e_macvlan_filter *mv_f;
5517         int i, vlan_num;
5518         enum rte_mac_filter_type filter_type;
5519         int ret = I40E_SUCCESS;
5520
5521         /* Can't find it, return an error */
5522         f = i40e_find_mac_filter(vsi, addr);
5523         if (f == NULL)
5524                 return I40E_ERR_PARAM;
5525
5526         vlan_num = vsi->vlan_num;
5527         filter_type = f->mac_info.filter_type;
5528         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5529                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5530                 if (vlan_num == 0) {
5531                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5532                         return I40E_ERR_PARAM;
5533                 }
5534         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5535                         filter_type == RTE_MAC_HASH_MATCH)
5536                 vlan_num = 1;
5537
5538         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5539         if (mv_f == NULL) {
5540                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5541                 return I40E_ERR_NO_MEMORY;
5542         }
5543
5544         for (i = 0; i < vlan_num; i++) {
5545                 mv_f[i].filter_type = filter_type;
5546                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5547                                 ETH_ADDR_LEN);
5548         }
5549         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5550                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5551                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5552                 if (ret != I40E_SUCCESS)
5553                         goto DONE;
5554         }
5555
5556         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5557         if (ret != I40E_SUCCESS)
5558                 goto DONE;
5559
5560         /* Remove the mac addr into mac list */
5561         TAILQ_REMOVE(&vsi->mac_list, f, next);
5562         rte_free(f);
5563         vsi->mac_num--;
5564
5565         ret = I40E_SUCCESS;
5566 DONE:
5567         rte_free(mv_f);
5568         return ret;
5569 }
5570
5571 /* Configure hash enable flags for RSS */
5572 uint64_t
5573 i40e_config_hena(uint64_t flags)
5574 {
5575         uint64_t hena = 0;
5576
5577         if (!flags)
5578                 return hena;
5579
5580         if (flags & ETH_RSS_FRAG_IPV4)
5581                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5582         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5583                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5584         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5585                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5586         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5587                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5588         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5589                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5590         if (flags & ETH_RSS_FRAG_IPV6)
5591                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5592         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5593                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5594         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5595                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5596         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5597                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5598         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5599                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5600         if (flags & ETH_RSS_L2_PAYLOAD)
5601                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5602
5603         return hena;
5604 }
5605
5606 /* Parse the hash enable flags */
5607 uint64_t
5608 i40e_parse_hena(uint64_t flags)
5609 {
5610         uint64_t rss_hf = 0;
5611
5612         if (!flags)
5613                 return rss_hf;
5614         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5615                 rss_hf |= ETH_RSS_FRAG_IPV4;
5616         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5617                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5618         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5619                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5620         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5621                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5622         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5623                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5624         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5625                 rss_hf |= ETH_RSS_FRAG_IPV6;
5626         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5627                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5628         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5629                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5630         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5631                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5632         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5633                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5634         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5635                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5636
5637         return rss_hf;
5638 }
5639
5640 /* Disable RSS */
5641 static void
5642 i40e_pf_disable_rss(struct i40e_pf *pf)
5643 {
5644         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5645         uint64_t hena;
5646
5647         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5648         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5649         hena &= ~I40E_RSS_HENA_ALL;
5650         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5651         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5652         I40E_WRITE_FLUSH(hw);
5653 }
5654
5655 static int
5656 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5657 {
5658         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5659         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5660         int ret = 0;
5661
5662         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5663                 sizeof(uint32_t)))
5664                 return -EINVAL;
5665
5666         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5667                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5668                         (struct i40e_aqc_get_set_rss_key_data *)key;
5669
5670                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5671                 if (ret)
5672                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5673                                      "via AQ");
5674         } else {
5675                 uint32_t *hash_key = (uint32_t *)key;
5676                 uint16_t i;
5677
5678                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5679                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5680                 I40E_WRITE_FLUSH(hw);
5681         }
5682
5683         return ret;
5684 }
5685
5686 static int
5687 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5688 {
5689         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5690         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5691         int ret;
5692
5693         if (!key || !key_len)
5694                 return -EINVAL;
5695
5696         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5697                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5698                         (struct i40e_aqc_get_set_rss_key_data *)key);
5699                 if (ret) {
5700                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5701                         return ret;
5702                 }
5703         } else {
5704                 uint32_t *key_dw = (uint32_t *)key;
5705                 uint16_t i;
5706
5707                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5708                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5709         }
5710         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5711
5712         return 0;
5713 }
5714
5715 static int
5716 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5717 {
5718         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5719         uint64_t rss_hf;
5720         uint64_t hena;
5721         int ret;
5722
5723         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5724                                rss_conf->rss_key_len);
5725         if (ret)
5726                 return ret;
5727
5728         rss_hf = rss_conf->rss_hf;
5729         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5730         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5731         hena &= ~I40E_RSS_HENA_ALL;
5732         hena |= i40e_config_hena(rss_hf);
5733         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5734         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5735         I40E_WRITE_FLUSH(hw);
5736
5737         return 0;
5738 }
5739
5740 static int
5741 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5742                          struct rte_eth_rss_conf *rss_conf)
5743 {
5744         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5747         uint64_t hena;
5748
5749         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5750         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5751         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5752                 if (rss_hf != 0) /* Enable RSS */
5753                         return -EINVAL;
5754                 return 0; /* Nothing to do */
5755         }
5756         /* RSS enabled */
5757         if (rss_hf == 0) /* Disable RSS */
5758                 return -EINVAL;
5759
5760         return i40e_hw_rss_hash_set(pf, rss_conf);
5761 }
5762
5763 static int
5764 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5765                            struct rte_eth_rss_conf *rss_conf)
5766 {
5767         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5769         uint64_t hena;
5770
5771         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5772                          &rss_conf->rss_key_len);
5773
5774         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5775         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5776         rss_conf->rss_hf = i40e_parse_hena(hena);
5777
5778         return 0;
5779 }
5780
5781 static int
5782 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5783 {
5784         switch (filter_type) {
5785         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5786                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5787                 break;
5788         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5789                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5790                 break;
5791         case RTE_TUNNEL_FILTER_IMAC_TENID:
5792                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5793                 break;
5794         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5795                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5796                 break;
5797         case ETH_TUNNEL_FILTER_IMAC:
5798                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5799                 break;
5800         default:
5801                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5802                 return -EINVAL;
5803         }
5804
5805         return 0;
5806 }
5807
5808 static int
5809 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5810                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5811                         uint8_t add)
5812 {
5813         uint16_t ip_type;
5814         uint8_t tun_type = 0;
5815         int val, ret = 0;
5816         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5817         struct i40e_vsi *vsi = pf->main_vsi;
5818         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5819         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5820
5821         cld_filter = rte_zmalloc("tunnel_filter",
5822                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5823                 0);
5824
5825         if (NULL == cld_filter) {
5826                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5827                 return -EINVAL;
5828         }
5829         pfilter = cld_filter;
5830
5831         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5832                         sizeof(struct ether_addr));
5833         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5834                         sizeof(struct ether_addr));
5835
5836         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5837         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5838                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5839                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5840                                 &tunnel_filter->ip_addr,
5841                                 sizeof(pfilter->ipaddr.v4.data));
5842         } else {
5843                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5844                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5845                                 &tunnel_filter->ip_addr,
5846                                 sizeof(pfilter->ipaddr.v6.data));
5847         }
5848
5849         /* check tunneled type */
5850         switch (tunnel_filter->tunnel_type) {
5851         case RTE_TUNNEL_TYPE_VXLAN:
5852                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5853                 break;
5854         case RTE_TUNNEL_TYPE_NVGRE:
5855                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5856                 break;
5857         default:
5858                 /* Other tunnel types is not supported. */
5859                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5860                 rte_free(cld_filter);
5861                 return -EINVAL;
5862         }
5863
5864         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5865                                                 &pfilter->flags);
5866         if (val < 0) {
5867                 rte_free(cld_filter);
5868                 return -EINVAL;
5869         }
5870
5871         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5872                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5873         pfilter->tenant_id = tunnel_filter->tenant_id;
5874         pfilter->queue_number = tunnel_filter->queue_id;
5875
5876         if (add)
5877                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5878         else
5879                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5880                                                 cld_filter, 1);
5881
5882         rte_free(cld_filter);
5883         return ret;
5884 }
5885
5886 static int
5887 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5888 {
5889         uint8_t i;
5890
5891         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5892                 if (pf->vxlan_ports[i] == port)
5893                         return i;
5894         }
5895
5896         return -1;
5897 }
5898
5899 static int
5900 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5901 {
5902         int  idx, ret;
5903         uint8_t filter_idx;
5904         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5905
5906         idx = i40e_get_vxlan_port_idx(pf, port);
5907
5908         /* Check if port already exists */
5909         if (idx >= 0) {
5910                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5911                 return -EINVAL;
5912         }
5913
5914         /* Now check if there is space to add the new port */
5915         idx = i40e_get_vxlan_port_idx(pf, 0);
5916         if (idx < 0) {
5917                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5918                         "not adding port %d", port);
5919                 return -ENOSPC;
5920         }
5921
5922         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5923                                         &filter_idx, NULL);
5924         if (ret < 0) {
5925                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5926                 return -1;
5927         }
5928
5929         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5930                          port,  filter_idx);
5931
5932         /* New port: add it and mark its index in the bitmap */
5933         pf->vxlan_ports[idx] = port;
5934         pf->vxlan_bitmap |= (1 << idx);
5935
5936         if (!(pf->flags & I40E_FLAG_VXLAN))
5937                 pf->flags |= I40E_FLAG_VXLAN;
5938
5939         return 0;
5940 }
5941
5942 static int
5943 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5944 {
5945         int idx;
5946         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5947
5948         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5949                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5950                 return -EINVAL;
5951         }
5952
5953         idx = i40e_get_vxlan_port_idx(pf, port);
5954
5955         if (idx < 0) {
5956                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5957                 return -EINVAL;
5958         }
5959
5960         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5961                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5962                 return -1;
5963         }
5964
5965         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5966                         port, idx);
5967
5968         pf->vxlan_ports[idx] = 0;
5969         pf->vxlan_bitmap &= ~(1 << idx);
5970
5971         if (!pf->vxlan_bitmap)
5972                 pf->flags &= ~I40E_FLAG_VXLAN;
5973
5974         return 0;
5975 }
5976
5977 /* Add UDP tunneling port */
5978 static int
5979 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5980                         struct rte_eth_udp_tunnel *udp_tunnel)
5981 {
5982         int ret = 0;
5983         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5984
5985         if (udp_tunnel == NULL)
5986                 return -EINVAL;
5987
5988         switch (udp_tunnel->prot_type) {
5989         case RTE_TUNNEL_TYPE_VXLAN:
5990                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5991                 break;
5992
5993         case RTE_TUNNEL_TYPE_GENEVE:
5994         case RTE_TUNNEL_TYPE_TEREDO:
5995                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5996                 ret = -1;
5997                 break;
5998
5999         default:
6000                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6001                 ret = -1;
6002                 break;
6003         }
6004
6005         return ret;
6006 }
6007
6008 /* Remove UDP tunneling port */
6009 static int
6010 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6011                         struct rte_eth_udp_tunnel *udp_tunnel)
6012 {
6013         int ret = 0;
6014         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6015
6016         if (udp_tunnel == NULL)
6017                 return -EINVAL;
6018
6019         switch (udp_tunnel->prot_type) {
6020         case RTE_TUNNEL_TYPE_VXLAN:
6021                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6022                 break;
6023         case RTE_TUNNEL_TYPE_GENEVE:
6024         case RTE_TUNNEL_TYPE_TEREDO:
6025                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6026                 ret = -1;
6027                 break;
6028         default:
6029                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6030                 ret = -1;
6031                 break;
6032         }
6033
6034         return ret;
6035 }
6036
6037 /* Calculate the maximum number of contiguous PF queues that are configured */
6038 static int
6039 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6040 {
6041         struct rte_eth_dev_data *data = pf->dev_data;
6042         int i, num;
6043         struct i40e_rx_queue *rxq;
6044
6045         num = 0;
6046         for (i = 0; i < pf->lan_nb_qps; i++) {
6047                 rxq = data->rx_queues[i];
6048                 if (rxq && rxq->q_set)
6049                         num++;
6050                 else
6051                         break;
6052         }
6053
6054         return num;
6055 }
6056
6057 /* Configure RSS */
6058 static int
6059 i40e_pf_config_rss(struct i40e_pf *pf)
6060 {
6061         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6062         struct rte_eth_rss_conf rss_conf;
6063         uint32_t i, lut = 0;
6064         uint16_t j, num;
6065
6066         /*
6067          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6068          * It's necessary to calulate the actual PF queues that are configured.
6069          */
6070         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6071                 num = i40e_pf_calc_configured_queues_num(pf);
6072         else
6073                 num = pf->dev_data->nb_rx_queues;
6074
6075         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6076         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6077                         num);
6078
6079         if (num == 0) {
6080                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6081                 return -ENOTSUP;
6082         }
6083
6084         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6085                 if (j == num)
6086                         j = 0;
6087                 lut = (lut << 8) | (j & ((0x1 <<
6088                         hw->func_caps.rss_table_entry_width) - 1));
6089                 if ((i & 3) == 3)
6090                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6091         }
6092
6093         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6094         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6095                 i40e_pf_disable_rss(pf);
6096                 return 0;
6097         }
6098         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6099                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6100                 /* Random default keys */
6101                 static uint32_t rss_key_default[] = {0x6b793944,
6102                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6103                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6104                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6105
6106                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6107                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6108                                                         sizeof(uint32_t);
6109         }
6110
6111         return i40e_hw_rss_hash_set(pf, &rss_conf);
6112 }
6113
6114 static int
6115 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6116                                struct rte_eth_tunnel_filter_conf *filter)
6117 {
6118         if (pf == NULL || filter == NULL) {
6119                 PMD_DRV_LOG(ERR, "Invalid parameter");
6120                 return -EINVAL;
6121         }
6122
6123         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6124                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6125                 return -EINVAL;
6126         }
6127
6128         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6129                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6130                 return -EINVAL;
6131         }
6132
6133         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6134                 (is_zero_ether_addr(filter->outer_mac))) {
6135                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6136                 return -EINVAL;
6137         }
6138
6139         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6140                 (is_zero_ether_addr(filter->inner_mac))) {
6141                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6142                 return -EINVAL;
6143         }
6144
6145         return 0;
6146 }
6147
6148 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6149 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6150 static int
6151 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6152 {
6153         uint32_t val, reg;
6154         int ret = -EINVAL;
6155
6156         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6157         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6158
6159         if (len == 3) {
6160                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6161         } else if (len == 4) {
6162                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6163         } else {
6164                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6165                 return ret;
6166         }
6167
6168         if (reg != val) {
6169                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6170                                                    reg, NULL);
6171                 if (ret != 0)
6172                         return ret;
6173         } else {
6174                 ret = 0;
6175         }
6176         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6177                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6178
6179         return ret;
6180 }
6181
6182 static int
6183 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6184 {
6185         int ret = -EINVAL;
6186
6187         if (!hw || !cfg)
6188                 return -EINVAL;
6189
6190         switch (cfg->cfg_type) {
6191         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6192                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6193                 break;
6194         default:
6195                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6196                 break;
6197         }
6198
6199         return ret;
6200 }
6201
6202 static int
6203 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6204                                enum rte_filter_op filter_op,
6205                                void *arg)
6206 {
6207         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6208         int ret = I40E_ERR_PARAM;
6209
6210         switch (filter_op) {
6211         case RTE_ETH_FILTER_SET:
6212                 ret = i40e_dev_global_config_set(hw,
6213                         (struct rte_eth_global_cfg *)arg);
6214                 break;
6215         default:
6216                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6217                 break;
6218         }
6219
6220         return ret;
6221 }
6222
6223 static int
6224 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6225                           enum rte_filter_op filter_op,
6226                           void *arg)
6227 {
6228         struct rte_eth_tunnel_filter_conf *filter;
6229         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6230         int ret = I40E_SUCCESS;
6231
6232         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6233
6234         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6235                 return I40E_ERR_PARAM;
6236
6237         switch (filter_op) {
6238         case RTE_ETH_FILTER_NOP:
6239                 if (!(pf->flags & I40E_FLAG_VXLAN))
6240                         ret = I40E_NOT_SUPPORTED;
6241                 break;
6242         case RTE_ETH_FILTER_ADD:
6243                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6244                 break;
6245         case RTE_ETH_FILTER_DELETE:
6246                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6247                 break;
6248         default:
6249                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6250                 ret = I40E_ERR_PARAM;
6251                 break;
6252         }
6253
6254         return ret;
6255 }
6256
6257 static int
6258 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6259 {
6260         int ret = 0;
6261         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6262
6263         /* RSS setup */
6264         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6265                 ret = i40e_pf_config_rss(pf);
6266         else
6267                 i40e_pf_disable_rss(pf);
6268
6269         return ret;
6270 }
6271
6272 /* Get the symmetric hash enable configurations per port */
6273 static void
6274 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6275 {
6276         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6277
6278         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6279 }
6280
6281 /* Set the symmetric hash enable configurations per port */
6282 static void
6283 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6284 {
6285         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6286
6287         if (enable > 0) {
6288                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6289                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6290                                                         "been enabled");
6291                         return;
6292                 }
6293                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6294         } else {
6295                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6296                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6297                                                         "been disabled");
6298                         return;
6299                 }
6300                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6301         }
6302         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6303         I40E_WRITE_FLUSH(hw);
6304 }
6305
6306 /*
6307  * Get global configurations of hash function type and symmetric hash enable
6308  * per flow type (pctype). Note that global configuration means it affects all
6309  * the ports on the same NIC.
6310  */
6311 static int
6312 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6313                                    struct rte_eth_hash_global_conf *g_cfg)
6314 {
6315         uint32_t reg, mask = I40E_FLOW_TYPES;
6316         uint16_t i;
6317         enum i40e_filter_pctype pctype;
6318
6319         memset(g_cfg, 0, sizeof(*g_cfg));
6320         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6321         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6322                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6323         else
6324                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6325         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6326                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6327
6328         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6329                 if (!(mask & (1UL << i)))
6330                         continue;
6331                 mask &= ~(1UL << i);
6332                 /* Bit set indicats the coresponding flow type is supported */
6333                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6334                 pctype = i40e_flowtype_to_pctype(i);
6335                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6336                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6337                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6338         }
6339
6340         return 0;
6341 }
6342
6343 static int
6344 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6345 {
6346         uint32_t i;
6347         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6348
6349         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6350                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6351                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6352                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6353                                                 g_cfg->hash_func);
6354                 return -EINVAL;
6355         }
6356
6357         /*
6358          * As i40e supports less than 32 flow types, only first 32 bits need to
6359          * be checked.
6360          */
6361         mask0 = g_cfg->valid_bit_mask[0];
6362         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6363                 if (i == 0) {
6364                         /* Check if any unsupported flow type configured */
6365                         if ((mask0 | i40e_mask) ^ i40e_mask)
6366                                 goto mask_err;
6367                 } else {
6368                         if (g_cfg->valid_bit_mask[i])
6369                                 goto mask_err;
6370                 }
6371         }
6372
6373         return 0;
6374
6375 mask_err:
6376         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6377
6378         return -EINVAL;
6379 }
6380
6381 /*
6382  * Set global configurations of hash function type and symmetric hash enable
6383  * per flow type (pctype). Note any modifying global configuration will affect
6384  * all the ports on the same NIC.
6385  */
6386 static int
6387 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6388                                    struct rte_eth_hash_global_conf *g_cfg)
6389 {
6390         int ret;
6391         uint16_t i;
6392         uint32_t reg;
6393         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6394         enum i40e_filter_pctype pctype;
6395
6396         /* Check the input parameters */
6397         ret = i40e_hash_global_config_check(g_cfg);
6398         if (ret < 0)
6399                 return ret;
6400
6401         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6402                 if (!(mask0 & (1UL << i)))
6403                         continue;
6404                 mask0 &= ~(1UL << i);
6405                 pctype = i40e_flowtype_to_pctype(i);
6406                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6407                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6408                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6409         }
6410
6411         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6412         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6413                 /* Toeplitz */
6414                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6415                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6416                                                                 "Toeplitz");
6417                         goto out;
6418                 }
6419                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6420         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6421                 /* Simple XOR */
6422                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6423                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6424                                                         "Simple XOR");
6425                         goto out;
6426                 }
6427                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6428         } else
6429                 /* Use the default, and keep it as it is */
6430                 goto out;
6431
6432         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6433
6434 out:
6435         I40E_WRITE_FLUSH(hw);
6436
6437         return 0;
6438 }
6439
6440 /**
6441  * Valid input sets for hash and flow director filters per PCTYPE
6442  */
6443 static uint64_t
6444 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6445                 enum rte_filter_type filter)
6446 {
6447         uint64_t valid;
6448
6449         static const uint64_t valid_hash_inset_table[] = {
6450                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6451                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6452                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6453                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6454                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6455                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6456                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6457                         I40E_INSET_FLEX_PAYLOAD,
6458                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6459                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6460                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6461                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6462                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6463                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6464                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6465                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6466                         I40E_INSET_FLEX_PAYLOAD,
6467                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6468                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6469                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6470                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6471                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6472                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6473                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6474                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6475                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6476                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6477                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6478                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6479                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6480                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6481                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6482                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6483                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6484                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6485                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6486                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6487                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6488                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6489                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6490                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6491                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6492                         I40E_INSET_FLEX_PAYLOAD,
6493                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6494                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6495                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6496                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6497                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6498                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6499                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6500                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6501                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6502                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6503                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6504                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6505                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6506                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6507                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6508                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6509                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6510                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6511                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6512                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6513                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6514                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6515                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6516                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6517                         I40E_INSET_FLEX_PAYLOAD,
6518                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6519                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6520                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6521                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6522                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6523                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6524                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6525                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6526                         I40E_INSET_FLEX_PAYLOAD,
6527                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6528                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6529                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6530                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6531                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6532                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6533                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6534                         I40E_INSET_FLEX_PAYLOAD,
6535                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6536                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6537                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6538                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6539                         I40E_INSET_FLEX_PAYLOAD,
6540         };
6541
6542         /**
6543          * Flow director supports only fields defined in
6544          * union rte_eth_fdir_flow.
6545          */
6546         static const uint64_t valid_fdir_inset_table[] = {
6547                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6548                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6549                 I40E_INSET_FLEX_PAYLOAD,
6550                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6551                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6552                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6553                 I40E_INSET_FLEX_PAYLOAD,
6554                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6555                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6556                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6557                 I40E_INSET_FLEX_PAYLOAD,
6558                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6559                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6560                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6561                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6562                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6563                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6564                 I40E_INSET_FLEX_PAYLOAD,
6565                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6566                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6567                 I40E_INSET_FLEX_PAYLOAD,
6568                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6569                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6570                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6571                 I40E_INSET_FLEX_PAYLOAD,
6572                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6573                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6574                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6575                 I40E_INSET_FLEX_PAYLOAD,
6576                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6577                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6578                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6579                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6580                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6581                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6582                 I40E_INSET_FLEX_PAYLOAD,
6583                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6584                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6585         };
6586
6587         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6588                 return 0;
6589         if (filter == RTE_ETH_FILTER_HASH)
6590                 valid = valid_hash_inset_table[pctype];
6591         else
6592                 valid = valid_fdir_inset_table[pctype];
6593
6594         return valid;
6595 }
6596
6597 /**
6598  * Validate if the input set is allowed for a specific PCTYPE
6599  */
6600 static int
6601 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6602                 enum rte_filter_type filter, uint64_t inset)
6603 {
6604         uint64_t valid;
6605
6606         valid = i40e_get_valid_input_set(pctype, filter);
6607         if (inset & (~valid))
6608                 return -EINVAL;
6609
6610         return 0;
6611 }
6612
6613 /* default input set fields combination per pctype */
6614 static uint64_t
6615 i40e_get_default_input_set(uint16_t pctype)
6616 {
6617         static const uint64_t default_inset_table[] = {
6618                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6619                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6620                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6621                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6622                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6623                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6624                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6625                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6626                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6627                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6628                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6629                         I40E_INSET_SCTP_VT,
6630                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6631                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6632                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6633                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6634                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6635                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6636                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6637                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6638                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6639                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6640                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6641                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6642                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6643                         I40E_INSET_SCTP_VT,
6644                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6645                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6646                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6647                         I40E_INSET_LAST_ETHER_TYPE,
6648         };
6649
6650         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6651                 return 0;
6652
6653         return default_inset_table[pctype];
6654 }
6655
6656 /**
6657  * Parse the input set from index to logical bit masks
6658  */
6659 static int
6660 i40e_parse_input_set(uint64_t *inset,
6661                      enum i40e_filter_pctype pctype,
6662                      enum rte_eth_input_set_field *field,
6663                      uint16_t size)
6664 {
6665         uint16_t i, j;
6666         int ret = -EINVAL;
6667
6668         static const struct {
6669                 enum rte_eth_input_set_field field;
6670                 uint64_t inset;
6671         } inset_convert_table[] = {
6672                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6673                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6674                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6675                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6676                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6677                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6678                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6679                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6680                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6681                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6682                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6683                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6684                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6685                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6686                         I40E_INSET_IPV6_NEXT_HDR},
6687                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6688                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6689                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6690                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6691                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6692                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6693                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6694                         I40E_INSET_SCTP_VT},
6695                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6696                         I40E_INSET_TUNNEL_DMAC},
6697                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6698                         I40E_INSET_VLAN_TUNNEL},
6699                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6700                         I40E_INSET_TUNNEL_ID},
6701                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6702                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6703                         I40E_INSET_FLEX_PAYLOAD_W1},
6704                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6705                         I40E_INSET_FLEX_PAYLOAD_W2},
6706                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6707                         I40E_INSET_FLEX_PAYLOAD_W3},
6708                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6709                         I40E_INSET_FLEX_PAYLOAD_W4},
6710                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6711                         I40E_INSET_FLEX_PAYLOAD_W5},
6712                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6713                         I40E_INSET_FLEX_PAYLOAD_W6},
6714                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6715                         I40E_INSET_FLEX_PAYLOAD_W7},
6716                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6717                         I40E_INSET_FLEX_PAYLOAD_W8},
6718         };
6719
6720         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6721                 return ret;
6722
6723         /* Only one item allowed for default or all */
6724         if (size == 1) {
6725                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6726                         *inset = i40e_get_default_input_set(pctype);
6727                         return 0;
6728                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6729                         *inset = I40E_INSET_NONE;
6730                         return 0;
6731                 }
6732         }
6733
6734         for (i = 0, *inset = 0; i < size; i++) {
6735                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6736                         if (field[i] == inset_convert_table[j].field) {
6737                                 *inset |= inset_convert_table[j].inset;
6738                                 break;
6739                         }
6740                 }
6741
6742                 /* It contains unsupported input set, return immediately */
6743                 if (j == RTE_DIM(inset_convert_table))
6744                         return ret;
6745         }
6746
6747         return 0;
6748 }
6749
6750 /**
6751  * Translate the input set from bit masks to register aware bit masks
6752  * and vice versa
6753  */
6754 static uint64_t
6755 i40e_translate_input_set_reg(uint64_t input)
6756 {
6757         uint64_t val = 0;
6758         uint16_t i;
6759
6760         static const struct {
6761                 uint64_t inset;
6762                 uint64_t inset_reg;
6763         } inset_map[] = {
6764                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6765                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6766                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6767                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6768                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6769                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6770                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6771                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6772                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6773                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6774                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6775                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6776                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6777                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6778                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6779                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6780                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6781                 {I40E_INSET_TUNNEL_DMAC,
6782                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6783                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6784                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6785                 {I40E_INSET_TUNNEL_SRC_PORT,
6786                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6787                 {I40E_INSET_TUNNEL_DST_PORT,
6788                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6789                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6790                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6791                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6792                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6793                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6794                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6795                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6796                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6797                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6798         };
6799
6800         if (input == 0)
6801                 return val;
6802
6803         /* Translate input set to register aware inset */
6804         for (i = 0; i < RTE_DIM(inset_map); i++) {
6805                 if (input & inset_map[i].inset)
6806                         val |= inset_map[i].inset_reg;
6807         }
6808
6809         return val;
6810 }
6811
6812 static uint8_t
6813 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6814 {
6815         uint8_t i, idx = 0;
6816
6817         static const struct {
6818                 uint64_t inset;
6819                 uint32_t mask;
6820         } inset_mask_map[] = {
6821                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6822                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6823                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6824                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6825         };
6826
6827         if (!inset || !mask || !nb_elem)
6828                 return 0;
6829
6830         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6831                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6832                         mask[i] = 0;
6833                 return I40E_INSET_MASK_NUM_REG;
6834         }
6835
6836         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6837                 if (idx >= nb_elem)
6838                         break;
6839                 if (inset & inset_mask_map[i].inset) {
6840                         mask[idx] = inset_mask_map[i].mask;
6841                         idx++;
6842                 }
6843         }
6844
6845         return idx;
6846 }
6847
6848 static uint64_t
6849 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6850                             enum i40e_filter_pctype pctype)
6851 {
6852         uint64_t reg = 0;
6853
6854         if (filter == RTE_ETH_FILTER_HASH) {
6855                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6856                 reg <<= I40E_32_BIT_WIDTH;
6857                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6858         } else if (filter == RTE_ETH_FILTER_FDIR) {
6859                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6860                 reg <<= I40E_32_BIT_WIDTH;
6861                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6862         }
6863
6864         return reg;
6865 }
6866
6867 static void
6868 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6869 {
6870         uint32_t reg = I40E_READ_REG(hw, addr);
6871
6872         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6873         if (reg != val)
6874                 I40E_WRITE_REG(hw, addr, val);
6875         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6876                     (uint32_t)I40E_READ_REG(hw, addr));
6877 }
6878
6879 static int
6880 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6881                          enum i40e_filter_pctype pctype,
6882                          enum rte_filter_input_set_op op,
6883                          uint32_t *mask_reg,
6884                          uint8_t num)
6885 {
6886         uint32_t reg;
6887         uint8_t i;
6888
6889         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6890                 return -EINVAL;
6891
6892         if (op == RTE_ETH_INPUT_SET_SELECT) {
6893                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6894                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6895                                              0);
6896                         if (i >= num)
6897                                 continue;
6898                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6899                                              mask_reg[i]);
6900                 }
6901         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6902                 uint8_t j, count = 0;
6903
6904                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6905                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6906                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6907                                 count++;
6908                 }
6909                 if (count + num > I40E_INSET_MASK_NUM_REG)
6910                         return -EINVAL;
6911
6912                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6913                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6914                                              mask_reg[j]);
6915         }
6916
6917         return 0;
6918 }
6919
6920 static int
6921 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6922                        enum i40e_filter_pctype pctype,
6923                        enum rte_filter_input_set_op op,
6924                        uint32_t *mask_reg,
6925                        uint8_t num)
6926 {
6927         uint32_t reg;
6928         uint8_t i;
6929
6930         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6931                 return -EINVAL;
6932
6933         if (op == RTE_ETH_INPUT_SET_SELECT) {
6934                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6935                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6936                                              0);
6937                         if (i >= num)
6938                                 continue;
6939                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6940                                              mask_reg[i]);
6941                 }
6942         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6943                 uint8_t j, count = 0;
6944
6945                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6946                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6947                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6948                                 count++;
6949                 }
6950                 if (count + num > I40E_INSET_MASK_NUM_REG)
6951                         return -EINVAL;
6952
6953                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6954                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6955                                              mask_reg[j]);
6956         }
6957
6958         return 0;
6959 }
6960
6961 int
6962 i40e_filter_inset_select(struct i40e_hw *hw,
6963                          struct rte_eth_input_set_conf *conf,
6964                          enum rte_filter_type filter)
6965 {
6966         enum i40e_filter_pctype pctype;
6967         uint64_t inset_reg = 0, input_set;
6968         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6969         uint8_t num;
6970         int ret;
6971
6972         if (!hw || !conf) {
6973                 PMD_DRV_LOG(ERR, "Invalid pointer");
6974                 return -EFAULT;
6975         }
6976
6977         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6978         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6979                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6980                             conf->flow_type);
6981                 return -EINVAL;
6982         }
6983         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6984                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6985                 return -EINVAL;
6986         }
6987
6988         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6989                                    conf->inset_size);
6990         if (ret) {
6991                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6992                 return -EINVAL;
6993         }
6994         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6995                 PMD_DRV_LOG(ERR, "Invalid input set");
6996                 return -EINVAL;
6997         }
6998
6999         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7000                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7001         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7002                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7003                 return -EINVAL;
7004         }
7005         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7006                                            I40E_INSET_MASK_NUM_REG);
7007         inset_reg |= i40e_translate_input_set_reg(input_set);
7008
7009         if (filter == RTE_ETH_FILTER_HASH) {
7010                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7011                                                num);
7012                 if (ret)
7013                         return -EINVAL;
7014
7015                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7016                                       (uint32_t)(inset_reg & UINT32_MAX));
7017                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7018                                      (uint32_t)((inset_reg >>
7019                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7020         } else if (filter == RTE_ETH_FILTER_FDIR) {
7021                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7022                                              num);
7023                 if (ret)
7024                         return -EINVAL;
7025
7026                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7027                                       (uint32_t)(inset_reg & UINT32_MAX));
7028                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7029                                      (uint32_t)((inset_reg >>
7030                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7031         } else {
7032                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7033                 return -EINVAL;
7034         }
7035         I40E_WRITE_FLUSH(hw);
7036
7037         return 0;
7038 }
7039
7040 static int
7041 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7042 {
7043         int ret = 0;
7044
7045         if (!hw || !info) {
7046                 PMD_DRV_LOG(ERR, "Invalid pointer");
7047                 return -EFAULT;
7048         }
7049
7050         switch (info->info_type) {
7051         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7052                 i40e_get_symmetric_hash_enable_per_port(hw,
7053                                         &(info->info.enable));
7054                 break;
7055         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7056                 ret = i40e_get_hash_filter_global_config(hw,
7057                                 &(info->info.global_conf));
7058                 break;
7059         default:
7060                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7061                                                         info->info_type);
7062                 ret = -EINVAL;
7063                 break;
7064         }
7065
7066         return ret;
7067 }
7068
7069 static int
7070 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7071 {
7072         int ret = 0;
7073
7074         if (!hw || !info) {
7075                 PMD_DRV_LOG(ERR, "Invalid pointer");
7076                 return -EFAULT;
7077         }
7078
7079         switch (info->info_type) {
7080         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7081                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7082                 break;
7083         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7084                 ret = i40e_set_hash_filter_global_config(hw,
7085                                 &(info->info.global_conf));
7086                 break;
7087         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7088                 ret = i40e_filter_inset_select(hw,
7089                                                &(info->info.input_set_conf),
7090                                                RTE_ETH_FILTER_HASH);
7091                 break;
7092
7093         default:
7094                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7095                                                         info->info_type);
7096                 ret = -EINVAL;
7097                 break;
7098         }
7099
7100         return ret;
7101 }
7102
7103 /* Operations for hash function */
7104 static int
7105 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7106                       enum rte_filter_op filter_op,
7107                       void *arg)
7108 {
7109         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7110         int ret = 0;
7111
7112         switch (filter_op) {
7113         case RTE_ETH_FILTER_NOP:
7114                 break;
7115         case RTE_ETH_FILTER_GET:
7116                 ret = i40e_hash_filter_get(hw,
7117                         (struct rte_eth_hash_filter_info *)arg);
7118                 break;
7119         case RTE_ETH_FILTER_SET:
7120                 ret = i40e_hash_filter_set(hw,
7121                         (struct rte_eth_hash_filter_info *)arg);
7122                 break;
7123         default:
7124                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7125                                                                 filter_op);
7126                 ret = -ENOTSUP;
7127                 break;
7128         }
7129
7130         return ret;
7131 }
7132
7133 /*
7134  * Configure ethertype filter, which can director packet by filtering
7135  * with mac address and ether_type or only ether_type
7136  */
7137 static int
7138 i40e_ethertype_filter_set(struct i40e_pf *pf,
7139                         struct rte_eth_ethertype_filter *filter,
7140                         bool add)
7141 {
7142         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7143         struct i40e_control_filter_stats stats;
7144         uint16_t flags = 0;
7145         int ret;
7146
7147         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7148                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7149                 return -EINVAL;
7150         }
7151         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7152                 filter->ether_type == ETHER_TYPE_IPv6) {
7153                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7154                         " control packet filter.", filter->ether_type);
7155                 return -EINVAL;
7156         }
7157         if (filter->ether_type == ETHER_TYPE_VLAN)
7158                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7159                         " not supported.");
7160
7161         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7162                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7163         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7164                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7165         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7166
7167         memset(&stats, 0, sizeof(stats));
7168         ret = i40e_aq_add_rem_control_packet_filter(hw,
7169                         filter->mac_addr.addr_bytes,
7170                         filter->ether_type, flags,
7171                         pf->main_vsi->seid,
7172                         filter->queue, add, &stats, NULL);
7173
7174         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7175                          " mac_etype_used = %u, etype_used = %u,"
7176                          " mac_etype_free = %u, etype_free = %u\n",
7177                          ret, stats.mac_etype_used, stats.etype_used,
7178                          stats.mac_etype_free, stats.etype_free);
7179         if (ret < 0)
7180                 return -ENOSYS;
7181         return 0;
7182 }
7183
7184 /*
7185  * Handle operations for ethertype filter.
7186  */
7187 static int
7188 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7189                                 enum rte_filter_op filter_op,
7190                                 void *arg)
7191 {
7192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7193         int ret = 0;
7194
7195         if (filter_op == RTE_ETH_FILTER_NOP)
7196                 return ret;
7197
7198         if (arg == NULL) {
7199                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7200                             filter_op);
7201                 return -EINVAL;
7202         }
7203
7204         switch (filter_op) {
7205         case RTE_ETH_FILTER_ADD:
7206                 ret = i40e_ethertype_filter_set(pf,
7207                         (struct rte_eth_ethertype_filter *)arg,
7208                         TRUE);
7209                 break;
7210         case RTE_ETH_FILTER_DELETE:
7211                 ret = i40e_ethertype_filter_set(pf,
7212                         (struct rte_eth_ethertype_filter *)arg,
7213                         FALSE);
7214                 break;
7215         default:
7216                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7217                 ret = -ENOSYS;
7218                 break;
7219         }
7220         return ret;
7221 }
7222
7223 static int
7224 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7225                      enum rte_filter_type filter_type,
7226                      enum rte_filter_op filter_op,
7227                      void *arg)
7228 {
7229         int ret = 0;
7230
7231         if (dev == NULL)
7232                 return -EINVAL;
7233
7234         switch (filter_type) {
7235         case RTE_ETH_FILTER_NONE:
7236                 /* For global configuration */
7237                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7238                 break;
7239         case RTE_ETH_FILTER_HASH:
7240                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7241                 break;
7242         case RTE_ETH_FILTER_MACVLAN:
7243                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7244                 break;
7245         case RTE_ETH_FILTER_ETHERTYPE:
7246                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7247                 break;
7248         case RTE_ETH_FILTER_TUNNEL:
7249                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7250                 break;
7251         case RTE_ETH_FILTER_FDIR:
7252                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7253                 break;
7254         default:
7255                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7256                                                         filter_type);
7257                 ret = -EINVAL;
7258                 break;
7259         }
7260
7261         return ret;
7262 }
7263
7264 /*
7265  * As some registers wouldn't be reset unless a global hardware reset,
7266  * hardware initialization is needed to put those registers into an
7267  * expected initial state.
7268  */
7269 static void
7270 i40e_hw_init(struct i40e_hw *hw)
7271 {
7272         /* clear the PF Queue Filter control register */
7273         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7274
7275         /* Disable symmetric hash per port */
7276         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7277 }
7278
7279 enum i40e_filter_pctype
7280 i40e_flowtype_to_pctype(uint16_t flow_type)
7281 {
7282         static const enum i40e_filter_pctype pctype_table[] = {
7283                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7284                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7285                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7286                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7287                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7288                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7289                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7290                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7291                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7292                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7293                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7294                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7295                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7296                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7297                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7298                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7299                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7300                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7301                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7302         };
7303
7304         return pctype_table[flow_type];
7305 }
7306
7307 uint16_t
7308 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7309 {
7310         static const uint16_t flowtype_table[] = {
7311                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7312                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7313                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7314                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7315                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7316                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7317                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7318                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7319                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7320                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7321                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7322                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7323                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7324                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7325                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7326                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7327                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7328                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7329                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7330         };
7331
7332         return flowtype_table[pctype];
7333 }
7334
7335 /*
7336  * On X710, performance number is far from the expectation on recent firmware
7337  * versions; on XL710, performance number is also far from the expectation on
7338  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7339  * mode is enabled and port MAC address is equal to the packet destination MAC
7340  * address. The fix for this issue may not be integrated in the following
7341  * firmware version. So the workaround in software driver is needed. It needs
7342  * to modify the initial values of 3 internal only registers for both X710 and
7343  * XL710. Note that the values for X710 or XL710 could be different, and the
7344  * workaround can be removed when it is fixed in firmware in the future.
7345  */
7346
7347 /* For both X710 and XL710 */
7348 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7349 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7350
7351 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7352 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7353
7354 /* For X710 */
7355 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7356 /* For XL710 */
7357 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7358 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7359
7360 static void
7361 i40e_configure_registers(struct i40e_hw *hw)
7362 {
7363         static struct {
7364                 uint32_t addr;
7365                 uint64_t val;
7366         } reg_table[] = {
7367                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7368                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7369                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7370         };
7371         uint64_t reg;
7372         uint32_t i;
7373         int ret;
7374
7375         for (i = 0; i < RTE_DIM(reg_table); i++) {
7376                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7377                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7378                                 reg_table[i].val =
7379                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7380                         else /* For X710 */
7381                                 reg_table[i].val =
7382                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7383                 }
7384
7385                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7386                                                         &reg, NULL);
7387                 if (ret < 0) {
7388                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7389                                                         reg_table[i].addr);
7390                         break;
7391                 }
7392                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7393                                                 reg_table[i].addr, reg);
7394                 if (reg == reg_table[i].val)
7395                         continue;
7396
7397                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7398                                                 reg_table[i].val, NULL);
7399                 if (ret < 0) {
7400                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7401                                 "address of 0x%"PRIx32, reg_table[i].val,
7402                                                         reg_table[i].addr);
7403                         break;
7404                 }
7405                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7406                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7407         }
7408 }
7409
7410 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7411 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7412 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7413 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7414 static int
7415 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7416 {
7417         uint32_t reg;
7418         int ret;
7419
7420         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7421                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7422                 return -EINVAL;
7423         }
7424
7425         /* Configure for double VLAN RX stripping */
7426         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7427         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7428                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7429                 ret = i40e_aq_debug_write_register(hw,
7430                                                    I40E_VSI_TSR(vsi->vsi_id),
7431                                                    reg, NULL);
7432                 if (ret < 0) {
7433                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7434                                     vsi->vsi_id);
7435                         return I40E_ERR_CONFIG;
7436                 }
7437         }
7438
7439         /* Configure for double VLAN TX insertion */
7440         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7441         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7442                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7443                 ret = i40e_aq_debug_write_register(hw,
7444                                                    I40E_VSI_L2TAGSTXVALID(
7445                                                    vsi->vsi_id), reg, NULL);
7446                 if (ret < 0) {
7447                         PMD_DRV_LOG(ERR, "Failed to update "
7448                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7449                         return I40E_ERR_CONFIG;
7450                 }
7451         }
7452
7453         return 0;
7454 }
7455
7456 /**
7457  * i40e_aq_add_mirror_rule
7458  * @hw: pointer to the hardware structure
7459  * @seid: VEB seid to add mirror rule to
7460  * @dst_id: destination vsi seid
7461  * @entries: Buffer which contains the entities to be mirrored
7462  * @count: number of entities contained in the buffer
7463  * @rule_id:the rule_id of the rule to be added
7464  *
7465  * Add a mirror rule for a given veb.
7466  *
7467  **/
7468 static enum i40e_status_code
7469 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7470                         uint16_t seid, uint16_t dst_id,
7471                         uint16_t rule_type, uint16_t *entries,
7472                         uint16_t count, uint16_t *rule_id)
7473 {
7474         struct i40e_aq_desc desc;
7475         struct i40e_aqc_add_delete_mirror_rule cmd;
7476         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7477                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7478                 &desc.params.raw;
7479         uint16_t buff_len;
7480         enum i40e_status_code status;
7481
7482         i40e_fill_default_direct_cmd_desc(&desc,
7483                                           i40e_aqc_opc_add_mirror_rule);
7484         memset(&cmd, 0, sizeof(cmd));
7485
7486         buff_len = sizeof(uint16_t) * count;
7487         desc.datalen = rte_cpu_to_le_16(buff_len);
7488         if (buff_len > 0)
7489                 desc.flags |= rte_cpu_to_le_16(
7490                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7491         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7492                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7493         cmd.num_entries = rte_cpu_to_le_16(count);
7494         cmd.seid = rte_cpu_to_le_16(seid);
7495         cmd.destination = rte_cpu_to_le_16(dst_id);
7496
7497         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7498         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7499         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7500                          "rule_id = %u"
7501                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7502                          hw->aq.asq_last_status, resp->rule_id,
7503                          resp->mirror_rules_used, resp->mirror_rules_free);
7504         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7505
7506         return status;
7507 }
7508
7509 /**
7510  * i40e_aq_del_mirror_rule
7511  * @hw: pointer to the hardware structure
7512  * @seid: VEB seid to add mirror rule to
7513  * @entries: Buffer which contains the entities to be mirrored
7514  * @count: number of entities contained in the buffer
7515  * @rule_id:the rule_id of the rule to be delete
7516  *
7517  * Delete a mirror rule for a given veb.
7518  *
7519  **/
7520 static enum i40e_status_code
7521 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7522                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7523                 uint16_t count, uint16_t rule_id)
7524 {
7525         struct i40e_aq_desc desc;
7526         struct i40e_aqc_add_delete_mirror_rule cmd;
7527         uint16_t buff_len = 0;
7528         enum i40e_status_code status;
7529         void *buff = NULL;
7530
7531         i40e_fill_default_direct_cmd_desc(&desc,
7532                                           i40e_aqc_opc_delete_mirror_rule);
7533         memset(&cmd, 0, sizeof(cmd));
7534         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7535                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7536                                                           I40E_AQ_FLAG_RD));
7537                 cmd.num_entries = count;
7538                 buff_len = sizeof(uint16_t) * count;
7539                 desc.datalen = rte_cpu_to_le_16(buff_len);
7540                 buff = (void *)entries;
7541         } else
7542                 /* rule id is filled in destination field for deleting mirror rule */
7543                 cmd.destination = rte_cpu_to_le_16(rule_id);
7544
7545         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7546                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7547         cmd.seid = rte_cpu_to_le_16(seid);
7548
7549         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7550         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7551
7552         return status;
7553 }
7554
7555 /**
7556  * i40e_mirror_rule_set
7557  * @dev: pointer to the hardware structure
7558  * @mirror_conf: mirror rule info
7559  * @sw_id: mirror rule's sw_id
7560  * @on: enable/disable
7561  *
7562  * set a mirror rule.
7563  *
7564  **/
7565 static int
7566 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7567                         struct rte_eth_mirror_conf *mirror_conf,
7568                         uint8_t sw_id, uint8_t on)
7569 {
7570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7571         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7572         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7573         struct i40e_mirror_rule *parent = NULL;
7574         uint16_t seid, dst_seid, rule_id;
7575         uint16_t i, j = 0;
7576         int ret;
7577
7578         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7579
7580         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7581                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7582                         " without veb or vfs.");
7583                 return -ENOSYS;
7584         }
7585         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7586                 PMD_DRV_LOG(ERR, "mirror table is full.");
7587                 return -ENOSPC;
7588         }
7589         if (mirror_conf->dst_pool > pf->vf_num) {
7590                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7591                                  mirror_conf->dst_pool);
7592                 return -EINVAL;
7593         }
7594
7595         seid = pf->main_vsi->veb->seid;
7596
7597         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7598                 if (sw_id <= it->index) {
7599                         mirr_rule = it;
7600                         break;
7601                 }
7602                 parent = it;
7603         }
7604         if (mirr_rule && sw_id == mirr_rule->index) {
7605                 if (on) {
7606                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7607                         return -EEXIST;
7608                 } else {
7609                         ret = i40e_aq_del_mirror_rule(hw, seid,
7610                                         mirr_rule->rule_type,
7611                                         mirr_rule->entries,
7612                                         mirr_rule->num_entries, mirr_rule->id);
7613                         if (ret < 0) {
7614                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7615                                                    " ret = %d, aq_err = %d.",
7616                                                    ret, hw->aq.asq_last_status);
7617                                 return -ENOSYS;
7618                         }
7619                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7620                         rte_free(mirr_rule);
7621                         pf->nb_mirror_rule--;
7622                         return 0;
7623                 }
7624         } else if (!on) {
7625                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7626                 return -ENOENT;
7627         }
7628
7629         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7630                                 sizeof(struct i40e_mirror_rule) , 0);
7631         if (!mirr_rule) {
7632                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7633                 return I40E_ERR_NO_MEMORY;
7634         }
7635         switch (mirror_conf->rule_type) {
7636         case ETH_MIRROR_VLAN:
7637                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7638                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7639                                 mirr_rule->entries[j] =
7640                                         mirror_conf->vlan.vlan_id[i];
7641                                 j++;
7642                         }
7643                 }
7644                 if (j == 0) {
7645                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7646                         rte_free(mirr_rule);
7647                         return -EINVAL;
7648                 }
7649                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7650                 break;
7651         case ETH_MIRROR_VIRTUAL_POOL_UP:
7652         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7653                 /* check if the specified pool bit is out of range */
7654                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7655                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7656                         rte_free(mirr_rule);
7657                         return -EINVAL;
7658                 }
7659                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7660                         if (mirror_conf->pool_mask & (1ULL << i)) {
7661                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7662                                 j++;
7663                         }
7664                 }
7665                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7666                         /* add pf vsi to entries */
7667                         mirr_rule->entries[j] = pf->main_vsi_seid;
7668                         j++;
7669                 }
7670                 if (j == 0) {
7671                         PMD_DRV_LOG(ERR, "pool is not specified.");
7672                         rte_free(mirr_rule);
7673                         return -EINVAL;
7674                 }
7675                 /* egress and ingress in aq commands means from switch but not port */
7676                 mirr_rule->rule_type =
7677                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7678                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7679                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7680                 break;
7681         case ETH_MIRROR_UPLINK_PORT:
7682                 /* egress and ingress in aq commands means from switch but not port*/
7683                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7684                 break;
7685         case ETH_MIRROR_DOWNLINK_PORT:
7686                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7687                 break;
7688         default:
7689                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7690                         mirror_conf->rule_type);
7691                 rte_free(mirr_rule);
7692                 return -EINVAL;
7693         }
7694
7695         /* If the dst_pool is equal to vf_num, consider it as PF */
7696         if (mirror_conf->dst_pool == pf->vf_num)
7697                 dst_seid = pf->main_vsi_seid;
7698         else
7699                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7700
7701         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7702                                       mirr_rule->rule_type, mirr_rule->entries,
7703                                       j, &rule_id);
7704         if (ret < 0) {
7705                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7706                                    " ret = %d, aq_err = %d.",
7707                                    ret, hw->aq.asq_last_status);
7708                 rte_free(mirr_rule);
7709                 return -ENOSYS;
7710         }
7711
7712         mirr_rule->index = sw_id;
7713         mirr_rule->num_entries = j;
7714         mirr_rule->id = rule_id;
7715         mirr_rule->dst_vsi_seid = dst_seid;
7716
7717         if (parent)
7718                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7719         else
7720                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7721
7722         pf->nb_mirror_rule++;
7723         return 0;
7724 }
7725
7726 /**
7727  * i40e_mirror_rule_reset
7728  * @dev: pointer to the device
7729  * @sw_id: mirror rule's sw_id
7730  *
7731  * reset a mirror rule.
7732  *
7733  **/
7734 static int
7735 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7736 {
7737         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7739         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7740         uint16_t seid;
7741         int ret;
7742
7743         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7744
7745         seid = pf->main_vsi->veb->seid;
7746
7747         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7748                 if (sw_id == it->index) {
7749                         mirr_rule = it;
7750                         break;
7751                 }
7752         }
7753         if (mirr_rule) {
7754                 ret = i40e_aq_del_mirror_rule(hw, seid,
7755                                 mirr_rule->rule_type,
7756                                 mirr_rule->entries,
7757                                 mirr_rule->num_entries, mirr_rule->id);
7758                 if (ret < 0) {
7759                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7760                                            " status = %d, aq_err = %d.",
7761                                            ret, hw->aq.asq_last_status);
7762                         return -ENOSYS;
7763                 }
7764                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7765                 rte_free(mirr_rule);
7766                 pf->nb_mirror_rule--;
7767         } else {
7768                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7769                 return -ENOENT;
7770         }
7771         return 0;
7772 }
7773
7774 static int
7775 i40e_timesync_enable(struct rte_eth_dev *dev)
7776 {
7777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7778         struct rte_eth_link *link = &dev->data->dev_link;
7779         uint32_t tsync_ctl_l;
7780         uint32_t tsync_ctl_h;
7781         uint32_t tsync_inc_l;
7782         uint32_t tsync_inc_h;
7783
7784         switch (link->link_speed) {
7785         case ETH_LINK_SPEED_40G:
7786                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7787                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7788                 break;
7789         case ETH_LINK_SPEED_10G:
7790                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7791                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7792                 break;
7793         case ETH_LINK_SPEED_1000:
7794                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7795                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7796                 break;
7797         default:
7798                 tsync_inc_l = 0x0;
7799                 tsync_inc_h = 0x0;
7800         }
7801
7802         /* Clear timesync registers. */
7803         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7804         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7805         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7806         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7807         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7808         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7809         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7810
7811         /* Set the timesync increment value. */
7812         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7813         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7814
7815         /* Enable timestamping of PTP packets. */
7816         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7817         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7818
7819         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7820         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7821         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7822
7823         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7824         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7825
7826         return 0;
7827 }
7828
7829 static int
7830 i40e_timesync_disable(struct rte_eth_dev *dev)
7831 {
7832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7833         uint32_t tsync_ctl_l;
7834         uint32_t tsync_ctl_h;
7835
7836         /* Disable timestamping of transmitted PTP packets. */
7837         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7838         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7839
7840         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7841         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7842
7843         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7844         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7845
7846         /* Set the timesync increment value. */
7847         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7848         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7849
7850         return 0;
7851 }
7852
7853 static int
7854 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7855                                 struct timespec *timestamp, uint32_t flags)
7856 {
7857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7858         uint32_t sync_status;
7859         uint32_t rx_stmpl;
7860         uint32_t rx_stmph;
7861         uint32_t index = flags & 0x03;
7862
7863         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7864         if ((sync_status & (1 << index)) == 0)
7865                 return -EINVAL;
7866
7867         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7868         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7869
7870         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7871         timestamp->tv_nsec = 0;
7872
7873         return  0;
7874 }
7875
7876 static int
7877 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7878                                 struct timespec *timestamp)
7879 {
7880         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7881         uint32_t sync_status;
7882         uint32_t tx_stmpl;
7883         uint32_t tx_stmph;
7884
7885         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7886         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7887                 return -EINVAL;
7888
7889         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7890         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7891
7892         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7893         timestamp->tv_nsec = 0;
7894
7895         return  0;
7896 }
7897
7898 /*
7899  * i40e_parse_dcb_configure - parse dcb configure from user
7900  * @dev: the device being configured
7901  * @dcb_cfg: pointer of the result of parse
7902  * @*tc_map: bit map of enabled traffic classes
7903  *
7904  * Returns 0 on success, negative value on failure
7905  */
7906 static int
7907 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7908                          struct i40e_dcbx_config *dcb_cfg,
7909                          uint8_t *tc_map)
7910 {
7911         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7912         uint8_t i, tc_bw, bw_lf;
7913
7914         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7915
7916         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7917         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7918                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7919                 return -EINVAL;
7920         }
7921
7922         /* assume each tc has the same bw */
7923         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7924         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7925                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7926         /* to ensure the sum of tcbw is equal to 100 */
7927         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7928         for (i = 0; i < bw_lf; i++)
7929                 dcb_cfg->etscfg.tcbwtable[i]++;
7930
7931         /* assume each tc has the same Transmission Selection Algorithm */
7932         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7933                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7934
7935         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7936                 dcb_cfg->etscfg.prioritytable[i] =
7937                                 dcb_rx_conf->dcb_tc[i];
7938
7939         /* FW needs one App to configure HW */
7940         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7941         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7942         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7943         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7944
7945         if (dcb_rx_conf->nb_tcs == 0)
7946                 *tc_map = 1; /* tc0 only */
7947         else
7948                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7949
7950         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7951                 dcb_cfg->pfc.willing = 0;
7952                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7953                 dcb_cfg->pfc.pfcenable = *tc_map;
7954         }
7955         return 0;
7956 }
7957
7958 /*
7959  * i40e_vsi_get_bw_info - Query VSI BW Information
7960  * @vsi: the VSI being queried
7961  *
7962  * Returns 0 on success, negative value on failure
7963  */
7964 static enum i40e_status_code
7965 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7966 {
7967         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7968         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7969         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7970         enum i40e_status_code ret;
7971         int i;
7972         uint32_t tc_bw_max;
7973
7974         /* Get the VSI level BW configuration */
7975         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7976         if (ret) {
7977                 PMD_INIT_LOG(ERR,
7978                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
7979                          i40e_stat_str(hw, ret),
7980                          i40e_aq_str(hw, hw->aq.asq_last_status));
7981                 return ret;
7982         }
7983
7984         /* Get the VSI level BW configuration per TC */
7985         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7986                                                   NULL);
7987         if (ret) {
7988                 PMD_INIT_LOG(ERR,
7989                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7990                          i40e_stat_str(hw, ret),
7991                          i40e_aq_str(hw, hw->aq.asq_last_status));
7992                 return ret;
7993         }
7994
7995         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7996                 PMD_INIT_LOG(WARNING,
7997                          "Enabled TCs mismatch from querying VSI BW info"
7998                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7999                          bw_ets_config.tc_valid_bits);
8000                 /* Still continuing */
8001         }
8002
8003         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
8004         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
8005         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
8006                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
8007         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8008                 vsi->bw_info.bw_ets_share_credits[i] =
8009                                 bw_ets_config.share_credits[i];
8010                 vsi->bw_info.bw_ets_limit_credits[i] =
8011                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
8012                 /* 3 bits out of 4 for each TC */
8013                 vsi->bw_info.bw_ets_max_quanta[i] =
8014                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
8015                 PMD_INIT_LOG(DEBUG,
8016                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
8017                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
8018         }
8019
8020         return ret;
8021 }
8022
8023 static enum i40e_status_code
8024 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8025                               struct i40e_aqc_vsi_properties_data *info,
8026                               uint8_t enabled_tcmap)
8027 {
8028         enum i40e_status_code ret;
8029         int i, total_tc = 0;
8030         uint16_t qpnum_per_tc, bsf, qp_idx;
8031         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8032
8033         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8034         if (ret != I40E_SUCCESS)
8035                 return ret;
8036
8037         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8038                 if (enabled_tcmap & (1 << i))
8039                         total_tc++;
8040         }
8041         if (total_tc == 0)
8042                 total_tc = 1;
8043         vsi->enabled_tc = enabled_tcmap;
8044
8045         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8046         /* Number of queues per enabled TC */
8047         if (qpnum_per_tc == 0) {
8048                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8049                 return I40E_ERR_INVALID_QP_ID;
8050         }
8051         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8052                                 I40E_MAX_Q_PER_TC);
8053         bsf = rte_bsf32(qpnum_per_tc);
8054
8055         /**
8056          * Configure TC and queue mapping parameters, for enabled TC,
8057          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8058          * default queue will serve it.
8059          */
8060         qp_idx = 0;
8061         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8062                 if (vsi->enabled_tc & (1 << i)) {
8063                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8064                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8065                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8066                         qp_idx += qpnum_per_tc;
8067                 } else
8068                         info->tc_mapping[i] = 0;
8069         }
8070
8071         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8072         if (vsi->type == I40E_VSI_SRIOV) {
8073                 info->mapping_flags |=
8074                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8075                 for (i = 0; i < vsi->nb_qps; i++)
8076                         info->queue_mapping[i] =
8077                                 rte_cpu_to_le_16(vsi->base_queue + i);
8078         } else {
8079                 info->mapping_flags |=
8080                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8081                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8082         }
8083         info->valid_sections |=
8084                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8085
8086         return I40E_SUCCESS;
8087 }
8088
8089 /*
8090  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8091  * @vsi: VSI to be configured
8092  * @tc_map: enabled TC bitmap
8093  *
8094  * Returns 0 on success, negative value on failure
8095  */
8096 static enum i40e_status_code
8097 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8098 {
8099         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8100         struct i40e_vsi_context ctxt;
8101         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8102         enum i40e_status_code ret = I40E_SUCCESS;
8103         int i;
8104
8105         /* Check if enabled_tc is same as existing or new TCs */
8106         if (vsi->enabled_tc == tc_map)
8107                 return ret;
8108
8109         /* configure tc bandwidth */
8110         memset(&bw_data, 0, sizeof(bw_data));
8111         bw_data.tc_valid_bits = tc_map;
8112         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8113         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8114                 if (tc_map & BIT_ULL(i))
8115                         bw_data.tc_bw_credits[i] = 1;
8116         }
8117         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8118         if (ret) {
8119                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8120                         " per TC failed = %d",
8121                         hw->aq.asq_last_status);
8122                 goto out;
8123         }
8124         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8125                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8126
8127         /* Update Queue Pairs Mapping for currently enabled UPs */
8128         ctxt.seid = vsi->seid;
8129         ctxt.pf_num = hw->pf_id;
8130         ctxt.vf_num = 0;
8131         ctxt.uplink_seid = vsi->uplink_seid;
8132         ctxt.info = vsi->info;
8133         i40e_get_cap(hw);
8134         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8135         if (ret)
8136                 goto out;
8137
8138         /* Update the VSI after updating the VSI queue-mapping information */
8139         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8140         if (ret) {
8141                 PMD_INIT_LOG(ERR, "Failed to configure "
8142                             "TC queue mapping = %d",
8143                             hw->aq.asq_last_status);
8144                 goto out;
8145         }
8146         /* update the local VSI info with updated queue map */
8147         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8148                                         sizeof(vsi->info.tc_mapping));
8149         (void)rte_memcpy(&vsi->info.queue_mapping,
8150                         &ctxt.info.queue_mapping,
8151                 sizeof(vsi->info.queue_mapping));
8152         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8153         vsi->info.valid_sections = 0;
8154
8155         /* Update current VSI BW information */
8156         ret = i40e_vsi_get_bw_info(vsi);
8157         if (ret) {
8158                 PMD_INIT_LOG(ERR,
8159                          "Failed updating vsi bw info, err %s aq_err %s",
8160                          i40e_stat_str(hw, ret),
8161                          i40e_aq_str(hw, hw->aq.asq_last_status));
8162                 goto out;
8163         }
8164
8165         vsi->enabled_tc = tc_map;
8166
8167 out:
8168         return ret;
8169 }
8170
8171 /*
8172  * i40e_dcb_hw_configure - program the dcb setting to hw
8173  * @pf: pf the configuration is taken on
8174  * @new_cfg: new configuration
8175  * @tc_map: enabled TC bitmap
8176  *
8177  * Returns 0 on success, negative value on failure
8178  */
8179 static enum i40e_status_code
8180 i40e_dcb_hw_configure(struct i40e_pf *pf,
8181                       struct i40e_dcbx_config *new_cfg,
8182                       uint8_t tc_map)
8183 {
8184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8185         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8186         struct i40e_vsi *main_vsi = pf->main_vsi;
8187         struct i40e_vsi_list *vsi_list;
8188         enum i40e_status_code ret;
8189         int i;
8190         uint32_t val;
8191
8192         /* Use the FW API if FW > v4.4*/
8193         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8194                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8195                                   " to configure DCB");
8196                 return I40E_ERR_FIRMWARE_API_VERSION;
8197         }
8198
8199         /* Check if need reconfiguration */
8200         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8201                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8202                 return I40E_SUCCESS;
8203         }
8204
8205         /* Copy the new config to the current config */
8206         *old_cfg = *new_cfg;
8207         old_cfg->etsrec = old_cfg->etscfg;
8208         ret = i40e_set_dcb_config(hw);
8209         if (ret) {
8210                 PMD_INIT_LOG(ERR,
8211                          "Set DCB Config failed, err %s aq_err %s\n",
8212                          i40e_stat_str(hw, ret),
8213                          i40e_aq_str(hw, hw->aq.asq_last_status));
8214                 return ret;
8215         }
8216         /* set receive Arbiter to RR mode and ETS scheme by default */
8217         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8218                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8219                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8220                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8221                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8222                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8223                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8224                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8225                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8226                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8227                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8228                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8229                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8230         }
8231         /* get local mib to check whether it is configured correctly */
8232         /* IEEE mode */
8233         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8234         /* Get Local DCB Config */
8235         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8236                                      &hw->local_dcbx_config);
8237
8238         /* Update each VSI */
8239         i40e_vsi_config_tc(main_vsi, tc_map);
8240         if (main_vsi->veb) {
8241                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8242                         /* Beside main VSI, only enable default
8243                          * TC for other VSIs
8244                          */
8245                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8246                                                 I40E_DEFAULT_TCMAP);
8247                         if (ret)
8248                                 PMD_INIT_LOG(WARNING,
8249                                          "Failed configuring TC for VSI seid=%d\n",
8250                                          vsi_list->vsi->seid);
8251                         /* continue */
8252                 }
8253         }
8254         return I40E_SUCCESS;
8255 }
8256
8257 /*
8258  * i40e_dcb_init_configure - initial dcb config
8259  * @dev: device being configured
8260  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8261  *
8262  * Returns 0 on success, negative value on failure
8263  */
8264 static int
8265 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8266 {
8267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8268         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8269         int ret = 0;
8270
8271         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8272                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8273                 return -ENOTSUP;
8274         }
8275
8276         /* DCB initialization:
8277          * Update DCB configuration from the Firmware and configure
8278          * LLDP MIB change event.
8279          */
8280         if (sw_dcb == TRUE) {
8281                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8282                 if (ret != I40E_SUCCESS)
8283                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8284
8285                 ret = i40e_init_dcb(hw);
8286                 /* if sw_dcb, lldp agent is stopped, the return from
8287                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8288                  * adminq status.
8289                  */
8290                 if (ret != I40E_SUCCESS &&
8291                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8292                         memset(&hw->local_dcbx_config, 0,
8293                                 sizeof(struct i40e_dcbx_config));
8294                         /* set dcb default configuration */
8295                         hw->local_dcbx_config.etscfg.willing = 0;
8296                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8297                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8298                         hw->local_dcbx_config.etscfg.tsatable[0] =
8299                                                 I40E_IEEE_TSA_ETS;
8300                         hw->local_dcbx_config.etsrec =
8301                                 hw->local_dcbx_config.etscfg;
8302                         hw->local_dcbx_config.pfc.willing = 0;
8303                         hw->local_dcbx_config.pfc.pfccap =
8304                                                 I40E_MAX_TRAFFIC_CLASS;
8305                         /* FW needs one App to configure HW */
8306                         hw->local_dcbx_config.numapps = 1;
8307                         hw->local_dcbx_config.app[0].selector =
8308                                                 I40E_APP_SEL_ETHTYPE;
8309                         hw->local_dcbx_config.app[0].priority = 3;
8310                         hw->local_dcbx_config.app[0].protocolid =
8311                                                 I40E_APP_PROTOID_FCOE;
8312                         ret = i40e_set_dcb_config(hw);
8313                         if (ret) {
8314                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8315                                         " err = %d, aq_err = %d.", ret,
8316                                           hw->aq.asq_last_status);
8317                                 return -ENOSYS;
8318                         }
8319                 } else {
8320                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8321                                           " aq_err = %d.", ret,
8322                                           hw->aq.asq_last_status);
8323                         return -ENOTSUP;
8324                 }
8325         } else {
8326                 ret = i40e_aq_start_lldp(hw, NULL);
8327                 if (ret != I40E_SUCCESS)
8328                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8329
8330                 ret = i40e_init_dcb(hw);
8331                 if (!ret) {
8332                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8333                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8334                                                   " DCBX offload.");
8335                                 return -ENOTSUP;
8336                         }
8337                 } else {
8338                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8339                                           " aq_err = %d.", ret,
8340                                           hw->aq.asq_last_status);
8341                         return -ENOTSUP;
8342                 }
8343         }
8344         return 0;
8345 }
8346
8347 /*
8348  * i40e_dcb_setup - setup dcb related config
8349  * @dev: device being configured
8350  *
8351  * Returns 0 on success, negative value on failure
8352  */
8353 static int
8354 i40e_dcb_setup(struct rte_eth_dev *dev)
8355 {
8356         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8357         struct i40e_dcbx_config dcb_cfg;
8358         uint8_t tc_map = 0;
8359         int ret = 0;
8360
8361         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8362                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8363                 return -ENOTSUP;
8364         }
8365
8366         if (pf->vf_num != 0 ||
8367             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8368                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8369
8370         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8371         if (ret) {
8372                 PMD_INIT_LOG(ERR, "invalid dcb config");
8373                 return -EINVAL;
8374         }
8375         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8376         if (ret) {
8377                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8378                 return -ENOSYS;
8379         }
8380
8381         return 0;
8382 }
8383
8384 static int
8385 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8386                       struct rte_eth_dcb_info *dcb_info)
8387 {
8388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8390         struct i40e_vsi *vsi = pf->main_vsi;
8391         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8392         uint16_t bsf, tc_mapping;
8393         int i;
8394
8395         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8396                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8397         else
8398                 dcb_info->nb_tcs = 1;
8399         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8400                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8401         for (i = 0; i < dcb_info->nb_tcs; i++)
8402                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8403
8404         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8405                 if (vsi->enabled_tc & (1 << i)) {
8406                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8407                         /* only main vsi support multi TCs */
8408                         dcb_info->tc_queue.tc_rxq[0][i].base =
8409                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8410                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8411                         dcb_info->tc_queue.tc_txq[0][i].base =
8412                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8413                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8414                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8415                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8416                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8417                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8418                 }
8419         }
8420
8421         return 0;
8422 }
8423
8424 static int
8425 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8426 {
8427         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8428         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8429         uint16_t interval =
8430                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8431         uint16_t msix_intr;
8432
8433         msix_intr = intr_handle->intr_vec[queue_id];
8434         if (msix_intr == I40E_MISC_VEC_ID)
8435                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8436                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8437                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8438                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8439                                (interval <<
8440                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8441         else
8442                 I40E_WRITE_REG(hw,
8443                                I40E_PFINT_DYN_CTLN(msix_intr -
8444                                                    I40E_RX_VEC_START),
8445                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8446                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8447                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8448                                (interval <<
8449                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8450
8451         I40E_WRITE_FLUSH(hw);
8452         rte_intr_enable(&dev->pci_dev->intr_handle);
8453
8454         return 0;
8455 }
8456
8457 static int
8458 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8459 {
8460         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8461         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8462         uint16_t msix_intr;
8463
8464         msix_intr = intr_handle->intr_vec[queue_id];
8465         if (msix_intr == I40E_MISC_VEC_ID)
8466                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8467         else
8468                 I40E_WRITE_REG(hw,
8469                                I40E_PFINT_DYN_CTLN(msix_intr -
8470                                                    I40E_RX_VEC_START),
8471                                0);
8472         I40E_WRITE_FLUSH(hw);
8473
8474         return 0;
8475 }