drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66
  67 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  68 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  69
  70 #define I40E_CLEAR_PXE_WAIT_MS     200
  71
  72 /* Maximun number of capability elements */
  73 #define I40E_MAX_CAP_ELE_NUM       128
  74
  75 /* Wait count and inteval */
  76 #define I40E_CHK_Q_ENA_COUNT       1000
  77 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  78
  79 /* Maximun number of VSI */
  80 #define I40E_MAX_NUM_VSIS          (384UL)
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 /**
 143  * Below are values for writing un-exposed registers suggested
 144  * by silicon experts
 145  */
 146 /* Destination MAC address */
 147 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 148 /* Source MAC address */
 149 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 150 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 151 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 152 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 154 /* Single VLAN tag in the inner L2 header */
 155 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 156 /* Source IPv4 address */
 157 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 158 /* Destination IPv4 address */
 159 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 160 /* Source IPv4 address for X722 */
 161 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 162 /* Destination IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 164 /* IPv4 Protocol for X722 */
 165 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 166 /* IPv4 Time to Live for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 168 /* IPv4 Type of Service (TOS) */
 169 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 170 /* IPv4 Protocol */
 171 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 172 /* IPv4 Time to Live */
 173 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 174 /* Source IPv6 address */
 175 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 176 /* Destination IPv6 address */
 177 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 178 /* IPv6 Traffic Class (TC) */
 179 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 180 /* IPv6 Next Header */
 181 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 182 /* IPv6 Hop Limit */
 183 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 184 /* Source L4 port */
 185 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 186 /* Destination L4 port */
 187 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 188 /* SCTP verification tag */
 189 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 190 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 191 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 192 /* Source port of tunneling UDP */
 193 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 194 /* Destination port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 196 /* UDP Tunneling ID, NVGRE/GRE key */
 197 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 198 /* Last ether type */
 199 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 200 /* Tunneling outer destination IPv4 address */
 201 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 202 /* Tunneling outer destination IPv6 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 204 /* 1st word of flex payload */
 205 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 206 /* 2nd word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 208 /* 3rd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 210 /* 4th word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 212 /* 5th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 214 /* 6th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 216 /* 7th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 218 /* 8th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 220 /* all 8 words flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 222 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 223
 224 #define I40E_TRANSLATE_INSET 0
 225 #define I40E_TRANSLATE_REG   1
 226
 227 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 228 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 229 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 230 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 231 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 232 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 233
 234 /* PCI offset for querying capability */
 235 #define PCI_DEV_CAP_REG            0xA4
 236 /* PCI offset for enabling/disabling Extended Tag */
 237 #define PCI_DEV_CTRL_REG           0xA8
 238 /* Bit mask of Extended Tag capability */
 239 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 240 /* Bit shift of Extended Tag enable/disable */
 241 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 242 /* Bit mask of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 244
 245 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int i40e_dev_configure(struct rte_eth_dev *dev);
 248 static int i40e_dev_start(struct rte_eth_dev *dev);
 249 static void i40e_dev_stop(struct rte_eth_dev *dev);
 250 static void i40e_dev_close(struct rte_eth_dev *dev);
 251 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 253 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 257 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 258                                struct rte_eth_stats *stats);
 259 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_xstat *xstats, unsigned n);
 261 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 262                                      struct rte_eth_xstat_name *xstats_names,
 263                                      unsigned limit);
 264 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 266                                             uint16_t queue_id,
 267                                             uint8_t stat_idx,
 268                                             uint8_t is_rx);
 269 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 270                                 char *fw_version, size_t fw_size);
 271 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 272                               struct rte_eth_dev_info *dev_info);
 273 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 274                                 uint16_t vlan_id,
 275                                 int on);
 276 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 277                               enum rte_vlan_type vlan_type,
 278                               uint16_t tpid);
 279 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 280 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 281                                       uint16_t queue,
 282                                       int on);
 283 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 284 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 285 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 286 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 287                               struct rte_eth_fc_conf *fc_conf);
 288 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 291                                        struct rte_eth_pfc_conf *pfc_conf);
 292 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 293                           struct ether_addr *mac_addr,
 294                           uint32_t index,
 295                           uint32_t pool);
 296 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 297 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 298                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 299                                     uint16_t reta_size);
 300 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 301                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                    uint16_t reta_size);
 303
 304 static int i40e_get_cap(struct i40e_hw *hw);
 305 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 306 static int i40e_pf_setup(struct i40e_pf *pf);
 307 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 308 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 309 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 310 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 311 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 312                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 313 static void i40e_stat_update_48(struct i40e_hw *hw,
 314                                uint32_t hireg,
 315                                uint32_t loreg,
 316                                bool offset_loaded,
 317                                uint64_t *offset,
 318                                uint64_t *stat);
 319 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 320 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 321                                        void *param);
 322 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 323                                 uint32_t base, uint32_t num);
 324 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 325 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 326                         uint32_t base);
 327 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 328                         uint16_t num);
 329 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 330 static int i40e_veb_release(struct i40e_veb *veb);
 331 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 332                                                 struct i40e_vsi *vsi);
 333 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 334 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 335 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 336                                              struct i40e_macvlan_filter *mv_f,
 337                                              int num,
 338                                              struct ether_addr *addr);
 339 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 340                                              struct i40e_macvlan_filter *mv_f,
 341                                              int num,
 342                                              uint16_t vlan);
 343 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 344 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 345                                     struct rte_eth_rss_conf *rss_conf);
 346 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 347                                       struct rte_eth_rss_conf *rss_conf);
 348 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 349                                         struct rte_eth_udp_tunnel *udp_tunnel);
 350 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 351                                         struct rte_eth_udp_tunnel *udp_tunnel);
 352 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 353 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 354                         struct rte_eth_ethertype_filter *filter,
 355                         bool add);
 356 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 357                                 enum rte_filter_op filter_op,
 358                                 void *arg);
 359 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 360                                 enum rte_filter_type filter_type,
 361                                 enum rte_filter_op filter_op,
 362                                 void *arg);
 363 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 364                                   struct rte_eth_dcb_info *dcb_info);
 365 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 366 static void i40e_configure_registers(struct i40e_hw *hw);
 367 static void i40e_hw_init(struct rte_eth_dev *dev);
 368 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 369 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 370                         struct rte_eth_mirror_conf *mirror_conf,
 371                         uint8_t sw_id, uint8_t on);
 372 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 373
 374 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 375 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 376 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 377                                            struct timespec *timestamp,
 378                                            uint32_t flags);
 379 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 380                                            struct timespec *timestamp);
 381 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 382
 383 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 384
 385 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 386                                    struct timespec *timestamp);
 387 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 388                                     const struct timespec *timestamp);
 389
 390 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 391                                          uint16_t queue_id);
 392 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 393                                           uint16_t queue_id);
 394
 395 static int i40e_get_regs(struct rte_eth_dev *dev,
 396                          struct rte_dev_reg_info *regs);
 397
 398 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 399
 400 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 401                            struct rte_dev_eeprom_info *eeprom);
 402
 403 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 404                                       struct ether_addr *mac_addr);
 405
 406 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 407
 408 static int i40e_ethertype_filter_convert(
 409         const struct rte_eth_ethertype_filter *input,
 410         struct i40e_ethertype_filter *filter);
 411 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 412                                    struct i40e_ethertype_filter *filter);
 413
 414 static int i40e_tunnel_filter_convert(
 415         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 416         struct i40e_tunnel_filter *tunnel_filter);
 417 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 418                                 struct i40e_tunnel_filter *tunnel_filter);
 419
 420 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 421 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 422 static void i40e_filter_restore(struct i40e_pf *pf);
 423
 424 static const struct rte_pci_id pci_id_i40e_map[] = {
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 445         { .vendor_id = 0, /* sentinel */ },
 446 };
 447
 448 static const struct eth_dev_ops i40e_eth_dev_ops = {
 449         .dev_configure                = i40e_dev_configure,
 450         .dev_start                    = i40e_dev_start,
 451         .dev_stop                     = i40e_dev_stop,
 452         .dev_close                    = i40e_dev_close,
 453         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 454         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 455         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 456         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 457         .dev_set_link_up              = i40e_dev_set_link_up,
 458         .dev_set_link_down            = i40e_dev_set_link_down,
 459         .link_update                  = i40e_dev_link_update,
 460         .stats_get                    = i40e_dev_stats_get,
 461         .xstats_get                   = i40e_dev_xstats_get,
 462         .xstats_get_names             = i40e_dev_xstats_get_names,
 463         .stats_reset                  = i40e_dev_stats_reset,
 464         .xstats_reset                 = i40e_dev_stats_reset,
 465         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 466         .fw_version_get               = i40e_fw_version_get,
 467         .dev_infos_get                = i40e_dev_info_get,
 468         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 469         .vlan_filter_set              = i40e_vlan_filter_set,
 470         .vlan_tpid_set                = i40e_vlan_tpid_set,
 471         .vlan_offload_set             = i40e_vlan_offload_set,
 472         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 473         .vlan_pvid_set                = i40e_vlan_pvid_set,
 474         .rx_queue_start               = i40e_dev_rx_queue_start,
 475         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 476         .tx_queue_start               = i40e_dev_tx_queue_start,
 477         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 478         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 479         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 480         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 481         .rx_queue_release             = i40e_dev_rx_queue_release,
 482         .rx_queue_count               = i40e_dev_rx_queue_count,
 483         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 484         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 485         .tx_queue_release             = i40e_dev_tx_queue_release,
 486         .dev_led_on                   = i40e_dev_led_on,
 487         .dev_led_off                  = i40e_dev_led_off,
 488         .flow_ctrl_get                = i40e_flow_ctrl_get,
 489         .flow_ctrl_set                = i40e_flow_ctrl_set,
 490         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 491         .mac_addr_add                 = i40e_macaddr_add,
 492         .mac_addr_remove              = i40e_macaddr_remove,
 493         .reta_update                  = i40e_dev_rss_reta_update,
 494         .reta_query                   = i40e_dev_rss_reta_query,
 495         .rss_hash_update              = i40e_dev_rss_hash_update,
 496         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 497         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 498         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 499         .filter_ctrl                  = i40e_dev_filter_ctrl,
 500         .rxq_info_get                 = i40e_rxq_info_get,
 501         .txq_info_get                 = i40e_txq_info_get,
 502         .mirror_rule_set              = i40e_mirror_rule_set,
 503         .mirror_rule_reset            = i40e_mirror_rule_reset,
 504         .timesync_enable              = i40e_timesync_enable,
 505         .timesync_disable             = i40e_timesync_disable,
 506         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 507         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 508         .get_dcb_info                 = i40e_dev_get_dcb_info,
 509         .timesync_adjust_time         = i40e_timesync_adjust_time,
 510         .timesync_read_time           = i40e_timesync_read_time,
 511         .timesync_write_time          = i40e_timesync_write_time,
 512         .get_reg                      = i40e_get_regs,
 513         .get_eeprom_length            = i40e_get_eeprom_length,
 514         .get_eeprom                   = i40e_get_eeprom,
 515         .mac_addr_set                 = i40e_set_default_mac_addr,
 516         .mtu_set                      = i40e_dev_mtu_set,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static struct eth_driver rte_i40e_pmd = {
 633         .pci_drv = {
 634                 .id_table = pci_id_i40e_map,
 635                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 636                 .probe = rte_eth_dev_pci_probe,
 637                 .remove = rte_eth_dev_pci_remove,
 638         },
 639         .eth_dev_init = eth_i40e_dev_init,
 640         .eth_dev_uninit = eth_i40e_dev_uninit,
 641         .dev_private_size = sizeof(struct i40e_adapter),
 642 };
 643
 644 static inline int
 645 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 646                                      struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = link;
 649         struct rte_eth_link *src = &(dev->data->dev_link);
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 static inline int
 659 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 660                                       struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = &(dev->data->dev_link);
 663         struct rte_eth_link *src = link;
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 673 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 674 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 675
 676 #ifndef I40E_GLQF_ORT
 677 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 678 #endif
 679 #ifndef I40E_GLQF_PIT
 680 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 681 #endif
 682
 683 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 684 {
 685         /*
 686          * Initialize registers for flexible payload, which should be set by NVM.
 687          * This should be removed from code once it is fixed in NVM.
 688          */
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 697         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 698         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 699         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 700         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 701
 702         /* Initialize registers for parsing packet type of QinQ */
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 704         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 705 }
 706
 707 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 708
 709 /*
 710  * Add a ethertype filter to drop all flow control frames transmitted
 711  * from VSIs.
 712 */
 713 static void
 714 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 715 {
 716         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 717         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 718                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 719                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 720         int ret;
 721
 722         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 723                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 724                                 pf->main_vsi_seid, 0,
 725                                 TRUE, NULL, NULL);
 726         if (ret)
 727                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 728                                   " frames from VSIs.");
 729 }
 730
 731 static int
 732 floating_veb_list_handler(__rte_unused const char *key,
 733                           const char *floating_veb_value,
 734                           void *opaque)
 735 {
 736         int idx = 0;
 737         unsigned int count = 0;
 738         char *end = NULL;
 739         int min, max;
 740         bool *vf_floating_veb = opaque;
 741
 742         while (isblank(*floating_veb_value))
 743                 floating_veb_value++;
 744
 745         /* Reset floating VEB configuration for VFs */
 746         for (idx = 0; idx < I40E_MAX_VF; idx++)
 747                 vf_floating_veb[idx] = false;
 748
 749         min = I40E_MAX_VF;
 750         do {
 751                 while (isblank(*floating_veb_value))
 752                         floating_veb_value++;
 753                 if (*floating_veb_value == '\0')
 754                         return -1;
 755                 errno = 0;
 756                 idx = strtoul(floating_veb_value, &end, 10);
 757                 if (errno || end == NULL)
 758                         return -1;
 759                 while (isblank(*end))
 760                         end++;
 761                 if (*end == '-') {
 762                         min = idx;
 763                 } else if ((*end == ';') || (*end == '\0')) {
 764                         max = idx;
 765                         if (min == I40E_MAX_VF)
 766                                 min = idx;
 767                         if (max >= I40E_MAX_VF)
 768                                 max = I40E_MAX_VF - 1;
 769                         for (idx = min; idx <= max; idx++) {
 770                                 vf_floating_veb[idx] = true;
 771                                 count++;
 772                         }
 773                         min = I40E_MAX_VF;
 774                 } else {
 775                         return -1;
 776                 }
 777                 floating_veb_value = end + 1;
 778         } while (*end != '\0');
 779
 780         if (count == 0)
 781                 return -1;
 782
 783         return 0;
 784 }
 785
 786 static void
 787 config_vf_floating_veb(struct rte_devargs *devargs,
 788                        uint16_t floating_veb,
 789                        bool *vf_floating_veb)
 790 {
 791         struct rte_kvargs *kvlist;
 792         int i;
 793         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 794
 795         if (!floating_veb)
 796                 return;
 797         /* All the VFs attach to the floating VEB by default
 798          * when the floating VEB is enabled.
 799          */
 800         for (i = 0; i < I40E_MAX_VF; i++)
 801                 vf_floating_veb[i] = true;
 802
 803         if (devargs == NULL)
 804                 return;
 805
 806         kvlist = rte_kvargs_parse(devargs->args, NULL);
 807         if (kvlist == NULL)
 808                 return;
 809
 810         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 811                 rte_kvargs_free(kvlist);
 812                 return;
 813         }
 814         /* When the floating_veb_list parameter exists, all the VFs
 815          * will attach to the legacy VEB firstly, then configure VFs
 816          * to the floating VEB according to the floating_veb_list.
 817          */
 818         if (rte_kvargs_process(kvlist, floating_veb_list,
 819                                floating_veb_list_handler,
 820                                vf_floating_veb) < 0) {
 821                 rte_kvargs_free(kvlist);
 822                 return;
 823         }
 824         rte_kvargs_free(kvlist);
 825 }
 826
 827 static int
 828 i40e_check_floating_handler(__rte_unused const char *key,
 829                             const char *value,
 830                             __rte_unused void *opaque)
 831 {
 832         if (strcmp(value, "1"))
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 static int
 839 is_floating_veb_supported(struct rte_devargs *devargs)
 840 {
 841         struct rte_kvargs *kvlist;
 842         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 843
 844         if (devargs == NULL)
 845                 return 0;
 846
 847         kvlist = rte_kvargs_parse(devargs->args, NULL);
 848         if (kvlist == NULL)
 849                 return 0;
 850
 851         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 852                 rte_kvargs_free(kvlist);
 853                 return 0;
 854         }
 855         /* Floating VEB is enabled when there's key-value:
 856          * enable_floating_veb=1
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_key,
 859                                i40e_check_floating_handler, NULL) < 0) {
 860                 rte_kvargs_free(kvlist);
 861                 return 0;
 862         }
 863         rte_kvargs_free(kvlist);
 864
 865         return 1;
 866 }
 867
 868 static void
 869 config_floating_veb(struct rte_eth_dev *dev)
 870 {
 871         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874
 875         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 876
 877         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 878                 pf->floating_veb =
 879                         is_floating_veb_supported(pci_dev->device.devargs);
 880                 config_vf_floating_veb(pci_dev->device.devargs,
 881                                        pf->floating_veb,
 882                                        pf->floating_veb_list);
 883         } else {
 884                 pf->floating_veb = false;
 885         }
 886 }
 887
 888 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 889 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 890
 891 static int
 892 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 893 {
 894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 895         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 896         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 897         int ret;
 898
 899         struct rte_hash_parameters ethertype_hash_params = {
 900                 .name = ethertype_hash_name,
 901                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 902                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 903                 .hash_func = rte_hash_crc,
 904         };
 905
 906         /* Initialize ethertype filter rule list and hash */
 907         TAILQ_INIT(&ethertype_rule->ethertype_list);
 908         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 909                  "ethertype_%s", dev->data->name);
 910         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 911         if (!ethertype_rule->hash_table) {
 912                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 913                 return -EINVAL;
 914         }
 915         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 916                                        sizeof(struct i40e_ethertype_filter *) *
 917                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 918                                        0);
 919         if (!ethertype_rule->hash_map) {
 920                 PMD_INIT_LOG(ERR,
 921                              "Failed to allocate memory for ethertype hash map!");
 922                 ret = -ENOMEM;
 923                 goto err_ethertype_hash_map_alloc;
 924         }
 925
 926         return 0;
 927
 928 err_ethertype_hash_map_alloc:
 929         rte_hash_free(ethertype_rule->hash_table);
 930
 931         return ret;
 932 }
 933
 934 static int
 935 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 936 {
 937         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 938         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 939         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 940         int ret;
 941
 942         struct rte_hash_parameters tunnel_hash_params = {
 943                 .name = tunnel_hash_name,
 944                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 945                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 946                 .hash_func = rte_hash_crc,
 947         };
 948
 949         /* Initialize tunnel filter rule list and hash */
 950         TAILQ_INIT(&tunnel_rule->tunnel_list);
 951         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 952                  "tunnel_%s", dev->data->name);
 953         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 954         if (!tunnel_rule->hash_table) {
 955                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 956                 return -EINVAL;
 957         }
 958         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 959                                     sizeof(struct i40e_tunnel_filter *) *
 960                                     I40E_MAX_TUNNEL_FILTER_NUM,
 961                                     0);
 962         if (!tunnel_rule->hash_map) {
 963                 PMD_INIT_LOG(ERR,
 964                              "Failed to allocate memory for tunnel hash map!");
 965                 ret = -ENOMEM;
 966                 goto err_tunnel_hash_map_alloc;
 967         }
 968
 969         return 0;
 970
 971 err_tunnel_hash_map_alloc:
 972         rte_hash_free(tunnel_rule->hash_table);
 973
 974         return ret;
 975 }
 976
 977 static int
 978 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 979 {
 980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 981         struct i40e_fdir_info *fdir_info = &pf->fdir;
 982         char fdir_hash_name[RTE_HASH_NAMESIZE];
 983         int ret;
 984
 985         struct rte_hash_parameters fdir_hash_params = {
 986                 .name = fdir_hash_name,
 987                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 988                 .key_len = sizeof(struct rte_eth_fdir_input),
 989                 .hash_func = rte_hash_crc,
 990         };
 991
 992         /* Initialize flow director filter rule list and hash */
 993         TAILQ_INIT(&fdir_info->fdir_list);
 994         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 995                  "fdir_%s", dev->data->name);
 996         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 997         if (!fdir_info->hash_table) {
 998                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 999                 return -EINVAL;
1000         }
1001         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1002                                           sizeof(struct i40e_fdir_filter *) *
1003                                           I40E_MAX_FDIR_FILTER_NUM,
1004                                           0);
1005         if (!fdir_info->hash_map) {
1006                 PMD_INIT_LOG(ERR,
1007                              "Failed to allocate memory for fdir hash map!");
1008                 ret = -ENOMEM;
1009                 goto err_fdir_hash_map_alloc;
1010         }
1011         return 0;
1012
1013 err_fdir_hash_map_alloc:
1014         rte_hash_free(fdir_info->hash_table);
1015
1016         return ret;
1017 }
1018
1019 static int
1020 eth_i40e_dev_init(struct rte_eth_dev *dev)
1021 {
1022         struct rte_pci_device *pci_dev;
1023         struct rte_intr_handle *intr_handle;
1024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1025         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         struct i40e_vsi *vsi;
1027         int ret;
1028         uint32_t len;
1029         uint8_t aq_fail = 0;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         dev->dev_ops = &i40e_eth_dev_ops;
1034         dev->rx_pkt_burst = i40e_recv_pkts;
1035         dev->tx_pkt_burst = i40e_xmit_pkts;
1036         dev->tx_pkt_prepare = i40e_prep_pkts;
1037
1038         /* for secondary processes, we don't initialise any further as primary
1039          * has already done this work. Only check we don't need a different
1040          * RX function */
1041         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1042                 i40e_set_rx_function(dev);
1043                 i40e_set_tx_function(dev);
1044                 return 0;
1045         }
1046         pci_dev = I40E_DEV_TO_PCI(dev);
1047         intr_handle = &pci_dev->intr_handle;
1048
1049         rte_eth_copy_pci_info(dev, pci_dev);
1050         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1051
1052         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1053         pf->adapter->eth_dev = dev;
1054         pf->dev_data = dev->data;
1055
1056         hw->back = I40E_PF_TO_ADAPTER(pf);
1057         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1058         if (!hw->hw_addr) {
1059                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1060                              "as address is NULL");
1061                 return -ENODEV;
1062         }
1063
1064         hw->vendor_id = pci_dev->id.vendor_id;
1065         hw->device_id = pci_dev->id.device_id;
1066         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1067         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1068         hw->bus.device = pci_dev->addr.devid;
1069         hw->bus.func = pci_dev->addr.function;
1070         hw->adapter_stopped = 0;
1071
1072         /* Make sure all is clean before doing PF reset */
1073         i40e_clear_hw(hw);
1074
1075         /* Initialize the hardware */
1076         i40e_hw_init(dev);
1077
1078         /* Reset here to make sure all is clean for each PF */
1079         ret = i40e_pf_reset(hw);
1080         if (ret) {
1081                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1082                 return ret;
1083         }
1084
1085         /* Initialize the shared code (base driver) */
1086         ret = i40e_init_shared_code(hw);
1087         if (ret) {
1088                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1089                 return ret;
1090         }
1091
1092         /*
1093          * To work around the NVM issue, initialize registers
1094          * for flexible payload and packet type of QinQ by
1095          * software. It should be removed once issues are fixed
1096          * in NVM.
1097          */
1098         i40e_GLQF_reg_init(hw);
1099
1100         /* Initialize the input set for filters (hash and fd) to default value */
1101         i40e_filter_input_set_init(pf);
1102
1103         /* Initialize the parameters for adminq */
1104         i40e_init_adminq_parameter(hw);
1105         ret = i40e_init_adminq(hw);
1106         if (ret != I40E_SUCCESS) {
1107                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1108                 return -EIO;
1109         }
1110         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1111                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1112                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1113                      ((hw->nvm.version >> 12) & 0xf),
1114                      ((hw->nvm.version >> 4) & 0xff),
1115                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1116
1117         /* Need the special FW version to support floating VEB */
1118         config_floating_veb(dev);
1119         /* Clear PXE mode */
1120         i40e_clear_pxe_mode(hw);
1121         ret = i40e_dev_sync_phy_type(hw);
1122         if (ret) {
1123                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1124                 goto err_sync_phy_type;
1125         }
1126         /*
1127          * On X710, performance number is far from the expectation on recent
1128          * firmware versions. The fix for this issue may not be integrated in
1129          * the following firmware version. So the workaround in software driver
1130          * is needed. It needs to modify the initial values of 3 internal only
1131          * registers. Note that the workaround can be removed when it is fixed
1132          * in firmware in the future.
1133          */
1134         i40e_configure_registers(hw);
1135
1136         /* Get hw capabilities */
1137         ret = i40e_get_cap(hw);
1138         if (ret != I40E_SUCCESS) {
1139                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1140                 goto err_get_capabilities;
1141         }
1142
1143         /* Initialize parameters for PF */
1144         ret = i40e_pf_parameter_init(dev);
1145         if (ret != 0) {
1146                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1147                 goto err_parameter_init;
1148         }
1149
1150         /* Initialize the queue management */
1151         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1152         if (ret < 0) {
1153                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1154                 goto err_qp_pool_init;
1155         }
1156         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1157                                 hw->func_caps.num_msix_vectors - 1);
1158         if (ret < 0) {
1159                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1160                 goto err_msix_pool_init;
1161         }
1162
1163         /* Initialize lan hmc */
1164         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1165                                 hw->func_caps.num_rx_qp, 0, 0);
1166         if (ret != I40E_SUCCESS) {
1167                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1168                 goto err_init_lan_hmc;
1169         }
1170
1171         /* Configure lan hmc */
1172         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1173         if (ret != I40E_SUCCESS) {
1174                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1175                 goto err_configure_lan_hmc;
1176         }
1177
1178         /* Get and check the mac address */
1179         i40e_get_mac_addr(hw, hw->mac.addr);
1180         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1181                 PMD_INIT_LOG(ERR, "mac address is not valid");
1182                 ret = -EIO;
1183                 goto err_get_mac_addr;
1184         }
1185         /* Copy the permanent MAC address */
1186         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1187                         (struct ether_addr *) hw->mac.perm_addr);
1188
1189         /* Disable flow control */
1190         hw->fc.requested_mode = I40E_FC_NONE;
1191         i40e_set_fc(hw, &aq_fail, TRUE);
1192
1193         /* Set the global registers with default ether type value */
1194         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1197                              "VLAN ether type");
1198                 goto err_setup_pf_switch;
1199         }
1200
1201         /* PF setup, which includes VSI setup */
1202         ret = i40e_pf_setup(pf);
1203         if (ret) {
1204                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1205                 goto err_setup_pf_switch;
1206         }
1207
1208         /* reset all stats of the device, including pf and main vsi */
1209         i40e_dev_stats_reset(dev);
1210
1211         vsi = pf->main_vsi;
1212
1213         /* Disable double vlan by default */
1214         i40e_vsi_config_double_vlan(vsi, FALSE);
1215
1216         /* Disable S-TAG identification when floating_veb is disabled */
1217         if (!pf->floating_veb) {
1218                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1219                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1220                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1221                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1222                 }
1223         }
1224
1225         if (!vsi->max_macaddrs)
1226                 len = ETHER_ADDR_LEN;
1227         else
1228                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1229
1230         /* Should be after VSI initialized */
1231         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1232         if (!dev->data->mac_addrs) {
1233                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1234                                         "for storing mac address");
1235                 goto err_mac_alloc;
1236         }
1237         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1238                                         &dev->data->mac_addrs[0]);
1239
1240         /* initialize pf host driver to setup SRIOV resource if applicable */
1241         i40e_pf_host_init(dev);
1242
1243         /* register callback func to eal lib */
1244         rte_intr_callback_register(intr_handle,
1245                                    i40e_dev_interrupt_handler, dev);
1246
1247         /* configure and enable device interrupt */
1248         i40e_pf_config_irq0(hw, TRUE);
1249         i40e_pf_enable_irq0(hw);
1250
1251         /* enable uio intr after callback register */
1252         rte_intr_enable(intr_handle);
1253         /*
1254          * Add an ethertype filter to drop all flow control frames transmitted
1255          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1256          * frames to wire.
1257          */
1258         i40e_add_tx_flow_control_drop_filter(pf);
1259
1260         /* Set the max frame size to 0x2600 by default,
1261          * in case other drivers changed the default value.
1262          */
1263         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1264
1265         /* initialize mirror rule list */
1266         TAILQ_INIT(&pf->mirror_list);
1267
1268         /* Init dcb to sw mode by default */
1269         ret = i40e_dcb_init_configure(dev, TRUE);
1270         if (ret != I40E_SUCCESS) {
1271                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1272                 pf->flags &= ~I40E_FLAG_DCB;
1273         }
1274
1275         ret = i40e_init_ethtype_filter_list(dev);
1276         if (ret < 0)
1277                 goto err_init_ethtype_filter_list;
1278         ret = i40e_init_tunnel_filter_list(dev);
1279         if (ret < 0)
1280                 goto err_init_tunnel_filter_list;
1281         ret = i40e_init_fdir_filter_list(dev);
1282         if (ret < 0)
1283                 goto err_init_fdir_filter_list;
1284
1285         return 0;
1286
1287 err_init_fdir_filter_list:
1288         rte_free(pf->tunnel.hash_table);
1289         rte_free(pf->tunnel.hash_map);
1290 err_init_tunnel_filter_list:
1291         rte_free(pf->ethertype.hash_table);
1292         rte_free(pf->ethertype.hash_map);
1293 err_init_ethtype_filter_list:
1294         rte_free(dev->data->mac_addrs);
1295 err_mac_alloc:
1296         i40e_vsi_release(pf->main_vsi);
1297 err_setup_pf_switch:
1298 err_get_mac_addr:
1299 err_configure_lan_hmc:
1300         (void)i40e_shutdown_lan_hmc(hw);
1301 err_init_lan_hmc:
1302         i40e_res_pool_destroy(&pf->msix_pool);
1303 err_msix_pool_init:
1304         i40e_res_pool_destroy(&pf->qp_pool);
1305 err_qp_pool_init:
1306 err_parameter_init:
1307 err_get_capabilities:
1308 err_sync_phy_type:
1309         (void)i40e_shutdown_adminq(hw);
1310
1311         return ret;
1312 }
1313
1314 static void
1315 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1316 {
1317         struct i40e_ethertype_filter *p_ethertype;
1318         struct i40e_ethertype_rule *ethertype_rule;
1319
1320         ethertype_rule = &pf->ethertype;
1321         /* Remove all ethertype filter rules and hash */
1322         if (ethertype_rule->hash_map)
1323                 rte_free(ethertype_rule->hash_map);
1324         if (ethertype_rule->hash_table)
1325                 rte_hash_free(ethertype_rule->hash_table);
1326
1327         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1328                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1329                              p_ethertype, rules);
1330                 rte_free(p_ethertype);
1331         }
1332 }
1333
1334 static void
1335 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1336 {
1337         struct i40e_tunnel_filter *p_tunnel;
1338         struct i40e_tunnel_rule *tunnel_rule;
1339
1340         tunnel_rule = &pf->tunnel;
1341         /* Remove all tunnel director rules and hash */
1342         if (tunnel_rule->hash_map)
1343                 rte_free(tunnel_rule->hash_map);
1344         if (tunnel_rule->hash_table)
1345                 rte_hash_free(tunnel_rule->hash_table);
1346
1347         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1348                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1349                 rte_free(p_tunnel);
1350         }
1351 }
1352
1353 static void
1354 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1355 {
1356         struct i40e_fdir_filter *p_fdir;
1357         struct i40e_fdir_info *fdir_info;
1358
1359         fdir_info = &pf->fdir;
1360         /* Remove all flow director rules and hash */
1361         if (fdir_info->hash_map)
1362                 rte_free(fdir_info->hash_map);
1363         if (fdir_info->hash_table)
1364                 rte_hash_free(fdir_info->hash_table);
1365
1366         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1367                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1368                 rte_free(p_fdir);
1369         }
1370 }
1371
1372 static int
1373 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1374 {
1375         struct i40e_pf *pf;
1376         struct rte_pci_device *pci_dev;
1377         struct rte_intr_handle *intr_handle;
1378         struct i40e_hw *hw;
1379         struct i40e_filter_control_settings settings;
1380         int ret;
1381         uint8_t aq_fail = 0;
1382
1383         PMD_INIT_FUNC_TRACE();
1384
1385         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1386                 return 0;
1387
1388         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1389         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1390         pci_dev = I40E_DEV_TO_PCI(dev);
1391         intr_handle = &pci_dev->intr_handle;
1392
1393         if (hw->adapter_stopped == 0)
1394                 i40e_dev_close(dev);
1395
1396         dev->dev_ops = NULL;
1397         dev->rx_pkt_burst = NULL;
1398         dev->tx_pkt_burst = NULL;
1399
1400         /* Clear PXE mode */
1401         i40e_clear_pxe_mode(hw);
1402
1403         /* Unconfigure filter control */
1404         memset(&settings, 0, sizeof(settings));
1405         ret = i40e_set_filter_control(hw, &settings);
1406         if (ret)
1407                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1408                                         ret);
1409
1410         /* Disable flow control */
1411         hw->fc.requested_mode = I40E_FC_NONE;
1412         i40e_set_fc(hw, &aq_fail, TRUE);
1413
1414         /* uninitialize pf host driver */
1415         i40e_pf_host_uninit(dev);
1416
1417         rte_free(dev->data->mac_addrs);
1418         dev->data->mac_addrs = NULL;
1419
1420         /* disable uio intr before callback unregister */
1421         rte_intr_disable(intr_handle);
1422
1423         /* register callback func to eal lib */
1424         rte_intr_callback_unregister(intr_handle,
1425                                      i40e_dev_interrupt_handler, dev);
1426
1427         i40e_rm_ethtype_filter_list(pf);
1428         i40e_rm_tunnel_filter_list(pf);
1429         i40e_rm_fdir_filter_list(pf);
1430
1431         return 0;
1432 }
1433
1434 static int
1435 i40e_dev_configure(struct rte_eth_dev *dev)
1436 {
1437         struct i40e_adapter *ad =
1438                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1439         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1441         int i, ret;
1442
1443         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1444          * bulk allocation or vector Rx preconditions we will reset it.
1445          */
1446         ad->rx_bulk_alloc_allowed = true;
1447         ad->rx_vec_allowed = true;
1448         ad->tx_simple_allowed = true;
1449         ad->tx_vec_allowed = true;
1450
1451         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1452                 ret = i40e_fdir_setup(pf);
1453                 if (ret != I40E_SUCCESS) {
1454                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1455                         return -ENOTSUP;
1456                 }
1457                 ret = i40e_fdir_configure(dev);
1458                 if (ret < 0) {
1459                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1460                         goto err;
1461                 }
1462         } else
1463                 i40e_fdir_teardown(pf);
1464
1465         ret = i40e_dev_init_vlan(dev);
1466         if (ret < 0)
1467                 goto err;
1468
1469         /* VMDQ setup.
1470          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1471          *  RSS setting have different requirements.
1472          *  General PMD driver call sequence are NIC init, configure,
1473          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1474          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1475          *  applicable. So, VMDQ setting has to be done before
1476          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1477          *  For RSS setting, it will try to calculate actual configured RX queue
1478          *  number, which will be available after rx_queue_setup(). dev_start()
1479          *  function is good to place RSS setup.
1480          */
1481         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1482                 ret = i40e_vmdq_setup(dev);
1483                 if (ret)
1484                         goto err;
1485         }
1486
1487         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1488                 ret = i40e_dcb_setup(dev);
1489                 if (ret) {
1490                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1491                         goto err_dcb;
1492                 }
1493         }
1494
1495         return 0;
1496
1497 err_dcb:
1498         /* need to release vmdq resource if exists */
1499         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1500                 i40e_vsi_release(pf->vmdq[i].vsi);
1501                 pf->vmdq[i].vsi = NULL;
1502         }
1503         rte_free(pf->vmdq);
1504         pf->vmdq = NULL;
1505 err:
1506         /* need to release fdir resource if exists */
1507         i40e_fdir_teardown(pf);
1508         return ret;
1509 }
1510
1511 void
1512 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1513 {
1514         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1515         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1516         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1517         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1518         uint16_t msix_vect = vsi->msix_intr;
1519         uint16_t i;
1520
1521         for (i = 0; i < vsi->nb_qps; i++) {
1522                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1523                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1524                 rte_wmb();
1525         }
1526
1527         if (vsi->type != I40E_VSI_SRIOV) {
1528                 if (!rte_intr_allow_others(intr_handle)) {
1529                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1530                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1531                         I40E_WRITE_REG(hw,
1532                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1533                                        0);
1534                 } else {
1535                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1536                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1537                         I40E_WRITE_REG(hw,
1538                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1539                                                        msix_vect - 1), 0);
1540                 }
1541         } else {
1542                 uint32_t reg;
1543                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1544                         vsi->user_param + (msix_vect - 1);
1545
1546                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1547                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1548         }
1549         I40E_WRITE_FLUSH(hw);
1550 }
1551
1552 static void
1553 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1554                        int base_queue, int nb_queue)
1555 {
1556         int i;
1557         uint32_t val;
1558         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1559
1560         /* Bind all RX queues to allocated MSIX interrupt */
1561         for (i = 0; i < nb_queue; i++) {
1562                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1563                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1564                         ((base_queue + i + 1) <<
1565                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1566                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1567                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1568
1569                 if (i == nb_queue - 1)
1570                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1571                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1572         }
1573
1574         /* Write first RX queue to Link list register as the head element */
1575         if (vsi->type != I40E_VSI_SRIOV) {
1576                 uint16_t interval =
1577                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1578
1579                 if (msix_vect == I40E_MISC_VEC_ID) {
1580                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1581                                        (base_queue <<
1582                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1583                                        (0x0 <<
1584                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1585                         I40E_WRITE_REG(hw,
1586                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1587                                        interval);
1588                 } else {
1589                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1590                                        (base_queue <<
1591                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1592                                        (0x0 <<
1593                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1594                         I40E_WRITE_REG(hw,
1595                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1596                                                        msix_vect - 1),
1597                                        interval);
1598                 }
1599         } else {
1600                 uint32_t reg;
1601
1602                 if (msix_vect == I40E_MISC_VEC_ID) {
1603                         I40E_WRITE_REG(hw,
1604                                        I40E_VPINT_LNKLST0(vsi->user_param),
1605                                        (base_queue <<
1606                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1607                                        (0x0 <<
1608                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1609                 } else {
1610                         /* num_msix_vectors_vf needs to minus irq0 */
1611                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1612                                 vsi->user_param + (msix_vect - 1);
1613
1614                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1615                                        (base_queue <<
1616                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1617                                        (0x0 <<
1618                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1619                 }
1620         }
1621
1622         I40E_WRITE_FLUSH(hw);
1623 }
1624
1625 void
1626 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1627 {
1628         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1629         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1630         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1631         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1632         uint16_t msix_vect = vsi->msix_intr;
1633         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1634         uint16_t queue_idx = 0;
1635         int record = 0;
1636         uint32_t val;
1637         int i;
1638
1639         for (i = 0; i < vsi->nb_qps; i++) {
1640                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1641                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1642         }
1643
1644         /* INTENA flag is not auto-cleared for interrupt */
1645         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1646         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1647                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1648                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1649         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1650
1651         /* VF bind interrupt */
1652         if (vsi->type == I40E_VSI_SRIOV) {
1653                 __vsi_queues_bind_intr(vsi, msix_vect,
1654                                        vsi->base_queue, vsi->nb_qps);
1655                 return;
1656         }
1657
1658         /* PF & VMDq bind interrupt */
1659         if (rte_intr_dp_is_en(intr_handle)) {
1660                 if (vsi->type == I40E_VSI_MAIN) {
1661                         queue_idx = 0;
1662                         record = 1;
1663                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1664                         struct i40e_vsi *main_vsi =
1665                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1666                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1667                         record = 1;
1668                 }
1669         }
1670
1671         for (i = 0; i < vsi->nb_used_qps; i++) {
1672                 if (nb_msix <= 1) {
1673                         if (!rte_intr_allow_others(intr_handle))
1674                                 /* allow to share MISC_VEC_ID */
1675                                 msix_vect = I40E_MISC_VEC_ID;
1676
1677                         /* no enough msix_vect, map all to one */
1678                         __vsi_queues_bind_intr(vsi, msix_vect,
1679                                                vsi->base_queue + i,
1680                                                vsi->nb_used_qps - i);
1681                         for (; !!record && i < vsi->nb_used_qps; i++)
1682                                 intr_handle->intr_vec[queue_idx + i] =
1683                                         msix_vect;
1684                         break;
1685                 }
1686                 /* 1:1 queue/msix_vect mapping */
1687                 __vsi_queues_bind_intr(vsi, msix_vect,
1688                                        vsi->base_queue + i, 1);
1689                 if (!!record)
1690                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1691
1692                 msix_vect++;
1693                 nb_msix--;
1694         }
1695 }
1696
1697 static void
1698 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1699 {
1700         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1701         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1702         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1703         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1704         uint16_t interval = i40e_calc_itr_interval(\
1705                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1706         uint16_t msix_intr, i;
1707
1708         if (rte_intr_allow_others(intr_handle))
1709                 for (i = 0; i < vsi->nb_msix; i++) {
1710                         msix_intr = vsi->msix_intr + i;
1711                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1712                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1713                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1714                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1715                                 (interval <<
1716                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1717                 }
1718         else
1719                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1720                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1721                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1722                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1723                                (interval <<
1724                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1725
1726         I40E_WRITE_FLUSH(hw);
1727 }
1728
1729 static void
1730 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1731 {
1732         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1733         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1735         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1736         uint16_t msix_intr, i;
1737
1738         if (rte_intr_allow_others(intr_handle))
1739                 for (i = 0; i < vsi->nb_msix; i++) {
1740                         msix_intr = vsi->msix_intr + i;
1741                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1742                                        0);
1743                 }
1744         else
1745                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1746
1747         I40E_WRITE_FLUSH(hw);
1748 }
1749
1750 static inline uint8_t
1751 i40e_parse_link_speeds(uint16_t link_speeds)
1752 {
1753         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1754
1755         if (link_speeds & ETH_LINK_SPEED_40G)
1756                 link_speed |= I40E_LINK_SPEED_40GB;
1757         if (link_speeds & ETH_LINK_SPEED_25G)
1758                 link_speed |= I40E_LINK_SPEED_25GB;
1759         if (link_speeds & ETH_LINK_SPEED_20G)
1760                 link_speed |= I40E_LINK_SPEED_20GB;
1761         if (link_speeds & ETH_LINK_SPEED_10G)
1762                 link_speed |= I40E_LINK_SPEED_10GB;
1763         if (link_speeds & ETH_LINK_SPEED_1G)
1764                 link_speed |= I40E_LINK_SPEED_1GB;
1765         if (link_speeds & ETH_LINK_SPEED_100M)
1766                 link_speed |= I40E_LINK_SPEED_100MB;
1767
1768         return link_speed;
1769 }
1770
1771 static int
1772 i40e_phy_conf_link(struct i40e_hw *hw,
1773                    uint8_t abilities,
1774                    uint8_t force_speed)
1775 {
1776         enum i40e_status_code status;
1777         struct i40e_aq_get_phy_abilities_resp phy_ab;
1778         struct i40e_aq_set_phy_config phy_conf;
1779         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1780                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1781                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1782                         I40E_AQ_PHY_FLAG_LOW_POWER;
1783         const uint8_t advt = I40E_LINK_SPEED_40GB |
1784                         I40E_LINK_SPEED_25GB |
1785                         I40E_LINK_SPEED_10GB |
1786                         I40E_LINK_SPEED_1GB |
1787                         I40E_LINK_SPEED_100MB;
1788         int ret = -ENOTSUP;
1789
1790
1791         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1792                                               NULL);
1793         if (status)
1794                 return ret;
1795
1796         memset(&phy_conf, 0, sizeof(phy_conf));
1797
1798         /* bits 0-2 use the values from get_phy_abilities_resp */
1799         abilities &= ~mask;
1800         abilities |= phy_ab.abilities & mask;
1801
1802         /* update ablities and speed */
1803         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1804                 phy_conf.link_speed = advt;
1805         else
1806                 phy_conf.link_speed = force_speed;
1807
1808         phy_conf.abilities = abilities;
1809
1810         /* use get_phy_abilities_resp value for the rest */
1811         phy_conf.phy_type = phy_ab.phy_type;
1812         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1813         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1814         phy_conf.eee_capability = phy_ab.eee_capability;
1815         phy_conf.eeer = phy_ab.eeer_val;
1816         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1817
1818         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1819                     phy_ab.abilities, phy_ab.link_speed);
1820         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1821                     phy_conf.abilities, phy_conf.link_speed);
1822
1823         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1824         if (status)
1825                 return ret;
1826
1827         return I40E_SUCCESS;
1828 }
1829
1830 static int
1831 i40e_apply_link_speed(struct rte_eth_dev *dev)
1832 {
1833         uint8_t speed;
1834         uint8_t abilities = 0;
1835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         struct rte_eth_conf *conf = &dev->data->dev_conf;
1837
1838         speed = i40e_parse_link_speeds(conf->link_speeds);
1839         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1840         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1841                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1842         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1843
1844         /* Skip changing speed on 40G interfaces, FW does not support */
1845         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1846                 speed =  I40E_LINK_SPEED_UNKNOWN;
1847                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1848         }
1849
1850         return i40e_phy_conf_link(hw, abilities, speed);
1851 }
1852
1853 static int
1854 i40e_dev_start(struct rte_eth_dev *dev)
1855 {
1856         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         struct i40e_vsi *main_vsi = pf->main_vsi;
1859         int ret, i;
1860         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1861         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1862         uint32_t intr_vector = 0;
1863
1864         hw->adapter_stopped = 0;
1865
1866         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1867                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1868                              dev->data->port_id);
1869                 return -EINVAL;
1870         }
1871
1872         rte_intr_disable(intr_handle);
1873
1874         if ((rte_intr_cap_multiple(intr_handle) ||
1875              !RTE_ETH_DEV_SRIOV(dev).active) &&
1876             dev->data->dev_conf.intr_conf.rxq != 0) {
1877                 intr_vector = dev->data->nb_rx_queues;
1878                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1879                         return -1;
1880         }
1881
1882         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1883                 intr_handle->intr_vec =
1884                         rte_zmalloc("intr_vec",
1885                                     dev->data->nb_rx_queues * sizeof(int),
1886                                     0);
1887                 if (!intr_handle->intr_vec) {
1888                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1889                                      " intr_vec\n", dev->data->nb_rx_queues);
1890                         return -ENOMEM;
1891                 }
1892         }
1893
1894         /* Initialize VSI */
1895         ret = i40e_dev_rxtx_init(pf);
1896         if (ret != I40E_SUCCESS) {
1897                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1898                 goto err_up;
1899         }
1900
1901         /* Map queues with MSIX interrupt */
1902         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1903                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1904         i40e_vsi_queues_bind_intr(main_vsi);
1905         i40e_vsi_enable_queues_intr(main_vsi);
1906
1907         /* Map VMDQ VSI queues with MSIX interrupt */
1908         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1909                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1910                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1911                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1912         }
1913
1914         /* enable FDIR MSIX interrupt */
1915         if (pf->fdir.fdir_vsi) {
1916                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1917                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1918         }
1919
1920         /* Enable all queues which have been configured */
1921         ret = i40e_dev_switch_queues(pf, TRUE);
1922         if (ret != I40E_SUCCESS) {
1923                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1924                 goto err_up;
1925         }
1926
1927         /* Enable receiving broadcast packets */
1928         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1929         if (ret != I40E_SUCCESS)
1930                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1931
1932         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1933                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1934                                                 true, NULL);
1935                 if (ret != I40E_SUCCESS)
1936                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1937         }
1938
1939         /* Apply link configure */
1940         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1941                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1942                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1943                                 ETH_LINK_SPEED_40G)) {
1944                 PMD_DRV_LOG(ERR, "Invalid link setting");
1945                 goto err_up;
1946         }
1947         ret = i40e_apply_link_speed(dev);
1948         if (I40E_SUCCESS != ret) {
1949                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1950                 goto err_up;
1951         }
1952
1953         if (!rte_intr_allow_others(intr_handle)) {
1954                 rte_intr_callback_unregister(intr_handle,
1955                                              i40e_dev_interrupt_handler,
1956                                              (void *)dev);
1957                 /* configure and enable device interrupt */
1958                 i40e_pf_config_irq0(hw, FALSE);
1959                 i40e_pf_enable_irq0(hw);
1960
1961                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1962                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1963                                      " no intr multiplex\n");
1964         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1965                 ret = i40e_aq_set_phy_int_mask(hw,
1966                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1967                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1968                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1969                 if (ret != I40E_SUCCESS)
1970                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1971
1972                 /* Call get_link_info aq commond to enable LSE */
1973                 i40e_dev_link_update(dev, 0);
1974         }
1975
1976         /* enable uio intr after callback register */
1977         rte_intr_enable(intr_handle);
1978
1979         i40e_filter_restore(pf);
1980
1981         return I40E_SUCCESS;
1982
1983 err_up:
1984         i40e_dev_switch_queues(pf, FALSE);
1985         i40e_dev_clear_queues(dev);
1986
1987         return ret;
1988 }
1989
1990 static void
1991 i40e_dev_stop(struct rte_eth_dev *dev)
1992 {
1993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1994         struct i40e_vsi *main_vsi = pf->main_vsi;
1995         struct i40e_mirror_rule *p_mirror;
1996         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1997         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1998         int i;
1999
2000         /* Disable all queues */
2001         i40e_dev_switch_queues(pf, FALSE);
2002
2003         /* un-map queues with interrupt registers */
2004         i40e_vsi_disable_queues_intr(main_vsi);
2005         i40e_vsi_queues_unbind_intr(main_vsi);
2006
2007         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2008                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2009                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2010         }
2011
2012         if (pf->fdir.fdir_vsi) {
2013                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2014                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2015         }
2016         /* Clear all queues and release memory */
2017         i40e_dev_clear_queues(dev);
2018
2019         /* Set link down */
2020         i40e_dev_set_link_down(dev);
2021
2022         /* Remove all mirror rules */
2023         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2024                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2025                 rte_free(p_mirror);
2026         }
2027         pf->nb_mirror_rule = 0;
2028
2029         if (!rte_intr_allow_others(intr_handle))
2030                 /* resume to the default handler */
2031                 rte_intr_callback_register(intr_handle,
2032                                            i40e_dev_interrupt_handler,
2033                                            (void *)dev);
2034
2035         /* Clean datapath event and queue/vec mapping */
2036         rte_intr_efd_disable(intr_handle);
2037         if (intr_handle->intr_vec) {
2038                 rte_free(intr_handle->intr_vec);
2039                 intr_handle->intr_vec = NULL;
2040         }
2041 }
2042
2043 static void
2044 i40e_dev_close(struct rte_eth_dev *dev)
2045 {
2046         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2047         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2048         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2049         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2050         uint32_t reg;
2051         int i;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         i40e_dev_stop(dev);
2056         hw->adapter_stopped = 1;
2057         i40e_dev_free_queues(dev);
2058
2059         /* Disable interrupt */
2060         i40e_pf_disable_irq0(hw);
2061         rte_intr_disable(intr_handle);
2062
2063         /* shutdown and destroy the HMC */
2064         i40e_shutdown_lan_hmc(hw);
2065
2066         /* release all the existing VSIs and VEBs */
2067         i40e_fdir_teardown(pf);
2068         i40e_vsi_release(pf->main_vsi);
2069
2070         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2071                 i40e_vsi_release(pf->vmdq[i].vsi);
2072                 pf->vmdq[i].vsi = NULL;
2073         }
2074
2075         rte_free(pf->vmdq);
2076         pf->vmdq = NULL;
2077
2078         /* shutdown the adminq */
2079         i40e_aq_queue_shutdown(hw, true);
2080         i40e_shutdown_adminq(hw);
2081
2082         i40e_res_pool_destroy(&pf->qp_pool);
2083         i40e_res_pool_destroy(&pf->msix_pool);
2084
2085         /* force a PF reset to clean anything leftover */
2086         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2087         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2088                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2089         I40E_WRITE_FLUSH(hw);
2090 }
2091
2092 static void
2093 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2094 {
2095         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         struct i40e_vsi *vsi = pf->main_vsi;
2098         int status;
2099
2100         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2101                                                      true, NULL, true);
2102         if (status != I40E_SUCCESS)
2103                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2104
2105         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2106                                                         TRUE, NULL);
2107         if (status != I40E_SUCCESS)
2108                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2109
2110 }
2111
2112 static void
2113 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2114 {
2115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2116         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117         struct i40e_vsi *vsi = pf->main_vsi;
2118         int status;
2119
2120         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2121                                                      false, NULL, true);
2122         if (status != I40E_SUCCESS)
2123                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2124
2125         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2126                                                         false, NULL);
2127         if (status != I40E_SUCCESS)
2128                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2129 }
2130
2131 static void
2132 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2133 {
2134         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2135         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136         struct i40e_vsi *vsi = pf->main_vsi;
2137         int ret;
2138
2139         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2140         if (ret != I40E_SUCCESS)
2141                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2142 }
2143
2144 static void
2145 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2146 {
2147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149         struct i40e_vsi *vsi = pf->main_vsi;
2150         int ret;
2151
2152         if (dev->data->promiscuous == 1)
2153                 return; /* must remain in all_multicast mode */
2154
2155         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2156                                 vsi->seid, FALSE, NULL);
2157         if (ret != I40E_SUCCESS)
2158                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2159 }
2160
2161 /*
2162  * Set device link up.
2163  */
2164 static int
2165 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2166 {
2167         /* re-apply link speed setting */
2168         return i40e_apply_link_speed(dev);
2169 }
2170
2171 /*
2172  * Set device link down.
2173  */
2174 static int
2175 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2176 {
2177         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2178         uint8_t abilities = 0;
2179         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2180
2181         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2182         return i40e_phy_conf_link(hw, abilities, speed);
2183 }
2184
2185 int
2186 i40e_dev_link_update(struct rte_eth_dev *dev,
2187                      int wait_to_complete)
2188 {
2189 #define CHECK_INTERVAL 100  /* 100ms */
2190 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2191         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192         struct i40e_link_status link_status;
2193         struct rte_eth_link link, old;
2194         int status;
2195         unsigned rep_cnt = MAX_REPEAT_TIME;
2196         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2197
2198         memset(&link, 0, sizeof(link));
2199         memset(&old, 0, sizeof(old));
2200         memset(&link_status, 0, sizeof(link_status));
2201         rte_i40e_dev_atomic_read_link_status(dev, &old);
2202
2203         do {
2204                 /* Get link status information from hardware */
2205                 status = i40e_aq_get_link_info(hw, enable_lse,
2206                                                 &link_status, NULL);
2207                 if (status != I40E_SUCCESS) {
2208                         link.link_speed = ETH_SPEED_NUM_100M;
2209                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2210                         PMD_DRV_LOG(ERR, "Failed to get link info");
2211                         goto out;
2212                 }
2213
2214                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2215                 if (!wait_to_complete)
2216                         break;
2217
2218                 rte_delay_ms(CHECK_INTERVAL);
2219         } while (!link.link_status && rep_cnt--);
2220
2221         if (!link.link_status)
2222                 goto out;
2223
2224         /* i40e uses full duplex only */
2225         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2226
2227         /* Parse the link status */
2228         switch (link_status.link_speed) {
2229         case I40E_LINK_SPEED_100MB:
2230                 link.link_speed = ETH_SPEED_NUM_100M;
2231                 break;
2232         case I40E_LINK_SPEED_1GB:
2233                 link.link_speed = ETH_SPEED_NUM_1G;
2234                 break;
2235         case I40E_LINK_SPEED_10GB:
2236                 link.link_speed = ETH_SPEED_NUM_10G;
2237                 break;
2238         case I40E_LINK_SPEED_20GB:
2239                 link.link_speed = ETH_SPEED_NUM_20G;
2240                 break;
2241         case I40E_LINK_SPEED_25GB:
2242                 link.link_speed = ETH_SPEED_NUM_25G;
2243                 break;
2244         case I40E_LINK_SPEED_40GB:
2245                 link.link_speed = ETH_SPEED_NUM_40G;
2246                 break;
2247         default:
2248                 link.link_speed = ETH_SPEED_NUM_100M;
2249                 break;
2250         }
2251
2252         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2253                         ETH_LINK_SPEED_FIXED);
2254
2255 out:
2256         rte_i40e_dev_atomic_write_link_status(dev, &link);
2257         if (link.link_status == old.link_status)
2258                 return -1;
2259
2260         return 0;
2261 }
2262
2263 /* Get all the statistics of a VSI */
2264 void
2265 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2266 {
2267         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2268         struct i40e_eth_stats *nes = &vsi->eth_stats;
2269         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2270         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2271
2272         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2273                             vsi->offset_loaded, &oes->rx_bytes,
2274                             &nes->rx_bytes);
2275         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2276                             vsi->offset_loaded, &oes->rx_unicast,
2277                             &nes->rx_unicast);
2278         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2279                             vsi->offset_loaded, &oes->rx_multicast,
2280                             &nes->rx_multicast);
2281         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2282                             vsi->offset_loaded, &oes->rx_broadcast,
2283                             &nes->rx_broadcast);
2284         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2285                             &oes->rx_discards, &nes->rx_discards);
2286         /* GLV_REPC not supported */
2287         /* GLV_RMPC not supported */
2288         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2289                             &oes->rx_unknown_protocol,
2290                             &nes->rx_unknown_protocol);
2291         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2292                             vsi->offset_loaded, &oes->tx_bytes,
2293                             &nes->tx_bytes);
2294         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2295                             vsi->offset_loaded, &oes->tx_unicast,
2296                             &nes->tx_unicast);
2297         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2298                             vsi->offset_loaded, &oes->tx_multicast,
2299                             &nes->tx_multicast);
2300         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2301                             vsi->offset_loaded,  &oes->tx_broadcast,
2302                             &nes->tx_broadcast);
2303         /* GLV_TDPC not supported */
2304         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2305                             &oes->tx_errors, &nes->tx_errors);
2306         vsi->offset_loaded = true;
2307
2308         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2309                     vsi->vsi_id);
2310         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2311         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2312         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2313         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2314         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2315         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2316                     nes->rx_unknown_protocol);
2317         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2318         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2319         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2320         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2321         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2322         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2323         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2324                     vsi->vsi_id);
2325 }
2326
2327 static void
2328 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2329 {
2330         unsigned int i;
2331         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2332         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2333
2334         /* Get statistics of struct i40e_eth_stats */
2335         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2336                             I40E_GLPRT_GORCL(hw->port),
2337                             pf->offset_loaded, &os->eth.rx_bytes,
2338                             &ns->eth.rx_bytes);
2339         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2340                             I40E_GLPRT_UPRCL(hw->port),
2341                             pf->offset_loaded, &os->eth.rx_unicast,
2342                             &ns->eth.rx_unicast);
2343         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2344                             I40E_GLPRT_MPRCL(hw->port),
2345                             pf->offset_loaded, &os->eth.rx_multicast,
2346                             &ns->eth.rx_multicast);
2347         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2348                             I40E_GLPRT_BPRCL(hw->port),
2349                             pf->offset_loaded, &os->eth.rx_broadcast,
2350                             &ns->eth.rx_broadcast);
2351         /* Workaround: CRC size should not be included in byte statistics,
2352          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2353          */
2354         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2355                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2356
2357         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2358                             pf->offset_loaded, &os->eth.rx_discards,
2359                             &ns->eth.rx_discards);
2360         /* GLPRT_REPC not supported */
2361         /* GLPRT_RMPC not supported */
2362         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2363                             pf->offset_loaded,
2364                             &os->eth.rx_unknown_protocol,
2365                             &ns->eth.rx_unknown_protocol);
2366         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2367                             I40E_GLPRT_GOTCL(hw->port),
2368                             pf->offset_loaded, &os->eth.tx_bytes,
2369                             &ns->eth.tx_bytes);
2370         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2371                             I40E_GLPRT_UPTCL(hw->port),
2372                             pf->offset_loaded, &os->eth.tx_unicast,
2373                             &ns->eth.tx_unicast);
2374         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2375                             I40E_GLPRT_MPTCL(hw->port),
2376                             pf->offset_loaded, &os->eth.tx_multicast,
2377                             &ns->eth.tx_multicast);
2378         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2379                             I40E_GLPRT_BPTCL(hw->port),
2380                             pf->offset_loaded, &os->eth.tx_broadcast,
2381                             &ns->eth.tx_broadcast);
2382         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2383                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2384         /* GLPRT_TEPC not supported */
2385
2386         /* additional port specific stats */
2387         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2388                             pf->offset_loaded, &os->tx_dropped_link_down,
2389                             &ns->tx_dropped_link_down);
2390         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2391                             pf->offset_loaded, &os->crc_errors,
2392                             &ns->crc_errors);
2393         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2394                             pf->offset_loaded, &os->illegal_bytes,
2395                             &ns->illegal_bytes);
2396         /* GLPRT_ERRBC not supported */
2397         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2398                             pf->offset_loaded, &os->mac_local_faults,
2399                             &ns->mac_local_faults);
2400         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2401                             pf->offset_loaded, &os->mac_remote_faults,
2402                             &ns->mac_remote_faults);
2403         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2404                             pf->offset_loaded, &os->rx_length_errors,
2405                             &ns->rx_length_errors);
2406         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2407                             pf->offset_loaded, &os->link_xon_rx,
2408                             &ns->link_xon_rx);
2409         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2410                             pf->offset_loaded, &os->link_xoff_rx,
2411                             &ns->link_xoff_rx);
2412         for (i = 0; i < 8; i++) {
2413                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2414                                     pf->offset_loaded,
2415                                     &os->priority_xon_rx[i],
2416                                     &ns->priority_xon_rx[i]);
2417                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2418                                     pf->offset_loaded,
2419                                     &os->priority_xoff_rx[i],
2420                                     &ns->priority_xoff_rx[i]);
2421         }
2422         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2423                             pf->offset_loaded, &os->link_xon_tx,
2424                             &ns->link_xon_tx);
2425         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2426                             pf->offset_loaded, &os->link_xoff_tx,
2427                             &ns->link_xoff_tx);
2428         for (i = 0; i < 8; i++) {
2429                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2430                                     pf->offset_loaded,
2431                                     &os->priority_xon_tx[i],
2432                                     &ns->priority_xon_tx[i]);
2433                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2434                                     pf->offset_loaded,
2435                                     &os->priority_xoff_tx[i],
2436                                     &ns->priority_xoff_tx[i]);
2437                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2438                                     pf->offset_loaded,
2439                                     &os->priority_xon_2_xoff[i],
2440                                     &ns->priority_xon_2_xoff[i]);
2441         }
2442         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2443                             I40E_GLPRT_PRC64L(hw->port),
2444                             pf->offset_loaded, &os->rx_size_64,
2445                             &ns->rx_size_64);
2446         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2447                             I40E_GLPRT_PRC127L(hw->port),
2448                             pf->offset_loaded, &os->rx_size_127,
2449                             &ns->rx_size_127);
2450         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2451                             I40E_GLPRT_PRC255L(hw->port),
2452                             pf->offset_loaded, &os->rx_size_255,
2453                             &ns->rx_size_255);
2454         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2455                             I40E_GLPRT_PRC511L(hw->port),
2456                             pf->offset_loaded, &os->rx_size_511,
2457                             &ns->rx_size_511);
2458         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2459                             I40E_GLPRT_PRC1023L(hw->port),
2460                             pf->offset_loaded, &os->rx_size_1023,
2461                             &ns->rx_size_1023);
2462         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2463                             I40E_GLPRT_PRC1522L(hw->port),
2464                             pf->offset_loaded, &os->rx_size_1522,
2465                             &ns->rx_size_1522);
2466         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2467                             I40E_GLPRT_PRC9522L(hw->port),
2468                             pf->offset_loaded, &os->rx_size_big,
2469                             &ns->rx_size_big);
2470         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2471                             pf->offset_loaded, &os->rx_undersize,
2472                             &ns->rx_undersize);
2473         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2474                             pf->offset_loaded, &os->rx_fragments,
2475                             &ns->rx_fragments);
2476         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2477                             pf->offset_loaded, &os->rx_oversize,
2478                             &ns->rx_oversize);
2479         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2480                             pf->offset_loaded, &os->rx_jabber,
2481                             &ns->rx_jabber);
2482         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2483                             I40E_GLPRT_PTC64L(hw->port),
2484                             pf->offset_loaded, &os->tx_size_64,
2485                             &ns->tx_size_64);
2486         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2487                             I40E_GLPRT_PTC127L(hw->port),
2488                             pf->offset_loaded, &os->tx_size_127,
2489                             &ns->tx_size_127);
2490         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2491                             I40E_GLPRT_PTC255L(hw->port),
2492                             pf->offset_loaded, &os->tx_size_255,
2493                             &ns->tx_size_255);
2494         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2495                             I40E_GLPRT_PTC511L(hw->port),
2496                             pf->offset_loaded, &os->tx_size_511,
2497                             &ns->tx_size_511);
2498         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2499                             I40E_GLPRT_PTC1023L(hw->port),
2500                             pf->offset_loaded, &os->tx_size_1023,
2501                             &ns->tx_size_1023);
2502         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2503                             I40E_GLPRT_PTC1522L(hw->port),
2504                             pf->offset_loaded, &os->tx_size_1522,
2505                             &ns->tx_size_1522);
2506         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2507                             I40E_GLPRT_PTC9522L(hw->port),
2508                             pf->offset_loaded, &os->tx_size_big,
2509                             &ns->tx_size_big);
2510         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2511                            pf->offset_loaded,
2512                            &os->fd_sb_match, &ns->fd_sb_match);
2513         /* GLPRT_MSPDC not supported */
2514         /* GLPRT_XEC not supported */
2515
2516         pf->offset_loaded = true;
2517
2518         if (pf->main_vsi)
2519                 i40e_update_vsi_stats(pf->main_vsi);
2520 }
2521
2522 /* Get all statistics of a port */
2523 static void
2524 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2525 {
2526         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2527         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2529         unsigned i;
2530
2531         /* call read registers - updates values, now write them to struct */
2532         i40e_read_stats_registers(pf, hw);
2533
2534         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2535                         pf->main_vsi->eth_stats.rx_multicast +
2536                         pf->main_vsi->eth_stats.rx_broadcast -
2537                         pf->main_vsi->eth_stats.rx_discards;
2538         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2539                         pf->main_vsi->eth_stats.tx_multicast +
2540                         pf->main_vsi->eth_stats.tx_broadcast;
2541         stats->ibytes   = ns->eth.rx_bytes;
2542         stats->obytes   = ns->eth.tx_bytes;
2543         stats->oerrors  = ns->eth.tx_errors +
2544                         pf->main_vsi->eth_stats.tx_errors;
2545
2546         /* Rx Errors */
2547         stats->imissed  = ns->eth.rx_discards +
2548                         pf->main_vsi->eth_stats.rx_discards;
2549         stats->ierrors  = ns->crc_errors +
2550                         ns->rx_length_errors + ns->rx_undersize +
2551                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2552
2553         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2554         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2555         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2556         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2557         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2558         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2559         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2560                     ns->eth.rx_unknown_protocol);
2561         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2562         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2563         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2564         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2565         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2566         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2567
2568         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2569                     ns->tx_dropped_link_down);
2570         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2571         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2572                     ns->illegal_bytes);
2573         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2574         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2575                     ns->mac_local_faults);
2576         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2577                     ns->mac_remote_faults);
2578         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2579                     ns->rx_length_errors);
2580         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2581         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2582         for (i = 0; i < 8; i++) {
2583                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2584                                 i, ns->priority_xon_rx[i]);
2585                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2586                                 i, ns->priority_xoff_rx[i]);
2587         }
2588         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2589         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2590         for (i = 0; i < 8; i++) {
2591                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2592                                 i, ns->priority_xon_tx[i]);
2593                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2594                                 i, ns->priority_xoff_tx[i]);
2595                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2596                                 i, ns->priority_xon_2_xoff[i]);
2597         }
2598         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2599         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2600         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2601         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2602         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2603         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2604         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2605         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2606         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2607         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2608         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2609         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2610         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2611         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2612         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2613         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2614         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2615         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2616         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2617                         ns->mac_short_packet_dropped);
2618         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2619                     ns->checksum_error);
2620         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2621         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2622 }
2623
2624 /* Reset the statistics */
2625 static void
2626 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2627 {
2628         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630
2631         /* Mark PF and VSI stats to update the offset, aka "reset" */
2632         pf->offset_loaded = false;
2633         if (pf->main_vsi)
2634                 pf->main_vsi->offset_loaded = false;
2635
2636         /* read the stats, reading current register values into offset */
2637         i40e_read_stats_registers(pf, hw);
2638 }
2639
2640 static uint32_t
2641 i40e_xstats_calc_num(void)
2642 {
2643         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2644                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2645                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2646 }
2647
2648 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2649                                      struct rte_eth_xstat_name *xstats_names,
2650                                      __rte_unused unsigned limit)
2651 {
2652         unsigned count = 0;
2653         unsigned i, prio;
2654
2655         if (xstats_names == NULL)
2656                 return i40e_xstats_calc_num();
2657
2658         /* Note: limit checked in rte_eth_xstats_names() */
2659
2660         /* Get stats from i40e_eth_stats struct */
2661         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2662                 snprintf(xstats_names[count].name,
2663                          sizeof(xstats_names[count].name),
2664                          "%s", rte_i40e_stats_strings[i].name);
2665                 count++;
2666         }
2667
2668         /* Get individiual stats from i40e_hw_port struct */
2669         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2670                 snprintf(xstats_names[count].name,
2671                         sizeof(xstats_names[count].name),
2672                          "%s", rte_i40e_hw_port_strings[i].name);
2673                 count++;
2674         }
2675
2676         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2677                 for (prio = 0; prio < 8; prio++) {
2678                         snprintf(xstats_names[count].name,
2679                                  sizeof(xstats_names[count].name),
2680                                  "rx_priority%u_%s", prio,
2681                                  rte_i40e_rxq_prio_strings[i].name);
2682                         count++;
2683                 }
2684         }
2685
2686         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2687                 for (prio = 0; prio < 8; prio++) {
2688                         snprintf(xstats_names[count].name,
2689                                  sizeof(xstats_names[count].name),
2690                                  "tx_priority%u_%s", prio,
2691                                  rte_i40e_txq_prio_strings[i].name);
2692                         count++;
2693                 }
2694         }
2695         return count;
2696 }
2697
2698 static int
2699 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2700                     unsigned n)
2701 {
2702         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2703         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         unsigned i, count, prio;
2705         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2706
2707         count = i40e_xstats_calc_num();
2708         if (n < count)
2709                 return count;
2710
2711         i40e_read_stats_registers(pf, hw);
2712
2713         if (xstats == NULL)
2714                 return 0;
2715
2716         count = 0;
2717
2718         /* Get stats from i40e_eth_stats struct */
2719         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2720                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2721                         rte_i40e_stats_strings[i].offset);
2722                 xstats[count].id = count;
2723                 count++;
2724         }
2725
2726         /* Get individiual stats from i40e_hw_port struct */
2727         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2728                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2729                         rte_i40e_hw_port_strings[i].offset);
2730                 xstats[count].id = count;
2731                 count++;
2732         }
2733
2734         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2735                 for (prio = 0; prio < 8; prio++) {
2736                         xstats[count].value =
2737                                 *(uint64_t *)(((char *)hw_stats) +
2738                                 rte_i40e_rxq_prio_strings[i].offset +
2739                                 (sizeof(uint64_t) * prio));
2740                         xstats[count].id = count;
2741                         count++;
2742                 }
2743         }
2744
2745         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2746                 for (prio = 0; prio < 8; prio++) {
2747                         xstats[count].value =
2748                                 *(uint64_t *)(((char *)hw_stats) +
2749                                 rte_i40e_txq_prio_strings[i].offset +
2750                                 (sizeof(uint64_t) * prio));
2751                         xstats[count].id = count;
2752                         count++;
2753                 }
2754         }
2755
2756         return count;
2757 }
2758
2759 static int
2760 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2761                                  __rte_unused uint16_t queue_id,
2762                                  __rte_unused uint8_t stat_idx,
2763                                  __rte_unused uint8_t is_rx)
2764 {
2765         PMD_INIT_FUNC_TRACE();
2766
2767         return -ENOSYS;
2768 }
2769
2770 static int
2771 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2772 {
2773         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774         u32 full_ver;
2775         u8 ver, patch;
2776         u16 build;
2777         int ret;
2778
2779         full_ver = hw->nvm.oem_ver;
2780         ver = (u8)(full_ver >> 24);
2781         build = (u16)((full_ver >> 8) & 0xffff);
2782         patch = (u8)(full_ver & 0xff);
2783
2784         ret = snprintf(fw_version, fw_size,
2785                  "%d.%d%d 0x%08x %d.%d.%d",
2786                  ((hw->nvm.version >> 12) & 0xf),
2787                  ((hw->nvm.version >> 4) & 0xff),
2788                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2789                  ver, build, patch);
2790
2791         ret += 1; /* add the size of '\0' */
2792         if (fw_size < (u32)ret)
2793                 return ret;
2794         else
2795                 return 0;
2796 }
2797
2798 static void
2799 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2800 {
2801         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2802         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2803         struct i40e_vsi *vsi = pf->main_vsi;
2804         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2805
2806         dev_info->pci_dev = pci_dev;
2807         dev_info->max_rx_queues = vsi->nb_qps;
2808         dev_info->max_tx_queues = vsi->nb_qps;
2809         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2810         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2811         dev_info->max_mac_addrs = vsi->max_macaddrs;
2812         dev_info->max_vfs = pci_dev->max_vfs;
2813         dev_info->rx_offload_capa =
2814                 DEV_RX_OFFLOAD_VLAN_STRIP |
2815                 DEV_RX_OFFLOAD_QINQ_STRIP |
2816                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2817                 DEV_RX_OFFLOAD_UDP_CKSUM |
2818                 DEV_RX_OFFLOAD_TCP_CKSUM;
2819         dev_info->tx_offload_capa =
2820                 DEV_TX_OFFLOAD_VLAN_INSERT |
2821                 DEV_TX_OFFLOAD_QINQ_INSERT |
2822                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2823                 DEV_TX_OFFLOAD_UDP_CKSUM |
2824                 DEV_TX_OFFLOAD_TCP_CKSUM |
2825                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2826                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2827                 DEV_TX_OFFLOAD_TCP_TSO |
2828                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2829                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2830                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2831                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2832         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2833                                                 sizeof(uint32_t);
2834         dev_info->reta_size = pf->hash_lut_size;
2835         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2836
2837         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2838                 .rx_thresh = {
2839                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2840                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2841                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2842                 },
2843                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2844                 .rx_drop_en = 0,
2845         };
2846
2847         dev_info->default_txconf = (struct rte_eth_txconf) {
2848                 .tx_thresh = {
2849                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2850                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2851                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2852                 },
2853                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2854                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2855                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2856                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2857         };
2858
2859         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2860                 .nb_max = I40E_MAX_RING_DESC,
2861                 .nb_min = I40E_MIN_RING_DESC,
2862                 .nb_align = I40E_ALIGN_RING_DESC,
2863         };
2864
2865         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2866                 .nb_max = I40E_MAX_RING_DESC,
2867                 .nb_min = I40E_MIN_RING_DESC,
2868                 .nb_align = I40E_ALIGN_RING_DESC,
2869                 .nb_seg_max = I40E_TX_MAX_SEG,
2870                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2871         };
2872
2873         if (pf->flags & I40E_FLAG_VMDQ) {
2874                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2875                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2876                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2877                                                 pf->max_nb_vmdq_vsi;
2878                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2879                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2880                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2881         }
2882
2883         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2884                 /* For XL710 */
2885                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2886         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2887                 /* For XXV710 */
2888                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2889         else
2890                 /* For X710 */
2891                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2892 }
2893
2894 static int
2895 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2896 {
2897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2898         struct i40e_vsi *vsi = pf->main_vsi;
2899         PMD_INIT_FUNC_TRACE();
2900
2901         if (on)
2902                 return i40e_vsi_add_vlan(vsi, vlan_id);
2903         else
2904                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2905 }
2906
2907 static int
2908 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2909                    enum rte_vlan_type vlan_type,
2910                    uint16_t tpid)
2911 {
2912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913         uint64_t reg_r = 0, reg_w = 0;
2914         uint16_t reg_id = 0;
2915         int ret = 0;
2916         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2917
2918         switch (vlan_type) {
2919         case ETH_VLAN_TYPE_OUTER:
2920                 if (qinq)
2921                         reg_id = 2;
2922                 else
2923                         reg_id = 3;
2924                 break;
2925         case ETH_VLAN_TYPE_INNER:
2926                 if (qinq)
2927                         reg_id = 3;
2928                 else {
2929                         ret = -EINVAL;
2930                         PMD_DRV_LOG(ERR,
2931                                 "Unsupported vlan type in single vlan.\n");
2932                         return ret;
2933                 }
2934                 break;
2935         default:
2936                 ret = -EINVAL;
2937                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2938                 return ret;
2939         }
2940         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2941                                           &reg_r, NULL);
2942         if (ret != I40E_SUCCESS) {
2943                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2944                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2945                 ret = -EIO;
2946                 return ret;
2947         }
2948         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2949                     "0x%08"PRIx64"", reg_id, reg_r);
2950
2951         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2952         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2953         if (reg_r == reg_w) {
2954                 ret = 0;
2955                 PMD_DRV_LOG(DEBUG, "No need to write");
2956                 return ret;
2957         }
2958
2959         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2960                                            reg_w, NULL);
2961         if (ret != I40E_SUCCESS) {
2962                 ret = -EIO;
2963                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2964                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2965                 return ret;
2966         }
2967         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2968                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2969
2970         return ret;
2971 }
2972
2973 static void
2974 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2975 {
2976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2977         struct i40e_vsi *vsi = pf->main_vsi;
2978
2979         if (mask & ETH_VLAN_FILTER_MASK) {
2980                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2981                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2982                 else
2983                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2984         }
2985
2986         if (mask & ETH_VLAN_STRIP_MASK) {
2987                 /* Enable or disable VLAN stripping */
2988                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2989                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2990                 else
2991                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2992         }
2993
2994         if (mask & ETH_VLAN_EXTEND_MASK) {
2995                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2996                         i40e_vsi_config_double_vlan(vsi, TRUE);
2997                         /* Set global registers with default ether type value */
2998                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2999                                            ETHER_TYPE_VLAN);
3000                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3001                                            ETHER_TYPE_VLAN);
3002                 }
3003                 else
3004                         i40e_vsi_config_double_vlan(vsi, FALSE);
3005         }
3006 }
3007
3008 static void
3009 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3010                           __rte_unused uint16_t queue,
3011                           __rte_unused int on)
3012 {
3013         PMD_INIT_FUNC_TRACE();
3014 }
3015
3016 static int
3017 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3018 {
3019         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3020         struct i40e_vsi *vsi = pf->main_vsi;
3021         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3022         struct i40e_vsi_vlan_pvid_info info;
3023
3024         memset(&info, 0, sizeof(info));
3025         info.on = on;
3026         if (info.on)
3027                 info.config.pvid = pvid;
3028         else {
3029                 info.config.reject.tagged =
3030                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3031                 info.config.reject.untagged =
3032                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3033         }
3034
3035         return i40e_vsi_vlan_pvid_set(vsi, &info);
3036 }
3037
3038 static int
3039 i40e_dev_led_on(struct rte_eth_dev *dev)
3040 {
3041         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042         uint32_t mode = i40e_led_get(hw);
3043
3044         if (mode == 0)
3045                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3046
3047         return 0;
3048 }
3049
3050 static int
3051 i40e_dev_led_off(struct rte_eth_dev *dev)
3052 {
3053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3054         uint32_t mode = i40e_led_get(hw);
3055
3056         if (mode != 0)
3057                 i40e_led_set(hw, 0, false);
3058
3059         return 0;
3060 }
3061
3062 static int
3063 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3064 {
3065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3067
3068         fc_conf->pause_time = pf->fc_conf.pause_time;
3069         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3070         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3071
3072          /* Return current mode according to actual setting*/
3073         switch (hw->fc.current_mode) {
3074         case I40E_FC_FULL:
3075                 fc_conf->mode = RTE_FC_FULL;
3076                 break;
3077         case I40E_FC_TX_PAUSE:
3078                 fc_conf->mode = RTE_FC_TX_PAUSE;
3079                 break;
3080         case I40E_FC_RX_PAUSE:
3081                 fc_conf->mode = RTE_FC_RX_PAUSE;
3082                 break;
3083         case I40E_FC_NONE:
3084         default:
3085                 fc_conf->mode = RTE_FC_NONE;
3086         };
3087
3088         return 0;
3089 }
3090
3091 static int
3092 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3093 {
3094         uint32_t mflcn_reg, fctrl_reg, reg;
3095         uint32_t max_high_water;
3096         uint8_t i, aq_failure;
3097         int err;
3098         struct i40e_hw *hw;
3099         struct i40e_pf *pf;
3100         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3101                 [RTE_FC_NONE] = I40E_FC_NONE,
3102                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3103                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3104                 [RTE_FC_FULL] = I40E_FC_FULL
3105         };
3106
3107         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3108
3109         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3110         if ((fc_conf->high_water > max_high_water) ||
3111                         (fc_conf->high_water < fc_conf->low_water)) {
3112                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3113                         "High_water must <= %d.", max_high_water);
3114                 return -EINVAL;
3115         }
3116
3117         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3118         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3119         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3120
3121         pf->fc_conf.pause_time = fc_conf->pause_time;
3122         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3123         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3124
3125         PMD_INIT_FUNC_TRACE();
3126
3127         /* All the link flow control related enable/disable register
3128          * configuration is handle by the F/W
3129          */
3130         err = i40e_set_fc(hw, &aq_failure, true);
3131         if (err < 0)
3132                 return -ENOSYS;
3133
3134         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3135                 /* Configure flow control refresh threshold,
3136                  * the value for stat_tx_pause_refresh_timer[8]
3137                  * is used for global pause operation.
3138                  */
3139
3140                 I40E_WRITE_REG(hw,
3141                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3142                                pf->fc_conf.pause_time);
3143
3144                 /* configure the timer value included in transmitted pause
3145                  * frame,
3146                  * the value for stat_tx_pause_quanta[8] is used for global
3147                  * pause operation
3148                  */
3149                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3150                                pf->fc_conf.pause_time);
3151
3152                 fctrl_reg = I40E_READ_REG(hw,
3153                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3154
3155                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3156                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3157                 else
3158                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3159
3160                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3161                                fctrl_reg);
3162         } else {
3163                 /* Configure pause time (2 TCs per register) */
3164                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3165                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3166                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3167
3168                 /* Configure flow control refresh threshold value */
3169                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3170                                pf->fc_conf.pause_time / 2);
3171
3172                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3173
3174                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3175                  *depending on configuration
3176                  */
3177                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3178                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3179                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3180                 } else {
3181                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3182                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3183                 }
3184
3185                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3186         }
3187
3188         /* config the water marker both based on the packets and bytes */
3189         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3190                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3191                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3192         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3193                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3194                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3195         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3196                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3197                        << I40E_KILOSHIFT);
3198         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3199                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3200                        << I40E_KILOSHIFT);
3201
3202         I40E_WRITE_FLUSH(hw);
3203
3204         return 0;
3205 }
3206
3207 static int
3208 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3209                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3210 {
3211         PMD_INIT_FUNC_TRACE();
3212
3213         return -ENOSYS;
3214 }
3215
3216 /* Add a MAC address, and update filters */
3217 static void
3218 i40e_macaddr_add(struct rte_eth_dev *dev,
3219                  struct ether_addr *mac_addr,
3220                  __rte_unused uint32_t index,
3221                  uint32_t pool)
3222 {
3223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3224         struct i40e_mac_filter_info mac_filter;
3225         struct i40e_vsi *vsi;
3226         int ret;
3227
3228         /* If VMDQ not enabled or configured, return */
3229         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3230                           !pf->nb_cfg_vmdq_vsi)) {
3231                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3232                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3233                         pool);
3234                 return;
3235         }
3236
3237         if (pool > pf->nb_cfg_vmdq_vsi) {
3238                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3239                                 pool, pf->nb_cfg_vmdq_vsi);
3240                 return;
3241         }
3242
3243         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3244         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3245                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3246         else
3247                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3248
3249         if (pool == 0)
3250                 vsi = pf->main_vsi;
3251         else
3252                 vsi = pf->vmdq[pool - 1].vsi;
3253
3254         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3255         if (ret != I40E_SUCCESS) {
3256                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3257                 return;
3258         }
3259 }
3260
3261 /* Remove a MAC address, and update filters */
3262 static void
3263 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3264 {
3265         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3266         struct i40e_vsi *vsi;
3267         struct rte_eth_dev_data *data = dev->data;
3268         struct ether_addr *macaddr;
3269         int ret;
3270         uint32_t i;
3271         uint64_t pool_sel;
3272
3273         macaddr = &(data->mac_addrs[index]);
3274
3275         pool_sel = dev->data->mac_pool_sel[index];
3276
3277         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3278                 if (pool_sel & (1ULL << i)) {
3279                         if (i == 0)
3280                                 vsi = pf->main_vsi;
3281                         else {
3282                                 /* No VMDQ pool enabled or configured */
3283                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3284                                         (i > pf->nb_cfg_vmdq_vsi)) {
3285                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3286                                                         "/configured");
3287                                         return;
3288                                 }
3289                                 vsi = pf->vmdq[i - 1].vsi;
3290                         }
3291                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3292
3293                         if (ret) {
3294                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3295                                 return;
3296                         }
3297                 }
3298         }
3299 }
3300
3301 /* Set perfect match or hash match of MAC and VLAN for a VF */
3302 static int
3303 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3304                  struct rte_eth_mac_filter *filter,
3305                  bool add)
3306 {
3307         struct i40e_hw *hw;
3308         struct i40e_mac_filter_info mac_filter;
3309         struct ether_addr old_mac;
3310         struct ether_addr *new_mac;
3311         struct i40e_pf_vf *vf = NULL;
3312         uint16_t vf_id;
3313         int ret;
3314
3315         if (pf == NULL) {
3316                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3317                 return -EINVAL;
3318         }
3319         hw = I40E_PF_TO_HW(pf);
3320
3321         if (filter == NULL) {
3322                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3323                 return -EINVAL;
3324         }
3325
3326         new_mac = &filter->mac_addr;
3327
3328         if (is_zero_ether_addr(new_mac)) {
3329                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3330                 return -EINVAL;
3331         }
3332
3333         vf_id = filter->dst_id;
3334
3335         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3336                 PMD_DRV_LOG(ERR, "Invalid argument.");
3337                 return -EINVAL;
3338         }
3339         vf = &pf->vfs[vf_id];
3340
3341         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3342                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3343                 return -EINVAL;
3344         }
3345
3346         if (add) {
3347                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3348                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3349                                 ETHER_ADDR_LEN);
3350                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3351                                  ETHER_ADDR_LEN);
3352
3353                 mac_filter.filter_type = filter->filter_type;
3354                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3355                 if (ret != I40E_SUCCESS) {
3356                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3357                         return -1;
3358                 }
3359                 ether_addr_copy(new_mac, &pf->dev_addr);
3360         } else {
3361                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3362                                 ETHER_ADDR_LEN);
3363                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3364                 if (ret != I40E_SUCCESS) {
3365                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3366                         return -1;
3367                 }
3368
3369                 /* Clear device address as it has been removed */
3370                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3371                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3372         }
3373
3374         return 0;
3375 }
3376
3377 /* MAC filter handle */
3378 static int
3379 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3380                 void *arg)
3381 {
3382         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3383         struct rte_eth_mac_filter *filter;
3384         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3385         int ret = I40E_NOT_SUPPORTED;
3386
3387         filter = (struct rte_eth_mac_filter *)(arg);
3388
3389         switch (filter_op) {
3390         case RTE_ETH_FILTER_NOP:
3391                 ret = I40E_SUCCESS;
3392                 break;
3393         case RTE_ETH_FILTER_ADD:
3394                 i40e_pf_disable_irq0(hw);
3395                 if (filter->is_vf)
3396                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3397                 i40e_pf_enable_irq0(hw);
3398                 break;
3399         case RTE_ETH_FILTER_DELETE:
3400                 i40e_pf_disable_irq0(hw);
3401                 if (filter->is_vf)
3402                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3403                 i40e_pf_enable_irq0(hw);
3404                 break;
3405         default:
3406                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3407                 ret = I40E_ERR_PARAM;
3408                 break;
3409         }
3410
3411         return ret;
3412 }
3413
3414 static int
3415 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3416 {
3417         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3418         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3419         int ret;
3420
3421         if (!lut)
3422                 return -EINVAL;
3423
3424         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3425                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3426                                           lut, lut_size);
3427                 if (ret) {
3428                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3429                         return ret;
3430                 }
3431         } else {
3432                 uint32_t *lut_dw = (uint32_t *)lut;
3433                 uint16_t i, lut_size_dw = lut_size / 4;
3434
3435                 for (i = 0; i < lut_size_dw; i++)
3436                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3437         }
3438
3439         return 0;
3440 }
3441
3442 static int
3443 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3444 {
3445         struct i40e_pf *pf;
3446         struct i40e_hw *hw;
3447         int ret;
3448
3449         if (!vsi || !lut)
3450                 return -EINVAL;
3451
3452         pf = I40E_VSI_TO_PF(vsi);
3453         hw = I40E_VSI_TO_HW(vsi);
3454
3455         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3456                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3457                                           lut, lut_size);
3458                 if (ret) {
3459                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3460                         return ret;
3461                 }
3462         } else {
3463                 uint32_t *lut_dw = (uint32_t *)lut;
3464                 uint16_t i, lut_size_dw = lut_size / 4;
3465
3466                 for (i = 0; i < lut_size_dw; i++)
3467                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3468                 I40E_WRITE_FLUSH(hw);
3469         }
3470
3471         return 0;
3472 }
3473
3474 static int
3475 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3476                          struct rte_eth_rss_reta_entry64 *reta_conf,
3477                          uint16_t reta_size)
3478 {
3479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3480         uint16_t i, lut_size = pf->hash_lut_size;
3481         uint16_t idx, shift;
3482         uint8_t *lut;
3483         int ret;
3484
3485         if (reta_size != lut_size ||
3486                 reta_size > ETH_RSS_RETA_SIZE_512) {
3487                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3488                         "(%d) doesn't match the number hardware can supported "
3489                                         "(%d)\n", reta_size, lut_size);
3490                 return -EINVAL;
3491         }
3492
3493         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3494         if (!lut) {
3495                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3496                 return -ENOMEM;
3497         }
3498         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3499         if (ret)
3500                 goto out;
3501         for (i = 0; i < reta_size; i++) {
3502                 idx = i / RTE_RETA_GROUP_SIZE;
3503                 shift = i % RTE_RETA_GROUP_SIZE;
3504                 if (reta_conf[idx].mask & (1ULL << shift))
3505                         lut[i] = reta_conf[idx].reta[shift];
3506         }
3507         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3508
3509 out:
3510         rte_free(lut);
3511
3512         return ret;
3513 }
3514
3515 static int
3516 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3517                         struct rte_eth_rss_reta_entry64 *reta_conf,
3518                         uint16_t reta_size)
3519 {
3520         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3521         uint16_t i, lut_size = pf->hash_lut_size;
3522         uint16_t idx, shift;
3523         uint8_t *lut;
3524         int ret;
3525
3526         if (reta_size != lut_size ||
3527                 reta_size > ETH_RSS_RETA_SIZE_512) {
3528                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3529                         "(%d) doesn't match the number hardware can supported "
3530                                         "(%d)\n", reta_size, lut_size);
3531                 return -EINVAL;
3532         }
3533
3534         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3535         if (!lut) {
3536                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3537                 return -ENOMEM;
3538         }
3539
3540         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3541         if (ret)
3542                 goto out;
3543         for (i = 0; i < reta_size; i++) {
3544                 idx = i / RTE_RETA_GROUP_SIZE;
3545                 shift = i % RTE_RETA_GROUP_SIZE;
3546                 if (reta_conf[idx].mask & (1ULL << shift))
3547                         reta_conf[idx].reta[shift] = lut[i];
3548         }
3549
3550 out:
3551         rte_free(lut);
3552
3553         return ret;
3554 }
3555
3556 /**
3557  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3558  * @hw:   pointer to the HW structure
3559  * @mem:  pointer to mem struct to fill out
3560  * @size: size of memory requested
3561  * @alignment: what to align the allocation to
3562  **/
3563 enum i40e_status_code
3564 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3565                         struct i40e_dma_mem *mem,
3566                         u64 size,
3567                         u32 alignment)
3568 {
3569         const struct rte_memzone *mz = NULL;
3570         char z_name[RTE_MEMZONE_NAMESIZE];
3571
3572         if (!mem)
3573                 return I40E_ERR_PARAM;
3574
3575         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3576         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3577                                          alignment, RTE_PGSIZE_2M);
3578         if (!mz)
3579                 return I40E_ERR_NO_MEMORY;
3580
3581         mem->size = size;
3582         mem->va = mz->addr;
3583         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3584         mem->zone = (const void *)mz;
3585         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3586                     "%"PRIu64, mz->name, mem->pa);
3587
3588         return I40E_SUCCESS;
3589 }
3590
3591 /**
3592  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3593  * @hw:   pointer to the HW structure
3594  * @mem:  ptr to mem struct to free
3595  **/
3596 enum i40e_status_code
3597 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3598                     struct i40e_dma_mem *mem)
3599 {
3600         if (!mem)
3601                 return I40E_ERR_PARAM;
3602
3603         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3604                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3605                     mem->pa);
3606         rte_memzone_free((const struct rte_memzone *)mem->zone);
3607         mem->zone = NULL;
3608         mem->va = NULL;
3609         mem->pa = (u64)0;
3610
3611         return I40E_SUCCESS;
3612 }
3613
3614 /**
3615  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3616  * @hw:   pointer to the HW structure
3617  * @mem:  pointer to mem struct to fill out
3618  * @size: size of memory requested
3619  **/
3620 enum i40e_status_code
3621 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3622                          struct i40e_virt_mem *mem,
3623                          u32 size)
3624 {
3625         if (!mem)
3626                 return I40E_ERR_PARAM;
3627
3628         mem->size = size;
3629         mem->va = rte_zmalloc("i40e", size, 0);
3630
3631         if (mem->va)
3632                 return I40E_SUCCESS;
3633         else
3634                 return I40E_ERR_NO_MEMORY;
3635 }
3636
3637 /**
3638  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3639  * @hw:   pointer to the HW structure
3640  * @mem:  pointer to mem struct to free
3641  **/
3642 enum i40e_status_code
3643 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3644                      struct i40e_virt_mem *mem)
3645 {
3646         if (!mem)
3647                 return I40E_ERR_PARAM;
3648
3649         rte_free(mem->va);
3650         mem->va = NULL;
3651
3652         return I40E_SUCCESS;
3653 }
3654
3655 void
3656 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3657 {
3658         rte_spinlock_init(&sp->spinlock);
3659 }
3660
3661 void
3662 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3663 {
3664         rte_spinlock_lock(&sp->spinlock);
3665 }
3666
3667 void
3668 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3669 {
3670         rte_spinlock_unlock(&sp->spinlock);
3671 }
3672
3673 void
3674 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3675 {
3676         return;
3677 }
3678
3679 /**
3680  * Get the hardware capabilities, which will be parsed
3681  * and saved into struct i40e_hw.
3682  */
3683 static int
3684 i40e_get_cap(struct i40e_hw *hw)
3685 {
3686         struct i40e_aqc_list_capabilities_element_resp *buf;
3687         uint16_t len, size = 0;
3688         int ret;
3689
3690         /* Calculate a huge enough buff for saving response data temporarily */
3691         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3692                                                 I40E_MAX_CAP_ELE_NUM;
3693         buf = rte_zmalloc("i40e", len, 0);
3694         if (!buf) {
3695                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3696                 return I40E_ERR_NO_MEMORY;
3697         }
3698
3699         /* Get, parse the capabilities and save it to hw */
3700         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3701                         i40e_aqc_opc_list_func_capabilities, NULL);
3702         if (ret != I40E_SUCCESS)
3703                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3704
3705         /* Free the temporary buffer after being used */
3706         rte_free(buf);
3707
3708         return ret;
3709 }
3710
3711 static int
3712 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3713 {
3714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3715         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3716         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3717         uint16_t qp_count = 0, vsi_count = 0;
3718
3719         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3720                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3721                 return -EINVAL;
3722         }
3723         /* Add the parameter init for LFC */
3724         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3725         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3726         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3727
3728         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3729         pf->max_num_vsi = hw->func_caps.num_vsis;
3730         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3731         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3732         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3733
3734         /* FDir queue/VSI allocation */
3735         pf->fdir_qp_offset = 0;
3736         if (hw->func_caps.fd) {
3737                 pf->flags |= I40E_FLAG_FDIR;
3738                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3739         } else {
3740                 pf->fdir_nb_qps = 0;
3741         }
3742         qp_count += pf->fdir_nb_qps;
3743         vsi_count += 1;
3744
3745         /* LAN queue/VSI allocation */
3746         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3747         if (!hw->func_caps.rss) {
3748                 pf->lan_nb_qps = 1;
3749         } else {
3750                 pf->flags |= I40E_FLAG_RSS;
3751                 if (hw->mac.type == I40E_MAC_X722)
3752                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3753                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3754         }
3755         qp_count += pf->lan_nb_qps;
3756         vsi_count += 1;
3757
3758         /* VF queue/VSI allocation */
3759         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3760         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3761                 pf->flags |= I40E_FLAG_SRIOV;
3762                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3763                 pf->vf_num = pci_dev->max_vfs;
3764                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3765                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3766                             pf->vf_nb_qps * pf->vf_num);
3767         } else {
3768                 pf->vf_nb_qps = 0;
3769                 pf->vf_num = 0;
3770         }
3771         qp_count += pf->vf_nb_qps * pf->vf_num;
3772         vsi_count += pf->vf_num;
3773
3774         /* VMDq queue/VSI allocation */
3775         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3776         pf->vmdq_nb_qps = 0;
3777         pf->max_nb_vmdq_vsi = 0;
3778         if (hw->func_caps.vmdq) {
3779                 if (qp_count < hw->func_caps.num_tx_qp &&
3780                         vsi_count < hw->func_caps.num_vsis) {
3781                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3782                                 qp_count) / pf->vmdq_nb_qp_max;
3783
3784                         /* Limit the maximum number of VMDq vsi to the maximum
3785                          * ethdev can support
3786                          */
3787                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3788                                 hw->func_caps.num_vsis - vsi_count);
3789                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3790                                 ETH_64_POOLS);
3791                         if (pf->max_nb_vmdq_vsi) {
3792                                 pf->flags |= I40E_FLAG_VMDQ;
3793                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3794                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3795                                             "per VMDQ VSI, in total %u queues",
3796                                             pf->max_nb_vmdq_vsi,
3797                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3798                                             pf->max_nb_vmdq_vsi);
3799                         } else {
3800                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3801                                             "VMDq");
3802                         }
3803                 } else {
3804                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3805                 }
3806         }
3807         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3808         vsi_count += pf->max_nb_vmdq_vsi;
3809
3810         if (hw->func_caps.dcb)
3811                 pf->flags |= I40E_FLAG_DCB;
3812
3813         if (qp_count > hw->func_caps.num_tx_qp) {
3814                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3815                             "the hardware maximum %u", qp_count,
3816                             hw->func_caps.num_tx_qp);
3817                 return -EINVAL;
3818         }
3819         if (vsi_count > hw->func_caps.num_vsis) {
3820                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3821                             "the hardware maximum %u", vsi_count,
3822                             hw->func_caps.num_vsis);
3823                 return -EINVAL;
3824         }
3825
3826         return 0;
3827 }
3828
3829 static int
3830 i40e_pf_get_switch_config(struct i40e_pf *pf)
3831 {
3832         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3833         struct i40e_aqc_get_switch_config_resp *switch_config;
3834         struct i40e_aqc_switch_config_element_resp *element;
3835         uint16_t start_seid = 0, num_reported;
3836         int ret;
3837
3838         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3839                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3840         if (!switch_config) {
3841                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3842                 return -ENOMEM;
3843         }
3844
3845         /* Get the switch configurations */
3846         ret = i40e_aq_get_switch_config(hw, switch_config,
3847                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3848         if (ret != I40E_SUCCESS) {
3849                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3850                 goto fail;
3851         }
3852         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3853         if (num_reported != 1) { /* The number should be 1 */
3854                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3855                 goto fail;
3856         }
3857
3858         /* Parse the switch configuration elements */
3859         element = &(switch_config->element[0]);
3860         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3861                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3862                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3863         } else
3864                 PMD_DRV_LOG(INFO, "Unknown element type");
3865
3866 fail:
3867         rte_free(switch_config);
3868
3869         return ret;
3870 }
3871
3872 static int
3873 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3874                         uint32_t num)
3875 {
3876         struct pool_entry *entry;
3877
3878         if (pool == NULL || num == 0)
3879                 return -EINVAL;
3880
3881         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3882         if (entry == NULL) {
3883                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3884                 return -ENOMEM;
3885         }
3886
3887         /* queue heap initialize */
3888         pool->num_free = num;
3889         pool->num_alloc = 0;
3890         pool->base = base;
3891         LIST_INIT(&pool->alloc_list);
3892         LIST_INIT(&pool->free_list);
3893
3894         /* Initialize element  */
3895         entry->base = 0;
3896         entry->len = num;
3897
3898         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3899         return 0;
3900 }
3901
3902 static void
3903 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3904 {
3905         struct pool_entry *entry, *next_entry;
3906
3907         if (pool == NULL)
3908                 return;
3909
3910         for (entry = LIST_FIRST(&pool->alloc_list);
3911                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3912                         entry = next_entry) {
3913                 LIST_REMOVE(entry, next);
3914                 rte_free(entry);
3915         }
3916
3917         for (entry = LIST_FIRST(&pool->free_list);
3918                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3919                         entry = next_entry) {
3920                 LIST_REMOVE(entry, next);
3921                 rte_free(entry);
3922         }
3923
3924         pool->num_free = 0;
3925         pool->num_alloc = 0;
3926         pool->base = 0;
3927         LIST_INIT(&pool->alloc_list);
3928         LIST_INIT(&pool->free_list);
3929 }
3930
3931 static int
3932 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3933                        uint32_t base)
3934 {
3935         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3936         uint32_t pool_offset;
3937         int insert;
3938
3939         if (pool == NULL) {
3940                 PMD_DRV_LOG(ERR, "Invalid parameter");
3941                 return -EINVAL;
3942         }
3943
3944         pool_offset = base - pool->base;
3945         /* Lookup in alloc list */
3946         LIST_FOREACH(entry, &pool->alloc_list, next) {
3947                 if (entry->base == pool_offset) {
3948                         valid_entry = entry;
3949                         LIST_REMOVE(entry, next);
3950                         break;
3951                 }
3952         }
3953
3954         /* Not find, return */
3955         if (valid_entry == NULL) {
3956                 PMD_DRV_LOG(ERR, "Failed to find entry");
3957                 return -EINVAL;
3958         }
3959
3960         /**
3961          * Found it, move it to free list  and try to merge.
3962          * In order to make merge easier, always sort it by qbase.
3963          * Find adjacent prev and last entries.
3964          */
3965         prev = next = NULL;
3966         LIST_FOREACH(entry, &pool->free_list, next) {
3967                 if (entry->base > valid_entry->base) {
3968                         next = entry;
3969                         break;
3970                 }
3971                 prev = entry;
3972         }
3973
3974         insert = 0;
3975         /* Try to merge with next one*/
3976         if (next != NULL) {
3977                 /* Merge with next one */
3978                 if (valid_entry->base + valid_entry->len == next->base) {
3979                         next->base = valid_entry->base;
3980                         next->len += valid_entry->len;
3981                         rte_free(valid_entry);
3982                         valid_entry = next;
3983                         insert = 1;
3984                 }
3985         }
3986
3987         if (prev != NULL) {
3988                 /* Merge with previous one */
3989                 if (prev->base + prev->len == valid_entry->base) {
3990                         prev->len += valid_entry->len;
3991                         /* If it merge with next one, remove next node */
3992                         if (insert == 1) {
3993                                 LIST_REMOVE(valid_entry, next);
3994                                 rte_free(valid_entry);
3995                         } else {
3996                                 rte_free(valid_entry);
3997                                 insert = 1;
3998                         }
3999                 }
4000         }
4001
4002         /* Not find any entry to merge, insert */
4003         if (insert == 0) {
4004                 if (prev != NULL)
4005                         LIST_INSERT_AFTER(prev, valid_entry, next);
4006                 else if (next != NULL)
4007                         LIST_INSERT_BEFORE(next, valid_entry, next);
4008                 else /* It's empty list, insert to head */
4009                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4010         }
4011
4012         pool->num_free += valid_entry->len;
4013         pool->num_alloc -= valid_entry->len;
4014
4015         return 0;
4016 }
4017
4018 static int
4019 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4020                        uint16_t num)
4021 {
4022         struct pool_entry *entry, *valid_entry;
4023
4024         if (pool == NULL || num == 0) {
4025                 PMD_DRV_LOG(ERR, "Invalid parameter");
4026                 return -EINVAL;
4027         }
4028
4029         if (pool->num_free < num) {
4030                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4031                             num, pool->num_free);
4032                 return -ENOMEM;
4033         }
4034
4035         valid_entry = NULL;
4036         /* Lookup  in free list and find most fit one */
4037         LIST_FOREACH(entry, &pool->free_list, next) {
4038                 if (entry->len >= num) {
4039                         /* Find best one */
4040                         if (entry->len == num) {
4041                                 valid_entry = entry;
4042                                 break;
4043                         }
4044                         if (valid_entry == NULL || valid_entry->len > entry->len)
4045                                 valid_entry = entry;
4046                 }
4047         }
4048
4049         /* Not find one to satisfy the request, return */
4050         if (valid_entry == NULL) {
4051                 PMD_DRV_LOG(ERR, "No valid entry found");
4052                 return -ENOMEM;
4053         }
4054         /**
4055          * The entry have equal queue number as requested,
4056          * remove it from alloc_list.
4057          */
4058         if (valid_entry->len == num) {
4059                 LIST_REMOVE(valid_entry, next);
4060         } else {
4061                 /**
4062                  * The entry have more numbers than requested,
4063                  * create a new entry for alloc_list and minus its
4064                  * queue base and number in free_list.
4065                  */
4066                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4067                 if (entry == NULL) {
4068                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4069                                     "resource pool");
4070                         return -ENOMEM;
4071                 }
4072                 entry->base = valid_entry->base;
4073                 entry->len = num;
4074                 valid_entry->base += num;
4075                 valid_entry->len -= num;
4076                 valid_entry = entry;
4077         }
4078
4079         /* Insert it into alloc list, not sorted */
4080         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4081
4082         pool->num_free -= valid_entry->len;
4083         pool->num_alloc += valid_entry->len;
4084
4085         return valid_entry->base + pool->base;
4086 }
4087
4088 /**
4089  * bitmap_is_subset - Check whether src2 is subset of src1
4090  **/
4091 static inline int
4092 bitmap_is_subset(uint8_t src1, uint8_t src2)
4093 {
4094         return !((src1 ^ src2) & src2);
4095 }
4096
4097 static enum i40e_status_code
4098 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4099 {
4100         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4101
4102         /* If DCB is not supported, only default TC is supported */
4103         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4104                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4105                 return I40E_NOT_SUPPORTED;
4106         }
4107
4108         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4109                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4110                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4111                             enabled_tcmap);
4112                 return I40E_NOT_SUPPORTED;
4113         }
4114         return I40E_SUCCESS;
4115 }
4116
4117 int
4118 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4119                                 struct i40e_vsi_vlan_pvid_info *info)
4120 {
4121         struct i40e_hw *hw;
4122         struct i40e_vsi_context ctxt;
4123         uint8_t vlan_flags = 0;
4124         int ret;
4125
4126         if (vsi == NULL || info == NULL) {
4127                 PMD_DRV_LOG(ERR, "invalid parameters");
4128                 return I40E_ERR_PARAM;
4129         }
4130
4131         if (info->on) {
4132                 vsi->info.pvid = info->config.pvid;
4133                 /**
4134                  * If insert pvid is enabled, only tagged pkts are
4135                  * allowed to be sent out.
4136                  */
4137                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4138                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4139         } else {
4140                 vsi->info.pvid = 0;
4141                 if (info->config.reject.tagged == 0)
4142                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4143
4144                 if (info->config.reject.untagged == 0)
4145                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4146         }
4147         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4148                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4149         vsi->info.port_vlan_flags |= vlan_flags;
4150         vsi->info.valid_sections =
4151                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4152         memset(&ctxt, 0, sizeof(ctxt));
4153         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4154         ctxt.seid = vsi->seid;
4155
4156         hw = I40E_VSI_TO_HW(vsi);
4157         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4158         if (ret != I40E_SUCCESS)
4159                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4160
4161         return ret;
4162 }
4163
4164 static int
4165 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4166 {
4167         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4168         int i, ret;
4169         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4170
4171         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4172         if (ret != I40E_SUCCESS)
4173                 return ret;
4174
4175         if (!vsi->seid) {
4176                 PMD_DRV_LOG(ERR, "seid not valid");
4177                 return -EINVAL;
4178         }
4179
4180         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4181         tc_bw_data.tc_valid_bits = enabled_tcmap;
4182         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4183                 tc_bw_data.tc_bw_credits[i] =
4184                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4185
4186         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4187         if (ret != I40E_SUCCESS) {
4188                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4189                 return ret;
4190         }
4191
4192         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4193                                         sizeof(vsi->info.qs_handle));
4194         return I40E_SUCCESS;
4195 }
4196
4197 static enum i40e_status_code
4198 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4199                                  struct i40e_aqc_vsi_properties_data *info,
4200                                  uint8_t enabled_tcmap)
4201 {
4202         enum i40e_status_code ret;
4203         int i, total_tc = 0;
4204         uint16_t qpnum_per_tc, bsf, qp_idx;
4205
4206         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4207         if (ret != I40E_SUCCESS)
4208                 return ret;
4209
4210         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4211                 if (enabled_tcmap & (1 << i))
4212                         total_tc++;
4213         vsi->enabled_tc = enabled_tcmap;
4214
4215         /* Number of queues per enabled TC */
4216         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4217         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4218         bsf = rte_bsf32(qpnum_per_tc);
4219
4220         /* Adjust the queue number to actual queues that can be applied */
4221         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4222                 vsi->nb_qps = qpnum_per_tc * total_tc;
4223
4224         /**
4225          * Configure TC and queue mapping parameters, for enabled TC,
4226          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4227          * default queue will serve it.
4228          */
4229         qp_idx = 0;
4230         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4231                 if (vsi->enabled_tc & (1 << i)) {
4232                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4233                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4234                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4235                         qp_idx += qpnum_per_tc;
4236                 } else
4237                         info->tc_mapping[i] = 0;
4238         }
4239
4240         /* Associate queue number with VSI */
4241         if (vsi->type == I40E_VSI_SRIOV) {
4242                 info->mapping_flags |=
4243                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4244                 for (i = 0; i < vsi->nb_qps; i++)
4245                         info->queue_mapping[i] =
4246                                 rte_cpu_to_le_16(vsi->base_queue + i);
4247         } else {
4248                 info->mapping_flags |=
4249                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4250                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4251         }
4252         info->valid_sections |=
4253                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4254
4255         return I40E_SUCCESS;
4256 }
4257
4258 static int
4259 i40e_veb_release(struct i40e_veb *veb)
4260 {
4261         struct i40e_vsi *vsi;
4262         struct i40e_hw *hw;
4263
4264         if (veb == NULL)
4265                 return -EINVAL;
4266
4267         if (!TAILQ_EMPTY(&veb->head)) {
4268                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4269                 return -EACCES;
4270         }
4271         /* associate_vsi field is NULL for floating VEB */
4272         if (veb->associate_vsi != NULL) {
4273                 vsi = veb->associate_vsi;
4274                 hw = I40E_VSI_TO_HW(vsi);
4275
4276                 vsi->uplink_seid = veb->uplink_seid;
4277                 vsi->veb = NULL;
4278         } else {
4279                 veb->associate_pf->main_vsi->floating_veb = NULL;
4280                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4281         }
4282
4283         i40e_aq_delete_element(hw, veb->seid, NULL);
4284         rte_free(veb);
4285         return I40E_SUCCESS;
4286 }
4287
4288 /* Setup a veb */
4289 static struct i40e_veb *
4290 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4291 {
4292         struct i40e_veb *veb;
4293         int ret;
4294         struct i40e_hw *hw;
4295
4296         if (pf == NULL) {
4297                 PMD_DRV_LOG(ERR,
4298                             "veb setup failed, associated PF shouldn't null");
4299                 return NULL;
4300         }
4301         hw = I40E_PF_TO_HW(pf);
4302
4303         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4304         if (!veb) {
4305                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4306                 goto fail;
4307         }
4308
4309         veb->associate_vsi = vsi;
4310         veb->associate_pf = pf;
4311         TAILQ_INIT(&veb->head);
4312         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4313
4314         /* create floating veb if vsi is NULL */
4315         if (vsi != NULL) {
4316                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4317                                       I40E_DEFAULT_TCMAP, false,
4318                                       &veb->seid, false, NULL);
4319         } else {
4320                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4321                                       true, &veb->seid, false, NULL);
4322         }
4323
4324         if (ret != I40E_SUCCESS) {
4325                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4326                             hw->aq.asq_last_status);
4327                 goto fail;
4328         }
4329
4330         /* get statistics index */
4331         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4332                                 &veb->stats_idx, NULL, NULL, NULL);
4333         if (ret != I40E_SUCCESS) {
4334                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4335                             hw->aq.asq_last_status);
4336                 goto fail;
4337         }
4338         /* Get VEB bandwidth, to be implemented */
4339         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4340         if (vsi)
4341                 vsi->uplink_seid = veb->seid;
4342
4343         return veb;
4344 fail:
4345         rte_free(veb);
4346         return NULL;
4347 }
4348
4349 int
4350 i40e_vsi_release(struct i40e_vsi *vsi)
4351 {
4352         struct i40e_pf *pf;
4353         struct i40e_hw *hw;
4354         struct i40e_vsi_list *vsi_list;
4355         void *temp;
4356         int ret;
4357         struct i40e_mac_filter *f;
4358         uint16_t user_param;
4359
4360         if (!vsi)
4361                 return I40E_SUCCESS;
4362
4363         user_param = vsi->user_param;
4364
4365         pf = I40E_VSI_TO_PF(vsi);
4366         hw = I40E_VSI_TO_HW(vsi);
4367
4368         /* VSI has child to attach, release child first */
4369         if (vsi->veb) {
4370                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4371                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4372                                 return -1;
4373                 }
4374                 i40e_veb_release(vsi->veb);
4375         }
4376
4377         if (vsi->floating_veb) {
4378                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4379                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4380                                 return -1;
4381                 }
4382         }
4383
4384         /* Remove all macvlan filters of the VSI */
4385         i40e_vsi_remove_all_macvlan_filter(vsi);
4386         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4387                 rte_free(f);
4388
4389         if (vsi->type != I40E_VSI_MAIN &&
4390             ((vsi->type != I40E_VSI_SRIOV) ||
4391             !pf->floating_veb_list[user_param])) {
4392                 /* Remove vsi from parent's sibling list */
4393                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4394                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4395                         return I40E_ERR_PARAM;
4396                 }
4397                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4398                                 &vsi->sib_vsi_list, list);
4399
4400                 /* Remove all switch element of the VSI */
4401                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4402                 if (ret != I40E_SUCCESS)
4403                         PMD_DRV_LOG(ERR, "Failed to delete element");
4404         }
4405
4406         if ((vsi->type == I40E_VSI_SRIOV) &&
4407             pf->floating_veb_list[user_param]) {
4408                 /* Remove vsi from parent's sibling list */
4409                 if (vsi->parent_vsi == NULL ||
4410                     vsi->parent_vsi->floating_veb == NULL) {
4411                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4412                         return I40E_ERR_PARAM;
4413                 }
4414                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4415                              &vsi->sib_vsi_list, list);
4416
4417                 /* Remove all switch element of the VSI */
4418                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4419                 if (ret != I40E_SUCCESS)
4420                         PMD_DRV_LOG(ERR, "Failed to delete element");
4421         }
4422
4423         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4424
4425         if (vsi->type != I40E_VSI_SRIOV)
4426                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4427         rte_free(vsi);
4428
4429         return I40E_SUCCESS;
4430 }
4431
4432 static int
4433 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4434 {
4435         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4436         struct i40e_aqc_remove_macvlan_element_data def_filter;
4437         struct i40e_mac_filter_info filter;
4438         int ret;
4439
4440         if (vsi->type != I40E_VSI_MAIN)
4441                 return I40E_ERR_CONFIG;
4442         memset(&def_filter, 0, sizeof(def_filter));
4443         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4444                                         ETH_ADDR_LEN);
4445         def_filter.vlan_tag = 0;
4446         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4447                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4448         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4449         if (ret != I40E_SUCCESS) {
4450                 struct i40e_mac_filter *f;
4451                 struct ether_addr *mac;
4452
4453                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4454                             "macvlan filter");
4455                 /* It needs to add the permanent mac into mac list */
4456                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4457                 if (f == NULL) {
4458                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4459                         return I40E_ERR_NO_MEMORY;
4460                 }
4461                 mac = &f->mac_info.mac_addr;
4462                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4463                                 ETH_ADDR_LEN);
4464                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4465                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4466                 vsi->mac_num++;
4467
4468                 return ret;
4469         }
4470         (void)rte_memcpy(&filter.mac_addr,
4471                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4472         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4473         return i40e_vsi_add_mac(vsi, &filter);
4474 }
4475
4476 /*
4477  * i40e_vsi_get_bw_config - Query VSI BW Information
4478  * @vsi: the VSI to be queried
4479  *
4480  * Returns 0 on success, negative value on failure
4481  */
4482 static enum i40e_status_code
4483 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4484 {
4485         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4486         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4487         struct i40e_hw *hw = &vsi->adapter->hw;
4488         i40e_status ret;
4489         int i;
4490         uint32_t bw_max;
4491
4492         memset(&bw_config, 0, sizeof(bw_config));
4493         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4494         if (ret != I40E_SUCCESS) {
4495                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4496                             hw->aq.asq_last_status);
4497                 return ret;
4498         }
4499
4500         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4501         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4502                                         &ets_sla_config, NULL);
4503         if (ret != I40E_SUCCESS) {
4504                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4505                             "configuration %u", hw->aq.asq_last_status);
4506                 return ret;
4507         }
4508
4509         /* store and print out BW info */
4510         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4511         vsi->bw_info.bw_max = bw_config.max_bw;
4512         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4513         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4514         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4515                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4516                      I40E_16_BIT_WIDTH);
4517         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4518                 vsi->bw_info.bw_ets_share_credits[i] =
4519                                 ets_sla_config.share_credits[i];
4520                 vsi->bw_info.bw_ets_credits[i] =
4521                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4522                 /* 4 bits per TC, 4th bit is reserved */
4523                 vsi->bw_info.bw_ets_max[i] =
4524                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4525                                   RTE_LEN2MASK(3, uint8_t));
4526                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4527                             vsi->bw_info.bw_ets_share_credits[i]);
4528                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4529                             vsi->bw_info.bw_ets_credits[i]);
4530                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4531                             vsi->bw_info.bw_ets_max[i]);
4532         }
4533
4534         return I40E_SUCCESS;
4535 }
4536
4537 /* i40e_enable_pf_lb
4538  * @pf: pointer to the pf structure
4539  *
4540  * allow loopback on pf
4541  */
4542 static inline void
4543 i40e_enable_pf_lb(struct i40e_pf *pf)
4544 {
4545         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4546         struct i40e_vsi_context ctxt;
4547         int ret;
4548
4549         /* Use the FW API if FW >= v5.0 */
4550         if (hw->aq.fw_maj_ver < 5) {
4551                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4552                 return;
4553         }
4554
4555         memset(&ctxt, 0, sizeof(ctxt));
4556         ctxt.seid = pf->main_vsi_seid;
4557         ctxt.pf_num = hw->pf_id;
4558         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4559         if (ret) {
4560                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4561                             ret, hw->aq.asq_last_status);
4562                 return;
4563         }
4564         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4565         ctxt.info.valid_sections =
4566                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4567         ctxt.info.switch_id |=
4568                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4569
4570         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4571         if (ret)
4572                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4573                             hw->aq.asq_last_status);
4574 }
4575
4576 /* Setup a VSI */
4577 struct i40e_vsi *
4578 i40e_vsi_setup(struct i40e_pf *pf,
4579                enum i40e_vsi_type type,
4580                struct i40e_vsi *uplink_vsi,
4581                uint16_t user_param)
4582 {
4583         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4584         struct i40e_vsi *vsi;
4585         struct i40e_mac_filter_info filter;
4586         int ret;
4587         struct i40e_vsi_context ctxt;
4588         struct ether_addr broadcast =
4589                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4590
4591         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4592             uplink_vsi == NULL) {
4593                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4594                             "VSI link shouldn't be NULL");
4595                 return NULL;
4596         }
4597
4598         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4599                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4600                             "uplink VSI should be NULL");
4601                 return NULL;
4602         }
4603
4604         /* two situations
4605          * 1.type is not MAIN and uplink vsi is not NULL
4606          * If uplink vsi didn't setup VEB, create one first under veb field
4607          * 2.type is SRIOV and the uplink is NULL
4608          * If floating VEB is NULL, create one veb under floating veb field
4609          */
4610
4611         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4612             uplink_vsi->veb == NULL) {
4613                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4614
4615                 if (uplink_vsi->veb == NULL) {
4616                         PMD_DRV_LOG(ERR, "VEB setup failed");
4617                         return NULL;
4618                 }
4619                 /* set ALLOWLOOPBACk on pf, when veb is created */
4620                 i40e_enable_pf_lb(pf);
4621         }
4622
4623         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4624             pf->main_vsi->floating_veb == NULL) {
4625                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4626
4627                 if (pf->main_vsi->floating_veb == NULL) {
4628                         PMD_DRV_LOG(ERR, "VEB setup failed");
4629                         return NULL;
4630                 }
4631         }
4632
4633         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4634         if (!vsi) {
4635                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4636                 return NULL;
4637         }
4638         TAILQ_INIT(&vsi->mac_list);
4639         vsi->type = type;
4640         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4641         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4642         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4643         vsi->user_param = user_param;
4644         /* Allocate queues */
4645         switch (vsi->type) {
4646         case I40E_VSI_MAIN  :
4647                 vsi->nb_qps = pf->lan_nb_qps;
4648                 break;
4649         case I40E_VSI_SRIOV :
4650                 vsi->nb_qps = pf->vf_nb_qps;
4651                 break;
4652         case I40E_VSI_VMDQ2:
4653                 vsi->nb_qps = pf->vmdq_nb_qps;
4654                 break;
4655         case I40E_VSI_FDIR:
4656                 vsi->nb_qps = pf->fdir_nb_qps;
4657                 break;
4658         default:
4659                 goto fail_mem;
4660         }
4661         /*
4662          * The filter status descriptor is reported in rx queue 0,
4663          * while the tx queue for fdir filter programming has no
4664          * such constraints, can be non-zero queues.
4665          * To simplify it, choose FDIR vsi use queue 0 pair.
4666          * To make sure it will use queue 0 pair, queue allocation
4667          * need be done before this function is called
4668          */
4669         if (type != I40E_VSI_FDIR) {
4670                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4671                         if (ret < 0) {
4672                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4673                                                 vsi->seid, ret);
4674                                 goto fail_mem;
4675                         }
4676                         vsi->base_queue = ret;
4677         } else
4678                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4679
4680         /* VF has MSIX interrupt in VF range, don't allocate here */
4681         if (type == I40E_VSI_MAIN) {
4682                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4683                                           RTE_MIN(vsi->nb_qps,
4684                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4685                 if (ret < 0) {
4686                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4687                                     vsi->seid, ret);
4688                         goto fail_queue_alloc;
4689                 }
4690                 vsi->msix_intr = ret;
4691                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4692         } else if (type != I40E_VSI_SRIOV) {
4693                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4694                 if (ret < 0) {
4695                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4696                         goto fail_queue_alloc;
4697                 }
4698                 vsi->msix_intr = ret;
4699                 vsi->nb_msix = 1;
4700         } else {
4701                 vsi->msix_intr = 0;
4702                 vsi->nb_msix = 0;
4703         }
4704
4705         /* Add VSI */
4706         if (type == I40E_VSI_MAIN) {
4707                 /* For main VSI, no need to add since it's default one */
4708                 vsi->uplink_seid = pf->mac_seid;
4709                 vsi->seid = pf->main_vsi_seid;
4710                 /* Bind queues with specific MSIX interrupt */
4711                 /**
4712                  * Needs 2 interrupt at least, one for misc cause which will
4713                  * enabled from OS side, Another for queues binding the
4714                  * interrupt from device side only.
4715                  */
4716
4717                 /* Get default VSI parameters from hardware */
4718                 memset(&ctxt, 0, sizeof(ctxt));
4719                 ctxt.seid = vsi->seid;
4720                 ctxt.pf_num = hw->pf_id;
4721                 ctxt.uplink_seid = vsi->uplink_seid;
4722                 ctxt.vf_num = 0;
4723                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4724                 if (ret != I40E_SUCCESS) {
4725                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4726                         goto fail_msix_alloc;
4727                 }
4728                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4729                         sizeof(struct i40e_aqc_vsi_properties_data));
4730                 vsi->vsi_id = ctxt.vsi_number;
4731                 vsi->info.valid_sections = 0;
4732
4733                 /* Configure tc, enabled TC0 only */
4734                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4735                         I40E_SUCCESS) {
4736                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4737                         goto fail_msix_alloc;
4738                 }
4739
4740                 /* TC, queue mapping */
4741                 memset(&ctxt, 0, sizeof(ctxt));
4742                 vsi->info.valid_sections |=
4743                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4744                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4745                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4746                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4747                         sizeof(struct i40e_aqc_vsi_properties_data));
4748                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4749                                                 I40E_DEFAULT_TCMAP);
4750                 if (ret != I40E_SUCCESS) {
4751                         PMD_DRV_LOG(ERR, "Failed to configure "
4752                                     "TC queue mapping");
4753                         goto fail_msix_alloc;
4754                 }
4755                 ctxt.seid = vsi->seid;
4756                 ctxt.pf_num = hw->pf_id;
4757                 ctxt.uplink_seid = vsi->uplink_seid;
4758                 ctxt.vf_num = 0;
4759
4760                 /* Update VSI parameters */
4761                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4762                 if (ret != I40E_SUCCESS) {
4763                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4764                         goto fail_msix_alloc;
4765                 }
4766
4767                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4768                                                 sizeof(vsi->info.tc_mapping));
4769                 (void)rte_memcpy(&vsi->info.queue_mapping,
4770                                 &ctxt.info.queue_mapping,
4771                         sizeof(vsi->info.queue_mapping));
4772                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4773                 vsi->info.valid_sections = 0;
4774
4775                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4776                                 ETH_ADDR_LEN);
4777
4778                 /**
4779                  * Updating default filter settings are necessary to prevent
4780                  * reception of tagged packets.
4781                  * Some old firmware configurations load a default macvlan
4782                  * filter which accepts both tagged and untagged packets.
4783                  * The updating is to use a normal filter instead if needed.
4784                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4785                  * The firmware with correct configurations load the default
4786                  * macvlan filter which is expected and cannot be removed.
4787                  */
4788                 i40e_update_default_filter_setting(vsi);
4789                 i40e_config_qinq(hw, vsi);
4790         } else if (type == I40E_VSI_SRIOV) {
4791                 memset(&ctxt, 0, sizeof(ctxt));
4792                 /**
4793                  * For other VSI, the uplink_seid equals to uplink VSI's
4794                  * uplink_seid since they share same VEB
4795                  */
4796                 if (uplink_vsi == NULL)
4797                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4798                 else
4799                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4800                 ctxt.pf_num = hw->pf_id;
4801                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4802                 ctxt.uplink_seid = vsi->uplink_seid;
4803                 ctxt.connection_type = 0x1;
4804                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4805
4806                 /* Use the VEB configuration if FW >= v5.0 */
4807                 if (hw->aq.fw_maj_ver >= 5) {
4808                         /* Configure switch ID */
4809                         ctxt.info.valid_sections |=
4810                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4811                         ctxt.info.switch_id =
4812                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4813                 }
4814
4815                 /* Configure port/vlan */
4816                 ctxt.info.valid_sections |=
4817                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4818                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4819                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4820                                                 I40E_DEFAULT_TCMAP);
4821                 if (ret != I40E_SUCCESS) {
4822                         PMD_DRV_LOG(ERR, "Failed to configure "
4823                                     "TC queue mapping");
4824                         goto fail_msix_alloc;
4825                 }
4826                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4827                 ctxt.info.valid_sections |=
4828                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4829                 /**
4830                  * Since VSI is not created yet, only configure parameter,
4831                  * will add vsi below.
4832                  */
4833
4834                 i40e_config_qinq(hw, vsi);
4835         } else if (type == I40E_VSI_VMDQ2) {
4836                 memset(&ctxt, 0, sizeof(ctxt));
4837                 /*
4838                  * For other VSI, the uplink_seid equals to uplink VSI's
4839                  * uplink_seid since they share same VEB
4840                  */
4841                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4842                 ctxt.pf_num = hw->pf_id;
4843                 ctxt.vf_num = 0;
4844                 ctxt.uplink_seid = vsi->uplink_seid;
4845                 ctxt.connection_type = 0x1;
4846                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4847
4848                 ctxt.info.valid_sections |=
4849                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4850                 /* user_param carries flag to enable loop back */
4851                 if (user_param) {
4852                         ctxt.info.switch_id =
4853                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4854                         ctxt.info.switch_id |=
4855                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4856                 }
4857
4858                 /* Configure port/vlan */
4859                 ctxt.info.valid_sections |=
4860                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4861                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4862                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4863                                                 I40E_DEFAULT_TCMAP);
4864                 if (ret != I40E_SUCCESS) {
4865                         PMD_DRV_LOG(ERR, "Failed to configure "
4866                                         "TC queue mapping");
4867                         goto fail_msix_alloc;
4868                 }
4869                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4870                 ctxt.info.valid_sections |=
4871                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4872         } else if (type == I40E_VSI_FDIR) {
4873                 memset(&ctxt, 0, sizeof(ctxt));
4874                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4875                 ctxt.pf_num = hw->pf_id;
4876                 ctxt.vf_num = 0;
4877                 ctxt.uplink_seid = vsi->uplink_seid;
4878                 ctxt.connection_type = 0x1;     /* regular data port */
4879                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4880                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4881                                                 I40E_DEFAULT_TCMAP);
4882                 if (ret != I40E_SUCCESS) {
4883                         PMD_DRV_LOG(ERR, "Failed to configure "
4884                                         "TC queue mapping.");
4885                         goto fail_msix_alloc;
4886                 }
4887                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4888                 ctxt.info.valid_sections |=
4889                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4890         } else {
4891                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4892                 goto fail_msix_alloc;
4893         }
4894
4895         if (vsi->type != I40E_VSI_MAIN) {
4896                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4897                 if (ret != I40E_SUCCESS) {
4898                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4899                                     hw->aq.asq_last_status);
4900                         goto fail_msix_alloc;
4901                 }
4902                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4903                 vsi->info.valid_sections = 0;
4904                 vsi->seid = ctxt.seid;
4905                 vsi->vsi_id = ctxt.vsi_number;
4906                 vsi->sib_vsi_list.vsi = vsi;
4907                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4908                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4909                                           &vsi->sib_vsi_list, list);
4910                 } else {
4911                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4912                                           &vsi->sib_vsi_list, list);
4913                 }
4914         }
4915
4916         /* MAC/VLAN configuration */
4917         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4918         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4919
4920         ret = i40e_vsi_add_mac(vsi, &filter);
4921         if (ret != I40E_SUCCESS) {
4922                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4923                 goto fail_msix_alloc;
4924         }
4925
4926         /* Get VSI BW information */
4927         i40e_vsi_get_bw_config(vsi);
4928         return vsi;
4929 fail_msix_alloc:
4930         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4931 fail_queue_alloc:
4932         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4933 fail_mem:
4934         rte_free(vsi);
4935         return NULL;
4936 }
4937
4938 /* Configure vlan filter on or off */
4939 int
4940 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4941 {
4942         int i, num;
4943         struct i40e_mac_filter *f;
4944         void *temp;
4945         struct i40e_mac_filter_info *mac_filter;
4946         enum rte_mac_filter_type desired_filter;
4947         int ret = I40E_SUCCESS;
4948
4949         if (on) {
4950                 /* Filter to match MAC and VLAN */
4951                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4952         } else {
4953                 /* Filter to match only MAC */
4954                 desired_filter = RTE_MAC_PERFECT_MATCH;
4955         }
4956
4957         num = vsi->mac_num;
4958
4959         mac_filter = rte_zmalloc("mac_filter_info_data",
4960                                  num * sizeof(*mac_filter), 0);
4961         if (mac_filter == NULL) {
4962                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4963                 return I40E_ERR_NO_MEMORY;
4964         }
4965
4966         i = 0;
4967
4968         /* Remove all existing mac */
4969         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4970                 mac_filter[i] = f->mac_info;
4971                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4972                 if (ret) {
4973                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4974                                     on ? "enable" : "disable");
4975                         goto DONE;
4976                 }
4977                 i++;
4978         }
4979
4980         /* Override with new filter */
4981         for (i = 0; i < num; i++) {
4982                 mac_filter[i].filter_type = desired_filter;
4983                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4984                 if (ret) {
4985                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4986                                     on ? "enable" : "disable");
4987                         goto DONE;
4988                 }
4989         }
4990
4991 DONE:
4992         rte_free(mac_filter);
4993         return ret;
4994 }
4995
4996 /* Configure vlan stripping on or off */
4997 int
4998 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4999 {
5000         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5001         struct i40e_vsi_context ctxt;
5002         uint8_t vlan_flags;
5003         int ret = I40E_SUCCESS;
5004
5005         /* Check if it has been already on or off */
5006         if (vsi->info.valid_sections &
5007                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5008                 if (on) {
5009                         if ((vsi->info.port_vlan_flags &
5010                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5011                                 return 0; /* already on */
5012                 } else {
5013                         if ((vsi->info.port_vlan_flags &
5014                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5015                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5016                                 return 0; /* already off */
5017                 }
5018         }
5019
5020         if (on)
5021                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5022         else
5023                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5024         vsi->info.valid_sections =
5025                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5026         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5027         vsi->info.port_vlan_flags |= vlan_flags;
5028         ctxt.seid = vsi->seid;
5029         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5030         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5031         if (ret)
5032                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5033                             on ? "enable" : "disable");
5034
5035         return ret;
5036 }
5037
5038 static int
5039 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5040 {
5041         struct rte_eth_dev_data *data = dev->data;
5042         int ret;
5043         int mask = 0;
5044
5045         /* Apply vlan offload setting */
5046         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5047         i40e_vlan_offload_set(dev, mask);
5048
5049         /* Apply double-vlan setting, not implemented yet */
5050
5051         /* Apply pvid setting */
5052         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5053                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5054         if (ret)
5055                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5056
5057         return ret;
5058 }
5059
5060 static int
5061 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5062 {
5063         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5064
5065         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5066 }
5067
5068 static int
5069 i40e_update_flow_control(struct i40e_hw *hw)
5070 {
5071 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5072         struct i40e_link_status link_status;
5073         uint32_t rxfc = 0, txfc = 0, reg;
5074         uint8_t an_info;
5075         int ret;
5076
5077         memset(&link_status, 0, sizeof(link_status));
5078         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5079         if (ret != I40E_SUCCESS) {
5080                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5081                 goto write_reg; /* Disable flow control */
5082         }
5083
5084         an_info = hw->phy.link_info.an_info;
5085         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5086                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5087                 ret = I40E_ERR_NOT_READY;
5088                 goto write_reg; /* Disable flow control */
5089         }
5090         /**
5091          * If link auto negotiation is enabled, flow control needs to
5092          * be configured according to it
5093          */
5094         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5095         case I40E_LINK_PAUSE_RXTX:
5096                 rxfc = 1;
5097                 txfc = 1;
5098                 hw->fc.current_mode = I40E_FC_FULL;
5099                 break;
5100         case I40E_AQ_LINK_PAUSE_RX:
5101                 rxfc = 1;
5102                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5103                 break;
5104         case I40E_AQ_LINK_PAUSE_TX:
5105                 txfc = 1;
5106                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5107                 break;
5108         default:
5109                 hw->fc.current_mode = I40E_FC_NONE;
5110                 break;
5111         }
5112
5113 write_reg:
5114         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5115                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5116         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5117         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5118         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5119         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5120
5121         return ret;
5122 }
5123
5124 /* PF setup */
5125 static int
5126 i40e_pf_setup(struct i40e_pf *pf)
5127 {
5128         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5129         struct i40e_filter_control_settings settings;
5130         struct i40e_vsi *vsi;
5131         int ret;
5132
5133         /* Clear all stats counters */
5134         pf->offset_loaded = FALSE;
5135         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5136         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5137
5138         ret = i40e_pf_get_switch_config(pf);
5139         if (ret != I40E_SUCCESS) {
5140                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5141                 return ret;
5142         }
5143         if (pf->flags & I40E_FLAG_FDIR) {
5144                 /* make queue allocated first, let FDIR use queue pair 0*/
5145                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5146                 if (ret != I40E_FDIR_QUEUE_ID) {
5147                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5148                                     " ret =%d", ret);
5149                         pf->flags &= ~I40E_FLAG_FDIR;
5150                 }
5151         }
5152         /*  main VSI setup */
5153         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5154         if (!vsi) {
5155                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5156                 return I40E_ERR_NOT_READY;
5157         }
5158         pf->main_vsi = vsi;
5159
5160         /* Configure filter control */
5161         memset(&settings, 0, sizeof(settings));
5162         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5163                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5164         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5165                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5166         else {
5167                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5168                                                 hw->func_caps.rss_table_size);
5169                 return I40E_ERR_PARAM;
5170         }
5171         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5172                         "size: %u\n", hw->func_caps.rss_table_size);
5173         pf->hash_lut_size = hw->func_caps.rss_table_size;
5174
5175         /* Enable ethtype and macvlan filters */
5176         settings.enable_ethtype = TRUE;
5177         settings.enable_macvlan = TRUE;
5178         ret = i40e_set_filter_control(hw, &settings);
5179         if (ret)
5180                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5181                                                                 ret);
5182
5183         /* Update flow control according to the auto negotiation */
5184         i40e_update_flow_control(hw);
5185
5186         return I40E_SUCCESS;
5187 }
5188
5189 int
5190 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5191 {
5192         uint32_t reg;
5193         uint16_t j;
5194
5195         /**
5196          * Set or clear TX Queue Disable flags,
5197          * which is required by hardware.
5198          */
5199         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5200         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5201
5202         /* Wait until the request is finished */
5203         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5204                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5205                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5206                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5207                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5208                                                         & 0x1))) {
5209                         break;
5210                 }
5211         }
5212         if (on) {
5213                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5214                         return I40E_SUCCESS; /* already on, skip next steps */
5215
5216                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5217                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5218         } else {
5219                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5220                         return I40E_SUCCESS; /* already off, skip next steps */
5221                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5222         }
5223         /* Write the register */
5224         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5225         /* Check the result */
5226         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5227                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5228                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5229                 if (on) {
5230                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5231                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5232                                 break;
5233                 } else {
5234                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5235                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5236                                 break;
5237                 }
5238         }
5239         /* Check if it is timeout */
5240         if (j >= I40E_CHK_Q_ENA_COUNT) {
5241                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5242                             (on ? "enable" : "disable"), q_idx);
5243                 return I40E_ERR_TIMEOUT;
5244         }
5245
5246         return I40E_SUCCESS;
5247 }
5248
5249 /* Swith on or off the tx queues */
5250 static int
5251 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5252 {
5253         struct rte_eth_dev_data *dev_data = pf->dev_data;
5254         struct i40e_tx_queue *txq;
5255         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5256         uint16_t i;
5257         int ret;
5258
5259         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5260                 txq = dev_data->tx_queues[i];
5261                 /* Don't operate the queue if not configured or
5262                  * if starting only per queue */
5263                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5264                         continue;
5265                 if (on)
5266                         ret = i40e_dev_tx_queue_start(dev, i);
5267                 else
5268                         ret = i40e_dev_tx_queue_stop(dev, i);
5269                 if ( ret != I40E_SUCCESS)
5270                         return ret;
5271         }
5272
5273         return I40E_SUCCESS;
5274 }
5275
5276 int
5277 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5278 {
5279         uint32_t reg;
5280         uint16_t j;
5281
5282         /* Wait until the request is finished */
5283         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5284                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5285                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5286                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5287                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5288                         break;
5289         }
5290
5291         if (on) {
5292                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5293                         return I40E_SUCCESS; /* Already on, skip next steps */
5294                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5295         } else {
5296                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5297                         return I40E_SUCCESS; /* Already off, skip next steps */
5298                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5299         }
5300
5301         /* Write the register */
5302         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5303         /* Check the result */
5304         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5305                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5306                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5307                 if (on) {
5308                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5309                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5310                                 break;
5311                 } else {
5312                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5313                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5314                                 break;
5315                 }
5316         }
5317
5318         /* Check if it is timeout */
5319         if (j >= I40E_CHK_Q_ENA_COUNT) {
5320                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5321                             (on ? "enable" : "disable"), q_idx);
5322                 return I40E_ERR_TIMEOUT;
5323         }
5324
5325         return I40E_SUCCESS;
5326 }
5327 /* Switch on or off the rx queues */
5328 static int
5329 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5330 {
5331         struct rte_eth_dev_data *dev_data = pf->dev_data;
5332         struct i40e_rx_queue *rxq;
5333         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5334         uint16_t i;
5335         int ret;
5336
5337         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5338                 rxq = dev_data->rx_queues[i];
5339                 /* Don't operate the queue if not configured or
5340                  * if starting only per queue */
5341                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5342                         continue;
5343                 if (on)
5344                         ret = i40e_dev_rx_queue_start(dev, i);
5345                 else
5346                         ret = i40e_dev_rx_queue_stop(dev, i);
5347                 if (ret != I40E_SUCCESS)
5348                         return ret;
5349         }
5350
5351         return I40E_SUCCESS;
5352 }
5353
5354 /* Switch on or off all the rx/tx queues */
5355 int
5356 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5357 {
5358         int ret;
5359
5360         if (on) {
5361                 /* enable rx queues before enabling tx queues */
5362                 ret = i40e_dev_switch_rx_queues(pf, on);
5363                 if (ret) {
5364                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5365                         return ret;
5366                 }
5367                 ret = i40e_dev_switch_tx_queues(pf, on);
5368         } else {
5369                 /* Stop tx queues before stopping rx queues */
5370                 ret = i40e_dev_switch_tx_queues(pf, on);
5371                 if (ret) {
5372                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5373                         return ret;
5374                 }
5375                 ret = i40e_dev_switch_rx_queues(pf, on);
5376         }
5377
5378         return ret;
5379 }
5380
5381 /* Initialize VSI for TX */
5382 static int
5383 i40e_dev_tx_init(struct i40e_pf *pf)
5384 {
5385         struct rte_eth_dev_data *data = pf->dev_data;
5386         uint16_t i;
5387         uint32_t ret = I40E_SUCCESS;
5388         struct i40e_tx_queue *txq;
5389
5390         for (i = 0; i < data->nb_tx_queues; i++) {
5391                 txq = data->tx_queues[i];
5392                 if (!txq || !txq->q_set)
5393                         continue;
5394                 ret = i40e_tx_queue_init(txq);
5395                 if (ret != I40E_SUCCESS)
5396                         break;
5397         }
5398         if (ret == I40E_SUCCESS)
5399                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5400                                      ->eth_dev);
5401
5402         return ret;
5403 }
5404
5405 /* Initialize VSI for RX */
5406 static int
5407 i40e_dev_rx_init(struct i40e_pf *pf)
5408 {
5409         struct rte_eth_dev_data *data = pf->dev_data;
5410         int ret = I40E_SUCCESS;
5411         uint16_t i;
5412         struct i40e_rx_queue *rxq;
5413
5414         i40e_pf_config_mq_rx(pf);
5415         for (i = 0; i < data->nb_rx_queues; i++) {
5416                 rxq = data->rx_queues[i];
5417                 if (!rxq || !rxq->q_set)
5418                         continue;
5419
5420                 ret = i40e_rx_queue_init(rxq);
5421                 if (ret != I40E_SUCCESS) {
5422                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5423                                     "initialization");
5424                         break;
5425                 }
5426         }
5427         if (ret == I40E_SUCCESS)
5428                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5429                                      ->eth_dev);
5430
5431         return ret;
5432 }
5433
5434 static int
5435 i40e_dev_rxtx_init(struct i40e_pf *pf)
5436 {
5437         int err;
5438
5439         err = i40e_dev_tx_init(pf);
5440         if (err) {
5441                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5442                 return err;
5443         }
5444         err = i40e_dev_rx_init(pf);
5445         if (err) {
5446                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5447                 return err;
5448         }
5449
5450         return err;
5451 }
5452
5453 static int
5454 i40e_vmdq_setup(struct rte_eth_dev *dev)
5455 {
5456         struct rte_eth_conf *conf = &dev->data->dev_conf;
5457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5458         int i, err, conf_vsis, j, loop;
5459         struct i40e_vsi *vsi;
5460         struct i40e_vmdq_info *vmdq_info;
5461         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5462         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5463
5464         /*
5465          * Disable interrupt to avoid message from VF. Furthermore, it will
5466          * avoid race condition in VSI creation/destroy.
5467          */
5468         i40e_pf_disable_irq0(hw);
5469
5470         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5471                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5472                 return -ENOTSUP;
5473         }
5474
5475         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5476         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5477                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5478                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5479                         pf->max_nb_vmdq_vsi);
5480                 return -ENOTSUP;
5481         }
5482
5483         if (pf->vmdq != NULL) {
5484                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5485                 return 0;
5486         }
5487
5488         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5489                                 sizeof(*vmdq_info) * conf_vsis, 0);
5490
5491         if (pf->vmdq == NULL) {
5492                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5493                 return -ENOMEM;
5494         }
5495
5496         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5497
5498         /* Create VMDQ VSI */
5499         for (i = 0; i < conf_vsis; i++) {
5500                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5501                                 vmdq_conf->enable_loop_back);
5502                 if (vsi == NULL) {
5503                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5504                         err = -1;
5505                         goto err_vsi_setup;
5506                 }
5507                 vmdq_info = &pf->vmdq[i];
5508                 vmdq_info->pf = pf;
5509                 vmdq_info->vsi = vsi;
5510         }
5511         pf->nb_cfg_vmdq_vsi = conf_vsis;
5512
5513         /* Configure Vlan */
5514         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5515         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5516                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5517                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5518                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5519                                         vmdq_conf->pool_map[i].vlan_id, j);
5520
5521                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5522                                                 vmdq_conf->pool_map[i].vlan_id);
5523                                 if (err) {
5524                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5525                                         err = -1;
5526                                         goto err_vsi_setup;
5527                                 }
5528                         }
5529                 }
5530         }
5531
5532         i40e_pf_enable_irq0(hw);
5533
5534         return 0;
5535
5536 err_vsi_setup:
5537         for (i = 0; i < conf_vsis; i++)
5538                 if (pf->vmdq[i].vsi == NULL)
5539                         break;
5540                 else
5541                         i40e_vsi_release(pf->vmdq[i].vsi);
5542
5543         rte_free(pf->vmdq);
5544         pf->vmdq = NULL;
5545         i40e_pf_enable_irq0(hw);
5546         return err;
5547 }
5548
5549 static void
5550 i40e_stat_update_32(struct i40e_hw *hw,
5551                    uint32_t reg,
5552                    bool offset_loaded,
5553                    uint64_t *offset,
5554                    uint64_t *stat)
5555 {
5556         uint64_t new_data;
5557
5558         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5559         if (!offset_loaded)
5560                 *offset = new_data;
5561
5562         if (new_data >= *offset)
5563                 *stat = (uint64_t)(new_data - *offset);
5564         else
5565                 *stat = (uint64_t)((new_data +
5566                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5567 }
5568
5569 static void
5570 i40e_stat_update_48(struct i40e_hw *hw,
5571                    uint32_t hireg,
5572                    uint32_t loreg,
5573                    bool offset_loaded,
5574                    uint64_t *offset,
5575                    uint64_t *stat)
5576 {
5577         uint64_t new_data;
5578
5579         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5580         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5581                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5582
5583         if (!offset_loaded)
5584                 *offset = new_data;
5585
5586         if (new_data >= *offset)
5587                 *stat = new_data - *offset;
5588         else
5589                 *stat = (uint64_t)((new_data +
5590                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5591
5592         *stat &= I40E_48_BIT_MASK;
5593 }
5594
5595 /* Disable IRQ0 */
5596 void
5597 i40e_pf_disable_irq0(struct i40e_hw *hw)
5598 {
5599         /* Disable all interrupt types */
5600         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5601         I40E_WRITE_FLUSH(hw);
5602 }
5603
5604 /* Enable IRQ0 */
5605 void
5606 i40e_pf_enable_irq0(struct i40e_hw *hw)
5607 {
5608         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5609                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5610                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5611                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5612         I40E_WRITE_FLUSH(hw);
5613 }
5614
5615 static void
5616 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5617 {
5618         /* read pending request and disable first */
5619         i40e_pf_disable_irq0(hw);
5620         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5621         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5622                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5623
5624         if (no_queue)
5625                 /* Link no queues with irq0 */
5626                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5627                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5628 }
5629
5630 static void
5631 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5632 {
5633         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5635         int i;
5636         uint16_t abs_vf_id;
5637         uint32_t index, offset, val;
5638
5639         if (!pf->vfs)
5640                 return;
5641         /**
5642          * Try to find which VF trigger a reset, use absolute VF id to access
5643          * since the reg is global register.
5644          */
5645         for (i = 0; i < pf->vf_num; i++) {
5646                 abs_vf_id = hw->func_caps.vf_base_id + i;
5647                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5648                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5649                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5650                 /* VFR event occured */
5651                 if (val & (0x1 << offset)) {
5652                         int ret;
5653
5654                         /* Clear the event first */
5655                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5656                                                         (0x1 << offset));
5657                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5658                         /**
5659                          * Only notify a VF reset event occured,
5660                          * don't trigger another SW reset
5661                          */
5662                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5663                         if (ret != I40E_SUCCESS)
5664                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5665                 }
5666         }
5667 }
5668
5669 static void
5670 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5671 {
5672         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5673         struct i40e_virtchnl_pf_event event;
5674         int i;
5675
5676         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5677         event.event_data.link_event.link_status =
5678                 dev->data->dev_link.link_status;
5679         event.event_data.link_event.link_speed =
5680                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5681
5682         for (i = 0; i < pf->vf_num; i++)
5683                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5684                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5685 }
5686
5687 static void
5688 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5689 {
5690         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5691         struct i40e_arq_event_info info;
5692         uint16_t pending, opcode;
5693         int ret;
5694
5695         info.buf_len = I40E_AQ_BUF_SZ;
5696         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5697         if (!info.msg_buf) {
5698                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5699                 return;
5700         }
5701
5702         pending = 1;
5703         while (pending) {
5704                 ret = i40e_clean_arq_element(hw, &info, &pending);
5705
5706                 if (ret != I40E_SUCCESS) {
5707                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5708                                     "aq_err: %u", hw->aq.asq_last_status);
5709                         break;
5710                 }
5711                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5712
5713                 switch (opcode) {
5714                 case i40e_aqc_opc_send_msg_to_pf:
5715                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5716                         i40e_pf_host_handle_vf_msg(dev,
5717                                         rte_le_to_cpu_16(info.desc.retval),
5718                                         rte_le_to_cpu_32(info.desc.cookie_high),
5719                                         rte_le_to_cpu_32(info.desc.cookie_low),
5720                                         info.msg_buf,
5721                                         info.msg_len);
5722                         break;
5723                 case i40e_aqc_opc_get_link_status:
5724                         ret = i40e_dev_link_update(dev, 0);
5725                         if (!ret) {
5726                                 i40e_notify_all_vfs_link_status(dev);
5727                                 _rte_eth_dev_callback_process(dev,
5728                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5729                         }
5730                         break;
5731                 default:
5732                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5733                                     opcode);
5734                         break;
5735                 }
5736         }
5737         rte_free(info.msg_buf);
5738 }
5739
5740 /**
5741  * Interrupt handler triggered by NIC  for handling
5742  * specific interrupt.
5743  *
5744  * @param handle
5745  *  Pointer to interrupt handle.
5746  * @param param
5747  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5748  *
5749  * @return
5750  *  void
5751  */
5752 static void
5753 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5754                            void *param)
5755 {
5756         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5757         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5758         uint32_t icr0;
5759
5760         /* Disable interrupt */
5761         i40e_pf_disable_irq0(hw);
5762
5763         /* read out interrupt causes */
5764         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5765
5766         /* No interrupt event indicated */
5767         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5768                 PMD_DRV_LOG(INFO, "No interrupt event");
5769                 goto done;
5770         }
5771 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5772         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5773                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5774         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5775                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5776         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5777                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5778         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5779                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5780         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5781                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5782         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5783                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5784         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5785                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5786 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5787
5788         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5789                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5790                 i40e_dev_handle_vfr_event(dev);
5791         }
5792         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5793                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5794                 i40e_dev_handle_aq_msg(dev);
5795         }
5796
5797 done:
5798         /* Enable interrupt */
5799         i40e_pf_enable_irq0(hw);
5800         rte_intr_enable(intr_handle);
5801 }
5802
5803 static int
5804 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5805                          struct i40e_macvlan_filter *filter,
5806                          int total)
5807 {
5808         int ele_num, ele_buff_size;
5809         int num, actual_num, i;
5810         uint16_t flags;
5811         int ret = I40E_SUCCESS;
5812         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5813         struct i40e_aqc_add_macvlan_element_data *req_list;
5814
5815         if (filter == NULL  || total == 0)
5816                 return I40E_ERR_PARAM;
5817         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5818         ele_buff_size = hw->aq.asq_buf_size;
5819
5820         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5821         if (req_list == NULL) {
5822                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5823                 return I40E_ERR_NO_MEMORY;
5824         }
5825
5826         num = 0;
5827         do {
5828                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5829                 memset(req_list, 0, ele_buff_size);
5830
5831                 for (i = 0; i < actual_num; i++) {
5832                         (void)rte_memcpy(req_list[i].mac_addr,
5833                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5834                         req_list[i].vlan_tag =
5835                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5836
5837                         switch (filter[num + i].filter_type) {
5838                         case RTE_MAC_PERFECT_MATCH:
5839                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5840                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5841                                 break;
5842                         case RTE_MACVLAN_PERFECT_MATCH:
5843                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5844                                 break;
5845                         case RTE_MAC_HASH_MATCH:
5846                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5847                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5848                                 break;
5849                         case RTE_MACVLAN_HASH_MATCH:
5850                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5851                                 break;
5852                         default:
5853                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5854                                 ret = I40E_ERR_PARAM;
5855                                 goto DONE;
5856                         }
5857
5858                         req_list[i].queue_number = 0;
5859
5860                         req_list[i].flags = rte_cpu_to_le_16(flags);
5861                 }
5862
5863                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5864                                                 actual_num, NULL);
5865                 if (ret != I40E_SUCCESS) {
5866                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5867                         goto DONE;
5868                 }
5869                 num += actual_num;
5870         } while (num < total);
5871
5872 DONE:
5873         rte_free(req_list);
5874         return ret;
5875 }
5876
5877 static int
5878 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5879                             struct i40e_macvlan_filter *filter,
5880                             int total)
5881 {
5882         int ele_num, ele_buff_size;
5883         int num, actual_num, i;
5884         uint16_t flags;
5885         int ret = I40E_SUCCESS;
5886         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5887         struct i40e_aqc_remove_macvlan_element_data *req_list;
5888
5889         if (filter == NULL  || total == 0)
5890                 return I40E_ERR_PARAM;
5891
5892         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5893         ele_buff_size = hw->aq.asq_buf_size;
5894
5895         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5896         if (req_list == NULL) {
5897                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5898                 return I40E_ERR_NO_MEMORY;
5899         }
5900
5901         num = 0;
5902         do {
5903                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5904                 memset(req_list, 0, ele_buff_size);
5905
5906                 for (i = 0; i < actual_num; i++) {
5907                         (void)rte_memcpy(req_list[i].mac_addr,
5908                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5909                         req_list[i].vlan_tag =
5910                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5911
5912                         switch (filter[num + i].filter_type) {
5913                         case RTE_MAC_PERFECT_MATCH:
5914                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5915                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5916                                 break;
5917                         case RTE_MACVLAN_PERFECT_MATCH:
5918                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5919                                 break;
5920                         case RTE_MAC_HASH_MATCH:
5921                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5922                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5923                                 break;
5924                         case RTE_MACVLAN_HASH_MATCH:
5925                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5926                                 break;
5927                         default:
5928                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5929                                 ret = I40E_ERR_PARAM;
5930                                 goto DONE;
5931                         }
5932                         req_list[i].flags = rte_cpu_to_le_16(flags);
5933                 }
5934
5935                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5936                                                 actual_num, NULL);
5937                 if (ret != I40E_SUCCESS) {
5938                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5939                         goto DONE;
5940                 }
5941                 num += actual_num;
5942         } while (num < total);
5943
5944 DONE:
5945         rte_free(req_list);
5946         return ret;
5947 }
5948
5949 /* Find out specific MAC filter */
5950 static struct i40e_mac_filter *
5951 i40e_find_mac_filter(struct i40e_vsi *vsi,
5952                          struct ether_addr *macaddr)
5953 {
5954         struct i40e_mac_filter *f;
5955
5956         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5957                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5958                         return f;
5959         }
5960
5961         return NULL;
5962 }
5963
5964 static bool
5965 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5966                          uint16_t vlan_id)
5967 {
5968         uint32_t vid_idx, vid_bit;
5969
5970         if (vlan_id > ETH_VLAN_ID_MAX)
5971                 return 0;
5972
5973         vid_idx = I40E_VFTA_IDX(vlan_id);
5974         vid_bit = I40E_VFTA_BIT(vlan_id);
5975
5976         if (vsi->vfta[vid_idx] & vid_bit)
5977                 return 1;
5978         else
5979                 return 0;
5980 }
5981
5982 static void
5983 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5984                          uint16_t vlan_id, bool on)
5985 {
5986         uint32_t vid_idx, vid_bit;
5987
5988         if (vlan_id > ETH_VLAN_ID_MAX)
5989                 return;
5990
5991         vid_idx = I40E_VFTA_IDX(vlan_id);
5992         vid_bit = I40E_VFTA_BIT(vlan_id);
5993
5994         if (on)
5995                 vsi->vfta[vid_idx] |= vid_bit;
5996         else
5997                 vsi->vfta[vid_idx] &= ~vid_bit;
5998 }
5999
6000 /**
6001  * Find all vlan options for specific mac addr,
6002  * return with actual vlan found.
6003  */
6004 static inline int
6005 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6006                            struct i40e_macvlan_filter *mv_f,
6007                            int num, struct ether_addr *addr)
6008 {
6009         int i;
6010         uint32_t j, k;
6011
6012         /**
6013          * Not to use i40e_find_vlan_filter to decrease the loop time,
6014          * although the code looks complex.
6015           */
6016         if (num < vsi->vlan_num)
6017                 return I40E_ERR_PARAM;
6018
6019         i = 0;
6020         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6021                 if (vsi->vfta[j]) {
6022                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6023                                 if (vsi->vfta[j] & (1 << k)) {
6024                                         if (i > num - 1) {
6025                                                 PMD_DRV_LOG(ERR, "vlan number "
6026                                                             "not match");
6027                                                 return I40E_ERR_PARAM;
6028                                         }
6029                                         (void)rte_memcpy(&mv_f[i].macaddr,
6030                                                         addr, ETH_ADDR_LEN);
6031                                         mv_f[i].vlan_id =
6032                                                 j * I40E_UINT32_BIT_SIZE + k;
6033                                         i++;
6034                                 }
6035                         }
6036                 }
6037         }
6038         return I40E_SUCCESS;
6039 }
6040
6041 static inline int
6042 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6043                            struct i40e_macvlan_filter *mv_f,
6044                            int num,
6045                            uint16_t vlan)
6046 {
6047         int i = 0;
6048         struct i40e_mac_filter *f;
6049
6050         if (num < vsi->mac_num)
6051                 return I40E_ERR_PARAM;
6052
6053         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6054                 if (i > num - 1) {
6055                         PMD_DRV_LOG(ERR, "buffer number not match");
6056                         return I40E_ERR_PARAM;
6057                 }
6058                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6059                                 ETH_ADDR_LEN);
6060                 mv_f[i].vlan_id = vlan;
6061                 mv_f[i].filter_type = f->mac_info.filter_type;
6062                 i++;
6063         }
6064
6065         return I40E_SUCCESS;
6066 }
6067
6068 static int
6069 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6070 {
6071         int i, num;
6072         struct i40e_mac_filter *f;
6073         struct i40e_macvlan_filter *mv_f;
6074         int ret = I40E_SUCCESS;
6075
6076         if (vsi == NULL || vsi->mac_num == 0)
6077                 return I40E_ERR_PARAM;
6078
6079         /* Case that no vlan is set */
6080         if (vsi->vlan_num == 0)
6081                 num = vsi->mac_num;
6082         else
6083                 num = vsi->mac_num * vsi->vlan_num;
6084
6085         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6086         if (mv_f == NULL) {
6087                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6088                 return I40E_ERR_NO_MEMORY;
6089         }
6090
6091         i = 0;
6092         if (vsi->vlan_num == 0) {
6093                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6094                         (void)rte_memcpy(&mv_f[i].macaddr,
6095                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6096                         mv_f[i].vlan_id = 0;
6097                         i++;
6098                 }
6099         } else {
6100                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6101                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6102                                         vsi->vlan_num, &f->mac_info.mac_addr);
6103                         if (ret != I40E_SUCCESS)
6104                                 goto DONE;
6105                         i += vsi->vlan_num;
6106                 }
6107         }
6108
6109         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6110 DONE:
6111         rte_free(mv_f);
6112
6113         return ret;
6114 }
6115
6116 int
6117 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6118 {
6119         struct i40e_macvlan_filter *mv_f;
6120         int mac_num;
6121         int ret = I40E_SUCCESS;
6122
6123         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6124                 return I40E_ERR_PARAM;
6125
6126         /* If it's already set, just return */
6127         if (i40e_find_vlan_filter(vsi,vlan))
6128                 return I40E_SUCCESS;
6129
6130         mac_num = vsi->mac_num;
6131
6132         if (mac_num == 0) {
6133                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6134                 return I40E_ERR_PARAM;
6135         }
6136
6137         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6138
6139         if (mv_f == NULL) {
6140                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6141                 return I40E_ERR_NO_MEMORY;
6142         }
6143
6144         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6145
6146         if (ret != I40E_SUCCESS)
6147                 goto DONE;
6148
6149         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6150
6151         if (ret != I40E_SUCCESS)
6152                 goto DONE;
6153
6154         i40e_set_vlan_filter(vsi, vlan, 1);
6155
6156         vsi->vlan_num++;
6157         ret = I40E_SUCCESS;
6158 DONE:
6159         rte_free(mv_f);
6160         return ret;
6161 }
6162
6163 int
6164 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6165 {
6166         struct i40e_macvlan_filter *mv_f;
6167         int mac_num;
6168         int ret = I40E_SUCCESS;
6169
6170         /**
6171          * Vlan 0 is the generic filter for untagged packets
6172          * and can't be removed.
6173          */
6174         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6175                 return I40E_ERR_PARAM;
6176
6177         /* If can't find it, just return */
6178         if (!i40e_find_vlan_filter(vsi, vlan))
6179                 return I40E_ERR_PARAM;
6180
6181         mac_num = vsi->mac_num;
6182
6183         if (mac_num == 0) {
6184                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6185                 return I40E_ERR_PARAM;
6186         }
6187
6188         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6189
6190         if (mv_f == NULL) {
6191                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6192                 return I40E_ERR_NO_MEMORY;
6193         }
6194
6195         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6196
6197         if (ret != I40E_SUCCESS)
6198                 goto DONE;
6199
6200         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6201
6202         if (ret != I40E_SUCCESS)
6203                 goto DONE;
6204
6205         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6206         if (vsi->vlan_num == 1) {
6207                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6208                 if (ret != I40E_SUCCESS)
6209                         goto DONE;
6210
6211                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6212                 if (ret != I40E_SUCCESS)
6213                         goto DONE;
6214         }
6215
6216         i40e_set_vlan_filter(vsi, vlan, 0);
6217
6218         vsi->vlan_num--;
6219         ret = I40E_SUCCESS;
6220 DONE:
6221         rte_free(mv_f);
6222         return ret;
6223 }
6224
6225 int
6226 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6227 {
6228         struct i40e_mac_filter *f;
6229         struct i40e_macvlan_filter *mv_f;
6230         int i, vlan_num = 0;
6231         int ret = I40E_SUCCESS;
6232
6233         /* If it's add and we've config it, return */
6234         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6235         if (f != NULL)
6236                 return I40E_SUCCESS;
6237         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6238                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6239
6240                 /**
6241                  * If vlan_num is 0, that's the first time to add mac,
6242                  * set mask for vlan_id 0.
6243                  */
6244                 if (vsi->vlan_num == 0) {
6245                         i40e_set_vlan_filter(vsi, 0, 1);
6246                         vsi->vlan_num = 1;
6247                 }
6248                 vlan_num = vsi->vlan_num;
6249         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6250                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6251                 vlan_num = 1;
6252
6253         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6254         if (mv_f == NULL) {
6255                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6256                 return I40E_ERR_NO_MEMORY;
6257         }
6258
6259         for (i = 0; i < vlan_num; i++) {
6260                 mv_f[i].filter_type = mac_filter->filter_type;
6261                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6262                                 ETH_ADDR_LEN);
6263         }
6264
6265         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6266                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6267                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6268                                         &mac_filter->mac_addr);
6269                 if (ret != I40E_SUCCESS)
6270                         goto DONE;
6271         }
6272
6273         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6274         if (ret != I40E_SUCCESS)
6275                 goto DONE;
6276
6277         /* Add the mac addr into mac list */
6278         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6279         if (f == NULL) {
6280                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6281                 ret = I40E_ERR_NO_MEMORY;
6282                 goto DONE;
6283         }
6284         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6285                         ETH_ADDR_LEN);
6286         f->mac_info.filter_type = mac_filter->filter_type;
6287         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6288         vsi->mac_num++;
6289
6290         ret = I40E_SUCCESS;
6291 DONE:
6292         rte_free(mv_f);
6293
6294         return ret;
6295 }
6296
6297 int
6298 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6299 {
6300         struct i40e_mac_filter *f;
6301         struct i40e_macvlan_filter *mv_f;
6302         int i, vlan_num;
6303         enum rte_mac_filter_type filter_type;
6304         int ret = I40E_SUCCESS;
6305
6306         /* Can't find it, return an error */
6307         f = i40e_find_mac_filter(vsi, addr);
6308         if (f == NULL)
6309                 return I40E_ERR_PARAM;
6310
6311         vlan_num = vsi->vlan_num;
6312         filter_type = f->mac_info.filter_type;
6313         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6314                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6315                 if (vlan_num == 0) {
6316                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6317                         return I40E_ERR_PARAM;
6318                 }
6319         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6320                         filter_type == RTE_MAC_HASH_MATCH)
6321                 vlan_num = 1;
6322
6323         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6324         if (mv_f == NULL) {
6325                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6326                 return I40E_ERR_NO_MEMORY;
6327         }
6328
6329         for (i = 0; i < vlan_num; i++) {
6330                 mv_f[i].filter_type = filter_type;
6331                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6332                                 ETH_ADDR_LEN);
6333         }
6334         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6335                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6336                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6337                 if (ret != I40E_SUCCESS)
6338                         goto DONE;
6339         }
6340
6341         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6342         if (ret != I40E_SUCCESS)
6343                 goto DONE;
6344
6345         /* Remove the mac addr into mac list */
6346         TAILQ_REMOVE(&vsi->mac_list, f, next);
6347         rte_free(f);
6348         vsi->mac_num--;
6349
6350         ret = I40E_SUCCESS;
6351 DONE:
6352         rte_free(mv_f);
6353         return ret;
6354 }
6355
6356 /* Configure hash enable flags for RSS */
6357 uint64_t
6358 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6359 {
6360         uint64_t hena = 0;
6361
6362         if (!flags)
6363                 return hena;
6364
6365         if (flags & ETH_RSS_FRAG_IPV4)
6366                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6367         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6368                 if (type == I40E_MAC_X722) {
6369                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6370                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6371                 } else
6372                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6373         }
6374         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6375                 if (type == I40E_MAC_X722) {
6376                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6377                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6378                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6379                 } else
6380                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6381         }
6382         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6383                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6384         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6385                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6386         if (flags & ETH_RSS_FRAG_IPV6)
6387                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6388         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6389                 if (type == I40E_MAC_X722) {
6390                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6391                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6392                 } else
6393                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6394         }
6395         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6396                 if (type == I40E_MAC_X722) {
6397                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6398                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6399                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6400                 } else
6401                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6402         }
6403         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6404                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6405         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6406                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6407         if (flags & ETH_RSS_L2_PAYLOAD)
6408                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6409
6410         return hena;
6411 }
6412
6413 /* Parse the hash enable flags */
6414 uint64_t
6415 i40e_parse_hena(uint64_t flags)
6416 {
6417         uint64_t rss_hf = 0;
6418
6419         if (!flags)
6420                 return rss_hf;
6421         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6422                 rss_hf |= ETH_RSS_FRAG_IPV4;
6423         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6424                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6425         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6426                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6427         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6428                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6429         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6430                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6431         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6432                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6433         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6434                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6435         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6436                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6437         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6438                 rss_hf |= ETH_RSS_FRAG_IPV6;
6439         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6440                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6441         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6442                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6443         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6444                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6445         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6446                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6447         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6448                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6449         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6450                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6451         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6452                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6453         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6454                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6455
6456         return rss_hf;
6457 }
6458
6459 /* Disable RSS */
6460 static void
6461 i40e_pf_disable_rss(struct i40e_pf *pf)
6462 {
6463         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6464         uint64_t hena;
6465
6466         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6467         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6468         if (hw->mac.type == I40E_MAC_X722)
6469                 hena &= ~I40E_RSS_HENA_ALL_X722;
6470         else
6471                 hena &= ~I40E_RSS_HENA_ALL;
6472         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6473         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6474         I40E_WRITE_FLUSH(hw);
6475 }
6476
6477 static int
6478 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6479 {
6480         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6481         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6482         int ret = 0;
6483
6484         if (!key || key_len == 0) {
6485                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6486                 return 0;
6487         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6488                 sizeof(uint32_t)) {
6489                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6490                 return -EINVAL;
6491         }
6492
6493         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6494                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6495                         (struct i40e_aqc_get_set_rss_key_data *)key;
6496
6497                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6498                 if (ret)
6499                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6500                                      "via AQ");
6501         } else {
6502                 uint32_t *hash_key = (uint32_t *)key;
6503                 uint16_t i;
6504
6505                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6506                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6507                 I40E_WRITE_FLUSH(hw);
6508         }
6509
6510         return ret;
6511 }
6512
6513 static int
6514 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6515 {
6516         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6517         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6518         int ret;
6519
6520         if (!key || !key_len)
6521                 return -EINVAL;
6522
6523         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6524                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6525                         (struct i40e_aqc_get_set_rss_key_data *)key);
6526                 if (ret) {
6527                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6528                         return ret;
6529                 }
6530         } else {
6531                 uint32_t *key_dw = (uint32_t *)key;
6532                 uint16_t i;
6533
6534                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6535                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6536         }
6537         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6538
6539         return 0;
6540 }
6541
6542 static int
6543 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6544 {
6545         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6546         uint64_t rss_hf;
6547         uint64_t hena;
6548         int ret;
6549
6550         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6551                                rss_conf->rss_key_len);
6552         if (ret)
6553                 return ret;
6554
6555         rss_hf = rss_conf->rss_hf;
6556         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6557         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6558         if (hw->mac.type == I40E_MAC_X722)
6559                 hena &= ~I40E_RSS_HENA_ALL_X722;
6560         else
6561                 hena &= ~I40E_RSS_HENA_ALL;
6562         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6563         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6564         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6565         I40E_WRITE_FLUSH(hw);
6566
6567         return 0;
6568 }
6569
6570 static int
6571 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6572                          struct rte_eth_rss_conf *rss_conf)
6573 {
6574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6576         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6577         uint64_t hena;
6578
6579         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6580         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6581         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6582                  ? I40E_RSS_HENA_ALL_X722
6583                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6584                 if (rss_hf != 0) /* Enable RSS */
6585                         return -EINVAL;
6586                 return 0; /* Nothing to do */
6587         }
6588         /* RSS enabled */
6589         if (rss_hf == 0) /* Disable RSS */
6590                 return -EINVAL;
6591
6592         return i40e_hw_rss_hash_set(pf, rss_conf);
6593 }
6594
6595 static int
6596 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6597                            struct rte_eth_rss_conf *rss_conf)
6598 {
6599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6601         uint64_t hena;
6602
6603         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6604                          &rss_conf->rss_key_len);
6605
6606         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6607         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6608         rss_conf->rss_hf = i40e_parse_hena(hena);
6609
6610         return 0;
6611 }
6612
6613 static int
6614 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6615 {
6616         switch (filter_type) {
6617         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6618                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6619                 break;
6620         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6621                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6622                 break;
6623         case RTE_TUNNEL_FILTER_IMAC_TENID:
6624                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6625                 break;
6626         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6627                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6628                 break;
6629         case ETH_TUNNEL_FILTER_IMAC:
6630                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6631                 break;
6632         case ETH_TUNNEL_FILTER_OIP:
6633                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6634                 break;
6635         case ETH_TUNNEL_FILTER_IIP:
6636                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6637                 break;
6638         default:
6639                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6640                 return -EINVAL;
6641         }
6642
6643         return 0;
6644 }
6645
6646 /* Convert tunnel filter structure */
6647 static int
6648 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6649                            *cld_filter,
6650                            struct i40e_tunnel_filter *tunnel_filter)
6651 {
6652         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6653                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6654         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6655                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6656         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6657         tunnel_filter->input.flags = cld_filter->flags;
6658         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6659         tunnel_filter->queue = cld_filter->queue_number;
6660
6661         return 0;
6662 }
6663
6664 /* Check if there exists the tunnel filter */
6665 struct i40e_tunnel_filter *
6666 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6667                              const struct i40e_tunnel_filter_input *input)
6668 {
6669         int ret;
6670
6671         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6672         if (ret < 0)
6673                 return NULL;
6674
6675         return tunnel_rule->hash_map[ret];
6676 }
6677
6678 /* Add a tunnel filter into the SW list */
6679 static int
6680 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6681                              struct i40e_tunnel_filter *tunnel_filter)
6682 {
6683         struct i40e_tunnel_rule *rule = &pf->tunnel;
6684         int ret;
6685
6686         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6687         if (ret < 0) {
6688                 PMD_DRV_LOG(ERR,
6689                             "Failed to insert tunnel filter to hash table %d!",
6690                             ret);
6691                 return ret;
6692         }
6693         rule->hash_map[ret] = tunnel_filter;
6694
6695         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6696
6697         return 0;
6698 }
6699
6700 /* Delete a tunnel filter from the SW list */
6701 int
6702 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6703                           struct i40e_tunnel_filter_input *input)
6704 {
6705         struct i40e_tunnel_rule *rule = &pf->tunnel;
6706         struct i40e_tunnel_filter *tunnel_filter;
6707         int ret;
6708
6709         ret = rte_hash_del_key(rule->hash_table, input);
6710         if (ret < 0) {
6711                 PMD_DRV_LOG(ERR,
6712                             "Failed to delete tunnel filter to hash table %d!",
6713                             ret);
6714                 return ret;
6715         }
6716         tunnel_filter = rule->hash_map[ret];
6717         rule->hash_map[ret] = NULL;
6718
6719         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6720         rte_free(tunnel_filter);
6721
6722         return 0;
6723 }
6724
6725 static int
6726 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6727                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6728                         uint8_t add)
6729 {
6730         uint16_t ip_type;
6731         uint32_t ipv4_addr;
6732         uint8_t i, tun_type = 0;
6733         /* internal varialbe to convert ipv6 byte order */
6734         uint32_t convert_ipv6[4];
6735         int val, ret = 0;
6736         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6737         struct i40e_vsi *vsi = pf->main_vsi;
6738         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6739         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6740         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6741         struct i40e_tunnel_filter *tunnel, *node;
6742         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6743
6744         cld_filter = rte_zmalloc("tunnel_filter",
6745                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6746                 0);
6747
6748         if (NULL == cld_filter) {
6749                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6750                 return -EINVAL;
6751         }
6752         pfilter = cld_filter;
6753
6754         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6755         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6756
6757         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6758         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6759                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6760                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6761                 rte_memcpy(&pfilter->ipaddr.v4.data,
6762                                 &rte_cpu_to_le_32(ipv4_addr),
6763                                 sizeof(pfilter->ipaddr.v4.data));
6764         } else {
6765                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6766                 for (i = 0; i < 4; i++) {
6767                         convert_ipv6[i] =
6768                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6769                 }
6770                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6771                                 sizeof(pfilter->ipaddr.v6.data));
6772         }
6773
6774         /* check tunneled type */
6775         switch (tunnel_filter->tunnel_type) {
6776         case RTE_TUNNEL_TYPE_VXLAN:
6777                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6778                 break;
6779         case RTE_TUNNEL_TYPE_NVGRE:
6780                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6781                 break;
6782         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6783                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6784                 break;
6785         default:
6786                 /* Other tunnel types is not supported. */
6787                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6788                 rte_free(cld_filter);
6789                 return -EINVAL;
6790         }
6791
6792         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6793                                                 &pfilter->flags);
6794         if (val < 0) {
6795                 rte_free(cld_filter);
6796                 return -EINVAL;
6797         }
6798
6799         pfilter->flags |= rte_cpu_to_le_16(
6800                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6801                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6802         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6803         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6804
6805         /* Check if there is the filter in SW list */
6806         memset(&check_filter, 0, sizeof(check_filter));
6807         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6808         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6809         if (add && node) {
6810                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6811                 return -EINVAL;
6812         }
6813
6814         if (!add && !node) {
6815                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6816                 return -EINVAL;
6817         }
6818
6819         if (add) {
6820                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6821                 if (ret < 0) {
6822                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6823                         return ret;
6824                 }
6825                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6826                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6827                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6828         } else {
6829                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6830                                                    cld_filter, 1);
6831                 if (ret < 0) {
6832                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6833                         return ret;
6834                 }
6835                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6836         }
6837
6838         rte_free(cld_filter);
6839         return ret;
6840 }
6841
6842 static int
6843 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6844 {
6845         uint8_t i;
6846
6847         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6848                 if (pf->vxlan_ports[i] == port)
6849                         return i;
6850         }
6851
6852         return -1;
6853 }
6854
6855 static int
6856 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6857 {
6858         int  idx, ret;
6859         uint8_t filter_idx;
6860         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6861
6862         idx = i40e_get_vxlan_port_idx(pf, port);
6863
6864         /* Check if port already exists */
6865         if (idx >= 0) {
6866                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6867                 return -EINVAL;
6868         }
6869
6870         /* Now check if there is space to add the new port */
6871         idx = i40e_get_vxlan_port_idx(pf, 0);
6872         if (idx < 0) {
6873                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6874                         "not adding port %d", port);
6875                 return -ENOSPC;
6876         }
6877
6878         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6879                                         &filter_idx, NULL);
6880         if (ret < 0) {
6881                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6882                 return -1;
6883         }
6884
6885         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6886                          port,  filter_idx);
6887
6888         /* New port: add it and mark its index in the bitmap */
6889         pf->vxlan_ports[idx] = port;
6890         pf->vxlan_bitmap |= (1 << idx);
6891
6892         if (!(pf->flags & I40E_FLAG_VXLAN))
6893                 pf->flags |= I40E_FLAG_VXLAN;
6894
6895         return 0;
6896 }
6897
6898 static int
6899 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6900 {
6901         int idx;
6902         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6903
6904         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6905                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6906                 return -EINVAL;
6907         }
6908
6909         idx = i40e_get_vxlan_port_idx(pf, port);
6910
6911         if (idx < 0) {
6912                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6913                 return -EINVAL;
6914         }
6915
6916         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6917                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6918                 return -1;
6919         }
6920
6921         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6922                         port, idx);
6923
6924         pf->vxlan_ports[idx] = 0;
6925         pf->vxlan_bitmap &= ~(1 << idx);
6926
6927         if (!pf->vxlan_bitmap)
6928                 pf->flags &= ~I40E_FLAG_VXLAN;
6929
6930         return 0;
6931 }
6932
6933 /* Add UDP tunneling port */
6934 static int
6935 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6936                              struct rte_eth_udp_tunnel *udp_tunnel)
6937 {
6938         int ret = 0;
6939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6940
6941         if (udp_tunnel == NULL)
6942                 return -EINVAL;
6943
6944         switch (udp_tunnel->prot_type) {
6945         case RTE_TUNNEL_TYPE_VXLAN:
6946                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6947                 break;
6948
6949         case RTE_TUNNEL_TYPE_GENEVE:
6950         case RTE_TUNNEL_TYPE_TEREDO:
6951                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6952                 ret = -1;
6953                 break;
6954
6955         default:
6956                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6957                 ret = -1;
6958                 break;
6959         }
6960
6961         return ret;
6962 }
6963
6964 /* Remove UDP tunneling port */
6965 static int
6966 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6967                              struct rte_eth_udp_tunnel *udp_tunnel)
6968 {
6969         int ret = 0;
6970         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6971
6972         if (udp_tunnel == NULL)
6973                 return -EINVAL;
6974
6975         switch (udp_tunnel->prot_type) {
6976         case RTE_TUNNEL_TYPE_VXLAN:
6977                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6978                 break;
6979         case RTE_TUNNEL_TYPE_GENEVE:
6980         case RTE_TUNNEL_TYPE_TEREDO:
6981                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6982                 ret = -1;
6983                 break;
6984         default:
6985                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6986                 ret = -1;
6987                 break;
6988         }
6989
6990         return ret;
6991 }
6992
6993 /* Calculate the maximum number of contiguous PF queues that are configured */
6994 static int
6995 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6996 {
6997         struct rte_eth_dev_data *data = pf->dev_data;
6998         int i, num;
6999         struct i40e_rx_queue *rxq;
7000
7001         num = 0;
7002         for (i = 0; i < pf->lan_nb_qps; i++) {
7003                 rxq = data->rx_queues[i];
7004                 if (rxq && rxq->q_set)
7005                         num++;
7006                 else
7007                         break;
7008         }
7009
7010         return num;
7011 }
7012
7013 /* Configure RSS */
7014 static int
7015 i40e_pf_config_rss(struct i40e_pf *pf)
7016 {
7017         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7018         struct rte_eth_rss_conf rss_conf;
7019         uint32_t i, lut = 0;
7020         uint16_t j, num;
7021
7022         /*
7023          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7024          * It's necessary to calulate the actual PF queues that are configured.
7025          */
7026         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7027                 num = i40e_pf_calc_configured_queues_num(pf);
7028         else
7029                 num = pf->dev_data->nb_rx_queues;
7030
7031         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7032         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7033                         num);
7034
7035         if (num == 0) {
7036                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7037                 return -ENOTSUP;
7038         }
7039
7040         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7041                 if (j == num)
7042                         j = 0;
7043                 lut = (lut << 8) | (j & ((0x1 <<
7044                         hw->func_caps.rss_table_entry_width) - 1));
7045                 if ((i & 3) == 3)
7046                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7047         }
7048
7049         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7050         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7051                 i40e_pf_disable_rss(pf);
7052                 return 0;
7053         }
7054         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7055                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7056                 /* Random default keys */
7057                 static uint32_t rss_key_default[] = {0x6b793944,
7058                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7059                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7060                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7061
7062                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7063                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7064                                                         sizeof(uint32_t);
7065         }
7066
7067         return i40e_hw_rss_hash_set(pf, &rss_conf);
7068 }
7069
7070 static int
7071 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7072                                struct rte_eth_tunnel_filter_conf *filter)
7073 {
7074         if (pf == NULL || filter == NULL) {
7075                 PMD_DRV_LOG(ERR, "Invalid parameter");
7076                 return -EINVAL;
7077         }
7078
7079         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7080                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7081                 return -EINVAL;
7082         }
7083
7084         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7085                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7086                 return -EINVAL;
7087         }
7088
7089         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7090                 (is_zero_ether_addr(&filter->outer_mac))) {
7091                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7092                 return -EINVAL;
7093         }
7094
7095         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7096                 (is_zero_ether_addr(&filter->inner_mac))) {
7097                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7098                 return -EINVAL;
7099         }
7100
7101         return 0;
7102 }
7103
7104 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7105 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7106 static int
7107 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7108 {
7109         uint32_t val, reg;
7110         int ret = -EINVAL;
7111
7112         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7113         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7114
7115         if (len == 3) {
7116                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7117         } else if (len == 4) {
7118                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7119         } else {
7120                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7121                 return ret;
7122         }
7123
7124         if (reg != val) {
7125                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7126                                                    reg, NULL);
7127                 if (ret != 0)
7128                         return ret;
7129         } else {
7130                 ret = 0;
7131         }
7132         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7133                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7134
7135         return ret;
7136 }
7137
7138 static int
7139 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7140 {
7141         int ret = -EINVAL;
7142
7143         if (!hw || !cfg)
7144                 return -EINVAL;
7145
7146         switch (cfg->cfg_type) {
7147         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7148                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7149                 break;
7150         default:
7151                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7152                 break;
7153         }
7154
7155         return ret;
7156 }
7157
7158 static int
7159 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7160                                enum rte_filter_op filter_op,
7161                                void *arg)
7162 {
7163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7164         int ret = I40E_ERR_PARAM;
7165
7166         switch (filter_op) {
7167         case RTE_ETH_FILTER_SET:
7168                 ret = i40e_dev_global_config_set(hw,
7169                         (struct rte_eth_global_cfg *)arg);
7170                 break;
7171         default:
7172                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7173                 break;
7174         }
7175
7176         return ret;
7177 }
7178
7179 static int
7180 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7181                           enum rte_filter_op filter_op,
7182                           void *arg)
7183 {
7184         struct rte_eth_tunnel_filter_conf *filter;
7185         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7186         int ret = I40E_SUCCESS;
7187
7188         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7189
7190         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7191                 return I40E_ERR_PARAM;
7192
7193         switch (filter_op) {
7194         case RTE_ETH_FILTER_NOP:
7195                 if (!(pf->flags & I40E_FLAG_VXLAN))
7196                         ret = I40E_NOT_SUPPORTED;
7197                 break;
7198         case RTE_ETH_FILTER_ADD:
7199                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7200                 break;
7201         case RTE_ETH_FILTER_DELETE:
7202                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7203                 break;
7204         default:
7205                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7206                 ret = I40E_ERR_PARAM;
7207                 break;
7208         }
7209
7210         return ret;
7211 }
7212
7213 static int
7214 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7215 {
7216         int ret = 0;
7217         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7218
7219         /* RSS setup */
7220         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7221                 ret = i40e_pf_config_rss(pf);
7222         else
7223                 i40e_pf_disable_rss(pf);
7224
7225         return ret;
7226 }
7227
7228 /* Get the symmetric hash enable configurations per port */
7229 static void
7230 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7231 {
7232         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7233
7234         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7235 }
7236
7237 /* Set the symmetric hash enable configurations per port */
7238 static void
7239 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7240 {
7241         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7242
7243         if (enable > 0) {
7244                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7245                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7246                                                         "been enabled");
7247                         return;
7248                 }
7249                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7250         } else {
7251                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7252                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7253                                                         "been disabled");
7254                         return;
7255                 }
7256                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7257         }
7258         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7259         I40E_WRITE_FLUSH(hw);
7260 }
7261
7262 /*
7263  * Get global configurations of hash function type and symmetric hash enable
7264  * per flow type (pctype). Note that global configuration means it affects all
7265  * the ports on the same NIC.
7266  */
7267 static int
7268 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7269                                    struct rte_eth_hash_global_conf *g_cfg)
7270 {
7271         uint32_t reg, mask = I40E_FLOW_TYPES;
7272         uint16_t i;
7273         enum i40e_filter_pctype pctype;
7274
7275         memset(g_cfg, 0, sizeof(*g_cfg));
7276         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7277         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7278                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7279         else
7280                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7281         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7282                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7283
7284         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7285                 if (!(mask & (1UL << i)))
7286                         continue;
7287                 mask &= ~(1UL << i);
7288                 /* Bit set indicats the coresponding flow type is supported */
7289                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7290                 /* if flowtype is invalid, continue */
7291                 if (!I40E_VALID_FLOW(i))
7292                         continue;
7293                 pctype = i40e_flowtype_to_pctype(i);
7294                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7295                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7296                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7297         }
7298
7299         return 0;
7300 }
7301
7302 static int
7303 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7304 {
7305         uint32_t i;
7306         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7307
7308         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7309                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7310                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7311                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7312                                                 g_cfg->hash_func);
7313                 return -EINVAL;
7314         }
7315
7316         /*
7317          * As i40e supports less than 32 flow types, only first 32 bits need to
7318          * be checked.
7319          */
7320         mask0 = g_cfg->valid_bit_mask[0];
7321         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7322                 if (i == 0) {
7323                         /* Check if any unsupported flow type configured */
7324                         if ((mask0 | i40e_mask) ^ i40e_mask)
7325                                 goto mask_err;
7326                 } else {
7327                         if (g_cfg->valid_bit_mask[i])
7328                                 goto mask_err;
7329                 }
7330         }
7331
7332         return 0;
7333
7334 mask_err:
7335         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7336
7337         return -EINVAL;
7338 }
7339
7340 /*
7341  * Set global configurations of hash function type and symmetric hash enable
7342  * per flow type (pctype). Note any modifying global configuration will affect
7343  * all the ports on the same NIC.
7344  */
7345 static int
7346 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7347                                    struct rte_eth_hash_global_conf *g_cfg)
7348 {
7349         int ret;
7350         uint16_t i;
7351         uint32_t reg;
7352         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7353         enum i40e_filter_pctype pctype;
7354
7355         /* Check the input parameters */
7356         ret = i40e_hash_global_config_check(g_cfg);
7357         if (ret < 0)
7358                 return ret;
7359
7360         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7361                 if (!(mask0 & (1UL << i)))
7362                         continue;
7363                 mask0 &= ~(1UL << i);
7364                 /* if flowtype is invalid, continue */
7365                 if (!I40E_VALID_FLOW(i))
7366                         continue;
7367                 pctype = i40e_flowtype_to_pctype(i);
7368                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7369                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7370                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7371         }
7372
7373         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7374         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7375                 /* Toeplitz */
7376                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7377                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7378                                                                 "Toeplitz");
7379                         goto out;
7380                 }
7381                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7382         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7383                 /* Simple XOR */
7384                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7385                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7386                                                         "Simple XOR");
7387                         goto out;
7388                 }
7389                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7390         } else
7391                 /* Use the default, and keep it as it is */
7392                 goto out;
7393
7394         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7395
7396 out:
7397         I40E_WRITE_FLUSH(hw);
7398
7399         return 0;
7400 }
7401
7402 /**
7403  * Valid input sets for hash and flow director filters per PCTYPE
7404  */
7405 static uint64_t
7406 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7407                 enum rte_filter_type filter)
7408 {
7409         uint64_t valid;
7410
7411         static const uint64_t valid_hash_inset_table[] = {
7412                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7413                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7414                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7415                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7416                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7417                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7418                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7419                         I40E_INSET_FLEX_PAYLOAD,
7420                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7421                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7422                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7423                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7424                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7425                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7426                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7427                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7428                         I40E_INSET_FLEX_PAYLOAD,
7429                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7430                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7431                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7432                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7433                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7434                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7435                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7436                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7437                         I40E_INSET_FLEX_PAYLOAD,
7438                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7439                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7440                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7441                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7442                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7443                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7444                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7445                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7446                         I40E_INSET_FLEX_PAYLOAD,
7447                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7448                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7449                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7450                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7451                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7452                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7453                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7454                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7455                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7456                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7457                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7458                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7459                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7460                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7461                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7462                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7463                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7464                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7465                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7466                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7467                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7468                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7469                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7470                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7471                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7472                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7473                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7474                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7475                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7476                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7477                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7478                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7479                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7480                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7481                         I40E_INSET_FLEX_PAYLOAD,
7482                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7483                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7484                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7485                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7486                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7487                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7488                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7489                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7490                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7491                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7492                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7493                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7494                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7495                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7496                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7497                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7498                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7499                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7500                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7501                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7502                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7503                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7504                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7505                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7506                         I40E_INSET_FLEX_PAYLOAD,
7507                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7508                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7509                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7510                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7511                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7512                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7513                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7514                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7515                         I40E_INSET_FLEX_PAYLOAD,
7516                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7517                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7518                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7519                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7520                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7521                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7522                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7523                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7524                         I40E_INSET_FLEX_PAYLOAD,
7525                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7526                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7527                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7528                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7529                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7530                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7531                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7532                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7533                         I40E_INSET_FLEX_PAYLOAD,
7534                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7535                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7536                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7537                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7538                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7539                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7540                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7541                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7542                         I40E_INSET_FLEX_PAYLOAD,
7543                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7544                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7545                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7546                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7547                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7548                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7549                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7550                         I40E_INSET_FLEX_PAYLOAD,
7551                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7552                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7553                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7554                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7555                         I40E_INSET_FLEX_PAYLOAD,
7556         };
7557
7558         /**
7559          * Flow director supports only fields defined in
7560          * union rte_eth_fdir_flow.
7561          */
7562         static const uint64_t valid_fdir_inset_table[] = {
7563                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7564                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7565                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7566                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7567                 I40E_INSET_IPV4_TTL,
7568                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7569                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7570                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7571                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7572                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7573                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7574                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7575                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7576                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7577                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7578                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7579                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7580                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7581                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7582                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7583                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7584                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7585                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7586                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7587                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7588                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7589                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7590                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7591                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7592                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7593                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7594                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7595                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7596                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7597                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7598                 I40E_INSET_SCTP_VT,
7599                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7600                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7601                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7602                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7603                 I40E_INSET_IPV4_TTL,
7604                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7605                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7606                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7607                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7608                 I40E_INSET_IPV6_HOP_LIMIT,
7609                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7610                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7611                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7612                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7613                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7614                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7615                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7616                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7617                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7618                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7619                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7620                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7621                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7622                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7623                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7624                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7625                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7626                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7627                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7628                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7629                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7630                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7631                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7632                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7633                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7634                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7635                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7636                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7637                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7638                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7639                 I40E_INSET_SCTP_VT,
7640                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7641                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7642                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7643                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7644                 I40E_INSET_IPV6_HOP_LIMIT,
7645                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7646                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7647                 I40E_INSET_LAST_ETHER_TYPE,
7648         };
7649
7650         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7651                 return 0;
7652         if (filter == RTE_ETH_FILTER_HASH)
7653                 valid = valid_hash_inset_table[pctype];
7654         else
7655                 valid = valid_fdir_inset_table[pctype];
7656
7657         return valid;
7658 }
7659
7660 /**
7661  * Validate if the input set is allowed for a specific PCTYPE
7662  */
7663 static int
7664 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7665                 enum rte_filter_type filter, uint64_t inset)
7666 {
7667         uint64_t valid;
7668
7669         valid = i40e_get_valid_input_set(pctype, filter);
7670         if (inset & (~valid))
7671                 return -EINVAL;
7672
7673         return 0;
7674 }
7675
7676 /* default input set fields combination per pctype */
7677 uint64_t
7678 i40e_get_default_input_set(uint16_t pctype)
7679 {
7680         static const uint64_t default_inset_table[] = {
7681                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7682                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7683                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7684                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7685                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7686                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7687                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7688                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7689                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7690                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7691                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7692                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7693                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7694                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7695                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7696                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7697                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7698                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7699                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7700                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7701                         I40E_INSET_SCTP_VT,
7702                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7703                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7704                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7705                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7706                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7707                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7708                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7709                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7710                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7711                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7712                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7713                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7714                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7715                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7716                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7717                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7718                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7719                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7720                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7721                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7722                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7723                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7724                         I40E_INSET_SCTP_VT,
7725                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7726                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7727                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7728                         I40E_INSET_LAST_ETHER_TYPE,
7729         };
7730
7731         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7732                 return 0;
7733
7734         return default_inset_table[pctype];
7735 }
7736
7737 /**
7738  * Parse the input set from index to logical bit masks
7739  */
7740 static int
7741 i40e_parse_input_set(uint64_t *inset,
7742                      enum i40e_filter_pctype pctype,
7743                      enum rte_eth_input_set_field *field,
7744                      uint16_t size)
7745 {
7746         uint16_t i, j;
7747         int ret = -EINVAL;
7748
7749         static const struct {
7750                 enum rte_eth_input_set_field field;
7751                 uint64_t inset;
7752         } inset_convert_table[] = {
7753                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7754                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7755                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7756                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7757                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7758                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7759                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7760                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7761                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7762                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7763                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7764                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7765                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7766                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7767                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7768                         I40E_INSET_IPV6_NEXT_HDR},
7769                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7770                         I40E_INSET_IPV6_HOP_LIMIT},
7771                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7772                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7773                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7774                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7775                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7776                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7777                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7778                         I40E_INSET_SCTP_VT},
7779                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7780                         I40E_INSET_TUNNEL_DMAC},
7781                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7782                         I40E_INSET_VLAN_TUNNEL},
7783                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7784                         I40E_INSET_TUNNEL_ID},
7785                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7786                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7787                         I40E_INSET_FLEX_PAYLOAD_W1},
7788                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7789                         I40E_INSET_FLEX_PAYLOAD_W2},
7790                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7791                         I40E_INSET_FLEX_PAYLOAD_W3},
7792                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7793                         I40E_INSET_FLEX_PAYLOAD_W4},
7794                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7795                         I40E_INSET_FLEX_PAYLOAD_W5},
7796                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7797                         I40E_INSET_FLEX_PAYLOAD_W6},
7798                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7799                         I40E_INSET_FLEX_PAYLOAD_W7},
7800                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7801                         I40E_INSET_FLEX_PAYLOAD_W8},
7802         };
7803
7804         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7805                 return ret;
7806
7807         /* Only one item allowed for default or all */
7808         if (size == 1) {
7809                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7810                         *inset = i40e_get_default_input_set(pctype);
7811                         return 0;
7812                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7813                         *inset = I40E_INSET_NONE;
7814                         return 0;
7815                 }
7816         }
7817
7818         for (i = 0, *inset = 0; i < size; i++) {
7819                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7820                         if (field[i] == inset_convert_table[j].field) {
7821                                 *inset |= inset_convert_table[j].inset;
7822                                 break;
7823                         }
7824                 }
7825
7826                 /* It contains unsupported input set, return immediately */
7827                 if (j == RTE_DIM(inset_convert_table))
7828                         return ret;
7829         }
7830
7831         return 0;
7832 }
7833
7834 /**
7835  * Translate the input set from bit masks to register aware bit masks
7836  * and vice versa
7837  */
7838 static uint64_t
7839 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7840 {
7841         uint64_t val = 0;
7842         uint16_t i;
7843
7844         struct inset_map {
7845                 uint64_t inset;
7846                 uint64_t inset_reg;
7847         };
7848
7849         static const struct inset_map inset_map_common[] = {
7850                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7851                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7852                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7853                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7854                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7855                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7856                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7857                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7858                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7859                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7860                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7861                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7862                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7863                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7864                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7865                 {I40E_INSET_TUNNEL_DMAC,
7866                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7867                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7868                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7869                 {I40E_INSET_TUNNEL_SRC_PORT,
7870                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7871                 {I40E_INSET_TUNNEL_DST_PORT,
7872                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7873                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7874                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7875                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7876                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7877                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7878                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7879                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7880                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7881                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7882         };
7883
7884     /* some different registers map in x722*/
7885         static const struct inset_map inset_map_diff_x722[] = {
7886                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7887                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7888                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7889                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7890         };
7891
7892         static const struct inset_map inset_map_diff_not_x722[] = {
7893                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7894                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7895                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7896                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7897         };
7898
7899         if (input == 0)
7900                 return val;
7901
7902         /* Translate input set to register aware inset */
7903         if (type == I40E_MAC_X722) {
7904                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7905                         if (input & inset_map_diff_x722[i].inset)
7906                                 val |= inset_map_diff_x722[i].inset_reg;
7907                 }
7908         } else {
7909                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7910                         if (input & inset_map_diff_not_x722[i].inset)
7911                                 val |= inset_map_diff_not_x722[i].inset_reg;
7912                 }
7913         }
7914
7915         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7916                 if (input & inset_map_common[i].inset)
7917                         val |= inset_map_common[i].inset_reg;
7918         }
7919
7920         return val;
7921 }
7922
7923 static int
7924 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7925 {
7926         uint8_t i, idx = 0;
7927         uint64_t inset_need_mask = inset;
7928
7929         static const struct {
7930                 uint64_t inset;
7931                 uint32_t mask;
7932         } inset_mask_map[] = {
7933                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7934                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7935                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7936                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7937                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7938                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7939                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7940                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7941         };
7942
7943         if (!inset || !mask || !nb_elem)
7944                 return 0;
7945
7946         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7947                 /* Clear the inset bit, if no MASK is required,
7948                  * for example proto + ttl
7949                  */
7950                 if ((inset & inset_mask_map[i].inset) ==
7951                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7952                         inset_need_mask &= ~inset_mask_map[i].inset;
7953                 if (!inset_need_mask)
7954                         return 0;
7955         }
7956         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7957                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7958                     inset_mask_map[i].inset) {
7959                         if (idx >= nb_elem) {
7960                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7961                                 return -EINVAL;
7962                         }
7963                         mask[idx] = inset_mask_map[i].mask;
7964                         idx++;
7965                 }
7966         }
7967
7968         return idx;
7969 }
7970
7971 static void
7972 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7973 {
7974         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7975
7976         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7977         if (reg != val)
7978                 i40e_write_rx_ctl(hw, addr, val);
7979         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7980                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7981 }
7982
7983 static void
7984 i40e_filter_input_set_init(struct i40e_pf *pf)
7985 {
7986         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7987         enum i40e_filter_pctype pctype;
7988         uint64_t input_set, inset_reg;
7989         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7990         int num, i;
7991
7992         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7993              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7994                 if (hw->mac.type == I40E_MAC_X722) {
7995                         if (!I40E_VALID_PCTYPE_X722(pctype))
7996                                 continue;
7997                 } else {
7998                         if (!I40E_VALID_PCTYPE(pctype))
7999                                 continue;
8000                 }
8001
8002                 input_set = i40e_get_default_input_set(pctype);
8003
8004                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8005                                                    I40E_INSET_MASK_NUM_REG);
8006                 if (num < 0)
8007                         return;
8008                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8009                                         input_set);
8010
8011                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8012                                       (uint32_t)(inset_reg & UINT32_MAX));
8013                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8014                                      (uint32_t)((inset_reg >>
8015                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8016                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8017                                       (uint32_t)(inset_reg & UINT32_MAX));
8018                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8019                                      (uint32_t)((inset_reg >>
8020                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8021
8022                 for (i = 0; i < num; i++) {
8023                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8024                                              mask_reg[i]);
8025                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8026                                              mask_reg[i]);
8027                 }
8028                 /*clear unused mask registers of the pctype */
8029                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8030                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8031                                              0);
8032                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8033                                              0);
8034                 }
8035                 I40E_WRITE_FLUSH(hw);
8036
8037                 /* store the default input set */
8038                 pf->hash_input_set[pctype] = input_set;
8039                 pf->fdir.input_set[pctype] = input_set;
8040         }
8041 }
8042
8043 int
8044 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8045                          struct rte_eth_input_set_conf *conf)
8046 {
8047         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8048         enum i40e_filter_pctype pctype;
8049         uint64_t input_set, inset_reg = 0;
8050         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8051         int ret, i, num;
8052
8053         if (!conf) {
8054                 PMD_DRV_LOG(ERR, "Invalid pointer");
8055                 return -EFAULT;
8056         }
8057         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8058             conf->op != RTE_ETH_INPUT_SET_ADD) {
8059                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8060                 return -EINVAL;
8061         }
8062
8063         if (!I40E_VALID_FLOW(conf->flow_type)) {
8064                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8065                 return -EINVAL;
8066         }
8067
8068         if (hw->mac.type == I40E_MAC_X722) {
8069                 /* get translated pctype value in fd pctype register */
8070                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8071                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8072                         conf->flow_type)));
8073         } else
8074                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8075
8076         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8077                                    conf->inset_size);
8078         if (ret) {
8079                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8080                 return -EINVAL;
8081         }
8082         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8083                                     input_set) != 0) {
8084                 PMD_DRV_LOG(ERR, "Invalid input set");
8085                 return -EINVAL;
8086         }
8087         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8088                 /* get inset value in register */
8089                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8090                 inset_reg <<= I40E_32_BIT_WIDTH;
8091                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8092                 input_set |= pf->hash_input_set[pctype];
8093         }
8094         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8095                                            I40E_INSET_MASK_NUM_REG);
8096         if (num < 0)
8097                 return -EINVAL;
8098
8099         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8100
8101         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8102                               (uint32_t)(inset_reg & UINT32_MAX));
8103         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8104                              (uint32_t)((inset_reg >>
8105                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8106
8107         for (i = 0; i < num; i++)
8108                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8109                                      mask_reg[i]);
8110         /*clear unused mask registers of the pctype */
8111         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8112                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8113                                      0);
8114         I40E_WRITE_FLUSH(hw);
8115
8116         pf->hash_input_set[pctype] = input_set;
8117         return 0;
8118 }
8119
8120 int
8121 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8122                          struct rte_eth_input_set_conf *conf)
8123 {
8124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8125         enum i40e_filter_pctype pctype;
8126         uint64_t input_set, inset_reg = 0;
8127         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8128         int ret, i, num;
8129
8130         if (!hw || !conf) {
8131                 PMD_DRV_LOG(ERR, "Invalid pointer");
8132                 return -EFAULT;
8133         }
8134         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8135             conf->op != RTE_ETH_INPUT_SET_ADD) {
8136                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8137                 return -EINVAL;
8138         }
8139
8140         if (!I40E_VALID_FLOW(conf->flow_type)) {
8141                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8142                 return -EINVAL;
8143         }
8144
8145         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8146
8147         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8148                                    conf->inset_size);
8149         if (ret) {
8150                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8151                 return -EINVAL;
8152         }
8153         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8154                                     input_set) != 0) {
8155                 PMD_DRV_LOG(ERR, "Invalid input set");
8156                 return -EINVAL;
8157         }
8158
8159         /* get inset value in register */
8160         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8161         inset_reg <<= I40E_32_BIT_WIDTH;
8162         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8163
8164         /* Can not change the inset reg for flex payload for fdir,
8165          * it is done by writing I40E_PRTQF_FD_FLXINSET
8166          * in i40e_set_flex_mask_on_pctype.
8167          */
8168         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8169                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8170         else
8171                 input_set |= pf->fdir.input_set[pctype];
8172         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8173                                            I40E_INSET_MASK_NUM_REG);
8174         if (num < 0)
8175                 return -EINVAL;
8176
8177         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8178
8179         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8180                               (uint32_t)(inset_reg & UINT32_MAX));
8181         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8182                              (uint32_t)((inset_reg >>
8183                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8184
8185         for (i = 0; i < num; i++)
8186                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8187                                      mask_reg[i]);
8188         /*clear unused mask registers of the pctype */
8189         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8190                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8191                                      0);
8192         I40E_WRITE_FLUSH(hw);
8193
8194         pf->fdir.input_set[pctype] = input_set;
8195         return 0;
8196 }
8197
8198 static int
8199 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8200 {
8201         int ret = 0;
8202
8203         if (!hw || !info) {
8204                 PMD_DRV_LOG(ERR, "Invalid pointer");
8205                 return -EFAULT;
8206         }
8207
8208         switch (info->info_type) {
8209         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8210                 i40e_get_symmetric_hash_enable_per_port(hw,
8211                                         &(info->info.enable));
8212                 break;
8213         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8214                 ret = i40e_get_hash_filter_global_config(hw,
8215                                 &(info->info.global_conf));
8216                 break;
8217         default:
8218                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8219                                                         info->info_type);
8220                 ret = -EINVAL;
8221                 break;
8222         }
8223
8224         return ret;
8225 }
8226
8227 static int
8228 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8229 {
8230         int ret = 0;
8231
8232         if (!hw || !info) {
8233                 PMD_DRV_LOG(ERR, "Invalid pointer");
8234                 return -EFAULT;
8235         }
8236
8237         switch (info->info_type) {
8238         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8239                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8240                 break;
8241         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8242                 ret = i40e_set_hash_filter_global_config(hw,
8243                                 &(info->info.global_conf));
8244                 break;
8245         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8246                 ret = i40e_hash_filter_inset_select(hw,
8247                                                &(info->info.input_set_conf));
8248                 break;
8249
8250         default:
8251                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8252                                                         info->info_type);
8253                 ret = -EINVAL;
8254                 break;
8255         }
8256
8257         return ret;
8258 }
8259
8260 /* Operations for hash function */
8261 static int
8262 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8263                       enum rte_filter_op filter_op,
8264                       void *arg)
8265 {
8266         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8267         int ret = 0;
8268
8269         switch (filter_op) {
8270         case RTE_ETH_FILTER_NOP:
8271                 break;
8272         case RTE_ETH_FILTER_GET:
8273                 ret = i40e_hash_filter_get(hw,
8274                         (struct rte_eth_hash_filter_info *)arg);
8275                 break;
8276         case RTE_ETH_FILTER_SET:
8277                 ret = i40e_hash_filter_set(hw,
8278                         (struct rte_eth_hash_filter_info *)arg);
8279                 break;
8280         default:
8281                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8282                                                                 filter_op);
8283                 ret = -ENOTSUP;
8284                 break;
8285         }
8286
8287         return ret;
8288 }
8289
8290 /* Convert ethertype filter structure */
8291 static int
8292 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8293                               struct i40e_ethertype_filter *filter)
8294 {
8295         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8296         filter->input.ether_type = input->ether_type;
8297         filter->flags = input->flags;
8298         filter->queue = input->queue;
8299
8300         return 0;
8301 }
8302
8303 /* Check if there exists the ehtertype filter */
8304 struct i40e_ethertype_filter *
8305 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8306                                 const struct i40e_ethertype_filter_input *input)
8307 {
8308         int ret;
8309
8310         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8311         if (ret < 0)
8312                 return NULL;
8313
8314         return ethertype_rule->hash_map[ret];
8315 }
8316
8317 /* Add ethertype filter in SW list */
8318 static int
8319 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8320                                 struct i40e_ethertype_filter *filter)
8321 {
8322         struct i40e_ethertype_rule *rule = &pf->ethertype;
8323         int ret;
8324
8325         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8326         if (ret < 0) {
8327                 PMD_DRV_LOG(ERR,
8328                             "Failed to insert ethertype filter"
8329                             " to hash table %d!",
8330                             ret);
8331                 return ret;
8332         }
8333         rule->hash_map[ret] = filter;
8334
8335         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8336
8337         return 0;
8338 }
8339
8340 /* Delete ethertype filter in SW list */
8341 int
8342 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8343                              struct i40e_ethertype_filter_input *input)
8344 {
8345         struct i40e_ethertype_rule *rule = &pf->ethertype;
8346         struct i40e_ethertype_filter *filter;
8347         int ret;
8348
8349         ret = rte_hash_del_key(rule->hash_table, input);
8350         if (ret < 0) {
8351                 PMD_DRV_LOG(ERR,
8352                             "Failed to delete ethertype filter"
8353                             " to hash table %d!",
8354                             ret);
8355                 return ret;
8356         }
8357         filter = rule->hash_map[ret];
8358         rule->hash_map[ret] = NULL;
8359
8360         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8361         rte_free(filter);
8362
8363         return 0;
8364 }
8365
8366 /*
8367  * Configure ethertype filter, which can director packet by filtering
8368  * with mac address and ether_type or only ether_type
8369  */
8370 static int
8371 i40e_ethertype_filter_set(struct i40e_pf *pf,
8372                         struct rte_eth_ethertype_filter *filter,
8373                         bool add)
8374 {
8375         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8376         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8377         struct i40e_ethertype_filter *ethertype_filter, *node;
8378         struct i40e_ethertype_filter check_filter;
8379         struct i40e_control_filter_stats stats;
8380         uint16_t flags = 0;
8381         int ret;
8382
8383         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8384                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8385                 return -EINVAL;
8386         }
8387         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8388                 filter->ether_type == ETHER_TYPE_IPv6) {
8389                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8390                         " control packet filter.", filter->ether_type);
8391                 return -EINVAL;
8392         }
8393         if (filter->ether_type == ETHER_TYPE_VLAN)
8394                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8395                         " not supported.");
8396
8397         /* Check if there is the filter in SW list */
8398         memset(&check_filter, 0, sizeof(check_filter));
8399         i40e_ethertype_filter_convert(filter, &check_filter);
8400         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8401                                                &check_filter.input);
8402         if (add && node) {
8403                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8404                 return -EINVAL;
8405         }
8406
8407         if (!add && !node) {
8408                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8409                 return -EINVAL;
8410         }
8411
8412         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8413                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8414         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8415                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8416         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8417
8418         memset(&stats, 0, sizeof(stats));
8419         ret = i40e_aq_add_rem_control_packet_filter(hw,
8420                         filter->mac_addr.addr_bytes,
8421                         filter->ether_type, flags,
8422                         pf->main_vsi->seid,
8423                         filter->queue, add, &stats, NULL);
8424
8425         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8426                          " mac_etype_used = %u, etype_used = %u,"
8427                          " mac_etype_free = %u, etype_free = %u\n",
8428                          ret, stats.mac_etype_used, stats.etype_used,
8429                          stats.mac_etype_free, stats.etype_free);
8430         if (ret < 0)
8431                 return -ENOSYS;
8432
8433         /* Add or delete a filter in SW list */
8434         if (add) {
8435                 ethertype_filter = rte_zmalloc("ethertype_filter",
8436                                        sizeof(*ethertype_filter), 0);
8437                 rte_memcpy(ethertype_filter, &check_filter,
8438                            sizeof(check_filter));
8439                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8440         } else {
8441                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8442         }
8443
8444         return ret;
8445 }
8446
8447 /*
8448  * Handle operations for ethertype filter.
8449  */
8450 static int
8451 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8452                                 enum rte_filter_op filter_op,
8453                                 void *arg)
8454 {
8455         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8456         int ret = 0;
8457
8458         if (filter_op == RTE_ETH_FILTER_NOP)
8459                 return ret;
8460
8461         if (arg == NULL) {
8462                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8463                             filter_op);
8464                 return -EINVAL;
8465         }
8466
8467         switch (filter_op) {
8468         case RTE_ETH_FILTER_ADD:
8469                 ret = i40e_ethertype_filter_set(pf,
8470                         (struct rte_eth_ethertype_filter *)arg,
8471                         TRUE);
8472                 break;
8473         case RTE_ETH_FILTER_DELETE:
8474                 ret = i40e_ethertype_filter_set(pf,
8475                         (struct rte_eth_ethertype_filter *)arg,
8476                         FALSE);
8477                 break;
8478         default:
8479                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8480                 ret = -ENOSYS;
8481                 break;
8482         }
8483         return ret;
8484 }
8485
8486 static int
8487 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8488                      enum rte_filter_type filter_type,
8489                      enum rte_filter_op filter_op,
8490                      void *arg)
8491 {
8492         int ret = 0;
8493
8494         if (dev == NULL)
8495                 return -EINVAL;
8496
8497         switch (filter_type) {
8498         case RTE_ETH_FILTER_NONE:
8499                 /* For global configuration */
8500                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8501                 break;
8502         case RTE_ETH_FILTER_HASH:
8503                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8504                 break;
8505         case RTE_ETH_FILTER_MACVLAN:
8506                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8507                 break;
8508         case RTE_ETH_FILTER_ETHERTYPE:
8509                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8510                 break;
8511         case RTE_ETH_FILTER_TUNNEL:
8512                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8513                 break;
8514         case RTE_ETH_FILTER_FDIR:
8515                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8516                 break;
8517         case RTE_ETH_FILTER_GENERIC:
8518                 if (filter_op != RTE_ETH_FILTER_GET)
8519                         return -EINVAL;
8520                 *(const void **)arg = &i40e_flow_ops;
8521                 break;
8522         default:
8523                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8524                                                         filter_type);
8525                 ret = -EINVAL;
8526                 break;
8527         }
8528
8529         return ret;
8530 }
8531
8532 /*
8533  * Check and enable Extended Tag.
8534  * Enabling Extended Tag is important for 40G performance.
8535  */
8536 static void
8537 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8538 {
8539         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8540         uint32_t buf = 0;
8541         int ret;
8542
8543         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8544                                       PCI_DEV_CAP_REG);
8545         if (ret < 0) {
8546                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8547                             PCI_DEV_CAP_REG);
8548                 return;
8549         }
8550         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8551                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8552                 return;
8553         }
8554
8555         buf = 0;
8556         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8557                                       PCI_DEV_CTRL_REG);
8558         if (ret < 0) {
8559                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8560                             PCI_DEV_CTRL_REG);
8561                 return;
8562         }
8563         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8564                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8565                 return;
8566         }
8567         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8568         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8569                                        PCI_DEV_CTRL_REG);
8570         if (ret < 0) {
8571                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8572                             PCI_DEV_CTRL_REG);
8573                 return;
8574         }
8575 }
8576
8577 /*
8578  * As some registers wouldn't be reset unless a global hardware reset,
8579  * hardware initialization is needed to put those registers into an
8580  * expected initial state.
8581  */
8582 static void
8583 i40e_hw_init(struct rte_eth_dev *dev)
8584 {
8585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8586
8587         i40e_enable_extended_tag(dev);
8588
8589         /* clear the PF Queue Filter control register */
8590         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8591
8592         /* Disable symmetric hash per port */
8593         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8594 }
8595
8596 enum i40e_filter_pctype
8597 i40e_flowtype_to_pctype(uint16_t flow_type)
8598 {
8599         static const enum i40e_filter_pctype pctype_table[] = {
8600                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8601                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8602                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8603                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8604                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8605                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8606                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8607                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8608                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8609                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8610                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8611                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8612                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8613                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8614                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8615                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8616                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8617                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8618                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8619         };
8620
8621         return pctype_table[flow_type];
8622 }
8623
8624 uint16_t
8625 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8626 {
8627         static const uint16_t flowtype_table[] = {
8628                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8629                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8630                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8631                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8632                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8633                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8634                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8635                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8636                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8637                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8638                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8639                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8640                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8641                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8642                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8643                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8644                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8645                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8646                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8647                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8648                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8649                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8650                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8651                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8652                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8653                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8654                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8655                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8656                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8657                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8658                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8659         };
8660
8661         return flowtype_table[pctype];
8662 }
8663
8664 /*
8665  * On X710, performance number is far from the expectation on recent firmware
8666  * versions; on XL710, performance number is also far from the expectation on
8667  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8668  * mode is enabled and port MAC address is equal to the packet destination MAC
8669  * address. The fix for this issue may not be integrated in the following
8670  * firmware version. So the workaround in software driver is needed. It needs
8671  * to modify the initial values of 3 internal only registers for both X710 and
8672  * XL710. Note that the values for X710 or XL710 could be different, and the
8673  * workaround can be removed when it is fixed in firmware in the future.
8674  */
8675
8676 /* For both X710 and XL710 */
8677 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8678 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8679
8680 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8681 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8682
8683 /* For X710 */
8684 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8685 /* For XL710 */
8686 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8687 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8688
8689 static int
8690 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8691 {
8692         enum i40e_status_code status;
8693         struct i40e_aq_get_phy_abilities_resp phy_ab;
8694         int ret = -ENOTSUP;
8695
8696         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8697                                               NULL);
8698
8699         if (status)
8700                 return ret;
8701
8702         return 0;
8703 }
8704
8705
8706 static void
8707 i40e_configure_registers(struct i40e_hw *hw)
8708 {
8709         static struct {
8710                 uint32_t addr;
8711                 uint64_t val;
8712         } reg_table[] = {
8713                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8714                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8715                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8716         };
8717         uint64_t reg;
8718         uint32_t i;
8719         int ret;
8720
8721         for (i = 0; i < RTE_DIM(reg_table); i++) {
8722                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8723                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8724                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8725                                 reg_table[i].val =
8726                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8727                         else /* For X710 */
8728                                 reg_table[i].val =
8729                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8730                 }
8731
8732                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8733                                                         &reg, NULL);
8734                 if (ret < 0) {
8735                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8736                                                         reg_table[i].addr);
8737                         break;
8738                 }
8739                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8740                                                 reg_table[i].addr, reg);
8741                 if (reg == reg_table[i].val)
8742                         continue;
8743
8744                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8745                                                 reg_table[i].val, NULL);
8746                 if (ret < 0) {
8747                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8748                                 "address of 0x%"PRIx32, reg_table[i].val,
8749                                                         reg_table[i].addr);
8750                         break;
8751                 }
8752                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8753                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8754         }
8755 }
8756
8757 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8758 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8759 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8760 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8761 static int
8762 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8763 {
8764         uint32_t reg;
8765         int ret;
8766
8767         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8768                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8769                 return -EINVAL;
8770         }
8771
8772         /* Configure for double VLAN RX stripping */
8773         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8774         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8775                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8776                 ret = i40e_aq_debug_write_register(hw,
8777                                                    I40E_VSI_TSR(vsi->vsi_id),
8778                                                    reg, NULL);
8779                 if (ret < 0) {
8780                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8781                                     vsi->vsi_id);
8782                         return I40E_ERR_CONFIG;
8783                 }
8784         }
8785
8786         /* Configure for double VLAN TX insertion */
8787         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8788         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8789                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8790                 ret = i40e_aq_debug_write_register(hw,
8791                                                    I40E_VSI_L2TAGSTXVALID(
8792                                                    vsi->vsi_id), reg, NULL);
8793                 if (ret < 0) {
8794                         PMD_DRV_LOG(ERR, "Failed to update "
8795                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8796                         return I40E_ERR_CONFIG;
8797                 }
8798         }
8799
8800         return 0;
8801 }
8802
8803 /**
8804  * i40e_aq_add_mirror_rule
8805  * @hw: pointer to the hardware structure
8806  * @seid: VEB seid to add mirror rule to
8807  * @dst_id: destination vsi seid
8808  * @entries: Buffer which contains the entities to be mirrored
8809  * @count: number of entities contained in the buffer
8810  * @rule_id:the rule_id of the rule to be added
8811  *
8812  * Add a mirror rule for a given veb.
8813  *
8814  **/
8815 static enum i40e_status_code
8816 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8817                         uint16_t seid, uint16_t dst_id,
8818                         uint16_t rule_type, uint16_t *entries,
8819                         uint16_t count, uint16_t *rule_id)
8820 {
8821         struct i40e_aq_desc desc;
8822         struct i40e_aqc_add_delete_mirror_rule cmd;
8823         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8824                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8825                 &desc.params.raw;
8826         uint16_t buff_len;
8827         enum i40e_status_code status;
8828
8829         i40e_fill_default_direct_cmd_desc(&desc,
8830                                           i40e_aqc_opc_add_mirror_rule);
8831         memset(&cmd, 0, sizeof(cmd));
8832
8833         buff_len = sizeof(uint16_t) * count;
8834         desc.datalen = rte_cpu_to_le_16(buff_len);
8835         if (buff_len > 0)
8836                 desc.flags |= rte_cpu_to_le_16(
8837                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8838         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8839                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8840         cmd.num_entries = rte_cpu_to_le_16(count);
8841         cmd.seid = rte_cpu_to_le_16(seid);
8842         cmd.destination = rte_cpu_to_le_16(dst_id);
8843
8844         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8845         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8846         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8847                          "rule_id = %u"
8848                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8849                          hw->aq.asq_last_status, resp->rule_id,
8850                          resp->mirror_rules_used, resp->mirror_rules_free);
8851         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8852
8853         return status;
8854 }
8855
8856 /**
8857  * i40e_aq_del_mirror_rule
8858  * @hw: pointer to the hardware structure
8859  * @seid: VEB seid to add mirror rule to
8860  * @entries: Buffer which contains the entities to be mirrored
8861  * @count: number of entities contained in the buffer
8862  * @rule_id:the rule_id of the rule to be delete
8863  *
8864  * Delete a mirror rule for a given veb.
8865  *
8866  **/
8867 static enum i40e_status_code
8868 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8869                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8870                 uint16_t count, uint16_t rule_id)
8871 {
8872         struct i40e_aq_desc desc;
8873         struct i40e_aqc_add_delete_mirror_rule cmd;
8874         uint16_t buff_len = 0;
8875         enum i40e_status_code status;
8876         void *buff = NULL;
8877
8878         i40e_fill_default_direct_cmd_desc(&desc,
8879                                           i40e_aqc_opc_delete_mirror_rule);
8880         memset(&cmd, 0, sizeof(cmd));
8881         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8882                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8883                                                           I40E_AQ_FLAG_RD));
8884                 cmd.num_entries = count;
8885                 buff_len = sizeof(uint16_t) * count;
8886                 desc.datalen = rte_cpu_to_le_16(buff_len);
8887                 buff = (void *)entries;
8888         } else
8889                 /* rule id is filled in destination field for deleting mirror rule */
8890                 cmd.destination = rte_cpu_to_le_16(rule_id);
8891
8892         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8893                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8894         cmd.seid = rte_cpu_to_le_16(seid);
8895
8896         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8897         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8898
8899         return status;
8900 }
8901
8902 /**
8903  * i40e_mirror_rule_set
8904  * @dev: pointer to the hardware structure
8905  * @mirror_conf: mirror rule info
8906  * @sw_id: mirror rule's sw_id
8907  * @on: enable/disable
8908  *
8909  * set a mirror rule.
8910  *
8911  **/
8912 static int
8913 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8914                         struct rte_eth_mirror_conf *mirror_conf,
8915                         uint8_t sw_id, uint8_t on)
8916 {
8917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8919         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8920         struct i40e_mirror_rule *parent = NULL;
8921         uint16_t seid, dst_seid, rule_id;
8922         uint16_t i, j = 0;
8923         int ret;
8924
8925         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8926
8927         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8928                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8929                         " without veb or vfs.");
8930                 return -ENOSYS;
8931         }
8932         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8933                 PMD_DRV_LOG(ERR, "mirror table is full.");
8934                 return -ENOSPC;
8935         }
8936         if (mirror_conf->dst_pool > pf->vf_num) {
8937                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8938                                  mirror_conf->dst_pool);
8939                 return -EINVAL;
8940         }
8941
8942         seid = pf->main_vsi->veb->seid;
8943
8944         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8945                 if (sw_id <= it->index) {
8946                         mirr_rule = it;
8947                         break;
8948                 }
8949                 parent = it;
8950         }
8951         if (mirr_rule && sw_id == mirr_rule->index) {
8952                 if (on) {
8953                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8954                         return -EEXIST;
8955                 } else {
8956                         ret = i40e_aq_del_mirror_rule(hw, seid,
8957                                         mirr_rule->rule_type,
8958                                         mirr_rule->entries,
8959                                         mirr_rule->num_entries, mirr_rule->id);
8960                         if (ret < 0) {
8961                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8962                                                    " ret = %d, aq_err = %d.",
8963                                                    ret, hw->aq.asq_last_status);
8964                                 return -ENOSYS;
8965                         }
8966                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8967                         rte_free(mirr_rule);
8968                         pf->nb_mirror_rule--;
8969                         return 0;
8970                 }
8971         } else if (!on) {
8972                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8973                 return -ENOENT;
8974         }
8975
8976         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8977                                 sizeof(struct i40e_mirror_rule) , 0);
8978         if (!mirr_rule) {
8979                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8980                 return I40E_ERR_NO_MEMORY;
8981         }
8982         switch (mirror_conf->rule_type) {
8983         case ETH_MIRROR_VLAN:
8984                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8985                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8986                                 mirr_rule->entries[j] =
8987                                         mirror_conf->vlan.vlan_id[i];
8988                                 j++;
8989                         }
8990                 }
8991                 if (j == 0) {
8992                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8993                         rte_free(mirr_rule);
8994                         return -EINVAL;
8995                 }
8996                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8997                 break;
8998         case ETH_MIRROR_VIRTUAL_POOL_UP:
8999         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9000                 /* check if the specified pool bit is out of range */
9001                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9002                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9003                         rte_free(mirr_rule);
9004                         return -EINVAL;
9005                 }
9006                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9007                         if (mirror_conf->pool_mask & (1ULL << i)) {
9008                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9009                                 j++;
9010                         }
9011                 }
9012                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9013                         /* add pf vsi to entries */
9014                         mirr_rule->entries[j] = pf->main_vsi_seid;
9015                         j++;
9016                 }
9017                 if (j == 0) {
9018                         PMD_DRV_LOG(ERR, "pool is not specified.");
9019                         rte_free(mirr_rule);
9020                         return -EINVAL;
9021                 }
9022                 /* egress and ingress in aq commands means from switch but not port */
9023                 mirr_rule->rule_type =
9024                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9025                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9026                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9027                 break;
9028         case ETH_MIRROR_UPLINK_PORT:
9029                 /* egress and ingress in aq commands means from switch but not port*/
9030                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9031                 break;
9032         case ETH_MIRROR_DOWNLINK_PORT:
9033                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9034                 break;
9035         default:
9036                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9037                         mirror_conf->rule_type);
9038                 rte_free(mirr_rule);
9039                 return -EINVAL;
9040         }
9041
9042         /* If the dst_pool is equal to vf_num, consider it as PF */
9043         if (mirror_conf->dst_pool == pf->vf_num)
9044                 dst_seid = pf->main_vsi_seid;
9045         else
9046                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9047
9048         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9049                                       mirr_rule->rule_type, mirr_rule->entries,
9050                                       j, &rule_id);
9051         if (ret < 0) {
9052                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9053                                    " ret = %d, aq_err = %d.",
9054                                    ret, hw->aq.asq_last_status);
9055                 rte_free(mirr_rule);
9056                 return -ENOSYS;
9057         }
9058
9059         mirr_rule->index = sw_id;
9060         mirr_rule->num_entries = j;
9061         mirr_rule->id = rule_id;
9062         mirr_rule->dst_vsi_seid = dst_seid;
9063
9064         if (parent)
9065                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9066         else
9067                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9068
9069         pf->nb_mirror_rule++;
9070         return 0;
9071 }
9072
9073 /**
9074  * i40e_mirror_rule_reset
9075  * @dev: pointer to the device
9076  * @sw_id: mirror rule's sw_id
9077  *
9078  * reset a mirror rule.
9079  *
9080  **/
9081 static int
9082 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9083 {
9084         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9086         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9087         uint16_t seid;
9088         int ret;
9089
9090         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9091
9092         seid = pf->main_vsi->veb->seid;
9093
9094         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9095                 if (sw_id == it->index) {
9096                         mirr_rule = it;
9097                         break;
9098                 }
9099         }
9100         if (mirr_rule) {
9101                 ret = i40e_aq_del_mirror_rule(hw, seid,
9102                                 mirr_rule->rule_type,
9103                                 mirr_rule->entries,
9104                                 mirr_rule->num_entries, mirr_rule->id);
9105                 if (ret < 0) {
9106                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9107                                            " status = %d, aq_err = %d.",
9108                                            ret, hw->aq.asq_last_status);
9109                         return -ENOSYS;
9110                 }
9111                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9112                 rte_free(mirr_rule);
9113                 pf->nb_mirror_rule--;
9114         } else {
9115                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9116                 return -ENOENT;
9117         }
9118         return 0;
9119 }
9120
9121 static uint64_t
9122 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9123 {
9124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9125         uint64_t systim_cycles;
9126
9127         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9128         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9129                         << 32;
9130
9131         return systim_cycles;
9132 }
9133
9134 static uint64_t
9135 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9136 {
9137         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9138         uint64_t rx_tstamp;
9139
9140         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9141         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9142                         << 32;
9143
9144         return rx_tstamp;
9145 }
9146
9147 static uint64_t
9148 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9149 {
9150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9151         uint64_t tx_tstamp;
9152
9153         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9154         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9155                         << 32;
9156
9157         return tx_tstamp;
9158 }
9159
9160 static void
9161 i40e_start_timecounters(struct rte_eth_dev *dev)
9162 {
9163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9164         struct i40e_adapter *adapter =
9165                         (struct i40e_adapter *)dev->data->dev_private;
9166         struct rte_eth_link link;
9167         uint32_t tsync_inc_l;
9168         uint32_t tsync_inc_h;
9169
9170         /* Get current link speed. */
9171         memset(&link, 0, sizeof(link));
9172         i40e_dev_link_update(dev, 1);
9173         rte_i40e_dev_atomic_read_link_status(dev, &link);
9174
9175         switch (link.link_speed) {
9176         case ETH_SPEED_NUM_40G:
9177                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9178                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9179                 break;
9180         case ETH_SPEED_NUM_10G:
9181                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9182                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9183                 break;
9184         case ETH_SPEED_NUM_1G:
9185                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9186                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9187                 break;
9188         default:
9189                 tsync_inc_l = 0x0;
9190                 tsync_inc_h = 0x0;
9191         }
9192
9193         /* Set the timesync increment value. */
9194         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9195         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9196
9197         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9198         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9199         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9200
9201         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9202         adapter->systime_tc.cc_shift = 0;
9203         adapter->systime_tc.nsec_mask = 0;
9204
9205         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9206         adapter->rx_tstamp_tc.cc_shift = 0;
9207         adapter->rx_tstamp_tc.nsec_mask = 0;
9208
9209         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9210         adapter->tx_tstamp_tc.cc_shift = 0;
9211         adapter->tx_tstamp_tc.nsec_mask = 0;
9212 }
9213
9214 static int
9215 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9216 {
9217         struct i40e_adapter *adapter =
9218                         (struct i40e_adapter *)dev->data->dev_private;
9219
9220         adapter->systime_tc.nsec += delta;
9221         adapter->rx_tstamp_tc.nsec += delta;
9222         adapter->tx_tstamp_tc.nsec += delta;
9223
9224         return 0;
9225 }
9226
9227 static int
9228 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9229 {
9230         uint64_t ns;
9231         struct i40e_adapter *adapter =
9232                         (struct i40e_adapter *)dev->data->dev_private;
9233
9234         ns = rte_timespec_to_ns(ts);
9235
9236         /* Set the timecounters to a new value. */
9237         adapter->systime_tc.nsec = ns;
9238         adapter->rx_tstamp_tc.nsec = ns;
9239         adapter->tx_tstamp_tc.nsec = ns;
9240
9241         return 0;
9242 }
9243
9244 static int
9245 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9246 {
9247         uint64_t ns, systime_cycles;
9248         struct i40e_adapter *adapter =
9249                         (struct i40e_adapter *)dev->data->dev_private;
9250
9251         systime_cycles = i40e_read_systime_cyclecounter(dev);
9252         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9253         *ts = rte_ns_to_timespec(ns);
9254
9255         return 0;
9256 }
9257
9258 static int
9259 i40e_timesync_enable(struct rte_eth_dev *dev)
9260 {
9261         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9262         uint32_t tsync_ctl_l;
9263         uint32_t tsync_ctl_h;
9264
9265         /* Stop the timesync system time. */
9266         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9267         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9268         /* Reset the timesync system time value. */
9269         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9270         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9271
9272         i40e_start_timecounters(dev);
9273
9274         /* Clear timesync registers. */
9275         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9276         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9277         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9278         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9279         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9280         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9281
9282         /* Enable timestamping of PTP packets. */
9283         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9284         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9285
9286         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9287         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9288         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9289
9290         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9291         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9292
9293         return 0;
9294 }
9295
9296 static int
9297 i40e_timesync_disable(struct rte_eth_dev *dev)
9298 {
9299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9300         uint32_t tsync_ctl_l;
9301         uint32_t tsync_ctl_h;
9302
9303         /* Disable timestamping of transmitted PTP packets. */
9304         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9305         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9306
9307         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9308         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9309
9310         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9311         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9312
9313         /* Reset the timesync increment value. */
9314         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9315         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9316
9317         return 0;
9318 }
9319
9320 static int
9321 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9322                                 struct timespec *timestamp, uint32_t flags)
9323 {
9324         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9325         struct i40e_adapter *adapter =
9326                 (struct i40e_adapter *)dev->data->dev_private;
9327
9328         uint32_t sync_status;
9329         uint32_t index = flags & 0x03;
9330         uint64_t rx_tstamp_cycles;
9331         uint64_t ns;
9332
9333         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9334         if ((sync_status & (1 << index)) == 0)
9335                 return -EINVAL;
9336
9337         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9338         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9339         *timestamp = rte_ns_to_timespec(ns);
9340
9341         return 0;
9342 }
9343
9344 static int
9345 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9346                                 struct timespec *timestamp)
9347 {
9348         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9349         struct i40e_adapter *adapter =
9350                 (struct i40e_adapter *)dev->data->dev_private;
9351
9352         uint32_t sync_status;
9353         uint64_t tx_tstamp_cycles;
9354         uint64_t ns;
9355
9356         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9357         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9358                 return -EINVAL;
9359
9360         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9361         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9362         *timestamp = rte_ns_to_timespec(ns);
9363
9364         return 0;
9365 }
9366
9367 /*
9368  * i40e_parse_dcb_configure - parse dcb configure from user
9369  * @dev: the device being configured
9370  * @dcb_cfg: pointer of the result of parse
9371  * @*tc_map: bit map of enabled traffic classes
9372  *
9373  * Returns 0 on success, negative value on failure
9374  */
9375 static int
9376 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9377                          struct i40e_dcbx_config *dcb_cfg,
9378                          uint8_t *tc_map)
9379 {
9380         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9381         uint8_t i, tc_bw, bw_lf;
9382
9383         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9384
9385         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9386         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9387                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9388                 return -EINVAL;
9389         }
9390
9391         /* assume each tc has the same bw */
9392         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9393         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9394                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9395         /* to ensure the sum of tcbw is equal to 100 */
9396         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9397         for (i = 0; i < bw_lf; i++)
9398                 dcb_cfg->etscfg.tcbwtable[i]++;
9399
9400         /* assume each tc has the same Transmission Selection Algorithm */
9401         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9402                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9403
9404         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9405                 dcb_cfg->etscfg.prioritytable[i] =
9406                                 dcb_rx_conf->dcb_tc[i];
9407
9408         /* FW needs one App to configure HW */
9409         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9410         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9411         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9412         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9413
9414         if (dcb_rx_conf->nb_tcs == 0)
9415                 *tc_map = 1; /* tc0 only */
9416         else
9417                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9418
9419         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9420                 dcb_cfg->pfc.willing = 0;
9421                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9422                 dcb_cfg->pfc.pfcenable = *tc_map;
9423         }
9424         return 0;
9425 }
9426
9427
9428 static enum i40e_status_code
9429 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9430                               struct i40e_aqc_vsi_properties_data *info,
9431                               uint8_t enabled_tcmap)
9432 {
9433         enum i40e_status_code ret;
9434         int i, total_tc = 0;
9435         uint16_t qpnum_per_tc, bsf, qp_idx;
9436         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9437         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9438         uint16_t used_queues;
9439
9440         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9441         if (ret != I40E_SUCCESS)
9442                 return ret;
9443
9444         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9445                 if (enabled_tcmap & (1 << i))
9446                         total_tc++;
9447         }
9448         if (total_tc == 0)
9449                 total_tc = 1;
9450         vsi->enabled_tc = enabled_tcmap;
9451
9452         /* different VSI has different queues assigned */
9453         if (vsi->type == I40E_VSI_MAIN)
9454                 used_queues = dev_data->nb_rx_queues -
9455                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9456         else if (vsi->type == I40E_VSI_VMDQ2)
9457                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9458         else {
9459                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9460                 return I40E_ERR_NO_AVAILABLE_VSI;
9461         }
9462
9463         qpnum_per_tc = used_queues / total_tc;
9464         /* Number of queues per enabled TC */
9465         if (qpnum_per_tc == 0) {
9466                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9467                 return I40E_ERR_INVALID_QP_ID;
9468         }
9469         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9470                                 I40E_MAX_Q_PER_TC);
9471         bsf = rte_bsf32(qpnum_per_tc);
9472
9473         /**
9474          * Configure TC and queue mapping parameters, for enabled TC,
9475          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9476          * default queue will serve it.
9477          */
9478         qp_idx = 0;
9479         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9480                 if (vsi->enabled_tc & (1 << i)) {
9481                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9482                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9483                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9484                         qp_idx += qpnum_per_tc;
9485                 } else
9486                         info->tc_mapping[i] = 0;
9487         }
9488
9489         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9490         if (vsi->type == I40E_VSI_SRIOV) {
9491                 info->mapping_flags |=
9492                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9493                 for (i = 0; i < vsi->nb_qps; i++)
9494                         info->queue_mapping[i] =
9495                                 rte_cpu_to_le_16(vsi->base_queue + i);
9496         } else {
9497                 info->mapping_flags |=
9498                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9499                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9500         }
9501         info->valid_sections |=
9502                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9503
9504         return I40E_SUCCESS;
9505 }
9506
9507 /*
9508  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9509  * @veb: VEB to be configured
9510  * @tc_map: enabled TC bitmap
9511  *
9512  * Returns 0 on success, negative value on failure
9513  */
9514 static enum i40e_status_code
9515 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9516 {
9517         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9518         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9519         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9520         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9521         enum i40e_status_code ret = I40E_SUCCESS;
9522         int i;
9523         uint32_t bw_max;
9524
9525         /* Check if enabled_tc is same as existing or new TCs */
9526         if (veb->enabled_tc == tc_map)
9527                 return ret;
9528
9529         /* configure tc bandwidth */
9530         memset(&veb_bw, 0, sizeof(veb_bw));
9531         veb_bw.tc_valid_bits = tc_map;
9532         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9533         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9534                 if (tc_map & BIT_ULL(i))
9535                         veb_bw.tc_bw_share_credits[i] = 1;
9536         }
9537         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9538                                                    &veb_bw, NULL);
9539         if (ret) {
9540                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9541                                   " per TC failed = %d",
9542                                   hw->aq.asq_last_status);
9543                 return ret;
9544         }
9545
9546         memset(&ets_query, 0, sizeof(ets_query));
9547         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9548                                                    &ets_query, NULL);
9549         if (ret != I40E_SUCCESS) {
9550                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9551                                  " configuration %u", hw->aq.asq_last_status);
9552                 return ret;
9553         }
9554         memset(&bw_query, 0, sizeof(bw_query));
9555         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9556                                                   &bw_query, NULL);
9557         if (ret != I40E_SUCCESS) {
9558                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9559                                  " configuration %u", hw->aq.asq_last_status);
9560                 return ret;
9561         }
9562
9563         /* store and print out BW info */
9564         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9565         veb->bw_info.bw_max = ets_query.tc_bw_max;
9566         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9567         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9568         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9569                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9570                      I40E_16_BIT_WIDTH);
9571         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9572                 veb->bw_info.bw_ets_share_credits[i] =
9573                                 bw_query.tc_bw_share_credits[i];
9574                 veb->bw_info.bw_ets_credits[i] =
9575                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9576                 /* 4 bits per TC, 4th bit is reserved */
9577                 veb->bw_info.bw_ets_max[i] =
9578                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9579                                   RTE_LEN2MASK(3, uint8_t));
9580                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9581                             veb->bw_info.bw_ets_share_credits[i]);
9582                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9583                             veb->bw_info.bw_ets_credits[i]);
9584                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9585                             veb->bw_info.bw_ets_max[i]);
9586         }
9587
9588         veb->enabled_tc = tc_map;
9589
9590         return ret;
9591 }
9592
9593
9594 /*
9595  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9596  * @vsi: VSI to be configured
9597  * @tc_map: enabled TC bitmap
9598  *
9599  * Returns 0 on success, negative value on failure
9600  */
9601 static enum i40e_status_code
9602 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9603 {
9604         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9605         struct i40e_vsi_context ctxt;
9606         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9607         enum i40e_status_code ret = I40E_SUCCESS;
9608         int i;
9609
9610         /* Check if enabled_tc is same as existing or new TCs */
9611         if (vsi->enabled_tc == tc_map)
9612                 return ret;
9613
9614         /* configure tc bandwidth */
9615         memset(&bw_data, 0, sizeof(bw_data));
9616         bw_data.tc_valid_bits = tc_map;
9617         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9618         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9619                 if (tc_map & BIT_ULL(i))
9620                         bw_data.tc_bw_credits[i] = 1;
9621         }
9622         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9623         if (ret) {
9624                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9625                         " per TC failed = %d",
9626                         hw->aq.asq_last_status);
9627                 goto out;
9628         }
9629         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9630                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9631
9632         /* Update Queue Pairs Mapping for currently enabled UPs */
9633         ctxt.seid = vsi->seid;
9634         ctxt.pf_num = hw->pf_id;
9635         ctxt.vf_num = 0;
9636         ctxt.uplink_seid = vsi->uplink_seid;
9637         ctxt.info = vsi->info;
9638         i40e_get_cap(hw);
9639         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9640         if (ret)
9641                 goto out;
9642
9643         /* Update the VSI after updating the VSI queue-mapping information */
9644         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9645         if (ret) {
9646                 PMD_INIT_LOG(ERR, "Failed to configure "
9647                             "TC queue mapping = %d",
9648                             hw->aq.asq_last_status);
9649                 goto out;
9650         }
9651         /* update the local VSI info with updated queue map */
9652         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9653                                         sizeof(vsi->info.tc_mapping));
9654         (void)rte_memcpy(&vsi->info.queue_mapping,
9655                         &ctxt.info.queue_mapping,
9656                 sizeof(vsi->info.queue_mapping));
9657         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9658         vsi->info.valid_sections = 0;
9659
9660         /* query and update current VSI BW information */
9661         ret = i40e_vsi_get_bw_config(vsi);
9662         if (ret) {
9663                 PMD_INIT_LOG(ERR,
9664                          "Failed updating vsi bw info, err %s aq_err %s",
9665                          i40e_stat_str(hw, ret),
9666                          i40e_aq_str(hw, hw->aq.asq_last_status));
9667                 goto out;
9668         }
9669
9670         vsi->enabled_tc = tc_map;
9671
9672 out:
9673         return ret;
9674 }
9675
9676 /*
9677  * i40e_dcb_hw_configure - program the dcb setting to hw
9678  * @pf: pf the configuration is taken on
9679  * @new_cfg: new configuration
9680  * @tc_map: enabled TC bitmap
9681  *
9682  * Returns 0 on success, negative value on failure
9683  */
9684 static enum i40e_status_code
9685 i40e_dcb_hw_configure(struct i40e_pf *pf,
9686                       struct i40e_dcbx_config *new_cfg,
9687                       uint8_t tc_map)
9688 {
9689         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9690         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9691         struct i40e_vsi *main_vsi = pf->main_vsi;
9692         struct i40e_vsi_list *vsi_list;
9693         enum i40e_status_code ret;
9694         int i;
9695         uint32_t val;
9696
9697         /* Use the FW API if FW > v4.4*/
9698         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9699               (hw->aq.fw_maj_ver >= 5))) {
9700                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9701                                   " to configure DCB");
9702                 return I40E_ERR_FIRMWARE_API_VERSION;
9703         }
9704
9705         /* Check if need reconfiguration */
9706         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9707                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9708                 return I40E_SUCCESS;
9709         }
9710
9711         /* Copy the new config to the current config */
9712         *old_cfg = *new_cfg;
9713         old_cfg->etsrec = old_cfg->etscfg;
9714         ret = i40e_set_dcb_config(hw);
9715         if (ret) {
9716                 PMD_INIT_LOG(ERR,
9717                          "Set DCB Config failed, err %s aq_err %s\n",
9718                          i40e_stat_str(hw, ret),
9719                          i40e_aq_str(hw, hw->aq.asq_last_status));
9720                 return ret;
9721         }
9722         /* set receive Arbiter to RR mode and ETS scheme by default */
9723         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9724                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9725                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9726                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9727                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9728                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9729                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9730                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9731                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9732                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9733                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9734                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9735                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9736         }
9737         /* get local mib to check whether it is configured correctly */
9738         /* IEEE mode */
9739         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9740         /* Get Local DCB Config */
9741         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9742                                      &hw->local_dcbx_config);
9743
9744         /* if Veb is created, need to update TC of it at first */
9745         if (main_vsi->veb) {
9746                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9747                 if (ret)
9748                         PMD_INIT_LOG(WARNING,
9749                                  "Failed configuring TC for VEB seid=%d\n",
9750                                  main_vsi->veb->seid);
9751         }
9752         /* Update each VSI */
9753         i40e_vsi_config_tc(main_vsi, tc_map);
9754         if (main_vsi->veb) {
9755                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9756                         /* Beside main VSI and VMDQ VSIs, only enable default
9757                          * TC for other VSIs
9758                          */
9759                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9760                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9761                                                          tc_map);
9762                         else
9763                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9764                                                          I40E_DEFAULT_TCMAP);
9765                         if (ret)
9766                                 PMD_INIT_LOG(WARNING,
9767                                          "Failed configuring TC for VSI seid=%d\n",
9768                                          vsi_list->vsi->seid);
9769                         /* continue */
9770                 }
9771         }
9772         return I40E_SUCCESS;
9773 }
9774
9775 /*
9776  * i40e_dcb_init_configure - initial dcb config
9777  * @dev: device being configured
9778  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9779  *
9780  * Returns 0 on success, negative value on failure
9781  */
9782 static int
9783 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9784 {
9785         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9786         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9787         int ret = 0;
9788
9789         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9790                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9791                 return -ENOTSUP;
9792         }
9793
9794         /* DCB initialization:
9795          * Update DCB configuration from the Firmware and configure
9796          * LLDP MIB change event.
9797          */
9798         if (sw_dcb == TRUE) {
9799                 ret = i40e_init_dcb(hw);
9800                 /* If lldp agent is stopped, the return value from
9801                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9802                  * adminq status. Otherwise, it should return success.
9803                  */
9804                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9805                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9806                         memset(&hw->local_dcbx_config, 0,
9807                                 sizeof(struct i40e_dcbx_config));
9808                         /* set dcb default configuration */
9809                         hw->local_dcbx_config.etscfg.willing = 0;
9810                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9811                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9812                         hw->local_dcbx_config.etscfg.tsatable[0] =
9813                                                 I40E_IEEE_TSA_ETS;
9814                         hw->local_dcbx_config.etsrec =
9815                                 hw->local_dcbx_config.etscfg;
9816                         hw->local_dcbx_config.pfc.willing = 0;
9817                         hw->local_dcbx_config.pfc.pfccap =
9818                                                 I40E_MAX_TRAFFIC_CLASS;
9819                         /* FW needs one App to configure HW */
9820                         hw->local_dcbx_config.numapps = 1;
9821                         hw->local_dcbx_config.app[0].selector =
9822                                                 I40E_APP_SEL_ETHTYPE;
9823                         hw->local_dcbx_config.app[0].priority = 3;
9824                         hw->local_dcbx_config.app[0].protocolid =
9825                                                 I40E_APP_PROTOID_FCOE;
9826                         ret = i40e_set_dcb_config(hw);
9827                         if (ret) {
9828                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9829                                         " err = %d, aq_err = %d.", ret,
9830                                           hw->aq.asq_last_status);
9831                                 return -ENOSYS;
9832                         }
9833                 } else {
9834                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9835                                           " err = %d, aq_err = %d.", ret,
9836                                           hw->aq.asq_last_status);
9837                         return -ENOTSUP;
9838                 }
9839         } else {
9840                 ret = i40e_aq_start_lldp(hw, NULL);
9841                 if (ret != I40E_SUCCESS)
9842                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9843
9844                 ret = i40e_init_dcb(hw);
9845                 if (!ret) {
9846                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9847                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9848                                                   " DCBX offload.");
9849                                 return -ENOTSUP;
9850                         }
9851                 } else {
9852                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9853                                           " aq_err = %d.", ret,
9854                                           hw->aq.asq_last_status);
9855                         return -ENOTSUP;
9856                 }
9857         }
9858         return 0;
9859 }
9860
9861 /*
9862  * i40e_dcb_setup - setup dcb related config
9863  * @dev: device being configured
9864  *
9865  * Returns 0 on success, negative value on failure
9866  */
9867 static int
9868 i40e_dcb_setup(struct rte_eth_dev *dev)
9869 {
9870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9871         struct i40e_dcbx_config dcb_cfg;
9872         uint8_t tc_map = 0;
9873         int ret = 0;
9874
9875         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9876                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9877                 return -ENOTSUP;
9878         }
9879
9880         if (pf->vf_num != 0)
9881                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9882
9883         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9884         if (ret) {
9885                 PMD_INIT_LOG(ERR, "invalid dcb config");
9886                 return -EINVAL;
9887         }
9888         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9889         if (ret) {
9890                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9891                 return -ENOSYS;
9892         }
9893
9894         return 0;
9895 }
9896
9897 static int
9898 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9899                       struct rte_eth_dcb_info *dcb_info)
9900 {
9901         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9903         struct i40e_vsi *vsi = pf->main_vsi;
9904         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9905         uint16_t bsf, tc_mapping;
9906         int i, j = 0;
9907
9908         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9909                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9910         else
9911                 dcb_info->nb_tcs = 1;
9912         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9913                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9914         for (i = 0; i < dcb_info->nb_tcs; i++)
9915                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9916
9917         /* get queue mapping if vmdq is disabled */
9918         if (!pf->nb_cfg_vmdq_vsi) {
9919                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9920                         if (!(vsi->enabled_tc & (1 << i)))
9921                                 continue;
9922                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9923                         dcb_info->tc_queue.tc_rxq[j][i].base =
9924                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9925                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9926                         dcb_info->tc_queue.tc_txq[j][i].base =
9927                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9928                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9929                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9930                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9931                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9932                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9933                 }
9934                 return 0;
9935         }
9936
9937         /* get queue mapping if vmdq is enabled */
9938         do {
9939                 vsi = pf->vmdq[j].vsi;
9940                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9941                         if (!(vsi->enabled_tc & (1 << i)))
9942                                 continue;
9943                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9944                         dcb_info->tc_queue.tc_rxq[j][i].base =
9945                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9946                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9947                         dcb_info->tc_queue.tc_txq[j][i].base =
9948                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9949                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9950                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9951                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9952                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9953                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9954                 }
9955                 j++;
9956         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9957         return 0;
9958 }
9959
9960 static int
9961 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9962 {
9963         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9964         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9966         uint16_t interval =
9967                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9968         uint16_t msix_intr;
9969
9970         msix_intr = intr_handle->intr_vec[queue_id];
9971         if (msix_intr == I40E_MISC_VEC_ID)
9972                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9973                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9974                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9975                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9976                                (interval <<
9977                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9978         else
9979                 I40E_WRITE_REG(hw,
9980                                I40E_PFINT_DYN_CTLN(msix_intr -
9981                                                    I40E_RX_VEC_START),
9982                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9983                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9984                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9985                                (interval <<
9986                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9987
9988         I40E_WRITE_FLUSH(hw);
9989         rte_intr_enable(&pci_dev->intr_handle);
9990
9991         return 0;
9992 }
9993
9994 static int
9995 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9996 {
9997         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9998         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9999         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10000         uint16_t msix_intr;
10001
10002         msix_intr = intr_handle->intr_vec[queue_id];
10003         if (msix_intr == I40E_MISC_VEC_ID)
10004                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10005         else
10006                 I40E_WRITE_REG(hw,
10007                                I40E_PFINT_DYN_CTLN(msix_intr -
10008                                                    I40E_RX_VEC_START),
10009                                0);
10010         I40E_WRITE_FLUSH(hw);
10011
10012         return 0;
10013 }
10014
10015 static int i40e_get_regs(struct rte_eth_dev *dev,
10016                          struct rte_dev_reg_info *regs)
10017 {
10018         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10019         uint32_t *ptr_data = regs->data;
10020         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10021         const struct i40e_reg_info *reg_info;
10022
10023         if (ptr_data == NULL) {
10024                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10025                 regs->width = sizeof(uint32_t);
10026                 return 0;
10027         }
10028
10029         /* The first few registers have to be read using AQ operations */
10030         reg_idx = 0;
10031         while (i40e_regs_adminq[reg_idx].name) {
10032                 reg_info = &i40e_regs_adminq[reg_idx++];
10033                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10034                         for (arr_idx2 = 0;
10035                                         arr_idx2 <= reg_info->count2;
10036                                         arr_idx2++) {
10037                                 reg_offset = arr_idx * reg_info->stride1 +
10038                                         arr_idx2 * reg_info->stride2;
10039                                 reg_offset += reg_info->base_addr;
10040                                 ptr_data[reg_offset >> 2] =
10041                                         i40e_read_rx_ctl(hw, reg_offset);
10042                         }
10043         }
10044
10045         /* The remaining registers can be read using primitives */
10046         reg_idx = 0;
10047         while (i40e_regs_others[reg_idx].name) {
10048                 reg_info = &i40e_regs_others[reg_idx++];
10049                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10050                         for (arr_idx2 = 0;
10051                                         arr_idx2 <= reg_info->count2;
10052                                         arr_idx2++) {
10053                                 reg_offset = arr_idx * reg_info->stride1 +
10054                                         arr_idx2 * reg_info->stride2;
10055                                 reg_offset += reg_info->base_addr;
10056                                 ptr_data[reg_offset >> 2] =
10057                                         I40E_READ_REG(hw, reg_offset);
10058                         }
10059         }
10060
10061         return 0;
10062 }
10063
10064 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10065 {
10066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10067
10068         /* Convert word count to byte count */
10069         return hw->nvm.sr_size << 1;
10070 }
10071
10072 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10073                            struct rte_dev_eeprom_info *eeprom)
10074 {
10075         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10076         uint16_t *data = eeprom->data;
10077         uint16_t offset, length, cnt_words;
10078         int ret_code;
10079
10080         offset = eeprom->offset >> 1;
10081         length = eeprom->length >> 1;
10082         cnt_words = length;
10083
10084         if (offset > hw->nvm.sr_size ||
10085                 offset + length > hw->nvm.sr_size) {
10086                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10087                 return -EINVAL;
10088         }
10089
10090         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10091
10092         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10093         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10094                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10095                 return -EIO;
10096         }
10097
10098         return 0;
10099 }
10100
10101 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10102                                       struct ether_addr *mac_addr)
10103 {
10104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10105
10106         if (!is_valid_assigned_ether_addr(mac_addr)) {
10107                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10108                 return;
10109         }
10110
10111         /* Flags: 0x3 updates port address */
10112         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10113 }
10114
10115 static int
10116 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10117 {
10118         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10119         struct rte_eth_dev_data *dev_data = pf->dev_data;
10120         uint32_t frame_size = mtu + ETHER_HDR_LEN
10121                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10122         int ret = 0;
10123
10124         /* check if mtu is within the allowed range */
10125         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10126                 return -EINVAL;
10127
10128         /* mtu setting is forbidden if port is start */
10129         if (dev_data->dev_started) {
10130                 PMD_DRV_LOG(ERR,
10131                             "port %d must be stopped before configuration\n",
10132                             dev_data->port_id);
10133                 return -EBUSY;
10134         }
10135
10136         if (frame_size > ETHER_MAX_LEN)
10137                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10138         else
10139                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10140
10141         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10142
10143         return ret;
10144 }
10145
10146 /* Restore ethertype filter */
10147 static void
10148 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10149 {
10150         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10151         struct i40e_ethertype_filter_list
10152                 *ethertype_list = &pf->ethertype.ethertype_list;
10153         struct i40e_ethertype_filter *f;
10154         struct i40e_control_filter_stats stats;
10155         uint16_t flags;
10156
10157         TAILQ_FOREACH(f, ethertype_list, rules) {
10158                 flags = 0;
10159                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10160                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10161                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10162                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10163                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10164
10165                 memset(&stats, 0, sizeof(stats));
10166                 i40e_aq_add_rem_control_packet_filter(hw,
10167                                             f->input.mac_addr.addr_bytes,
10168                                             f->input.ether_type,
10169                                             flags, pf->main_vsi->seid,
10170                                             f->queue, 1, &stats, NULL);
10171         }
10172         PMD_DRV_LOG(INFO, "Ethertype filter:"
10173                     " mac_etype_used = %u, etype_used = %u,"
10174                     " mac_etype_free = %u, etype_free = %u\n",
10175                     stats.mac_etype_used, stats.etype_used,
10176                     stats.mac_etype_free, stats.etype_free);
10177 }
10178
10179 /* Restore tunnel filter */
10180 static void
10181 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10182 {
10183         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10184         struct i40e_vsi *vsi = pf->main_vsi;
10185         struct i40e_tunnel_filter_list
10186                 *tunnel_list = &pf->tunnel.tunnel_list;
10187         struct i40e_tunnel_filter *f;
10188         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10189
10190         TAILQ_FOREACH(f, tunnel_list, rules) {
10191                 memset(&cld_filter, 0, sizeof(cld_filter));
10192                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10193                 cld_filter.queue_number = f->queue;
10194                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10195         }
10196 }
10197
10198 static void
10199 i40e_filter_restore(struct i40e_pf *pf)
10200 {
10201         i40e_ethertype_filter_restore(pf);
10202         i40e_tunnel_filter_restore(pf);
10203         i40e_fdir_filter_restore(pf);
10204 }