drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61 #include "i40e_pf.h"
  62
  63 /* Maximun number of MAC addresses */
  64 #define I40E_NUM_MACADDR_MAX       64
  65 #define I40E_CLEAR_PXE_WAIT_MS     200
  66
  67 /* Maximun number of capability elements */
  68 #define I40E_MAX_CAP_ELE_NUM       128
  69
  70 /* Wait count and inteval */
  71 #define I40E_CHK_Q_ENA_COUNT       1000
  72 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  73
  74 /* Maximun number of VSI */
  75 #define I40E_MAX_NUM_VSIS          (384UL)
  76
  77 /* Default queue interrupt throttling time in microseconds */
  78 #define I40E_ITR_INDEX_DEFAULT          0
  79 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  80 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA  0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 136
 137 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 138 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 139 static int i40e_dev_configure(struct rte_eth_dev *dev);
 140 static int i40e_dev_start(struct rte_eth_dev *dev);
 141 static void i40e_dev_stop(struct rte_eth_dev *dev);
 142 static void i40e_dev_close(struct rte_eth_dev *dev);
 143 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 148 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 149 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 150                                struct rte_eth_stats *stats);
 151 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 152 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 153                                             uint16_t queue_id,
 154                                             uint8_t stat_idx,
 155                                             uint8_t is_rx);
 156 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 157                               struct rte_eth_dev_info *dev_info);
 158 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 159                                 uint16_t vlan_id,
 160                                 int on);
 161 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 162 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 163 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 164                                       uint16_t queue,
 165                                       int on);
 166 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 167 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 168 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 169 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 170                               struct rte_eth_fc_conf *fc_conf);
 171 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 172                               struct rte_eth_fc_conf *fc_conf);
 173 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 174                                        struct rte_eth_pfc_conf *pfc_conf);
 175 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 176                           struct ether_addr *mac_addr,
 177                           uint32_t index,
 178                           uint32_t pool);
 179 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 180 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 181                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 182                                     uint16_t reta_size);
 183 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 184                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 185                                    uint16_t reta_size);
 186
 187 static int i40e_get_cap(struct i40e_hw *hw);
 188 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 189 static int i40e_pf_setup(struct i40e_pf *pf);
 190 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 191 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 192 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 193                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 194 static void i40e_stat_update_48(struct i40e_hw *hw,
 195                                uint32_t hireg,
 196                                uint32_t loreg,
 197                                bool offset_loaded,
 198                                uint64_t *offset,
 199                                uint64_t *stat);
 200 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 201 static void i40e_dev_interrupt_handler(
 202                 __rte_unused struct rte_intr_handle *handle, void *param);
 203 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 204                                 uint32_t base, uint32_t num);
 205 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 206 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 207                         uint32_t base);
 208 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 209                         uint16_t num);
 210 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 211 static int i40e_veb_release(struct i40e_veb *veb);
 212 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 213                                                 struct i40e_vsi *vsi);
 214 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 215 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 216 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 217                                              struct i40e_macvlan_filter *mv_f,
 218                                              int num,
 219                                              struct ether_addr *addr);
 220 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 221                                              struct i40e_macvlan_filter *mv_f,
 222                                              int num,
 223                                              uint16_t vlan);
 224 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 225 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 226                                     struct rte_eth_rss_conf *rss_conf);
 227 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 228                                       struct rte_eth_rss_conf *rss_conf);
 229 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 230                                 struct rte_eth_udp_tunnel *udp_tunnel);
 231 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 232                                 struct rte_eth_udp_tunnel *udp_tunnel);
 233 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 234                         struct rte_eth_ethertype_filter *filter,
 235                         bool add);
 236 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 240                                 enum rte_filter_type filter_type,
 241                                 enum rte_filter_op filter_op,
 242                                 void *arg);
 243 static void i40e_configure_registers(struct i40e_hw *hw);
 244 static void i40e_hw_init(struct i40e_hw *hw);
 245 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 246 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 247                         struct rte_eth_mirror_conf *mirror_conf,
 248                         uint8_t sw_id, uint8_t on);
 249 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 250
 251 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 252 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 253 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 254                                            struct timespec *timestamp,
 255                                            uint32_t flags);
 256 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 257                                            struct timespec *timestamp);
 258
 259 static const struct rte_pci_id pci_id_i40e_map[] = {
 260 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 261 #include "rte_pci_dev_ids.h"
 262 { .vendor_id = 0, /* sentinel */ },
 263 };
 264
 265 static const struct eth_dev_ops i40e_eth_dev_ops = {
 266         .dev_configure                = i40e_dev_configure,
 267         .dev_start                    = i40e_dev_start,
 268         .dev_stop                     = i40e_dev_stop,
 269         .dev_close                    = i40e_dev_close,
 270         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 271         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 272         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 273         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 274         .dev_set_link_up              = i40e_dev_set_link_up,
 275         .dev_set_link_down            = i40e_dev_set_link_down,
 276         .link_update                  = i40e_dev_link_update,
 277         .stats_get                    = i40e_dev_stats_get,
 278         .stats_reset                  = i40e_dev_stats_reset,
 279         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 280         .dev_infos_get                = i40e_dev_info_get,
 281         .vlan_filter_set              = i40e_vlan_filter_set,
 282         .vlan_tpid_set                = i40e_vlan_tpid_set,
 283         .vlan_offload_set             = i40e_vlan_offload_set,
 284         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 285         .vlan_pvid_set                = i40e_vlan_pvid_set,
 286         .rx_queue_start               = i40e_dev_rx_queue_start,
 287         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 288         .tx_queue_start               = i40e_dev_tx_queue_start,
 289         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 290         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 291         .rx_queue_release             = i40e_dev_rx_queue_release,
 292         .rx_queue_count               = i40e_dev_rx_queue_count,
 293         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 294         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 295         .tx_queue_release             = i40e_dev_tx_queue_release,
 296         .dev_led_on                   = i40e_dev_led_on,
 297         .dev_led_off                  = i40e_dev_led_off,
 298         .flow_ctrl_get                = i40e_flow_ctrl_get,
 299         .flow_ctrl_set                = i40e_flow_ctrl_set,
 300         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 301         .mac_addr_add                 = i40e_macaddr_add,
 302         .mac_addr_remove              = i40e_macaddr_remove,
 303         .reta_update                  = i40e_dev_rss_reta_update,
 304         .reta_query                   = i40e_dev_rss_reta_query,
 305         .rss_hash_update              = i40e_dev_rss_hash_update,
 306         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 307         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 308         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 309         .filter_ctrl                  = i40e_dev_filter_ctrl,
 310         .mirror_rule_set              = i40e_mirror_rule_set,
 311         .mirror_rule_reset            = i40e_mirror_rule_reset,
 312         .timesync_enable              = i40e_timesync_enable,
 313         .timesync_disable             = i40e_timesync_disable,
 314         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 315         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 316 };
 317
 318 static struct eth_driver rte_i40e_pmd = {
 319         .pci_drv = {
 320                 .name = "rte_i40e_pmd",
 321                 .id_table = pci_id_i40e_map,
 322                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 323                         RTE_PCI_DRV_DETACHABLE,
 324         },
 325         .eth_dev_init = eth_i40e_dev_init,
 326         .eth_dev_uninit = eth_i40e_dev_uninit,
 327         .dev_private_size = sizeof(struct i40e_adapter),
 328 };
 329
 330 static inline int
 331 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 332                                      struct rte_eth_link *link)
 333 {
 334         struct rte_eth_link *dst = link;
 335         struct rte_eth_link *src = &(dev->data->dev_link);
 336
 337         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 338                                         *(uint64_t *)src) == 0)
 339                 return -1;
 340
 341         return 0;
 342 }
 343
 344 static inline int
 345 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 346                                       struct rte_eth_link *link)
 347 {
 348         struct rte_eth_link *dst = &(dev->data->dev_link);
 349         struct rte_eth_link *src = link;
 350
 351         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 352                                         *(uint64_t *)src) == 0)
 353                 return -1;
 354
 355         return 0;
 356 }
 357
 358 /*
 359  * Driver initialization routine.
 360  * Invoked once at EAL init time.
 361  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 362  */
 363 static int
 364 rte_i40e_pmd_init(const char *name __rte_unused,
 365                   const char *params __rte_unused)
 366 {
 367         PMD_INIT_FUNC_TRACE();
 368         rte_eth_driver_register(&rte_i40e_pmd);
 369
 370         return 0;
 371 }
 372
 373 static struct rte_driver rte_i40e_driver = {
 374         .type = PMD_PDEV,
 375         .init = rte_i40e_pmd_init,
 376 };
 377
 378 PMD_REGISTER_DRIVER(rte_i40e_driver);
 379
 380 /*
 381  * Initialize registers for flexible payload, which should be set by NVM.
 382  * This should be removed from code once it is fixed in NVM.
 383  */
 384 #ifndef I40E_GLQF_ORT
 385 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 386 #endif
 387 #ifndef I40E_GLQF_PIT
 388 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 389 #endif
 390
 391 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 392 {
 393         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 394         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 395         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 396         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 397         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 398         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 399         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 400         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 401         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 402         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 403
 404         /* GLQF_PIT Registers */
 405         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 406         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 407 }
 408
 409 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 410
 411 /*
 412  * Add a ethertype filter to drop all flow control frames transmitted
 413  * from VSIs.
 414 */
 415 static void
 416 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 417 {
 418         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 419         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 420                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 421                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 422         int ret;
 423
 424         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 425                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 426                                 pf->main_vsi_seid, 0,
 427                                 TRUE, NULL, NULL);
 428         if (ret)
 429                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 430                                   " frames from VSIs.");
 431 }
 432
 433 static int
 434 eth_i40e_dev_init(struct rte_eth_dev *dev)
 435 {
 436         struct rte_pci_device *pci_dev;
 437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 439         struct i40e_vsi *vsi;
 440         int ret;
 441         uint32_t len;
 442         uint8_t aq_fail = 0;
 443
 444         PMD_INIT_FUNC_TRACE();
 445
 446         dev->dev_ops = &i40e_eth_dev_ops;
 447         dev->rx_pkt_burst = i40e_recv_pkts;
 448         dev->tx_pkt_burst = i40e_xmit_pkts;
 449
 450         /* for secondary processes, we don't initialise any further as primary
 451          * has already done this work. Only check we don't need a different
 452          * RX function */
 453         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 454                 i40e_set_rx_function(dev);
 455                 i40e_set_tx_function(dev);
 456                 return 0;
 457         }
 458         pci_dev = dev->pci_dev;
 459         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 460         pf->adapter->eth_dev = dev;
 461         pf->dev_data = dev->data;
 462
 463         hw->back = I40E_PF_TO_ADAPTER(pf);
 464         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 465         if (!hw->hw_addr) {
 466                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 467                              "as address is NULL");
 468                 return -ENODEV;
 469         }
 470
 471         hw->vendor_id = pci_dev->id.vendor_id;
 472         hw->device_id = pci_dev->id.device_id;
 473         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 474         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 475         hw->bus.device = pci_dev->addr.devid;
 476         hw->bus.func = pci_dev->addr.function;
 477         hw->adapter_stopped = 0;
 478
 479         /* Make sure all is clean before doing PF reset */
 480         i40e_clear_hw(hw);
 481
 482         /* Initialize the hardware */
 483         i40e_hw_init(hw);
 484
 485         /* Reset here to make sure all is clean for each PF */
 486         ret = i40e_pf_reset(hw);
 487         if (ret) {
 488                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 489                 return ret;
 490         }
 491
 492         /* Initialize the shared code (base driver) */
 493         ret = i40e_init_shared_code(hw);
 494         if (ret) {
 495                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 496                 return ret;
 497         }
 498
 499         /*
 500          * To work around the NVM issue,initialize registers
 501          * for flexible payload by software.
 502          * It should be removed once issues are fixed in NVM.
 503          */
 504         i40e_flex_payload_reg_init(hw);
 505
 506         /* Initialize the parameters for adminq */
 507         i40e_init_adminq_parameter(hw);
 508         ret = i40e_init_adminq(hw);
 509         if (ret != I40E_SUCCESS) {
 510                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 511                 return -EIO;
 512         }
 513         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 514                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 515                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 516                      ((hw->nvm.version >> 12) & 0xf),
 517                      ((hw->nvm.version >> 4) & 0xff),
 518                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 519
 520         /* Disable LLDP */
 521         ret = i40e_aq_stop_lldp(hw, true, NULL);
 522         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 523                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 524
 525         /* Clear PXE mode */
 526         i40e_clear_pxe_mode(hw);
 527
 528         /*
 529          * On X710, performance number is far from the expectation on recent
 530          * firmware versions. The fix for this issue may not be integrated in
 531          * the following firmware version. So the workaround in software driver
 532          * is needed. It needs to modify the initial values of 3 internal only
 533          * registers. Note that the workaround can be removed when it is fixed
 534          * in firmware in the future.
 535          */
 536         i40e_configure_registers(hw);
 537
 538         /* Get hw capabilities */
 539         ret = i40e_get_cap(hw);
 540         if (ret != I40E_SUCCESS) {
 541                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 542                 goto err_get_capabilities;
 543         }
 544
 545         /* Initialize parameters for PF */
 546         ret = i40e_pf_parameter_init(dev);
 547         if (ret != 0) {
 548                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 549                 goto err_parameter_init;
 550         }
 551
 552         /* Initialize the queue management */
 553         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 554         if (ret < 0) {
 555                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 556                 goto err_qp_pool_init;
 557         }
 558         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 559                                 hw->func_caps.num_msix_vectors - 1);
 560         if (ret < 0) {
 561                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 562                 goto err_msix_pool_init;
 563         }
 564
 565         /* Initialize lan hmc */
 566         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 567                                 hw->func_caps.num_rx_qp, 0, 0);
 568         if (ret != I40E_SUCCESS) {
 569                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 570                 goto err_init_lan_hmc;
 571         }
 572
 573         /* Configure lan hmc */
 574         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 575         if (ret != I40E_SUCCESS) {
 576                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 577                 goto err_configure_lan_hmc;
 578         }
 579
 580         /* Get and check the mac address */
 581         i40e_get_mac_addr(hw, hw->mac.addr);
 582         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 583                 PMD_INIT_LOG(ERR, "mac address is not valid");
 584                 ret = -EIO;
 585                 goto err_get_mac_addr;
 586         }
 587         /* Copy the permanent MAC address */
 588         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 589                         (struct ether_addr *) hw->mac.perm_addr);
 590
 591         /* Disable flow control */
 592         hw->fc.requested_mode = I40E_FC_NONE;
 593         i40e_set_fc(hw, &aq_fail, TRUE);
 594
 595         /* PF setup, which includes VSI setup */
 596         ret = i40e_pf_setup(pf);
 597         if (ret) {
 598                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 599                 goto err_setup_pf_switch;
 600         }
 601
 602         vsi = pf->main_vsi;
 603
 604         /* Disable double vlan by default */
 605         i40e_vsi_config_double_vlan(vsi, FALSE);
 606
 607         if (!vsi->max_macaddrs)
 608                 len = ETHER_ADDR_LEN;
 609         else
 610                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 611
 612         /* Should be after VSI initialized */
 613         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 614         if (!dev->data->mac_addrs) {
 615                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 616                                         "for storing mac address");
 617                 goto err_mac_alloc;
 618         }
 619         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 620                                         &dev->data->mac_addrs[0]);
 621
 622         /* initialize pf host driver to setup SRIOV resource if applicable */
 623         i40e_pf_host_init(dev);
 624
 625         /* register callback func to eal lib */
 626         rte_intr_callback_register(&(pci_dev->intr_handle),
 627                 i40e_dev_interrupt_handler, (void *)dev);
 628
 629         /* configure and enable device interrupt */
 630         i40e_pf_config_irq0(hw);
 631         i40e_pf_enable_irq0(hw);
 632
 633         /* enable uio intr after callback register */
 634         rte_intr_enable(&(pci_dev->intr_handle));
 635         /*
 636          * Add an ethertype filter to drop all flow control frames transmitted
 637          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 638          * frames to wire.
 639          */
 640         i40e_add_tx_flow_control_drop_filter(pf);
 641
 642         /* initialize mirror rule list */
 643         TAILQ_INIT(&pf->mirror_list);
 644
 645         return 0;
 646
 647 err_mac_alloc:
 648         i40e_vsi_release(pf->main_vsi);
 649 err_setup_pf_switch:
 650 err_get_mac_addr:
 651 err_configure_lan_hmc:
 652         (void)i40e_shutdown_lan_hmc(hw);
 653 err_init_lan_hmc:
 654         i40e_res_pool_destroy(&pf->msix_pool);
 655 err_msix_pool_init:
 656         i40e_res_pool_destroy(&pf->qp_pool);
 657 err_qp_pool_init:
 658 err_parameter_init:
 659 err_get_capabilities:
 660         (void)i40e_shutdown_adminq(hw);
 661
 662         return ret;
 663 }
 664
 665 static int
 666 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 667 {
 668         struct rte_pci_device *pci_dev;
 669         struct i40e_hw *hw;
 670         struct i40e_filter_control_settings settings;
 671         int ret;
 672         uint8_t aq_fail = 0;
 673
 674         PMD_INIT_FUNC_TRACE();
 675
 676         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 677                 return 0;
 678
 679         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 680         pci_dev = dev->pci_dev;
 681
 682         if (hw->adapter_stopped == 0)
 683                 i40e_dev_close(dev);
 684
 685         dev->dev_ops = NULL;
 686         dev->rx_pkt_burst = NULL;
 687         dev->tx_pkt_burst = NULL;
 688
 689         /* Disable LLDP */
 690         ret = i40e_aq_stop_lldp(hw, true, NULL);
 691         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 692                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 693
 694         /* Clear PXE mode */
 695         i40e_clear_pxe_mode(hw);
 696
 697         /* Unconfigure filter control */
 698         memset(&settings, 0, sizeof(settings));
 699         ret = i40e_set_filter_control(hw, &settings);
 700         if (ret)
 701                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 702                                         ret);
 703
 704         /* Disable flow control */
 705         hw->fc.requested_mode = I40E_FC_NONE;
 706         i40e_set_fc(hw, &aq_fail, TRUE);
 707
 708         /* uninitialize pf host driver */
 709         i40e_pf_host_uninit(dev);
 710
 711         rte_free(dev->data->mac_addrs);
 712         dev->data->mac_addrs = NULL;
 713
 714         /* disable uio intr before callback unregister */
 715         rte_intr_disable(&(pci_dev->intr_handle));
 716
 717         /* register callback func to eal lib */
 718         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 719                 i40e_dev_interrupt_handler, (void *)dev);
 720
 721         return 0;
 722 }
 723
 724 static int
 725 i40e_dev_configure(struct rte_eth_dev *dev)
 726 {
 727         struct i40e_adapter *ad =
 728                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 730         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 731         int ret;
 732
 733         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 734          * bulk allocation or vector Rx preconditions we will reset it.
 735          */
 736         ad->rx_bulk_alloc_allowed = true;
 737         ad->rx_vec_allowed = true;
 738         ad->tx_simple_allowed = true;
 739         ad->tx_vec_allowed = true;
 740
 741         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 742                 ret = i40e_fdir_setup(pf);
 743                 if (ret != I40E_SUCCESS) {
 744                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 745                         return -ENOTSUP;
 746                 }
 747                 ret = i40e_fdir_configure(dev);
 748                 if (ret < 0) {
 749                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 750                         goto err;
 751                 }
 752         } else
 753                 i40e_fdir_teardown(pf);
 754
 755         ret = i40e_dev_init_vlan(dev);
 756         if (ret < 0)
 757                 goto err;
 758
 759         /* VMDQ setup.
 760          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 761          *  RSS setting have different requirements.
 762          *  General PMD driver call sequence are NIC init, configure,
 763          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 764          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 765          *  applicable. So, VMDQ setting has to be done before
 766          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 767          *  For RSS setting, it will try to calculate actual configured RX queue
 768          *  number, which will be available after rx_queue_setup(). dev_start()
 769          *  function is good to place RSS setup.
 770          */
 771         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 772                 ret = i40e_vmdq_setup(dev);
 773                 if (ret)
 774                         goto err;
 775         }
 776         return 0;
 777 err:
 778         i40e_fdir_teardown(pf);
 779         return ret;
 780 }
 781
 782 void
 783 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 784 {
 785         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 786         uint16_t msix_vect = vsi->msix_intr;
 787         uint16_t i;
 788
 789         for (i = 0; i < vsi->nb_qps; i++) {
 790                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 791                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 792                 rte_wmb();
 793         }
 794
 795         if (vsi->type != I40E_VSI_SRIOV) {
 796                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 797                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 798                                 msix_vect - 1), 0);
 799         } else {
 800                 uint32_t reg;
 801                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 802                         vsi->user_param + (msix_vect - 1);
 803
 804                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 805         }
 806         I40E_WRITE_FLUSH(hw);
 807 }
 808
 809 static inline uint16_t
 810 i40e_calc_itr_interval(int16_t interval)
 811 {
 812         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 813                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 814
 815         /* Convert to hardware count, as writing each 1 represents 2 us */
 816         return (interval/2);
 817 }
 818
 819 void
 820 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 821 {
 822         uint32_t val;
 823         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 824         uint16_t msix_vect = vsi->msix_intr;
 825         int i;
 826
 827         for (i = 0; i < vsi->nb_qps; i++)
 828                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 829
 830         /* Bind all RX queues to allocated MSIX interrupt */
 831         for (i = 0; i < vsi->nb_qps; i++) {
 832                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 833                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 834                         ((vsi->base_queue + i + 1) <<
 835                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 836                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 837                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 838
 839                 if (i == vsi->nb_qps - 1)
 840                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 841                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 842         }
 843
 844         /* Write first RX queue to Link list register as the head element */
 845         if (vsi->type != I40E_VSI_SRIOV) {
 846                 uint16_t interval =
 847                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 848
 849                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 850                                                 (vsi->base_queue <<
 851                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 852                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 853
 854                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 855                                                 msix_vect - 1), interval);
 856
 857 #ifndef I40E_GLINT_CTL
 858 #define I40E_GLINT_CTL                     0x0003F800
 859 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 860 #endif
 861                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 862                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 863                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 864         } else {
 865                 uint32_t reg;
 866
 867                 /* num_msix_vectors_vf needs to minus irq0 */
 868                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 869                         vsi->user_param + (msix_vect - 1);
 870
 871                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 872                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 873                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 874         }
 875
 876         I40E_WRITE_FLUSH(hw);
 877 }
 878
 879 static void
 880 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 881 {
 882         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 883         uint16_t interval = i40e_calc_itr_interval(\
 884                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 885
 886         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 887                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 888                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 889                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 890                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 891 }
 892
 893 static void
 894 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 895 {
 896         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 897
 898         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 899 }
 900
 901 static inline uint8_t
 902 i40e_parse_link_speed(uint16_t eth_link_speed)
 903 {
 904         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 905
 906         switch (eth_link_speed) {
 907         case ETH_LINK_SPEED_40G:
 908                 link_speed = I40E_LINK_SPEED_40GB;
 909                 break;
 910         case ETH_LINK_SPEED_20G:
 911                 link_speed = I40E_LINK_SPEED_20GB;
 912                 break;
 913         case ETH_LINK_SPEED_10G:
 914                 link_speed = I40E_LINK_SPEED_10GB;
 915                 break;
 916         case ETH_LINK_SPEED_1000:
 917                 link_speed = I40E_LINK_SPEED_1GB;
 918                 break;
 919         case ETH_LINK_SPEED_100:
 920                 link_speed = I40E_LINK_SPEED_100MB;
 921                 break;
 922         }
 923
 924         return link_speed;
 925 }
 926
 927 static int
 928 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 929 {
 930         enum i40e_status_code status;
 931         struct i40e_aq_get_phy_abilities_resp phy_ab;
 932         struct i40e_aq_set_phy_config phy_conf;
 933         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 934                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 935                         I40E_AQ_PHY_FLAG_LOW_POWER;
 936         const uint8_t advt = I40E_LINK_SPEED_40GB |
 937                         I40E_LINK_SPEED_10GB |
 938                         I40E_LINK_SPEED_1GB |
 939                         I40E_LINK_SPEED_100MB;
 940         int ret = -ENOTSUP;
 941
 942         /* Skip it on 40G interfaces, as a workaround for the link issue */
 943         if (i40e_is_40G_device(hw->device_id))
 944                 return I40E_SUCCESS;
 945
 946         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 947                                               NULL);
 948         if (status)
 949                 return ret;
 950
 951         memset(&phy_conf, 0, sizeof(phy_conf));
 952
 953         /* bits 0-2 use the values from get_phy_abilities_resp */
 954         abilities &= ~mask;
 955         abilities |= phy_ab.abilities & mask;
 956
 957         /* update ablities and speed */
 958         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 959                 phy_conf.link_speed = advt;
 960         else
 961                 phy_conf.link_speed = force_speed;
 962
 963         phy_conf.abilities = abilities;
 964
 965         /* use get_phy_abilities_resp value for the rest */
 966         phy_conf.phy_type = phy_ab.phy_type;
 967         phy_conf.eee_capability = phy_ab.eee_capability;
 968         phy_conf.eeer = phy_ab.eeer_val;
 969         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 970
 971         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 972                     phy_ab.abilities, phy_ab.link_speed);
 973         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 974                     phy_conf.abilities, phy_conf.link_speed);
 975
 976         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 977         if (status)
 978                 return ret;
 979
 980         return I40E_SUCCESS;
 981 }
 982
 983 static int
 984 i40e_apply_link_speed(struct rte_eth_dev *dev)
 985 {
 986         uint8_t speed;
 987         uint8_t abilities = 0;
 988         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 989         struct rte_eth_conf *conf = &dev->data->dev_conf;
 990
 991         speed = i40e_parse_link_speed(conf->link_speed);
 992         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 993         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 994                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 995         else
 996                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 997
 998         return i40e_phy_conf_link(hw, abilities, speed);
 999 }
1000
1001 static int
1002 i40e_dev_start(struct rte_eth_dev *dev)
1003 {
1004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         struct i40e_vsi *main_vsi = pf->main_vsi;
1007         int ret, i;
1008
1009         hw->adapter_stopped = 0;
1010
1011         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1012                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1013                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1014                              dev->data->dev_conf.link_duplex,
1015                              dev->data->port_id);
1016                 return -EINVAL;
1017         }
1018
1019         /* Initialize VSI */
1020         ret = i40e_dev_rxtx_init(pf);
1021         if (ret != I40E_SUCCESS) {
1022                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1023                 goto err_up;
1024         }
1025
1026         /* Map queues with MSIX interrupt */
1027         i40e_vsi_queues_bind_intr(main_vsi);
1028         i40e_vsi_enable_queues_intr(main_vsi);
1029
1030         /* Map VMDQ VSI queues with MSIX interrupt */
1031         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1032                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1033                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1034         }
1035
1036         /* enable FDIR MSIX interrupt */
1037         if (pf->fdir.fdir_vsi) {
1038                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1039                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1040         }
1041
1042         /* Enable all queues which have been configured */
1043         ret = i40e_dev_switch_queues(pf, TRUE);
1044         if (ret != I40E_SUCCESS) {
1045                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1046                 goto err_up;
1047         }
1048
1049         /* Enable receiving broadcast packets */
1050         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1051         if (ret != I40E_SUCCESS)
1052                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1053
1054         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1055                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1056                                                 true, NULL);
1057                 if (ret != I40E_SUCCESS)
1058                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1059         }
1060
1061         /* Apply link configure */
1062         ret = i40e_apply_link_speed(dev);
1063         if (I40E_SUCCESS != ret) {
1064                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1065                 goto err_up;
1066         }
1067
1068         return I40E_SUCCESS;
1069
1070 err_up:
1071         i40e_dev_switch_queues(pf, FALSE);
1072         i40e_dev_clear_queues(dev);
1073
1074         return ret;
1075 }
1076
1077 static void
1078 i40e_dev_stop(struct rte_eth_dev *dev)
1079 {
1080         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1081         struct i40e_vsi *main_vsi = pf->main_vsi;
1082         struct i40e_mirror_rule *p_mirror;
1083         int i;
1084
1085         /* Disable all queues */
1086         i40e_dev_switch_queues(pf, FALSE);
1087
1088         /* un-map queues with interrupt registers */
1089         i40e_vsi_disable_queues_intr(main_vsi);
1090         i40e_vsi_queues_unbind_intr(main_vsi);
1091
1092         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1093                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1094                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1095         }
1096
1097         if (pf->fdir.fdir_vsi) {
1098                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1099                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1100         }
1101         /* Clear all queues and release memory */
1102         i40e_dev_clear_queues(dev);
1103
1104         /* Set link down */
1105         i40e_dev_set_link_down(dev);
1106
1107         /* Remove all mirror rules */
1108         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1109                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1110                 rte_free(p_mirror);
1111         }
1112         pf->nb_mirror_rule = 0;
1113
1114 }
1115
1116 static void
1117 i40e_dev_close(struct rte_eth_dev *dev)
1118 {
1119         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1120         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1121         uint32_t reg;
1122         int i;
1123
1124         PMD_INIT_FUNC_TRACE();
1125
1126         i40e_dev_stop(dev);
1127         hw->adapter_stopped = 1;
1128         i40e_dev_free_queues(dev);
1129
1130         /* Disable interrupt */
1131         i40e_pf_disable_irq0(hw);
1132         rte_intr_disable(&(dev->pci_dev->intr_handle));
1133
1134         /* shutdown and destroy the HMC */
1135         i40e_shutdown_lan_hmc(hw);
1136
1137         /* release all the existing VSIs and VEBs */
1138         i40e_fdir_teardown(pf);
1139         i40e_vsi_release(pf->main_vsi);
1140
1141         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1142                 i40e_vsi_release(pf->vmdq[i].vsi);
1143                 pf->vmdq[i].vsi = NULL;
1144         }
1145
1146         rte_free(pf->vmdq);
1147         pf->vmdq = NULL;
1148
1149         /* shutdown the adminq */
1150         i40e_aq_queue_shutdown(hw, true);
1151         i40e_shutdown_adminq(hw);
1152
1153         i40e_res_pool_destroy(&pf->qp_pool);
1154         i40e_res_pool_destroy(&pf->msix_pool);
1155
1156         /* force a PF reset to clean anything leftover */
1157         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1158         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1159                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1160         I40E_WRITE_FLUSH(hw);
1161 }
1162
1163 static void
1164 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1165 {
1166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168         struct i40e_vsi *vsi = pf->main_vsi;
1169         int status;
1170
1171         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1172                                                         true, NULL);
1173         if (status != I40E_SUCCESS)
1174                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1175
1176         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1177                                                         TRUE, NULL);
1178         if (status != I40E_SUCCESS)
1179                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1180
1181 }
1182
1183 static void
1184 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1185 {
1186         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1188         struct i40e_vsi *vsi = pf->main_vsi;
1189         int status;
1190
1191         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1192                                                         false, NULL);
1193         if (status != I40E_SUCCESS)
1194                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1195
1196         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1197                                                         false, NULL);
1198         if (status != I40E_SUCCESS)
1199                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1200 }
1201
1202 static void
1203 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1204 {
1205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207         struct i40e_vsi *vsi = pf->main_vsi;
1208         int ret;
1209
1210         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1211         if (ret != I40E_SUCCESS)
1212                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1213 }
1214
1215 static void
1216 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1217 {
1218         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1219         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1220         struct i40e_vsi *vsi = pf->main_vsi;
1221         int ret;
1222
1223         if (dev->data->promiscuous == 1)
1224                 return; /* must remain in all_multicast mode */
1225
1226         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1227                                 vsi->seid, FALSE, NULL);
1228         if (ret != I40E_SUCCESS)
1229                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1230 }
1231
1232 /*
1233  * Set device link up.
1234  */
1235 static int
1236 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1237 {
1238         /* re-apply link speed setting */
1239         return i40e_apply_link_speed(dev);
1240 }
1241
1242 /*
1243  * Set device link down.
1244  */
1245 static int
1246 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1247 {
1248         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1249         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1250         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251
1252         return i40e_phy_conf_link(hw, abilities, speed);
1253 }
1254
1255 int
1256 i40e_dev_link_update(struct rte_eth_dev *dev,
1257                      int wait_to_complete)
1258 {
1259 #define CHECK_INTERVAL 100  /* 100ms */
1260 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1261         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1262         struct i40e_link_status link_status;
1263         struct rte_eth_link link, old;
1264         int status;
1265         unsigned rep_cnt = MAX_REPEAT_TIME;
1266
1267         memset(&link, 0, sizeof(link));
1268         memset(&old, 0, sizeof(old));
1269         memset(&link_status, 0, sizeof(link_status));
1270         rte_i40e_dev_atomic_read_link_status(dev, &old);
1271
1272         do {
1273                 /* Get link status information from hardware */
1274                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1275                 if (status != I40E_SUCCESS) {
1276                         link.link_speed = ETH_LINK_SPEED_100;
1277                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1278                         PMD_DRV_LOG(ERR, "Failed to get link info");
1279                         goto out;
1280                 }
1281
1282                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1283                 if (!wait_to_complete)
1284                         break;
1285
1286                 rte_delay_ms(CHECK_INTERVAL);
1287         } while (!link.link_status && rep_cnt--);
1288
1289         if (!link.link_status)
1290                 goto out;
1291
1292         /* i40e uses full duplex only */
1293         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1294
1295         /* Parse the link status */
1296         switch (link_status.link_speed) {
1297         case I40E_LINK_SPEED_100MB:
1298                 link.link_speed = ETH_LINK_SPEED_100;
1299                 break;
1300         case I40E_LINK_SPEED_1GB:
1301                 link.link_speed = ETH_LINK_SPEED_1000;
1302                 break;
1303         case I40E_LINK_SPEED_10GB:
1304                 link.link_speed = ETH_LINK_SPEED_10G;
1305                 break;
1306         case I40E_LINK_SPEED_20GB:
1307                 link.link_speed = ETH_LINK_SPEED_20G;
1308                 break;
1309         case I40E_LINK_SPEED_40GB:
1310                 link.link_speed = ETH_LINK_SPEED_40G;
1311                 break;
1312         default:
1313                 link.link_speed = ETH_LINK_SPEED_100;
1314                 break;
1315         }
1316
1317 out:
1318         rte_i40e_dev_atomic_write_link_status(dev, &link);
1319         if (link.link_status == old.link_status)
1320                 return -1;
1321
1322         return 0;
1323 }
1324
1325 /* Get all the statistics of a VSI */
1326 void
1327 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1328 {
1329         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1330         struct i40e_eth_stats *nes = &vsi->eth_stats;
1331         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1332         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1333
1334         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1335                             vsi->offset_loaded, &oes->rx_bytes,
1336                             &nes->rx_bytes);
1337         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1338                             vsi->offset_loaded, &oes->rx_unicast,
1339                             &nes->rx_unicast);
1340         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1341                             vsi->offset_loaded, &oes->rx_multicast,
1342                             &nes->rx_multicast);
1343         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1344                             vsi->offset_loaded, &oes->rx_broadcast,
1345                             &nes->rx_broadcast);
1346         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1347                             &oes->rx_discards, &nes->rx_discards);
1348         /* GLV_REPC not supported */
1349         /* GLV_RMPC not supported */
1350         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1351                             &oes->rx_unknown_protocol,
1352                             &nes->rx_unknown_protocol);
1353         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1354                             vsi->offset_loaded, &oes->tx_bytes,
1355                             &nes->tx_bytes);
1356         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1357                             vsi->offset_loaded, &oes->tx_unicast,
1358                             &nes->tx_unicast);
1359         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1360                             vsi->offset_loaded, &oes->tx_multicast,
1361                             &nes->tx_multicast);
1362         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1363                             vsi->offset_loaded,  &oes->tx_broadcast,
1364                             &nes->tx_broadcast);
1365         /* GLV_TDPC not supported */
1366         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1367                             &oes->tx_errors, &nes->tx_errors);
1368         vsi->offset_loaded = true;
1369
1370         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1371                     vsi->vsi_id);
1372         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1373         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1374         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1375         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1376         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1377         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1378                     nes->rx_unknown_protocol);
1379         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1380         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1381         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1382         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1383         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1384         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1385         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1386                     vsi->vsi_id);
1387 }
1388
1389 /* Get all statistics of a port */
1390 static void
1391 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1392 {
1393         uint32_t i;
1394         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1397         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1398
1399         /* Get statistics of struct i40e_eth_stats */
1400         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1401                             I40E_GLPRT_GORCL(hw->port),
1402                             pf->offset_loaded, &os->eth.rx_bytes,
1403                             &ns->eth.rx_bytes);
1404         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1405                             I40E_GLPRT_UPRCL(hw->port),
1406                             pf->offset_loaded, &os->eth.rx_unicast,
1407                             &ns->eth.rx_unicast);
1408         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1409                             I40E_GLPRT_MPRCL(hw->port),
1410                             pf->offset_loaded, &os->eth.rx_multicast,
1411                             &ns->eth.rx_multicast);
1412         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1413                             I40E_GLPRT_BPRCL(hw->port),
1414                             pf->offset_loaded, &os->eth.rx_broadcast,
1415                             &ns->eth.rx_broadcast);
1416         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1417                             pf->offset_loaded, &os->eth.rx_discards,
1418                             &ns->eth.rx_discards);
1419         /* GLPRT_REPC not supported */
1420         /* GLPRT_RMPC not supported */
1421         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1422                             pf->offset_loaded,
1423                             &os->eth.rx_unknown_protocol,
1424                             &ns->eth.rx_unknown_protocol);
1425         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1426                             I40E_GLPRT_GOTCL(hw->port),
1427                             pf->offset_loaded, &os->eth.tx_bytes,
1428                             &ns->eth.tx_bytes);
1429         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1430                             I40E_GLPRT_UPTCL(hw->port),
1431                             pf->offset_loaded, &os->eth.tx_unicast,
1432                             &ns->eth.tx_unicast);
1433         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1434                             I40E_GLPRT_MPTCL(hw->port),
1435                             pf->offset_loaded, &os->eth.tx_multicast,
1436                             &ns->eth.tx_multicast);
1437         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1438                             I40E_GLPRT_BPTCL(hw->port),
1439                             pf->offset_loaded, &os->eth.tx_broadcast,
1440                             &ns->eth.tx_broadcast);
1441         /* GLPRT_TEPC not supported */
1442
1443         /* additional port specific stats */
1444         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1445                             pf->offset_loaded, &os->tx_dropped_link_down,
1446                             &ns->tx_dropped_link_down);
1447         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1448                             pf->offset_loaded, &os->crc_errors,
1449                             &ns->crc_errors);
1450         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1451                             pf->offset_loaded, &os->illegal_bytes,
1452                             &ns->illegal_bytes);
1453         /* GLPRT_ERRBC not supported */
1454         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1455                             pf->offset_loaded, &os->mac_local_faults,
1456                             &ns->mac_local_faults);
1457         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1458                             pf->offset_loaded, &os->mac_remote_faults,
1459                             &ns->mac_remote_faults);
1460         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1461                             pf->offset_loaded, &os->rx_length_errors,
1462                             &ns->rx_length_errors);
1463         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1464                             pf->offset_loaded, &os->link_xon_rx,
1465                             &ns->link_xon_rx);
1466         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1467                             pf->offset_loaded, &os->link_xoff_rx,
1468                             &ns->link_xoff_rx);
1469         for (i = 0; i < 8; i++) {
1470                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1471                                     pf->offset_loaded,
1472                                     &os->priority_xon_rx[i],
1473                                     &ns->priority_xon_rx[i]);
1474                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1475                                     pf->offset_loaded,
1476                                     &os->priority_xoff_rx[i],
1477                                     &ns->priority_xoff_rx[i]);
1478         }
1479         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1480                             pf->offset_loaded, &os->link_xon_tx,
1481                             &ns->link_xon_tx);
1482         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1483                             pf->offset_loaded, &os->link_xoff_tx,
1484                             &ns->link_xoff_tx);
1485         for (i = 0; i < 8; i++) {
1486                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1487                                     pf->offset_loaded,
1488                                     &os->priority_xon_tx[i],
1489                                     &ns->priority_xon_tx[i]);
1490                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1491                                     pf->offset_loaded,
1492                                     &os->priority_xoff_tx[i],
1493                                     &ns->priority_xoff_tx[i]);
1494                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1495                                     pf->offset_loaded,
1496                                     &os->priority_xon_2_xoff[i],
1497                                     &ns->priority_xon_2_xoff[i]);
1498         }
1499         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1500                             I40E_GLPRT_PRC64L(hw->port),
1501                             pf->offset_loaded, &os->rx_size_64,
1502                             &ns->rx_size_64);
1503         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1504                             I40E_GLPRT_PRC127L(hw->port),
1505                             pf->offset_loaded, &os->rx_size_127,
1506                             &ns->rx_size_127);
1507         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1508                             I40E_GLPRT_PRC255L(hw->port),
1509                             pf->offset_loaded, &os->rx_size_255,
1510                             &ns->rx_size_255);
1511         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1512                             I40E_GLPRT_PRC511L(hw->port),
1513                             pf->offset_loaded, &os->rx_size_511,
1514                             &ns->rx_size_511);
1515         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1516                             I40E_GLPRT_PRC1023L(hw->port),
1517                             pf->offset_loaded, &os->rx_size_1023,
1518                             &ns->rx_size_1023);
1519         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1520                             I40E_GLPRT_PRC1522L(hw->port),
1521                             pf->offset_loaded, &os->rx_size_1522,
1522                             &ns->rx_size_1522);
1523         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1524                             I40E_GLPRT_PRC9522L(hw->port),
1525                             pf->offset_loaded, &os->rx_size_big,
1526                             &ns->rx_size_big);
1527         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1528                             pf->offset_loaded, &os->rx_undersize,
1529                             &ns->rx_undersize);
1530         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1531                             pf->offset_loaded, &os->rx_fragments,
1532                             &ns->rx_fragments);
1533         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1534                             pf->offset_loaded, &os->rx_oversize,
1535                             &ns->rx_oversize);
1536         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1537                             pf->offset_loaded, &os->rx_jabber,
1538                             &ns->rx_jabber);
1539         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1540                             I40E_GLPRT_PTC64L(hw->port),
1541                             pf->offset_loaded, &os->tx_size_64,
1542                             &ns->tx_size_64);
1543         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1544                             I40E_GLPRT_PTC127L(hw->port),
1545                             pf->offset_loaded, &os->tx_size_127,
1546                             &ns->tx_size_127);
1547         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1548                             I40E_GLPRT_PTC255L(hw->port),
1549                             pf->offset_loaded, &os->tx_size_255,
1550                             &ns->tx_size_255);
1551         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1552                             I40E_GLPRT_PTC511L(hw->port),
1553                             pf->offset_loaded, &os->tx_size_511,
1554                             &ns->tx_size_511);
1555         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1556                             I40E_GLPRT_PTC1023L(hw->port),
1557                             pf->offset_loaded, &os->tx_size_1023,
1558                             &ns->tx_size_1023);
1559         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1560                             I40E_GLPRT_PTC1522L(hw->port),
1561                             pf->offset_loaded, &os->tx_size_1522,
1562                             &ns->tx_size_1522);
1563         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1564                             I40E_GLPRT_PTC9522L(hw->port),
1565                             pf->offset_loaded, &os->tx_size_big,
1566                             &ns->tx_size_big);
1567         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1568                            pf->offset_loaded,
1569                            &os->fd_sb_match, &ns->fd_sb_match);
1570         /* GLPRT_MSPDC not supported */
1571         /* GLPRT_XEC not supported */
1572
1573         pf->offset_loaded = true;
1574
1575         if (pf->main_vsi)
1576                 i40e_update_vsi_stats(pf->main_vsi);
1577
1578         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1579                                                 ns->eth.rx_broadcast;
1580         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1581                                                 ns->eth.tx_broadcast;
1582         stats->ibytes   = ns->eth.rx_bytes;
1583         stats->obytes   = ns->eth.tx_bytes;
1584         stats->oerrors  = ns->eth.tx_errors;
1585         stats->imcasts  = ns->eth.rx_multicast;
1586         stats->fdirmatch = ns->fd_sb_match;
1587
1588         /* Rx Errors */
1589         stats->ibadcrc  = ns->crc_errors;
1590         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1591                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1592         stats->imissed  = ns->eth.rx_discards;
1593         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1594
1595         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1596         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1597         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1598         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1599         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1600         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1601         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1602                     ns->eth.rx_unknown_protocol);
1603         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1604         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1605         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1606         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1607         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1608         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1609
1610         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1611                     ns->tx_dropped_link_down);
1612         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1613         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1614                     ns->illegal_bytes);
1615         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1616         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1617                     ns->mac_local_faults);
1618         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1619                     ns->mac_remote_faults);
1620         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1621                     ns->rx_length_errors);
1622         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1623         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1624         for (i = 0; i < 8; i++) {
1625                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1626                                 i, ns->priority_xon_rx[i]);
1627                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1628                                 i, ns->priority_xoff_rx[i]);
1629         }
1630         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1631         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1632         for (i = 0; i < 8; i++) {
1633                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1634                                 i, ns->priority_xon_tx[i]);
1635                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1636                                 i, ns->priority_xoff_tx[i]);
1637                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1638                                 i, ns->priority_xon_2_xoff[i]);
1639         }
1640         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1641         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1642         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1643         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1644         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1645         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1646         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1647         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1648         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1649         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1650         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1651         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1652         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1653         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1654         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1655         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1656         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1657         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1658         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1659                         ns->mac_short_packet_dropped);
1660         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1661                     ns->checksum_error);
1662         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1663         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1664 }
1665
1666 /* Reset the statistics */
1667 static void
1668 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1669 {
1670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1671
1672         /* It results in reloading the start point of each counter */
1673         pf->offset_loaded = false;
1674 }
1675
1676 static int
1677 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1678                                  __rte_unused uint16_t queue_id,
1679                                  __rte_unused uint8_t stat_idx,
1680                                  __rte_unused uint8_t is_rx)
1681 {
1682         PMD_INIT_FUNC_TRACE();
1683
1684         return -ENOSYS;
1685 }
1686
1687 static void
1688 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1689 {
1690         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1691         struct i40e_vsi *vsi = pf->main_vsi;
1692
1693         dev_info->max_rx_queues = vsi->nb_qps;
1694         dev_info->max_tx_queues = vsi->nb_qps;
1695         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1696         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1697         dev_info->max_mac_addrs = vsi->max_macaddrs;
1698         dev_info->max_vfs = dev->pci_dev->max_vfs;
1699         dev_info->rx_offload_capa =
1700                 DEV_RX_OFFLOAD_VLAN_STRIP |
1701                 DEV_RX_OFFLOAD_QINQ_STRIP |
1702                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1703                 DEV_RX_OFFLOAD_UDP_CKSUM |
1704                 DEV_RX_OFFLOAD_TCP_CKSUM;
1705         dev_info->tx_offload_capa =
1706                 DEV_TX_OFFLOAD_VLAN_INSERT |
1707                 DEV_TX_OFFLOAD_QINQ_INSERT |
1708                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1709                 DEV_TX_OFFLOAD_UDP_CKSUM |
1710                 DEV_TX_OFFLOAD_TCP_CKSUM |
1711                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1712                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1713                 DEV_TX_OFFLOAD_TCP_TSO;
1714         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1715                                                 sizeof(uint32_t);
1716         dev_info->reta_size = pf->hash_lut_size;
1717         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1718
1719         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1720                 .rx_thresh = {
1721                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1722                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1723                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1724                 },
1725                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1726                 .rx_drop_en = 0,
1727         };
1728
1729         dev_info->default_txconf = (struct rte_eth_txconf) {
1730                 .tx_thresh = {
1731                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1732                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1733                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1734                 },
1735                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1736                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1737                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1738                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1739         };
1740
1741         if (pf->flags & I40E_FLAG_VMDQ) {
1742                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1743                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1744                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1745                                                 pf->max_nb_vmdq_vsi;
1746                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1747                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1748                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1749         }
1750 }
1751
1752 static int
1753 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1754 {
1755         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1756         struct i40e_vsi *vsi = pf->main_vsi;
1757         PMD_INIT_FUNC_TRACE();
1758
1759         if (on)
1760                 return i40e_vsi_add_vlan(vsi, vlan_id);
1761         else
1762                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1763 }
1764
1765 static void
1766 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1767                    __rte_unused uint16_t tpid)
1768 {
1769         PMD_INIT_FUNC_TRACE();
1770 }
1771
1772 static void
1773 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1774 {
1775         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1776         struct i40e_vsi *vsi = pf->main_vsi;
1777
1778         if (mask & ETH_VLAN_STRIP_MASK) {
1779                 /* Enable or disable VLAN stripping */
1780                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1781                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1782                 else
1783                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1784         }
1785
1786         if (mask & ETH_VLAN_EXTEND_MASK) {
1787                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1788                         i40e_vsi_config_double_vlan(vsi, TRUE);
1789                 else
1790                         i40e_vsi_config_double_vlan(vsi, FALSE);
1791         }
1792 }
1793
1794 static void
1795 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1796                           __rte_unused uint16_t queue,
1797                           __rte_unused int on)
1798 {
1799         PMD_INIT_FUNC_TRACE();
1800 }
1801
1802 static int
1803 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1804 {
1805         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1806         struct i40e_vsi *vsi = pf->main_vsi;
1807         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1808         struct i40e_vsi_vlan_pvid_info info;
1809
1810         memset(&info, 0, sizeof(info));
1811         info.on = on;
1812         if (info.on)
1813                 info.config.pvid = pvid;
1814         else {
1815                 info.config.reject.tagged =
1816                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1817                 info.config.reject.untagged =
1818                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1819         }
1820
1821         return i40e_vsi_vlan_pvid_set(vsi, &info);
1822 }
1823
1824 static int
1825 i40e_dev_led_on(struct rte_eth_dev *dev)
1826 {
1827         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828         uint32_t mode = i40e_led_get(hw);
1829
1830         if (mode == 0)
1831                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1832
1833         return 0;
1834 }
1835
1836 static int
1837 i40e_dev_led_off(struct rte_eth_dev *dev)
1838 {
1839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         uint32_t mode = i40e_led_get(hw);
1841
1842         if (mode != 0)
1843                 i40e_led_set(hw, 0, false);
1844
1845         return 0;
1846 }
1847
1848 static int
1849 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1850 {
1851         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1853
1854         fc_conf->pause_time = pf->fc_conf.pause_time;
1855         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
1856         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
1857
1858          /* Return current mode according to actual setting*/
1859         switch (hw->fc.current_mode) {
1860         case I40E_FC_FULL:
1861                 fc_conf->mode = RTE_FC_FULL;
1862                 break;
1863         case I40E_FC_TX_PAUSE:
1864                 fc_conf->mode = RTE_FC_TX_PAUSE;
1865                 break;
1866         case I40E_FC_RX_PAUSE:
1867                 fc_conf->mode = RTE_FC_RX_PAUSE;
1868                 break;
1869         case I40E_FC_NONE:
1870         default:
1871                 fc_conf->mode = RTE_FC_NONE;
1872         };
1873
1874         return 0;
1875 }
1876
1877 static int
1878 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1879 {
1880         uint32_t mflcn_reg, fctrl_reg, reg;
1881         uint32_t max_high_water;
1882         uint8_t i, aq_failure;
1883         int err;
1884         struct i40e_hw *hw;
1885         struct i40e_pf *pf;
1886         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
1887                 [RTE_FC_NONE] = I40E_FC_NONE,
1888                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
1889                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
1890                 [RTE_FC_FULL] = I40E_FC_FULL
1891         };
1892
1893         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
1894
1895         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
1896         if ((fc_conf->high_water > max_high_water) ||
1897                         (fc_conf->high_water < fc_conf->low_water)) {
1898                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
1899                         "High_water must <= %d.", max_high_water);
1900                 return -EINVAL;
1901         }
1902
1903         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1905         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
1906
1907         pf->fc_conf.pause_time = fc_conf->pause_time;
1908         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
1909         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
1910
1911         PMD_INIT_FUNC_TRACE();
1912
1913         /* All the link flow control related enable/disable register
1914          * configuration is handle by the F/W
1915          */
1916         err = i40e_set_fc(hw, &aq_failure, true);
1917         if (err < 0)
1918                 return -ENOSYS;
1919
1920         if (i40e_is_40G_device(hw->device_id)) {
1921                 /* Configure flow control refresh threshold,
1922                  * the value for stat_tx_pause_refresh_timer[8]
1923                  * is used for global pause operation.
1924                  */
1925
1926                 I40E_WRITE_REG(hw,
1927                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
1928                                pf->fc_conf.pause_time);
1929
1930                 /* configure the timer value included in transmitted pause
1931                  * frame,
1932                  * the value for stat_tx_pause_quanta[8] is used for global
1933                  * pause operation
1934                  */
1935                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
1936                                pf->fc_conf.pause_time);
1937
1938                 fctrl_reg = I40E_READ_REG(hw,
1939                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
1940
1941                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1942                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
1943                 else
1944                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
1945
1946                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
1947                                fctrl_reg);
1948         } else {
1949                 /* Configure pause time (2 TCs per register) */
1950                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
1951                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
1952                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
1953
1954                 /* Configure flow control refresh threshold value */
1955                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
1956                                pf->fc_conf.pause_time / 2);
1957
1958                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
1959
1960                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
1961                  *depending on configuration
1962                  */
1963                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
1964                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
1965                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
1966                 } else {
1967                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
1968                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
1969                 }
1970
1971                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
1972         }
1973
1974         /* config the water marker both based on the packets and bytes */
1975         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
1976                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
1977                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
1978         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
1979                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
1980                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
1981         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
1982                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
1983                        << I40E_KILOSHIFT);
1984         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
1985                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
1986                        << I40E_KILOSHIFT);
1987
1988         I40E_WRITE_FLUSH(hw);
1989
1990         return 0;
1991 }
1992
1993 static int
1994 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1995                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1996 {
1997         PMD_INIT_FUNC_TRACE();
1998
1999         return -ENOSYS;
2000 }
2001
2002 /* Add a MAC address, and update filters */
2003 static void
2004 i40e_macaddr_add(struct rte_eth_dev *dev,
2005                  struct ether_addr *mac_addr,
2006                  __rte_unused uint32_t index,
2007                  uint32_t pool)
2008 {
2009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2010         struct i40e_mac_filter_info mac_filter;
2011         struct i40e_vsi *vsi;
2012         int ret;
2013
2014         /* If VMDQ not enabled or configured, return */
2015         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2016                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2017                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2018                         pool);
2019                 return;
2020         }
2021
2022         if (pool > pf->nb_cfg_vmdq_vsi) {
2023                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2024                                 pool, pf->nb_cfg_vmdq_vsi);
2025                 return;
2026         }
2027
2028         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2029         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2030
2031         if (pool == 0)
2032                 vsi = pf->main_vsi;
2033         else
2034                 vsi = pf->vmdq[pool - 1].vsi;
2035
2036         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2037         if (ret != I40E_SUCCESS) {
2038                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2039                 return;
2040         }
2041 }
2042
2043 /* Remove a MAC address, and update filters */
2044 static void
2045 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2046 {
2047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2048         struct i40e_vsi *vsi;
2049         struct rte_eth_dev_data *data = dev->data;
2050         struct ether_addr *macaddr;
2051         int ret;
2052         uint32_t i;
2053         uint64_t pool_sel;
2054
2055         macaddr = &(data->mac_addrs[index]);
2056
2057         pool_sel = dev->data->mac_pool_sel[index];
2058
2059         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2060                 if (pool_sel & (1ULL << i)) {
2061                         if (i == 0)
2062                                 vsi = pf->main_vsi;
2063                         else {
2064                                 /* No VMDQ pool enabled or configured */
2065                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2066                                         (i > pf->nb_cfg_vmdq_vsi)) {
2067                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2068                                                         "/configured");
2069                                         return;
2070                                 }
2071                                 vsi = pf->vmdq[i - 1].vsi;
2072                         }
2073                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2074
2075                         if (ret) {
2076                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2077                                 return;
2078                         }
2079                 }
2080         }
2081 }
2082
2083 /* Set perfect match or hash match of MAC and VLAN for a VF */
2084 static int
2085 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2086                  struct rte_eth_mac_filter *filter,
2087                  bool add)
2088 {
2089         struct i40e_hw *hw;
2090         struct i40e_mac_filter_info mac_filter;
2091         struct ether_addr old_mac;
2092         struct ether_addr *new_mac;
2093         struct i40e_pf_vf *vf = NULL;
2094         uint16_t vf_id;
2095         int ret;
2096
2097         if (pf == NULL) {
2098                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2099                 return -EINVAL;
2100         }
2101         hw = I40E_PF_TO_HW(pf);
2102
2103         if (filter == NULL) {
2104                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2105                 return -EINVAL;
2106         }
2107
2108         new_mac = &filter->mac_addr;
2109
2110         if (is_zero_ether_addr(new_mac)) {
2111                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2112                 return -EINVAL;
2113         }
2114
2115         vf_id = filter->dst_id;
2116
2117         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2118                 PMD_DRV_LOG(ERR, "Invalid argument.");
2119                 return -EINVAL;
2120         }
2121         vf = &pf->vfs[vf_id];
2122
2123         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2124                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2125                 return -EINVAL;
2126         }
2127
2128         if (add) {
2129                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2130                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2131                                 ETHER_ADDR_LEN);
2132                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2133                                  ETHER_ADDR_LEN);
2134
2135                 mac_filter.filter_type = filter->filter_type;
2136                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2137                 if (ret != I40E_SUCCESS) {
2138                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2139                         return -1;
2140                 }
2141                 ether_addr_copy(new_mac, &pf->dev_addr);
2142         } else {
2143                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2144                                 ETHER_ADDR_LEN);
2145                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2146                 if (ret != I40E_SUCCESS) {
2147                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2148                         return -1;
2149                 }
2150
2151                 /* Clear device address as it has been removed */
2152                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2153                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2154         }
2155
2156         return 0;
2157 }
2158
2159 /* MAC filter handle */
2160 static int
2161 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2162                 void *arg)
2163 {
2164         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2165         struct rte_eth_mac_filter *filter;
2166         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2167         int ret = I40E_NOT_SUPPORTED;
2168
2169         filter = (struct rte_eth_mac_filter *)(arg);
2170
2171         switch (filter_op) {
2172         case RTE_ETH_FILTER_NOP:
2173                 ret = I40E_SUCCESS;
2174                 break;
2175         case RTE_ETH_FILTER_ADD:
2176                 i40e_pf_disable_irq0(hw);
2177                 if (filter->is_vf)
2178                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2179                 i40e_pf_enable_irq0(hw);
2180                 break;
2181         case RTE_ETH_FILTER_DELETE:
2182                 i40e_pf_disable_irq0(hw);
2183                 if (filter->is_vf)
2184                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2185                 i40e_pf_enable_irq0(hw);
2186                 break;
2187         default:
2188                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2189                 ret = I40E_ERR_PARAM;
2190                 break;
2191         }
2192
2193         return ret;
2194 }
2195
2196 static int
2197 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2198                          struct rte_eth_rss_reta_entry64 *reta_conf,
2199                          uint16_t reta_size)
2200 {
2201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2202         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         uint32_t lut, l;
2204         uint16_t i, j, lut_size = pf->hash_lut_size;
2205         uint16_t idx, shift;
2206         uint8_t mask;
2207
2208         if (reta_size != lut_size ||
2209                 reta_size > ETH_RSS_RETA_SIZE_512) {
2210                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2211                         "(%d) doesn't match the number hardware can supported "
2212                                         "(%d)\n", reta_size, lut_size);
2213                 return -EINVAL;
2214         }
2215
2216         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2217                 idx = i / RTE_RETA_GROUP_SIZE;
2218                 shift = i % RTE_RETA_GROUP_SIZE;
2219                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2220                                                 I40E_4_BIT_MASK);
2221                 if (!mask)
2222                         continue;
2223                 if (mask == I40E_4_BIT_MASK)
2224                         l = 0;
2225                 else
2226                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2227                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2228                         if (mask & (0x1 << j))
2229                                 lut |= reta_conf[idx].reta[shift + j] <<
2230                                                         (CHAR_BIT * j);
2231                         else
2232                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2233                 }
2234                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2235         }
2236
2237         return 0;
2238 }
2239
2240 static int
2241 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2242                         struct rte_eth_rss_reta_entry64 *reta_conf,
2243                         uint16_t reta_size)
2244 {
2245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2247         uint32_t lut;
2248         uint16_t i, j, lut_size = pf->hash_lut_size;
2249         uint16_t idx, shift;
2250         uint8_t mask;
2251
2252         if (reta_size != lut_size ||
2253                 reta_size > ETH_RSS_RETA_SIZE_512) {
2254                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2255                         "(%d) doesn't match the number hardware can supported "
2256                                         "(%d)\n", reta_size, lut_size);
2257                 return -EINVAL;
2258         }
2259
2260         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2261                 idx = i / RTE_RETA_GROUP_SIZE;
2262                 shift = i % RTE_RETA_GROUP_SIZE;
2263                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2264                                                 I40E_4_BIT_MASK);
2265                 if (!mask)
2266                         continue;
2267
2268                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2269                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2270                         if (mask & (0x1 << j))
2271                                 reta_conf[idx].reta[shift + j] = ((lut >>
2272                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2273                 }
2274         }
2275
2276         return 0;
2277 }
2278
2279 /**
2280  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2281  * @hw:   pointer to the HW structure
2282  * @mem:  pointer to mem struct to fill out
2283  * @size: size of memory requested
2284  * @alignment: what to align the allocation to
2285  **/
2286 enum i40e_status_code
2287 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2288                         struct i40e_dma_mem *mem,
2289                         u64 size,
2290                         u32 alignment)
2291 {
2292         static uint64_t id = 0;
2293         const struct rte_memzone *mz = NULL;
2294         char z_name[RTE_MEMZONE_NAMESIZE];
2295
2296         if (!mem)
2297                 return I40E_ERR_PARAM;
2298
2299         id++;
2300         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2301 #ifdef RTE_LIBRTE_XEN_DOM0
2302         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2303                                          alignment, RTE_PGSIZE_2M);
2304 #else
2305         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2306                                          alignment);
2307 #endif
2308         if (!mz)
2309                 return I40E_ERR_NO_MEMORY;
2310
2311         mem->id = id;
2312         mem->size = size;
2313         mem->va = mz->addr;
2314 #ifdef RTE_LIBRTE_XEN_DOM0
2315         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2316 #else
2317         mem->pa = mz->phys_addr;
2318 #endif
2319
2320         return I40E_SUCCESS;
2321 }
2322
2323 /**
2324  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2325  * @hw:   pointer to the HW structure
2326  * @mem:  ptr to mem struct to free
2327  **/
2328 enum i40e_status_code
2329 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2330                     struct i40e_dma_mem *mem)
2331 {
2332         if (!mem || !mem->va)
2333                 return I40E_ERR_PARAM;
2334
2335         mem->va = NULL;
2336         mem->pa = (u64)0;
2337
2338         return I40E_SUCCESS;
2339 }
2340
2341 /**
2342  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2343  * @hw:   pointer to the HW structure
2344  * @mem:  pointer to mem struct to fill out
2345  * @size: size of memory requested
2346  **/
2347 enum i40e_status_code
2348 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2349                          struct i40e_virt_mem *mem,
2350                          u32 size)
2351 {
2352         if (!mem)
2353                 return I40E_ERR_PARAM;
2354
2355         mem->size = size;
2356         mem->va = rte_zmalloc("i40e", size, 0);
2357
2358         if (mem->va)
2359                 return I40E_SUCCESS;
2360         else
2361                 return I40E_ERR_NO_MEMORY;
2362 }
2363
2364 /**
2365  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2366  * @hw:   pointer to the HW structure
2367  * @mem:  pointer to mem struct to free
2368  **/
2369 enum i40e_status_code
2370 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2371                      struct i40e_virt_mem *mem)
2372 {
2373         if (!mem)
2374                 return I40E_ERR_PARAM;
2375
2376         rte_free(mem->va);
2377         mem->va = NULL;
2378
2379         return I40E_SUCCESS;
2380 }
2381
2382 void
2383 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2384 {
2385         rte_spinlock_init(&sp->spinlock);
2386 }
2387
2388 void
2389 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2390 {
2391         rte_spinlock_lock(&sp->spinlock);
2392 }
2393
2394 void
2395 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2396 {
2397         rte_spinlock_unlock(&sp->spinlock);
2398 }
2399
2400 void
2401 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2402 {
2403         return;
2404 }
2405
2406 /**
2407  * Get the hardware capabilities, which will be parsed
2408  * and saved into struct i40e_hw.
2409  */
2410 static int
2411 i40e_get_cap(struct i40e_hw *hw)
2412 {
2413         struct i40e_aqc_list_capabilities_element_resp *buf;
2414         uint16_t len, size = 0;
2415         int ret;
2416
2417         /* Calculate a huge enough buff for saving response data temporarily */
2418         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2419                                                 I40E_MAX_CAP_ELE_NUM;
2420         buf = rte_zmalloc("i40e", len, 0);
2421         if (!buf) {
2422                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2423                 return I40E_ERR_NO_MEMORY;
2424         }
2425
2426         /* Get, parse the capabilities and save it to hw */
2427         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2428                         i40e_aqc_opc_list_func_capabilities, NULL);
2429         if (ret != I40E_SUCCESS)
2430                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2431
2432         /* Free the temporary buffer after being used */
2433         rte_free(buf);
2434
2435         return ret;
2436 }
2437
2438 static int
2439 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2440 {
2441         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2443         uint16_t sum_queues = 0, sum_vsis, left_queues;
2444
2445         /* First check if FW support SRIOV */
2446         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2447                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2448                 return -EINVAL;
2449         }
2450         /* Add the parameter init for LFC */
2451         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2452         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2453         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2454
2455         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2456         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2457         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2458         /* Allocate queues for pf */
2459         if (hw->func_caps.rss) {
2460                 pf->flags |= I40E_FLAG_RSS;
2461                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2462                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2463                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2464         } else
2465                 pf->lan_nb_qps = 1;
2466         sum_queues = pf->lan_nb_qps;
2467         /* Default VSI is not counted in */
2468         sum_vsis = 0;
2469         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2470
2471         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2472                 pf->flags |= I40E_FLAG_SRIOV;
2473                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2474                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2475                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2476                                      "max supported %u.",
2477                                      dev->pci_dev->max_vfs,
2478                                      hw->func_caps.num_vfs);
2479                         return -EINVAL;
2480                 }
2481                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2482                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2483                                      "max support %u queues.",
2484                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2485                         return -EINVAL;
2486                 }
2487                 pf->vf_num = dev->pci_dev->max_vfs;
2488                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2489                 sum_vsis   += pf->vf_num;
2490                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2491                              pf->vf_num, pf->vf_nb_qps);
2492         } else
2493                 pf->vf_num = 0;
2494
2495         if (hw->func_caps.vmdq) {
2496                 pf->flags |= I40E_FLAG_VMDQ;
2497                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2498                 pf->max_nb_vmdq_vsi = 1;
2499                 /*
2500                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2501                  * later.
2502                  */
2503                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2504                 sum_vsis += pf->max_nb_vmdq_vsi;
2505         } else {
2506                 pf->vmdq_nb_qps = 0;
2507                 pf->max_nb_vmdq_vsi = 0;
2508         }
2509         pf->nb_cfg_vmdq_vsi = 0;
2510
2511         if (hw->func_caps.fd) {
2512                 pf->flags |= I40E_FLAG_FDIR;
2513                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2514                 /**
2515                  * Each flow director consumes one VSI and one queue,
2516                  * but can't calculate out predictably here.
2517                  */
2518         }
2519
2520         if (sum_vsis > pf->max_num_vsi ||
2521                 sum_queues > hw->func_caps.num_rx_qp) {
2522                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2523                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2524                              pf->max_num_vsi, sum_vsis);
2525                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2526                              hw->func_caps.num_rx_qp, sum_queues);
2527                 return -EINVAL;
2528         }
2529
2530         /* Adjust VMDQ setting to support as many VMs as possible */
2531         if (pf->flags & I40E_FLAG_VMDQ) {
2532                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2533
2534                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2535                                         pf->max_num_vsi - sum_vsis);
2536
2537                 /* Limit the max VMDQ number that rte_ether that can support  */
2538                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2539                                         ETH_64_POOLS - 1);
2540
2541                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2542                                 pf->max_nb_vmdq_vsi);
2543                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2544         }
2545
2546         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2547          * cause */
2548         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2549                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2550                              sum_vsis, hw->func_caps.num_msix_vectors);
2551                 return -EINVAL;
2552         }
2553         return I40E_SUCCESS;
2554 }
2555
2556 static int
2557 i40e_pf_get_switch_config(struct i40e_pf *pf)
2558 {
2559         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2560         struct i40e_aqc_get_switch_config_resp *switch_config;
2561         struct i40e_aqc_switch_config_element_resp *element;
2562         uint16_t start_seid = 0, num_reported;
2563         int ret;
2564
2565         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2566                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2567         if (!switch_config) {
2568                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2569                 return -ENOMEM;
2570         }
2571
2572         /* Get the switch configurations */
2573         ret = i40e_aq_get_switch_config(hw, switch_config,
2574                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2575         if (ret != I40E_SUCCESS) {
2576                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2577                 goto fail;
2578         }
2579         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2580         if (num_reported != 1) { /* The number should be 1 */
2581                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2582                 goto fail;
2583         }
2584
2585         /* Parse the switch configuration elements */
2586         element = &(switch_config->element[0]);
2587         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2588                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2589                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2590         } else
2591                 PMD_DRV_LOG(INFO, "Unknown element type");
2592
2593 fail:
2594         rte_free(switch_config);
2595
2596         return ret;
2597 }
2598
2599 static int
2600 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2601                         uint32_t num)
2602 {
2603         struct pool_entry *entry;
2604
2605         if (pool == NULL || num == 0)
2606                 return -EINVAL;
2607
2608         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2609         if (entry == NULL) {
2610                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2611                 return -ENOMEM;
2612         }
2613
2614         /* queue heap initialize */
2615         pool->num_free = num;
2616         pool->num_alloc = 0;
2617         pool->base = base;
2618         LIST_INIT(&pool->alloc_list);
2619         LIST_INIT(&pool->free_list);
2620
2621         /* Initialize element  */
2622         entry->base = 0;
2623         entry->len = num;
2624
2625         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2626         return 0;
2627 }
2628
2629 static void
2630 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2631 {
2632         struct pool_entry *entry;
2633
2634         if (pool == NULL)
2635                 return;
2636
2637         LIST_FOREACH(entry, &pool->alloc_list, next) {
2638                 LIST_REMOVE(entry, next);
2639                 rte_free(entry);
2640         }
2641
2642         LIST_FOREACH(entry, &pool->free_list, next) {
2643                 LIST_REMOVE(entry, next);
2644                 rte_free(entry);
2645         }
2646
2647         pool->num_free = 0;
2648         pool->num_alloc = 0;
2649         pool->base = 0;
2650         LIST_INIT(&pool->alloc_list);
2651         LIST_INIT(&pool->free_list);
2652 }
2653
2654 static int
2655 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2656                        uint32_t base)
2657 {
2658         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2659         uint32_t pool_offset;
2660         int insert;
2661
2662         if (pool == NULL) {
2663                 PMD_DRV_LOG(ERR, "Invalid parameter");
2664                 return -EINVAL;
2665         }
2666
2667         pool_offset = base - pool->base;
2668         /* Lookup in alloc list */
2669         LIST_FOREACH(entry, &pool->alloc_list, next) {
2670                 if (entry->base == pool_offset) {
2671                         valid_entry = entry;
2672                         LIST_REMOVE(entry, next);
2673                         break;
2674                 }
2675         }
2676
2677         /* Not find, return */
2678         if (valid_entry == NULL) {
2679                 PMD_DRV_LOG(ERR, "Failed to find entry");
2680                 return -EINVAL;
2681         }
2682
2683         /**
2684          * Found it, move it to free list  and try to merge.
2685          * In order to make merge easier, always sort it by qbase.
2686          * Find adjacent prev and last entries.
2687          */
2688         prev = next = NULL;
2689         LIST_FOREACH(entry, &pool->free_list, next) {
2690                 if (entry->base > valid_entry->base) {
2691                         next = entry;
2692                         break;
2693                 }
2694                 prev = entry;
2695         }
2696
2697         insert = 0;
2698         /* Try to merge with next one*/
2699         if (next != NULL) {
2700                 /* Merge with next one */
2701                 if (valid_entry->base + valid_entry->len == next->base) {
2702                         next->base = valid_entry->base;
2703                         next->len += valid_entry->len;
2704                         rte_free(valid_entry);
2705                         valid_entry = next;
2706                         insert = 1;
2707                 }
2708         }
2709
2710         if (prev != NULL) {
2711                 /* Merge with previous one */
2712                 if (prev->base + prev->len == valid_entry->base) {
2713                         prev->len += valid_entry->len;
2714                         /* If it merge with next one, remove next node */
2715                         if (insert == 1) {
2716                                 LIST_REMOVE(valid_entry, next);
2717                                 rte_free(valid_entry);
2718                         } else {
2719                                 rte_free(valid_entry);
2720                                 insert = 1;
2721                         }
2722                 }
2723         }
2724
2725         /* Not find any entry to merge, insert */
2726         if (insert == 0) {
2727                 if (prev != NULL)
2728                         LIST_INSERT_AFTER(prev, valid_entry, next);
2729                 else if (next != NULL)
2730                         LIST_INSERT_BEFORE(next, valid_entry, next);
2731                 else /* It's empty list, insert to head */
2732                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2733         }
2734
2735         pool->num_free += valid_entry->len;
2736         pool->num_alloc -= valid_entry->len;
2737
2738         return 0;
2739 }
2740
2741 static int
2742 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2743                        uint16_t num)
2744 {
2745         struct pool_entry *entry, *valid_entry;
2746
2747         if (pool == NULL || num == 0) {
2748                 PMD_DRV_LOG(ERR, "Invalid parameter");
2749                 return -EINVAL;
2750         }
2751
2752         if (pool->num_free < num) {
2753                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2754                             num, pool->num_free);
2755                 return -ENOMEM;
2756         }
2757
2758         valid_entry = NULL;
2759         /* Lookup  in free list and find most fit one */
2760         LIST_FOREACH(entry, &pool->free_list, next) {
2761                 if (entry->len >= num) {
2762                         /* Find best one */
2763                         if (entry->len == num) {
2764                                 valid_entry = entry;
2765                                 break;
2766                         }
2767                         if (valid_entry == NULL || valid_entry->len > entry->len)
2768                                 valid_entry = entry;
2769                 }
2770         }
2771
2772         /* Not find one to satisfy the request, return */
2773         if (valid_entry == NULL) {
2774                 PMD_DRV_LOG(ERR, "No valid entry found");
2775                 return -ENOMEM;
2776         }
2777         /**
2778          * The entry have equal queue number as requested,
2779          * remove it from alloc_list.
2780          */
2781         if (valid_entry->len == num) {
2782                 LIST_REMOVE(valid_entry, next);
2783         } else {
2784                 /**
2785                  * The entry have more numbers than requested,
2786                  * create a new entry for alloc_list and minus its
2787                  * queue base and number in free_list.
2788                  */
2789                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2790                 if (entry == NULL) {
2791                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2792                                     "resource pool");
2793                         return -ENOMEM;
2794                 }
2795                 entry->base = valid_entry->base;
2796                 entry->len = num;
2797                 valid_entry->base += num;
2798                 valid_entry->len -= num;
2799                 valid_entry = entry;
2800         }
2801
2802         /* Insert it into alloc list, not sorted */
2803         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2804
2805         pool->num_free -= valid_entry->len;
2806         pool->num_alloc += valid_entry->len;
2807
2808         return (valid_entry->base + pool->base);
2809 }
2810
2811 /**
2812  * bitmap_is_subset - Check whether src2 is subset of src1
2813  **/
2814 static inline int
2815 bitmap_is_subset(uint8_t src1, uint8_t src2)
2816 {
2817         return !((src1 ^ src2) & src2);
2818 }
2819
2820 static int
2821 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2822 {
2823         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2824
2825         /* If DCB is not supported, only default TC is supported */
2826         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2827                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2828                 return -EINVAL;
2829         }
2830
2831         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2832                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2833                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2834                             enabled_tcmap);
2835                 return -EINVAL;
2836         }
2837         return I40E_SUCCESS;
2838 }
2839
2840 int
2841 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2842                                 struct i40e_vsi_vlan_pvid_info *info)
2843 {
2844         struct i40e_hw *hw;
2845         struct i40e_vsi_context ctxt;
2846         uint8_t vlan_flags = 0;
2847         int ret;
2848
2849         if (vsi == NULL || info == NULL) {
2850                 PMD_DRV_LOG(ERR, "invalid parameters");
2851                 return I40E_ERR_PARAM;
2852         }
2853
2854         if (info->on) {
2855                 vsi->info.pvid = info->config.pvid;
2856                 /**
2857                  * If insert pvid is enabled, only tagged pkts are
2858                  * allowed to be sent out.
2859                  */
2860                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2861                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2862         } else {
2863                 vsi->info.pvid = 0;
2864                 if (info->config.reject.tagged == 0)
2865                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2866
2867                 if (info->config.reject.untagged == 0)
2868                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2869         }
2870         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2871                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2872         vsi->info.port_vlan_flags |= vlan_flags;
2873         vsi->info.valid_sections =
2874                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2875         memset(&ctxt, 0, sizeof(ctxt));
2876         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2877         ctxt.seid = vsi->seid;
2878
2879         hw = I40E_VSI_TO_HW(vsi);
2880         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2881         if (ret != I40E_SUCCESS)
2882                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2883
2884         return ret;
2885 }
2886
2887 static int
2888 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2889 {
2890         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2891         int i, ret;
2892         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2893
2894         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2895         if (ret != I40E_SUCCESS)
2896                 return ret;
2897
2898         if (!vsi->seid) {
2899                 PMD_DRV_LOG(ERR, "seid not valid");
2900                 return -EINVAL;
2901         }
2902
2903         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2904         tc_bw_data.tc_valid_bits = enabled_tcmap;
2905         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2906                 tc_bw_data.tc_bw_credits[i] =
2907                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2908
2909         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2910         if (ret != I40E_SUCCESS) {
2911                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2912                 return ret;
2913         }
2914
2915         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2916                                         sizeof(vsi->info.qs_handle));
2917         return I40E_SUCCESS;
2918 }
2919
2920 static int
2921 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2922                                  struct i40e_aqc_vsi_properties_data *info,
2923                                  uint8_t enabled_tcmap)
2924 {
2925         int ret, total_tc = 0, i;
2926         uint16_t qpnum_per_tc, bsf, qp_idx;
2927
2928         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2929         if (ret != I40E_SUCCESS)
2930                 return ret;
2931
2932         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2933                 if (enabled_tcmap & (1 << i))
2934                         total_tc++;
2935         vsi->enabled_tc = enabled_tcmap;
2936
2937         /* Number of queues per enabled TC */
2938         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2939         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2940         bsf = rte_bsf32(qpnum_per_tc);
2941
2942         /* Adjust the queue number to actual queues that can be applied */
2943         vsi->nb_qps = qpnum_per_tc * total_tc;
2944
2945         /**
2946          * Configure TC and queue mapping parameters, for enabled TC,
2947          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2948          * default queue will serve it.
2949          */
2950         qp_idx = 0;
2951         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2952                 if (vsi->enabled_tc & (1 << i)) {
2953                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2954                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2955                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2956                         qp_idx += qpnum_per_tc;
2957                 } else
2958                         info->tc_mapping[i] = 0;
2959         }
2960
2961         /* Associate queue number with VSI */
2962         if (vsi->type == I40E_VSI_SRIOV) {
2963                 info->mapping_flags |=
2964                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2965                 for (i = 0; i < vsi->nb_qps; i++)
2966                         info->queue_mapping[i] =
2967                                 rte_cpu_to_le_16(vsi->base_queue + i);
2968         } else {
2969                 info->mapping_flags |=
2970                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2971                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2972         }
2973         info->valid_sections |=
2974                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2975
2976         return I40E_SUCCESS;
2977 }
2978
2979 static int
2980 i40e_veb_release(struct i40e_veb *veb)
2981 {
2982         struct i40e_vsi *vsi;
2983         struct i40e_hw *hw;
2984
2985         if (veb == NULL || veb->associate_vsi == NULL)
2986                 return -EINVAL;
2987
2988         if (!TAILQ_EMPTY(&veb->head)) {
2989                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2990                 return -EACCES;
2991         }
2992
2993         vsi = veb->associate_vsi;
2994         hw = I40E_VSI_TO_HW(vsi);
2995
2996         vsi->uplink_seid = veb->uplink_seid;
2997         i40e_aq_delete_element(hw, veb->seid, NULL);
2998         rte_free(veb);
2999         vsi->veb = NULL;
3000         return I40E_SUCCESS;
3001 }
3002
3003 /* Setup a veb */
3004 static struct i40e_veb *
3005 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3006 {
3007         struct i40e_veb *veb;
3008         int ret;
3009         struct i40e_hw *hw;
3010
3011         if (NULL == pf || vsi == NULL) {
3012                 PMD_DRV_LOG(ERR, "veb setup failed, "
3013                             "associated VSI shouldn't null");
3014                 return NULL;
3015         }
3016         hw = I40E_PF_TO_HW(pf);
3017
3018         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3019         if (!veb) {
3020                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3021                 goto fail;
3022         }
3023
3024         veb->associate_vsi = vsi;
3025         TAILQ_INIT(&veb->head);
3026         veb->uplink_seid = vsi->uplink_seid;
3027
3028         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3029                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3030
3031         if (ret != I40E_SUCCESS) {
3032                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3033                             hw->aq.asq_last_status);
3034                 goto fail;
3035         }
3036
3037         /* get statistics index */
3038         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3039                                 &veb->stats_idx, NULL, NULL, NULL);
3040         if (ret != I40E_SUCCESS) {
3041                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3042                             hw->aq.asq_last_status);
3043                 goto fail;
3044         }
3045
3046         /* Get VEB bandwidth, to be implemented */
3047         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3048         vsi->uplink_seid = veb->seid;
3049
3050         return veb;
3051 fail:
3052         rte_free(veb);
3053         return NULL;
3054 }
3055
3056 int
3057 i40e_vsi_release(struct i40e_vsi *vsi)
3058 {
3059         struct i40e_pf *pf;
3060         struct i40e_hw *hw;
3061         struct i40e_vsi_list *vsi_list;
3062         int ret;
3063         struct i40e_mac_filter *f;
3064
3065         if (!vsi)
3066                 return I40E_SUCCESS;
3067
3068         pf = I40E_VSI_TO_PF(vsi);
3069         hw = I40E_VSI_TO_HW(vsi);
3070
3071         /* VSI has child to attach, release child first */
3072         if (vsi->veb) {
3073                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3074                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3075                                 return -1;
3076                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3077                 }
3078                 i40e_veb_release(vsi->veb);
3079         }
3080
3081         /* Remove all macvlan filters of the VSI */
3082         i40e_vsi_remove_all_macvlan_filter(vsi);
3083         TAILQ_FOREACH(f, &vsi->mac_list, next)
3084                 rte_free(f);
3085
3086         if (vsi->type != I40E_VSI_MAIN) {
3087                 /* Remove vsi from parent's sibling list */
3088                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3089                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3090                         return I40E_ERR_PARAM;
3091                 }
3092                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3093                                 &vsi->sib_vsi_list, list);
3094
3095                 /* Remove all switch element of the VSI */
3096                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3097                 if (ret != I40E_SUCCESS)
3098                         PMD_DRV_LOG(ERR, "Failed to delete element");
3099         }
3100         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3101
3102         if (vsi->type != I40E_VSI_SRIOV)
3103                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3104         rte_free(vsi);
3105
3106         return I40E_SUCCESS;
3107 }
3108
3109 static int
3110 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3111 {
3112         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3113         struct i40e_aqc_remove_macvlan_element_data def_filter;
3114         struct i40e_mac_filter_info filter;
3115         int ret;
3116
3117         if (vsi->type != I40E_VSI_MAIN)
3118                 return I40E_ERR_CONFIG;
3119         memset(&def_filter, 0, sizeof(def_filter));
3120         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3121                                         ETH_ADDR_LEN);
3122         def_filter.vlan_tag = 0;
3123         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3124                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3125         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3126         if (ret != I40E_SUCCESS) {
3127                 struct i40e_mac_filter *f;
3128                 struct ether_addr *mac;
3129
3130                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3131                             "macvlan filter");
3132                 /* It needs to add the permanent mac into mac list */
3133                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3134                 if (f == NULL) {
3135                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3136                         return I40E_ERR_NO_MEMORY;
3137                 }
3138                 mac = &f->mac_info.mac_addr;
3139                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3140                                 ETH_ADDR_LEN);
3141                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3142                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3143                 vsi->mac_num++;
3144
3145                 return ret;
3146         }
3147         (void)rte_memcpy(&filter.mac_addr,
3148                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3149         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3150         return i40e_vsi_add_mac(vsi, &filter);
3151 }
3152
3153 static int
3154 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3155 {
3156         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3157         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3158         struct i40e_hw *hw = &vsi->adapter->hw;
3159         i40e_status ret;
3160         int i;
3161
3162         memset(&bw_config, 0, sizeof(bw_config));
3163         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3164         if (ret != I40E_SUCCESS) {
3165                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3166                             hw->aq.asq_last_status);
3167                 return ret;
3168         }
3169
3170         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3171         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3172                                         &ets_sla_config, NULL);
3173         if (ret != I40E_SUCCESS) {
3174                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3175                             "configuration %u", hw->aq.asq_last_status);
3176                 return ret;
3177         }
3178
3179         /* Not store the info yet, just print out */
3180         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3181         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3182         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3183                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3184                             ets_sla_config.share_credits[i]);
3185                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3186                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3187                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3188                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3189                             (i * 4));
3190         }
3191
3192         return 0;
3193 }
3194
3195 /* Setup a VSI */
3196 struct i40e_vsi *
3197 i40e_vsi_setup(struct i40e_pf *pf,
3198                enum i40e_vsi_type type,
3199                struct i40e_vsi *uplink_vsi,
3200                uint16_t user_param)
3201 {
3202         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3203         struct i40e_vsi *vsi;
3204         struct i40e_mac_filter_info filter;
3205         int ret;
3206         struct i40e_vsi_context ctxt;
3207         struct ether_addr broadcast =
3208                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3209
3210         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3211                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3212                             "VSI link shouldn't be NULL");
3213                 return NULL;
3214         }
3215
3216         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3217                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3218                             "uplink VSI should be NULL");
3219                 return NULL;
3220         }
3221
3222         /* If uplink vsi didn't setup VEB, create one first */
3223         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3224                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3225
3226                 if (NULL == uplink_vsi->veb) {
3227                         PMD_DRV_LOG(ERR, "VEB setup failed");
3228                         return NULL;
3229                 }
3230         }
3231
3232         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3233         if (!vsi) {
3234                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3235                 return NULL;
3236         }
3237         TAILQ_INIT(&vsi->mac_list);
3238         vsi->type = type;
3239         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3240         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3241         vsi->parent_vsi = uplink_vsi;
3242         vsi->user_param = user_param;
3243         /* Allocate queues */
3244         switch (vsi->type) {
3245         case I40E_VSI_MAIN  :
3246                 vsi->nb_qps = pf->lan_nb_qps;
3247                 break;
3248         case I40E_VSI_SRIOV :
3249                 vsi->nb_qps = pf->vf_nb_qps;
3250                 break;
3251         case I40E_VSI_VMDQ2:
3252                 vsi->nb_qps = pf->vmdq_nb_qps;
3253                 break;
3254         case I40E_VSI_FDIR:
3255                 vsi->nb_qps = pf->fdir_nb_qps;
3256                 break;
3257         default:
3258                 goto fail_mem;
3259         }
3260         /*
3261          * The filter status descriptor is reported in rx queue 0,
3262          * while the tx queue for fdir filter programming has no
3263          * such constraints, can be non-zero queues.
3264          * To simplify it, choose FDIR vsi use queue 0 pair.
3265          * To make sure it will use queue 0 pair, queue allocation
3266          * need be done before this function is called
3267          */
3268         if (type != I40E_VSI_FDIR) {
3269                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3270                         if (ret < 0) {
3271                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3272                                                 vsi->seid, ret);
3273                                 goto fail_mem;
3274                         }
3275                         vsi->base_queue = ret;
3276         } else
3277                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3278
3279         /* VF has MSIX interrupt in VF range, don't allocate here */
3280         if (type != I40E_VSI_SRIOV) {
3281                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3282                 if (ret < 0) {
3283                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3284                         goto fail_queue_alloc;
3285                 }
3286                 vsi->msix_intr = ret;
3287         } else
3288                 vsi->msix_intr = 0;
3289         /* Add VSI */
3290         if (type == I40E_VSI_MAIN) {
3291                 /* For main VSI, no need to add since it's default one */
3292                 vsi->uplink_seid = pf->mac_seid;
3293                 vsi->seid = pf->main_vsi_seid;
3294                 /* Bind queues with specific MSIX interrupt */
3295                 /**
3296                  * Needs 2 interrupt at least, one for misc cause which will
3297                  * enabled from OS side, Another for queues binding the
3298                  * interrupt from device side only.
3299                  */
3300
3301                 /* Get default VSI parameters from hardware */
3302                 memset(&ctxt, 0, sizeof(ctxt));
3303                 ctxt.seid = vsi->seid;
3304                 ctxt.pf_num = hw->pf_id;
3305                 ctxt.uplink_seid = vsi->uplink_seid;
3306                 ctxt.vf_num = 0;
3307                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3308                 if (ret != I40E_SUCCESS) {
3309                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3310                         goto fail_msix_alloc;
3311                 }
3312                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3313                         sizeof(struct i40e_aqc_vsi_properties_data));
3314                 vsi->vsi_id = ctxt.vsi_number;
3315                 vsi->info.valid_sections = 0;
3316
3317                 /* Configure tc, enabled TC0 only */
3318                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3319                         I40E_SUCCESS) {
3320                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3321                         goto fail_msix_alloc;
3322                 }
3323
3324                 /* TC, queue mapping */
3325                 memset(&ctxt, 0, sizeof(ctxt));
3326                 vsi->info.valid_sections |=
3327                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3328                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3329                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3330                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3331                         sizeof(struct i40e_aqc_vsi_properties_data));
3332                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3333                                                 I40E_DEFAULT_TCMAP);
3334                 if (ret != I40E_SUCCESS) {
3335                         PMD_DRV_LOG(ERR, "Failed to configure "
3336                                     "TC queue mapping");
3337                         goto fail_msix_alloc;
3338                 }
3339                 ctxt.seid = vsi->seid;
3340                 ctxt.pf_num = hw->pf_id;
3341                 ctxt.uplink_seid = vsi->uplink_seid;
3342                 ctxt.vf_num = 0;
3343
3344                 /* Update VSI parameters */
3345                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3346                 if (ret != I40E_SUCCESS) {
3347                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3348                         goto fail_msix_alloc;
3349                 }
3350
3351                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3352                                                 sizeof(vsi->info.tc_mapping));
3353                 (void)rte_memcpy(&vsi->info.queue_mapping,
3354                                 &ctxt.info.queue_mapping,
3355                         sizeof(vsi->info.queue_mapping));
3356                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3357                 vsi->info.valid_sections = 0;
3358
3359                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3360                                 ETH_ADDR_LEN);
3361
3362                 /**
3363                  * Updating default filter settings are necessary to prevent
3364                  * reception of tagged packets.
3365                  * Some old firmware configurations load a default macvlan
3366                  * filter which accepts both tagged and untagged packets.
3367                  * The updating is to use a normal filter instead if needed.
3368                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3369                  * The firmware with correct configurations load the default
3370                  * macvlan filter which is expected and cannot be removed.
3371                  */
3372                 i40e_update_default_filter_setting(vsi);
3373                 i40e_config_qinq(hw, vsi);
3374         } else if (type == I40E_VSI_SRIOV) {
3375                 memset(&ctxt, 0, sizeof(ctxt));
3376                 /**
3377                  * For other VSI, the uplink_seid equals to uplink VSI's
3378                  * uplink_seid since they share same VEB
3379                  */
3380                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3381                 ctxt.pf_num = hw->pf_id;
3382                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3383                 ctxt.uplink_seid = vsi->uplink_seid;
3384                 ctxt.connection_type = 0x1;
3385                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3386
3387                 /**
3388                  * Do not configure switch ID to enable VEB switch by
3389                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3390                  * if the source mac address of packet sent from VF is not
3391                  * listed in the VEB's mac table, the VEB will switch the
3392                  * packet back to the VF. Need to enable it when HW issue
3393                  * is fixed.
3394                  */
3395
3396                 /* Configure port/vlan */
3397                 ctxt.info.valid_sections |=
3398                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3399                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3400                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3401                                                 I40E_DEFAULT_TCMAP);
3402                 if (ret != I40E_SUCCESS) {
3403                         PMD_DRV_LOG(ERR, "Failed to configure "
3404                                     "TC queue mapping");
3405                         goto fail_msix_alloc;
3406                 }
3407                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3408                 ctxt.info.valid_sections |=
3409                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3410                 /**
3411                  * Since VSI is not created yet, only configure parameter,
3412                  * will add vsi below.
3413                  */
3414
3415                 i40e_config_qinq(hw, vsi);
3416         } else if (type == I40E_VSI_VMDQ2) {
3417                 memset(&ctxt, 0, sizeof(ctxt));
3418                 /*
3419                  * For other VSI, the uplink_seid equals to uplink VSI's
3420                  * uplink_seid since they share same VEB
3421                  */
3422                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3423                 ctxt.pf_num = hw->pf_id;
3424                 ctxt.vf_num = 0;
3425                 ctxt.uplink_seid = vsi->uplink_seid;
3426                 ctxt.connection_type = 0x1;
3427                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3428
3429                 ctxt.info.valid_sections |=
3430                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3431                 /* user_param carries flag to enable loop back */
3432                 if (user_param) {
3433                         ctxt.info.switch_id =
3434                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3435                         ctxt.info.switch_id |=
3436                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3437                 }
3438
3439                 /* Configure port/vlan */
3440                 ctxt.info.valid_sections |=
3441                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3442                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3443                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3444                                                 I40E_DEFAULT_TCMAP);
3445                 if (ret != I40E_SUCCESS) {
3446                         PMD_DRV_LOG(ERR, "Failed to configure "
3447                                         "TC queue mapping");
3448                         goto fail_msix_alloc;
3449                 }
3450                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3451                 ctxt.info.valid_sections |=
3452                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3453         } else if (type == I40E_VSI_FDIR) {
3454                 memset(&ctxt, 0, sizeof(ctxt));
3455                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3456                 ctxt.pf_num = hw->pf_id;
3457                 ctxt.vf_num = 0;
3458                 ctxt.uplink_seid = vsi->uplink_seid;
3459                 ctxt.connection_type = 0x1;     /* regular data port */
3460                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3461                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3462                                                 I40E_DEFAULT_TCMAP);
3463                 if (ret != I40E_SUCCESS) {
3464                         PMD_DRV_LOG(ERR, "Failed to configure "
3465                                         "TC queue mapping.");
3466                         goto fail_msix_alloc;
3467                 }
3468                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3469                 ctxt.info.valid_sections |=
3470                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3471         } else {
3472                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3473                 goto fail_msix_alloc;
3474         }
3475
3476         if (vsi->type != I40E_VSI_MAIN) {
3477                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3478                 if (ret != I40E_SUCCESS) {
3479                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3480                                     hw->aq.asq_last_status);
3481                         goto fail_msix_alloc;
3482                 }
3483                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3484                 vsi->info.valid_sections = 0;
3485                 vsi->seid = ctxt.seid;
3486                 vsi->vsi_id = ctxt.vsi_number;
3487                 vsi->sib_vsi_list.vsi = vsi;
3488                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3489                                 &vsi->sib_vsi_list, list);
3490         }
3491
3492         /* MAC/VLAN configuration */
3493         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3494         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3495
3496         ret = i40e_vsi_add_mac(vsi, &filter);
3497         if (ret != I40E_SUCCESS) {
3498                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3499                 goto fail_msix_alloc;
3500         }
3501
3502         /* Get VSI BW information */
3503         i40e_vsi_dump_bw_config(vsi);
3504         return vsi;
3505 fail_msix_alloc:
3506         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3507 fail_queue_alloc:
3508         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3509 fail_mem:
3510         rte_free(vsi);
3511         return NULL;
3512 }
3513
3514 /* Configure vlan stripping on or off */
3515 int
3516 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3517 {
3518         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3519         struct i40e_vsi_context ctxt;
3520         uint8_t vlan_flags;
3521         int ret = I40E_SUCCESS;
3522
3523         /* Check if it has been already on or off */
3524         if (vsi->info.valid_sections &
3525                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3526                 if (on) {
3527                         if ((vsi->info.port_vlan_flags &
3528                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3529                                 return 0; /* already on */
3530                 } else {
3531                         if ((vsi->info.port_vlan_flags &
3532                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3533                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3534                                 return 0; /* already off */
3535                 }
3536         }
3537
3538         if (on)
3539                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3540         else
3541                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3542         vsi->info.valid_sections =
3543                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3544         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3545         vsi->info.port_vlan_flags |= vlan_flags;
3546         ctxt.seid = vsi->seid;
3547         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3548         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3549         if (ret)
3550                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3551                             on ? "enable" : "disable");
3552
3553         return ret;
3554 }
3555
3556 static int
3557 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3558 {
3559         struct rte_eth_dev_data *data = dev->data;
3560         int ret;
3561
3562         /* Apply vlan offload setting */
3563         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3564
3565         /* Apply double-vlan setting, not implemented yet */
3566
3567         /* Apply pvid setting */
3568         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3569                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3570         if (ret)
3571                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3572
3573         return ret;
3574 }
3575
3576 static int
3577 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3578 {
3579         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3580
3581         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3582 }
3583
3584 static int
3585 i40e_update_flow_control(struct i40e_hw *hw)
3586 {
3587 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3588         struct i40e_link_status link_status;
3589         uint32_t rxfc = 0, txfc = 0, reg;
3590         uint8_t an_info;
3591         int ret;
3592
3593         memset(&link_status, 0, sizeof(link_status));
3594         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3595         if (ret != I40E_SUCCESS) {
3596                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3597                 goto write_reg; /* Disable flow control */
3598         }
3599
3600         an_info = hw->phy.link_info.an_info;
3601         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3602                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3603                 ret = I40E_ERR_NOT_READY;
3604                 goto write_reg; /* Disable flow control */
3605         }
3606         /**
3607          * If link auto negotiation is enabled, flow control needs to
3608          * be configured according to it
3609          */
3610         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3611         case I40E_LINK_PAUSE_RXTX:
3612                 rxfc = 1;
3613                 txfc = 1;
3614                 hw->fc.current_mode = I40E_FC_FULL;
3615                 break;
3616         case I40E_AQ_LINK_PAUSE_RX:
3617                 rxfc = 1;
3618                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3619                 break;
3620         case I40E_AQ_LINK_PAUSE_TX:
3621                 txfc = 1;
3622                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3623                 break;
3624         default:
3625                 hw->fc.current_mode = I40E_FC_NONE;
3626                 break;
3627         }
3628
3629 write_reg:
3630         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3631                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3632         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3633         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3634         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3635         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3636
3637         return ret;
3638 }
3639
3640 /* PF setup */
3641 static int
3642 i40e_pf_setup(struct i40e_pf *pf)
3643 {
3644         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3645         struct i40e_filter_control_settings settings;
3646         struct i40e_vsi *vsi;
3647         int ret;
3648
3649         /* Clear all stats counters */
3650         pf->offset_loaded = FALSE;
3651         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3652         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3653
3654         ret = i40e_pf_get_switch_config(pf);
3655         if (ret != I40E_SUCCESS) {
3656                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3657                 return ret;
3658         }
3659         if (pf->flags & I40E_FLAG_FDIR) {
3660                 /* make queue allocated first, let FDIR use queue pair 0*/
3661                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3662                 if (ret != I40E_FDIR_QUEUE_ID) {
3663                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3664                                     " ret =%d", ret);
3665                         pf->flags &= ~I40E_FLAG_FDIR;
3666                 }
3667         }
3668         /*  main VSI setup */
3669         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3670         if (!vsi) {
3671                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3672                 return I40E_ERR_NOT_READY;
3673         }
3674         pf->main_vsi = vsi;
3675
3676         /* Configure filter control */
3677         memset(&settings, 0, sizeof(settings));
3678         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3679                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3680         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3681                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3682         else {
3683                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3684                                                 hw->func_caps.rss_table_size);
3685                 return I40E_ERR_PARAM;
3686         }
3687         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3688                         "size: %u\n", hw->func_caps.rss_table_size);
3689         pf->hash_lut_size = hw->func_caps.rss_table_size;
3690
3691         /* Enable ethtype and macvlan filters */
3692         settings.enable_ethtype = TRUE;
3693         settings.enable_macvlan = TRUE;
3694         ret = i40e_set_filter_control(hw, &settings);
3695         if (ret)
3696                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3697                                                                 ret);
3698
3699         /* Update flow control according to the auto negotiation */
3700         i40e_update_flow_control(hw);
3701
3702         return I40E_SUCCESS;
3703 }
3704
3705 int
3706 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3707 {
3708         uint32_t reg;
3709         uint16_t j;
3710
3711         /**
3712          * Set or clear TX Queue Disable flags,
3713          * which is required by hardware.
3714          */
3715         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3716         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3717
3718         /* Wait until the request is finished */
3719         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3720                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3721                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3722                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3723                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3724                                                         & 0x1))) {
3725                         break;
3726                 }
3727         }
3728         if (on) {
3729                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3730                         return I40E_SUCCESS; /* already on, skip next steps */
3731
3732                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3733                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3734         } else {
3735                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3736                         return I40E_SUCCESS; /* already off, skip next steps */
3737                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3738         }
3739         /* Write the register */
3740         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3741         /* Check the result */
3742         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3743                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3744                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3745                 if (on) {
3746                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3747                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3748                                 break;
3749                 } else {
3750                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3751                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3752                                 break;
3753                 }
3754         }
3755         /* Check if it is timeout */
3756         if (j >= I40E_CHK_Q_ENA_COUNT) {
3757                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3758                             (on ? "enable" : "disable"), q_idx);
3759                 return I40E_ERR_TIMEOUT;
3760         }
3761
3762         return I40E_SUCCESS;
3763 }
3764
3765 /* Swith on or off the tx queues */
3766 static int
3767 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3768 {
3769         struct rte_eth_dev_data *dev_data = pf->dev_data;
3770         struct i40e_tx_queue *txq;
3771         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3772         uint16_t i;
3773         int ret;
3774
3775         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3776                 txq = dev_data->tx_queues[i];
3777                 /* Don't operate the queue if not configured or
3778                  * if starting only per queue */
3779                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3780                         continue;
3781                 if (on)
3782                         ret = i40e_dev_tx_queue_start(dev, i);
3783                 else
3784                         ret = i40e_dev_tx_queue_stop(dev, i);
3785                 if ( ret != I40E_SUCCESS)
3786                         return ret;
3787         }
3788
3789         return I40E_SUCCESS;
3790 }
3791
3792 int
3793 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3794 {
3795         uint32_t reg;
3796         uint16_t j;
3797
3798         /* Wait until the request is finished */
3799         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3800                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3801                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3802                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3803                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3804                         break;
3805         }
3806
3807         if (on) {
3808                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3809                         return I40E_SUCCESS; /* Already on, skip next steps */
3810                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3811         } else {
3812                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3813                         return I40E_SUCCESS; /* Already off, skip next steps */
3814                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3815         }
3816
3817         /* Write the register */
3818         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3819         /* Check the result */
3820         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3821                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3822                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3823                 if (on) {
3824                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3825                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3826                                 break;
3827                 } else {
3828                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3829                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3830                                 break;
3831                 }
3832         }
3833
3834         /* Check if it is timeout */
3835         if (j >= I40E_CHK_Q_ENA_COUNT) {
3836                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3837                             (on ? "enable" : "disable"), q_idx);
3838                 return I40E_ERR_TIMEOUT;
3839         }
3840
3841         return I40E_SUCCESS;
3842 }
3843 /* Switch on or off the rx queues */
3844 static int
3845 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3846 {
3847         struct rte_eth_dev_data *dev_data = pf->dev_data;
3848         struct i40e_rx_queue *rxq;
3849         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3850         uint16_t i;
3851         int ret;
3852
3853         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3854                 rxq = dev_data->rx_queues[i];
3855                 /* Don't operate the queue if not configured or
3856                  * if starting only per queue */
3857                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3858                         continue;
3859                 if (on)
3860                         ret = i40e_dev_rx_queue_start(dev, i);
3861                 else
3862                         ret = i40e_dev_rx_queue_stop(dev, i);
3863                 if (ret != I40E_SUCCESS)
3864                         return ret;
3865         }
3866
3867         return I40E_SUCCESS;
3868 }
3869
3870 /* Switch on or off all the rx/tx queues */
3871 int
3872 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3873 {
3874         int ret;
3875
3876         if (on) {
3877                 /* enable rx queues before enabling tx queues */
3878                 ret = i40e_dev_switch_rx_queues(pf, on);
3879                 if (ret) {
3880                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3881                         return ret;
3882                 }
3883                 ret = i40e_dev_switch_tx_queues(pf, on);
3884         } else {
3885                 /* Stop tx queues before stopping rx queues */
3886                 ret = i40e_dev_switch_tx_queues(pf, on);
3887                 if (ret) {
3888                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3889                         return ret;
3890                 }
3891                 ret = i40e_dev_switch_rx_queues(pf, on);
3892         }
3893
3894         return ret;
3895 }
3896
3897 /* Initialize VSI for TX */
3898 static int
3899 i40e_dev_tx_init(struct i40e_pf *pf)
3900 {
3901         struct rte_eth_dev_data *data = pf->dev_data;
3902         uint16_t i;
3903         uint32_t ret = I40E_SUCCESS;
3904         struct i40e_tx_queue *txq;
3905
3906         for (i = 0; i < data->nb_tx_queues; i++) {
3907                 txq = data->tx_queues[i];
3908                 if (!txq || !txq->q_set)
3909                         continue;
3910                 ret = i40e_tx_queue_init(txq);
3911                 if (ret != I40E_SUCCESS)
3912                         break;
3913         }
3914         if (ret == I40E_SUCCESS)
3915                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
3916                                      ->eth_dev);
3917
3918         return ret;
3919 }
3920
3921 /* Initialize VSI for RX */
3922 static int
3923 i40e_dev_rx_init(struct i40e_pf *pf)
3924 {
3925         struct rte_eth_dev_data *data = pf->dev_data;
3926         int ret = I40E_SUCCESS;
3927         uint16_t i;
3928         struct i40e_rx_queue *rxq;
3929
3930         i40e_pf_config_mq_rx(pf);
3931         for (i = 0; i < data->nb_rx_queues; i++) {
3932                 rxq = data->rx_queues[i];
3933                 if (!rxq || !rxq->q_set)
3934                         continue;
3935
3936                 ret = i40e_rx_queue_init(rxq);
3937                 if (ret != I40E_SUCCESS) {
3938                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3939                                     "initialization");
3940                         break;
3941                 }
3942         }
3943         if (ret == I40E_SUCCESS)
3944                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
3945                                      ->eth_dev);
3946
3947         return ret;
3948 }
3949
3950 static int
3951 i40e_dev_rxtx_init(struct i40e_pf *pf)
3952 {
3953         int err;
3954
3955         err = i40e_dev_tx_init(pf);
3956         if (err) {
3957                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3958                 return err;
3959         }
3960         err = i40e_dev_rx_init(pf);
3961         if (err) {
3962                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3963                 return err;
3964         }
3965
3966         return err;
3967 }
3968
3969 static int
3970 i40e_vmdq_setup(struct rte_eth_dev *dev)
3971 {
3972         struct rte_eth_conf *conf = &dev->data->dev_conf;
3973         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3974         int i, err, conf_vsis, j, loop;
3975         struct i40e_vsi *vsi;
3976         struct i40e_vmdq_info *vmdq_info;
3977         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3978         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3979
3980         /*
3981          * Disable interrupt to avoid message from VF. Furthermore, it will
3982          * avoid race condition in VSI creation/destroy.
3983          */
3984         i40e_pf_disable_irq0(hw);
3985
3986         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3987                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3988                 return -ENOTSUP;
3989         }
3990
3991         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3992         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3993                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3994                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3995                         pf->max_nb_vmdq_vsi);
3996                 return -ENOTSUP;
3997         }
3998
3999         if (pf->vmdq != NULL) {
4000                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4001                 return 0;
4002         }
4003
4004         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4005                                 sizeof(*vmdq_info) * conf_vsis, 0);
4006
4007         if (pf->vmdq == NULL) {
4008                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4009                 return -ENOMEM;
4010         }
4011
4012         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4013
4014         /* Create VMDQ VSI */
4015         for (i = 0; i < conf_vsis; i++) {
4016                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4017                                 vmdq_conf->enable_loop_back);
4018                 if (vsi == NULL) {
4019                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4020                         err = -1;
4021                         goto err_vsi_setup;
4022                 }
4023                 vmdq_info = &pf->vmdq[i];
4024                 vmdq_info->pf = pf;
4025                 vmdq_info->vsi = vsi;
4026         }
4027         pf->nb_cfg_vmdq_vsi = conf_vsis;
4028
4029         /* Configure Vlan */
4030         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4031         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4032                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4033                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4034                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4035                                         vmdq_conf->pool_map[i].vlan_id, j);
4036
4037                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4038                                                 vmdq_conf->pool_map[i].vlan_id);
4039                                 if (err) {
4040                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4041                                         err = -1;
4042                                         goto err_vsi_setup;
4043                                 }
4044                         }
4045                 }
4046         }
4047
4048         i40e_pf_enable_irq0(hw);
4049
4050         return 0;
4051
4052 err_vsi_setup:
4053         for (i = 0; i < conf_vsis; i++)
4054                 if (pf->vmdq[i].vsi == NULL)
4055                         break;
4056                 else
4057                         i40e_vsi_release(pf->vmdq[i].vsi);
4058
4059         rte_free(pf->vmdq);
4060         pf->vmdq = NULL;
4061         i40e_pf_enable_irq0(hw);
4062         return err;
4063 }
4064
4065 static void
4066 i40e_stat_update_32(struct i40e_hw *hw,
4067                    uint32_t reg,
4068                    bool offset_loaded,
4069                    uint64_t *offset,
4070                    uint64_t *stat)
4071 {
4072         uint64_t new_data;
4073
4074         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4075         if (!offset_loaded)
4076                 *offset = new_data;
4077
4078         if (new_data >= *offset)
4079                 *stat = (uint64_t)(new_data - *offset);
4080         else
4081                 *stat = (uint64_t)((new_data +
4082                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4083 }
4084
4085 static void
4086 i40e_stat_update_48(struct i40e_hw *hw,
4087                    uint32_t hireg,
4088                    uint32_t loreg,
4089                    bool offset_loaded,
4090                    uint64_t *offset,
4091                    uint64_t *stat)
4092 {
4093         uint64_t new_data;
4094
4095         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4096         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4097                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4098
4099         if (!offset_loaded)
4100                 *offset = new_data;
4101
4102         if (new_data >= *offset)
4103                 *stat = new_data - *offset;
4104         else
4105                 *stat = (uint64_t)((new_data +
4106                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4107
4108         *stat &= I40E_48_BIT_MASK;
4109 }
4110
4111 /* Disable IRQ0 */
4112 void
4113 i40e_pf_disable_irq0(struct i40e_hw *hw)
4114 {
4115         /* Disable all interrupt types */
4116         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4117         I40E_WRITE_FLUSH(hw);
4118 }
4119
4120 /* Enable IRQ0 */
4121 void
4122 i40e_pf_enable_irq0(struct i40e_hw *hw)
4123 {
4124         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4125                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4126                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4127                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4128         I40E_WRITE_FLUSH(hw);
4129 }
4130
4131 static void
4132 i40e_pf_config_irq0(struct i40e_hw *hw)
4133 {
4134         /* read pending request and disable first */
4135         i40e_pf_disable_irq0(hw);
4136         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4137         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4138                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4139
4140         /* Link no queues with irq0 */
4141         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4142                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4143 }
4144
4145 static void
4146 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4147 {
4148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4149         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4150         int i;
4151         uint16_t abs_vf_id;
4152         uint32_t index, offset, val;
4153
4154         if (!pf->vfs)
4155                 return;
4156         /**
4157          * Try to find which VF trigger a reset, use absolute VF id to access
4158          * since the reg is global register.
4159          */
4160         for (i = 0; i < pf->vf_num; i++) {
4161                 abs_vf_id = hw->func_caps.vf_base_id + i;
4162                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4163                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4164                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4165                 /* VFR event occured */
4166                 if (val & (0x1 << offset)) {
4167                         int ret;
4168
4169                         /* Clear the event first */
4170                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4171                                                         (0x1 << offset));
4172                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4173                         /**
4174                          * Only notify a VF reset event occured,
4175                          * don't trigger another SW reset
4176                          */
4177                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4178                         if (ret != I40E_SUCCESS)
4179                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4180                 }
4181         }
4182 }
4183
4184 static void
4185 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4186 {
4187         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4188         struct i40e_arq_event_info info;
4189         uint16_t pending, opcode;
4190         int ret;
4191
4192         info.buf_len = I40E_AQ_BUF_SZ;
4193         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4194         if (!info.msg_buf) {
4195                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4196                 return;
4197         }
4198
4199         pending = 1;
4200         while (pending) {
4201                 ret = i40e_clean_arq_element(hw, &info, &pending);
4202
4203                 if (ret != I40E_SUCCESS) {
4204                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4205                                     "aq_err: %u", hw->aq.asq_last_status);
4206                         break;
4207                 }
4208                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4209
4210                 switch (opcode) {
4211                 case i40e_aqc_opc_send_msg_to_pf:
4212                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4213                         i40e_pf_host_handle_vf_msg(dev,
4214                                         rte_le_to_cpu_16(info.desc.retval),
4215                                         rte_le_to_cpu_32(info.desc.cookie_high),
4216                                         rte_le_to_cpu_32(info.desc.cookie_low),
4217                                         info.msg_buf,
4218                                         info.msg_len);
4219                         break;
4220                 default:
4221                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4222                                     opcode);
4223                         break;
4224                 }
4225         }
4226         rte_free(info.msg_buf);
4227 }
4228
4229 /*
4230  * Interrupt handler is registered as the alarm callback for handling LSC
4231  * interrupt in a definite of time, in order to wait the NIC into a stable
4232  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4233  * no need for link down interrupt.
4234  */
4235 static void
4236 i40e_dev_interrupt_delayed_handler(void *param)
4237 {
4238         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4240         uint32_t icr0;
4241
4242         /* read interrupt causes again */
4243         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4244
4245 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4246         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4247                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4248         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4249                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4250         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4251                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4252         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4253                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4254         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4255                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4256                                                                 "state\n");
4257         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4258                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4259         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4260                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4261 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4262
4263         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4264                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4265                 i40e_dev_handle_vfr_event(dev);
4266         }
4267         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4268                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4269                 i40e_dev_handle_aq_msg(dev);
4270         }
4271
4272         /* handle the link up interrupt in an alarm callback */
4273         i40e_dev_link_update(dev, 0);
4274         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4275
4276         i40e_pf_enable_irq0(hw);
4277         rte_intr_enable(&(dev->pci_dev->intr_handle));
4278 }
4279
4280 /**
4281  * Interrupt handler triggered by NIC  for handling
4282  * specific interrupt.
4283  *
4284  * @param handle
4285  *  Pointer to interrupt handle.
4286  * @param param
4287  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4288  *
4289  * @return
4290  *  void
4291  */
4292 static void
4293 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4294                            void *param)
4295 {
4296         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4297         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4298         uint32_t icr0;
4299
4300         /* Disable interrupt */
4301         i40e_pf_disable_irq0(hw);
4302
4303         /* read out interrupt causes */
4304         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4305
4306         /* No interrupt event indicated */
4307         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4308                 PMD_DRV_LOG(INFO, "No interrupt event");
4309                 goto done;
4310         }
4311 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4312         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4313                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4314         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4315                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4316         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4317                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4318         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4319                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4320         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4321                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4322         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4323                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4324         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4325                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4326 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4327
4328         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4329                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4330                 i40e_dev_handle_vfr_event(dev);
4331         }
4332         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4333                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4334                 i40e_dev_handle_aq_msg(dev);
4335         }
4336
4337         /* Link Status Change interrupt */
4338         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4339 #define I40E_US_PER_SECOND 1000000
4340                 struct rte_eth_link link;
4341
4342                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4343                 memset(&link, 0, sizeof(link));
4344                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4345                 i40e_dev_link_update(dev, 0);
4346
4347                 /*
4348                  * For link up interrupt, it needs to wait 1 second to let the
4349                  * hardware be a stable state. Otherwise several consecutive
4350                  * interrupts can be observed.
4351                  * For link down interrupt, no need to wait.
4352                  */
4353                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4354                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4355                         return;
4356                 else
4357                         _rte_eth_dev_callback_process(dev,
4358                                 RTE_ETH_EVENT_INTR_LSC);
4359         }
4360
4361 done:
4362         /* Enable interrupt */
4363         i40e_pf_enable_irq0(hw);
4364         rte_intr_enable(&(dev->pci_dev->intr_handle));
4365 }
4366
4367 static int
4368 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4369                          struct i40e_macvlan_filter *filter,
4370                          int total)
4371 {
4372         int ele_num, ele_buff_size;
4373         int num, actual_num, i;
4374         uint16_t flags;
4375         int ret = I40E_SUCCESS;
4376         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4377         struct i40e_aqc_add_macvlan_element_data *req_list;
4378
4379         if (filter == NULL  || total == 0)
4380                 return I40E_ERR_PARAM;
4381         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4382         ele_buff_size = hw->aq.asq_buf_size;
4383
4384         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4385         if (req_list == NULL) {
4386                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4387                 return I40E_ERR_NO_MEMORY;
4388         }
4389
4390         num = 0;
4391         do {
4392                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4393                 memset(req_list, 0, ele_buff_size);
4394
4395                 for (i = 0; i < actual_num; i++) {
4396                         (void)rte_memcpy(req_list[i].mac_addr,
4397                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4398                         req_list[i].vlan_tag =
4399                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4400
4401                         switch (filter[num + i].filter_type) {
4402                         case RTE_MAC_PERFECT_MATCH:
4403                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4404                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4405                                 break;
4406                         case RTE_MACVLAN_PERFECT_MATCH:
4407                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4408                                 break;
4409                         case RTE_MAC_HASH_MATCH:
4410                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4411                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4412                                 break;
4413                         case RTE_MACVLAN_HASH_MATCH:
4414                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4415                                 break;
4416                         default:
4417                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4418                                 ret = I40E_ERR_PARAM;
4419                                 goto DONE;
4420                         }
4421
4422                         req_list[i].queue_number = 0;
4423
4424                         req_list[i].flags = rte_cpu_to_le_16(flags);
4425                 }
4426
4427                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4428                                                 actual_num, NULL);
4429                 if (ret != I40E_SUCCESS) {
4430                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4431                         goto DONE;
4432                 }
4433                 num += actual_num;
4434         } while (num < total);
4435
4436 DONE:
4437         rte_free(req_list);
4438         return ret;
4439 }
4440
4441 static int
4442 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4443                             struct i40e_macvlan_filter *filter,
4444                             int total)
4445 {
4446         int ele_num, ele_buff_size;
4447         int num, actual_num, i;
4448         uint16_t flags;
4449         int ret = I40E_SUCCESS;
4450         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4451         struct i40e_aqc_remove_macvlan_element_data *req_list;
4452
4453         if (filter == NULL  || total == 0)
4454                 return I40E_ERR_PARAM;
4455
4456         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4457         ele_buff_size = hw->aq.asq_buf_size;
4458
4459         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4460         if (req_list == NULL) {
4461                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4462                 return I40E_ERR_NO_MEMORY;
4463         }
4464
4465         num = 0;
4466         do {
4467                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4468                 memset(req_list, 0, ele_buff_size);
4469
4470                 for (i = 0; i < actual_num; i++) {
4471                         (void)rte_memcpy(req_list[i].mac_addr,
4472                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4473                         req_list[i].vlan_tag =
4474                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4475
4476                         switch (filter[num + i].filter_type) {
4477                         case RTE_MAC_PERFECT_MATCH:
4478                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4479                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4480                                 break;
4481                         case RTE_MACVLAN_PERFECT_MATCH:
4482                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4483                                 break;
4484                         case RTE_MAC_HASH_MATCH:
4485                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4486                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4487                                 break;
4488                         case RTE_MACVLAN_HASH_MATCH:
4489                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4490                                 break;
4491                         default:
4492                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4493                                 ret = I40E_ERR_PARAM;
4494                                 goto DONE;
4495                         }
4496                         req_list[i].flags = rte_cpu_to_le_16(flags);
4497                 }
4498
4499                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4500                                                 actual_num, NULL);
4501                 if (ret != I40E_SUCCESS) {
4502                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4503                         goto DONE;
4504                 }
4505                 num += actual_num;
4506         } while (num < total);
4507
4508 DONE:
4509         rte_free(req_list);
4510         return ret;
4511 }
4512
4513 /* Find out specific MAC filter */
4514 static struct i40e_mac_filter *
4515 i40e_find_mac_filter(struct i40e_vsi *vsi,
4516                          struct ether_addr *macaddr)
4517 {
4518         struct i40e_mac_filter *f;
4519
4520         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4521                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4522                         return f;
4523         }
4524
4525         return NULL;
4526 }
4527
4528 static bool
4529 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4530                          uint16_t vlan_id)
4531 {
4532         uint32_t vid_idx, vid_bit;
4533
4534         if (vlan_id > ETH_VLAN_ID_MAX)
4535                 return 0;
4536
4537         vid_idx = I40E_VFTA_IDX(vlan_id);
4538         vid_bit = I40E_VFTA_BIT(vlan_id);
4539
4540         if (vsi->vfta[vid_idx] & vid_bit)
4541                 return 1;
4542         else
4543                 return 0;
4544 }
4545
4546 static void
4547 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4548                          uint16_t vlan_id, bool on)
4549 {
4550         uint32_t vid_idx, vid_bit;
4551
4552         if (vlan_id > ETH_VLAN_ID_MAX)
4553                 return;
4554
4555         vid_idx = I40E_VFTA_IDX(vlan_id);
4556         vid_bit = I40E_VFTA_BIT(vlan_id);
4557
4558         if (on)
4559                 vsi->vfta[vid_idx] |= vid_bit;
4560         else
4561                 vsi->vfta[vid_idx] &= ~vid_bit;
4562 }
4563
4564 /**
4565  * Find all vlan options for specific mac addr,
4566  * return with actual vlan found.
4567  */
4568 static inline int
4569 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4570                            struct i40e_macvlan_filter *mv_f,
4571                            int num, struct ether_addr *addr)
4572 {
4573         int i;
4574         uint32_t j, k;
4575
4576         /**
4577          * Not to use i40e_find_vlan_filter to decrease the loop time,
4578          * although the code looks complex.
4579           */
4580         if (num < vsi->vlan_num)
4581                 return I40E_ERR_PARAM;
4582
4583         i = 0;
4584         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4585                 if (vsi->vfta[j]) {
4586                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4587                                 if (vsi->vfta[j] & (1 << k)) {
4588                                         if (i > num - 1) {
4589                                                 PMD_DRV_LOG(ERR, "vlan number "
4590                                                             "not match");
4591                                                 return I40E_ERR_PARAM;
4592                                         }
4593                                         (void)rte_memcpy(&mv_f[i].macaddr,
4594                                                         addr, ETH_ADDR_LEN);
4595                                         mv_f[i].vlan_id =
4596                                                 j * I40E_UINT32_BIT_SIZE + k;
4597                                         i++;
4598                                 }
4599                         }
4600                 }
4601         }
4602         return I40E_SUCCESS;
4603 }
4604
4605 static inline int
4606 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4607                            struct i40e_macvlan_filter *mv_f,
4608                            int num,
4609                            uint16_t vlan)
4610 {
4611         int i = 0;
4612         struct i40e_mac_filter *f;
4613
4614         if (num < vsi->mac_num)
4615                 return I40E_ERR_PARAM;
4616
4617         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4618                 if (i > num - 1) {
4619                         PMD_DRV_LOG(ERR, "buffer number not match");
4620                         return I40E_ERR_PARAM;
4621                 }
4622                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4623                                 ETH_ADDR_LEN);
4624                 mv_f[i].vlan_id = vlan;
4625                 mv_f[i].filter_type = f->mac_info.filter_type;
4626                 i++;
4627         }
4628
4629         return I40E_SUCCESS;
4630 }
4631
4632 static int
4633 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4634 {
4635         int i, num;
4636         struct i40e_mac_filter *f;
4637         struct i40e_macvlan_filter *mv_f;
4638         int ret = I40E_SUCCESS;
4639
4640         if (vsi == NULL || vsi->mac_num == 0)
4641                 return I40E_ERR_PARAM;
4642
4643         /* Case that no vlan is set */
4644         if (vsi->vlan_num == 0)
4645                 num = vsi->mac_num;
4646         else
4647                 num = vsi->mac_num * vsi->vlan_num;
4648
4649         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4650         if (mv_f == NULL) {
4651                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4652                 return I40E_ERR_NO_MEMORY;
4653         }
4654
4655         i = 0;
4656         if (vsi->vlan_num == 0) {
4657                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4658                         (void)rte_memcpy(&mv_f[i].macaddr,
4659                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4660                         mv_f[i].vlan_id = 0;
4661                         i++;
4662                 }
4663         } else {
4664                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4665                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4666                                         vsi->vlan_num, &f->mac_info.mac_addr);
4667                         if (ret != I40E_SUCCESS)
4668                                 goto DONE;
4669                         i += vsi->vlan_num;
4670                 }
4671         }
4672
4673         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4674 DONE:
4675         rte_free(mv_f);
4676
4677         return ret;
4678 }
4679
4680 int
4681 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4682 {
4683         struct i40e_macvlan_filter *mv_f;
4684         int mac_num;
4685         int ret = I40E_SUCCESS;
4686
4687         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4688                 return I40E_ERR_PARAM;
4689
4690         /* If it's already set, just return */
4691         if (i40e_find_vlan_filter(vsi,vlan))
4692                 return I40E_SUCCESS;
4693
4694         mac_num = vsi->mac_num;
4695
4696         if (mac_num == 0) {
4697                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4698                 return I40E_ERR_PARAM;
4699         }
4700
4701         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4702
4703         if (mv_f == NULL) {
4704                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4705                 return I40E_ERR_NO_MEMORY;
4706         }
4707
4708         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4709
4710         if (ret != I40E_SUCCESS)
4711                 goto DONE;
4712
4713         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4714
4715         if (ret != I40E_SUCCESS)
4716                 goto DONE;
4717
4718         i40e_set_vlan_filter(vsi, vlan, 1);
4719
4720         vsi->vlan_num++;
4721         ret = I40E_SUCCESS;
4722 DONE:
4723         rte_free(mv_f);
4724         return ret;
4725 }
4726
4727 int
4728 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4729 {
4730         struct i40e_macvlan_filter *mv_f;
4731         int mac_num;
4732         int ret = I40E_SUCCESS;
4733
4734         /**
4735          * Vlan 0 is the generic filter for untagged packets
4736          * and can't be removed.
4737          */
4738         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4739                 return I40E_ERR_PARAM;
4740
4741         /* If can't find it, just return */
4742         if (!i40e_find_vlan_filter(vsi, vlan))
4743                 return I40E_ERR_PARAM;
4744
4745         mac_num = vsi->mac_num;
4746
4747         if (mac_num == 0) {
4748                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4749                 return I40E_ERR_PARAM;
4750         }
4751
4752         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4753
4754         if (mv_f == NULL) {
4755                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4756                 return I40E_ERR_NO_MEMORY;
4757         }
4758
4759         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4760
4761         if (ret != I40E_SUCCESS)
4762                 goto DONE;
4763
4764         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4765
4766         if (ret != I40E_SUCCESS)
4767                 goto DONE;
4768
4769         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4770         if (vsi->vlan_num == 1) {
4771                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4772                 if (ret != I40E_SUCCESS)
4773                         goto DONE;
4774
4775                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4776                 if (ret != I40E_SUCCESS)
4777                         goto DONE;
4778         }
4779
4780         i40e_set_vlan_filter(vsi, vlan, 0);
4781
4782         vsi->vlan_num--;
4783         ret = I40E_SUCCESS;
4784 DONE:
4785         rte_free(mv_f);
4786         return ret;
4787 }
4788
4789 int
4790 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4791 {
4792         struct i40e_mac_filter *f;
4793         struct i40e_macvlan_filter *mv_f;
4794         int i, vlan_num = 0;
4795         int ret = I40E_SUCCESS;
4796
4797         /* If it's add and we've config it, return */
4798         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4799         if (f != NULL)
4800                 return I40E_SUCCESS;
4801         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4802                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4803
4804                 /**
4805                  * If vlan_num is 0, that's the first time to add mac,
4806                  * set mask for vlan_id 0.
4807                  */
4808                 if (vsi->vlan_num == 0) {
4809                         i40e_set_vlan_filter(vsi, 0, 1);
4810                         vsi->vlan_num = 1;
4811                 }
4812                 vlan_num = vsi->vlan_num;
4813         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4814                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4815                 vlan_num = 1;
4816
4817         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4818         if (mv_f == NULL) {
4819                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4820                 return I40E_ERR_NO_MEMORY;
4821         }
4822
4823         for (i = 0; i < vlan_num; i++) {
4824                 mv_f[i].filter_type = mac_filter->filter_type;
4825                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4826                                 ETH_ADDR_LEN);
4827         }
4828
4829         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4830                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4831                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4832                                         &mac_filter->mac_addr);
4833                 if (ret != I40E_SUCCESS)
4834                         goto DONE;
4835         }
4836
4837         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4838         if (ret != I40E_SUCCESS)
4839                 goto DONE;
4840
4841         /* Add the mac addr into mac list */
4842         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4843         if (f == NULL) {
4844                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4845                 ret = I40E_ERR_NO_MEMORY;
4846                 goto DONE;
4847         }
4848         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4849                         ETH_ADDR_LEN);
4850         f->mac_info.filter_type = mac_filter->filter_type;
4851         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4852         vsi->mac_num++;
4853
4854         ret = I40E_SUCCESS;
4855 DONE:
4856         rte_free(mv_f);
4857
4858         return ret;
4859 }
4860
4861 int
4862 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4863 {
4864         struct i40e_mac_filter *f;
4865         struct i40e_macvlan_filter *mv_f;
4866         int i, vlan_num;
4867         enum rte_mac_filter_type filter_type;
4868         int ret = I40E_SUCCESS;
4869
4870         /* Can't find it, return an error */
4871         f = i40e_find_mac_filter(vsi, addr);
4872         if (f == NULL)
4873                 return I40E_ERR_PARAM;
4874
4875         vlan_num = vsi->vlan_num;
4876         filter_type = f->mac_info.filter_type;
4877         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4878                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4879                 if (vlan_num == 0) {
4880                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4881                         return I40E_ERR_PARAM;
4882                 }
4883         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4884                         filter_type == RTE_MAC_HASH_MATCH)
4885                 vlan_num = 1;
4886
4887         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4888         if (mv_f == NULL) {
4889                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4890                 return I40E_ERR_NO_MEMORY;
4891         }
4892
4893         for (i = 0; i < vlan_num; i++) {
4894                 mv_f[i].filter_type = filter_type;
4895                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4896                                 ETH_ADDR_LEN);
4897         }
4898         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4899                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4900                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4901                 if (ret != I40E_SUCCESS)
4902                         goto DONE;
4903         }
4904
4905         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4906         if (ret != I40E_SUCCESS)
4907                 goto DONE;
4908
4909         /* Remove the mac addr into mac list */
4910         TAILQ_REMOVE(&vsi->mac_list, f, next);
4911         rte_free(f);
4912         vsi->mac_num--;
4913
4914         ret = I40E_SUCCESS;
4915 DONE:
4916         rte_free(mv_f);
4917         return ret;
4918 }
4919
4920 /* Configure hash enable flags for RSS */
4921 uint64_t
4922 i40e_config_hena(uint64_t flags)
4923 {
4924         uint64_t hena = 0;
4925
4926         if (!flags)
4927                 return hena;
4928
4929         if (flags & ETH_RSS_FRAG_IPV4)
4930                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4931         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4932                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4933         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4934                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4935         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4936                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4937         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4938                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4939         if (flags & ETH_RSS_FRAG_IPV6)
4940                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4941         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4942                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4943         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4944                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4945         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4946                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4947         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4948                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4949         if (flags & ETH_RSS_L2_PAYLOAD)
4950                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4951
4952         return hena;
4953 }
4954
4955 /* Parse the hash enable flags */
4956 uint64_t
4957 i40e_parse_hena(uint64_t flags)
4958 {
4959         uint64_t rss_hf = 0;
4960
4961         if (!flags)
4962                 return rss_hf;
4963         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4964                 rss_hf |= ETH_RSS_FRAG_IPV4;
4965         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4966                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4967         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4968                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4969         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4970                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4971         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4972                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4973         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4974                 rss_hf |= ETH_RSS_FRAG_IPV6;
4975         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4976                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4977         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4978                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4979         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4980                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4981         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4982                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4983         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4984                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4985
4986         return rss_hf;
4987 }
4988
4989 /* Disable RSS */
4990 static void
4991 i40e_pf_disable_rss(struct i40e_pf *pf)
4992 {
4993         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4994         uint64_t hena;
4995
4996         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4997         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4998         hena &= ~I40E_RSS_HENA_ALL;
4999         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5000         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5001         I40E_WRITE_FLUSH(hw);
5002 }
5003
5004 static int
5005 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
5006 {
5007         uint32_t *hash_key;
5008         uint8_t hash_key_len;
5009         uint64_t rss_hf;
5010         uint16_t i;
5011         uint64_t hena;
5012
5013         hash_key = (uint32_t *)(rss_conf->rss_key);
5014         hash_key_len = rss_conf->rss_key_len;
5015         if (hash_key != NULL && hash_key_len >=
5016                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5017                 /* Fill in RSS hash key */
5018                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5019                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5020         }
5021
5022         rss_hf = rss_conf->rss_hf;
5023         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5024         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5025         hena &= ~I40E_RSS_HENA_ALL;
5026         hena |= i40e_config_hena(rss_hf);
5027         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5028         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5029         I40E_WRITE_FLUSH(hw);
5030
5031         return 0;
5032 }
5033
5034 static int
5035 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5036                          struct rte_eth_rss_conf *rss_conf)
5037 {
5038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5040         uint64_t hena;
5041
5042         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5043         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5044         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5045                 if (rss_hf != 0) /* Enable RSS */
5046                         return -EINVAL;
5047                 return 0; /* Nothing to do */
5048         }
5049         /* RSS enabled */
5050         if (rss_hf == 0) /* Disable RSS */
5051                 return -EINVAL;
5052
5053         return i40e_hw_rss_hash_set(hw, rss_conf);
5054 }
5055
5056 static int
5057 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5058                            struct rte_eth_rss_conf *rss_conf)
5059 {
5060         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5061         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
5062         uint64_t hena;
5063         uint16_t i;
5064
5065         if (hash_key != NULL) {
5066                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5067                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5068                 rss_conf->rss_key_len = i * sizeof(uint32_t);
5069         }
5070         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5071         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5072         rss_conf->rss_hf = i40e_parse_hena(hena);
5073
5074         return 0;
5075 }
5076
5077 static int
5078 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5079 {
5080         switch (filter_type) {
5081         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5082                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5083                 break;
5084         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5085                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5086                 break;
5087         case RTE_TUNNEL_FILTER_IMAC_TENID:
5088                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5089                 break;
5090         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5091                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5092                 break;
5093         case ETH_TUNNEL_FILTER_IMAC:
5094                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5095                 break;
5096         default:
5097                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5098                 return -EINVAL;
5099         }
5100
5101         return 0;
5102 }
5103
5104 static int
5105 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5106                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5107                         uint8_t add)
5108 {
5109         uint16_t ip_type;
5110         uint8_t tun_type = 0;
5111         int val, ret = 0;
5112         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5113         struct i40e_vsi *vsi = pf->main_vsi;
5114         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5115         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5116
5117         cld_filter = rte_zmalloc("tunnel_filter",
5118                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5119                 0);
5120
5121         if (NULL == cld_filter) {
5122                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5123                 return -EINVAL;
5124         }
5125         pfilter = cld_filter;
5126
5127         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5128                         sizeof(struct ether_addr));
5129         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5130                         sizeof(struct ether_addr));
5131
5132         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5133         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5134                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5135                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5136                                 &tunnel_filter->ip_addr,
5137                                 sizeof(pfilter->ipaddr.v4.data));
5138         } else {
5139                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5140                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5141                                 &tunnel_filter->ip_addr,
5142                                 sizeof(pfilter->ipaddr.v6.data));
5143         }
5144
5145         /* check tunneled type */
5146         switch (tunnel_filter->tunnel_type) {
5147         case RTE_TUNNEL_TYPE_VXLAN:
5148                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5149                 break;
5150         case RTE_TUNNEL_TYPE_NVGRE:
5151                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5152                 break;
5153         default:
5154                 /* Other tunnel types is not supported. */
5155                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5156                 rte_free(cld_filter);
5157                 return -EINVAL;
5158         }
5159
5160         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5161                                                 &pfilter->flags);
5162         if (val < 0) {
5163                 rte_free(cld_filter);
5164                 return -EINVAL;
5165         }
5166
5167         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5168                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5169         pfilter->tenant_id = tunnel_filter->tenant_id;
5170         pfilter->queue_number = tunnel_filter->queue_id;
5171
5172         if (add)
5173                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5174         else
5175                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5176                                                 cld_filter, 1);
5177
5178         rte_free(cld_filter);
5179         return ret;
5180 }
5181
5182 static int
5183 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5184 {
5185         uint8_t i;
5186
5187         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5188                 if (pf->vxlan_ports[i] == port)
5189                         return i;
5190         }
5191
5192         return -1;
5193 }
5194
5195 static int
5196 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5197 {
5198         int  idx, ret;
5199         uint8_t filter_idx;
5200         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5201
5202         idx = i40e_get_vxlan_port_idx(pf, port);
5203
5204         /* Check if port already exists */
5205         if (idx >= 0) {
5206                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5207                 return -EINVAL;
5208         }
5209
5210         /* Now check if there is space to add the new port */
5211         idx = i40e_get_vxlan_port_idx(pf, 0);
5212         if (idx < 0) {
5213                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5214                         "not adding port %d", port);
5215                 return -ENOSPC;
5216         }
5217
5218         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5219                                         &filter_idx, NULL);
5220         if (ret < 0) {
5221                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5222                 return -1;
5223         }
5224
5225         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5226                          port,  filter_idx);
5227
5228         /* New port: add it and mark its index in the bitmap */
5229         pf->vxlan_ports[idx] = port;
5230         pf->vxlan_bitmap |= (1 << idx);
5231
5232         if (!(pf->flags & I40E_FLAG_VXLAN))
5233                 pf->flags |= I40E_FLAG_VXLAN;
5234
5235         return 0;
5236 }
5237
5238 static int
5239 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5240 {
5241         int idx;
5242         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5243
5244         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5245                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5246                 return -EINVAL;
5247         }
5248
5249         idx = i40e_get_vxlan_port_idx(pf, port);
5250
5251         if (idx < 0) {
5252                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5253                 return -EINVAL;
5254         }
5255
5256         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5257                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5258                 return -1;
5259         }
5260
5261         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5262                         port, idx);
5263
5264         pf->vxlan_ports[idx] = 0;
5265         pf->vxlan_bitmap &= ~(1 << idx);
5266
5267         if (!pf->vxlan_bitmap)
5268                 pf->flags &= ~I40E_FLAG_VXLAN;
5269
5270         return 0;
5271 }
5272
5273 /* Add UDP tunneling port */
5274 static int
5275 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5276                         struct rte_eth_udp_tunnel *udp_tunnel)
5277 {
5278         int ret = 0;
5279         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5280
5281         if (udp_tunnel == NULL)
5282                 return -EINVAL;
5283
5284         switch (udp_tunnel->prot_type) {
5285         case RTE_TUNNEL_TYPE_VXLAN:
5286                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5287                 break;
5288
5289         case RTE_TUNNEL_TYPE_GENEVE:
5290         case RTE_TUNNEL_TYPE_TEREDO:
5291                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5292                 ret = -1;
5293                 break;
5294
5295         default:
5296                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5297                 ret = -1;
5298                 break;
5299         }
5300
5301         return ret;
5302 }
5303
5304 /* Remove UDP tunneling port */
5305 static int
5306 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5307                         struct rte_eth_udp_tunnel *udp_tunnel)
5308 {
5309         int ret = 0;
5310         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5311
5312         if (udp_tunnel == NULL)
5313                 return -EINVAL;
5314
5315         switch (udp_tunnel->prot_type) {
5316         case RTE_TUNNEL_TYPE_VXLAN:
5317                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5318                 break;
5319         case RTE_TUNNEL_TYPE_GENEVE:
5320         case RTE_TUNNEL_TYPE_TEREDO:
5321                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5322                 ret = -1;
5323                 break;
5324         default:
5325                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5326                 ret = -1;
5327                 break;
5328         }
5329
5330         return ret;
5331 }
5332
5333 /* Calculate the maximum number of contiguous PF queues that are configured */
5334 static int
5335 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5336 {
5337         struct rte_eth_dev_data *data = pf->dev_data;
5338         int i, num;
5339         struct i40e_rx_queue *rxq;
5340
5341         num = 0;
5342         for (i = 0; i < pf->lan_nb_qps; i++) {
5343                 rxq = data->rx_queues[i];
5344                 if (rxq && rxq->q_set)
5345                         num++;
5346                 else
5347                         break;
5348         }
5349
5350         return num;
5351 }
5352
5353 /* Configure RSS */
5354 static int
5355 i40e_pf_config_rss(struct i40e_pf *pf)
5356 {
5357         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5358         struct rte_eth_rss_conf rss_conf;
5359         uint32_t i, lut = 0;
5360         uint16_t j, num;
5361
5362         /*
5363          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5364          * It's necessary to calulate the actual PF queues that are configured.
5365          */
5366         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5367                 num = i40e_pf_calc_configured_queues_num(pf);
5368                 num = i40e_align_floor(num);
5369         } else
5370                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5371
5372         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5373                         num);
5374
5375         if (num == 0) {
5376                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5377                 return -ENOTSUP;
5378         }
5379
5380         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5381                 if (j == num)
5382                         j = 0;
5383                 lut = (lut << 8) | (j & ((0x1 <<
5384                         hw->func_caps.rss_table_entry_width) - 1));
5385                 if ((i & 3) == 3)
5386                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5387         }
5388
5389         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5390         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5391                 i40e_pf_disable_rss(pf);
5392                 return 0;
5393         }
5394         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5395                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5396                 /* Random default keys */
5397                 static uint32_t rss_key_default[] = {0x6b793944,
5398                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5399                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5400                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5401
5402                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5403                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5404                                                         sizeof(uint32_t);
5405         }
5406
5407         return i40e_hw_rss_hash_set(hw, &rss_conf);
5408 }
5409
5410 static int
5411 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5412                         struct rte_eth_tunnel_filter_conf *filter)
5413 {
5414         if (pf == NULL || filter == NULL) {
5415                 PMD_DRV_LOG(ERR, "Invalid parameter");
5416                 return -EINVAL;
5417         }
5418
5419         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5420                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5421                 return -EINVAL;
5422         }
5423
5424         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5425                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5426                 return -EINVAL;
5427         }
5428
5429         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5430                 (is_zero_ether_addr(filter->outer_mac))) {
5431                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5432                 return -EINVAL;
5433         }
5434
5435         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5436                 (is_zero_ether_addr(filter->inner_mac))) {
5437                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5438                 return -EINVAL;
5439         }
5440
5441         return 0;
5442 }
5443
5444 static int
5445 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5446                         void *arg)
5447 {
5448         struct rte_eth_tunnel_filter_conf *filter;
5449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5450         int ret = I40E_SUCCESS;
5451
5452         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5453
5454         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5455                 return I40E_ERR_PARAM;
5456
5457         switch (filter_op) {
5458         case RTE_ETH_FILTER_NOP:
5459                 if (!(pf->flags & I40E_FLAG_VXLAN))
5460                         ret = I40E_NOT_SUPPORTED;
5461         case RTE_ETH_FILTER_ADD:
5462                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5463                 break;
5464         case RTE_ETH_FILTER_DELETE:
5465                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5466                 break;
5467         default:
5468                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5469                 ret = I40E_ERR_PARAM;
5470                 break;
5471         }
5472
5473         return ret;
5474 }
5475
5476 static int
5477 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5478 {
5479         int ret = 0;
5480         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5481
5482         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5483                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5484                 return -ENOTSUP;
5485         }
5486
5487         /* RSS setup */
5488         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5489                 ret = i40e_pf_config_rss(pf);
5490         else
5491                 i40e_pf_disable_rss(pf);
5492
5493         return ret;
5494 }
5495
5496 /* Get the symmetric hash enable configurations per port */
5497 static void
5498 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5499 {
5500         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5501
5502         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5503 }
5504
5505 /* Set the symmetric hash enable configurations per port */
5506 static void
5507 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5508 {
5509         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5510
5511         if (enable > 0) {
5512                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5513                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5514                                                         "been enabled");
5515                         return;
5516                 }
5517                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5518         } else {
5519                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5520                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5521                                                         "been disabled");
5522                         return;
5523                 }
5524                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5525         }
5526         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5527         I40E_WRITE_FLUSH(hw);
5528 }
5529
5530 /*
5531  * Get global configurations of hash function type and symmetric hash enable
5532  * per flow type (pctype). Note that global configuration means it affects all
5533  * the ports on the same NIC.
5534  */
5535 static int
5536 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5537                                    struct rte_eth_hash_global_conf *g_cfg)
5538 {
5539         uint32_t reg, mask = I40E_FLOW_TYPES;
5540         uint16_t i;
5541         enum i40e_filter_pctype pctype;
5542
5543         memset(g_cfg, 0, sizeof(*g_cfg));
5544         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5545         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5546                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5547         else
5548                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5549         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5550                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5551
5552         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5553                 if (!(mask & (1UL << i)))
5554                         continue;
5555                 mask &= ~(1UL << i);
5556                 /* Bit set indicats the coresponding flow type is supported */
5557                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5558                 pctype = i40e_flowtype_to_pctype(i);
5559                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5560                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5561                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5562         }
5563
5564         return 0;
5565 }
5566
5567 static int
5568 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5569 {
5570         uint32_t i;
5571         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5572
5573         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5574                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5575                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5576                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5577                                                 g_cfg->hash_func);
5578                 return -EINVAL;
5579         }
5580
5581         /*
5582          * As i40e supports less than 32 flow types, only first 32 bits need to
5583          * be checked.
5584          */
5585         mask0 = g_cfg->valid_bit_mask[0];
5586         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5587                 if (i == 0) {
5588                         /* Check if any unsupported flow type configured */
5589                         if ((mask0 | i40e_mask) ^ i40e_mask)
5590                                 goto mask_err;
5591                 } else {
5592                         if (g_cfg->valid_bit_mask[i])
5593                                 goto mask_err;
5594                 }
5595         }
5596
5597         return 0;
5598
5599 mask_err:
5600         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5601
5602         return -EINVAL;
5603 }
5604
5605 /*
5606  * Set global configurations of hash function type and symmetric hash enable
5607  * per flow type (pctype). Note any modifying global configuration will affect
5608  * all the ports on the same NIC.
5609  */
5610 static int
5611 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5612                                    struct rte_eth_hash_global_conf *g_cfg)
5613 {
5614         int ret;
5615         uint16_t i;
5616         uint32_t reg;
5617         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5618         enum i40e_filter_pctype pctype;
5619
5620         /* Check the input parameters */
5621         ret = i40e_hash_global_config_check(g_cfg);
5622         if (ret < 0)
5623                 return ret;
5624
5625         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5626                 if (!(mask0 & (1UL << i)))
5627                         continue;
5628                 mask0 &= ~(1UL << i);
5629                 pctype = i40e_flowtype_to_pctype(i);
5630                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5631                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5632                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5633         }
5634
5635         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5636         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5637                 /* Toeplitz */
5638                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5639                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5640                                                                 "Toeplitz");
5641                         goto out;
5642                 }
5643                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5644         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5645                 /* Simple XOR */
5646                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5647                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5648                                                         "Simple XOR");
5649                         goto out;
5650                 }
5651                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5652         } else
5653                 /* Use the default, and keep it as it is */
5654                 goto out;
5655
5656         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5657
5658 out:
5659         I40E_WRITE_FLUSH(hw);
5660
5661         return 0;
5662 }
5663
5664 static int
5665 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5666 {
5667         int ret = 0;
5668
5669         if (!hw || !info) {
5670                 PMD_DRV_LOG(ERR, "Invalid pointer");
5671                 return -EFAULT;
5672         }
5673
5674         switch (info->info_type) {
5675         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5676                 i40e_get_symmetric_hash_enable_per_port(hw,
5677                                         &(info->info.enable));
5678                 break;
5679         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5680                 ret = i40e_get_hash_filter_global_config(hw,
5681                                 &(info->info.global_conf));
5682                 break;
5683         default:
5684                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5685                                                         info->info_type);
5686                 ret = -EINVAL;
5687                 break;
5688         }
5689
5690         return ret;
5691 }
5692
5693 static int
5694 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5695 {
5696         int ret = 0;
5697
5698         if (!hw || !info) {
5699                 PMD_DRV_LOG(ERR, "Invalid pointer");
5700                 return -EFAULT;
5701         }
5702
5703         switch (info->info_type) {
5704         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5705                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5706                 break;
5707         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5708                 ret = i40e_set_hash_filter_global_config(hw,
5709                                 &(info->info.global_conf));
5710                 break;
5711         default:
5712                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5713                                                         info->info_type);
5714                 ret = -EINVAL;
5715                 break;
5716         }
5717
5718         return ret;
5719 }
5720
5721 /* Operations for hash function */
5722 static int
5723 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5724                       enum rte_filter_op filter_op,
5725                       void *arg)
5726 {
5727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728         int ret = 0;
5729
5730         switch (filter_op) {
5731         case RTE_ETH_FILTER_NOP:
5732                 break;
5733         case RTE_ETH_FILTER_GET:
5734                 ret = i40e_hash_filter_get(hw,
5735                         (struct rte_eth_hash_filter_info *)arg);
5736                 break;
5737         case RTE_ETH_FILTER_SET:
5738                 ret = i40e_hash_filter_set(hw,
5739                         (struct rte_eth_hash_filter_info *)arg);
5740                 break;
5741         default:
5742                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5743                                                                 filter_op);
5744                 ret = -ENOTSUP;
5745                 break;
5746         }
5747
5748         return ret;
5749 }
5750
5751 /*
5752  * Configure ethertype filter, which can director packet by filtering
5753  * with mac address and ether_type or only ether_type
5754  */
5755 static int
5756 i40e_ethertype_filter_set(struct i40e_pf *pf,
5757                         struct rte_eth_ethertype_filter *filter,
5758                         bool add)
5759 {
5760         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5761         struct i40e_control_filter_stats stats;
5762         uint16_t flags = 0;
5763         int ret;
5764
5765         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5766                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5767                 return -EINVAL;
5768         }
5769         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5770                 filter->ether_type == ETHER_TYPE_IPv6) {
5771                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5772                         " control packet filter.", filter->ether_type);
5773                 return -EINVAL;
5774         }
5775         if (filter->ether_type == ETHER_TYPE_VLAN)
5776                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5777                         " not supported.");
5778
5779         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5780                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5781         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5782                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5783         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5784
5785         memset(&stats, 0, sizeof(stats));
5786         ret = i40e_aq_add_rem_control_packet_filter(hw,
5787                         filter->mac_addr.addr_bytes,
5788                         filter->ether_type, flags,
5789                         pf->main_vsi->seid,
5790                         filter->queue, add, &stats, NULL);
5791
5792         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5793                          " mac_etype_used = %u, etype_used = %u,"
5794                          " mac_etype_free = %u, etype_free = %u\n",
5795                          ret, stats.mac_etype_used, stats.etype_used,
5796                          stats.mac_etype_free, stats.etype_free);
5797         if (ret < 0)
5798                 return -ENOSYS;
5799         return 0;
5800 }
5801
5802 /*
5803  * Handle operations for ethertype filter.
5804  */
5805 static int
5806 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5807                                 enum rte_filter_op filter_op,
5808                                 void *arg)
5809 {
5810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5811         int ret = 0;
5812
5813         if (filter_op == RTE_ETH_FILTER_NOP)
5814                 return ret;
5815
5816         if (arg == NULL) {
5817                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5818                             filter_op);
5819                 return -EINVAL;
5820         }
5821
5822         switch (filter_op) {
5823         case RTE_ETH_FILTER_ADD:
5824                 ret = i40e_ethertype_filter_set(pf,
5825                         (struct rte_eth_ethertype_filter *)arg,
5826                         TRUE);
5827                 break;
5828         case RTE_ETH_FILTER_DELETE:
5829                 ret = i40e_ethertype_filter_set(pf,
5830                         (struct rte_eth_ethertype_filter *)arg,
5831                         FALSE);
5832                 break;
5833         default:
5834                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5835                 ret = -ENOSYS;
5836                 break;
5837         }
5838         return ret;
5839 }
5840
5841 static int
5842 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5843                      enum rte_filter_type filter_type,
5844                      enum rte_filter_op filter_op,
5845                      void *arg)
5846 {
5847         int ret = 0;
5848
5849         if (dev == NULL)
5850                 return -EINVAL;
5851
5852         switch (filter_type) {
5853         case RTE_ETH_FILTER_HASH:
5854                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5855                 break;
5856         case RTE_ETH_FILTER_MACVLAN:
5857                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5858                 break;
5859         case RTE_ETH_FILTER_ETHERTYPE:
5860                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5861                 break;
5862         case RTE_ETH_FILTER_TUNNEL:
5863                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5864                 break;
5865         case RTE_ETH_FILTER_FDIR:
5866                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5867                 break;
5868         default:
5869                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5870                                                         filter_type);
5871                 ret = -EINVAL;
5872                 break;
5873         }
5874
5875         return ret;
5876 }
5877
5878 /*
5879  * As some registers wouldn't be reset unless a global hardware reset,
5880  * hardware initialization is needed to put those registers into an
5881  * expected initial state.
5882  */
5883 static void
5884 i40e_hw_init(struct i40e_hw *hw)
5885 {
5886         /* clear the PF Queue Filter control register */
5887         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5888
5889         /* Disable symmetric hash per port */
5890         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5891 }
5892
5893 enum i40e_filter_pctype
5894 i40e_flowtype_to_pctype(uint16_t flow_type)
5895 {
5896         static const enum i40e_filter_pctype pctype_table[] = {
5897                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5898                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5899                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5900                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5901                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5902                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5903                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5904                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5905                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5906                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5907                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5908                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5909                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5910                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5911                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5912                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5913                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5914                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5915                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5916         };
5917
5918         return pctype_table[flow_type];
5919 }
5920
5921 uint16_t
5922 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5923 {
5924         static const uint16_t flowtype_table[] = {
5925                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5926                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5927                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5928                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5929                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5930                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5931                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5932                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5933                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5934                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5935                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5936                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5937                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5938                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5939                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5940                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5941                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5942                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5943                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5944         };
5945
5946         return flowtype_table[pctype];
5947 }
5948
5949 /*
5950  * On X710, performance number is far from the expectation on recent firmware
5951  * versions; on XL710, performance number is also far from the expectation on
5952  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5953  * mode is enabled and port MAC address is equal to the packet destination MAC
5954  * address. The fix for this issue may not be integrated in the following
5955  * firmware version. So the workaround in software driver is needed. It needs
5956  * to modify the initial values of 3 internal only registers for both X710 and
5957  * XL710. Note that the values for X710 or XL710 could be different, and the
5958  * workaround can be removed when it is fixed in firmware in the future.
5959  */
5960
5961 /* For both X710 and XL710 */
5962 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5963 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5964
5965 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5966 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5967
5968 /* For X710 */
5969 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5970 /* For XL710 */
5971 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5972 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5973
5974 static void
5975 i40e_configure_registers(struct i40e_hw *hw)
5976 {
5977         static struct {
5978                 uint32_t addr;
5979                 uint64_t val;
5980         } reg_table[] = {
5981                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5982                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5983                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5984         };
5985         uint64_t reg;
5986         uint32_t i;
5987         int ret;
5988
5989         for (i = 0; i < RTE_DIM(reg_table); i++) {
5990                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5991                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5992                                 reg_table[i].val =
5993                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5994                         else /* For X710 */
5995                                 reg_table[i].val =
5996                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5997                 }
5998
5999                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
6000                                                         &reg, NULL);
6001                 if (ret < 0) {
6002                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
6003                                                         reg_table[i].addr);
6004                         break;
6005                 }
6006                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
6007                                                 reg_table[i].addr, reg);
6008                 if (reg == reg_table[i].val)
6009                         continue;
6010
6011                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
6012                                                 reg_table[i].val, NULL);
6013                 if (ret < 0) {
6014                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
6015                                 "address of 0x%"PRIx32, reg_table[i].val,
6016                                                         reg_table[i].addr);
6017                         break;
6018                 }
6019                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6020                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6021         }
6022 }
6023
6024 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
6025 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
6026 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
6027 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6028 static int
6029 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6030 {
6031         uint32_t reg;
6032         int ret;
6033
6034         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6035                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6036                 return -EINVAL;
6037         }
6038
6039         /* Configure for double VLAN RX stripping */
6040         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6041         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6042                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6043                 ret = i40e_aq_debug_write_register(hw,
6044                                                    I40E_VSI_TSR(vsi->vsi_id),
6045                                                    reg, NULL);
6046                 if (ret < 0) {
6047                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6048                                     vsi->vsi_id);
6049                         return I40E_ERR_CONFIG;
6050                 }
6051         }
6052
6053         /* Configure for double VLAN TX insertion */
6054         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6055         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6056                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6057                 ret = i40e_aq_debug_write_register(hw,
6058                                                    I40E_VSI_L2TAGSTXVALID(
6059                                                    vsi->vsi_id), reg, NULL);
6060                 if (ret < 0) {
6061                         PMD_DRV_LOG(ERR, "Failed to update "
6062                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6063                         return I40E_ERR_CONFIG;
6064                 }
6065         }
6066
6067         return 0;
6068 }
6069
6070 /**
6071  * i40e_aq_add_mirror_rule
6072  * @hw: pointer to the hardware structure
6073  * @seid: VEB seid to add mirror rule to
6074  * @dst_id: destination vsi seid
6075  * @entries: Buffer which contains the entities to be mirrored
6076  * @count: number of entities contained in the buffer
6077  * @rule_id:the rule_id of the rule to be added
6078  *
6079  * Add a mirror rule for a given veb.
6080  *
6081  **/
6082 static enum i40e_status_code
6083 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6084                         uint16_t seid, uint16_t dst_id,
6085                         uint16_t rule_type, uint16_t *entries,
6086                         uint16_t count, uint16_t *rule_id)
6087 {
6088         struct i40e_aq_desc desc;
6089         struct i40e_aqc_add_delete_mirror_rule cmd;
6090         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6091                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6092                 &desc.params.raw;
6093         uint16_t buff_len;
6094         enum i40e_status_code status;
6095
6096         i40e_fill_default_direct_cmd_desc(&desc,
6097                                           i40e_aqc_opc_add_mirror_rule);
6098         memset(&cmd, 0, sizeof(cmd));
6099
6100         buff_len = sizeof(uint16_t) * count;
6101         desc.datalen = rte_cpu_to_le_16(buff_len);
6102         if (buff_len > 0)
6103                 desc.flags |= rte_cpu_to_le_16(
6104                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6105         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6106                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6107         cmd.num_entries = rte_cpu_to_le_16(count);
6108         cmd.seid = rte_cpu_to_le_16(seid);
6109         cmd.destination = rte_cpu_to_le_16(dst_id);
6110
6111         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6112         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6113         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6114                          "rule_id = %u"
6115                          " mirror_rules_used = %u, mirror_rules_free = %u,",
6116                          hw->aq.asq_last_status, resp->rule_id,
6117                          resp->mirror_rules_used, resp->mirror_rules_free);
6118         *rule_id = rte_le_to_cpu_16(resp->rule_id);
6119
6120         return status;
6121 }
6122
6123 /**
6124  * i40e_aq_del_mirror_rule
6125  * @hw: pointer to the hardware structure
6126  * @seid: VEB seid to add mirror rule to
6127  * @entries: Buffer which contains the entities to be mirrored
6128  * @count: number of entities contained in the buffer
6129  * @rule_id:the rule_id of the rule to be delete
6130  *
6131  * Delete a mirror rule for a given veb.
6132  *
6133  **/
6134 static enum i40e_status_code
6135 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6136                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6137                 uint16_t count, uint16_t rule_id)
6138 {
6139         struct i40e_aq_desc desc;
6140         struct i40e_aqc_add_delete_mirror_rule cmd;
6141         uint16_t buff_len = 0;
6142         enum i40e_status_code status;
6143         void *buff = NULL;
6144
6145         i40e_fill_default_direct_cmd_desc(&desc,
6146                                           i40e_aqc_opc_delete_mirror_rule);
6147         memset(&cmd, 0, sizeof(cmd));
6148         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6149                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6150                                                           I40E_AQ_FLAG_RD));
6151                 cmd.num_entries = count;
6152                 buff_len = sizeof(uint16_t) * count;
6153                 desc.datalen = rte_cpu_to_le_16(buff_len);
6154                 buff = (void *)entries;
6155         } else
6156                 /* rule id is filled in destination field for deleting mirror rule */
6157                 cmd.destination = rte_cpu_to_le_16(rule_id);
6158
6159         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6160                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6161         cmd.seid = rte_cpu_to_le_16(seid);
6162
6163         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6164         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6165
6166         return status;
6167 }
6168
6169 /**
6170  * i40e_mirror_rule_set
6171  * @dev: pointer to the hardware structure
6172  * @mirror_conf: mirror rule info
6173  * @sw_id: mirror rule's sw_id
6174  * @on: enable/disable
6175  *
6176  * set a mirror rule.
6177  *
6178  **/
6179 static int
6180 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6181                         struct rte_eth_mirror_conf *mirror_conf,
6182                         uint8_t sw_id, uint8_t on)
6183 {
6184         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6185         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6186         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6187         struct i40e_mirror_rule *parent = NULL;
6188         uint16_t seid, dst_seid, rule_id;
6189         uint16_t i, j = 0;
6190         int ret;
6191
6192         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6193
6194         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6195                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6196                         " without veb or vfs.");
6197                 return -ENOSYS;
6198         }
6199         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6200                 PMD_DRV_LOG(ERR, "mirror table is full.");
6201                 return -ENOSPC;
6202         }
6203         if (mirror_conf->dst_pool > pf->vf_num) {
6204                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6205                                  mirror_conf->dst_pool);
6206                 return -EINVAL;
6207         }
6208
6209         seid = pf->main_vsi->veb->seid;
6210
6211         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6212                 if (sw_id <= it->index) {
6213                         mirr_rule = it;
6214                         break;
6215                 }
6216                 parent = it;
6217         }
6218         if (mirr_rule && sw_id == mirr_rule->index) {
6219                 if (on) {
6220                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6221                         return -EEXIST;
6222                 } else {
6223                         ret = i40e_aq_del_mirror_rule(hw, seid,
6224                                         mirr_rule->rule_type,
6225                                         mirr_rule->entries,
6226                                         mirr_rule->num_entries, mirr_rule->id);
6227                         if (ret < 0) {
6228                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6229                                                    " ret = %d, aq_err = %d.",
6230                                                    ret, hw->aq.asq_last_status);
6231                                 return -ENOSYS;
6232                         }
6233                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6234                         rte_free(mirr_rule);
6235                         pf->nb_mirror_rule--;
6236                         return 0;
6237                 }
6238         } else if (!on) {
6239                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6240                 return -ENOENT;
6241         }
6242
6243         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6244                                 sizeof(struct i40e_mirror_rule) , 0);
6245         if (!mirr_rule) {
6246                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6247                 return I40E_ERR_NO_MEMORY;
6248         }
6249         switch (mirror_conf->rule_type) {
6250         case ETH_MIRROR_VLAN:
6251                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6252                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6253                                 mirr_rule->entries[j] =
6254                                         mirror_conf->vlan.vlan_id[i];
6255                                 j++;
6256                         }
6257                 }
6258                 if (j == 0) {
6259                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6260                         rte_free(mirr_rule);
6261                         return -EINVAL;
6262                 }
6263                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6264                 break;
6265         case ETH_MIRROR_VIRTUAL_POOL_UP:
6266         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6267                 /* check if the specified pool bit is out of range */
6268                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6269                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6270                         rte_free(mirr_rule);
6271                         return -EINVAL;
6272                 }
6273                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6274                         if (mirror_conf->pool_mask & (1ULL << i)) {
6275                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6276                                 j++;
6277                         }
6278                 }
6279                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6280                         /* add pf vsi to entries */
6281                         mirr_rule->entries[j] = pf->main_vsi_seid;
6282                         j++;
6283                 }
6284                 if (j == 0) {
6285                         PMD_DRV_LOG(ERR, "pool is not specified.");
6286                         rte_free(mirr_rule);
6287                         return -EINVAL;
6288                 }
6289                 /* egress and ingress in aq commands means from switch but not port */
6290                 mirr_rule->rule_type =
6291                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6292                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6293                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6294                 break;
6295         case ETH_MIRROR_UPLINK_PORT:
6296                 /* egress and ingress in aq commands means from switch but not port*/
6297                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6298                 break;
6299         case ETH_MIRROR_DOWNLINK_PORT:
6300                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6301                 break;
6302         default:
6303                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6304                         mirror_conf->rule_type);
6305                 rte_free(mirr_rule);
6306                 return -EINVAL;
6307         }
6308
6309         /* If the dst_pool is equal to vf_num, consider it as PF */
6310         if (mirror_conf->dst_pool == pf->vf_num)
6311                 dst_seid = pf->main_vsi_seid;
6312         else
6313                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6314
6315         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6316                                       mirr_rule->rule_type, mirr_rule->entries,
6317                                       j, &rule_id);
6318         if (ret < 0) {
6319                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6320                                    " ret = %d, aq_err = %d.",
6321                                    ret, hw->aq.asq_last_status);
6322                 rte_free(mirr_rule);
6323                 return -ENOSYS;
6324         }
6325
6326         mirr_rule->index = sw_id;
6327         mirr_rule->num_entries = j;
6328         mirr_rule->id = rule_id;
6329         mirr_rule->dst_vsi_seid = dst_seid;
6330
6331         if (parent)
6332                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6333         else
6334                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6335
6336         pf->nb_mirror_rule++;
6337         return 0;
6338 }
6339
6340 /**
6341  * i40e_mirror_rule_reset
6342  * @dev: pointer to the device
6343  * @sw_id: mirror rule's sw_id
6344  *
6345  * reset a mirror rule.
6346  *
6347  **/
6348 static int
6349 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6350 {
6351         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6353         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6354         uint16_t seid;
6355         int ret;
6356
6357         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6358
6359         seid = pf->main_vsi->veb->seid;
6360
6361         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6362                 if (sw_id == it->index) {
6363                         mirr_rule = it;
6364                         break;
6365                 }
6366         }
6367         if (mirr_rule) {
6368                 ret = i40e_aq_del_mirror_rule(hw, seid,
6369                                 mirr_rule->rule_type,
6370                                 mirr_rule->entries,
6371                                 mirr_rule->num_entries, mirr_rule->id);
6372                 if (ret < 0) {
6373                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6374                                            " status = %d, aq_err = %d.",
6375                                            ret, hw->aq.asq_last_status);
6376                         return -ENOSYS;
6377                 }
6378                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6379                 rte_free(mirr_rule);
6380                 pf->nb_mirror_rule--;
6381         } else {
6382                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6383                 return -ENOENT;
6384         }
6385         return 0;
6386 }
6387
6388 static int
6389 i40e_timesync_enable(struct rte_eth_dev *dev)
6390 {
6391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6392         struct rte_eth_link *link = &dev->data->dev_link;
6393         uint32_t tsync_ctl_l;
6394         uint32_t tsync_ctl_h;
6395         uint32_t tsync_inc_l;
6396         uint32_t tsync_inc_h;
6397
6398         switch (link->link_speed) {
6399         case ETH_LINK_SPEED_40G:
6400                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6401                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6402                 break;
6403         case ETH_LINK_SPEED_10G:
6404                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6405                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6406                 break;
6407         case ETH_LINK_SPEED_1000:
6408                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6409                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6410                 break;
6411         default:
6412                 tsync_inc_l = 0x0;
6413                 tsync_inc_h = 0x0;
6414         }
6415
6416         /* Clear timesync registers. */
6417         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6418         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6419         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6420         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6421         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6422         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6423         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6424
6425         /* Set the timesync increment value. */
6426         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6427         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6428
6429         /* Enable timestamping of PTP packets. */
6430         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6431         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6432
6433         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6434         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6435         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6436
6437         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6438         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6439
6440         return 0;
6441 }
6442
6443 static int
6444 i40e_timesync_disable(struct rte_eth_dev *dev)
6445 {
6446         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6447         uint32_t tsync_ctl_l;
6448         uint32_t tsync_ctl_h;
6449
6450         /* Disable timestamping of transmitted PTP packets. */
6451         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6452         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6453
6454         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6455         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6456
6457         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6458         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6459
6460         /* Set the timesync increment value. */
6461         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6462         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6463
6464         return 0;
6465 }
6466
6467 static int
6468 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6469                                 struct timespec *timestamp, uint32_t flags)
6470 {
6471         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6472         uint32_t sync_status;
6473         uint32_t rx_stmpl;
6474         uint32_t rx_stmph;
6475         uint32_t index = flags & 0x03;
6476
6477         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6478         if ((sync_status & (1 << index)) == 0)
6479                 return -EINVAL;
6480
6481         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6482         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6483
6484         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6485         timestamp->tv_nsec = 0;
6486
6487         return  0;
6488 }
6489
6490 static int
6491 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6492                                 struct timespec *timestamp)
6493 {
6494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6495         uint32_t sync_status;
6496         uint32_t tx_stmpl;
6497         uint32_t tx_stmph;
6498
6499         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6500         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6501                 return -EINVAL;
6502
6503         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6504         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6505
6506         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6507         timestamp->tv_nsec = 0;
6508
6509         return  0;
6510 }