drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 #define I40E_CLEAR_PXE_WAIT_MS     200
  66
  67 /* Maximun number of capability elements */
  68 #define I40E_MAX_CAP_ELE_NUM       128
  69
  70 /* Wait count and inteval */
  71 #define I40E_CHK_Q_ENA_COUNT       1000
  72 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  73
  74 /* Maximun number of VSI */
  75 #define I40E_MAX_NUM_VSIS          (384UL)
  76
  77 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  78
  79 /* Flow control default timer */
  80 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  81
  82 /* Flow control default high water */
  83 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  84
  85 /* Flow control default low water */
  86 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  87
  88 /* Flow control enable fwd bit */
  89 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  90
  91 /* Receive Packet Buffer size */
  92 #define I40E_RXPBSIZE (968 * 1024)
  93
  94 /* Kilobytes shift */
  95 #define I40E_KILOSHIFT 10
  96
  97 /* Receive Average Packet Size in Byte*/
  98 #define I40E_PACKET_AVERAGE_SIZE 128
  99
 100 /* Mask of PF interrupt causes */
 101 #define I40E_PFINT_ICR0_ENA_MASK ( \
 102                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 103                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 104                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 105                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 106                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 107                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 108                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 112
 113 #define I40E_FLOW_TYPES ( \
 114         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 115         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 116         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 125
 126 /* Additional timesync values. */
 127 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 128 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 129 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 130 #define I40E_PRTTSYN_TSYNENA     0x80000000
 131 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 132 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 133
 134 #define I40E_MAX_PERCENT            100
 135 #define I40E_DEFAULT_DCB_APP_NUM    1
 136 #define I40E_DEFAULT_DCB_APP_PRIO   3
 137
 138 #define I40E_INSET_NONE            0x00000000000000000ULL
 139
 140 /* bit0 ~ bit 7 */
 141 #define I40E_INSET_DMAC            0x0000000000000001ULL
 142 #define I40E_INSET_SMAC            0x0000000000000002ULL
 143 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 144 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 145 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 146
 147 /* bit 8 ~ bit 15 */
 148 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 149 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 150 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 151 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 152 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 153 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 154 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 155
 156 /* bit 16 ~ bit 31 */
 157 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 158 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 159 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 160 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 161 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 162 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 163 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 164 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 165
 166 /* bit 32 ~ bit 47, tunnel fields */
 167 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 168 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 169 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 170 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 171 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 172 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 173
 174 /* bit 48 ~ bit 55 */
 175 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 176
 177 /* bit 56 ~ bit 63, Flex Payload */
 178 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 179 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 180 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD \
 187         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 188         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 189         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 190         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 191
 192 /**
 193  * Below are values for writing un-exposed registers suggested
 194  * by silicon experts
 195  */
 196 /* Destination MAC address */
 197 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 198 /* Source MAC address */
 199 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 200 /* VLAN tag in the outer L2 header */
 201 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0080000000000000ULL
 202 /* VLAN tag in the inner L2 header */
 203 #define I40E_REG_INSET_L2_INNER_VLAN             0x0100000000000000ULL
 204 /* Source IPv4 address */
 205 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 206 /* Destination IPv4 address */
 207 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 208 /* IPv4 Type of Service (TOS) */
 209 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 210 /* IPv4 Protocol */
 211 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 212 /* Source IPv6 address */
 213 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 214 /* Destination IPv6 address */
 215 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 216 /* IPv6 Traffic Class (TC) */
 217 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 218 /* IPv6 Next Header */
 219 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 220 /* Source L4 port */
 221 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 222 /* Destination L4 port */
 223 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 224 /* SCTP verification tag */
 225 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 226 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 227 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 228 /* Source port of tunneling UDP */
 229 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 230 /* Destination port of tunneling UDP */
 231 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 232 /* UDP Tunneling ID, NVGRE/GRE key */
 233 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 234 /* Last ether type */
 235 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 236 /* Tunneling outer destination IPv4 address */
 237 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 238 /* Tunneling outer destination IPv6 address */
 239 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 240 /* 1st word of flex payload */
 241 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 242 /* 2nd word of flex payload */
 243 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 244 /* 3rd word of flex payload */
 245 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 246 /* 4th word of flex payload */
 247 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 248 /* 5th word of flex payload */
 249 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 250 /* 6th word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 252 /* 7th word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 254 /* 8th word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 256
 257 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 258
 259 #define I40E_TRANSLATE_INSET 0
 260 #define I40E_TRANSLATE_REG   1
 261
 262 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 263 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 264 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 265 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 266
 267 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 268 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 269 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 270         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 271
 272 /* PCI offset for querying capability */
 273 #define PCI_DEV_CAP_REG            0xA4
 274 /* PCI offset for enabling/disabling Extended Tag */
 275 #define PCI_DEV_CTRL_REG           0xA8
 276 /* Bit mask of Extended Tag capability */
 277 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 278 /* Bit shift of Extended Tag enable/disable */
 279 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 280 /* Bit mask of Extended Tag enable/disable */
 281 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 282
 283 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 284 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 285 static int i40e_dev_configure(struct rte_eth_dev *dev);
 286 static int i40e_dev_start(struct rte_eth_dev *dev);
 287 static void i40e_dev_stop(struct rte_eth_dev *dev);
 288 static void i40e_dev_close(struct rte_eth_dev *dev);
 289 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 290 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 291 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 292 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 293 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 294 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 295 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 296                                struct rte_eth_stats *stats);
 297 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 298                                struct rte_eth_xstats *xstats, unsigned n);
 299 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 300 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 301                                             uint16_t queue_id,
 302                                             uint8_t stat_idx,
 303                                             uint8_t is_rx);
 304 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 305                               struct rte_eth_dev_info *dev_info);
 306 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 307                                 uint16_t vlan_id,
 308                                 int on);
 309 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 310                               enum rte_vlan_type vlan_type,
 311                               uint16_t tpid);
 312 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 313 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 314                                       uint16_t queue,
 315                                       int on);
 316 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 317 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 318 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 319 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 320                               struct rte_eth_fc_conf *fc_conf);
 321 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 322                               struct rte_eth_fc_conf *fc_conf);
 323 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 324                                        struct rte_eth_pfc_conf *pfc_conf);
 325 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 326                           struct ether_addr *mac_addr,
 327                           uint32_t index,
 328                           uint32_t pool);
 329 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 330 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 331                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 332                                     uint16_t reta_size);
 333 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 334                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 335                                    uint16_t reta_size);
 336
 337 static int i40e_get_cap(struct i40e_hw *hw);
 338 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 339 static int i40e_pf_setup(struct i40e_pf *pf);
 340 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 341 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 342 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 343 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 344 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 345                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 346 static void i40e_stat_update_48(struct i40e_hw *hw,
 347                                uint32_t hireg,
 348                                uint32_t loreg,
 349                                bool offset_loaded,
 350                                uint64_t *offset,
 351                                uint64_t *stat);
 352 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 353 static void i40e_dev_interrupt_handler(
 354                 __rte_unused struct rte_intr_handle *handle, void *param);
 355 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 356                                 uint32_t base, uint32_t num);
 357 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 358 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 359                         uint32_t base);
 360 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 361                         uint16_t num);
 362 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 363 static int i40e_veb_release(struct i40e_veb *veb);
 364 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 365                                                 struct i40e_vsi *vsi);
 366 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 367 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 368 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 369                                              struct i40e_macvlan_filter *mv_f,
 370                                              int num,
 371                                              struct ether_addr *addr);
 372 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 373                                              struct i40e_macvlan_filter *mv_f,
 374                                              int num,
 375                                              uint16_t vlan);
 376 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 377 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 378                                     struct rte_eth_rss_conf *rss_conf);
 379 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 380                                       struct rte_eth_rss_conf *rss_conf);
 381 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 382                                         struct rte_eth_udp_tunnel *udp_tunnel);
 383 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 384                                         struct rte_eth_udp_tunnel *udp_tunnel);
 385 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 386                         struct rte_eth_ethertype_filter *filter,
 387                         bool add);
 388 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 389                                 enum rte_filter_op filter_op,
 390                                 void *arg);
 391 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 392                                 enum rte_filter_type filter_type,
 393                                 enum rte_filter_op filter_op,
 394                                 void *arg);
 395 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 396                                   struct rte_eth_dcb_info *dcb_info);
 397 static void i40e_configure_registers(struct i40e_hw *hw);
 398 static void i40e_hw_init(struct rte_eth_dev *dev);
 399 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 400 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 401                         struct rte_eth_mirror_conf *mirror_conf,
 402                         uint8_t sw_id, uint8_t on);
 403 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 404
 405 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 406 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 407 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 408                                            struct timespec *timestamp,
 409                                            uint32_t flags);
 410 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 411                                            struct timespec *timestamp);
 412 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 413
 414 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 415
 416 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 417                                    struct timespec *timestamp);
 418 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 419                                     const struct timespec *timestamp);
 420
 421 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 422                                          uint16_t queue_id);
 423 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 424                                           uint16_t queue_id);
 425
 426
 427 static const struct rte_pci_id pci_id_i40e_map[] = {
 428 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 429 #include "rte_pci_dev_ids.h"
 430 { .vendor_id = 0, /* sentinel */ },
 431 };
 432
 433 static const struct eth_dev_ops i40e_eth_dev_ops = {
 434         .dev_configure                = i40e_dev_configure,
 435         .dev_start                    = i40e_dev_start,
 436         .dev_stop                     = i40e_dev_stop,
 437         .dev_close                    = i40e_dev_close,
 438         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 439         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 440         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 441         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 442         .dev_set_link_up              = i40e_dev_set_link_up,
 443         .dev_set_link_down            = i40e_dev_set_link_down,
 444         .link_update                  = i40e_dev_link_update,
 445         .stats_get                    = i40e_dev_stats_get,
 446         .xstats_get                   = i40e_dev_xstats_get,
 447         .stats_reset                  = i40e_dev_stats_reset,
 448         .xstats_reset                 = i40e_dev_stats_reset,
 449         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 450         .dev_infos_get                = i40e_dev_info_get,
 451         .vlan_filter_set              = i40e_vlan_filter_set,
 452         .vlan_tpid_set                = i40e_vlan_tpid_set,
 453         .vlan_offload_set             = i40e_vlan_offload_set,
 454         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 455         .vlan_pvid_set                = i40e_vlan_pvid_set,
 456         .rx_queue_start               = i40e_dev_rx_queue_start,
 457         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 458         .tx_queue_start               = i40e_dev_tx_queue_start,
 459         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 460         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 461         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 462         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 463         .rx_queue_release             = i40e_dev_rx_queue_release,
 464         .rx_queue_count               = i40e_dev_rx_queue_count,
 465         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 466         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 467         .tx_queue_release             = i40e_dev_tx_queue_release,
 468         .dev_led_on                   = i40e_dev_led_on,
 469         .dev_led_off                  = i40e_dev_led_off,
 470         .flow_ctrl_get                = i40e_flow_ctrl_get,
 471         .flow_ctrl_set                = i40e_flow_ctrl_set,
 472         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 473         .mac_addr_add                 = i40e_macaddr_add,
 474         .mac_addr_remove              = i40e_macaddr_remove,
 475         .reta_update                  = i40e_dev_rss_reta_update,
 476         .reta_query                   = i40e_dev_rss_reta_query,
 477         .rss_hash_update              = i40e_dev_rss_hash_update,
 478         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 479         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 480         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 481         .filter_ctrl                  = i40e_dev_filter_ctrl,
 482         .rxq_info_get                 = i40e_rxq_info_get,
 483         .txq_info_get                 = i40e_txq_info_get,
 484         .mirror_rule_set              = i40e_mirror_rule_set,
 485         .mirror_rule_reset            = i40e_mirror_rule_reset,
 486         .timesync_enable              = i40e_timesync_enable,
 487         .timesync_disable             = i40e_timesync_disable,
 488         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 489         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 490         .get_dcb_info                 = i40e_dev_get_dcb_info,
 491         .timesync_adjust_time         = i40e_timesync_adjust_time,
 492         .timesync_read_time           = i40e_timesync_read_time,
 493         .timesync_write_time          = i40e_timesync_write_time,
 494 };
 495
 496 /* store statistics names and its offset in stats structure */
 497 struct rte_i40e_xstats_name_off {
 498         char name[RTE_ETH_XSTATS_NAME_SIZE];
 499         unsigned offset;
 500 };
 501
 502 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 503         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 504         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 505         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 506         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 507         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 508                 rx_unknown_protocol)},
 509         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 510         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 511         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 512         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 513 };
 514
 515 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 516                 sizeof(rte_i40e_stats_strings[0]))
 517
 518 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 519         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 520                 tx_dropped_link_down)},
 521         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 522         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 523                 illegal_bytes)},
 524         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 525         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 526                 mac_local_faults)},
 527         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 528                 mac_remote_faults)},
 529         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 530                 rx_length_errors)},
 531         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 532         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 533         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 534         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 535         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 536         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 537                 rx_size_127)},
 538         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 539                 rx_size_255)},
 540         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 541                 rx_size_511)},
 542         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 543                 rx_size_1023)},
 544         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 545                 rx_size_1522)},
 546         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 547                 rx_size_big)},
 548         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 549                 rx_undersize)},
 550         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_oversize)},
 552         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 553                 mac_short_packet_dropped)},
 554         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 555                 rx_fragments)},
 556         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 557         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 558         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 559                 tx_size_127)},
 560         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 561                 tx_size_255)},
 562         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 563                 tx_size_511)},
 564         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 565                 tx_size_1023)},
 566         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 567                 tx_size_1522)},
 568         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 569                 tx_size_big)},
 570         {"rx_flow_director_atr_match_packets",
 571                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 572         {"rx_flow_director_sb_match_packets",
 573                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 574         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 575                 tx_lpi_status)},
 576         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 577                 rx_lpi_status)},
 578         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 579                 tx_lpi_count)},
 580         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 581                 rx_lpi_count)},
 582 };
 583
 584 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 585                 sizeof(rte_i40e_hw_port_strings[0]))
 586
 587 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 588         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 589                 priority_xon_rx)},
 590         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 591                 priority_xoff_rx)},
 592 };
 593
 594 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 595                 sizeof(rte_i40e_rxq_prio_strings[0]))
 596
 597 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 598         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 599                 priority_xon_tx)},
 600         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 601                 priority_xoff_tx)},
 602         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 603                 priority_xon_2_xoff)},
 604 };
 605
 606 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 607                 sizeof(rte_i40e_txq_prio_strings[0]))
 608
 609 static struct eth_driver rte_i40e_pmd = {
 610         .pci_drv = {
 611                 .name = "rte_i40e_pmd",
 612                 .id_table = pci_id_i40e_map,
 613                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 614                         RTE_PCI_DRV_DETACHABLE,
 615         },
 616         .eth_dev_init = eth_i40e_dev_init,
 617         .eth_dev_uninit = eth_i40e_dev_uninit,
 618         .dev_private_size = sizeof(struct i40e_adapter),
 619 };
 620
 621 static inline int
 622 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 623                                      struct rte_eth_link *link)
 624 {
 625         struct rte_eth_link *dst = link;
 626         struct rte_eth_link *src = &(dev->data->dev_link);
 627
 628         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 629                                         *(uint64_t *)src) == 0)
 630                 return -1;
 631
 632         return 0;
 633 }
 634
 635 static inline int
 636 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 637                                       struct rte_eth_link *link)
 638 {
 639         struct rte_eth_link *dst = &(dev->data->dev_link);
 640         struct rte_eth_link *src = link;
 641
 642         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 643                                         *(uint64_t *)src) == 0)
 644                 return -1;
 645
 646         return 0;
 647 }
 648
 649 /*
 650  * Driver initialization routine.
 651  * Invoked once at EAL init time.
 652  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 653  */
 654 static int
 655 rte_i40e_pmd_init(const char *name __rte_unused,
 656                   const char *params __rte_unused)
 657 {
 658         PMD_INIT_FUNC_TRACE();
 659         rte_eth_driver_register(&rte_i40e_pmd);
 660
 661         return 0;
 662 }
 663
 664 static struct rte_driver rte_i40e_driver = {
 665         .type = PMD_PDEV,
 666         .init = rte_i40e_pmd_init,
 667 };
 668
 669 PMD_REGISTER_DRIVER(rte_i40e_driver);
 670
 671 /*
 672  * Initialize registers for flexible payload, which should be set by NVM.
 673  * This should be removed from code once it is fixed in NVM.
 674  */
 675 #ifndef I40E_GLQF_ORT
 676 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 677 #endif
 678 #ifndef I40E_GLQF_PIT
 679 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 680 #endif
 681
 682 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 683 {
 684         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 685         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 686         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 687         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 688         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 694
 695         /* GLQF_PIT Registers */
 696         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 697         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 698 }
 699
 700 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 701
 702 /*
 703  * Add a ethertype filter to drop all flow control frames transmitted
 704  * from VSIs.
 705 */
 706 static void
 707 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 708 {
 709         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 710         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 711                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 712                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 713         int ret;
 714
 715         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 716                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 717                                 pf->main_vsi_seid, 0,
 718                                 TRUE, NULL, NULL);
 719         if (ret)
 720                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 721                                   " frames from VSIs.");
 722 }
 723
 724 static int
 725 eth_i40e_dev_init(struct rte_eth_dev *dev)
 726 {
 727         struct rte_pci_device *pci_dev;
 728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 729         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 730         struct i40e_vsi *vsi;
 731         int ret;
 732         uint32_t len;
 733         uint8_t aq_fail = 0;
 734
 735         PMD_INIT_FUNC_TRACE();
 736
 737         dev->dev_ops = &i40e_eth_dev_ops;
 738         dev->rx_pkt_burst = i40e_recv_pkts;
 739         dev->tx_pkt_burst = i40e_xmit_pkts;
 740
 741         /* for secondary processes, we don't initialise any further as primary
 742          * has already done this work. Only check we don't need a different
 743          * RX function */
 744         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 745                 i40e_set_rx_function(dev);
 746                 i40e_set_tx_function(dev);
 747                 return 0;
 748         }
 749         pci_dev = dev->pci_dev;
 750
 751         rte_eth_copy_pci_info(dev, pci_dev);
 752
 753         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 754         pf->adapter->eth_dev = dev;
 755         pf->dev_data = dev->data;
 756
 757         hw->back = I40E_PF_TO_ADAPTER(pf);
 758         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 759         if (!hw->hw_addr) {
 760                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 761                              "as address is NULL");
 762                 return -ENODEV;
 763         }
 764
 765         hw->vendor_id = pci_dev->id.vendor_id;
 766         hw->device_id = pci_dev->id.device_id;
 767         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 768         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 769         hw->bus.device = pci_dev->addr.devid;
 770         hw->bus.func = pci_dev->addr.function;
 771         hw->adapter_stopped = 0;
 772
 773         /* Make sure all is clean before doing PF reset */
 774         i40e_clear_hw(hw);
 775
 776         /* Initialize the hardware */
 777         i40e_hw_init(dev);
 778
 779         /* Reset here to make sure all is clean for each PF */
 780         ret = i40e_pf_reset(hw);
 781         if (ret) {
 782                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 783                 return ret;
 784         }
 785
 786         /* Initialize the shared code (base driver) */
 787         ret = i40e_init_shared_code(hw);
 788         if (ret) {
 789                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 790                 return ret;
 791         }
 792
 793         /*
 794          * To work around the NVM issue,initialize registers
 795          * for flexible payload by software.
 796          * It should be removed once issues are fixed in NVM.
 797          */
 798         i40e_flex_payload_reg_init(hw);
 799
 800         /* Initialize the parameters for adminq */
 801         i40e_init_adminq_parameter(hw);
 802         ret = i40e_init_adminq(hw);
 803         if (ret != I40E_SUCCESS) {
 804                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 805                 return -EIO;
 806         }
 807         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 808                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 809                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 810                      ((hw->nvm.version >> 12) & 0xf),
 811                      ((hw->nvm.version >> 4) & 0xff),
 812                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 813
 814         /* Clear PXE mode */
 815         i40e_clear_pxe_mode(hw);
 816
 817         /*
 818          * On X710, performance number is far from the expectation on recent
 819          * firmware versions. The fix for this issue may not be integrated in
 820          * the following firmware version. So the workaround in software driver
 821          * is needed. It needs to modify the initial values of 3 internal only
 822          * registers. Note that the workaround can be removed when it is fixed
 823          * in firmware in the future.
 824          */
 825         i40e_configure_registers(hw);
 826
 827         /* Get hw capabilities */
 828         ret = i40e_get_cap(hw);
 829         if (ret != I40E_SUCCESS) {
 830                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 831                 goto err_get_capabilities;
 832         }
 833
 834         /* Initialize parameters for PF */
 835         ret = i40e_pf_parameter_init(dev);
 836         if (ret != 0) {
 837                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 838                 goto err_parameter_init;
 839         }
 840
 841         /* Initialize the queue management */
 842         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 843         if (ret < 0) {
 844                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 845                 goto err_qp_pool_init;
 846         }
 847         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 848                                 hw->func_caps.num_msix_vectors - 1);
 849         if (ret < 0) {
 850                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 851                 goto err_msix_pool_init;
 852         }
 853
 854         /* Initialize lan hmc */
 855         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 856                                 hw->func_caps.num_rx_qp, 0, 0);
 857         if (ret != I40E_SUCCESS) {
 858                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 859                 goto err_init_lan_hmc;
 860         }
 861
 862         /* Configure lan hmc */
 863         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 864         if (ret != I40E_SUCCESS) {
 865                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 866                 goto err_configure_lan_hmc;
 867         }
 868
 869         /* Get and check the mac address */
 870         i40e_get_mac_addr(hw, hw->mac.addr);
 871         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 872                 PMD_INIT_LOG(ERR, "mac address is not valid");
 873                 ret = -EIO;
 874                 goto err_get_mac_addr;
 875         }
 876         /* Copy the permanent MAC address */
 877         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 878                         (struct ether_addr *) hw->mac.perm_addr);
 879
 880         /* Disable flow control */
 881         hw->fc.requested_mode = I40E_FC_NONE;
 882         i40e_set_fc(hw, &aq_fail, TRUE);
 883
 884         /* Set the global registers with default ether type value */
 885         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 886         if (ret != I40E_SUCCESS) {
 887                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 888                              "VLAN ether type");
 889                 goto err_setup_pf_switch;
 890         }
 891         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 892         if (ret != I40E_SUCCESS) {
 893                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 894                              "VLAN ether type");
 895                 goto err_setup_pf_switch;
 896         }
 897
 898         /* PF setup, which includes VSI setup */
 899         ret = i40e_pf_setup(pf);
 900         if (ret) {
 901                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 902                 goto err_setup_pf_switch;
 903         }
 904
 905         vsi = pf->main_vsi;
 906
 907         /* Disable double vlan by default */
 908         i40e_vsi_config_double_vlan(vsi, FALSE);
 909
 910         if (!vsi->max_macaddrs)
 911                 len = ETHER_ADDR_LEN;
 912         else
 913                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 914
 915         /* Should be after VSI initialized */
 916         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 917         if (!dev->data->mac_addrs) {
 918                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 919                                         "for storing mac address");
 920                 goto err_mac_alloc;
 921         }
 922         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 923                                         &dev->data->mac_addrs[0]);
 924
 925         /* initialize pf host driver to setup SRIOV resource if applicable */
 926         i40e_pf_host_init(dev);
 927
 928         /* register callback func to eal lib */
 929         rte_intr_callback_register(&(pci_dev->intr_handle),
 930                 i40e_dev_interrupt_handler, (void *)dev);
 931
 932         /* configure and enable device interrupt */
 933         i40e_pf_config_irq0(hw, TRUE);
 934         i40e_pf_enable_irq0(hw);
 935
 936         /* enable uio intr after callback register */
 937         rte_intr_enable(&(pci_dev->intr_handle));
 938         /*
 939          * Add an ethertype filter to drop all flow control frames transmitted
 940          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 941          * frames to wire.
 942          */
 943         i40e_add_tx_flow_control_drop_filter(pf);
 944
 945         /* Set the max frame size to 0x2600 by default,
 946          * in case other drivers changed the default value.
 947          */
 948         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 949
 950         /* initialize mirror rule list */
 951         TAILQ_INIT(&pf->mirror_list);
 952
 953         /* Init dcb to sw mode by default */
 954         ret = i40e_dcb_init_configure(dev, TRUE);
 955         if (ret != I40E_SUCCESS) {
 956                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 957                 pf->flags &= ~I40E_FLAG_DCB;
 958         }
 959
 960         return 0;
 961
 962 err_mac_alloc:
 963         i40e_vsi_release(pf->main_vsi);
 964 err_setup_pf_switch:
 965 err_get_mac_addr:
 966 err_configure_lan_hmc:
 967         (void)i40e_shutdown_lan_hmc(hw);
 968 err_init_lan_hmc:
 969         i40e_res_pool_destroy(&pf->msix_pool);
 970 err_msix_pool_init:
 971         i40e_res_pool_destroy(&pf->qp_pool);
 972 err_qp_pool_init:
 973 err_parameter_init:
 974 err_get_capabilities:
 975         (void)i40e_shutdown_adminq(hw);
 976
 977         return ret;
 978 }
 979
 980 static int
 981 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 982 {
 983         struct rte_pci_device *pci_dev;
 984         struct i40e_hw *hw;
 985         struct i40e_filter_control_settings settings;
 986         int ret;
 987         uint8_t aq_fail = 0;
 988
 989         PMD_INIT_FUNC_TRACE();
 990
 991         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 992                 return 0;
 993
 994         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 995         pci_dev = dev->pci_dev;
 996
 997         if (hw->adapter_stopped == 0)
 998                 i40e_dev_close(dev);
 999
1000         dev->dev_ops = NULL;
1001         dev->rx_pkt_burst = NULL;
1002         dev->tx_pkt_burst = NULL;
1003
1004         /* Disable LLDP */
1005         ret = i40e_aq_stop_lldp(hw, true, NULL);
1006         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1007                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1008
1009         /* Clear PXE mode */
1010         i40e_clear_pxe_mode(hw);
1011
1012         /* Unconfigure filter control */
1013         memset(&settings, 0, sizeof(settings));
1014         ret = i40e_set_filter_control(hw, &settings);
1015         if (ret)
1016                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1017                                         ret);
1018
1019         /* Disable flow control */
1020         hw->fc.requested_mode = I40E_FC_NONE;
1021         i40e_set_fc(hw, &aq_fail, TRUE);
1022
1023         /* uninitialize pf host driver */
1024         i40e_pf_host_uninit(dev);
1025
1026         rte_free(dev->data->mac_addrs);
1027         dev->data->mac_addrs = NULL;
1028
1029         /* disable uio intr before callback unregister */
1030         rte_intr_disable(&(pci_dev->intr_handle));
1031
1032         /* register callback func to eal lib */
1033         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1034                 i40e_dev_interrupt_handler, (void *)dev);
1035
1036         return 0;
1037 }
1038
1039 static int
1040 i40e_dev_configure(struct rte_eth_dev *dev)
1041 {
1042         struct i40e_adapter *ad =
1043                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1044         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1045         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1046         int i, ret;
1047
1048         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1049          * bulk allocation or vector Rx preconditions we will reset it.
1050          */
1051         ad->rx_bulk_alloc_allowed = true;
1052         ad->rx_vec_allowed = true;
1053         ad->tx_simple_allowed = true;
1054         ad->tx_vec_allowed = true;
1055
1056         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1057                 ret = i40e_fdir_setup(pf);
1058                 if (ret != I40E_SUCCESS) {
1059                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1060                         return -ENOTSUP;
1061                 }
1062                 ret = i40e_fdir_configure(dev);
1063                 if (ret < 0) {
1064                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1065                         goto err;
1066                 }
1067         } else
1068                 i40e_fdir_teardown(pf);
1069
1070         ret = i40e_dev_init_vlan(dev);
1071         if (ret < 0)
1072                 goto err;
1073
1074         /* VMDQ setup.
1075          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1076          *  RSS setting have different requirements.
1077          *  General PMD driver call sequence are NIC init, configure,
1078          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1079          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1080          *  applicable. So, VMDQ setting has to be done before
1081          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1082          *  For RSS setting, it will try to calculate actual configured RX queue
1083          *  number, which will be available after rx_queue_setup(). dev_start()
1084          *  function is good to place RSS setup.
1085          */
1086         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1087                 ret = i40e_vmdq_setup(dev);
1088                 if (ret)
1089                         goto err;
1090         }
1091
1092         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1093                 ret = i40e_dcb_setup(dev);
1094                 if (ret) {
1095                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1096                         goto err_dcb;
1097                 }
1098         }
1099
1100         return 0;
1101
1102 err_dcb:
1103         /* need to release vmdq resource if exists */
1104         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1105                 i40e_vsi_release(pf->vmdq[i].vsi);
1106                 pf->vmdq[i].vsi = NULL;
1107         }
1108         rte_free(pf->vmdq);
1109         pf->vmdq = NULL;
1110 err:
1111         /* need to release fdir resource if exists */
1112         i40e_fdir_teardown(pf);
1113         return ret;
1114 }
1115
1116 void
1117 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1118 {
1119         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1120         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1121         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1122         uint16_t msix_vect = vsi->msix_intr;
1123         uint16_t i;
1124
1125         for (i = 0; i < vsi->nb_qps; i++) {
1126                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1127                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1128                 rte_wmb();
1129         }
1130
1131         if (vsi->type != I40E_VSI_SRIOV) {
1132                 if (!rte_intr_allow_others(intr_handle)) {
1133                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1134                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1135                         I40E_WRITE_REG(hw,
1136                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1137                                        0);
1138                 } else {
1139                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1140                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1141                         I40E_WRITE_REG(hw,
1142                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1143                                                        msix_vect - 1), 0);
1144                 }
1145         } else {
1146                 uint32_t reg;
1147                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1148                         vsi->user_param + (msix_vect - 1);
1149
1150                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1151                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1152         }
1153         I40E_WRITE_FLUSH(hw);
1154 }
1155
1156 static void
1157 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1158                        int base_queue, int nb_queue)
1159 {
1160         int i;
1161         uint32_t val;
1162         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1163
1164         /* Bind all RX queues to allocated MSIX interrupt */
1165         for (i = 0; i < nb_queue; i++) {
1166                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1167                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1168                         ((base_queue + i + 1) <<
1169                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1170                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1171                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1172
1173                 if (i == nb_queue - 1)
1174                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1175                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1176         }
1177
1178         /* Write first RX queue to Link list register as the head element */
1179         if (vsi->type != I40E_VSI_SRIOV) {
1180                 uint16_t interval =
1181                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1182
1183                 if (msix_vect == I40E_MISC_VEC_ID) {
1184                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1185                                        (base_queue <<
1186                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1187                                        (0x0 <<
1188                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1189                         I40E_WRITE_REG(hw,
1190                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1191                                        interval);
1192                 } else {
1193                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1194                                        (base_queue <<
1195                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1196                                        (0x0 <<
1197                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1198                         I40E_WRITE_REG(hw,
1199                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1200                                                        msix_vect - 1),
1201                                        interval);
1202                 }
1203         } else {
1204                 uint32_t reg;
1205
1206                 if (msix_vect == I40E_MISC_VEC_ID) {
1207                         I40E_WRITE_REG(hw,
1208                                        I40E_VPINT_LNKLST0(vsi->user_param),
1209                                        (base_queue <<
1210                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1211                                        (0x0 <<
1212                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1213                 } else {
1214                         /* num_msix_vectors_vf needs to minus irq0 */
1215                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1216                                 vsi->user_param + (msix_vect - 1);
1217
1218                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1219                                        (base_queue <<
1220                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1221                                        (0x0 <<
1222                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1223                 }
1224         }
1225
1226         I40E_WRITE_FLUSH(hw);
1227 }
1228
1229 void
1230 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1231 {
1232         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1233         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1234         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1235         uint16_t msix_vect = vsi->msix_intr;
1236         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1237         uint16_t queue_idx = 0;
1238         int record = 0;
1239         uint32_t val;
1240         int i;
1241
1242         for (i = 0; i < vsi->nb_qps; i++) {
1243                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1244                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1245         }
1246
1247         /* INTENA flag is not auto-cleared for interrupt */
1248         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1249         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1250                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1251                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1252         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1253
1254         /* VF bind interrupt */
1255         if (vsi->type == I40E_VSI_SRIOV) {
1256                 __vsi_queues_bind_intr(vsi, msix_vect,
1257                                        vsi->base_queue, vsi->nb_qps);
1258                 return;
1259         }
1260
1261         /* PF & VMDq bind interrupt */
1262         if (rte_intr_dp_is_en(intr_handle)) {
1263                 if (vsi->type == I40E_VSI_MAIN) {
1264                         queue_idx = 0;
1265                         record = 1;
1266                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1267                         struct i40e_vsi *main_vsi =
1268                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1269                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1270                         record = 1;
1271                 }
1272         }
1273
1274         for (i = 0; i < vsi->nb_used_qps; i++) {
1275                 if (nb_msix <= 1) {
1276                         if (!rte_intr_allow_others(intr_handle))
1277                                 /* allow to share MISC_VEC_ID */
1278                                 msix_vect = I40E_MISC_VEC_ID;
1279
1280                         /* no enough msix_vect, map all to one */
1281                         __vsi_queues_bind_intr(vsi, msix_vect,
1282                                                vsi->base_queue + i,
1283                                                vsi->nb_used_qps - i);
1284                         for (; !!record && i < vsi->nb_used_qps; i++)
1285                                 intr_handle->intr_vec[queue_idx + i] =
1286                                         msix_vect;
1287                         break;
1288                 }
1289                 /* 1:1 queue/msix_vect mapping */
1290                 __vsi_queues_bind_intr(vsi, msix_vect,
1291                                        vsi->base_queue + i, 1);
1292                 if (!!record)
1293                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1294
1295                 msix_vect++;
1296                 nb_msix--;
1297         }
1298 }
1299
1300 static void
1301 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1302 {
1303         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1304         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1305         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1306         uint16_t interval = i40e_calc_itr_interval(\
1307                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1308         uint16_t msix_intr, i;
1309
1310         if (rte_intr_allow_others(intr_handle))
1311                 for (i = 0; i < vsi->nb_msix; i++) {
1312                         msix_intr = vsi->msix_intr + i;
1313                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1314                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1315                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1316                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1317                                 (interval <<
1318                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1319                 }
1320         else
1321                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1322                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1323                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1324                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1325                                (interval <<
1326                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1327
1328         I40E_WRITE_FLUSH(hw);
1329 }
1330
1331 static void
1332 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1333 {
1334         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1335         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1336         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1337         uint16_t msix_intr, i;
1338
1339         if (rte_intr_allow_others(intr_handle))
1340                 for (i = 0; i < vsi->nb_msix; i++) {
1341                         msix_intr = vsi->msix_intr + i;
1342                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1343                                        0);
1344                 }
1345         else
1346                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1347
1348         I40E_WRITE_FLUSH(hw);
1349 }
1350
1351 static inline uint8_t
1352 i40e_parse_link_speed(uint16_t eth_link_speed)
1353 {
1354         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1355
1356         switch (eth_link_speed) {
1357         case ETH_LINK_SPEED_40G:
1358                 link_speed = I40E_LINK_SPEED_40GB;
1359                 break;
1360         case ETH_LINK_SPEED_20G:
1361                 link_speed = I40E_LINK_SPEED_20GB;
1362                 break;
1363         case ETH_LINK_SPEED_10G:
1364                 link_speed = I40E_LINK_SPEED_10GB;
1365                 break;
1366         case ETH_LINK_SPEED_1000:
1367                 link_speed = I40E_LINK_SPEED_1GB;
1368                 break;
1369         case ETH_LINK_SPEED_100:
1370                 link_speed = I40E_LINK_SPEED_100MB;
1371                 break;
1372         }
1373
1374         return link_speed;
1375 }
1376
1377 static int
1378 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1379                    __rte_unused uint8_t abilities,
1380                    __rte_unused uint8_t force_speed)
1381 {
1382         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1383          * for the link control limitation of that all link control should be
1384          * handled by firmware. It should follow up if link control will be
1385          * opened to software driver in future firmware versions.
1386          */
1387         return I40E_SUCCESS;
1388 }
1389
1390 static int
1391 i40e_apply_link_speed(struct rte_eth_dev *dev)
1392 {
1393         uint8_t speed;
1394         uint8_t abilities = 0;
1395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         struct rte_eth_conf *conf = &dev->data->dev_conf;
1397
1398         speed = i40e_parse_link_speed(conf->link_speed);
1399         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1400         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1401                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1402         else
1403                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1404
1405         return i40e_phy_conf_link(hw, abilities, speed);
1406 }
1407
1408 static int
1409 i40e_dev_start(struct rte_eth_dev *dev)
1410 {
1411         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1412         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413         struct i40e_vsi *main_vsi = pf->main_vsi;
1414         int ret, i;
1415         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1416         uint32_t intr_vector = 0;
1417
1418         hw->adapter_stopped = 0;
1419
1420         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1421                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1422                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1423                              dev->data->dev_conf.link_duplex,
1424                              dev->data->port_id);
1425                 return -EINVAL;
1426         }
1427
1428         rte_intr_disable(intr_handle);
1429
1430         if ((rte_intr_cap_multiple(intr_handle) ||
1431              !RTE_ETH_DEV_SRIOV(dev).active) &&
1432             dev->data->dev_conf.intr_conf.rxq != 0) {
1433                 intr_vector = dev->data->nb_rx_queues;
1434                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1435                         return -1;
1436         }
1437
1438         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1439                 intr_handle->intr_vec =
1440                         rte_zmalloc("intr_vec",
1441                                     dev->data->nb_rx_queues * sizeof(int),
1442                                     0);
1443                 if (!intr_handle->intr_vec) {
1444                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1445                                      " intr_vec\n", dev->data->nb_rx_queues);
1446                         return -ENOMEM;
1447                 }
1448         }
1449
1450         /* Initialize VSI */
1451         ret = i40e_dev_rxtx_init(pf);
1452         if (ret != I40E_SUCCESS) {
1453                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1454                 goto err_up;
1455         }
1456
1457         /* Map queues with MSIX interrupt */
1458         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1459                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1460         i40e_vsi_queues_bind_intr(main_vsi);
1461         i40e_vsi_enable_queues_intr(main_vsi);
1462
1463         /* Map VMDQ VSI queues with MSIX interrupt */
1464         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1465                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1466                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1467                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1468         }
1469
1470         /* enable FDIR MSIX interrupt */
1471         if (pf->fdir.fdir_vsi) {
1472                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1473                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1474         }
1475
1476         /* Enable all queues which have been configured */
1477         ret = i40e_dev_switch_queues(pf, TRUE);
1478         if (ret != I40E_SUCCESS) {
1479                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1480                 goto err_up;
1481         }
1482
1483         /* Enable receiving broadcast packets */
1484         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1485         if (ret != I40E_SUCCESS)
1486                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1487
1488         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1489                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1490                                                 true, NULL);
1491                 if (ret != I40E_SUCCESS)
1492                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1493         }
1494
1495         /* Apply link configure */
1496         ret = i40e_apply_link_speed(dev);
1497         if (I40E_SUCCESS != ret) {
1498                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1499                 goto err_up;
1500         }
1501
1502         if (!rte_intr_allow_others(intr_handle)) {
1503                 rte_intr_callback_unregister(intr_handle,
1504                                              i40e_dev_interrupt_handler,
1505                                              (void *)dev);
1506                 /* configure and enable device interrupt */
1507                 i40e_pf_config_irq0(hw, FALSE);
1508                 i40e_pf_enable_irq0(hw);
1509
1510                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1511                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1512                                      " no intr multiplex\n");
1513         }
1514
1515         /* enable uio intr after callback register */
1516         rte_intr_enable(intr_handle);
1517
1518         return I40E_SUCCESS;
1519
1520 err_up:
1521         i40e_dev_switch_queues(pf, FALSE);
1522         i40e_dev_clear_queues(dev);
1523
1524         return ret;
1525 }
1526
1527 static void
1528 i40e_dev_stop(struct rte_eth_dev *dev)
1529 {
1530         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1531         struct i40e_vsi *main_vsi = pf->main_vsi;
1532         struct i40e_mirror_rule *p_mirror;
1533         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1534         int i;
1535
1536         /* Disable all queues */
1537         i40e_dev_switch_queues(pf, FALSE);
1538
1539         /* un-map queues with interrupt registers */
1540         i40e_vsi_disable_queues_intr(main_vsi);
1541         i40e_vsi_queues_unbind_intr(main_vsi);
1542
1543         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1544                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1545                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1546         }
1547
1548         if (pf->fdir.fdir_vsi) {
1549                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1550                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1551         }
1552         /* Clear all queues and release memory */
1553         i40e_dev_clear_queues(dev);
1554
1555         /* Set link down */
1556         i40e_dev_set_link_down(dev);
1557
1558         /* Remove all mirror rules */
1559         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1560                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1561                 rte_free(p_mirror);
1562         }
1563         pf->nb_mirror_rule = 0;
1564
1565         if (!rte_intr_allow_others(intr_handle))
1566                 /* resume to the default handler */
1567                 rte_intr_callback_register(intr_handle,
1568                                            i40e_dev_interrupt_handler,
1569                                            (void *)dev);
1570
1571         /* Clean datapath event and queue/vec mapping */
1572         rte_intr_efd_disable(intr_handle);
1573         if (intr_handle->intr_vec) {
1574                 rte_free(intr_handle->intr_vec);
1575                 intr_handle->intr_vec = NULL;
1576         }
1577 }
1578
1579 static void
1580 i40e_dev_close(struct rte_eth_dev *dev)
1581 {
1582         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1583         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584         uint32_t reg;
1585         int i;
1586
1587         PMD_INIT_FUNC_TRACE();
1588
1589         i40e_dev_stop(dev);
1590         hw->adapter_stopped = 1;
1591         i40e_dev_free_queues(dev);
1592
1593         /* Disable interrupt */
1594         i40e_pf_disable_irq0(hw);
1595         rte_intr_disable(&(dev->pci_dev->intr_handle));
1596
1597         /* shutdown and destroy the HMC */
1598         i40e_shutdown_lan_hmc(hw);
1599
1600         /* release all the existing VSIs and VEBs */
1601         i40e_fdir_teardown(pf);
1602         i40e_vsi_release(pf->main_vsi);
1603
1604         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1605                 i40e_vsi_release(pf->vmdq[i].vsi);
1606                 pf->vmdq[i].vsi = NULL;
1607         }
1608
1609         rte_free(pf->vmdq);
1610         pf->vmdq = NULL;
1611
1612         /* shutdown the adminq */
1613         i40e_aq_queue_shutdown(hw, true);
1614         i40e_shutdown_adminq(hw);
1615
1616         i40e_res_pool_destroy(&pf->qp_pool);
1617         i40e_res_pool_destroy(&pf->msix_pool);
1618
1619         /* force a PF reset to clean anything leftover */
1620         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1621         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1622                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1623         I40E_WRITE_FLUSH(hw);
1624 }
1625
1626 static void
1627 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1628 {
1629         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         struct i40e_vsi *vsi = pf->main_vsi;
1632         int status;
1633
1634         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1635                                                         true, NULL);
1636         if (status != I40E_SUCCESS)
1637                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1638
1639         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1640                                                         TRUE, NULL);
1641         if (status != I40E_SUCCESS)
1642                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1643
1644 }
1645
1646 static void
1647 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1648 {
1649         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651         struct i40e_vsi *vsi = pf->main_vsi;
1652         int status;
1653
1654         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1655                                                         false, NULL);
1656         if (status != I40E_SUCCESS)
1657                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1658
1659         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1660                                                         false, NULL);
1661         if (status != I40E_SUCCESS)
1662                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1663 }
1664
1665 static void
1666 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1667 {
1668         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1670         struct i40e_vsi *vsi = pf->main_vsi;
1671         int ret;
1672
1673         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1674         if (ret != I40E_SUCCESS)
1675                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1676 }
1677
1678 static void
1679 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1680 {
1681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1682         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683         struct i40e_vsi *vsi = pf->main_vsi;
1684         int ret;
1685
1686         if (dev->data->promiscuous == 1)
1687                 return; /* must remain in all_multicast mode */
1688
1689         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1690                                 vsi->seid, FALSE, NULL);
1691         if (ret != I40E_SUCCESS)
1692                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1693 }
1694
1695 /*
1696  * Set device link up.
1697  */
1698 static int
1699 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1700 {
1701         /* re-apply link speed setting */
1702         return i40e_apply_link_speed(dev);
1703 }
1704
1705 /*
1706  * Set device link down.
1707  */
1708 static int
1709 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1710 {
1711         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1712         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1714
1715         return i40e_phy_conf_link(hw, abilities, speed);
1716 }
1717
1718 int
1719 i40e_dev_link_update(struct rte_eth_dev *dev,
1720                      int wait_to_complete)
1721 {
1722 #define CHECK_INTERVAL 100  /* 100ms */
1723 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1724         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725         struct i40e_link_status link_status;
1726         struct rte_eth_link link, old;
1727         int status;
1728         unsigned rep_cnt = MAX_REPEAT_TIME;
1729
1730         memset(&link, 0, sizeof(link));
1731         memset(&old, 0, sizeof(old));
1732         memset(&link_status, 0, sizeof(link_status));
1733         rte_i40e_dev_atomic_read_link_status(dev, &old);
1734
1735         do {
1736                 /* Get link status information from hardware */
1737                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1738                 if (status != I40E_SUCCESS) {
1739                         link.link_speed = ETH_LINK_SPEED_100;
1740                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1741                         PMD_DRV_LOG(ERR, "Failed to get link info");
1742                         goto out;
1743                 }
1744
1745                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1746                 if (!wait_to_complete)
1747                         break;
1748
1749                 rte_delay_ms(CHECK_INTERVAL);
1750         } while (!link.link_status && rep_cnt--);
1751
1752         if (!link.link_status)
1753                 goto out;
1754
1755         /* i40e uses full duplex only */
1756         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1757
1758         /* Parse the link status */
1759         switch (link_status.link_speed) {
1760         case I40E_LINK_SPEED_100MB:
1761                 link.link_speed = ETH_LINK_SPEED_100;
1762                 break;
1763         case I40E_LINK_SPEED_1GB:
1764                 link.link_speed = ETH_LINK_SPEED_1000;
1765                 break;
1766         case I40E_LINK_SPEED_10GB:
1767                 link.link_speed = ETH_LINK_SPEED_10G;
1768                 break;
1769         case I40E_LINK_SPEED_20GB:
1770                 link.link_speed = ETH_LINK_SPEED_20G;
1771                 break;
1772         case I40E_LINK_SPEED_40GB:
1773                 link.link_speed = ETH_LINK_SPEED_40G;
1774                 break;
1775         default:
1776                 link.link_speed = ETH_LINK_SPEED_100;
1777                 break;
1778         }
1779
1780 out:
1781         rte_i40e_dev_atomic_write_link_status(dev, &link);
1782         if (link.link_status == old.link_status)
1783                 return -1;
1784
1785         return 0;
1786 }
1787
1788 /* Get all the statistics of a VSI */
1789 void
1790 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1791 {
1792         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1793         struct i40e_eth_stats *nes = &vsi->eth_stats;
1794         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1795         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1796
1797         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1798                             vsi->offset_loaded, &oes->rx_bytes,
1799                             &nes->rx_bytes);
1800         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1801                             vsi->offset_loaded, &oes->rx_unicast,
1802                             &nes->rx_unicast);
1803         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1804                             vsi->offset_loaded, &oes->rx_multicast,
1805                             &nes->rx_multicast);
1806         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1807                             vsi->offset_loaded, &oes->rx_broadcast,
1808                             &nes->rx_broadcast);
1809         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1810                             &oes->rx_discards, &nes->rx_discards);
1811         /* GLV_REPC not supported */
1812         /* GLV_RMPC not supported */
1813         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1814                             &oes->rx_unknown_protocol,
1815                             &nes->rx_unknown_protocol);
1816         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1817                             vsi->offset_loaded, &oes->tx_bytes,
1818                             &nes->tx_bytes);
1819         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1820                             vsi->offset_loaded, &oes->tx_unicast,
1821                             &nes->tx_unicast);
1822         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1823                             vsi->offset_loaded, &oes->tx_multicast,
1824                             &nes->tx_multicast);
1825         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1826                             vsi->offset_loaded,  &oes->tx_broadcast,
1827                             &nes->tx_broadcast);
1828         /* GLV_TDPC not supported */
1829         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1830                             &oes->tx_errors, &nes->tx_errors);
1831         vsi->offset_loaded = true;
1832
1833         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1834                     vsi->vsi_id);
1835         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1836         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1837         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1838         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1839         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1840         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1841                     nes->rx_unknown_protocol);
1842         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1843         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1844         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1845         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1846         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1847         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1848         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1849                     vsi->vsi_id);
1850 }
1851
1852 static void
1853 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1854 {
1855         unsigned int i;
1856         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1857         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1858
1859         /* Get statistics of struct i40e_eth_stats */
1860         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1861                             I40E_GLPRT_GORCL(hw->port),
1862                             pf->offset_loaded, &os->eth.rx_bytes,
1863                             &ns->eth.rx_bytes);
1864         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1865                             I40E_GLPRT_UPRCL(hw->port),
1866                             pf->offset_loaded, &os->eth.rx_unicast,
1867                             &ns->eth.rx_unicast);
1868         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1869                             I40E_GLPRT_MPRCL(hw->port),
1870                             pf->offset_loaded, &os->eth.rx_multicast,
1871                             &ns->eth.rx_multicast);
1872         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1873                             I40E_GLPRT_BPRCL(hw->port),
1874                             pf->offset_loaded, &os->eth.rx_broadcast,
1875                             &ns->eth.rx_broadcast);
1876         /* Workaround: CRC size should not be included in byte statistics,
1877          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1878          */
1879         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1880                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1881
1882         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1883                             pf->offset_loaded, &os->eth.rx_discards,
1884                             &ns->eth.rx_discards);
1885         /* GLPRT_REPC not supported */
1886         /* GLPRT_RMPC not supported */
1887         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1888                             pf->offset_loaded,
1889                             &os->eth.rx_unknown_protocol,
1890                             &ns->eth.rx_unknown_protocol);
1891         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1892                             I40E_GLPRT_GOTCL(hw->port),
1893                             pf->offset_loaded, &os->eth.tx_bytes,
1894                             &ns->eth.tx_bytes);
1895         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1896                             I40E_GLPRT_UPTCL(hw->port),
1897                             pf->offset_loaded, &os->eth.tx_unicast,
1898                             &ns->eth.tx_unicast);
1899         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1900                             I40E_GLPRT_MPTCL(hw->port),
1901                             pf->offset_loaded, &os->eth.tx_multicast,
1902                             &ns->eth.tx_multicast);
1903         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1904                             I40E_GLPRT_BPTCL(hw->port),
1905                             pf->offset_loaded, &os->eth.tx_broadcast,
1906                             &ns->eth.tx_broadcast);
1907         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1908                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1909         /* GLPRT_TEPC not supported */
1910
1911         /* additional port specific stats */
1912         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1913                             pf->offset_loaded, &os->tx_dropped_link_down,
1914                             &ns->tx_dropped_link_down);
1915         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1916                             pf->offset_loaded, &os->crc_errors,
1917                             &ns->crc_errors);
1918         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1919                             pf->offset_loaded, &os->illegal_bytes,
1920                             &ns->illegal_bytes);
1921         /* GLPRT_ERRBC not supported */
1922         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1923                             pf->offset_loaded, &os->mac_local_faults,
1924                             &ns->mac_local_faults);
1925         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1926                             pf->offset_loaded, &os->mac_remote_faults,
1927                             &ns->mac_remote_faults);
1928         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1929                             pf->offset_loaded, &os->rx_length_errors,
1930                             &ns->rx_length_errors);
1931         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1932                             pf->offset_loaded, &os->link_xon_rx,
1933                             &ns->link_xon_rx);
1934         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1935                             pf->offset_loaded, &os->link_xoff_rx,
1936                             &ns->link_xoff_rx);
1937         for (i = 0; i < 8; i++) {
1938                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1939                                     pf->offset_loaded,
1940                                     &os->priority_xon_rx[i],
1941                                     &ns->priority_xon_rx[i]);
1942                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1943                                     pf->offset_loaded,
1944                                     &os->priority_xoff_rx[i],
1945                                     &ns->priority_xoff_rx[i]);
1946         }
1947         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1948                             pf->offset_loaded, &os->link_xon_tx,
1949                             &ns->link_xon_tx);
1950         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1951                             pf->offset_loaded, &os->link_xoff_tx,
1952                             &ns->link_xoff_tx);
1953         for (i = 0; i < 8; i++) {
1954                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1955                                     pf->offset_loaded,
1956                                     &os->priority_xon_tx[i],
1957                                     &ns->priority_xon_tx[i]);
1958                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1959                                     pf->offset_loaded,
1960                                     &os->priority_xoff_tx[i],
1961                                     &ns->priority_xoff_tx[i]);
1962                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1963                                     pf->offset_loaded,
1964                                     &os->priority_xon_2_xoff[i],
1965                                     &ns->priority_xon_2_xoff[i]);
1966         }
1967         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1968                             I40E_GLPRT_PRC64L(hw->port),
1969                             pf->offset_loaded, &os->rx_size_64,
1970                             &ns->rx_size_64);
1971         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1972                             I40E_GLPRT_PRC127L(hw->port),
1973                             pf->offset_loaded, &os->rx_size_127,
1974                             &ns->rx_size_127);
1975         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1976                             I40E_GLPRT_PRC255L(hw->port),
1977                             pf->offset_loaded, &os->rx_size_255,
1978                             &ns->rx_size_255);
1979         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1980                             I40E_GLPRT_PRC511L(hw->port),
1981                             pf->offset_loaded, &os->rx_size_511,
1982                             &ns->rx_size_511);
1983         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1984                             I40E_GLPRT_PRC1023L(hw->port),
1985                             pf->offset_loaded, &os->rx_size_1023,
1986                             &ns->rx_size_1023);
1987         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1988                             I40E_GLPRT_PRC1522L(hw->port),
1989                             pf->offset_loaded, &os->rx_size_1522,
1990                             &ns->rx_size_1522);
1991         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1992                             I40E_GLPRT_PRC9522L(hw->port),
1993                             pf->offset_loaded, &os->rx_size_big,
1994                             &ns->rx_size_big);
1995         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1996                             pf->offset_loaded, &os->rx_undersize,
1997                             &ns->rx_undersize);
1998         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1999                             pf->offset_loaded, &os->rx_fragments,
2000                             &ns->rx_fragments);
2001         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2002                             pf->offset_loaded, &os->rx_oversize,
2003                             &ns->rx_oversize);
2004         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2005                             pf->offset_loaded, &os->rx_jabber,
2006                             &ns->rx_jabber);
2007         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2008                             I40E_GLPRT_PTC64L(hw->port),
2009                             pf->offset_loaded, &os->tx_size_64,
2010                             &ns->tx_size_64);
2011         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2012                             I40E_GLPRT_PTC127L(hw->port),
2013                             pf->offset_loaded, &os->tx_size_127,
2014                             &ns->tx_size_127);
2015         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2016                             I40E_GLPRT_PTC255L(hw->port),
2017                             pf->offset_loaded, &os->tx_size_255,
2018                             &ns->tx_size_255);
2019         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2020                             I40E_GLPRT_PTC511L(hw->port),
2021                             pf->offset_loaded, &os->tx_size_511,
2022                             &ns->tx_size_511);
2023         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2024                             I40E_GLPRT_PTC1023L(hw->port),
2025                             pf->offset_loaded, &os->tx_size_1023,
2026                             &ns->tx_size_1023);
2027         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2028                             I40E_GLPRT_PTC1522L(hw->port),
2029                             pf->offset_loaded, &os->tx_size_1522,
2030                             &ns->tx_size_1522);
2031         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2032                             I40E_GLPRT_PTC9522L(hw->port),
2033                             pf->offset_loaded, &os->tx_size_big,
2034                             &ns->tx_size_big);
2035         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2036                            pf->offset_loaded,
2037                            &os->fd_sb_match, &ns->fd_sb_match);
2038         /* GLPRT_MSPDC not supported */
2039         /* GLPRT_XEC not supported */
2040
2041         pf->offset_loaded = true;
2042
2043         if (pf->main_vsi)
2044                 i40e_update_vsi_stats(pf->main_vsi);
2045 }
2046
2047 /* Get all statistics of a port */
2048 static void
2049 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2050 {
2051         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2052         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2053         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2054         unsigned i;
2055
2056         /* call read registers - updates values, now write them to struct */
2057         i40e_read_stats_registers(pf, hw);
2058
2059         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2060                         pf->main_vsi->eth_stats.rx_multicast +
2061                         pf->main_vsi->eth_stats.rx_broadcast -
2062                         pf->main_vsi->eth_stats.rx_discards;
2063         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2064                         pf->main_vsi->eth_stats.tx_multicast +
2065                         pf->main_vsi->eth_stats.tx_broadcast;
2066         stats->ibytes   = ns->eth.rx_bytes;
2067         stats->obytes   = ns->eth.tx_bytes;
2068         stats->oerrors  = ns->eth.tx_errors +
2069                         pf->main_vsi->eth_stats.tx_errors;
2070         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2071
2072         /* Rx Errors */
2073         stats->imissed  = ns->eth.rx_discards +
2074                         pf->main_vsi->eth_stats.rx_discards;
2075         stats->ierrors  = ns->crc_errors +
2076                         ns->rx_length_errors + ns->rx_undersize +
2077                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2078                         stats->imissed;
2079
2080         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2081         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2082         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2083         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2084         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2085         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2086         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2087                     ns->eth.rx_unknown_protocol);
2088         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2089         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2090         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2091         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2092         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2093         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2094
2095         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2096                     ns->tx_dropped_link_down);
2097         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2098         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2099                     ns->illegal_bytes);
2100         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2101         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2102                     ns->mac_local_faults);
2103         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2104                     ns->mac_remote_faults);
2105         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2106                     ns->rx_length_errors);
2107         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2108         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2109         for (i = 0; i < 8; i++) {
2110                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2111                                 i, ns->priority_xon_rx[i]);
2112                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2113                                 i, ns->priority_xoff_rx[i]);
2114         }
2115         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2116         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2117         for (i = 0; i < 8; i++) {
2118                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2119                                 i, ns->priority_xon_tx[i]);
2120                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2121                                 i, ns->priority_xoff_tx[i]);
2122                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2123                                 i, ns->priority_xon_2_xoff[i]);
2124         }
2125         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2126         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2127         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2128         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2129         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2130         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2131         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2132         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2133         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2134         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2135         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2136         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2137         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2138         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2139         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2140         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2141         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2142         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2143         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2144                         ns->mac_short_packet_dropped);
2145         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2146                     ns->checksum_error);
2147         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2148         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2149 }
2150
2151 /* Reset the statistics */
2152 static void
2153 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2154 {
2155         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2156         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157
2158         /* Mark PF and VSI stats to update the offset, aka "reset" */
2159         pf->offset_loaded = false;
2160         if (pf->main_vsi)
2161                 pf->main_vsi->offset_loaded = false;
2162
2163         /* read the stats, reading current register values into offset */
2164         i40e_read_stats_registers(pf, hw);
2165 }
2166
2167 static uint32_t
2168 i40e_xstats_calc_num(void)
2169 {
2170         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2171                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2172                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2173 }
2174
2175 static int
2176 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2177                     unsigned n)
2178 {
2179         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2180         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2181         unsigned i, count, prio;
2182         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2183
2184         count = i40e_xstats_calc_num();
2185         if (n < count)
2186                 return count;
2187
2188         i40e_read_stats_registers(pf, hw);
2189
2190         if (xstats == NULL)
2191                 return 0;
2192
2193         count = 0;
2194
2195         /* Get stats from i40e_eth_stats struct */
2196         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2197                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2198                          "%s", rte_i40e_stats_strings[i].name);
2199                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2200                         rte_i40e_stats_strings[i].offset);
2201                 count++;
2202         }
2203
2204         /* Get individiual stats from i40e_hw_port struct */
2205         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2206                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2207                          "%s", rte_i40e_hw_port_strings[i].name);
2208                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2209                                 rte_i40e_hw_port_strings[i].offset);
2210                 count++;
2211         }
2212
2213         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2214                 for (prio = 0; prio < 8; prio++) {
2215                         snprintf(xstats[count].name,
2216                                  sizeof(xstats[count].name),
2217                                  "rx_priority%u_%s", prio,
2218                                  rte_i40e_rxq_prio_strings[i].name);
2219                         xstats[count].value =
2220                                 *(uint64_t *)(((char *)hw_stats) +
2221                                 rte_i40e_rxq_prio_strings[i].offset +
2222                                 (sizeof(uint64_t) * prio));
2223                         count++;
2224                 }
2225         }
2226
2227         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2228                 for (prio = 0; prio < 8; prio++) {
2229                         snprintf(xstats[count].name,
2230                                  sizeof(xstats[count].name),
2231                                  "tx_priority%u_%s", prio,
2232                                  rte_i40e_txq_prio_strings[i].name);
2233                         xstats[count].value =
2234                                 *(uint64_t *)(((char *)hw_stats) +
2235                                 rte_i40e_txq_prio_strings[i].offset +
2236                                 (sizeof(uint64_t) * prio));
2237                         count++;
2238                 }
2239         }
2240
2241         return count;
2242 }
2243
2244 static int
2245 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2246                                  __rte_unused uint16_t queue_id,
2247                                  __rte_unused uint8_t stat_idx,
2248                                  __rte_unused uint8_t is_rx)
2249 {
2250         PMD_INIT_FUNC_TRACE();
2251
2252         return -ENOSYS;
2253 }
2254
2255 static void
2256 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2257 {
2258         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2259         struct i40e_vsi *vsi = pf->main_vsi;
2260
2261         dev_info->max_rx_queues = vsi->nb_qps;
2262         dev_info->max_tx_queues = vsi->nb_qps;
2263         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2264         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2265         dev_info->max_mac_addrs = vsi->max_macaddrs;
2266         dev_info->max_vfs = dev->pci_dev->max_vfs;
2267         dev_info->rx_offload_capa =
2268                 DEV_RX_OFFLOAD_VLAN_STRIP |
2269                 DEV_RX_OFFLOAD_QINQ_STRIP |
2270                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2271                 DEV_RX_OFFLOAD_UDP_CKSUM |
2272                 DEV_RX_OFFLOAD_TCP_CKSUM;
2273         dev_info->tx_offload_capa =
2274                 DEV_TX_OFFLOAD_VLAN_INSERT |
2275                 DEV_TX_OFFLOAD_QINQ_INSERT |
2276                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2277                 DEV_TX_OFFLOAD_UDP_CKSUM |
2278                 DEV_TX_OFFLOAD_TCP_CKSUM |
2279                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2280                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2281                 DEV_TX_OFFLOAD_TCP_TSO;
2282         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2283                                                 sizeof(uint32_t);
2284         dev_info->reta_size = pf->hash_lut_size;
2285         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2286
2287         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2288                 .rx_thresh = {
2289                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2290                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2291                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2292                 },
2293                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2294                 .rx_drop_en = 0,
2295         };
2296
2297         dev_info->default_txconf = (struct rte_eth_txconf) {
2298                 .tx_thresh = {
2299                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2300                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2301                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2302                 },
2303                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2304                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2305                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2306                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2307         };
2308
2309         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2310                 .nb_max = I40E_MAX_RING_DESC,
2311                 .nb_min = I40E_MIN_RING_DESC,
2312                 .nb_align = I40E_ALIGN_RING_DESC,
2313         };
2314
2315         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2316                 .nb_max = I40E_MAX_RING_DESC,
2317                 .nb_min = I40E_MIN_RING_DESC,
2318                 .nb_align = I40E_ALIGN_RING_DESC,
2319         };
2320
2321         if (pf->flags & I40E_FLAG_VMDQ) {
2322                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2323                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2324                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2325                                                 pf->max_nb_vmdq_vsi;
2326                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2327                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2328                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2329         }
2330 }
2331
2332 static int
2333 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2334 {
2335         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2336         struct i40e_vsi *vsi = pf->main_vsi;
2337         PMD_INIT_FUNC_TRACE();
2338
2339         if (on)
2340                 return i40e_vsi_add_vlan(vsi, vlan_id);
2341         else
2342                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2343 }
2344
2345 static int
2346 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2347                    enum rte_vlan_type vlan_type,
2348                    uint16_t tpid)
2349 {
2350         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351         uint64_t reg_r = 0, reg_w = 0;
2352         uint16_t reg_id = 0;
2353         int ret = 0;
2354
2355         switch (vlan_type) {
2356         case ETH_VLAN_TYPE_OUTER:
2357                 reg_id = 2;
2358                 break;
2359         case ETH_VLAN_TYPE_INNER:
2360                 reg_id = 3;
2361                 break;
2362         default:
2363                 ret = -EINVAL;
2364                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2365                 return ret;
2366         }
2367         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2368                                           &reg_r, NULL);
2369         if (ret != I40E_SUCCESS) {
2370                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2371                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2372                 ret = -EIO;
2373                 return ret;
2374         }
2375         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2376                     "0x%08"PRIx64"", reg_id, reg_r);
2377
2378         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2379         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2380         if (reg_r == reg_w) {
2381                 ret = 0;
2382                 PMD_DRV_LOG(DEBUG, "No need to write");
2383                 return ret;
2384         }
2385
2386         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2387                                            reg_w, NULL);
2388         if (ret != I40E_SUCCESS) {
2389                 ret = -EIO;
2390                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2391                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2392                 return ret;
2393         }
2394         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2395                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2396
2397         return ret;
2398 }
2399
2400 static void
2401 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2402 {
2403         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2404         struct i40e_vsi *vsi = pf->main_vsi;
2405
2406         if (mask & ETH_VLAN_FILTER_MASK) {
2407                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2408                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2409                 else
2410                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2411         }
2412
2413         if (mask & ETH_VLAN_STRIP_MASK) {
2414                 /* Enable or disable VLAN stripping */
2415                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2416                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2417                 else
2418                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2419         }
2420
2421         if (mask & ETH_VLAN_EXTEND_MASK) {
2422                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2423                         i40e_vsi_config_double_vlan(vsi, TRUE);
2424                 else
2425                         i40e_vsi_config_double_vlan(vsi, FALSE);
2426         }
2427 }
2428
2429 static void
2430 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2431                           __rte_unused uint16_t queue,
2432                           __rte_unused int on)
2433 {
2434         PMD_INIT_FUNC_TRACE();
2435 }
2436
2437 static int
2438 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2439 {
2440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2441         struct i40e_vsi *vsi = pf->main_vsi;
2442         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2443         struct i40e_vsi_vlan_pvid_info info;
2444
2445         memset(&info, 0, sizeof(info));
2446         info.on = on;
2447         if (info.on)
2448                 info.config.pvid = pvid;
2449         else {
2450                 info.config.reject.tagged =
2451                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2452                 info.config.reject.untagged =
2453                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2454         }
2455
2456         return i40e_vsi_vlan_pvid_set(vsi, &info);
2457 }
2458
2459 static int
2460 i40e_dev_led_on(struct rte_eth_dev *dev)
2461 {
2462         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463         uint32_t mode = i40e_led_get(hw);
2464
2465         if (mode == 0)
2466                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2467
2468         return 0;
2469 }
2470
2471 static int
2472 i40e_dev_led_off(struct rte_eth_dev *dev)
2473 {
2474         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         uint32_t mode = i40e_led_get(hw);
2476
2477         if (mode != 0)
2478                 i40e_led_set(hw, 0, false);
2479
2480         return 0;
2481 }
2482
2483 static int
2484 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2485 {
2486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2488
2489         fc_conf->pause_time = pf->fc_conf.pause_time;
2490         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2491         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2492
2493          /* Return current mode according to actual setting*/
2494         switch (hw->fc.current_mode) {
2495         case I40E_FC_FULL:
2496                 fc_conf->mode = RTE_FC_FULL;
2497                 break;
2498         case I40E_FC_TX_PAUSE:
2499                 fc_conf->mode = RTE_FC_TX_PAUSE;
2500                 break;
2501         case I40E_FC_RX_PAUSE:
2502                 fc_conf->mode = RTE_FC_RX_PAUSE;
2503                 break;
2504         case I40E_FC_NONE:
2505         default:
2506                 fc_conf->mode = RTE_FC_NONE;
2507         };
2508
2509         return 0;
2510 }
2511
2512 static int
2513 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2514 {
2515         uint32_t mflcn_reg, fctrl_reg, reg;
2516         uint32_t max_high_water;
2517         uint8_t i, aq_failure;
2518         int err;
2519         struct i40e_hw *hw;
2520         struct i40e_pf *pf;
2521         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2522                 [RTE_FC_NONE] = I40E_FC_NONE,
2523                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2524                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2525                 [RTE_FC_FULL] = I40E_FC_FULL
2526         };
2527
2528         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2529
2530         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2531         if ((fc_conf->high_water > max_high_water) ||
2532                         (fc_conf->high_water < fc_conf->low_water)) {
2533                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2534                         "High_water must <= %d.", max_high_water);
2535                 return -EINVAL;
2536         }
2537
2538         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2540         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2541
2542         pf->fc_conf.pause_time = fc_conf->pause_time;
2543         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2544         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2545
2546         PMD_INIT_FUNC_TRACE();
2547
2548         /* All the link flow control related enable/disable register
2549          * configuration is handle by the F/W
2550          */
2551         err = i40e_set_fc(hw, &aq_failure, true);
2552         if (err < 0)
2553                 return -ENOSYS;
2554
2555         if (i40e_is_40G_device(hw->device_id)) {
2556                 /* Configure flow control refresh threshold,
2557                  * the value for stat_tx_pause_refresh_timer[8]
2558                  * is used for global pause operation.
2559                  */
2560
2561                 I40E_WRITE_REG(hw,
2562                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2563                                pf->fc_conf.pause_time);
2564
2565                 /* configure the timer value included in transmitted pause
2566                  * frame,
2567                  * the value for stat_tx_pause_quanta[8] is used for global
2568                  * pause operation
2569                  */
2570                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2571                                pf->fc_conf.pause_time);
2572
2573                 fctrl_reg = I40E_READ_REG(hw,
2574                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2575
2576                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2577                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2578                 else
2579                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2580
2581                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2582                                fctrl_reg);
2583         } else {
2584                 /* Configure pause time (2 TCs per register) */
2585                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2586                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2587                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2588
2589                 /* Configure flow control refresh threshold value */
2590                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2591                                pf->fc_conf.pause_time / 2);
2592
2593                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2594
2595                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2596                  *depending on configuration
2597                  */
2598                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2599                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2600                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2601                 } else {
2602                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2603                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2604                 }
2605
2606                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2607         }
2608
2609         /* config the water marker both based on the packets and bytes */
2610         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2611                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2612                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2613         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2614                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2615                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2616         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2617                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2618                        << I40E_KILOSHIFT);
2619         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2620                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2621                        << I40E_KILOSHIFT);
2622
2623         I40E_WRITE_FLUSH(hw);
2624
2625         return 0;
2626 }
2627
2628 static int
2629 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2630                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2631 {
2632         PMD_INIT_FUNC_TRACE();
2633
2634         return -ENOSYS;
2635 }
2636
2637 /* Add a MAC address, and update filters */
2638 static void
2639 i40e_macaddr_add(struct rte_eth_dev *dev,
2640                  struct ether_addr *mac_addr,
2641                  __rte_unused uint32_t index,
2642                  uint32_t pool)
2643 {
2644         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2645         struct i40e_mac_filter_info mac_filter;
2646         struct i40e_vsi *vsi;
2647         int ret;
2648
2649         /* If VMDQ not enabled or configured, return */
2650         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2651                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2652                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2653                         pool);
2654                 return;
2655         }
2656
2657         if (pool > pf->nb_cfg_vmdq_vsi) {
2658                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2659                                 pool, pf->nb_cfg_vmdq_vsi);
2660                 return;
2661         }
2662
2663         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2664         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2665                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2666         else
2667                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2668
2669         if (pool == 0)
2670                 vsi = pf->main_vsi;
2671         else
2672                 vsi = pf->vmdq[pool - 1].vsi;
2673
2674         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2675         if (ret != I40E_SUCCESS) {
2676                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2677                 return;
2678         }
2679 }
2680
2681 /* Remove a MAC address, and update filters */
2682 static void
2683 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2684 {
2685         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2686         struct i40e_vsi *vsi;
2687         struct rte_eth_dev_data *data = dev->data;
2688         struct ether_addr *macaddr;
2689         int ret;
2690         uint32_t i;
2691         uint64_t pool_sel;
2692
2693         macaddr = &(data->mac_addrs[index]);
2694
2695         pool_sel = dev->data->mac_pool_sel[index];
2696
2697         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2698                 if (pool_sel & (1ULL << i)) {
2699                         if (i == 0)
2700                                 vsi = pf->main_vsi;
2701                         else {
2702                                 /* No VMDQ pool enabled or configured */
2703                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2704                                         (i > pf->nb_cfg_vmdq_vsi)) {
2705                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2706                                                         "/configured");
2707                                         return;
2708                                 }
2709                                 vsi = pf->vmdq[i - 1].vsi;
2710                         }
2711                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2712
2713                         if (ret) {
2714                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2715                                 return;
2716                         }
2717                 }
2718         }
2719 }
2720
2721 /* Set perfect match or hash match of MAC and VLAN for a VF */
2722 static int
2723 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2724                  struct rte_eth_mac_filter *filter,
2725                  bool add)
2726 {
2727         struct i40e_hw *hw;
2728         struct i40e_mac_filter_info mac_filter;
2729         struct ether_addr old_mac;
2730         struct ether_addr *new_mac;
2731         struct i40e_pf_vf *vf = NULL;
2732         uint16_t vf_id;
2733         int ret;
2734
2735         if (pf == NULL) {
2736                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2737                 return -EINVAL;
2738         }
2739         hw = I40E_PF_TO_HW(pf);
2740
2741         if (filter == NULL) {
2742                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2743                 return -EINVAL;
2744         }
2745
2746         new_mac = &filter->mac_addr;
2747
2748         if (is_zero_ether_addr(new_mac)) {
2749                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2750                 return -EINVAL;
2751         }
2752
2753         vf_id = filter->dst_id;
2754
2755         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2756                 PMD_DRV_LOG(ERR, "Invalid argument.");
2757                 return -EINVAL;
2758         }
2759         vf = &pf->vfs[vf_id];
2760
2761         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2762                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2763                 return -EINVAL;
2764         }
2765
2766         if (add) {
2767                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2768                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2769                                 ETHER_ADDR_LEN);
2770                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2771                                  ETHER_ADDR_LEN);
2772
2773                 mac_filter.filter_type = filter->filter_type;
2774                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2775                 if (ret != I40E_SUCCESS) {
2776                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2777                         return -1;
2778                 }
2779                 ether_addr_copy(new_mac, &pf->dev_addr);
2780         } else {
2781                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2782                                 ETHER_ADDR_LEN);
2783                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2784                 if (ret != I40E_SUCCESS) {
2785                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2786                         return -1;
2787                 }
2788
2789                 /* Clear device address as it has been removed */
2790                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2791                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2792         }
2793
2794         return 0;
2795 }
2796
2797 /* MAC filter handle */
2798 static int
2799 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2800                 void *arg)
2801 {
2802         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2803         struct rte_eth_mac_filter *filter;
2804         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2805         int ret = I40E_NOT_SUPPORTED;
2806
2807         filter = (struct rte_eth_mac_filter *)(arg);
2808
2809         switch (filter_op) {
2810         case RTE_ETH_FILTER_NOP:
2811                 ret = I40E_SUCCESS;
2812                 break;
2813         case RTE_ETH_FILTER_ADD:
2814                 i40e_pf_disable_irq0(hw);
2815                 if (filter->is_vf)
2816                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2817                 i40e_pf_enable_irq0(hw);
2818                 break;
2819         case RTE_ETH_FILTER_DELETE:
2820                 i40e_pf_disable_irq0(hw);
2821                 if (filter->is_vf)
2822                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2823                 i40e_pf_enable_irq0(hw);
2824                 break;
2825         default:
2826                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2827                 ret = I40E_ERR_PARAM;
2828                 break;
2829         }
2830
2831         return ret;
2832 }
2833
2834 static int
2835 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2836 {
2837         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2838         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2839         int ret;
2840
2841         if (!lut)
2842                 return -EINVAL;
2843
2844         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2845                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2846                                           lut, lut_size);
2847                 if (ret) {
2848                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2849                         return ret;
2850                 }
2851         } else {
2852                 uint32_t *lut_dw = (uint32_t *)lut;
2853                 uint16_t i, lut_size_dw = lut_size / 4;
2854
2855                 for (i = 0; i < lut_size_dw; i++)
2856                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2857         }
2858
2859         return 0;
2860 }
2861
2862 static int
2863 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2864 {
2865         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2866         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2867         int ret;
2868
2869         if (!vsi || !lut)
2870                 return -EINVAL;
2871
2872         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2873                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2874                                           lut, lut_size);
2875                 if (ret) {
2876                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2877                         return ret;
2878                 }
2879         } else {
2880                 uint32_t *lut_dw = (uint32_t *)lut;
2881                 uint16_t i, lut_size_dw = lut_size / 4;
2882
2883                 for (i = 0; i < lut_size_dw; i++)
2884                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2885                 I40E_WRITE_FLUSH(hw);
2886         }
2887
2888         return 0;
2889 }
2890
2891 static int
2892 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2893                          struct rte_eth_rss_reta_entry64 *reta_conf,
2894                          uint16_t reta_size)
2895 {
2896         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2897         uint16_t i, lut_size = pf->hash_lut_size;
2898         uint16_t idx, shift;
2899         uint8_t *lut;
2900         int ret;
2901
2902         if (reta_size != lut_size ||
2903                 reta_size > ETH_RSS_RETA_SIZE_512) {
2904                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2905                         "(%d) doesn't match the number hardware can supported "
2906                                         "(%d)\n", reta_size, lut_size);
2907                 return -EINVAL;
2908         }
2909
2910         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2911         if (!lut) {
2912                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2913                 return -ENOMEM;
2914         }
2915         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2916         if (ret)
2917                 goto out;
2918         for (i = 0; i < reta_size; i++) {
2919                 idx = i / RTE_RETA_GROUP_SIZE;
2920                 shift = i % RTE_RETA_GROUP_SIZE;
2921                 if (reta_conf[idx].mask & (1ULL << shift))
2922                         lut[i] = reta_conf[idx].reta[shift];
2923         }
2924         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2925
2926 out:
2927         rte_free(lut);
2928
2929         return ret;
2930 }
2931
2932 static int
2933 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2934                         struct rte_eth_rss_reta_entry64 *reta_conf,
2935                         uint16_t reta_size)
2936 {
2937         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2938         uint16_t i, lut_size = pf->hash_lut_size;
2939         uint16_t idx, shift;
2940         uint8_t *lut;
2941         int ret;
2942
2943         if (reta_size != lut_size ||
2944                 reta_size > ETH_RSS_RETA_SIZE_512) {
2945                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2946                         "(%d) doesn't match the number hardware can supported "
2947                                         "(%d)\n", reta_size, lut_size);
2948                 return -EINVAL;
2949         }
2950
2951         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2952         if (!lut) {
2953                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2954                 return -ENOMEM;
2955         }
2956
2957         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2958         if (ret)
2959                 goto out;
2960         for (i = 0; i < reta_size; i++) {
2961                 idx = i / RTE_RETA_GROUP_SIZE;
2962                 shift = i % RTE_RETA_GROUP_SIZE;
2963                 if (reta_conf[idx].mask & (1ULL << shift))
2964                         reta_conf[idx].reta[shift] = lut[i];
2965         }
2966
2967 out:
2968         rte_free(lut);
2969
2970         return ret;
2971 }
2972
2973 /**
2974  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2975  * @hw:   pointer to the HW structure
2976  * @mem:  pointer to mem struct to fill out
2977  * @size: size of memory requested
2978  * @alignment: what to align the allocation to
2979  **/
2980 enum i40e_status_code
2981 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2982                         struct i40e_dma_mem *mem,
2983                         u64 size,
2984                         u32 alignment)
2985 {
2986         const struct rte_memzone *mz = NULL;
2987         char z_name[RTE_MEMZONE_NAMESIZE];
2988
2989         if (!mem)
2990                 return I40E_ERR_PARAM;
2991
2992         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2993         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2994                                          alignment, RTE_PGSIZE_2M);
2995         if (!mz)
2996                 return I40E_ERR_NO_MEMORY;
2997
2998         mem->size = size;
2999         mem->va = mz->addr;
3000         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3001         mem->zone = (const void *)mz;
3002         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3003                     "%"PRIu64, mz->name, mem->pa);
3004
3005         return I40E_SUCCESS;
3006 }
3007
3008 /**
3009  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3010  * @hw:   pointer to the HW structure
3011  * @mem:  ptr to mem struct to free
3012  **/
3013 enum i40e_status_code
3014 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3015                     struct i40e_dma_mem *mem)
3016 {
3017         if (!mem)
3018                 return I40E_ERR_PARAM;
3019
3020         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3021                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3022                     mem->pa);
3023         rte_memzone_free((const struct rte_memzone *)mem->zone);
3024         mem->zone = NULL;
3025         mem->va = NULL;
3026         mem->pa = (u64)0;
3027
3028         return I40E_SUCCESS;
3029 }
3030
3031 /**
3032  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3033  * @hw:   pointer to the HW structure
3034  * @mem:  pointer to mem struct to fill out
3035  * @size: size of memory requested
3036  **/
3037 enum i40e_status_code
3038 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3039                          struct i40e_virt_mem *mem,
3040                          u32 size)
3041 {
3042         if (!mem)
3043                 return I40E_ERR_PARAM;
3044
3045         mem->size = size;
3046         mem->va = rte_zmalloc("i40e", size, 0);
3047
3048         if (mem->va)
3049                 return I40E_SUCCESS;
3050         else
3051                 return I40E_ERR_NO_MEMORY;
3052 }
3053
3054 /**
3055  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3056  * @hw:   pointer to the HW structure
3057  * @mem:  pointer to mem struct to free
3058  **/
3059 enum i40e_status_code
3060 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3061                      struct i40e_virt_mem *mem)
3062 {
3063         if (!mem)
3064                 return I40E_ERR_PARAM;
3065
3066         rte_free(mem->va);
3067         mem->va = NULL;
3068
3069         return I40E_SUCCESS;
3070 }
3071
3072 void
3073 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3074 {
3075         rte_spinlock_init(&sp->spinlock);
3076 }
3077
3078 void
3079 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3080 {
3081         rte_spinlock_lock(&sp->spinlock);
3082 }
3083
3084 void
3085 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3086 {
3087         rte_spinlock_unlock(&sp->spinlock);
3088 }
3089
3090 void
3091 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3092 {
3093         return;
3094 }
3095
3096 /**
3097  * Get the hardware capabilities, which will be parsed
3098  * and saved into struct i40e_hw.
3099  */
3100 static int
3101 i40e_get_cap(struct i40e_hw *hw)
3102 {
3103         struct i40e_aqc_list_capabilities_element_resp *buf;
3104         uint16_t len, size = 0;
3105         int ret;
3106
3107         /* Calculate a huge enough buff for saving response data temporarily */
3108         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3109                                                 I40E_MAX_CAP_ELE_NUM;
3110         buf = rte_zmalloc("i40e", len, 0);
3111         if (!buf) {
3112                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3113                 return I40E_ERR_NO_MEMORY;
3114         }
3115
3116         /* Get, parse the capabilities and save it to hw */
3117         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3118                         i40e_aqc_opc_list_func_capabilities, NULL);
3119         if (ret != I40E_SUCCESS)
3120                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3121
3122         /* Free the temporary buffer after being used */
3123         rte_free(buf);
3124
3125         return ret;
3126 }
3127
3128 static int
3129 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3130 {
3131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3132         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3133         uint16_t qp_count = 0, vsi_count = 0;
3134
3135         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3136                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3137                 return -EINVAL;
3138         }
3139         /* Add the parameter init for LFC */
3140         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3141         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3142         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3143
3144         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3145         pf->max_num_vsi = hw->func_caps.num_vsis;
3146         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3147         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3148         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3149
3150         /* FDir queue/VSI allocation */
3151         pf->fdir_qp_offset = 0;
3152         if (hw->func_caps.fd) {
3153                 pf->flags |= I40E_FLAG_FDIR;
3154                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3155         } else {
3156                 pf->fdir_nb_qps = 0;
3157         }
3158         qp_count += pf->fdir_nb_qps;
3159         vsi_count += 1;
3160
3161         /* LAN queue/VSI allocation */
3162         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3163         if (!hw->func_caps.rss) {
3164                 pf->lan_nb_qps = 1;
3165         } else {
3166                 pf->flags |= I40E_FLAG_RSS;
3167                 if (hw->mac.type == I40E_MAC_X722)
3168                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3169                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3170         }
3171         qp_count += pf->lan_nb_qps;
3172         vsi_count += 1;
3173
3174         /* VF queue/VSI allocation */
3175         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3176         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3177                 pf->flags |= I40E_FLAG_SRIOV;
3178                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3179                 pf->vf_num = dev->pci_dev->max_vfs;
3180                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3181                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3182                             pf->vf_nb_qps * pf->vf_num);
3183         } else {
3184                 pf->vf_nb_qps = 0;
3185                 pf->vf_num = 0;
3186         }
3187         qp_count += pf->vf_nb_qps * pf->vf_num;
3188         vsi_count += pf->vf_num;
3189
3190         /* VMDq queue/VSI allocation */
3191         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3192         pf->vmdq_nb_qps = 0;
3193         pf->max_nb_vmdq_vsi = 0;
3194         if (hw->func_caps.vmdq) {
3195                 if (qp_count < hw->func_caps.num_tx_qp &&
3196                         vsi_count < hw->func_caps.num_vsis) {
3197                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3198                                 qp_count) / pf->vmdq_nb_qp_max;
3199
3200                         /* Limit the maximum number of VMDq vsi to the maximum
3201                          * ethdev can support
3202                          */
3203                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3204                                 hw->func_caps.num_vsis - vsi_count);
3205                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3206                                 ETH_64_POOLS);
3207                         if (pf->max_nb_vmdq_vsi) {
3208                                 pf->flags |= I40E_FLAG_VMDQ;
3209                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3210                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3211                                             "per VMDQ VSI, in total %u queues",
3212                                             pf->max_nb_vmdq_vsi,
3213                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3214                                             pf->max_nb_vmdq_vsi);
3215                         } else {
3216                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3217                                             "VMDq");
3218                         }
3219                 } else {
3220                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3221                 }
3222         }
3223         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3224         vsi_count += pf->max_nb_vmdq_vsi;
3225
3226         if (hw->func_caps.dcb)
3227                 pf->flags |= I40E_FLAG_DCB;
3228
3229         if (qp_count > hw->func_caps.num_tx_qp) {
3230                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3231                             "the hardware maximum %u", qp_count,
3232                             hw->func_caps.num_tx_qp);
3233                 return -EINVAL;
3234         }
3235         if (vsi_count > hw->func_caps.num_vsis) {
3236                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3237                             "the hardware maximum %u", vsi_count,
3238                             hw->func_caps.num_vsis);
3239                 return -EINVAL;
3240         }
3241
3242         return 0;
3243 }
3244
3245 static int
3246 i40e_pf_get_switch_config(struct i40e_pf *pf)
3247 {
3248         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3249         struct i40e_aqc_get_switch_config_resp *switch_config;
3250         struct i40e_aqc_switch_config_element_resp *element;
3251         uint16_t start_seid = 0, num_reported;
3252         int ret;
3253
3254         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3255                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3256         if (!switch_config) {
3257                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3258                 return -ENOMEM;
3259         }
3260
3261         /* Get the switch configurations */
3262         ret = i40e_aq_get_switch_config(hw, switch_config,
3263                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3264         if (ret != I40E_SUCCESS) {
3265                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3266                 goto fail;
3267         }
3268         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3269         if (num_reported != 1) { /* The number should be 1 */
3270                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3271                 goto fail;
3272         }
3273
3274         /* Parse the switch configuration elements */
3275         element = &(switch_config->element[0]);
3276         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3277                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3278                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3279         } else
3280                 PMD_DRV_LOG(INFO, "Unknown element type");
3281
3282 fail:
3283         rte_free(switch_config);
3284
3285         return ret;
3286 }
3287
3288 static int
3289 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3290                         uint32_t num)
3291 {
3292         struct pool_entry *entry;
3293
3294         if (pool == NULL || num == 0)
3295                 return -EINVAL;
3296
3297         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3298         if (entry == NULL) {
3299                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3300                 return -ENOMEM;
3301         }
3302
3303         /* queue heap initialize */
3304         pool->num_free = num;
3305         pool->num_alloc = 0;
3306         pool->base = base;
3307         LIST_INIT(&pool->alloc_list);
3308         LIST_INIT(&pool->free_list);
3309
3310         /* Initialize element  */
3311         entry->base = 0;
3312         entry->len = num;
3313
3314         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3315         return 0;
3316 }
3317
3318 static void
3319 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3320 {
3321         struct pool_entry *entry;
3322
3323         if (pool == NULL)
3324                 return;
3325
3326         LIST_FOREACH(entry, &pool->alloc_list, next) {
3327                 LIST_REMOVE(entry, next);
3328                 rte_free(entry);
3329         }
3330
3331         LIST_FOREACH(entry, &pool->free_list, next) {
3332                 LIST_REMOVE(entry, next);
3333                 rte_free(entry);
3334         }
3335
3336         pool->num_free = 0;
3337         pool->num_alloc = 0;
3338         pool->base = 0;
3339         LIST_INIT(&pool->alloc_list);
3340         LIST_INIT(&pool->free_list);
3341 }
3342
3343 static int
3344 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3345                        uint32_t base)
3346 {
3347         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3348         uint32_t pool_offset;
3349         int insert;
3350
3351         if (pool == NULL) {
3352                 PMD_DRV_LOG(ERR, "Invalid parameter");
3353                 return -EINVAL;
3354         }
3355
3356         pool_offset = base - pool->base;
3357         /* Lookup in alloc list */
3358         LIST_FOREACH(entry, &pool->alloc_list, next) {
3359                 if (entry->base == pool_offset) {
3360                         valid_entry = entry;
3361                         LIST_REMOVE(entry, next);
3362                         break;
3363                 }
3364         }
3365
3366         /* Not find, return */
3367         if (valid_entry == NULL) {
3368                 PMD_DRV_LOG(ERR, "Failed to find entry");
3369                 return -EINVAL;
3370         }
3371
3372         /**
3373          * Found it, move it to free list  and try to merge.
3374          * In order to make merge easier, always sort it by qbase.
3375          * Find adjacent prev and last entries.
3376          */
3377         prev = next = NULL;
3378         LIST_FOREACH(entry, &pool->free_list, next) {
3379                 if (entry->base > valid_entry->base) {
3380                         next = entry;
3381                         break;
3382                 }
3383                 prev = entry;
3384         }
3385
3386         insert = 0;
3387         /* Try to merge with next one*/
3388         if (next != NULL) {
3389                 /* Merge with next one */
3390                 if (valid_entry->base + valid_entry->len == next->base) {
3391                         next->base = valid_entry->base;
3392                         next->len += valid_entry->len;
3393                         rte_free(valid_entry);
3394                         valid_entry = next;
3395                         insert = 1;
3396                 }
3397         }
3398
3399         if (prev != NULL) {
3400                 /* Merge with previous one */
3401                 if (prev->base + prev->len == valid_entry->base) {
3402                         prev->len += valid_entry->len;
3403                         /* If it merge with next one, remove next node */
3404                         if (insert == 1) {
3405                                 LIST_REMOVE(valid_entry, next);
3406                                 rte_free(valid_entry);
3407                         } else {
3408                                 rte_free(valid_entry);
3409                                 insert = 1;
3410                         }
3411                 }
3412         }
3413
3414         /* Not find any entry to merge, insert */
3415         if (insert == 0) {
3416                 if (prev != NULL)
3417                         LIST_INSERT_AFTER(prev, valid_entry, next);
3418                 else if (next != NULL)
3419                         LIST_INSERT_BEFORE(next, valid_entry, next);
3420                 else /* It's empty list, insert to head */
3421                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3422         }
3423
3424         pool->num_free += valid_entry->len;
3425         pool->num_alloc -= valid_entry->len;
3426
3427         return 0;
3428 }
3429
3430 static int
3431 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3432                        uint16_t num)
3433 {
3434         struct pool_entry *entry, *valid_entry;
3435
3436         if (pool == NULL || num == 0) {
3437                 PMD_DRV_LOG(ERR, "Invalid parameter");
3438                 return -EINVAL;
3439         }
3440
3441         if (pool->num_free < num) {
3442                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3443                             num, pool->num_free);
3444                 return -ENOMEM;
3445         }
3446
3447         valid_entry = NULL;
3448         /* Lookup  in free list and find most fit one */
3449         LIST_FOREACH(entry, &pool->free_list, next) {
3450                 if (entry->len >= num) {
3451                         /* Find best one */
3452                         if (entry->len == num) {
3453                                 valid_entry = entry;
3454                                 break;
3455                         }
3456                         if (valid_entry == NULL || valid_entry->len > entry->len)
3457                                 valid_entry = entry;
3458                 }
3459         }
3460
3461         /* Not find one to satisfy the request, return */
3462         if (valid_entry == NULL) {
3463                 PMD_DRV_LOG(ERR, "No valid entry found");
3464                 return -ENOMEM;
3465         }
3466         /**
3467          * The entry have equal queue number as requested,
3468          * remove it from alloc_list.
3469          */
3470         if (valid_entry->len == num) {
3471                 LIST_REMOVE(valid_entry, next);
3472         } else {
3473                 /**
3474                  * The entry have more numbers than requested,
3475                  * create a new entry for alloc_list and minus its
3476                  * queue base and number in free_list.
3477                  */
3478                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3479                 if (entry == NULL) {
3480                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3481                                     "resource pool");
3482                         return -ENOMEM;
3483                 }
3484                 entry->base = valid_entry->base;
3485                 entry->len = num;
3486                 valid_entry->base += num;
3487                 valid_entry->len -= num;
3488                 valid_entry = entry;
3489         }
3490
3491         /* Insert it into alloc list, not sorted */
3492         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3493
3494         pool->num_free -= valid_entry->len;
3495         pool->num_alloc += valid_entry->len;
3496
3497         return valid_entry->base + pool->base;
3498 }
3499
3500 /**
3501  * bitmap_is_subset - Check whether src2 is subset of src1
3502  **/
3503 static inline int
3504 bitmap_is_subset(uint8_t src1, uint8_t src2)
3505 {
3506         return !((src1 ^ src2) & src2);
3507 }
3508
3509 static enum i40e_status_code
3510 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3511 {
3512         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3513
3514         /* If DCB is not supported, only default TC is supported */
3515         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3516                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3517                 return I40E_NOT_SUPPORTED;
3518         }
3519
3520         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3521                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3522                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3523                             enabled_tcmap);
3524                 return I40E_NOT_SUPPORTED;
3525         }
3526         return I40E_SUCCESS;
3527 }
3528
3529 int
3530 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3531                                 struct i40e_vsi_vlan_pvid_info *info)
3532 {
3533         struct i40e_hw *hw;
3534         struct i40e_vsi_context ctxt;
3535         uint8_t vlan_flags = 0;
3536         int ret;
3537
3538         if (vsi == NULL || info == NULL) {
3539                 PMD_DRV_LOG(ERR, "invalid parameters");
3540                 return I40E_ERR_PARAM;
3541         }
3542
3543         if (info->on) {
3544                 vsi->info.pvid = info->config.pvid;
3545                 /**
3546                  * If insert pvid is enabled, only tagged pkts are
3547                  * allowed to be sent out.
3548                  */
3549                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3550                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3551         } else {
3552                 vsi->info.pvid = 0;
3553                 if (info->config.reject.tagged == 0)
3554                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3555
3556                 if (info->config.reject.untagged == 0)
3557                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3558         }
3559         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3560                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3561         vsi->info.port_vlan_flags |= vlan_flags;
3562         vsi->info.valid_sections =
3563                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3564         memset(&ctxt, 0, sizeof(ctxt));
3565         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3566         ctxt.seid = vsi->seid;
3567
3568         hw = I40E_VSI_TO_HW(vsi);
3569         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3570         if (ret != I40E_SUCCESS)
3571                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3572
3573         return ret;
3574 }
3575
3576 static int
3577 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3578 {
3579         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3580         int i, ret;
3581         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3582
3583         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3584         if (ret != I40E_SUCCESS)
3585                 return ret;
3586
3587         if (!vsi->seid) {
3588                 PMD_DRV_LOG(ERR, "seid not valid");
3589                 return -EINVAL;
3590         }
3591
3592         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3593         tc_bw_data.tc_valid_bits = enabled_tcmap;
3594         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3595                 tc_bw_data.tc_bw_credits[i] =
3596                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3597
3598         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3599         if (ret != I40E_SUCCESS) {
3600                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3601                 return ret;
3602         }
3603
3604         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3605                                         sizeof(vsi->info.qs_handle));
3606         return I40E_SUCCESS;
3607 }
3608
3609 static enum i40e_status_code
3610 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3611                                  struct i40e_aqc_vsi_properties_data *info,
3612                                  uint8_t enabled_tcmap)
3613 {
3614         enum i40e_status_code ret;
3615         int i, total_tc = 0;
3616         uint16_t qpnum_per_tc, bsf, qp_idx;
3617
3618         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3619         if (ret != I40E_SUCCESS)
3620                 return ret;
3621
3622         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3623                 if (enabled_tcmap & (1 << i))
3624                         total_tc++;
3625         vsi->enabled_tc = enabled_tcmap;
3626
3627         /* Number of queues per enabled TC */
3628         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3629         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3630         bsf = rte_bsf32(qpnum_per_tc);
3631
3632         /* Adjust the queue number to actual queues that can be applied */
3633         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3634                 vsi->nb_qps = qpnum_per_tc * total_tc;
3635
3636         /**
3637          * Configure TC and queue mapping parameters, for enabled TC,
3638          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3639          * default queue will serve it.
3640          */
3641         qp_idx = 0;
3642         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3643                 if (vsi->enabled_tc & (1 << i)) {
3644                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3645                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3646                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3647                         qp_idx += qpnum_per_tc;
3648                 } else
3649                         info->tc_mapping[i] = 0;
3650         }
3651
3652         /* Associate queue number with VSI */
3653         if (vsi->type == I40E_VSI_SRIOV) {
3654                 info->mapping_flags |=
3655                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3656                 for (i = 0; i < vsi->nb_qps; i++)
3657                         info->queue_mapping[i] =
3658                                 rte_cpu_to_le_16(vsi->base_queue + i);
3659         } else {
3660                 info->mapping_flags |=
3661                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3662                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3663         }
3664         info->valid_sections |=
3665                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3666
3667         return I40E_SUCCESS;
3668 }
3669
3670 static int
3671 i40e_veb_release(struct i40e_veb *veb)
3672 {
3673         struct i40e_vsi *vsi;
3674         struct i40e_hw *hw;
3675
3676         if (veb == NULL || veb->associate_vsi == NULL)
3677                 return -EINVAL;
3678
3679         if (!TAILQ_EMPTY(&veb->head)) {
3680                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3681                 return -EACCES;
3682         }
3683
3684         vsi = veb->associate_vsi;
3685         hw = I40E_VSI_TO_HW(vsi);
3686
3687         vsi->uplink_seid = veb->uplink_seid;
3688         i40e_aq_delete_element(hw, veb->seid, NULL);
3689         rte_free(veb);
3690         vsi->veb = NULL;
3691         return I40E_SUCCESS;
3692 }
3693
3694 /* Setup a veb */
3695 static struct i40e_veb *
3696 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3697 {
3698         struct i40e_veb *veb;
3699         int ret;
3700         struct i40e_hw *hw;
3701
3702         if (NULL == pf || vsi == NULL) {
3703                 PMD_DRV_LOG(ERR, "veb setup failed, "
3704                             "associated VSI shouldn't null");
3705                 return NULL;
3706         }
3707         hw = I40E_PF_TO_HW(pf);
3708
3709         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3710         if (!veb) {
3711                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3712                 goto fail;
3713         }
3714
3715         veb->associate_vsi = vsi;
3716         TAILQ_INIT(&veb->head);
3717         veb->uplink_seid = vsi->uplink_seid;
3718
3719         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3720                 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3721
3722         if (ret != I40E_SUCCESS) {
3723                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3724                             hw->aq.asq_last_status);
3725                 goto fail;
3726         }
3727
3728         /* get statistics index */
3729         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3730                                 &veb->stats_idx, NULL, NULL, NULL);
3731         if (ret != I40E_SUCCESS) {
3732                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3733                             hw->aq.asq_last_status);
3734                 goto fail;
3735         }
3736
3737         /* Get VEB bandwidth, to be implemented */
3738         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3739         vsi->uplink_seid = veb->seid;
3740
3741         return veb;
3742 fail:
3743         rte_free(veb);
3744         return NULL;
3745 }
3746
3747 int
3748 i40e_vsi_release(struct i40e_vsi *vsi)
3749 {
3750         struct i40e_pf *pf;
3751         struct i40e_hw *hw;
3752         struct i40e_vsi_list *vsi_list;
3753         int ret;
3754         struct i40e_mac_filter *f;
3755
3756         if (!vsi)
3757                 return I40E_SUCCESS;
3758
3759         pf = I40E_VSI_TO_PF(vsi);
3760         hw = I40E_VSI_TO_HW(vsi);
3761
3762         /* VSI has child to attach, release child first */
3763         if (vsi->veb) {
3764                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3765                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3766                                 return -1;
3767                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3768                 }
3769                 i40e_veb_release(vsi->veb);
3770         }
3771
3772         /* Remove all macvlan filters of the VSI */
3773         i40e_vsi_remove_all_macvlan_filter(vsi);
3774         TAILQ_FOREACH(f, &vsi->mac_list, next)
3775                 rte_free(f);
3776
3777         if (vsi->type != I40E_VSI_MAIN) {
3778                 /* Remove vsi from parent's sibling list */
3779                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3780                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3781                         return I40E_ERR_PARAM;
3782                 }
3783                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3784                                 &vsi->sib_vsi_list, list);
3785
3786                 /* Remove all switch element of the VSI */
3787                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3788                 if (ret != I40E_SUCCESS)
3789                         PMD_DRV_LOG(ERR, "Failed to delete element");
3790         }
3791         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3792
3793         if (vsi->type != I40E_VSI_SRIOV)
3794                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3795         rte_free(vsi);
3796
3797         return I40E_SUCCESS;
3798 }
3799
3800 static int
3801 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3802 {
3803         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3804         struct i40e_aqc_remove_macvlan_element_data def_filter;
3805         struct i40e_mac_filter_info filter;
3806         int ret;
3807
3808         if (vsi->type != I40E_VSI_MAIN)
3809                 return I40E_ERR_CONFIG;
3810         memset(&def_filter, 0, sizeof(def_filter));
3811         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3812                                         ETH_ADDR_LEN);
3813         def_filter.vlan_tag = 0;
3814         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3815                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3816         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3817         if (ret != I40E_SUCCESS) {
3818                 struct i40e_mac_filter *f;
3819                 struct ether_addr *mac;
3820
3821                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3822                             "macvlan filter");
3823                 /* It needs to add the permanent mac into mac list */
3824                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3825                 if (f == NULL) {
3826                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3827                         return I40E_ERR_NO_MEMORY;
3828                 }
3829                 mac = &f->mac_info.mac_addr;
3830                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3831                                 ETH_ADDR_LEN);
3832                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3833                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3834                 vsi->mac_num++;
3835
3836                 return ret;
3837         }
3838         (void)rte_memcpy(&filter.mac_addr,
3839                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3840         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3841         return i40e_vsi_add_mac(vsi, &filter);
3842 }
3843
3844 /*
3845  * i40e_vsi_get_bw_config - Query VSI BW Information
3846  * @vsi: the VSI to be queried
3847  *
3848  * Returns 0 on success, negative value on failure
3849  */
3850 static enum i40e_status_code
3851 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3852 {
3853         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3854         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3855         struct i40e_hw *hw = &vsi->adapter->hw;
3856         i40e_status ret;
3857         int i;
3858         uint32_t bw_max;
3859
3860         memset(&bw_config, 0, sizeof(bw_config));
3861         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3862         if (ret != I40E_SUCCESS) {
3863                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3864                             hw->aq.asq_last_status);
3865                 return ret;
3866         }
3867
3868         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3869         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3870                                         &ets_sla_config, NULL);
3871         if (ret != I40E_SUCCESS) {
3872                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3873                             "configuration %u", hw->aq.asq_last_status);
3874                 return ret;
3875         }
3876
3877         /* store and print out BW info */
3878         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3879         vsi->bw_info.bw_max = bw_config.max_bw;
3880         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3881         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3882         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3883                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3884                      I40E_16_BIT_WIDTH);
3885         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3886                 vsi->bw_info.bw_ets_share_credits[i] =
3887                                 ets_sla_config.share_credits[i];
3888                 vsi->bw_info.bw_ets_credits[i] =
3889                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3890                 /* 4 bits per TC, 4th bit is reserved */
3891                 vsi->bw_info.bw_ets_max[i] =
3892                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3893                                   RTE_LEN2MASK(3, uint8_t));
3894                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3895                             vsi->bw_info.bw_ets_share_credits[i]);
3896                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3897                             vsi->bw_info.bw_ets_credits[i]);
3898                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3899                             vsi->bw_info.bw_ets_max[i]);
3900         }
3901
3902         return I40E_SUCCESS;
3903 }
3904
3905 /* i40e_enable_pf_lb
3906  * @pf: pointer to the pf structure
3907  *
3908  * allow loopback on pf
3909  */
3910 static inline void
3911 i40e_enable_pf_lb(struct i40e_pf *pf)
3912 {
3913         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3914         struct i40e_vsi_context ctxt;
3915         int ret;
3916
3917         /* Use the FW API if FW >= v5.0 */
3918         if (hw->aq.fw_maj_ver < 5) {
3919                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3920                 return;
3921         }
3922
3923         memset(&ctxt, 0, sizeof(ctxt));
3924         ctxt.seid = pf->main_vsi_seid;
3925         ctxt.pf_num = hw->pf_id;
3926         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3927         if (ret) {
3928                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3929                             ret, hw->aq.asq_last_status);
3930                 return;
3931         }
3932         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3933         ctxt.info.valid_sections =
3934                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3935         ctxt.info.switch_id |=
3936                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3937
3938         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3939         if (ret)
3940                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3941                             hw->aq.asq_last_status);
3942 }
3943
3944 /* Setup a VSI */
3945 struct i40e_vsi *
3946 i40e_vsi_setup(struct i40e_pf *pf,
3947                enum i40e_vsi_type type,
3948                struct i40e_vsi *uplink_vsi,
3949                uint16_t user_param)
3950 {
3951         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3952         struct i40e_vsi *vsi;
3953         struct i40e_mac_filter_info filter;
3954         int ret;
3955         struct i40e_vsi_context ctxt;
3956         struct ether_addr broadcast =
3957                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3958
3959         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3960                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3961                             "VSI link shouldn't be NULL");
3962                 return NULL;
3963         }
3964
3965         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3966                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3967                             "uplink VSI should be NULL");
3968                 return NULL;
3969         }
3970
3971         /* If uplink vsi didn't setup VEB, create one first */
3972         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3973                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3974
3975                 if (NULL == uplink_vsi->veb) {
3976                         PMD_DRV_LOG(ERR, "VEB setup failed");
3977                         return NULL;
3978                 }
3979                 /* set ALLOWLOOPBACk on pf, when veb is created */
3980                 i40e_enable_pf_lb(pf);
3981         }
3982
3983         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3984         if (!vsi) {
3985                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3986                 return NULL;
3987         }
3988         TAILQ_INIT(&vsi->mac_list);
3989         vsi->type = type;
3990         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3991         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3992         vsi->parent_vsi = uplink_vsi;
3993         vsi->user_param = user_param;
3994         /* Allocate queues */
3995         switch (vsi->type) {
3996         case I40E_VSI_MAIN  :
3997                 vsi->nb_qps = pf->lan_nb_qps;
3998                 break;
3999         case I40E_VSI_SRIOV :
4000                 vsi->nb_qps = pf->vf_nb_qps;
4001                 break;
4002         case I40E_VSI_VMDQ2:
4003                 vsi->nb_qps = pf->vmdq_nb_qps;
4004                 break;
4005         case I40E_VSI_FDIR:
4006                 vsi->nb_qps = pf->fdir_nb_qps;
4007                 break;
4008         default:
4009                 goto fail_mem;
4010         }
4011         /*
4012          * The filter status descriptor is reported in rx queue 0,
4013          * while the tx queue for fdir filter programming has no
4014          * such constraints, can be non-zero queues.
4015          * To simplify it, choose FDIR vsi use queue 0 pair.
4016          * To make sure it will use queue 0 pair, queue allocation
4017          * need be done before this function is called
4018          */
4019         if (type != I40E_VSI_FDIR) {
4020                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4021                         if (ret < 0) {
4022                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4023                                                 vsi->seid, ret);
4024                                 goto fail_mem;
4025                         }
4026                         vsi->base_queue = ret;
4027         } else
4028                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4029
4030         /* VF has MSIX interrupt in VF range, don't allocate here */
4031         if (type == I40E_VSI_MAIN) {
4032                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4033                                           RTE_MIN(vsi->nb_qps,
4034                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4035                 if (ret < 0) {
4036                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4037                                     vsi->seid, ret);
4038                         goto fail_queue_alloc;
4039                 }
4040                 vsi->msix_intr = ret;
4041                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4042         } else if (type != I40E_VSI_SRIOV) {
4043                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4044                 if (ret < 0) {
4045                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4046                         goto fail_queue_alloc;
4047                 }
4048                 vsi->msix_intr = ret;
4049                 vsi->nb_msix = 1;
4050         } else {
4051                 vsi->msix_intr = 0;
4052                 vsi->nb_msix = 0;
4053         }
4054
4055         /* Add VSI */
4056         if (type == I40E_VSI_MAIN) {
4057                 /* For main VSI, no need to add since it's default one */
4058                 vsi->uplink_seid = pf->mac_seid;
4059                 vsi->seid = pf->main_vsi_seid;
4060                 /* Bind queues with specific MSIX interrupt */
4061                 /**
4062                  * Needs 2 interrupt at least, one for misc cause which will
4063                  * enabled from OS side, Another for queues binding the
4064                  * interrupt from device side only.
4065                  */
4066
4067                 /* Get default VSI parameters from hardware */
4068                 memset(&ctxt, 0, sizeof(ctxt));
4069                 ctxt.seid = vsi->seid;
4070                 ctxt.pf_num = hw->pf_id;
4071                 ctxt.uplink_seid = vsi->uplink_seid;
4072                 ctxt.vf_num = 0;
4073                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4074                 if (ret != I40E_SUCCESS) {
4075                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4076                         goto fail_msix_alloc;
4077                 }
4078                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4079                         sizeof(struct i40e_aqc_vsi_properties_data));
4080                 vsi->vsi_id = ctxt.vsi_number;
4081                 vsi->info.valid_sections = 0;
4082
4083                 /* Configure tc, enabled TC0 only */
4084                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4085                         I40E_SUCCESS) {
4086                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4087                         goto fail_msix_alloc;
4088                 }
4089
4090                 /* TC, queue mapping */
4091                 memset(&ctxt, 0, sizeof(ctxt));
4092                 vsi->info.valid_sections |=
4093                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4094                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4095                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4096                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4097                         sizeof(struct i40e_aqc_vsi_properties_data));
4098                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4099                                                 I40E_DEFAULT_TCMAP);
4100                 if (ret != I40E_SUCCESS) {
4101                         PMD_DRV_LOG(ERR, "Failed to configure "
4102                                     "TC queue mapping");
4103                         goto fail_msix_alloc;
4104                 }
4105                 ctxt.seid = vsi->seid;
4106                 ctxt.pf_num = hw->pf_id;
4107                 ctxt.uplink_seid = vsi->uplink_seid;
4108                 ctxt.vf_num = 0;
4109
4110                 /* Update VSI parameters */
4111                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4112                 if (ret != I40E_SUCCESS) {
4113                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4114                         goto fail_msix_alloc;
4115                 }
4116
4117                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4118                                                 sizeof(vsi->info.tc_mapping));
4119                 (void)rte_memcpy(&vsi->info.queue_mapping,
4120                                 &ctxt.info.queue_mapping,
4121                         sizeof(vsi->info.queue_mapping));
4122                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4123                 vsi->info.valid_sections = 0;
4124
4125                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4126                                 ETH_ADDR_LEN);
4127
4128                 /**
4129                  * Updating default filter settings are necessary to prevent
4130                  * reception of tagged packets.
4131                  * Some old firmware configurations load a default macvlan
4132                  * filter which accepts both tagged and untagged packets.
4133                  * The updating is to use a normal filter instead if needed.
4134                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4135                  * The firmware with correct configurations load the default
4136                  * macvlan filter which is expected and cannot be removed.
4137                  */
4138                 i40e_update_default_filter_setting(vsi);
4139                 i40e_config_qinq(hw, vsi);
4140         } else if (type == I40E_VSI_SRIOV) {
4141                 memset(&ctxt, 0, sizeof(ctxt));
4142                 /**
4143                  * For other VSI, the uplink_seid equals to uplink VSI's
4144                  * uplink_seid since they share same VEB
4145                  */
4146                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4147                 ctxt.pf_num = hw->pf_id;
4148                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4149                 ctxt.uplink_seid = vsi->uplink_seid;
4150                 ctxt.connection_type = 0x1;
4151                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4152
4153                 /* Use the VEB configuration if FW >= v5.0 */
4154                 if (hw->aq.fw_maj_ver >= 5) {
4155                         /* Configure switch ID */
4156                         ctxt.info.valid_sections |=
4157                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4158                         ctxt.info.switch_id =
4159                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4160                 }
4161
4162                 /* Configure port/vlan */
4163                 ctxt.info.valid_sections |=
4164                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4165                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4166                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4167                                                 I40E_DEFAULT_TCMAP);
4168                 if (ret != I40E_SUCCESS) {
4169                         PMD_DRV_LOG(ERR, "Failed to configure "
4170                                     "TC queue mapping");
4171                         goto fail_msix_alloc;
4172                 }
4173                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4174                 ctxt.info.valid_sections |=
4175                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4176                 /**
4177                  * Since VSI is not created yet, only configure parameter,
4178                  * will add vsi below.
4179                  */
4180
4181                 i40e_config_qinq(hw, vsi);
4182         } else if (type == I40E_VSI_VMDQ2) {
4183                 memset(&ctxt, 0, sizeof(ctxt));
4184                 /*
4185                  * For other VSI, the uplink_seid equals to uplink VSI's
4186                  * uplink_seid since they share same VEB
4187                  */
4188                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4189                 ctxt.pf_num = hw->pf_id;
4190                 ctxt.vf_num = 0;
4191                 ctxt.uplink_seid = vsi->uplink_seid;
4192                 ctxt.connection_type = 0x1;
4193                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4194
4195                 ctxt.info.valid_sections |=
4196                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4197                 /* user_param carries flag to enable loop back */
4198                 if (user_param) {
4199                         ctxt.info.switch_id =
4200                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4201                         ctxt.info.switch_id |=
4202                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4203                 }
4204
4205                 /* Configure port/vlan */
4206                 ctxt.info.valid_sections |=
4207                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4208                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4209                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4210                                                 I40E_DEFAULT_TCMAP);
4211                 if (ret != I40E_SUCCESS) {
4212                         PMD_DRV_LOG(ERR, "Failed to configure "
4213                                         "TC queue mapping");
4214                         goto fail_msix_alloc;
4215                 }
4216                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4217                 ctxt.info.valid_sections |=
4218                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4219         } else if (type == I40E_VSI_FDIR) {
4220                 memset(&ctxt, 0, sizeof(ctxt));
4221                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4222                 ctxt.pf_num = hw->pf_id;
4223                 ctxt.vf_num = 0;
4224                 ctxt.uplink_seid = vsi->uplink_seid;
4225                 ctxt.connection_type = 0x1;     /* regular data port */
4226                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4227                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4228                                                 I40E_DEFAULT_TCMAP);
4229                 if (ret != I40E_SUCCESS) {
4230                         PMD_DRV_LOG(ERR, "Failed to configure "
4231                                         "TC queue mapping.");
4232                         goto fail_msix_alloc;
4233                 }
4234                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4235                 ctxt.info.valid_sections |=
4236                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4237         } else {
4238                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4239                 goto fail_msix_alloc;
4240         }
4241
4242         if (vsi->type != I40E_VSI_MAIN) {
4243                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4244                 if (ret != I40E_SUCCESS) {
4245                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4246                                     hw->aq.asq_last_status);
4247                         goto fail_msix_alloc;
4248                 }
4249                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4250                 vsi->info.valid_sections = 0;
4251                 vsi->seid = ctxt.seid;
4252                 vsi->vsi_id = ctxt.vsi_number;
4253                 vsi->sib_vsi_list.vsi = vsi;
4254                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4255                                 &vsi->sib_vsi_list, list);
4256         }
4257
4258         /* MAC/VLAN configuration */
4259         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4260         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4261
4262         ret = i40e_vsi_add_mac(vsi, &filter);
4263         if (ret != I40E_SUCCESS) {
4264                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4265                 goto fail_msix_alloc;
4266         }
4267
4268         /* Get VSI BW information */
4269         i40e_vsi_get_bw_config(vsi);
4270         return vsi;
4271 fail_msix_alloc:
4272         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4273 fail_queue_alloc:
4274         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4275 fail_mem:
4276         rte_free(vsi);
4277         return NULL;
4278 }
4279
4280 /* Configure vlan filter on or off */
4281 int
4282 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4283 {
4284         int i, num;
4285         struct i40e_mac_filter *f;
4286         struct i40e_mac_filter_info *mac_filter;
4287         enum rte_mac_filter_type desired_filter;
4288         int ret = I40E_SUCCESS;
4289
4290         if (on) {
4291                 /* Filter to match MAC and VLAN */
4292                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4293         } else {
4294                 /* Filter to match only MAC */
4295                 desired_filter = RTE_MAC_PERFECT_MATCH;
4296         }
4297
4298         num = vsi->mac_num;
4299
4300         mac_filter = rte_zmalloc("mac_filter_info_data",
4301                                  num * sizeof(*mac_filter), 0);
4302         if (mac_filter == NULL) {
4303                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4304                 return I40E_ERR_NO_MEMORY;
4305         }
4306
4307         i = 0;
4308
4309         /* Remove all existing mac */
4310         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4311                 mac_filter[i] = f->mac_info;
4312                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4313                 if (ret) {
4314                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4315                                     on ? "enable" : "disable");
4316                         goto DONE;
4317                 }
4318                 i++;
4319         }
4320
4321         /* Override with new filter */
4322         for (i = 0; i < num; i++) {
4323                 mac_filter[i].filter_type = desired_filter;
4324                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4325                 if (ret) {
4326                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4327                                     on ? "enable" : "disable");
4328                         goto DONE;
4329                 }
4330         }
4331
4332 DONE:
4333         rte_free(mac_filter);
4334         return ret;
4335 }
4336
4337 /* Configure vlan stripping on or off */
4338 int
4339 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4340 {
4341         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4342         struct i40e_vsi_context ctxt;
4343         uint8_t vlan_flags;
4344         int ret = I40E_SUCCESS;
4345
4346         /* Check if it has been already on or off */
4347         if (vsi->info.valid_sections &
4348                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4349                 if (on) {
4350                         if ((vsi->info.port_vlan_flags &
4351                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4352                                 return 0; /* already on */
4353                 } else {
4354                         if ((vsi->info.port_vlan_flags &
4355                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4356                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4357                                 return 0; /* already off */
4358                 }
4359         }
4360
4361         if (on)
4362                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4363         else
4364                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4365         vsi->info.valid_sections =
4366                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4367         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4368         vsi->info.port_vlan_flags |= vlan_flags;
4369         ctxt.seid = vsi->seid;
4370         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4371         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4372         if (ret)
4373                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4374                             on ? "enable" : "disable");
4375
4376         return ret;
4377 }
4378
4379 static int
4380 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4381 {
4382         struct rte_eth_dev_data *data = dev->data;
4383         int ret;
4384         int mask = 0;
4385
4386         /* Apply vlan offload setting */
4387         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4388         i40e_vlan_offload_set(dev, mask);
4389
4390         /* Apply double-vlan setting, not implemented yet */
4391
4392         /* Apply pvid setting */
4393         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4394                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4395         if (ret)
4396                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4397
4398         return ret;
4399 }
4400
4401 static int
4402 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4403 {
4404         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4405
4406         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4407 }
4408
4409 static int
4410 i40e_update_flow_control(struct i40e_hw *hw)
4411 {
4412 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4413         struct i40e_link_status link_status;
4414         uint32_t rxfc = 0, txfc = 0, reg;
4415         uint8_t an_info;
4416         int ret;
4417
4418         memset(&link_status, 0, sizeof(link_status));
4419         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4420         if (ret != I40E_SUCCESS) {
4421                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4422                 goto write_reg; /* Disable flow control */
4423         }
4424
4425         an_info = hw->phy.link_info.an_info;
4426         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4427                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4428                 ret = I40E_ERR_NOT_READY;
4429                 goto write_reg; /* Disable flow control */
4430         }
4431         /**
4432          * If link auto negotiation is enabled, flow control needs to
4433          * be configured according to it
4434          */
4435         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4436         case I40E_LINK_PAUSE_RXTX:
4437                 rxfc = 1;
4438                 txfc = 1;
4439                 hw->fc.current_mode = I40E_FC_FULL;
4440                 break;
4441         case I40E_AQ_LINK_PAUSE_RX:
4442                 rxfc = 1;
4443                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4444                 break;
4445         case I40E_AQ_LINK_PAUSE_TX:
4446                 txfc = 1;
4447                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4448                 break;
4449         default:
4450                 hw->fc.current_mode = I40E_FC_NONE;
4451                 break;
4452         }
4453
4454 write_reg:
4455         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4456                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4457         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4458         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4459         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4460         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4461
4462         return ret;
4463 }
4464
4465 /* PF setup */
4466 static int
4467 i40e_pf_setup(struct i40e_pf *pf)
4468 {
4469         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4470         struct i40e_filter_control_settings settings;
4471         struct i40e_vsi *vsi;
4472         int ret;
4473
4474         /* Clear all stats counters */
4475         pf->offset_loaded = FALSE;
4476         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4477         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4478
4479         ret = i40e_pf_get_switch_config(pf);
4480         if (ret != I40E_SUCCESS) {
4481                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4482                 return ret;
4483         }
4484         if (pf->flags & I40E_FLAG_FDIR) {
4485                 /* make queue allocated first, let FDIR use queue pair 0*/
4486                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4487                 if (ret != I40E_FDIR_QUEUE_ID) {
4488                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4489                                     " ret =%d", ret);
4490                         pf->flags &= ~I40E_FLAG_FDIR;
4491                 }
4492         }
4493         /*  main VSI setup */
4494         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4495         if (!vsi) {
4496                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4497                 return I40E_ERR_NOT_READY;
4498         }
4499         pf->main_vsi = vsi;
4500
4501         /* Configure filter control */
4502         memset(&settings, 0, sizeof(settings));
4503         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4504                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4505         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4506                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4507         else {
4508                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4509                                                 hw->func_caps.rss_table_size);
4510                 return I40E_ERR_PARAM;
4511         }
4512         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4513                         "size: %u\n", hw->func_caps.rss_table_size);
4514         pf->hash_lut_size = hw->func_caps.rss_table_size;
4515
4516         /* Enable ethtype and macvlan filters */
4517         settings.enable_ethtype = TRUE;
4518         settings.enable_macvlan = TRUE;
4519         ret = i40e_set_filter_control(hw, &settings);
4520         if (ret)
4521                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4522                                                                 ret);
4523
4524         /* Update flow control according to the auto negotiation */
4525         i40e_update_flow_control(hw);
4526
4527         return I40E_SUCCESS;
4528 }
4529
4530 int
4531 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4532 {
4533         uint32_t reg;
4534         uint16_t j;
4535
4536         /**
4537          * Set or clear TX Queue Disable flags,
4538          * which is required by hardware.
4539          */
4540         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4541         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4542
4543         /* Wait until the request is finished */
4544         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4545                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4546                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4547                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4548                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4549                                                         & 0x1))) {
4550                         break;
4551                 }
4552         }
4553         if (on) {
4554                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4555                         return I40E_SUCCESS; /* already on, skip next steps */
4556
4557                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4558                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4559         } else {
4560                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4561                         return I40E_SUCCESS; /* already off, skip next steps */
4562                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4563         }
4564         /* Write the register */
4565         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4566         /* Check the result */
4567         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4568                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4569                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4570                 if (on) {
4571                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4572                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4573                                 break;
4574                 } else {
4575                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4576                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4577                                 break;
4578                 }
4579         }
4580         /* Check if it is timeout */
4581         if (j >= I40E_CHK_Q_ENA_COUNT) {
4582                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4583                             (on ? "enable" : "disable"), q_idx);
4584                 return I40E_ERR_TIMEOUT;
4585         }
4586
4587         return I40E_SUCCESS;
4588 }
4589
4590 /* Swith on or off the tx queues */
4591 static int
4592 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4593 {
4594         struct rte_eth_dev_data *dev_data = pf->dev_data;
4595         struct i40e_tx_queue *txq;
4596         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4597         uint16_t i;
4598         int ret;
4599
4600         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4601                 txq = dev_data->tx_queues[i];
4602                 /* Don't operate the queue if not configured or
4603                  * if starting only per queue */
4604                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4605                         continue;
4606                 if (on)
4607                         ret = i40e_dev_tx_queue_start(dev, i);
4608                 else
4609                         ret = i40e_dev_tx_queue_stop(dev, i);
4610                 if ( ret != I40E_SUCCESS)
4611                         return ret;
4612         }
4613
4614         return I40E_SUCCESS;
4615 }
4616
4617 int
4618 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4619 {
4620         uint32_t reg;
4621         uint16_t j;
4622
4623         /* Wait until the request is finished */
4624         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4625                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4626                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4627                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4628                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4629                         break;
4630         }
4631
4632         if (on) {
4633                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4634                         return I40E_SUCCESS; /* Already on, skip next steps */
4635                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4636         } else {
4637                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4638                         return I40E_SUCCESS; /* Already off, skip next steps */
4639                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4640         }
4641
4642         /* Write the register */
4643         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4644         /* Check the result */
4645         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4646                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4647                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4648                 if (on) {
4649                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4650                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4651                                 break;
4652                 } else {
4653                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4654                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4655                                 break;
4656                 }
4657         }
4658
4659         /* Check if it is timeout */
4660         if (j >= I40E_CHK_Q_ENA_COUNT) {
4661                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4662                             (on ? "enable" : "disable"), q_idx);
4663                 return I40E_ERR_TIMEOUT;
4664         }
4665
4666         return I40E_SUCCESS;
4667 }
4668 /* Switch on or off the rx queues */
4669 static int
4670 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4671 {
4672         struct rte_eth_dev_data *dev_data = pf->dev_data;
4673         struct i40e_rx_queue *rxq;
4674         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4675         uint16_t i;
4676         int ret;
4677
4678         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4679                 rxq = dev_data->rx_queues[i];
4680                 /* Don't operate the queue if not configured or
4681                  * if starting only per queue */
4682                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4683                         continue;
4684                 if (on)
4685                         ret = i40e_dev_rx_queue_start(dev, i);
4686                 else
4687                         ret = i40e_dev_rx_queue_stop(dev, i);
4688                 if (ret != I40E_SUCCESS)
4689                         return ret;
4690         }
4691
4692         return I40E_SUCCESS;
4693 }
4694
4695 /* Switch on or off all the rx/tx queues */
4696 int
4697 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4698 {
4699         int ret;
4700
4701         if (on) {
4702                 /* enable rx queues before enabling tx queues */
4703                 ret = i40e_dev_switch_rx_queues(pf, on);
4704                 if (ret) {
4705                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4706                         return ret;
4707                 }
4708                 ret = i40e_dev_switch_tx_queues(pf, on);
4709         } else {
4710                 /* Stop tx queues before stopping rx queues */
4711                 ret = i40e_dev_switch_tx_queues(pf, on);
4712                 if (ret) {
4713                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4714                         return ret;
4715                 }
4716                 ret = i40e_dev_switch_rx_queues(pf, on);
4717         }
4718
4719         return ret;
4720 }
4721
4722 /* Initialize VSI for TX */
4723 static int
4724 i40e_dev_tx_init(struct i40e_pf *pf)
4725 {
4726         struct rte_eth_dev_data *data = pf->dev_data;
4727         uint16_t i;
4728         uint32_t ret = I40E_SUCCESS;
4729         struct i40e_tx_queue *txq;
4730
4731         for (i = 0; i < data->nb_tx_queues; i++) {
4732                 txq = data->tx_queues[i];
4733                 if (!txq || !txq->q_set)
4734                         continue;
4735                 ret = i40e_tx_queue_init(txq);
4736                 if (ret != I40E_SUCCESS)
4737                         break;
4738         }
4739         if (ret == I40E_SUCCESS)
4740                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4741                                      ->eth_dev);
4742
4743         return ret;
4744 }
4745
4746 /* Initialize VSI for RX */
4747 static int
4748 i40e_dev_rx_init(struct i40e_pf *pf)
4749 {
4750         struct rte_eth_dev_data *data = pf->dev_data;
4751         int ret = I40E_SUCCESS;
4752         uint16_t i;
4753         struct i40e_rx_queue *rxq;
4754
4755         i40e_pf_config_mq_rx(pf);
4756         for (i = 0; i < data->nb_rx_queues; i++) {
4757                 rxq = data->rx_queues[i];
4758                 if (!rxq || !rxq->q_set)
4759                         continue;
4760
4761                 ret = i40e_rx_queue_init(rxq);
4762                 if (ret != I40E_SUCCESS) {
4763                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4764                                     "initialization");
4765                         break;
4766                 }
4767         }
4768         if (ret == I40E_SUCCESS)
4769                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4770                                      ->eth_dev);
4771
4772         return ret;
4773 }
4774
4775 static int
4776 i40e_dev_rxtx_init(struct i40e_pf *pf)
4777 {
4778         int err;
4779
4780         err = i40e_dev_tx_init(pf);
4781         if (err) {
4782                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4783                 return err;
4784         }
4785         err = i40e_dev_rx_init(pf);
4786         if (err) {
4787                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4788                 return err;
4789         }
4790
4791         return err;
4792 }
4793
4794 static int
4795 i40e_vmdq_setup(struct rte_eth_dev *dev)
4796 {
4797         struct rte_eth_conf *conf = &dev->data->dev_conf;
4798         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4799         int i, err, conf_vsis, j, loop;
4800         struct i40e_vsi *vsi;
4801         struct i40e_vmdq_info *vmdq_info;
4802         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4803         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4804
4805         /*
4806          * Disable interrupt to avoid message from VF. Furthermore, it will
4807          * avoid race condition in VSI creation/destroy.
4808          */
4809         i40e_pf_disable_irq0(hw);
4810
4811         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4812                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4813                 return -ENOTSUP;
4814         }
4815
4816         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4817         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4818                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4819                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4820                         pf->max_nb_vmdq_vsi);
4821                 return -ENOTSUP;
4822         }
4823
4824         if (pf->vmdq != NULL) {
4825                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4826                 return 0;
4827         }
4828
4829         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4830                                 sizeof(*vmdq_info) * conf_vsis, 0);
4831
4832         if (pf->vmdq == NULL) {
4833                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4834                 return -ENOMEM;
4835         }
4836
4837         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4838
4839         /* Create VMDQ VSI */
4840         for (i = 0; i < conf_vsis; i++) {
4841                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4842                                 vmdq_conf->enable_loop_back);
4843                 if (vsi == NULL) {
4844                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4845                         err = -1;
4846                         goto err_vsi_setup;
4847                 }
4848                 vmdq_info = &pf->vmdq[i];
4849                 vmdq_info->pf = pf;
4850                 vmdq_info->vsi = vsi;
4851         }
4852         pf->nb_cfg_vmdq_vsi = conf_vsis;
4853
4854         /* Configure Vlan */
4855         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4856         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4857                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4858                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4859                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4860                                         vmdq_conf->pool_map[i].vlan_id, j);
4861
4862                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4863                                                 vmdq_conf->pool_map[i].vlan_id);
4864                                 if (err) {
4865                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4866                                         err = -1;
4867                                         goto err_vsi_setup;
4868                                 }
4869                         }
4870                 }
4871         }
4872
4873         i40e_pf_enable_irq0(hw);
4874
4875         return 0;
4876
4877 err_vsi_setup:
4878         for (i = 0; i < conf_vsis; i++)
4879                 if (pf->vmdq[i].vsi == NULL)
4880                         break;
4881                 else
4882                         i40e_vsi_release(pf->vmdq[i].vsi);
4883
4884         rte_free(pf->vmdq);
4885         pf->vmdq = NULL;
4886         i40e_pf_enable_irq0(hw);
4887         return err;
4888 }
4889
4890 static void
4891 i40e_stat_update_32(struct i40e_hw *hw,
4892                    uint32_t reg,
4893                    bool offset_loaded,
4894                    uint64_t *offset,
4895                    uint64_t *stat)
4896 {
4897         uint64_t new_data;
4898
4899         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4900         if (!offset_loaded)
4901                 *offset = new_data;
4902
4903         if (new_data >= *offset)
4904                 *stat = (uint64_t)(new_data - *offset);
4905         else
4906                 *stat = (uint64_t)((new_data +
4907                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4908 }
4909
4910 static void
4911 i40e_stat_update_48(struct i40e_hw *hw,
4912                    uint32_t hireg,
4913                    uint32_t loreg,
4914                    bool offset_loaded,
4915                    uint64_t *offset,
4916                    uint64_t *stat)
4917 {
4918         uint64_t new_data;
4919
4920         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4921         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4922                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4923
4924         if (!offset_loaded)
4925                 *offset = new_data;
4926
4927         if (new_data >= *offset)
4928                 *stat = new_data - *offset;
4929         else
4930                 *stat = (uint64_t)((new_data +
4931                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4932
4933         *stat &= I40E_48_BIT_MASK;
4934 }
4935
4936 /* Disable IRQ0 */
4937 void
4938 i40e_pf_disable_irq0(struct i40e_hw *hw)
4939 {
4940         /* Disable all interrupt types */
4941         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4942         I40E_WRITE_FLUSH(hw);
4943 }
4944
4945 /* Enable IRQ0 */
4946 void
4947 i40e_pf_enable_irq0(struct i40e_hw *hw)
4948 {
4949         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4950                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4951                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4952                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4953         I40E_WRITE_FLUSH(hw);
4954 }
4955
4956 static void
4957 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4958 {
4959         /* read pending request and disable first */
4960         i40e_pf_disable_irq0(hw);
4961         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4962         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4963                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4964
4965         if (no_queue)
4966                 /* Link no queues with irq0 */
4967                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4968                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4969 }
4970
4971 static void
4972 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4973 {
4974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4975         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4976         int i;
4977         uint16_t abs_vf_id;
4978         uint32_t index, offset, val;
4979
4980         if (!pf->vfs)
4981                 return;
4982         /**
4983          * Try to find which VF trigger a reset, use absolute VF id to access
4984          * since the reg is global register.
4985          */
4986         for (i = 0; i < pf->vf_num; i++) {
4987                 abs_vf_id = hw->func_caps.vf_base_id + i;
4988                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4989                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4990                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4991                 /* VFR event occured */
4992                 if (val & (0x1 << offset)) {
4993                         int ret;
4994
4995                         /* Clear the event first */
4996                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4997                                                         (0x1 << offset));
4998                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4999                         /**
5000                          * Only notify a VF reset event occured,
5001                          * don't trigger another SW reset
5002                          */
5003                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5004                         if (ret != I40E_SUCCESS)
5005                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5006                 }
5007         }
5008 }
5009
5010 static void
5011 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5012 {
5013         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014         struct i40e_arq_event_info info;
5015         uint16_t pending, opcode;
5016         int ret;
5017
5018         info.buf_len = I40E_AQ_BUF_SZ;
5019         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5020         if (!info.msg_buf) {
5021                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5022                 return;
5023         }
5024
5025         pending = 1;
5026         while (pending) {
5027                 ret = i40e_clean_arq_element(hw, &info, &pending);
5028
5029                 if (ret != I40E_SUCCESS) {
5030                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5031                                     "aq_err: %u", hw->aq.asq_last_status);
5032                         break;
5033                 }
5034                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5035
5036                 switch (opcode) {
5037                 case i40e_aqc_opc_send_msg_to_pf:
5038                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5039                         i40e_pf_host_handle_vf_msg(dev,
5040                                         rte_le_to_cpu_16(info.desc.retval),
5041                                         rte_le_to_cpu_32(info.desc.cookie_high),
5042                                         rte_le_to_cpu_32(info.desc.cookie_low),
5043                                         info.msg_buf,
5044                                         info.msg_len);
5045                         break;
5046                 default:
5047                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5048                                     opcode);
5049                         break;
5050                 }
5051         }
5052         rte_free(info.msg_buf);
5053 }
5054
5055 /*
5056  * Interrupt handler is registered as the alarm callback for handling LSC
5057  * interrupt in a definite of time, in order to wait the NIC into a stable
5058  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5059  * no need for link down interrupt.
5060  */
5061 static void
5062 i40e_dev_interrupt_delayed_handler(void *param)
5063 {
5064         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5066         uint32_t icr0;
5067
5068         /* read interrupt causes again */
5069         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5070
5071 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5072         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5073                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5074         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5075                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5076         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5077                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5078         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5079                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5080         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5081                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5082                                                                 "state\n");
5083         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5084                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5085         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5086                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5087 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5088
5089         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5090                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5091                 i40e_dev_handle_vfr_event(dev);
5092         }
5093         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5094                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5095                 i40e_dev_handle_aq_msg(dev);
5096         }
5097
5098         /* handle the link up interrupt in an alarm callback */
5099         i40e_dev_link_update(dev, 0);
5100         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5101
5102         i40e_pf_enable_irq0(hw);
5103         rte_intr_enable(&(dev->pci_dev->intr_handle));
5104 }
5105
5106 /**
5107  * Interrupt handler triggered by NIC  for handling
5108  * specific interrupt.
5109  *
5110  * @param handle
5111  *  Pointer to interrupt handle.
5112  * @param param
5113  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5114  *
5115  * @return
5116  *  void
5117  */
5118 static void
5119 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5120                            void *param)
5121 {
5122         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5124         uint32_t icr0;
5125
5126         /* Disable interrupt */
5127         i40e_pf_disable_irq0(hw);
5128
5129         /* read out interrupt causes */
5130         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5131
5132         /* No interrupt event indicated */
5133         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5134                 PMD_DRV_LOG(INFO, "No interrupt event");
5135                 goto done;
5136         }
5137 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5138         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5139                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5140         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5141                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5142         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5143                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5144         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5145                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5146         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5147                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5148         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5149                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5150         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5151                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5152 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5153
5154         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5155                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5156                 i40e_dev_handle_vfr_event(dev);
5157         }
5158         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5159                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5160                 i40e_dev_handle_aq_msg(dev);
5161         }
5162
5163         /* Link Status Change interrupt */
5164         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5165 #define I40E_US_PER_SECOND 1000000
5166                 struct rte_eth_link link;
5167
5168                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5169                 memset(&link, 0, sizeof(link));
5170                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5171                 i40e_dev_link_update(dev, 0);
5172
5173                 /*
5174                  * For link up interrupt, it needs to wait 1 second to let the
5175                  * hardware be a stable state. Otherwise several consecutive
5176                  * interrupts can be observed.
5177                  * For link down interrupt, no need to wait.
5178                  */
5179                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5180                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5181                         return;
5182                 else
5183                         _rte_eth_dev_callback_process(dev,
5184                                 RTE_ETH_EVENT_INTR_LSC);
5185         }
5186
5187 done:
5188         /* Enable interrupt */
5189         i40e_pf_enable_irq0(hw);
5190         rte_intr_enable(&(dev->pci_dev->intr_handle));
5191 }
5192
5193 static int
5194 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5195                          struct i40e_macvlan_filter *filter,
5196                          int total)
5197 {
5198         int ele_num, ele_buff_size;
5199         int num, actual_num, i;
5200         uint16_t flags;
5201         int ret = I40E_SUCCESS;
5202         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5203         struct i40e_aqc_add_macvlan_element_data *req_list;
5204
5205         if (filter == NULL  || total == 0)
5206                 return I40E_ERR_PARAM;
5207         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5208         ele_buff_size = hw->aq.asq_buf_size;
5209
5210         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5211         if (req_list == NULL) {
5212                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5213                 return I40E_ERR_NO_MEMORY;
5214         }
5215
5216         num = 0;
5217         do {
5218                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5219                 memset(req_list, 0, ele_buff_size);
5220
5221                 for (i = 0; i < actual_num; i++) {
5222                         (void)rte_memcpy(req_list[i].mac_addr,
5223                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5224                         req_list[i].vlan_tag =
5225                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5226
5227                         switch (filter[num + i].filter_type) {
5228                         case RTE_MAC_PERFECT_MATCH:
5229                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5230                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5231                                 break;
5232                         case RTE_MACVLAN_PERFECT_MATCH:
5233                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5234                                 break;
5235                         case RTE_MAC_HASH_MATCH:
5236                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5237                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5238                                 break;
5239                         case RTE_MACVLAN_HASH_MATCH:
5240                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5241                                 break;
5242                         default:
5243                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5244                                 ret = I40E_ERR_PARAM;
5245                                 goto DONE;
5246                         }
5247
5248                         req_list[i].queue_number = 0;
5249
5250                         req_list[i].flags = rte_cpu_to_le_16(flags);
5251                 }
5252
5253                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5254                                                 actual_num, NULL);
5255                 if (ret != I40E_SUCCESS) {
5256                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5257                         goto DONE;
5258                 }
5259                 num += actual_num;
5260         } while (num < total);
5261
5262 DONE:
5263         rte_free(req_list);
5264         return ret;
5265 }
5266
5267 static int
5268 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5269                             struct i40e_macvlan_filter *filter,
5270                             int total)
5271 {
5272         int ele_num, ele_buff_size;
5273         int num, actual_num, i;
5274         uint16_t flags;
5275         int ret = I40E_SUCCESS;
5276         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5277         struct i40e_aqc_remove_macvlan_element_data *req_list;
5278
5279         if (filter == NULL  || total == 0)
5280                 return I40E_ERR_PARAM;
5281
5282         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5283         ele_buff_size = hw->aq.asq_buf_size;
5284
5285         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5286         if (req_list == NULL) {
5287                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5288                 return I40E_ERR_NO_MEMORY;
5289         }
5290
5291         num = 0;
5292         do {
5293                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5294                 memset(req_list, 0, ele_buff_size);
5295
5296                 for (i = 0; i < actual_num; i++) {
5297                         (void)rte_memcpy(req_list[i].mac_addr,
5298                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5299                         req_list[i].vlan_tag =
5300                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5301
5302                         switch (filter[num + i].filter_type) {
5303                         case RTE_MAC_PERFECT_MATCH:
5304                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5305                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5306                                 break;
5307                         case RTE_MACVLAN_PERFECT_MATCH:
5308                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5309                                 break;
5310                         case RTE_MAC_HASH_MATCH:
5311                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5312                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5313                                 break;
5314                         case RTE_MACVLAN_HASH_MATCH:
5315                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5316                                 break;
5317                         default:
5318                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5319                                 ret = I40E_ERR_PARAM;
5320                                 goto DONE;
5321                         }
5322                         req_list[i].flags = rte_cpu_to_le_16(flags);
5323                 }
5324
5325                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5326                                                 actual_num, NULL);
5327                 if (ret != I40E_SUCCESS) {
5328                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5329                         goto DONE;
5330                 }
5331                 num += actual_num;
5332         } while (num < total);
5333
5334 DONE:
5335         rte_free(req_list);
5336         return ret;
5337 }
5338
5339 /* Find out specific MAC filter */
5340 static struct i40e_mac_filter *
5341 i40e_find_mac_filter(struct i40e_vsi *vsi,
5342                          struct ether_addr *macaddr)
5343 {
5344         struct i40e_mac_filter *f;
5345
5346         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5347                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5348                         return f;
5349         }
5350
5351         return NULL;
5352 }
5353
5354 static bool
5355 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5356                          uint16_t vlan_id)
5357 {
5358         uint32_t vid_idx, vid_bit;
5359
5360         if (vlan_id > ETH_VLAN_ID_MAX)
5361                 return 0;
5362
5363         vid_idx = I40E_VFTA_IDX(vlan_id);
5364         vid_bit = I40E_VFTA_BIT(vlan_id);
5365
5366         if (vsi->vfta[vid_idx] & vid_bit)
5367                 return 1;
5368         else
5369                 return 0;
5370 }
5371
5372 static void
5373 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5374                          uint16_t vlan_id, bool on)
5375 {
5376         uint32_t vid_idx, vid_bit;
5377
5378         if (vlan_id > ETH_VLAN_ID_MAX)
5379                 return;
5380
5381         vid_idx = I40E_VFTA_IDX(vlan_id);
5382         vid_bit = I40E_VFTA_BIT(vlan_id);
5383
5384         if (on)
5385                 vsi->vfta[vid_idx] |= vid_bit;
5386         else
5387                 vsi->vfta[vid_idx] &= ~vid_bit;
5388 }
5389
5390 /**
5391  * Find all vlan options for specific mac addr,
5392  * return with actual vlan found.
5393  */
5394 static inline int
5395 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5396                            struct i40e_macvlan_filter *mv_f,
5397                            int num, struct ether_addr *addr)
5398 {
5399         int i;
5400         uint32_t j, k;
5401
5402         /**
5403          * Not to use i40e_find_vlan_filter to decrease the loop time,
5404          * although the code looks complex.
5405           */
5406         if (num < vsi->vlan_num)
5407                 return I40E_ERR_PARAM;
5408
5409         i = 0;
5410         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5411                 if (vsi->vfta[j]) {
5412                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5413                                 if (vsi->vfta[j] & (1 << k)) {
5414                                         if (i > num - 1) {
5415                                                 PMD_DRV_LOG(ERR, "vlan number "
5416                                                             "not match");
5417                                                 return I40E_ERR_PARAM;
5418                                         }
5419                                         (void)rte_memcpy(&mv_f[i].macaddr,
5420                                                         addr, ETH_ADDR_LEN);
5421                                         mv_f[i].vlan_id =
5422                                                 j * I40E_UINT32_BIT_SIZE + k;
5423                                         i++;
5424                                 }
5425                         }
5426                 }
5427         }
5428         return I40E_SUCCESS;
5429 }
5430
5431 static inline int
5432 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5433                            struct i40e_macvlan_filter *mv_f,
5434                            int num,
5435                            uint16_t vlan)
5436 {
5437         int i = 0;
5438         struct i40e_mac_filter *f;
5439
5440         if (num < vsi->mac_num)
5441                 return I40E_ERR_PARAM;
5442
5443         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5444                 if (i > num - 1) {
5445                         PMD_DRV_LOG(ERR, "buffer number not match");
5446                         return I40E_ERR_PARAM;
5447                 }
5448                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5449                                 ETH_ADDR_LEN);
5450                 mv_f[i].vlan_id = vlan;
5451                 mv_f[i].filter_type = f->mac_info.filter_type;
5452                 i++;
5453         }
5454
5455         return I40E_SUCCESS;
5456 }
5457
5458 static int
5459 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5460 {
5461         int i, num;
5462         struct i40e_mac_filter *f;
5463         struct i40e_macvlan_filter *mv_f;
5464         int ret = I40E_SUCCESS;
5465
5466         if (vsi == NULL || vsi->mac_num == 0)
5467                 return I40E_ERR_PARAM;
5468
5469         /* Case that no vlan is set */
5470         if (vsi->vlan_num == 0)
5471                 num = vsi->mac_num;
5472         else
5473                 num = vsi->mac_num * vsi->vlan_num;
5474
5475         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5476         if (mv_f == NULL) {
5477                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5478                 return I40E_ERR_NO_MEMORY;
5479         }
5480
5481         i = 0;
5482         if (vsi->vlan_num == 0) {
5483                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5484                         (void)rte_memcpy(&mv_f[i].macaddr,
5485                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5486                         mv_f[i].vlan_id = 0;
5487                         i++;
5488                 }
5489         } else {
5490                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5491                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5492                                         vsi->vlan_num, &f->mac_info.mac_addr);
5493                         if (ret != I40E_SUCCESS)
5494                                 goto DONE;
5495                         i += vsi->vlan_num;
5496                 }
5497         }
5498
5499         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5500 DONE:
5501         rte_free(mv_f);
5502
5503         return ret;
5504 }
5505
5506 int
5507 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5508 {
5509         struct i40e_macvlan_filter *mv_f;
5510         int mac_num;
5511         int ret = I40E_SUCCESS;
5512
5513         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5514                 return I40E_ERR_PARAM;
5515
5516         /* If it's already set, just return */
5517         if (i40e_find_vlan_filter(vsi,vlan))
5518                 return I40E_SUCCESS;
5519
5520         mac_num = vsi->mac_num;
5521
5522         if (mac_num == 0) {
5523                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5524                 return I40E_ERR_PARAM;
5525         }
5526
5527         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5528
5529         if (mv_f == NULL) {
5530                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5531                 return I40E_ERR_NO_MEMORY;
5532         }
5533
5534         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5535
5536         if (ret != I40E_SUCCESS)
5537                 goto DONE;
5538
5539         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5540
5541         if (ret != I40E_SUCCESS)
5542                 goto DONE;
5543
5544         i40e_set_vlan_filter(vsi, vlan, 1);
5545
5546         vsi->vlan_num++;
5547         ret = I40E_SUCCESS;
5548 DONE:
5549         rte_free(mv_f);
5550         return ret;
5551 }
5552
5553 int
5554 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5555 {
5556         struct i40e_macvlan_filter *mv_f;
5557         int mac_num;
5558         int ret = I40E_SUCCESS;
5559
5560         /**
5561          * Vlan 0 is the generic filter for untagged packets
5562          * and can't be removed.
5563          */
5564         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5565                 return I40E_ERR_PARAM;
5566
5567         /* If can't find it, just return */
5568         if (!i40e_find_vlan_filter(vsi, vlan))
5569                 return I40E_ERR_PARAM;
5570
5571         mac_num = vsi->mac_num;
5572
5573         if (mac_num == 0) {
5574                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5575                 return I40E_ERR_PARAM;
5576         }
5577
5578         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5579
5580         if (mv_f == NULL) {
5581                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5582                 return I40E_ERR_NO_MEMORY;
5583         }
5584
5585         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5586
5587         if (ret != I40E_SUCCESS)
5588                 goto DONE;
5589
5590         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5591
5592         if (ret != I40E_SUCCESS)
5593                 goto DONE;
5594
5595         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5596         if (vsi->vlan_num == 1) {
5597                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5598                 if (ret != I40E_SUCCESS)
5599                         goto DONE;
5600
5601                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5602                 if (ret != I40E_SUCCESS)
5603                         goto DONE;
5604         }
5605
5606         i40e_set_vlan_filter(vsi, vlan, 0);
5607
5608         vsi->vlan_num--;
5609         ret = I40E_SUCCESS;
5610 DONE:
5611         rte_free(mv_f);
5612         return ret;
5613 }
5614
5615 int
5616 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5617 {
5618         struct i40e_mac_filter *f;
5619         struct i40e_macvlan_filter *mv_f;
5620         int i, vlan_num = 0;
5621         int ret = I40E_SUCCESS;
5622
5623         /* If it's add and we've config it, return */
5624         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5625         if (f != NULL)
5626                 return I40E_SUCCESS;
5627         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5628                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5629
5630                 /**
5631                  * If vlan_num is 0, that's the first time to add mac,
5632                  * set mask for vlan_id 0.
5633                  */
5634                 if (vsi->vlan_num == 0) {
5635                         i40e_set_vlan_filter(vsi, 0, 1);
5636                         vsi->vlan_num = 1;
5637                 }
5638                 vlan_num = vsi->vlan_num;
5639         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5640                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5641                 vlan_num = 1;
5642
5643         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5644         if (mv_f == NULL) {
5645                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5646                 return I40E_ERR_NO_MEMORY;
5647         }
5648
5649         for (i = 0; i < vlan_num; i++) {
5650                 mv_f[i].filter_type = mac_filter->filter_type;
5651                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5652                                 ETH_ADDR_LEN);
5653         }
5654
5655         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5656                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5657                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5658                                         &mac_filter->mac_addr);
5659                 if (ret != I40E_SUCCESS)
5660                         goto DONE;
5661         }
5662
5663         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5664         if (ret != I40E_SUCCESS)
5665                 goto DONE;
5666
5667         /* Add the mac addr into mac list */
5668         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5669         if (f == NULL) {
5670                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5671                 ret = I40E_ERR_NO_MEMORY;
5672                 goto DONE;
5673         }
5674         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5675                         ETH_ADDR_LEN);
5676         f->mac_info.filter_type = mac_filter->filter_type;
5677         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5678         vsi->mac_num++;
5679
5680         ret = I40E_SUCCESS;
5681 DONE:
5682         rte_free(mv_f);
5683
5684         return ret;
5685 }
5686
5687 int
5688 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5689 {
5690         struct i40e_mac_filter *f;
5691         struct i40e_macvlan_filter *mv_f;
5692         int i, vlan_num;
5693         enum rte_mac_filter_type filter_type;
5694         int ret = I40E_SUCCESS;
5695
5696         /* Can't find it, return an error */
5697         f = i40e_find_mac_filter(vsi, addr);
5698         if (f == NULL)
5699                 return I40E_ERR_PARAM;
5700
5701         vlan_num = vsi->vlan_num;
5702         filter_type = f->mac_info.filter_type;
5703         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5704                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5705                 if (vlan_num == 0) {
5706                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5707                         return I40E_ERR_PARAM;
5708                 }
5709         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5710                         filter_type == RTE_MAC_HASH_MATCH)
5711                 vlan_num = 1;
5712
5713         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5714         if (mv_f == NULL) {
5715                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5716                 return I40E_ERR_NO_MEMORY;
5717         }
5718
5719         for (i = 0; i < vlan_num; i++) {
5720                 mv_f[i].filter_type = filter_type;
5721                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5722                                 ETH_ADDR_LEN);
5723         }
5724         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5725                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5726                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5727                 if (ret != I40E_SUCCESS)
5728                         goto DONE;
5729         }
5730
5731         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5732         if (ret != I40E_SUCCESS)
5733                 goto DONE;
5734
5735         /* Remove the mac addr into mac list */
5736         TAILQ_REMOVE(&vsi->mac_list, f, next);
5737         rte_free(f);
5738         vsi->mac_num--;
5739
5740         ret = I40E_SUCCESS;
5741 DONE:
5742         rte_free(mv_f);
5743         return ret;
5744 }
5745
5746 /* Configure hash enable flags for RSS */
5747 uint64_t
5748 i40e_config_hena(uint64_t flags)
5749 {
5750         uint64_t hena = 0;
5751
5752         if (!flags)
5753                 return hena;
5754
5755         if (flags & ETH_RSS_FRAG_IPV4)
5756                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5757         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5758                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5759         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5760                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5761         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5762                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5763         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5764                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5765         if (flags & ETH_RSS_FRAG_IPV6)
5766                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5767         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5768                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5769         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5770                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5771         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5772                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5773         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5774                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5775         if (flags & ETH_RSS_L2_PAYLOAD)
5776                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5777
5778         return hena;
5779 }
5780
5781 /* Parse the hash enable flags */
5782 uint64_t
5783 i40e_parse_hena(uint64_t flags)
5784 {
5785         uint64_t rss_hf = 0;
5786
5787         if (!flags)
5788                 return rss_hf;
5789         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5790                 rss_hf |= ETH_RSS_FRAG_IPV4;
5791         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5792                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5793         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5794                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5795         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5796                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5797         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5798                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5799         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5800                 rss_hf |= ETH_RSS_FRAG_IPV6;
5801         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5802                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5803         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5804                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5805         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5806                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5807         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5808                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5809         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5810                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5811
5812         return rss_hf;
5813 }
5814
5815 /* Disable RSS */
5816 static void
5817 i40e_pf_disable_rss(struct i40e_pf *pf)
5818 {
5819         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5820         uint64_t hena;
5821
5822         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5823         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5824         hena &= ~I40E_RSS_HENA_ALL;
5825         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5826         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5827         I40E_WRITE_FLUSH(hw);
5828 }
5829
5830 static int
5831 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5832 {
5833         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5834         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5835         int ret = 0;
5836
5837         if (!key || key_len == 0) {
5838                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5839                 return 0;
5840         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5841                 sizeof(uint32_t)) {
5842                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5843                 return -EINVAL;
5844         }
5845
5846         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5847                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5848                         (struct i40e_aqc_get_set_rss_key_data *)key;
5849
5850                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5851                 if (ret)
5852                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5853                                      "via AQ");
5854         } else {
5855                 uint32_t *hash_key = (uint32_t *)key;
5856                 uint16_t i;
5857
5858                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5859                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5860                 I40E_WRITE_FLUSH(hw);
5861         }
5862
5863         return ret;
5864 }
5865
5866 static int
5867 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5868 {
5869         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5870         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5871         int ret;
5872
5873         if (!key || !key_len)
5874                 return -EINVAL;
5875
5876         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5877                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5878                         (struct i40e_aqc_get_set_rss_key_data *)key);
5879                 if (ret) {
5880                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5881                         return ret;
5882                 }
5883         } else {
5884                 uint32_t *key_dw = (uint32_t *)key;
5885                 uint16_t i;
5886
5887                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5888                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5889         }
5890         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5891
5892         return 0;
5893 }
5894
5895 static int
5896 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5897 {
5898         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5899         uint64_t rss_hf;
5900         uint64_t hena;
5901         int ret;
5902
5903         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5904                                rss_conf->rss_key_len);
5905         if (ret)
5906                 return ret;
5907
5908         rss_hf = rss_conf->rss_hf;
5909         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5910         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5911         hena &= ~I40E_RSS_HENA_ALL;
5912         hena |= i40e_config_hena(rss_hf);
5913         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5914         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5915         I40E_WRITE_FLUSH(hw);
5916
5917         return 0;
5918 }
5919
5920 static int
5921 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5922                          struct rte_eth_rss_conf *rss_conf)
5923 {
5924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5926         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5927         uint64_t hena;
5928
5929         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5930         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5931         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5932                 if (rss_hf != 0) /* Enable RSS */
5933                         return -EINVAL;
5934                 return 0; /* Nothing to do */
5935         }
5936         /* RSS enabled */
5937         if (rss_hf == 0) /* Disable RSS */
5938                 return -EINVAL;
5939
5940         return i40e_hw_rss_hash_set(pf, rss_conf);
5941 }
5942
5943 static int
5944 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5945                            struct rte_eth_rss_conf *rss_conf)
5946 {
5947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5949         uint64_t hena;
5950
5951         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5952                          &rss_conf->rss_key_len);
5953
5954         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5955         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5956         rss_conf->rss_hf = i40e_parse_hena(hena);
5957
5958         return 0;
5959 }
5960
5961 static int
5962 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5963 {
5964         switch (filter_type) {
5965         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5966                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5967                 break;
5968         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5969                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5970                 break;
5971         case RTE_TUNNEL_FILTER_IMAC_TENID:
5972                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5973                 break;
5974         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5975                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5976                 break;
5977         case ETH_TUNNEL_FILTER_IMAC:
5978                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5979                 break;
5980         case ETH_TUNNEL_FILTER_OIP:
5981                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
5982                 break;
5983         case ETH_TUNNEL_FILTER_IIP:
5984                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
5985                 break;
5986         default:
5987                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5988                 return -EINVAL;
5989         }
5990
5991         return 0;
5992 }
5993
5994 static int
5995 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5996                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5997                         uint8_t add)
5998 {
5999         uint16_t ip_type;
6000         uint8_t i, tun_type = 0;
6001         /* internal varialbe to convert ipv6 byte order */
6002         uint32_t convert_ipv6[4];
6003         int val, ret = 0;
6004         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6005         struct i40e_vsi *vsi = pf->main_vsi;
6006         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6007         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6008
6009         cld_filter = rte_zmalloc("tunnel_filter",
6010                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6011                 0);
6012
6013         if (NULL == cld_filter) {
6014                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6015                 return -EINVAL;
6016         }
6017         pfilter = cld_filter;
6018
6019         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6020         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6021
6022         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6023         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6024                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6025                 rte_memcpy(&pfilter->ipaddr.v4.data,
6026                                 &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
6027                                 sizeof(pfilter->ipaddr.v4.data));
6028         } else {
6029                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6030                 for (i = 0; i < 4; i++) {
6031                         convert_ipv6[i] =
6032                         rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
6033                 }
6034                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6035                                 sizeof(pfilter->ipaddr.v6.data));
6036         }
6037
6038         /* check tunneled type */
6039         switch (tunnel_filter->tunnel_type) {
6040         case RTE_TUNNEL_TYPE_VXLAN:
6041                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6042                 break;
6043         case RTE_TUNNEL_TYPE_NVGRE:
6044                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6045                 break;
6046         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6047                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6048                 break;
6049         default:
6050                 /* Other tunnel types is not supported. */
6051                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6052                 rte_free(cld_filter);
6053                 return -EINVAL;
6054         }
6055
6056         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6057                                                 &pfilter->flags);
6058         if (val < 0) {
6059                 rte_free(cld_filter);
6060                 return -EINVAL;
6061         }
6062
6063         pfilter->flags |= rte_cpu_to_le_16(
6064                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6065                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6066         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6067         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6068
6069         if (add)
6070                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6071         else
6072                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6073                                                 cld_filter, 1);
6074
6075         rte_free(cld_filter);
6076         return ret;
6077 }
6078
6079 static int
6080 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6081 {
6082         uint8_t i;
6083
6084         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6085                 if (pf->vxlan_ports[i] == port)
6086                         return i;
6087         }
6088
6089         return -1;
6090 }
6091
6092 static int
6093 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6094 {
6095         int  idx, ret;
6096         uint8_t filter_idx;
6097         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6098
6099         idx = i40e_get_vxlan_port_idx(pf, port);
6100
6101         /* Check if port already exists */
6102         if (idx >= 0) {
6103                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6104                 return -EINVAL;
6105         }
6106
6107         /* Now check if there is space to add the new port */
6108         idx = i40e_get_vxlan_port_idx(pf, 0);
6109         if (idx < 0) {
6110                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6111                         "not adding port %d", port);
6112                 return -ENOSPC;
6113         }
6114
6115         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6116                                         &filter_idx, NULL);
6117         if (ret < 0) {
6118                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6119                 return -1;
6120         }
6121
6122         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6123                          port,  filter_idx);
6124
6125         /* New port: add it and mark its index in the bitmap */
6126         pf->vxlan_ports[idx] = port;
6127         pf->vxlan_bitmap |= (1 << idx);
6128
6129         if (!(pf->flags & I40E_FLAG_VXLAN))
6130                 pf->flags |= I40E_FLAG_VXLAN;
6131
6132         return 0;
6133 }
6134
6135 static int
6136 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6137 {
6138         int idx;
6139         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6140
6141         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6142                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6143                 return -EINVAL;
6144         }
6145
6146         idx = i40e_get_vxlan_port_idx(pf, port);
6147
6148         if (idx < 0) {
6149                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6150                 return -EINVAL;
6151         }
6152
6153         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6154                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6155                 return -1;
6156         }
6157
6158         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6159                         port, idx);
6160
6161         pf->vxlan_ports[idx] = 0;
6162         pf->vxlan_bitmap &= ~(1 << idx);
6163
6164         if (!pf->vxlan_bitmap)
6165                 pf->flags &= ~I40E_FLAG_VXLAN;
6166
6167         return 0;
6168 }
6169
6170 /* Add UDP tunneling port */
6171 static int
6172 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6173                              struct rte_eth_udp_tunnel *udp_tunnel)
6174 {
6175         int ret = 0;
6176         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6177
6178         if (udp_tunnel == NULL)
6179                 return -EINVAL;
6180
6181         switch (udp_tunnel->prot_type) {
6182         case RTE_TUNNEL_TYPE_VXLAN:
6183                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6184                 break;
6185
6186         case RTE_TUNNEL_TYPE_GENEVE:
6187         case RTE_TUNNEL_TYPE_TEREDO:
6188                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6189                 ret = -1;
6190                 break;
6191
6192         default:
6193                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6194                 ret = -1;
6195                 break;
6196         }
6197
6198         return ret;
6199 }
6200
6201 /* Remove UDP tunneling port */
6202 static int
6203 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6204                              struct rte_eth_udp_tunnel *udp_tunnel)
6205 {
6206         int ret = 0;
6207         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6208
6209         if (udp_tunnel == NULL)
6210                 return -EINVAL;
6211
6212         switch (udp_tunnel->prot_type) {
6213         case RTE_TUNNEL_TYPE_VXLAN:
6214                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6215                 break;
6216         case RTE_TUNNEL_TYPE_GENEVE:
6217         case RTE_TUNNEL_TYPE_TEREDO:
6218                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6219                 ret = -1;
6220                 break;
6221         default:
6222                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6223                 ret = -1;
6224                 break;
6225         }
6226
6227         return ret;
6228 }
6229
6230 /* Calculate the maximum number of contiguous PF queues that are configured */
6231 static int
6232 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6233 {
6234         struct rte_eth_dev_data *data = pf->dev_data;
6235         int i, num;
6236         struct i40e_rx_queue *rxq;
6237
6238         num = 0;
6239         for (i = 0; i < pf->lan_nb_qps; i++) {
6240                 rxq = data->rx_queues[i];
6241                 if (rxq && rxq->q_set)
6242                         num++;
6243                 else
6244                         break;
6245         }
6246
6247         return num;
6248 }
6249
6250 /* Configure RSS */
6251 static int
6252 i40e_pf_config_rss(struct i40e_pf *pf)
6253 {
6254         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6255         struct rte_eth_rss_conf rss_conf;
6256         uint32_t i, lut = 0;
6257         uint16_t j, num;
6258
6259         /*
6260          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6261          * It's necessary to calulate the actual PF queues that are configured.
6262          */
6263         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6264                 num = i40e_pf_calc_configured_queues_num(pf);
6265         else
6266                 num = pf->dev_data->nb_rx_queues;
6267
6268         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6269         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6270                         num);
6271
6272         if (num == 0) {
6273                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6274                 return -ENOTSUP;
6275         }
6276
6277         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6278                 if (j == num)
6279                         j = 0;
6280                 lut = (lut << 8) | (j & ((0x1 <<
6281                         hw->func_caps.rss_table_entry_width) - 1));
6282                 if ((i & 3) == 3)
6283                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6284         }
6285
6286         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6287         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6288                 i40e_pf_disable_rss(pf);
6289                 return 0;
6290         }
6291         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6292                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6293                 /* Random default keys */
6294                 static uint32_t rss_key_default[] = {0x6b793944,
6295                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6296                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6297                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6298
6299                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6300                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6301                                                         sizeof(uint32_t);
6302         }
6303
6304         return i40e_hw_rss_hash_set(pf, &rss_conf);
6305 }
6306
6307 static int
6308 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6309                                struct rte_eth_tunnel_filter_conf *filter)
6310 {
6311         if (pf == NULL || filter == NULL) {
6312                 PMD_DRV_LOG(ERR, "Invalid parameter");
6313                 return -EINVAL;
6314         }
6315
6316         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6317                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6318                 return -EINVAL;
6319         }
6320
6321         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6322                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6323                 return -EINVAL;
6324         }
6325
6326         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6327                 (is_zero_ether_addr(&filter->outer_mac))) {
6328                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6329                 return -EINVAL;
6330         }
6331
6332         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6333                 (is_zero_ether_addr(&filter->inner_mac))) {
6334                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6335                 return -EINVAL;
6336         }
6337
6338         return 0;
6339 }
6340
6341 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6342 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6343 static int
6344 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6345 {
6346         uint32_t val, reg;
6347         int ret = -EINVAL;
6348
6349         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6350         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6351
6352         if (len == 3) {
6353                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6354         } else if (len == 4) {
6355                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6356         } else {
6357                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6358                 return ret;
6359         }
6360
6361         if (reg != val) {
6362                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6363                                                    reg, NULL);
6364                 if (ret != 0)
6365                         return ret;
6366         } else {
6367                 ret = 0;
6368         }
6369         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6370                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6371
6372         return ret;
6373 }
6374
6375 static int
6376 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6377 {
6378         int ret = -EINVAL;
6379
6380         if (!hw || !cfg)
6381                 return -EINVAL;
6382
6383         switch (cfg->cfg_type) {
6384         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6385                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6386                 break;
6387         default:
6388                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6389                 break;
6390         }
6391
6392         return ret;
6393 }
6394
6395 static int
6396 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6397                                enum rte_filter_op filter_op,
6398                                void *arg)
6399 {
6400         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6401         int ret = I40E_ERR_PARAM;
6402
6403         switch (filter_op) {
6404         case RTE_ETH_FILTER_SET:
6405                 ret = i40e_dev_global_config_set(hw,
6406                         (struct rte_eth_global_cfg *)arg);
6407                 break;
6408         default:
6409                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6410                 break;
6411         }
6412
6413         return ret;
6414 }
6415
6416 static int
6417 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6418                           enum rte_filter_op filter_op,
6419                           void *arg)
6420 {
6421         struct rte_eth_tunnel_filter_conf *filter;
6422         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6423         int ret = I40E_SUCCESS;
6424
6425         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6426
6427         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6428                 return I40E_ERR_PARAM;
6429
6430         switch (filter_op) {
6431         case RTE_ETH_FILTER_NOP:
6432                 if (!(pf->flags & I40E_FLAG_VXLAN))
6433                         ret = I40E_NOT_SUPPORTED;
6434                 break;
6435         case RTE_ETH_FILTER_ADD:
6436                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6437                 break;
6438         case RTE_ETH_FILTER_DELETE:
6439                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6440                 break;
6441         default:
6442                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6443                 ret = I40E_ERR_PARAM;
6444                 break;
6445         }
6446
6447         return ret;
6448 }
6449
6450 static int
6451 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6452 {
6453         int ret = 0;
6454         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6455
6456         /* RSS setup */
6457         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6458                 ret = i40e_pf_config_rss(pf);
6459         else
6460                 i40e_pf_disable_rss(pf);
6461
6462         return ret;
6463 }
6464
6465 /* Get the symmetric hash enable configurations per port */
6466 static void
6467 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6468 {
6469         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6470
6471         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6472 }
6473
6474 /* Set the symmetric hash enable configurations per port */
6475 static void
6476 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6477 {
6478         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6479
6480         if (enable > 0) {
6481                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6482                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6483                                                         "been enabled");
6484                         return;
6485                 }
6486                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6487         } else {
6488                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6489                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6490                                                         "been disabled");
6491                         return;
6492                 }
6493                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6494         }
6495         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6496         I40E_WRITE_FLUSH(hw);
6497 }
6498
6499 /*
6500  * Get global configurations of hash function type and symmetric hash enable
6501  * per flow type (pctype). Note that global configuration means it affects all
6502  * the ports on the same NIC.
6503  */
6504 static int
6505 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6506                                    struct rte_eth_hash_global_conf *g_cfg)
6507 {
6508         uint32_t reg, mask = I40E_FLOW_TYPES;
6509         uint16_t i;
6510         enum i40e_filter_pctype pctype;
6511
6512         memset(g_cfg, 0, sizeof(*g_cfg));
6513         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6514         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6515                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6516         else
6517                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6518         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6519                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6520
6521         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6522                 if (!(mask & (1UL << i)))
6523                         continue;
6524                 mask &= ~(1UL << i);
6525                 /* Bit set indicats the coresponding flow type is supported */
6526                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6527                 pctype = i40e_flowtype_to_pctype(i);
6528                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6529                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6530                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6531         }
6532
6533         return 0;
6534 }
6535
6536 static int
6537 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6538 {
6539         uint32_t i;
6540         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6541
6542         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6543                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6544                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6545                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6546                                                 g_cfg->hash_func);
6547                 return -EINVAL;
6548         }
6549
6550         /*
6551          * As i40e supports less than 32 flow types, only first 32 bits need to
6552          * be checked.
6553          */
6554         mask0 = g_cfg->valid_bit_mask[0];
6555         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6556                 if (i == 0) {
6557                         /* Check if any unsupported flow type configured */
6558                         if ((mask0 | i40e_mask) ^ i40e_mask)
6559                                 goto mask_err;
6560                 } else {
6561                         if (g_cfg->valid_bit_mask[i])
6562                                 goto mask_err;
6563                 }
6564         }
6565
6566         return 0;
6567
6568 mask_err:
6569         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6570
6571         return -EINVAL;
6572 }
6573
6574 /*
6575  * Set global configurations of hash function type and symmetric hash enable
6576  * per flow type (pctype). Note any modifying global configuration will affect
6577  * all the ports on the same NIC.
6578  */
6579 static int
6580 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6581                                    struct rte_eth_hash_global_conf *g_cfg)
6582 {
6583         int ret;
6584         uint16_t i;
6585         uint32_t reg;
6586         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6587         enum i40e_filter_pctype pctype;
6588
6589         /* Check the input parameters */
6590         ret = i40e_hash_global_config_check(g_cfg);
6591         if (ret < 0)
6592                 return ret;
6593
6594         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6595                 if (!(mask0 & (1UL << i)))
6596                         continue;
6597                 mask0 &= ~(1UL << i);
6598                 pctype = i40e_flowtype_to_pctype(i);
6599                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6600                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6601                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6602         }
6603
6604         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6605         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6606                 /* Toeplitz */
6607                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6608                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6609                                                                 "Toeplitz");
6610                         goto out;
6611                 }
6612                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6613         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6614                 /* Simple XOR */
6615                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6616                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6617                                                         "Simple XOR");
6618                         goto out;
6619                 }
6620                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6621         } else
6622                 /* Use the default, and keep it as it is */
6623                 goto out;
6624
6625         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6626
6627 out:
6628         I40E_WRITE_FLUSH(hw);
6629
6630         return 0;
6631 }
6632
6633 /**
6634  * Valid input sets for hash and flow director filters per PCTYPE
6635  */
6636 static uint64_t
6637 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6638                 enum rte_filter_type filter)
6639 {
6640         uint64_t valid;
6641
6642         static const uint64_t valid_hash_inset_table[] = {
6643                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6644                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6645                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6646                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6647                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6648                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6649                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6650                         I40E_INSET_FLEX_PAYLOAD,
6651                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6652                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6653                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6654                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6655                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6656                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6657                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6658                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6659                         I40E_INSET_FLEX_PAYLOAD,
6660                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6661                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6662                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6663                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6664                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6665                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6666                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6667                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6668                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6669                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6670                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6671                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6672                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6673                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6674                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6675                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6676                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6677                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6678                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6679                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6680                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6681                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6682                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6683                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6684                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6685                         I40E_INSET_FLEX_PAYLOAD,
6686                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6687                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6688                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6689                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6690                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6691                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6692                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6693                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6694                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6695                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6696                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6697                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6698                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6699                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6700                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6701                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6702                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6703                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6704                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6705                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6706                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6707                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6708                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6709                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6710                         I40E_INSET_FLEX_PAYLOAD,
6711                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6712                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6713                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6714                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6715                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6716                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6717                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6718                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6719                         I40E_INSET_FLEX_PAYLOAD,
6720                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6721                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6722                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6723                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6724                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6725                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6726                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6727                         I40E_INSET_FLEX_PAYLOAD,
6728                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6729                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6730                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6731                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6732                         I40E_INSET_FLEX_PAYLOAD,
6733         };
6734
6735         /**
6736          * Flow director supports only fields defined in
6737          * union rte_eth_fdir_flow.
6738          */
6739         static const uint64_t valid_fdir_inset_table[] = {
6740                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6741                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6742                 I40E_INSET_FLEX_PAYLOAD,
6743                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6744                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6745                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6746                 I40E_INSET_FLEX_PAYLOAD,
6747                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6748                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6749                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6750                 I40E_INSET_FLEX_PAYLOAD,
6751                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6752                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6753                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6754                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6755                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6756                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6757                 I40E_INSET_FLEX_PAYLOAD,
6758                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6759                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6760                 I40E_INSET_FLEX_PAYLOAD,
6761                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6762                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6763                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6764                 I40E_INSET_FLEX_PAYLOAD,
6765                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6766                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6767                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6768                 I40E_INSET_FLEX_PAYLOAD,
6769                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6770                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6771                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6772                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6773                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6774                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6775                 I40E_INSET_FLEX_PAYLOAD,
6776                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6777                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6778         };
6779
6780         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6781                 return 0;
6782         if (filter == RTE_ETH_FILTER_HASH)
6783                 valid = valid_hash_inset_table[pctype];
6784         else
6785                 valid = valid_fdir_inset_table[pctype];
6786
6787         return valid;
6788 }
6789
6790 /**
6791  * Validate if the input set is allowed for a specific PCTYPE
6792  */
6793 static int
6794 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6795                 enum rte_filter_type filter, uint64_t inset)
6796 {
6797         uint64_t valid;
6798
6799         valid = i40e_get_valid_input_set(pctype, filter);
6800         if (inset & (~valid))
6801                 return -EINVAL;
6802
6803         return 0;
6804 }
6805
6806 /* default input set fields combination per pctype */
6807 static uint64_t
6808 i40e_get_default_input_set(uint16_t pctype)
6809 {
6810         static const uint64_t default_inset_table[] = {
6811                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6812                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6813                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6814                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6815                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6816                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6817                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6818                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6819                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6820                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6821                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6822                         I40E_INSET_SCTP_VT,
6823                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6824                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6825                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6826                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6827                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6828                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6829                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6830                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6831                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6832                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6833                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6834                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6835                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6836                         I40E_INSET_SCTP_VT,
6837                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6838                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6839                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6840                         I40E_INSET_LAST_ETHER_TYPE,
6841         };
6842
6843         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6844                 return 0;
6845
6846         return default_inset_table[pctype];
6847 }
6848
6849 /**
6850  * Parse the input set from index to logical bit masks
6851  */
6852 static int
6853 i40e_parse_input_set(uint64_t *inset,
6854                      enum i40e_filter_pctype pctype,
6855                      enum rte_eth_input_set_field *field,
6856                      uint16_t size)
6857 {
6858         uint16_t i, j;
6859         int ret = -EINVAL;
6860
6861         static const struct {
6862                 enum rte_eth_input_set_field field;
6863                 uint64_t inset;
6864         } inset_convert_table[] = {
6865                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6866                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6867                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6868                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6869                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6870                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6871                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6872                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6873                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6874                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6875                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6876                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6877                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6878                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6879                         I40E_INSET_IPV6_NEXT_HDR},
6880                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6881                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6882                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6883                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6884                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6885                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6886                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6887                         I40E_INSET_SCTP_VT},
6888                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6889                         I40E_INSET_TUNNEL_DMAC},
6890                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6891                         I40E_INSET_VLAN_TUNNEL},
6892                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6893                         I40E_INSET_TUNNEL_ID},
6894                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6895                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6896                         I40E_INSET_FLEX_PAYLOAD_W1},
6897                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6898                         I40E_INSET_FLEX_PAYLOAD_W2},
6899                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6900                         I40E_INSET_FLEX_PAYLOAD_W3},
6901                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6902                         I40E_INSET_FLEX_PAYLOAD_W4},
6903                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6904                         I40E_INSET_FLEX_PAYLOAD_W5},
6905                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6906                         I40E_INSET_FLEX_PAYLOAD_W6},
6907                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6908                         I40E_INSET_FLEX_PAYLOAD_W7},
6909                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6910                         I40E_INSET_FLEX_PAYLOAD_W8},
6911         };
6912
6913         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6914                 return ret;
6915
6916         /* Only one item allowed for default or all */
6917         if (size == 1) {
6918                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6919                         *inset = i40e_get_default_input_set(pctype);
6920                         return 0;
6921                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6922                         *inset = I40E_INSET_NONE;
6923                         return 0;
6924                 }
6925         }
6926
6927         for (i = 0, *inset = 0; i < size; i++) {
6928                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6929                         if (field[i] == inset_convert_table[j].field) {
6930                                 *inset |= inset_convert_table[j].inset;
6931                                 break;
6932                         }
6933                 }
6934
6935                 /* It contains unsupported input set, return immediately */
6936                 if (j == RTE_DIM(inset_convert_table))
6937                         return ret;
6938         }
6939
6940         return 0;
6941 }
6942
6943 /**
6944  * Translate the input set from bit masks to register aware bit masks
6945  * and vice versa
6946  */
6947 static uint64_t
6948 i40e_translate_input_set_reg(uint64_t input)
6949 {
6950         uint64_t val = 0;
6951         uint16_t i;
6952
6953         static const struct {
6954                 uint64_t inset;
6955                 uint64_t inset_reg;
6956         } inset_map[] = {
6957                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6958                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6959                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6960                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6961                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6962                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6963                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6964                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6965                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6966                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6967                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6968                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6969                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6970                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6971                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6972                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6973                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6974                 {I40E_INSET_TUNNEL_DMAC,
6975                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6976                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6977                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6978                 {I40E_INSET_TUNNEL_SRC_PORT,
6979                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6980                 {I40E_INSET_TUNNEL_DST_PORT,
6981                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6982                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6983                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6984                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6985                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6986                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6987                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6988                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6989                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6990                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6991         };
6992
6993         if (input == 0)
6994                 return val;
6995
6996         /* Translate input set to register aware inset */
6997         for (i = 0; i < RTE_DIM(inset_map); i++) {
6998                 if (input & inset_map[i].inset)
6999                         val |= inset_map[i].inset_reg;
7000         }
7001
7002         return val;
7003 }
7004
7005 static uint8_t
7006 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7007 {
7008         uint8_t i, idx = 0;
7009
7010         static const struct {
7011                 uint64_t inset;
7012                 uint32_t mask;
7013         } inset_mask_map[] = {
7014                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7015                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7016                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7017                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7018         };
7019
7020         if (!inset || !mask || !nb_elem)
7021                 return 0;
7022
7023         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
7024                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
7025                         mask[i] = 0;
7026                 return I40E_INSET_MASK_NUM_REG;
7027         }
7028
7029         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7030                 if (idx >= nb_elem)
7031                         break;
7032                 if (inset & inset_mask_map[i].inset) {
7033                         mask[idx] = inset_mask_map[i].mask;
7034                         idx++;
7035                 }
7036         }
7037
7038         return idx;
7039 }
7040
7041 static uint64_t
7042 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
7043                             enum i40e_filter_pctype pctype)
7044 {
7045         uint64_t reg = 0;
7046
7047         if (filter == RTE_ETH_FILTER_HASH) {
7048                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7049                 reg <<= I40E_32_BIT_WIDTH;
7050                 reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7051         } else if (filter == RTE_ETH_FILTER_FDIR) {
7052                 reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7053                 reg <<= I40E_32_BIT_WIDTH;
7054                 reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7055         }
7056
7057         return reg;
7058 }
7059
7060 static void
7061 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7062 {
7063         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7064
7065         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7066         if (reg != val)
7067                 i40e_write_rx_ctl(hw, addr, val);
7068         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7069                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7070 }
7071
7072 static int
7073 i40e_set_hash_inset_mask(struct i40e_hw *hw,
7074                          enum i40e_filter_pctype pctype,
7075                          enum rte_filter_input_set_op op,
7076                          uint32_t *mask_reg,
7077                          uint8_t num)
7078 {
7079         uint32_t reg;
7080         uint8_t i;
7081
7082         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7083                 return -EINVAL;
7084
7085         if (op == RTE_ETH_INPUT_SET_SELECT) {
7086                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7087                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7088                                              0);
7089                         if (i >= num)
7090                                 continue;
7091                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7092                                              mask_reg[i]);
7093                 }
7094         } else if (op == RTE_ETH_INPUT_SET_ADD) {
7095                 uint8_t j, count = 0;
7096
7097                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7098                         reg = i40e_read_rx_ctl(hw,
7099                                                I40E_GLQF_HASH_MSK(i, pctype));
7100                         if (reg & I40E_GLQF_HASH_MSK_MASK_MASK)
7101                                 count++;
7102                 }
7103                 if (count + num > I40E_INSET_MASK_NUM_REG)
7104                         return -EINVAL;
7105
7106                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7107                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7108                                              mask_reg[j]);
7109         }
7110
7111         return 0;
7112 }
7113
7114 static int
7115 i40e_set_fd_inset_mask(struct i40e_hw *hw,
7116                        enum i40e_filter_pctype pctype,
7117                        enum rte_filter_input_set_op op,
7118                        uint32_t *mask_reg,
7119                        uint8_t num)
7120 {
7121         uint32_t reg;
7122         uint8_t i;
7123
7124         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7125                 return -EINVAL;
7126
7127         if (op == RTE_ETH_INPUT_SET_SELECT) {
7128                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7129                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7130                                              0);
7131                         if (i >= num)
7132                                 continue;
7133                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7134                                              mask_reg[i]);
7135                 }
7136         } else if (op == RTE_ETH_INPUT_SET_ADD) {
7137                 uint8_t j, count = 0;
7138
7139                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7140                         reg = i40e_read_rx_ctl(hw,
7141                                                I40E_GLQF_FD_MSK(i, pctype));
7142                         if (reg & I40E_GLQF_FD_MSK_MASK_MASK)
7143                                 count++;
7144                 }
7145                 if (count + num > I40E_INSET_MASK_NUM_REG)
7146                         return -EINVAL;
7147
7148                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7149                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7150                                              mask_reg[j]);
7151         }
7152
7153         return 0;
7154 }
7155
7156 int
7157 i40e_filter_inset_select(struct i40e_hw *hw,
7158                          struct rte_eth_input_set_conf *conf,
7159                          enum rte_filter_type filter)
7160 {
7161         enum i40e_filter_pctype pctype;
7162         uint64_t inset_reg = 0, input_set;
7163         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
7164         uint8_t num;
7165         int ret;
7166
7167         if (!hw || !conf) {
7168                 PMD_DRV_LOG(ERR, "Invalid pointer");
7169                 return -EFAULT;
7170         }
7171
7172         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7173         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7174                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7175                             conf->flow_type);
7176                 return -EINVAL;
7177         }
7178         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
7179                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7180                 return -EINVAL;
7181         }
7182
7183         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7184                                    conf->inset_size);
7185         if (ret) {
7186                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7187                 return -EINVAL;
7188         }
7189         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
7190                 PMD_DRV_LOG(ERR, "Invalid input set");
7191                 return -EINVAL;
7192         }
7193
7194         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7195                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7196         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7197                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7198                 return -EINVAL;
7199         }
7200         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7201                                            I40E_INSET_MASK_NUM_REG);
7202         inset_reg |= i40e_translate_input_set_reg(input_set);
7203
7204         if (filter == RTE_ETH_FILTER_HASH) {
7205                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7206                                                num);
7207                 if (ret)
7208                         return -EINVAL;
7209
7210                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7211                                       (uint32_t)(inset_reg & UINT32_MAX));
7212                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7213                                      (uint32_t)((inset_reg >>
7214                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7215         } else if (filter == RTE_ETH_FILTER_FDIR) {
7216                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7217                                              num);
7218                 if (ret)
7219                         return -EINVAL;
7220
7221                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7222                                       (uint32_t)(inset_reg & UINT32_MAX));
7223                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7224                                      (uint32_t)((inset_reg >>
7225                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7226         } else {
7227                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7228                 return -EINVAL;
7229         }
7230         I40E_WRITE_FLUSH(hw);
7231
7232         return 0;
7233 }
7234
7235 static int
7236 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7237 {
7238         int ret = 0;
7239
7240         if (!hw || !info) {
7241                 PMD_DRV_LOG(ERR, "Invalid pointer");
7242                 return -EFAULT;
7243         }
7244
7245         switch (info->info_type) {
7246         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7247                 i40e_get_symmetric_hash_enable_per_port(hw,
7248                                         &(info->info.enable));
7249                 break;
7250         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7251                 ret = i40e_get_hash_filter_global_config(hw,
7252                                 &(info->info.global_conf));
7253                 break;
7254         default:
7255                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7256                                                         info->info_type);
7257                 ret = -EINVAL;
7258                 break;
7259         }
7260
7261         return ret;
7262 }
7263
7264 static int
7265 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7266 {
7267         int ret = 0;
7268
7269         if (!hw || !info) {
7270                 PMD_DRV_LOG(ERR, "Invalid pointer");
7271                 return -EFAULT;
7272         }
7273
7274         switch (info->info_type) {
7275         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7276                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7277                 break;
7278         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7279                 ret = i40e_set_hash_filter_global_config(hw,
7280                                 &(info->info.global_conf));
7281                 break;
7282         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7283                 ret = i40e_filter_inset_select(hw,
7284                                                &(info->info.input_set_conf),
7285                                                RTE_ETH_FILTER_HASH);
7286                 break;
7287
7288         default:
7289                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7290                                                         info->info_type);
7291                 ret = -EINVAL;
7292                 break;
7293         }
7294
7295         return ret;
7296 }
7297
7298 /* Operations for hash function */
7299 static int
7300 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7301                       enum rte_filter_op filter_op,
7302                       void *arg)
7303 {
7304         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7305         int ret = 0;
7306
7307         switch (filter_op) {
7308         case RTE_ETH_FILTER_NOP:
7309                 break;
7310         case RTE_ETH_FILTER_GET:
7311                 ret = i40e_hash_filter_get(hw,
7312                         (struct rte_eth_hash_filter_info *)arg);
7313                 break;
7314         case RTE_ETH_FILTER_SET:
7315                 ret = i40e_hash_filter_set(hw,
7316                         (struct rte_eth_hash_filter_info *)arg);
7317                 break;
7318         default:
7319                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7320                                                                 filter_op);
7321                 ret = -ENOTSUP;
7322                 break;
7323         }
7324
7325         return ret;
7326 }
7327
7328 /*
7329  * Configure ethertype filter, which can director packet by filtering
7330  * with mac address and ether_type or only ether_type
7331  */
7332 static int
7333 i40e_ethertype_filter_set(struct i40e_pf *pf,
7334                         struct rte_eth_ethertype_filter *filter,
7335                         bool add)
7336 {
7337         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7338         struct i40e_control_filter_stats stats;
7339         uint16_t flags = 0;
7340         int ret;
7341
7342         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7343                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7344                 return -EINVAL;
7345         }
7346         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7347                 filter->ether_type == ETHER_TYPE_IPv6) {
7348                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7349                         " control packet filter.", filter->ether_type);
7350                 return -EINVAL;
7351         }
7352         if (filter->ether_type == ETHER_TYPE_VLAN)
7353                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7354                         " not supported.");
7355
7356         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7357                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7358         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7359                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7360         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7361
7362         memset(&stats, 0, sizeof(stats));
7363         ret = i40e_aq_add_rem_control_packet_filter(hw,
7364                         filter->mac_addr.addr_bytes,
7365                         filter->ether_type, flags,
7366                         pf->main_vsi->seid,
7367                         filter->queue, add, &stats, NULL);
7368
7369         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7370                          " mac_etype_used = %u, etype_used = %u,"
7371                          " mac_etype_free = %u, etype_free = %u\n",
7372                          ret, stats.mac_etype_used, stats.etype_used,
7373                          stats.mac_etype_free, stats.etype_free);
7374         if (ret < 0)
7375                 return -ENOSYS;
7376         return 0;
7377 }
7378
7379 /*
7380  * Handle operations for ethertype filter.
7381  */
7382 static int
7383 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7384                                 enum rte_filter_op filter_op,
7385                                 void *arg)
7386 {
7387         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7388         int ret = 0;
7389
7390         if (filter_op == RTE_ETH_FILTER_NOP)
7391                 return ret;
7392
7393         if (arg == NULL) {
7394                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7395                             filter_op);
7396                 return -EINVAL;
7397         }
7398
7399         switch (filter_op) {
7400         case RTE_ETH_FILTER_ADD:
7401                 ret = i40e_ethertype_filter_set(pf,
7402                         (struct rte_eth_ethertype_filter *)arg,
7403                         TRUE);
7404                 break;
7405         case RTE_ETH_FILTER_DELETE:
7406                 ret = i40e_ethertype_filter_set(pf,
7407                         (struct rte_eth_ethertype_filter *)arg,
7408                         FALSE);
7409                 break;
7410         default:
7411                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7412                 ret = -ENOSYS;
7413                 break;
7414         }
7415         return ret;
7416 }
7417
7418 static int
7419 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7420                      enum rte_filter_type filter_type,
7421                      enum rte_filter_op filter_op,
7422                      void *arg)
7423 {
7424         int ret = 0;
7425
7426         if (dev == NULL)
7427                 return -EINVAL;
7428
7429         switch (filter_type) {
7430         case RTE_ETH_FILTER_NONE:
7431                 /* For global configuration */
7432                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7433                 break;
7434         case RTE_ETH_FILTER_HASH:
7435                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7436                 break;
7437         case RTE_ETH_FILTER_MACVLAN:
7438                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7439                 break;
7440         case RTE_ETH_FILTER_ETHERTYPE:
7441                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7442                 break;
7443         case RTE_ETH_FILTER_TUNNEL:
7444                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7445                 break;
7446         case RTE_ETH_FILTER_FDIR:
7447                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7448                 break;
7449         default:
7450                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7451                                                         filter_type);
7452                 ret = -EINVAL;
7453                 break;
7454         }
7455
7456         return ret;
7457 }
7458
7459 /*
7460  * Check and enable Extended Tag.
7461  * Enabling Extended Tag is important for 40G performance.
7462  */
7463 static void
7464 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7465 {
7466         uint32_t buf = 0;
7467         int ret;
7468
7469         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7470                                       PCI_DEV_CAP_REG);
7471         if (ret < 0) {
7472                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7473                             PCI_DEV_CAP_REG);
7474                 return;
7475         }
7476         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7477                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7478                 return;
7479         }
7480
7481         buf = 0;
7482         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7483                                       PCI_DEV_CTRL_REG);
7484         if (ret < 0) {
7485                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7486                             PCI_DEV_CTRL_REG);
7487                 return;
7488         }
7489         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7490                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7491                 return;
7492         }
7493         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7494         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7495                                        PCI_DEV_CTRL_REG);
7496         if (ret < 0) {
7497                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7498                             PCI_DEV_CTRL_REG);
7499                 return;
7500         }
7501 }
7502
7503 /*
7504  * As some registers wouldn't be reset unless a global hardware reset,
7505  * hardware initialization is needed to put those registers into an
7506  * expected initial state.
7507  */
7508 static void
7509 i40e_hw_init(struct rte_eth_dev *dev)
7510 {
7511         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7512
7513         i40e_enable_extended_tag(dev);
7514
7515         /* clear the PF Queue Filter control register */
7516         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7517
7518         /* Disable symmetric hash per port */
7519         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7520 }
7521
7522 enum i40e_filter_pctype
7523 i40e_flowtype_to_pctype(uint16_t flow_type)
7524 {
7525         static const enum i40e_filter_pctype pctype_table[] = {
7526                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7527                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7528                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7529                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7530                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7531                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7532                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7533                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7534                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7535                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7536                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7537                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7538                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7539                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7540                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7541                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7542                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7543                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7544                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7545         };
7546
7547         return pctype_table[flow_type];
7548 }
7549
7550 uint16_t
7551 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7552 {
7553         static const uint16_t flowtype_table[] = {
7554                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7555                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7556                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7557                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7558                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7559                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7560                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7561                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7562                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7563                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7564                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7565                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7566                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7567                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7568                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7569                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7570                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7571                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7572                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7573         };
7574
7575         return flowtype_table[pctype];
7576 }
7577
7578 /*
7579  * On X710, performance number is far from the expectation on recent firmware
7580  * versions; on XL710, performance number is also far from the expectation on
7581  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7582  * mode is enabled and port MAC address is equal to the packet destination MAC
7583  * address. The fix for this issue may not be integrated in the following
7584  * firmware version. So the workaround in software driver is needed. It needs
7585  * to modify the initial values of 3 internal only registers for both X710 and
7586  * XL710. Note that the values for X710 or XL710 could be different, and the
7587  * workaround can be removed when it is fixed in firmware in the future.
7588  */
7589
7590 /* For both X710 and XL710 */
7591 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7592 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7593
7594 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7595 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7596
7597 /* For X710 */
7598 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7599 /* For XL710 */
7600 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7601 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7602
7603 static void
7604 i40e_configure_registers(struct i40e_hw *hw)
7605 {
7606         static struct {
7607                 uint32_t addr;
7608                 uint64_t val;
7609         } reg_table[] = {
7610                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7611                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7612                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7613         };
7614         uint64_t reg;
7615         uint32_t i;
7616         int ret;
7617
7618         for (i = 0; i < RTE_DIM(reg_table); i++) {
7619                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7620                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7621                                 reg_table[i].val =
7622                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7623                         else /* For X710 */
7624                                 reg_table[i].val =
7625                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7626                 }
7627
7628                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7629                                                         &reg, NULL);
7630                 if (ret < 0) {
7631                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7632                                                         reg_table[i].addr);
7633                         break;
7634                 }
7635                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7636                                                 reg_table[i].addr, reg);
7637                 if (reg == reg_table[i].val)
7638                         continue;
7639
7640                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7641                                                 reg_table[i].val, NULL);
7642                 if (ret < 0) {
7643                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7644                                 "address of 0x%"PRIx32, reg_table[i].val,
7645                                                         reg_table[i].addr);
7646                         break;
7647                 }
7648                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7649                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7650         }
7651 }
7652
7653 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7654 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7655 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7656 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7657 static int
7658 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7659 {
7660         uint32_t reg;
7661         int ret;
7662
7663         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7664                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7665                 return -EINVAL;
7666         }
7667
7668         /* Configure for double VLAN RX stripping */
7669         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7670         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7671                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7672                 ret = i40e_aq_debug_write_register(hw,
7673                                                    I40E_VSI_TSR(vsi->vsi_id),
7674                                                    reg, NULL);
7675                 if (ret < 0) {
7676                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7677                                     vsi->vsi_id);
7678                         return I40E_ERR_CONFIG;
7679                 }
7680         }
7681
7682         /* Configure for double VLAN TX insertion */
7683         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7684         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7685                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7686                 ret = i40e_aq_debug_write_register(hw,
7687                                                    I40E_VSI_L2TAGSTXVALID(
7688                                                    vsi->vsi_id), reg, NULL);
7689                 if (ret < 0) {
7690                         PMD_DRV_LOG(ERR, "Failed to update "
7691                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7692                         return I40E_ERR_CONFIG;
7693                 }
7694         }
7695
7696         return 0;
7697 }
7698
7699 /**
7700  * i40e_aq_add_mirror_rule
7701  * @hw: pointer to the hardware structure
7702  * @seid: VEB seid to add mirror rule to
7703  * @dst_id: destination vsi seid
7704  * @entries: Buffer which contains the entities to be mirrored
7705  * @count: number of entities contained in the buffer
7706  * @rule_id:the rule_id of the rule to be added
7707  *
7708  * Add a mirror rule for a given veb.
7709  *
7710  **/
7711 static enum i40e_status_code
7712 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7713                         uint16_t seid, uint16_t dst_id,
7714                         uint16_t rule_type, uint16_t *entries,
7715                         uint16_t count, uint16_t *rule_id)
7716 {
7717         struct i40e_aq_desc desc;
7718         struct i40e_aqc_add_delete_mirror_rule cmd;
7719         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7720                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7721                 &desc.params.raw;
7722         uint16_t buff_len;
7723         enum i40e_status_code status;
7724
7725         i40e_fill_default_direct_cmd_desc(&desc,
7726                                           i40e_aqc_opc_add_mirror_rule);
7727         memset(&cmd, 0, sizeof(cmd));
7728
7729         buff_len = sizeof(uint16_t) * count;
7730         desc.datalen = rte_cpu_to_le_16(buff_len);
7731         if (buff_len > 0)
7732                 desc.flags |= rte_cpu_to_le_16(
7733                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7734         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7735                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7736         cmd.num_entries = rte_cpu_to_le_16(count);
7737         cmd.seid = rte_cpu_to_le_16(seid);
7738         cmd.destination = rte_cpu_to_le_16(dst_id);
7739
7740         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7741         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7742         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7743                          "rule_id = %u"
7744                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7745                          hw->aq.asq_last_status, resp->rule_id,
7746                          resp->mirror_rules_used, resp->mirror_rules_free);
7747         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7748
7749         return status;
7750 }
7751
7752 /**
7753  * i40e_aq_del_mirror_rule
7754  * @hw: pointer to the hardware structure
7755  * @seid: VEB seid to add mirror rule to
7756  * @entries: Buffer which contains the entities to be mirrored
7757  * @count: number of entities contained in the buffer
7758  * @rule_id:the rule_id of the rule to be delete
7759  *
7760  * Delete a mirror rule for a given veb.
7761  *
7762  **/
7763 static enum i40e_status_code
7764 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7765                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7766                 uint16_t count, uint16_t rule_id)
7767 {
7768         struct i40e_aq_desc desc;
7769         struct i40e_aqc_add_delete_mirror_rule cmd;
7770         uint16_t buff_len = 0;
7771         enum i40e_status_code status;
7772         void *buff = NULL;
7773
7774         i40e_fill_default_direct_cmd_desc(&desc,
7775                                           i40e_aqc_opc_delete_mirror_rule);
7776         memset(&cmd, 0, sizeof(cmd));
7777         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7778                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7779                                                           I40E_AQ_FLAG_RD));
7780                 cmd.num_entries = count;
7781                 buff_len = sizeof(uint16_t) * count;
7782                 desc.datalen = rte_cpu_to_le_16(buff_len);
7783                 buff = (void *)entries;
7784         } else
7785                 /* rule id is filled in destination field for deleting mirror rule */
7786                 cmd.destination = rte_cpu_to_le_16(rule_id);
7787
7788         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7789                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7790         cmd.seid = rte_cpu_to_le_16(seid);
7791
7792         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7793         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7794
7795         return status;
7796 }
7797
7798 /**
7799  * i40e_mirror_rule_set
7800  * @dev: pointer to the hardware structure
7801  * @mirror_conf: mirror rule info
7802  * @sw_id: mirror rule's sw_id
7803  * @on: enable/disable
7804  *
7805  * set a mirror rule.
7806  *
7807  **/
7808 static int
7809 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7810                         struct rte_eth_mirror_conf *mirror_conf,
7811                         uint8_t sw_id, uint8_t on)
7812 {
7813         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7815         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7816         struct i40e_mirror_rule *parent = NULL;
7817         uint16_t seid, dst_seid, rule_id;
7818         uint16_t i, j = 0;
7819         int ret;
7820
7821         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7822
7823         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7824                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7825                         " without veb or vfs.");
7826                 return -ENOSYS;
7827         }
7828         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7829                 PMD_DRV_LOG(ERR, "mirror table is full.");
7830                 return -ENOSPC;
7831         }
7832         if (mirror_conf->dst_pool > pf->vf_num) {
7833                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7834                                  mirror_conf->dst_pool);
7835                 return -EINVAL;
7836         }
7837
7838         seid = pf->main_vsi->veb->seid;
7839
7840         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7841                 if (sw_id <= it->index) {
7842                         mirr_rule = it;
7843                         break;
7844                 }
7845                 parent = it;
7846         }
7847         if (mirr_rule && sw_id == mirr_rule->index) {
7848                 if (on) {
7849                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7850                         return -EEXIST;
7851                 } else {
7852                         ret = i40e_aq_del_mirror_rule(hw, seid,
7853                                         mirr_rule->rule_type,
7854                                         mirr_rule->entries,
7855                                         mirr_rule->num_entries, mirr_rule->id);
7856                         if (ret < 0) {
7857                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7858                                                    " ret = %d, aq_err = %d.",
7859                                                    ret, hw->aq.asq_last_status);
7860                                 return -ENOSYS;
7861                         }
7862                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7863                         rte_free(mirr_rule);
7864                         pf->nb_mirror_rule--;
7865                         return 0;
7866                 }
7867         } else if (!on) {
7868                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7869                 return -ENOENT;
7870         }
7871
7872         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7873                                 sizeof(struct i40e_mirror_rule) , 0);
7874         if (!mirr_rule) {
7875                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7876                 return I40E_ERR_NO_MEMORY;
7877         }
7878         switch (mirror_conf->rule_type) {
7879         case ETH_MIRROR_VLAN:
7880                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7881                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7882                                 mirr_rule->entries[j] =
7883                                         mirror_conf->vlan.vlan_id[i];
7884                                 j++;
7885                         }
7886                 }
7887                 if (j == 0) {
7888                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7889                         rte_free(mirr_rule);
7890                         return -EINVAL;
7891                 }
7892                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7893                 break;
7894         case ETH_MIRROR_VIRTUAL_POOL_UP:
7895         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7896                 /* check if the specified pool bit is out of range */
7897                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7898                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7899                         rte_free(mirr_rule);
7900                         return -EINVAL;
7901                 }
7902                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7903                         if (mirror_conf->pool_mask & (1ULL << i)) {
7904                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7905                                 j++;
7906                         }
7907                 }
7908                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7909                         /* add pf vsi to entries */
7910                         mirr_rule->entries[j] = pf->main_vsi_seid;
7911                         j++;
7912                 }
7913                 if (j == 0) {
7914                         PMD_DRV_LOG(ERR, "pool is not specified.");
7915                         rte_free(mirr_rule);
7916                         return -EINVAL;
7917                 }
7918                 /* egress and ingress in aq commands means from switch but not port */
7919                 mirr_rule->rule_type =
7920                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7921                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7922                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7923                 break;
7924         case ETH_MIRROR_UPLINK_PORT:
7925                 /* egress and ingress in aq commands means from switch but not port*/
7926                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7927                 break;
7928         case ETH_MIRROR_DOWNLINK_PORT:
7929                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7930                 break;
7931         default:
7932                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7933                         mirror_conf->rule_type);
7934                 rte_free(mirr_rule);
7935                 return -EINVAL;
7936         }
7937
7938         /* If the dst_pool is equal to vf_num, consider it as PF */
7939         if (mirror_conf->dst_pool == pf->vf_num)
7940                 dst_seid = pf->main_vsi_seid;
7941         else
7942                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7943
7944         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7945                                       mirr_rule->rule_type, mirr_rule->entries,
7946                                       j, &rule_id);
7947         if (ret < 0) {
7948                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7949                                    " ret = %d, aq_err = %d.",
7950                                    ret, hw->aq.asq_last_status);
7951                 rte_free(mirr_rule);
7952                 return -ENOSYS;
7953         }
7954
7955         mirr_rule->index = sw_id;
7956         mirr_rule->num_entries = j;
7957         mirr_rule->id = rule_id;
7958         mirr_rule->dst_vsi_seid = dst_seid;
7959
7960         if (parent)
7961                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7962         else
7963                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7964
7965         pf->nb_mirror_rule++;
7966         return 0;
7967 }
7968
7969 /**
7970  * i40e_mirror_rule_reset
7971  * @dev: pointer to the device
7972  * @sw_id: mirror rule's sw_id
7973  *
7974  * reset a mirror rule.
7975  *
7976  **/
7977 static int
7978 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7979 {
7980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7982         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7983         uint16_t seid;
7984         int ret;
7985
7986         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7987
7988         seid = pf->main_vsi->veb->seid;
7989
7990         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7991                 if (sw_id == it->index) {
7992                         mirr_rule = it;
7993                         break;
7994                 }
7995         }
7996         if (mirr_rule) {
7997                 ret = i40e_aq_del_mirror_rule(hw, seid,
7998                                 mirr_rule->rule_type,
7999                                 mirr_rule->entries,
8000                                 mirr_rule->num_entries, mirr_rule->id);
8001                 if (ret < 0) {
8002                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8003                                            " status = %d, aq_err = %d.",
8004                                            ret, hw->aq.asq_last_status);
8005                         return -ENOSYS;
8006                 }
8007                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8008                 rte_free(mirr_rule);
8009                 pf->nb_mirror_rule--;
8010         } else {
8011                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8012                 return -ENOENT;
8013         }
8014         return 0;
8015 }
8016
8017 static uint64_t
8018 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8019 {
8020         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8021         uint64_t systim_cycles;
8022
8023         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8024         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8025                         << 32;
8026
8027         return systim_cycles;
8028 }
8029
8030 static uint64_t
8031 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8032 {
8033         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8034         uint64_t rx_tstamp;
8035
8036         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8037         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8038                         << 32;
8039
8040         return rx_tstamp;
8041 }
8042
8043 static uint64_t
8044 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8045 {
8046         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8047         uint64_t tx_tstamp;
8048
8049         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8050         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8051                         << 32;
8052
8053         return tx_tstamp;
8054 }
8055
8056 static void
8057 i40e_start_timecounters(struct rte_eth_dev *dev)
8058 {
8059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8060         struct i40e_adapter *adapter =
8061                         (struct i40e_adapter *)dev->data->dev_private;
8062         struct rte_eth_link link;
8063         uint32_t tsync_inc_l;
8064         uint32_t tsync_inc_h;
8065
8066         /* Get current link speed. */
8067         memset(&link, 0, sizeof(link));
8068         i40e_dev_link_update(dev, 1);
8069         rte_i40e_dev_atomic_read_link_status(dev, &link);
8070
8071         switch (link.link_speed) {
8072         case ETH_LINK_SPEED_40G:
8073                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8074                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8075                 break;
8076         case ETH_LINK_SPEED_10G:
8077                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8078                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8079                 break;
8080         case ETH_LINK_SPEED_1000:
8081                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8082                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8083                 break;
8084         default:
8085                 tsync_inc_l = 0x0;
8086                 tsync_inc_h = 0x0;
8087         }
8088
8089         /* Set the timesync increment value. */
8090         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8091         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8092
8093         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8094         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8095         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8096
8097         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8098         adapter->systime_tc.cc_shift = 0;
8099         adapter->systime_tc.nsec_mask = 0;
8100
8101         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8102         adapter->rx_tstamp_tc.cc_shift = 0;
8103         adapter->rx_tstamp_tc.nsec_mask = 0;
8104
8105         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8106         adapter->tx_tstamp_tc.cc_shift = 0;
8107         adapter->tx_tstamp_tc.nsec_mask = 0;
8108 }
8109
8110 static int
8111 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8112 {
8113         struct i40e_adapter *adapter =
8114                         (struct i40e_adapter *)dev->data->dev_private;
8115
8116         adapter->systime_tc.nsec += delta;
8117         adapter->rx_tstamp_tc.nsec += delta;
8118         adapter->tx_tstamp_tc.nsec += delta;
8119
8120         return 0;
8121 }
8122
8123 static int
8124 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8125 {
8126         uint64_t ns;
8127         struct i40e_adapter *adapter =
8128                         (struct i40e_adapter *)dev->data->dev_private;
8129
8130         ns = rte_timespec_to_ns(ts);
8131
8132         /* Set the timecounters to a new value. */
8133         adapter->systime_tc.nsec = ns;
8134         adapter->rx_tstamp_tc.nsec = ns;
8135         adapter->tx_tstamp_tc.nsec = ns;
8136
8137         return 0;
8138 }
8139
8140 static int
8141 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8142 {
8143         uint64_t ns, systime_cycles;
8144         struct i40e_adapter *adapter =
8145                         (struct i40e_adapter *)dev->data->dev_private;
8146
8147         systime_cycles = i40e_read_systime_cyclecounter(dev);
8148         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8149         *ts = rte_ns_to_timespec(ns);
8150
8151         return 0;
8152 }
8153
8154 static int
8155 i40e_timesync_enable(struct rte_eth_dev *dev)
8156 {
8157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8158         uint32_t tsync_ctl_l;
8159         uint32_t tsync_ctl_h;
8160
8161         /* Stop the timesync system time. */
8162         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8163         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8164         /* Reset the timesync system time value. */
8165         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8166         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8167
8168         i40e_start_timecounters(dev);
8169
8170         /* Clear timesync registers. */
8171         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8172         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8173         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8174         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8175         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8176         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8177
8178         /* Enable timestamping of PTP packets. */
8179         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8180         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8181
8182         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8183         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8184         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8185
8186         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8187         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8188
8189         return 0;
8190 }
8191
8192 static int
8193 i40e_timesync_disable(struct rte_eth_dev *dev)
8194 {
8195         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8196         uint32_t tsync_ctl_l;
8197         uint32_t tsync_ctl_h;
8198
8199         /* Disable timestamping of transmitted PTP packets. */
8200         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8201         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8202
8203         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8204         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8205
8206         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8207         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8208
8209         /* Reset the timesync increment value. */
8210         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8211         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8212
8213         return 0;
8214 }
8215
8216 static int
8217 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8218                                 struct timespec *timestamp, uint32_t flags)
8219 {
8220         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8221         struct i40e_adapter *adapter =
8222                 (struct i40e_adapter *)dev->data->dev_private;
8223
8224         uint32_t sync_status;
8225         uint32_t index = flags & 0x03;
8226         uint64_t rx_tstamp_cycles;
8227         uint64_t ns;
8228
8229         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8230         if ((sync_status & (1 << index)) == 0)
8231                 return -EINVAL;
8232
8233         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8234         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8235         *timestamp = rte_ns_to_timespec(ns);
8236
8237         return 0;
8238 }
8239
8240 static int
8241 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8242                                 struct timespec *timestamp)
8243 {
8244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8245         struct i40e_adapter *adapter =
8246                 (struct i40e_adapter *)dev->data->dev_private;
8247
8248         uint32_t sync_status;
8249         uint64_t tx_tstamp_cycles;
8250         uint64_t ns;
8251
8252         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8253         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8254                 return -EINVAL;
8255
8256         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8257         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8258         *timestamp = rte_ns_to_timespec(ns);
8259
8260         return 0;
8261 }
8262
8263 /*
8264  * i40e_parse_dcb_configure - parse dcb configure from user
8265  * @dev: the device being configured
8266  * @dcb_cfg: pointer of the result of parse
8267  * @*tc_map: bit map of enabled traffic classes
8268  *
8269  * Returns 0 on success, negative value on failure
8270  */
8271 static int
8272 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8273                          struct i40e_dcbx_config *dcb_cfg,
8274                          uint8_t *tc_map)
8275 {
8276         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8277         uint8_t i, tc_bw, bw_lf;
8278
8279         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8280
8281         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8282         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8283                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8284                 return -EINVAL;
8285         }
8286
8287         /* assume each tc has the same bw */
8288         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8289         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8290                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8291         /* to ensure the sum of tcbw is equal to 100 */
8292         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8293         for (i = 0; i < bw_lf; i++)
8294                 dcb_cfg->etscfg.tcbwtable[i]++;
8295
8296         /* assume each tc has the same Transmission Selection Algorithm */
8297         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8298                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8299
8300         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8301                 dcb_cfg->etscfg.prioritytable[i] =
8302                                 dcb_rx_conf->dcb_tc[i];
8303
8304         /* FW needs one App to configure HW */
8305         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8306         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8307         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8308         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8309
8310         if (dcb_rx_conf->nb_tcs == 0)
8311                 *tc_map = 1; /* tc0 only */
8312         else
8313                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8314
8315         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8316                 dcb_cfg->pfc.willing = 0;
8317                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8318                 dcb_cfg->pfc.pfcenable = *tc_map;
8319         }
8320         return 0;
8321 }
8322
8323
8324 static enum i40e_status_code
8325 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8326                               struct i40e_aqc_vsi_properties_data *info,
8327                               uint8_t enabled_tcmap)
8328 {
8329         enum i40e_status_code ret;
8330         int i, total_tc = 0;
8331         uint16_t qpnum_per_tc, bsf, qp_idx;
8332         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8333         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8334         uint16_t used_queues;
8335
8336         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8337         if (ret != I40E_SUCCESS)
8338                 return ret;
8339
8340         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8341                 if (enabled_tcmap & (1 << i))
8342                         total_tc++;
8343         }
8344         if (total_tc == 0)
8345                 total_tc = 1;
8346         vsi->enabled_tc = enabled_tcmap;
8347
8348         /* different VSI has different queues assigned */
8349         if (vsi->type == I40E_VSI_MAIN)
8350                 used_queues = dev_data->nb_rx_queues -
8351                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8352         else if (vsi->type == I40E_VSI_VMDQ2)
8353                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8354         else {
8355                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8356                 return I40E_ERR_NO_AVAILABLE_VSI;
8357         }
8358
8359         qpnum_per_tc = used_queues / total_tc;
8360         /* Number of queues per enabled TC */
8361         if (qpnum_per_tc == 0) {
8362                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8363                 return I40E_ERR_INVALID_QP_ID;
8364         }
8365         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8366                                 I40E_MAX_Q_PER_TC);
8367         bsf = rte_bsf32(qpnum_per_tc);
8368
8369         /**
8370          * Configure TC and queue mapping parameters, for enabled TC,
8371          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8372          * default queue will serve it.
8373          */
8374         qp_idx = 0;
8375         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8376                 if (vsi->enabled_tc & (1 << i)) {
8377                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8378                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8379                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8380                         qp_idx += qpnum_per_tc;
8381                 } else
8382                         info->tc_mapping[i] = 0;
8383         }
8384
8385         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8386         if (vsi->type == I40E_VSI_SRIOV) {
8387                 info->mapping_flags |=
8388                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8389                 for (i = 0; i < vsi->nb_qps; i++)
8390                         info->queue_mapping[i] =
8391                                 rte_cpu_to_le_16(vsi->base_queue + i);
8392         } else {
8393                 info->mapping_flags |=
8394                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8395                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8396         }
8397         info->valid_sections |=
8398                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8399
8400         return I40E_SUCCESS;
8401 }
8402
8403 /*
8404  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8405  * @veb: VEB to be configured
8406  * @tc_map: enabled TC bitmap
8407  *
8408  * Returns 0 on success, negative value on failure
8409  */
8410 static enum i40e_status_code
8411 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8412 {
8413         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8414         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8415         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8416         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8417         enum i40e_status_code ret = I40E_SUCCESS;
8418         int i;
8419         uint32_t bw_max;
8420
8421         /* Check if enabled_tc is same as existing or new TCs */
8422         if (veb->enabled_tc == tc_map)
8423                 return ret;
8424
8425         /* configure tc bandwidth */
8426         memset(&veb_bw, 0, sizeof(veb_bw));
8427         veb_bw.tc_valid_bits = tc_map;
8428         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8429         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8430                 if (tc_map & BIT_ULL(i))
8431                         veb_bw.tc_bw_share_credits[i] = 1;
8432         }
8433         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8434                                                    &veb_bw, NULL);
8435         if (ret) {
8436                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8437                                   " per TC failed = %d",
8438                                   hw->aq.asq_last_status);
8439                 return ret;
8440         }
8441
8442         memset(&ets_query, 0, sizeof(ets_query));
8443         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8444                                                    &ets_query, NULL);
8445         if (ret != I40E_SUCCESS) {
8446                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8447                                  " configuration %u", hw->aq.asq_last_status);
8448                 return ret;
8449         }
8450         memset(&bw_query, 0, sizeof(bw_query));
8451         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8452                                                   &bw_query, NULL);
8453         if (ret != I40E_SUCCESS) {
8454                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8455                                  " configuration %u", hw->aq.asq_last_status);
8456                 return ret;
8457         }
8458
8459         /* store and print out BW info */
8460         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8461         veb->bw_info.bw_max = ets_query.tc_bw_max;
8462         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8463         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8464         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8465                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8466                      I40E_16_BIT_WIDTH);
8467         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8468                 veb->bw_info.bw_ets_share_credits[i] =
8469                                 bw_query.tc_bw_share_credits[i];
8470                 veb->bw_info.bw_ets_credits[i] =
8471                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8472                 /* 4 bits per TC, 4th bit is reserved */
8473                 veb->bw_info.bw_ets_max[i] =
8474                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8475                                   RTE_LEN2MASK(3, uint8_t));
8476                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8477                             veb->bw_info.bw_ets_share_credits[i]);
8478                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8479                             veb->bw_info.bw_ets_credits[i]);
8480                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8481                             veb->bw_info.bw_ets_max[i]);
8482         }
8483
8484         veb->enabled_tc = tc_map;
8485
8486         return ret;
8487 }
8488
8489
8490 /*
8491  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8492  * @vsi: VSI to be configured
8493  * @tc_map: enabled TC bitmap
8494  *
8495  * Returns 0 on success, negative value on failure
8496  */
8497 static enum i40e_status_code
8498 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8499 {
8500         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8501         struct i40e_vsi_context ctxt;
8502         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8503         enum i40e_status_code ret = I40E_SUCCESS;
8504         int i;
8505
8506         /* Check if enabled_tc is same as existing or new TCs */
8507         if (vsi->enabled_tc == tc_map)
8508                 return ret;
8509
8510         /* configure tc bandwidth */
8511         memset(&bw_data, 0, sizeof(bw_data));
8512         bw_data.tc_valid_bits = tc_map;
8513         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8514         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8515                 if (tc_map & BIT_ULL(i))
8516                         bw_data.tc_bw_credits[i] = 1;
8517         }
8518         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8519         if (ret) {
8520                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8521                         " per TC failed = %d",
8522                         hw->aq.asq_last_status);
8523                 goto out;
8524         }
8525         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8526                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8527
8528         /* Update Queue Pairs Mapping for currently enabled UPs */
8529         ctxt.seid = vsi->seid;
8530         ctxt.pf_num = hw->pf_id;
8531         ctxt.vf_num = 0;
8532         ctxt.uplink_seid = vsi->uplink_seid;
8533         ctxt.info = vsi->info;
8534         i40e_get_cap(hw);
8535         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8536         if (ret)
8537                 goto out;
8538
8539         /* Update the VSI after updating the VSI queue-mapping information */
8540         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8541         if (ret) {
8542                 PMD_INIT_LOG(ERR, "Failed to configure "
8543                             "TC queue mapping = %d",
8544                             hw->aq.asq_last_status);
8545                 goto out;
8546         }
8547         /* update the local VSI info with updated queue map */
8548         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8549                                         sizeof(vsi->info.tc_mapping));
8550         (void)rte_memcpy(&vsi->info.queue_mapping,
8551                         &ctxt.info.queue_mapping,
8552                 sizeof(vsi->info.queue_mapping));
8553         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8554         vsi->info.valid_sections = 0;
8555
8556         /* query and update current VSI BW information */
8557         ret = i40e_vsi_get_bw_config(vsi);
8558         if (ret) {
8559                 PMD_INIT_LOG(ERR,
8560                          "Failed updating vsi bw info, err %s aq_err %s",
8561                          i40e_stat_str(hw, ret),
8562                          i40e_aq_str(hw, hw->aq.asq_last_status));
8563                 goto out;
8564         }
8565
8566         vsi->enabled_tc = tc_map;
8567
8568 out:
8569         return ret;
8570 }
8571
8572 /*
8573  * i40e_dcb_hw_configure - program the dcb setting to hw
8574  * @pf: pf the configuration is taken on
8575  * @new_cfg: new configuration
8576  * @tc_map: enabled TC bitmap
8577  *
8578  * Returns 0 on success, negative value on failure
8579  */
8580 static enum i40e_status_code
8581 i40e_dcb_hw_configure(struct i40e_pf *pf,
8582                       struct i40e_dcbx_config *new_cfg,
8583                       uint8_t tc_map)
8584 {
8585         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8586         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8587         struct i40e_vsi *main_vsi = pf->main_vsi;
8588         struct i40e_vsi_list *vsi_list;
8589         enum i40e_status_code ret;
8590         int i;
8591         uint32_t val;
8592
8593         /* Use the FW API if FW > v4.4*/
8594         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8595               (hw->aq.fw_maj_ver >= 5))) {
8596                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8597                                   " to configure DCB");
8598                 return I40E_ERR_FIRMWARE_API_VERSION;
8599         }
8600
8601         /* Check if need reconfiguration */
8602         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8603                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8604                 return I40E_SUCCESS;
8605         }
8606
8607         /* Copy the new config to the current config */
8608         *old_cfg = *new_cfg;
8609         old_cfg->etsrec = old_cfg->etscfg;
8610         ret = i40e_set_dcb_config(hw);
8611         if (ret) {
8612                 PMD_INIT_LOG(ERR,
8613                          "Set DCB Config failed, err %s aq_err %s\n",
8614                          i40e_stat_str(hw, ret),
8615                          i40e_aq_str(hw, hw->aq.asq_last_status));
8616                 return ret;
8617         }
8618         /* set receive Arbiter to RR mode and ETS scheme by default */
8619         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8620                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8621                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8622                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8623                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8624                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8625                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8626                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8627                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8628                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8629                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8630                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8631                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8632         }
8633         /* get local mib to check whether it is configured correctly */
8634         /* IEEE mode */
8635         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8636         /* Get Local DCB Config */
8637         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8638                                      &hw->local_dcbx_config);
8639
8640         /* if Veb is created, need to update TC of it at first */
8641         if (main_vsi->veb) {
8642                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8643                 if (ret)
8644                         PMD_INIT_LOG(WARNING,
8645                                  "Failed configuring TC for VEB seid=%d\n",
8646                                  main_vsi->veb->seid);
8647         }
8648         /* Update each VSI */
8649         i40e_vsi_config_tc(main_vsi, tc_map);
8650         if (main_vsi->veb) {
8651                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8652                         /* Beside main VSI and VMDQ VSIs, only enable default
8653                          * TC for other VSIs
8654                          */
8655                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8656                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8657                                                          tc_map);
8658                         else
8659                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8660                                                          I40E_DEFAULT_TCMAP);
8661                         if (ret)
8662                                 PMD_INIT_LOG(WARNING,
8663                                          "Failed configuring TC for VSI seid=%d\n",
8664                                          vsi_list->vsi->seid);
8665                         /* continue */
8666                 }
8667         }
8668         return I40E_SUCCESS;
8669 }
8670
8671 /*
8672  * i40e_dcb_init_configure - initial dcb config
8673  * @dev: device being configured
8674  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8675  *
8676  * Returns 0 on success, negative value on failure
8677  */
8678 static int
8679 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8680 {
8681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8682         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8683         int ret = 0;
8684
8685         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8686                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8687                 return -ENOTSUP;
8688         }
8689
8690         /* DCB initialization:
8691          * Update DCB configuration from the Firmware and configure
8692          * LLDP MIB change event.
8693          */
8694         if (sw_dcb == TRUE) {
8695                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8696                 if (ret != I40E_SUCCESS)
8697                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8698
8699                 ret = i40e_init_dcb(hw);
8700                 /* if sw_dcb, lldp agent is stopped, the return from
8701                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8702                  * adminq status.
8703                  */
8704                 if (ret != I40E_SUCCESS &&
8705                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8706                         memset(&hw->local_dcbx_config, 0,
8707                                 sizeof(struct i40e_dcbx_config));
8708                         /* set dcb default configuration */
8709                         hw->local_dcbx_config.etscfg.willing = 0;
8710                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8711                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8712                         hw->local_dcbx_config.etscfg.tsatable[0] =
8713                                                 I40E_IEEE_TSA_ETS;
8714                         hw->local_dcbx_config.etsrec =
8715                                 hw->local_dcbx_config.etscfg;
8716                         hw->local_dcbx_config.pfc.willing = 0;
8717                         hw->local_dcbx_config.pfc.pfccap =
8718                                                 I40E_MAX_TRAFFIC_CLASS;
8719                         /* FW needs one App to configure HW */
8720                         hw->local_dcbx_config.numapps = 1;
8721                         hw->local_dcbx_config.app[0].selector =
8722                                                 I40E_APP_SEL_ETHTYPE;
8723                         hw->local_dcbx_config.app[0].priority = 3;
8724                         hw->local_dcbx_config.app[0].protocolid =
8725                                                 I40E_APP_PROTOID_FCOE;
8726                         ret = i40e_set_dcb_config(hw);
8727                         if (ret) {
8728                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8729                                         " err = %d, aq_err = %d.", ret,
8730                                           hw->aq.asq_last_status);
8731                                 return -ENOSYS;
8732                         }
8733                 } else {
8734                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8735                                           " aq_err = %d.", ret,
8736                                           hw->aq.asq_last_status);
8737                         return -ENOTSUP;
8738                 }
8739         } else {
8740                 ret = i40e_aq_start_lldp(hw, NULL);
8741                 if (ret != I40E_SUCCESS)
8742                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8743
8744                 ret = i40e_init_dcb(hw);
8745                 if (!ret) {
8746                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8747                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8748                                                   " DCBX offload.");
8749                                 return -ENOTSUP;
8750                         }
8751                 } else {
8752                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8753                                           " aq_err = %d.", ret,
8754                                           hw->aq.asq_last_status);
8755                         return -ENOTSUP;
8756                 }
8757         }
8758         return 0;
8759 }
8760
8761 /*
8762  * i40e_dcb_setup - setup dcb related config
8763  * @dev: device being configured
8764  *
8765  * Returns 0 on success, negative value on failure
8766  */
8767 static int
8768 i40e_dcb_setup(struct rte_eth_dev *dev)
8769 {
8770         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8771         struct i40e_dcbx_config dcb_cfg;
8772         uint8_t tc_map = 0;
8773         int ret = 0;
8774
8775         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8776                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8777                 return -ENOTSUP;
8778         }
8779
8780         if (pf->vf_num != 0)
8781                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8782
8783         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8784         if (ret) {
8785                 PMD_INIT_LOG(ERR, "invalid dcb config");
8786                 return -EINVAL;
8787         }
8788         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8789         if (ret) {
8790                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8791                 return -ENOSYS;
8792         }
8793
8794         return 0;
8795 }
8796
8797 static int
8798 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8799                       struct rte_eth_dcb_info *dcb_info)
8800 {
8801         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8802         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8803         struct i40e_vsi *vsi = pf->main_vsi;
8804         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8805         uint16_t bsf, tc_mapping;
8806         int i, j;
8807
8808         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8809                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8810         else
8811                 dcb_info->nb_tcs = 1;
8812         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8813                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8814         for (i = 0; i < dcb_info->nb_tcs; i++)
8815                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8816
8817         j = 0;
8818         do {
8819                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8820                         if (!(vsi->enabled_tc & (1 << i)))
8821                                 continue;
8822                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8823                         /* only main vsi support multi TCs */
8824                         dcb_info->tc_queue.tc_rxq[j][i].base =
8825                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8826                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8827                         dcb_info->tc_queue.tc_txq[j][i].base =
8828                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8829                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8830                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8831                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8832                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8833                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8834                 }
8835                 vsi = pf->vmdq[j].vsi;
8836                 j++;
8837         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8838         return 0;
8839 }
8840
8841 static int
8842 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8843 {
8844         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8845         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8846         uint16_t interval =
8847                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8848         uint16_t msix_intr;
8849
8850         msix_intr = intr_handle->intr_vec[queue_id];
8851         if (msix_intr == I40E_MISC_VEC_ID)
8852                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8853                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8854                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8855                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8856                                (interval <<
8857                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8858         else
8859                 I40E_WRITE_REG(hw,
8860                                I40E_PFINT_DYN_CTLN(msix_intr -
8861                                                    I40E_RX_VEC_START),
8862                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8863                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8864                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8865                                (interval <<
8866                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8867
8868         I40E_WRITE_FLUSH(hw);
8869         rte_intr_enable(&dev->pci_dev->intr_handle);
8870
8871         return 0;
8872 }
8873
8874 static int
8875 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8876 {
8877         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8879         uint16_t msix_intr;
8880
8881         msix_intr = intr_handle->intr_vec[queue_id];
8882         if (msix_intr == I40E_MISC_VEC_ID)
8883                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8884         else
8885                 I40E_WRITE_REG(hw,
8886                                I40E_PFINT_DYN_CTLN(msix_intr -
8887                                                    I40E_RX_VEC_START),
8888                                0);
8889         I40E_WRITE_FLUSH(hw);
8890
8891         return 0;
8892 }