drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "base/i40e_dcb.h"
  60 #include "i40e_ethdev.h"
  61 #include "i40e_rxtx.h"
  62 #include "i40e_pf.h"
  63
  64 /* Maximun number of MAC addresses */
  65 #define I40E_NUM_MACADDR_MAX       64
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 /* Default queue interrupt throttling time in microseconds */
  79 #define I40E_ITR_INDEX_DEFAULT          0
  80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  81 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA  0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 143 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 144 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 145 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 146 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 147 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 148
 149 #define I40E_INSET_NONE            0x00000000000000000ULL
 150
 151 /* bit0 ~ bit 7 */
 152 #define I40E_INSET_DMAC            0x0000000000000001ULL
 153 #define I40E_INSET_SMAC            0x0000000000000002ULL
 154 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 155 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 156 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 157
 158 /* bit 8 ~ bit 15 */
 159 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 160 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 161 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 162 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 163 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 164 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 165 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 166
 167 /* bit 16 ~ bit 31 */
 168 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 169 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 170 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 171 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 172 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 173 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 174 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 175 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 176
 177 /* bit 32 ~ bit 47, tunnel fields */
 178 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 179 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 180 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 181 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 182 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 183 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 184
 185 /* bit 48 ~ bit 55 */
 186 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 187
 188 /* bit 56 ~ bit 63, Flex Payload */
 189 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 194 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 195 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 196 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 197 #define I40E_INSET_FLEX_PAYLOAD \
 198         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 199         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 200         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 201         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 202
 203 /**
 204  * Below are values for writing un-exposed registers suggested
 205  * by silicon experts
 206  */
 207 /* Destination MAC address */
 208 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 209 /* Source MAC address */
 210 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 211 /* VLAN tag in the outer L2 header */
 212 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 213 /* VLAN tag in the inner L2 header */
 214 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 215 /* Source IPv4 address */
 216 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 217 /* Destination IPv4 address */
 218 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 219 /* IPv4 Type of Service (TOS) */
 220 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 221 /* IPv4 Protocol */
 222 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 223 /* Source IPv6 address */
 224 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 225 /* Destination IPv6 address */
 226 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 227 /* IPv6 Traffic Class (TC) */
 228 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 229 /* IPv6 Next Header */
 230 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 231 /* Source L4 port */
 232 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 233 /* Destination L4 port */
 234 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 235 /* SCTP verification tag */
 236 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 237 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 238 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 239 /* Source port of tunneling UDP */
 240 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 241 /* Destination port of tunneling UDP */
 242 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 243 /* UDP Tunneling ID, NVGRE/GRE key */
 244 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 245 /* Last ether type */
 246 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 247 /* Tunneling outer destination IPv4 address */
 248 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 249 /* Tunneling outer destination IPv6 address */
 250 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 251 /* 1st word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 253 /* 2nd word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 255 /* 3rd word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 257 /* 4th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 259 /* 5th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 261 /* 6th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 263 /* 7th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 265 /* 8th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 267
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 274 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 275 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 276 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 277
 278 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 279 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 280 static int i40e_dev_configure(struct rte_eth_dev *dev);
 281 static int i40e_dev_start(struct rte_eth_dev *dev);
 282 static void i40e_dev_stop(struct rte_eth_dev *dev);
 283 static void i40e_dev_close(struct rte_eth_dev *dev);
 284 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 285 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 286 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 287 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 288 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 289 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 290 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 291                                struct rte_eth_stats *stats);
 292 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 293                                struct rte_eth_xstats *xstats, unsigned n);
 294 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 295 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
 296 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 297                                             uint16_t queue_id,
 298                                             uint8_t stat_idx,
 299                                             uint8_t is_rx);
 300 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 301                               struct rte_eth_dev_info *dev_info);
 302 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 303                                 uint16_t vlan_id,
 304                                 int on);
 305 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 306 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 307 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 308                                       uint16_t queue,
 309                                       int on);
 310 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 311 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 312 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 313 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 314                               struct rte_eth_fc_conf *fc_conf);
 315 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 316                               struct rte_eth_fc_conf *fc_conf);
 317 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 318                                        struct rte_eth_pfc_conf *pfc_conf);
 319 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 320                           struct ether_addr *mac_addr,
 321                           uint32_t index,
 322                           uint32_t pool);
 323 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 324 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 325                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 326                                     uint16_t reta_size);
 327 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 328                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 329                                    uint16_t reta_size);
 330
 331 static int i40e_get_cap(struct i40e_hw *hw);
 332 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 333 static int i40e_pf_setup(struct i40e_pf *pf);
 334 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 335 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 336 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 337 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 338 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 339                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 340 static void i40e_stat_update_48(struct i40e_hw *hw,
 341                                uint32_t hireg,
 342                                uint32_t loreg,
 343                                bool offset_loaded,
 344                                uint64_t *offset,
 345                                uint64_t *stat);
 346 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 347 static void i40e_dev_interrupt_handler(
 348                 __rte_unused struct rte_intr_handle *handle, void *param);
 349 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 350                                 uint32_t base, uint32_t num);
 351 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 352 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 353                         uint32_t base);
 354 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 355                         uint16_t num);
 356 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 357 static int i40e_veb_release(struct i40e_veb *veb);
 358 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 359                                                 struct i40e_vsi *vsi);
 360 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 361 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 362 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 363                                              struct i40e_macvlan_filter *mv_f,
 364                                              int num,
 365                                              struct ether_addr *addr);
 366 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 367                                              struct i40e_macvlan_filter *mv_f,
 368                                              int num,
 369                                              uint16_t vlan);
 370 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 371 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 372                                     struct rte_eth_rss_conf *rss_conf);
 373 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 374                                       struct rte_eth_rss_conf *rss_conf);
 375 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 376                                 struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 378                                 struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 380                         struct rte_eth_ethertype_filter *filter,
 381                         bool add);
 382 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 383                                 enum rte_filter_op filter_op,
 384                                 void *arg);
 385 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 386                                 enum rte_filter_type filter_type,
 387                                 enum rte_filter_op filter_op,
 388                                 void *arg);
 389 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 390                                   struct rte_eth_dcb_info *dcb_info);
 391 static void i40e_configure_registers(struct i40e_hw *hw);
 392 static void i40e_hw_init(struct i40e_hw *hw);
 393 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 394 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 395                         struct rte_eth_mirror_conf *mirror_conf,
 396                         uint8_t sw_id, uint8_t on);
 397 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 398
 399 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 400 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 401 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 402                                            struct timespec *timestamp,
 403                                            uint32_t flags);
 404 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 405                                            struct timespec *timestamp);
 406 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 407
 408
 409 static const struct rte_pci_id pci_id_i40e_map[] = {
 410 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 411 #include "rte_pci_dev_ids.h"
 412 { .vendor_id = 0, /* sentinel */ },
 413 };
 414
 415 static const struct eth_dev_ops i40e_eth_dev_ops = {
 416         .dev_configure                = i40e_dev_configure,
 417         .dev_start                    = i40e_dev_start,
 418         .dev_stop                     = i40e_dev_stop,
 419         .dev_close                    = i40e_dev_close,
 420         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 421         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 422         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 423         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 424         .dev_set_link_up              = i40e_dev_set_link_up,
 425         .dev_set_link_down            = i40e_dev_set_link_down,
 426         .link_update                  = i40e_dev_link_update,
 427         .stats_get                    = i40e_dev_stats_get,
 428         .xstats_get                   = i40e_dev_xstats_get,
 429         .stats_reset                  = i40e_dev_stats_reset,
 430         .xstats_reset                 = i40e_dev_xstats_reset,
 431         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 432         .dev_infos_get                = i40e_dev_info_get,
 433         .vlan_filter_set              = i40e_vlan_filter_set,
 434         .vlan_tpid_set                = i40e_vlan_tpid_set,
 435         .vlan_offload_set             = i40e_vlan_offload_set,
 436         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 437         .vlan_pvid_set                = i40e_vlan_pvid_set,
 438         .rx_queue_start               = i40e_dev_rx_queue_start,
 439         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 440         .tx_queue_start               = i40e_dev_tx_queue_start,
 441         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 442         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 443         .rx_queue_release             = i40e_dev_rx_queue_release,
 444         .rx_queue_count               = i40e_dev_rx_queue_count,
 445         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 446         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 447         .tx_queue_release             = i40e_dev_tx_queue_release,
 448         .dev_led_on                   = i40e_dev_led_on,
 449         .dev_led_off                  = i40e_dev_led_off,
 450         .flow_ctrl_get                = i40e_flow_ctrl_get,
 451         .flow_ctrl_set                = i40e_flow_ctrl_set,
 452         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 453         .mac_addr_add                 = i40e_macaddr_add,
 454         .mac_addr_remove              = i40e_macaddr_remove,
 455         .reta_update                  = i40e_dev_rss_reta_update,
 456         .reta_query                   = i40e_dev_rss_reta_query,
 457         .rss_hash_update              = i40e_dev_rss_hash_update,
 458         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 459         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 460         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 461         .filter_ctrl                  = i40e_dev_filter_ctrl,
 462         .rxq_info_get                 = i40e_rxq_info_get,
 463         .txq_info_get                 = i40e_txq_info_get,
 464         .mirror_rule_set              = i40e_mirror_rule_set,
 465         .mirror_rule_reset            = i40e_mirror_rule_reset,
 466         .timesync_enable              = i40e_timesync_enable,
 467         .timesync_disable             = i40e_timesync_disable,
 468         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 469         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 470         .get_dcb_info                 = i40e_dev_get_dcb_info,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_i40e_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 480         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 481         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 482         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 483         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 484         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 485                 rx_unknown_protocol)},
 486         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 487         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 488         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 489         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 490 };
 491
 492 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 493         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 494                 tx_dropped_link_down)},
 495         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 496         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 497                 illegal_bytes)},
 498         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 499         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 500                 mac_local_faults)},
 501         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 502                 mac_remote_faults)},
 503         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 504                 rx_length_errors)},
 505         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 506         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 507         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 508         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 509         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 510         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 511                 rx_size_127)},
 512         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 513                 rx_size_255)},
 514         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 515                 rx_size_511)},
 516         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 517                 rx_size_1023)},
 518         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 519                 rx_size_1522)},
 520         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 521                 rx_size_big)},
 522         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 523                 rx_undersize)},
 524         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 525                 rx_oversize)},
 526         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 527                 mac_short_packet_dropped)},
 528         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 529                 rx_fragments)},
 530         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 531         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 532         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 533                 tx_size_127)},
 534         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 535                 tx_size_255)},
 536         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 537                 tx_size_511)},
 538         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 539                 tx_size_1023)},
 540         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 541                 tx_size_1522)},
 542         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 543                 tx_size_big)},
 544         {"rx_flow_director_atr_match_packets",
 545                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 546         {"rx_flow_director_sb_match_packets",
 547                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 548         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 549                 tx_lpi_status)},
 550         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 551                 rx_lpi_status)},
 552         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 553                 tx_lpi_count)},
 554         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 555                 rx_lpi_count)},
 556 };
 557
 558 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
 559 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
 560
 561 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 562                 sizeof(rte_i40e_stats_strings[0]))
 563 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 564                 sizeof(rte_i40e_hw_port_strings[0]))
 565 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
 566                 I40E_NB_HW_PORT_Q_STATS)
 567
 568 static struct eth_driver rte_i40e_pmd = {
 569         .pci_drv = {
 570                 .name = "rte_i40e_pmd",
 571                 .id_table = pci_id_i40e_map,
 572                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 573                         RTE_PCI_DRV_DETACHABLE,
 574         },
 575         .eth_dev_init = eth_i40e_dev_init,
 576         .eth_dev_uninit = eth_i40e_dev_uninit,
 577         .dev_private_size = sizeof(struct i40e_adapter),
 578 };
 579
 580 static inline int
 581 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 582                                      struct rte_eth_link *link)
 583 {
 584         struct rte_eth_link *dst = link;
 585         struct rte_eth_link *src = &(dev->data->dev_link);
 586
 587         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 588                                         *(uint64_t *)src) == 0)
 589                 return -1;
 590
 591         return 0;
 592 }
 593
 594 static inline int
 595 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 596                                       struct rte_eth_link *link)
 597 {
 598         struct rte_eth_link *dst = &(dev->data->dev_link);
 599         struct rte_eth_link *src = link;
 600
 601         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 602                                         *(uint64_t *)src) == 0)
 603                 return -1;
 604
 605         return 0;
 606 }
 607
 608 /*
 609  * Driver initialization routine.
 610  * Invoked once at EAL init time.
 611  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 612  */
 613 static int
 614 rte_i40e_pmd_init(const char *name __rte_unused,
 615                   const char *params __rte_unused)
 616 {
 617         PMD_INIT_FUNC_TRACE();
 618         rte_eth_driver_register(&rte_i40e_pmd);
 619
 620         return 0;
 621 }
 622
 623 static struct rte_driver rte_i40e_driver = {
 624         .type = PMD_PDEV,
 625         .init = rte_i40e_pmd_init,
 626 };
 627
 628 PMD_REGISTER_DRIVER(rte_i40e_driver);
 629
 630 /*
 631  * Initialize registers for flexible payload, which should be set by NVM.
 632  * This should be removed from code once it is fixed in NVM.
 633  */
 634 #ifndef I40E_GLQF_ORT
 635 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 636 #endif
 637 #ifndef I40E_GLQF_PIT
 638 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 639 #endif
 640
 641 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 642 {
 643         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 644         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 645         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 646         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 647         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 648         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 649         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 650         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 651         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 652         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 653
 654         /* GLQF_PIT Registers */
 655         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 656         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 657 }
 658
 659 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 660
 661 /*
 662  * Add a ethertype filter to drop all flow control frames transmitted
 663  * from VSIs.
 664 */
 665 static void
 666 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 667 {
 668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 669         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 670                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 671                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 672         int ret;
 673
 674         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 675                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 676                                 pf->main_vsi_seid, 0,
 677                                 TRUE, NULL, NULL);
 678         if (ret)
 679                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 680                                   " frames from VSIs.");
 681 }
 682
 683 static int
 684 eth_i40e_dev_init(struct rte_eth_dev *dev)
 685 {
 686         struct rte_pci_device *pci_dev;
 687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 689         struct i40e_vsi *vsi;
 690         int ret;
 691         uint32_t len;
 692         uint8_t aq_fail = 0;
 693
 694         PMD_INIT_FUNC_TRACE();
 695
 696         dev->dev_ops = &i40e_eth_dev_ops;
 697         dev->rx_pkt_burst = i40e_recv_pkts;
 698         dev->tx_pkt_burst = i40e_xmit_pkts;
 699
 700         /* for secondary processes, we don't initialise any further as primary
 701          * has already done this work. Only check we don't need a different
 702          * RX function */
 703         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 704                 i40e_set_rx_function(dev);
 705                 i40e_set_tx_function(dev);
 706                 return 0;
 707         }
 708         pci_dev = dev->pci_dev;
 709
 710         rte_eth_copy_pci_info(dev, pci_dev);
 711
 712         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 713         pf->adapter->eth_dev = dev;
 714         pf->dev_data = dev->data;
 715
 716         hw->back = I40E_PF_TO_ADAPTER(pf);
 717         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 718         if (!hw->hw_addr) {
 719                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 720                              "as address is NULL");
 721                 return -ENODEV;
 722         }
 723
 724         hw->vendor_id = pci_dev->id.vendor_id;
 725         hw->device_id = pci_dev->id.device_id;
 726         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 727         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 728         hw->bus.device = pci_dev->addr.devid;
 729         hw->bus.func = pci_dev->addr.function;
 730         hw->adapter_stopped = 0;
 731
 732         /* Make sure all is clean before doing PF reset */
 733         i40e_clear_hw(hw);
 734
 735         /* Initialize the hardware */
 736         i40e_hw_init(hw);
 737
 738         /* Reset here to make sure all is clean for each PF */
 739         ret = i40e_pf_reset(hw);
 740         if (ret) {
 741                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 742                 return ret;
 743         }
 744
 745         /* Initialize the shared code (base driver) */
 746         ret = i40e_init_shared_code(hw);
 747         if (ret) {
 748                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 749                 return ret;
 750         }
 751
 752         /*
 753          * To work around the NVM issue,initialize registers
 754          * for flexible payload by software.
 755          * It should be removed once issues are fixed in NVM.
 756          */
 757         i40e_flex_payload_reg_init(hw);
 758
 759         /* Initialize the parameters for adminq */
 760         i40e_init_adminq_parameter(hw);
 761         ret = i40e_init_adminq(hw);
 762         if (ret != I40E_SUCCESS) {
 763                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 764                 return -EIO;
 765         }
 766         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 767                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 768                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 769                      ((hw->nvm.version >> 12) & 0xf),
 770                      ((hw->nvm.version >> 4) & 0xff),
 771                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 772
 773         /* Clear PXE mode */
 774         i40e_clear_pxe_mode(hw);
 775
 776         /*
 777          * On X710, performance number is far from the expectation on recent
 778          * firmware versions. The fix for this issue may not be integrated in
 779          * the following firmware version. So the workaround in software driver
 780          * is needed. It needs to modify the initial values of 3 internal only
 781          * registers. Note that the workaround can be removed when it is fixed
 782          * in firmware in the future.
 783          */
 784         i40e_configure_registers(hw);
 785
 786         /* Get hw capabilities */
 787         ret = i40e_get_cap(hw);
 788         if (ret != I40E_SUCCESS) {
 789                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 790                 goto err_get_capabilities;
 791         }
 792
 793         /* Initialize parameters for PF */
 794         ret = i40e_pf_parameter_init(dev);
 795         if (ret != 0) {
 796                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 797                 goto err_parameter_init;
 798         }
 799
 800         /* Initialize the queue management */
 801         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 802         if (ret < 0) {
 803                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 804                 goto err_qp_pool_init;
 805         }
 806         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 807                                 hw->func_caps.num_msix_vectors - 1);
 808         if (ret < 0) {
 809                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 810                 goto err_msix_pool_init;
 811         }
 812
 813         /* Initialize lan hmc */
 814         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 815                                 hw->func_caps.num_rx_qp, 0, 0);
 816         if (ret != I40E_SUCCESS) {
 817                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 818                 goto err_init_lan_hmc;
 819         }
 820
 821         /* Configure lan hmc */
 822         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 823         if (ret != I40E_SUCCESS) {
 824                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 825                 goto err_configure_lan_hmc;
 826         }
 827
 828         /* Get and check the mac address */
 829         i40e_get_mac_addr(hw, hw->mac.addr);
 830         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 831                 PMD_INIT_LOG(ERR, "mac address is not valid");
 832                 ret = -EIO;
 833                 goto err_get_mac_addr;
 834         }
 835         /* Copy the permanent MAC address */
 836         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 837                         (struct ether_addr *) hw->mac.perm_addr);
 838
 839         /* Disable flow control */
 840         hw->fc.requested_mode = I40E_FC_NONE;
 841         i40e_set_fc(hw, &aq_fail, TRUE);
 842
 843         /* PF setup, which includes VSI setup */
 844         ret = i40e_pf_setup(pf);
 845         if (ret) {
 846                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 847                 goto err_setup_pf_switch;
 848         }
 849
 850         vsi = pf->main_vsi;
 851
 852         /* Disable double vlan by default */
 853         i40e_vsi_config_double_vlan(vsi, FALSE);
 854
 855         if (!vsi->max_macaddrs)
 856                 len = ETHER_ADDR_LEN;
 857         else
 858                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 859
 860         /* Should be after VSI initialized */
 861         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 862         if (!dev->data->mac_addrs) {
 863                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 864                                         "for storing mac address");
 865                 goto err_mac_alloc;
 866         }
 867         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 868                                         &dev->data->mac_addrs[0]);
 869
 870         /* initialize pf host driver to setup SRIOV resource if applicable */
 871         i40e_pf_host_init(dev);
 872
 873         /* register callback func to eal lib */
 874         rte_intr_callback_register(&(pci_dev->intr_handle),
 875                 i40e_dev_interrupt_handler, (void *)dev);
 876
 877         /* configure and enable device interrupt */
 878         i40e_pf_config_irq0(hw);
 879         i40e_pf_enable_irq0(hw);
 880
 881         /* enable uio intr after callback register */
 882         rte_intr_enable(&(pci_dev->intr_handle));
 883         /*
 884          * Add an ethertype filter to drop all flow control frames transmitted
 885          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 886          * frames to wire.
 887          */
 888         i40e_add_tx_flow_control_drop_filter(pf);
 889
 890         /* initialize mirror rule list */
 891         TAILQ_INIT(&pf->mirror_list);
 892
 893         /* Init dcb to sw mode by default */
 894         ret = i40e_dcb_init_configure(dev, TRUE);
 895         if (ret != I40E_SUCCESS) {
 896                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 897                 pf->flags &= ~I40E_FLAG_DCB;
 898         }
 899
 900         return 0;
 901
 902 err_mac_alloc:
 903         i40e_vsi_release(pf->main_vsi);
 904 err_setup_pf_switch:
 905 err_get_mac_addr:
 906 err_configure_lan_hmc:
 907         (void)i40e_shutdown_lan_hmc(hw);
 908 err_init_lan_hmc:
 909         i40e_res_pool_destroy(&pf->msix_pool);
 910 err_msix_pool_init:
 911         i40e_res_pool_destroy(&pf->qp_pool);
 912 err_qp_pool_init:
 913 err_parameter_init:
 914 err_get_capabilities:
 915         (void)i40e_shutdown_adminq(hw);
 916
 917         return ret;
 918 }
 919
 920 static int
 921 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 922 {
 923         struct rte_pci_device *pci_dev;
 924         struct i40e_hw *hw;
 925         struct i40e_filter_control_settings settings;
 926         int ret;
 927         uint8_t aq_fail = 0;
 928
 929         PMD_INIT_FUNC_TRACE();
 930
 931         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 932                 return 0;
 933
 934         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 935         pci_dev = dev->pci_dev;
 936
 937         if (hw->adapter_stopped == 0)
 938                 i40e_dev_close(dev);
 939
 940         dev->dev_ops = NULL;
 941         dev->rx_pkt_burst = NULL;
 942         dev->tx_pkt_burst = NULL;
 943
 944         /* Disable LLDP */
 945         ret = i40e_aq_stop_lldp(hw, true, NULL);
 946         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 947                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 948
 949         /* Clear PXE mode */
 950         i40e_clear_pxe_mode(hw);
 951
 952         /* Unconfigure filter control */
 953         memset(&settings, 0, sizeof(settings));
 954         ret = i40e_set_filter_control(hw, &settings);
 955         if (ret)
 956                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 957                                         ret);
 958
 959         /* Disable flow control */
 960         hw->fc.requested_mode = I40E_FC_NONE;
 961         i40e_set_fc(hw, &aq_fail, TRUE);
 962
 963         /* uninitialize pf host driver */
 964         i40e_pf_host_uninit(dev);
 965
 966         rte_free(dev->data->mac_addrs);
 967         dev->data->mac_addrs = NULL;
 968
 969         /* disable uio intr before callback unregister */
 970         rte_intr_disable(&(pci_dev->intr_handle));
 971
 972         /* register callback func to eal lib */
 973         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 974                 i40e_dev_interrupt_handler, (void *)dev);
 975
 976         return 0;
 977 }
 978
 979 static int
 980 i40e_dev_configure(struct rte_eth_dev *dev)
 981 {
 982         struct i40e_adapter *ad =
 983                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 984         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 985         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 986         int i, ret;
 987
 988         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 989          * bulk allocation or vector Rx preconditions we will reset it.
 990          */
 991         ad->rx_bulk_alloc_allowed = true;
 992         ad->rx_vec_allowed = true;
 993         ad->tx_simple_allowed = true;
 994         ad->tx_vec_allowed = true;
 995
 996         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 997                 ret = i40e_fdir_setup(pf);
 998                 if (ret != I40E_SUCCESS) {
 999                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1000                         return -ENOTSUP;
1001                 }
1002                 ret = i40e_fdir_configure(dev);
1003                 if (ret < 0) {
1004                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1005                         goto err;
1006                 }
1007         } else
1008                 i40e_fdir_teardown(pf);
1009
1010         ret = i40e_dev_init_vlan(dev);
1011         if (ret < 0)
1012                 goto err;
1013
1014         /* VMDQ setup.
1015          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1016          *  RSS setting have different requirements.
1017          *  General PMD driver call sequence are NIC init, configure,
1018          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1019          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1020          *  applicable. So, VMDQ setting has to be done before
1021          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1022          *  For RSS setting, it will try to calculate actual configured RX queue
1023          *  number, which will be available after rx_queue_setup(). dev_start()
1024          *  function is good to place RSS setup.
1025          */
1026         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1027                 ret = i40e_vmdq_setup(dev);
1028                 if (ret)
1029                         goto err;
1030         }
1031
1032         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1033                 ret = i40e_dcb_setup(dev);
1034                 if (ret) {
1035                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1036                         goto err_dcb;
1037                 }
1038         }
1039
1040         return 0;
1041
1042 err_dcb:
1043         /* need to release vmdq resource if exists */
1044         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1045                 i40e_vsi_release(pf->vmdq[i].vsi);
1046                 pf->vmdq[i].vsi = NULL;
1047         }
1048         rte_free(pf->vmdq);
1049         pf->vmdq = NULL;
1050 err:
1051         /* need to release fdir resource if exists */
1052         i40e_fdir_teardown(pf);
1053         return ret;
1054 }
1055
1056 void
1057 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1058 {
1059         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1060         uint16_t msix_vect = vsi->msix_intr;
1061         uint16_t i;
1062
1063         for (i = 0; i < vsi->nb_qps; i++) {
1064                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1065                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1066                 rte_wmb();
1067         }
1068
1069         if (vsi->type != I40E_VSI_SRIOV) {
1070                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
1071                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1072                                 msix_vect - 1), 0);
1073         } else {
1074                 uint32_t reg;
1075                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1076                         vsi->user_param + (msix_vect - 1);
1077
1078                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
1079         }
1080         I40E_WRITE_FLUSH(hw);
1081 }
1082
1083 static inline uint16_t
1084 i40e_calc_itr_interval(int16_t interval)
1085 {
1086         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
1087                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1088
1089         /* Convert to hardware count, as writing each 1 represents 2 us */
1090         return (interval/2);
1091 }
1092
1093 void
1094 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1095 {
1096         uint32_t val;
1097         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1098         uint16_t msix_vect = vsi->msix_intr;
1099         int i;
1100
1101         for (i = 0; i < vsi->nb_qps; i++)
1102                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1103
1104         /* Bind all RX queues to allocated MSIX interrupt */
1105         for (i = 0; i < vsi->nb_qps; i++) {
1106                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1107                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1108                         ((vsi->base_queue + i + 1) <<
1109                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1110                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1111                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1112
1113                 if (i == vsi->nb_qps - 1)
1114                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1115                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
1116         }
1117
1118         /* Write first RX queue to Link list register as the head element */
1119         if (vsi->type != I40E_VSI_SRIOV) {
1120                 uint16_t interval =
1121                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1122
1123                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1124                                                 (vsi->base_queue <<
1125                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1126                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1127
1128                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1129                                                 msix_vect - 1), interval);
1130
1131 #ifndef I40E_GLINT_CTL
1132 #define I40E_GLINT_CTL                     0x0003F800
1133 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
1134 #endif
1135                 /* Disable auto-mask on enabling of all none-zero  interrupt */
1136                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
1137                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
1138         } else {
1139                 uint32_t reg;
1140
1141                 /* num_msix_vectors_vf needs to minus irq0 */
1142                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1143                         vsi->user_param + (msix_vect - 1);
1144
1145                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
1146                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1147                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1148         }
1149
1150         I40E_WRITE_FLUSH(hw);
1151 }
1152
1153 static void
1154 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1155 {
1156         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1157         uint16_t interval = i40e_calc_itr_interval(\
1158                         RTE_LIBRTE_I40E_ITR_INTERVAL);
1159
1160         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
1161                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
1162                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1163                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1164                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1165 }
1166
1167 static void
1168 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1169 {
1170         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1171
1172         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
1173 }
1174
1175 static inline uint8_t
1176 i40e_parse_link_speed(uint16_t eth_link_speed)
1177 {
1178         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1179
1180         switch (eth_link_speed) {
1181         case ETH_LINK_SPEED_40G:
1182                 link_speed = I40E_LINK_SPEED_40GB;
1183                 break;
1184         case ETH_LINK_SPEED_20G:
1185                 link_speed = I40E_LINK_SPEED_20GB;
1186                 break;
1187         case ETH_LINK_SPEED_10G:
1188                 link_speed = I40E_LINK_SPEED_10GB;
1189                 break;
1190         case ETH_LINK_SPEED_1000:
1191                 link_speed = I40E_LINK_SPEED_1GB;
1192                 break;
1193         case ETH_LINK_SPEED_100:
1194                 link_speed = I40E_LINK_SPEED_100MB;
1195                 break;
1196         }
1197
1198         return link_speed;
1199 }
1200
1201 static int
1202 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1203 {
1204         enum i40e_status_code status;
1205         struct i40e_aq_get_phy_abilities_resp phy_ab;
1206         struct i40e_aq_set_phy_config phy_conf;
1207         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1208                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1209                         I40E_AQ_PHY_FLAG_LOW_POWER;
1210         const uint8_t advt = I40E_LINK_SPEED_40GB |
1211                         I40E_LINK_SPEED_10GB |
1212                         I40E_LINK_SPEED_1GB |
1213                         I40E_LINK_SPEED_100MB;
1214         int ret = -ENOTSUP;
1215
1216         /* Skip it on 40G interfaces, as a workaround for the link issue */
1217         if (i40e_is_40G_device(hw->device_id))
1218                 return I40E_SUCCESS;
1219
1220         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1221                                               NULL);
1222         if (status)
1223                 return ret;
1224
1225         memset(&phy_conf, 0, sizeof(phy_conf));
1226
1227         /* bits 0-2 use the values from get_phy_abilities_resp */
1228         abilities &= ~mask;
1229         abilities |= phy_ab.abilities & mask;
1230
1231         /* update ablities and speed */
1232         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1233                 phy_conf.link_speed = advt;
1234         else
1235                 phy_conf.link_speed = force_speed;
1236
1237         phy_conf.abilities = abilities;
1238
1239         /* use get_phy_abilities_resp value for the rest */
1240         phy_conf.phy_type = phy_ab.phy_type;
1241         phy_conf.eee_capability = phy_ab.eee_capability;
1242         phy_conf.eeer = phy_ab.eeer_val;
1243         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1244
1245         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1246                     phy_ab.abilities, phy_ab.link_speed);
1247         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1248                     phy_conf.abilities, phy_conf.link_speed);
1249
1250         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1251         if (status)
1252                 return ret;
1253
1254         return I40E_SUCCESS;
1255 }
1256
1257 static int
1258 i40e_apply_link_speed(struct rte_eth_dev *dev)
1259 {
1260         uint8_t speed;
1261         uint8_t abilities = 0;
1262         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263         struct rte_eth_conf *conf = &dev->data->dev_conf;
1264
1265         speed = i40e_parse_link_speed(conf->link_speed);
1266         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1267         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1268                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1269         else
1270                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1271
1272         return i40e_phy_conf_link(hw, abilities, speed);
1273 }
1274
1275 static int
1276 i40e_dev_start(struct rte_eth_dev *dev)
1277 {
1278         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1279         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280         struct i40e_vsi *main_vsi = pf->main_vsi;
1281         int ret, i;
1282
1283         hw->adapter_stopped = 0;
1284
1285         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1286                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1287                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1288                              dev->data->dev_conf.link_duplex,
1289                              dev->data->port_id);
1290                 return -EINVAL;
1291         }
1292
1293         /* Initialize VSI */
1294         ret = i40e_dev_rxtx_init(pf);
1295         if (ret != I40E_SUCCESS) {
1296                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1297                 goto err_up;
1298         }
1299
1300         /* Map queues with MSIX interrupt */
1301         i40e_vsi_queues_bind_intr(main_vsi);
1302         i40e_vsi_enable_queues_intr(main_vsi);
1303
1304         /* Map VMDQ VSI queues with MSIX interrupt */
1305         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1306                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1307                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1308         }
1309
1310         /* enable FDIR MSIX interrupt */
1311         if (pf->fdir.fdir_vsi) {
1312                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1313                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1314         }
1315
1316         /* Enable all queues which have been configured */
1317         ret = i40e_dev_switch_queues(pf, TRUE);
1318         if (ret != I40E_SUCCESS) {
1319                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1320                 goto err_up;
1321         }
1322
1323         /* Enable receiving broadcast packets */
1324         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1325         if (ret != I40E_SUCCESS)
1326                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1327
1328         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1329                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1330                                                 true, NULL);
1331                 if (ret != I40E_SUCCESS)
1332                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1333         }
1334
1335         /* Apply link configure */
1336         ret = i40e_apply_link_speed(dev);
1337         if (I40E_SUCCESS != ret) {
1338                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1339                 goto err_up;
1340         }
1341
1342         return I40E_SUCCESS;
1343
1344 err_up:
1345         i40e_dev_switch_queues(pf, FALSE);
1346         i40e_dev_clear_queues(dev);
1347
1348         return ret;
1349 }
1350
1351 static void
1352 i40e_dev_stop(struct rte_eth_dev *dev)
1353 {
1354         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1355         struct i40e_vsi *main_vsi = pf->main_vsi;
1356         struct i40e_mirror_rule *p_mirror;
1357         int i;
1358
1359         /* Disable all queues */
1360         i40e_dev_switch_queues(pf, FALSE);
1361
1362         /* un-map queues with interrupt registers */
1363         i40e_vsi_disable_queues_intr(main_vsi);
1364         i40e_vsi_queues_unbind_intr(main_vsi);
1365
1366         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1367                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1368                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1369         }
1370
1371         if (pf->fdir.fdir_vsi) {
1372                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1373                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1374         }
1375         /* Clear all queues and release memory */
1376         i40e_dev_clear_queues(dev);
1377
1378         /* Set link down */
1379         i40e_dev_set_link_down(dev);
1380
1381         /* Remove all mirror rules */
1382         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1383                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1384                 rte_free(p_mirror);
1385         }
1386         pf->nb_mirror_rule = 0;
1387
1388 }
1389
1390 static void
1391 i40e_dev_close(struct rte_eth_dev *dev)
1392 {
1393         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1394         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1395         uint32_t reg;
1396         int i;
1397
1398         PMD_INIT_FUNC_TRACE();
1399
1400         i40e_dev_stop(dev);
1401         hw->adapter_stopped = 1;
1402         i40e_dev_free_queues(dev);
1403
1404         /* Disable interrupt */
1405         i40e_pf_disable_irq0(hw);
1406         rte_intr_disable(&(dev->pci_dev->intr_handle));
1407
1408         /* shutdown and destroy the HMC */
1409         i40e_shutdown_lan_hmc(hw);
1410
1411         /* release all the existing VSIs and VEBs */
1412         i40e_fdir_teardown(pf);
1413         i40e_vsi_release(pf->main_vsi);
1414
1415         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1416                 i40e_vsi_release(pf->vmdq[i].vsi);
1417                 pf->vmdq[i].vsi = NULL;
1418         }
1419
1420         rte_free(pf->vmdq);
1421         pf->vmdq = NULL;
1422
1423         /* shutdown the adminq */
1424         i40e_aq_queue_shutdown(hw, true);
1425         i40e_shutdown_adminq(hw);
1426
1427         i40e_res_pool_destroy(&pf->qp_pool);
1428         i40e_res_pool_destroy(&pf->msix_pool);
1429
1430         /* force a PF reset to clean anything leftover */
1431         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1432         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1433                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1434         I40E_WRITE_FLUSH(hw);
1435 }
1436
1437 static void
1438 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1439 {
1440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1441         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1442         struct i40e_vsi *vsi = pf->main_vsi;
1443         int status;
1444
1445         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1446                                                         true, NULL);
1447         if (status != I40E_SUCCESS)
1448                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1449
1450         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1451                                                         TRUE, NULL);
1452         if (status != I40E_SUCCESS)
1453                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1454
1455 }
1456
1457 static void
1458 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1459 {
1460         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1461         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462         struct i40e_vsi *vsi = pf->main_vsi;
1463         int status;
1464
1465         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1466                                                         false, NULL);
1467         if (status != I40E_SUCCESS)
1468                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1469
1470         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1471                                                         false, NULL);
1472         if (status != I40E_SUCCESS)
1473                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1474 }
1475
1476 static void
1477 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1478 {
1479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1480         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481         struct i40e_vsi *vsi = pf->main_vsi;
1482         int ret;
1483
1484         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1485         if (ret != I40E_SUCCESS)
1486                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1487 }
1488
1489 static void
1490 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1491 {
1492         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1493         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1494         struct i40e_vsi *vsi = pf->main_vsi;
1495         int ret;
1496
1497         if (dev->data->promiscuous == 1)
1498                 return; /* must remain in all_multicast mode */
1499
1500         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1501                                 vsi->seid, FALSE, NULL);
1502         if (ret != I40E_SUCCESS)
1503                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1504 }
1505
1506 /*
1507  * Set device link up.
1508  */
1509 static int
1510 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1511 {
1512         /* re-apply link speed setting */
1513         return i40e_apply_link_speed(dev);
1514 }
1515
1516 /*
1517  * Set device link down.
1518  */
1519 static int
1520 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1521 {
1522         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1523         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1525
1526         return i40e_phy_conf_link(hw, abilities, speed);
1527 }
1528
1529 int
1530 i40e_dev_link_update(struct rte_eth_dev *dev,
1531                      int wait_to_complete)
1532 {
1533 #define CHECK_INTERVAL 100  /* 100ms */
1534 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1535         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536         struct i40e_link_status link_status;
1537         struct rte_eth_link link, old;
1538         int status;
1539         unsigned rep_cnt = MAX_REPEAT_TIME;
1540
1541         memset(&link, 0, sizeof(link));
1542         memset(&old, 0, sizeof(old));
1543         memset(&link_status, 0, sizeof(link_status));
1544         rte_i40e_dev_atomic_read_link_status(dev, &old);
1545
1546         do {
1547                 /* Get link status information from hardware */
1548                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1549                 if (status != I40E_SUCCESS) {
1550                         link.link_speed = ETH_LINK_SPEED_100;
1551                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1552                         PMD_DRV_LOG(ERR, "Failed to get link info");
1553                         goto out;
1554                 }
1555
1556                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1557                 if (!wait_to_complete)
1558                         break;
1559
1560                 rte_delay_ms(CHECK_INTERVAL);
1561         } while (!link.link_status && rep_cnt--);
1562
1563         if (!link.link_status)
1564                 goto out;
1565
1566         /* i40e uses full duplex only */
1567         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1568
1569         /* Parse the link status */
1570         switch (link_status.link_speed) {
1571         case I40E_LINK_SPEED_100MB:
1572                 link.link_speed = ETH_LINK_SPEED_100;
1573                 break;
1574         case I40E_LINK_SPEED_1GB:
1575                 link.link_speed = ETH_LINK_SPEED_1000;
1576                 break;
1577         case I40E_LINK_SPEED_10GB:
1578                 link.link_speed = ETH_LINK_SPEED_10G;
1579                 break;
1580         case I40E_LINK_SPEED_20GB:
1581                 link.link_speed = ETH_LINK_SPEED_20G;
1582                 break;
1583         case I40E_LINK_SPEED_40GB:
1584                 link.link_speed = ETH_LINK_SPEED_40G;
1585                 break;
1586         default:
1587                 link.link_speed = ETH_LINK_SPEED_100;
1588                 break;
1589         }
1590
1591 out:
1592         rte_i40e_dev_atomic_write_link_status(dev, &link);
1593         if (link.link_status == old.link_status)
1594                 return -1;
1595
1596         return 0;
1597 }
1598
1599 /* Get all the statistics of a VSI */
1600 void
1601 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1602 {
1603         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1604         struct i40e_eth_stats *nes = &vsi->eth_stats;
1605         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1606         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1607
1608         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1609                             vsi->offset_loaded, &oes->rx_bytes,
1610                             &nes->rx_bytes);
1611         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1612                             vsi->offset_loaded, &oes->rx_unicast,
1613                             &nes->rx_unicast);
1614         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1615                             vsi->offset_loaded, &oes->rx_multicast,
1616                             &nes->rx_multicast);
1617         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1618                             vsi->offset_loaded, &oes->rx_broadcast,
1619                             &nes->rx_broadcast);
1620         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1621                             &oes->rx_discards, &nes->rx_discards);
1622         /* GLV_REPC not supported */
1623         /* GLV_RMPC not supported */
1624         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1625                             &oes->rx_unknown_protocol,
1626                             &nes->rx_unknown_protocol);
1627         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1628                             vsi->offset_loaded, &oes->tx_bytes,
1629                             &nes->tx_bytes);
1630         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1631                             vsi->offset_loaded, &oes->tx_unicast,
1632                             &nes->tx_unicast);
1633         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1634                             vsi->offset_loaded, &oes->tx_multicast,
1635                             &nes->tx_multicast);
1636         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1637                             vsi->offset_loaded,  &oes->tx_broadcast,
1638                             &nes->tx_broadcast);
1639         /* GLV_TDPC not supported */
1640         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1641                             &oes->tx_errors, &nes->tx_errors);
1642         vsi->offset_loaded = true;
1643
1644         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1645                     vsi->vsi_id);
1646         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1647         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1648         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1649         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1650         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1651         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1652                     nes->rx_unknown_protocol);
1653         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1654         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1655         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1656         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1657         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1658         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1659         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1660                     vsi->vsi_id);
1661 }
1662
1663 static void
1664 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1665 {
1666         unsigned int i;
1667         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1668         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1669         /* Get statistics of struct i40e_eth_stats */
1670         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1671                             I40E_GLPRT_GORCL(hw->port),
1672                             pf->offset_loaded, &os->eth.rx_bytes,
1673                             &ns->eth.rx_bytes);
1674         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1675                             I40E_GLPRT_UPRCL(hw->port),
1676                             pf->offset_loaded, &os->eth.rx_unicast,
1677                             &ns->eth.rx_unicast);
1678         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1679                             I40E_GLPRT_MPRCL(hw->port),
1680                             pf->offset_loaded, &os->eth.rx_multicast,
1681                             &ns->eth.rx_multicast);
1682         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1683                             I40E_GLPRT_BPRCL(hw->port),
1684                             pf->offset_loaded, &os->eth.rx_broadcast,
1685                             &ns->eth.rx_broadcast);
1686         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1687                             pf->offset_loaded, &os->eth.rx_discards,
1688                             &ns->eth.rx_discards);
1689         /* GLPRT_REPC not supported */
1690         /* GLPRT_RMPC not supported */
1691         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1692                             pf->offset_loaded,
1693                             &os->eth.rx_unknown_protocol,
1694                             &ns->eth.rx_unknown_protocol);
1695         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1696                             I40E_GLPRT_GOTCL(hw->port),
1697                             pf->offset_loaded, &os->eth.tx_bytes,
1698                             &ns->eth.tx_bytes);
1699         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1700                             I40E_GLPRT_UPTCL(hw->port),
1701                             pf->offset_loaded, &os->eth.tx_unicast,
1702                             &ns->eth.tx_unicast);
1703         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1704                             I40E_GLPRT_MPTCL(hw->port),
1705                             pf->offset_loaded, &os->eth.tx_multicast,
1706                             &ns->eth.tx_multicast);
1707         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1708                             I40E_GLPRT_BPTCL(hw->port),
1709                             pf->offset_loaded, &os->eth.tx_broadcast,
1710                             &ns->eth.tx_broadcast);
1711         /* GLPRT_TEPC not supported */
1712
1713         /* additional port specific stats */
1714         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1715                             pf->offset_loaded, &os->tx_dropped_link_down,
1716                             &ns->tx_dropped_link_down);
1717         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1718                             pf->offset_loaded, &os->crc_errors,
1719                             &ns->crc_errors);
1720         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1721                             pf->offset_loaded, &os->illegal_bytes,
1722                             &ns->illegal_bytes);
1723         /* GLPRT_ERRBC not supported */
1724         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1725                             pf->offset_loaded, &os->mac_local_faults,
1726                             &ns->mac_local_faults);
1727         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1728                             pf->offset_loaded, &os->mac_remote_faults,
1729                             &ns->mac_remote_faults);
1730         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1731                             pf->offset_loaded, &os->rx_length_errors,
1732                             &ns->rx_length_errors);
1733         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1734                             pf->offset_loaded, &os->link_xon_rx,
1735                             &ns->link_xon_rx);
1736         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1737                             pf->offset_loaded, &os->link_xoff_rx,
1738                             &ns->link_xoff_rx);
1739         for (i = 0; i < 8; i++) {
1740                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1741                                     pf->offset_loaded,
1742                                     &os->priority_xon_rx[i],
1743                                     &ns->priority_xon_rx[i]);
1744                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1745                                     pf->offset_loaded,
1746                                     &os->priority_xoff_rx[i],
1747                                     &ns->priority_xoff_rx[i]);
1748         }
1749         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1750                             pf->offset_loaded, &os->link_xon_tx,
1751                             &ns->link_xon_tx);
1752         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1753                             pf->offset_loaded, &os->link_xoff_tx,
1754                             &ns->link_xoff_tx);
1755         for (i = 0; i < 8; i++) {
1756                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1757                                     pf->offset_loaded,
1758                                     &os->priority_xon_tx[i],
1759                                     &ns->priority_xon_tx[i]);
1760                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1761                                     pf->offset_loaded,
1762                                     &os->priority_xoff_tx[i],
1763                                     &ns->priority_xoff_tx[i]);
1764                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1765                                     pf->offset_loaded,
1766                                     &os->priority_xon_2_xoff[i],
1767                                     &ns->priority_xon_2_xoff[i]);
1768         }
1769         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1770                             I40E_GLPRT_PRC64L(hw->port),
1771                             pf->offset_loaded, &os->rx_size_64,
1772                             &ns->rx_size_64);
1773         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1774                             I40E_GLPRT_PRC127L(hw->port),
1775                             pf->offset_loaded, &os->rx_size_127,
1776                             &ns->rx_size_127);
1777         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1778                             I40E_GLPRT_PRC255L(hw->port),
1779                             pf->offset_loaded, &os->rx_size_255,
1780                             &ns->rx_size_255);
1781         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1782                             I40E_GLPRT_PRC511L(hw->port),
1783                             pf->offset_loaded, &os->rx_size_511,
1784                             &ns->rx_size_511);
1785         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1786                             I40E_GLPRT_PRC1023L(hw->port),
1787                             pf->offset_loaded, &os->rx_size_1023,
1788                             &ns->rx_size_1023);
1789         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1790                             I40E_GLPRT_PRC1522L(hw->port),
1791                             pf->offset_loaded, &os->rx_size_1522,
1792                             &ns->rx_size_1522);
1793         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1794                             I40E_GLPRT_PRC9522L(hw->port),
1795                             pf->offset_loaded, &os->rx_size_big,
1796                             &ns->rx_size_big);
1797         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1798                             pf->offset_loaded, &os->rx_undersize,
1799                             &ns->rx_undersize);
1800         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1801                             pf->offset_loaded, &os->rx_fragments,
1802                             &ns->rx_fragments);
1803         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1804                             pf->offset_loaded, &os->rx_oversize,
1805                             &ns->rx_oversize);
1806         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1807                             pf->offset_loaded, &os->rx_jabber,
1808                             &ns->rx_jabber);
1809         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1810                             I40E_GLPRT_PTC64L(hw->port),
1811                             pf->offset_loaded, &os->tx_size_64,
1812                             &ns->tx_size_64);
1813         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1814                             I40E_GLPRT_PTC127L(hw->port),
1815                             pf->offset_loaded, &os->tx_size_127,
1816                             &ns->tx_size_127);
1817         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1818                             I40E_GLPRT_PTC255L(hw->port),
1819                             pf->offset_loaded, &os->tx_size_255,
1820                             &ns->tx_size_255);
1821         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1822                             I40E_GLPRT_PTC511L(hw->port),
1823                             pf->offset_loaded, &os->tx_size_511,
1824                             &ns->tx_size_511);
1825         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1826                             I40E_GLPRT_PTC1023L(hw->port),
1827                             pf->offset_loaded, &os->tx_size_1023,
1828                             &ns->tx_size_1023);
1829         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1830                             I40E_GLPRT_PTC1522L(hw->port),
1831                             pf->offset_loaded, &os->tx_size_1522,
1832                             &ns->tx_size_1522);
1833         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1834                             I40E_GLPRT_PTC9522L(hw->port),
1835                             pf->offset_loaded, &os->tx_size_big,
1836                             &ns->tx_size_big);
1837         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1838                            pf->offset_loaded,
1839                            &os->fd_sb_match, &ns->fd_sb_match);
1840         /* GLPRT_MSPDC not supported */
1841         /* GLPRT_XEC not supported */
1842
1843         pf->offset_loaded = true;
1844
1845         if (pf->main_vsi)
1846                 i40e_update_vsi_stats(pf->main_vsi);
1847 }
1848
1849 /* Get all statistics of a port */
1850 static void
1851 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1852 {
1853         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1854         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1856         unsigned i;
1857
1858         /* call read registers - updates values, now write them to struct */
1859         i40e_read_stats_registers(pf, hw);
1860
1861         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1862                                                 ns->eth.rx_broadcast;
1863         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1864                                                 ns->eth.tx_broadcast;
1865         stats->ibytes   = ns->eth.rx_bytes;
1866         stats->obytes   = ns->eth.tx_bytes;
1867         stats->oerrors  = ns->eth.tx_errors;
1868         stats->imcasts  = ns->eth.rx_multicast;
1869         stats->fdirmatch = ns->fd_sb_match;
1870
1871         /* Rx Errors */
1872         stats->ibadcrc  = ns->crc_errors;
1873         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1874                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1875         stats->imissed  = ns->eth.rx_discards;
1876         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1877
1878         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1879         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1880         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1881         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1882         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1883         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1884         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1885                     ns->eth.rx_unknown_protocol);
1886         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1887         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1888         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1889         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1890         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1891         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1892
1893         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1894                     ns->tx_dropped_link_down);
1895         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1896         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1897                     ns->illegal_bytes);
1898         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1899         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1900                     ns->mac_local_faults);
1901         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1902                     ns->mac_remote_faults);
1903         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1904                     ns->rx_length_errors);
1905         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1906         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1907         for (i = 0; i < 8; i++) {
1908                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1909                                 i, ns->priority_xon_rx[i]);
1910                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1911                                 i, ns->priority_xoff_rx[i]);
1912         }
1913         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1914         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1915         for (i = 0; i < 8; i++) {
1916                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1917                                 i, ns->priority_xon_tx[i]);
1918                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1919                                 i, ns->priority_xoff_tx[i]);
1920                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1921                                 i, ns->priority_xon_2_xoff[i]);
1922         }
1923         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1924         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1925         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1926         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1927         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1928         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1929         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1930         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1931         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1932         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1933         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1934         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1935         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1936         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1937         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1938         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1939         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1940         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1941         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1942                         ns->mac_short_packet_dropped);
1943         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1944                     ns->checksum_error);
1945         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1946         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1947 }
1948
1949 static void
1950 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
1951 {
1952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954         struct i40e_hw_port_stats *hw_stats = &pf->stats;
1955
1956         /* The hw registers are cleared on read */
1957         pf->offset_loaded = false;
1958         i40e_read_stats_registers(pf, hw);
1959
1960         /* reset software counters */
1961         memset(hw_stats, 0, sizeof(*hw_stats));
1962 }
1963
1964 static int
1965 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1966                     unsigned n)
1967 {
1968         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1969         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1970         unsigned i, count = 0;
1971         struct i40e_hw_port_stats *hw_stats = &pf->stats;
1972
1973         if (n < I40E_NB_XSTATS)
1974                 return I40E_NB_XSTATS;
1975
1976         i40e_read_stats_registers(pf, hw);
1977
1978         /* Reset */
1979         if (xstats == NULL)
1980                 return 0;
1981
1982         /* Get stats from i40e_eth_stats struct */
1983         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
1984                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1985                          "%s", rte_i40e_stats_strings[i].name);
1986                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
1987                         rte_i40e_stats_strings[i].offset);
1988                 count++;
1989         }
1990
1991         /* Get individiual stats from i40e_hw_port struct */
1992         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
1993                 snprintf(xstats[count].name, sizeof(xstats[count].name),
1994                          "%s", rte_i40e_hw_port_strings[i].name);
1995                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
1996                                 rte_i40e_hw_port_strings[i].offset);
1997                 count++;
1998         }
1999
2000         /* Get per-queue stats from i40e_hw_port struct */
2001         for (i = 0; i < 8; i++) {
2002                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2003                          "rx_q%u_xon_priority_packets", i);
2004                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2005                                 offsetof(struct i40e_hw_port_stats,
2006                                          priority_xon_rx[i]));
2007                 count++;
2008
2009                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2010                          "rx_q%u_xoff_priority_packets", i);
2011                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2012                                 offsetof(struct i40e_hw_port_stats,
2013                                          priority_xoff_rx[i]));
2014                 count++;
2015
2016                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2017                          "tx_q%u_xon_priority_packets", i);
2018                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2019                                 offsetof(struct i40e_hw_port_stats,
2020                                          priority_xon_tx[i]));
2021                 count++;
2022
2023                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2024                          "tx_q%u_xoff_priority_packets", i);
2025                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2026                                 offsetof(struct i40e_hw_port_stats,
2027                                          priority_xoff_tx[i]));
2028                 count++;
2029
2030                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2031                          "xx_q%u_xon_to_xoff_priority_packets", i);
2032                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2033                                 offsetof(struct i40e_hw_port_stats,
2034                                          priority_xon_2_xoff[i]));
2035                 count++;
2036         }
2037
2038         return I40E_NB_XSTATS;
2039 }
2040
2041 /* Reset the statistics */
2042 static void
2043 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2044 {
2045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2046
2047         /* It results in reloading the start point of each counter */
2048         pf->offset_loaded = false;
2049 }
2050
2051 static int
2052 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2053                                  __rte_unused uint16_t queue_id,
2054                                  __rte_unused uint8_t stat_idx,
2055                                  __rte_unused uint8_t is_rx)
2056 {
2057         PMD_INIT_FUNC_TRACE();
2058
2059         return -ENOSYS;
2060 }
2061
2062 static void
2063 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2064 {
2065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066         struct i40e_vsi *vsi = pf->main_vsi;
2067
2068         dev_info->max_rx_queues = vsi->nb_qps;
2069         dev_info->max_tx_queues = vsi->nb_qps;
2070         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2071         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2072         dev_info->max_mac_addrs = vsi->max_macaddrs;
2073         dev_info->max_vfs = dev->pci_dev->max_vfs;
2074         dev_info->rx_offload_capa =
2075                 DEV_RX_OFFLOAD_VLAN_STRIP |
2076                 DEV_RX_OFFLOAD_QINQ_STRIP |
2077                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2078                 DEV_RX_OFFLOAD_UDP_CKSUM |
2079                 DEV_RX_OFFLOAD_TCP_CKSUM;
2080         dev_info->tx_offload_capa =
2081                 DEV_TX_OFFLOAD_VLAN_INSERT |
2082                 DEV_TX_OFFLOAD_QINQ_INSERT |
2083                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2084                 DEV_TX_OFFLOAD_UDP_CKSUM |
2085                 DEV_TX_OFFLOAD_TCP_CKSUM |
2086                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2087                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2088                 DEV_TX_OFFLOAD_TCP_TSO;
2089         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2090                                                 sizeof(uint32_t);
2091         dev_info->reta_size = pf->hash_lut_size;
2092         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2093
2094         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2095                 .rx_thresh = {
2096                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2097                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2098                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2099                 },
2100                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2101                 .rx_drop_en = 0,
2102         };
2103
2104         dev_info->default_txconf = (struct rte_eth_txconf) {
2105                 .tx_thresh = {
2106                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2107                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2108                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2109                 },
2110                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2111                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2112                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2113                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2114         };
2115
2116         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2117                 .nb_max = I40E_MAX_RING_DESC,
2118                 .nb_min = I40E_MIN_RING_DESC,
2119                 .nb_align = I40E_ALIGN_RING_DESC,
2120         };
2121
2122         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2123                 .nb_max = I40E_MAX_RING_DESC,
2124                 .nb_min = I40E_MIN_RING_DESC,
2125                 .nb_align = I40E_ALIGN_RING_DESC,
2126         };
2127
2128         if (pf->flags & I40E_FLAG_VMDQ) {
2129                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2130                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2131                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2132                                                 pf->max_nb_vmdq_vsi;
2133                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2134                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2135                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2136         }
2137 }
2138
2139 static int
2140 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2141 {
2142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2143         struct i40e_vsi *vsi = pf->main_vsi;
2144         PMD_INIT_FUNC_TRACE();
2145
2146         if (on)
2147                 return i40e_vsi_add_vlan(vsi, vlan_id);
2148         else
2149                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2150 }
2151
2152 static void
2153 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2154                    __rte_unused uint16_t tpid)
2155 {
2156         PMD_INIT_FUNC_TRACE();
2157 }
2158
2159 static void
2160 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2161 {
2162         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2163         struct i40e_vsi *vsi = pf->main_vsi;
2164
2165         if (mask & ETH_VLAN_STRIP_MASK) {
2166                 /* Enable or disable VLAN stripping */
2167                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2168                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2169                 else
2170                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2171         }
2172
2173         if (mask & ETH_VLAN_EXTEND_MASK) {
2174                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2175                         i40e_vsi_config_double_vlan(vsi, TRUE);
2176                 else
2177                         i40e_vsi_config_double_vlan(vsi, FALSE);
2178         }
2179 }
2180
2181 static void
2182 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2183                           __rte_unused uint16_t queue,
2184                           __rte_unused int on)
2185 {
2186         PMD_INIT_FUNC_TRACE();
2187 }
2188
2189 static int
2190 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2191 {
2192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193         struct i40e_vsi *vsi = pf->main_vsi;
2194         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2195         struct i40e_vsi_vlan_pvid_info info;
2196
2197         memset(&info, 0, sizeof(info));
2198         info.on = on;
2199         if (info.on)
2200                 info.config.pvid = pvid;
2201         else {
2202                 info.config.reject.tagged =
2203                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2204                 info.config.reject.untagged =
2205                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2206         }
2207
2208         return i40e_vsi_vlan_pvid_set(vsi, &info);
2209 }
2210
2211 static int
2212 i40e_dev_led_on(struct rte_eth_dev *dev)
2213 {
2214         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2215         uint32_t mode = i40e_led_get(hw);
2216
2217         if (mode == 0)
2218                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2219
2220         return 0;
2221 }
2222
2223 static int
2224 i40e_dev_led_off(struct rte_eth_dev *dev)
2225 {
2226         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         uint32_t mode = i40e_led_get(hw);
2228
2229         if (mode != 0)
2230                 i40e_led_set(hw, 0, false);
2231
2232         return 0;
2233 }
2234
2235 static int
2236 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2237 {
2238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2240
2241         fc_conf->pause_time = pf->fc_conf.pause_time;
2242         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2243         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2244
2245          /* Return current mode according to actual setting*/
2246         switch (hw->fc.current_mode) {
2247         case I40E_FC_FULL:
2248                 fc_conf->mode = RTE_FC_FULL;
2249                 break;
2250         case I40E_FC_TX_PAUSE:
2251                 fc_conf->mode = RTE_FC_TX_PAUSE;
2252                 break;
2253         case I40E_FC_RX_PAUSE:
2254                 fc_conf->mode = RTE_FC_RX_PAUSE;
2255                 break;
2256         case I40E_FC_NONE:
2257         default:
2258                 fc_conf->mode = RTE_FC_NONE;
2259         };
2260
2261         return 0;
2262 }
2263
2264 static int
2265 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2266 {
2267         uint32_t mflcn_reg, fctrl_reg, reg;
2268         uint32_t max_high_water;
2269         uint8_t i, aq_failure;
2270         int err;
2271         struct i40e_hw *hw;
2272         struct i40e_pf *pf;
2273         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2274                 [RTE_FC_NONE] = I40E_FC_NONE,
2275                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2276                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2277                 [RTE_FC_FULL] = I40E_FC_FULL
2278         };
2279
2280         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2281
2282         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2283         if ((fc_conf->high_water > max_high_water) ||
2284                         (fc_conf->high_water < fc_conf->low_water)) {
2285                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2286                         "High_water must <= %d.", max_high_water);
2287                 return -EINVAL;
2288         }
2289
2290         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2292         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2293
2294         pf->fc_conf.pause_time = fc_conf->pause_time;
2295         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2296         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2297
2298         PMD_INIT_FUNC_TRACE();
2299
2300         /* All the link flow control related enable/disable register
2301          * configuration is handle by the F/W
2302          */
2303         err = i40e_set_fc(hw, &aq_failure, true);
2304         if (err < 0)
2305                 return -ENOSYS;
2306
2307         if (i40e_is_40G_device(hw->device_id)) {
2308                 /* Configure flow control refresh threshold,
2309                  * the value for stat_tx_pause_refresh_timer[8]
2310                  * is used for global pause operation.
2311                  */
2312
2313                 I40E_WRITE_REG(hw,
2314                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2315                                pf->fc_conf.pause_time);
2316
2317                 /* configure the timer value included in transmitted pause
2318                  * frame,
2319                  * the value for stat_tx_pause_quanta[8] is used for global
2320                  * pause operation
2321                  */
2322                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2323                                pf->fc_conf.pause_time);
2324
2325                 fctrl_reg = I40E_READ_REG(hw,
2326                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2327
2328                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2329                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2330                 else
2331                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2332
2333                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2334                                fctrl_reg);
2335         } else {
2336                 /* Configure pause time (2 TCs per register) */
2337                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2338                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2339                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2340
2341                 /* Configure flow control refresh threshold value */
2342                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2343                                pf->fc_conf.pause_time / 2);
2344
2345                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2346
2347                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2348                  *depending on configuration
2349                  */
2350                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2351                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2352                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2353                 } else {
2354                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2355                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2356                 }
2357
2358                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2359         }
2360
2361         /* config the water marker both based on the packets and bytes */
2362         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2363                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2364                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2365         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2366                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2367                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2368         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2369                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2370                        << I40E_KILOSHIFT);
2371         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2372                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2373                        << I40E_KILOSHIFT);
2374
2375         I40E_WRITE_FLUSH(hw);
2376
2377         return 0;
2378 }
2379
2380 static int
2381 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2382                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2383 {
2384         PMD_INIT_FUNC_TRACE();
2385
2386         return -ENOSYS;
2387 }
2388
2389 /* Add a MAC address, and update filters */
2390 static void
2391 i40e_macaddr_add(struct rte_eth_dev *dev,
2392                  struct ether_addr *mac_addr,
2393                  __rte_unused uint32_t index,
2394                  uint32_t pool)
2395 {
2396         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2397         struct i40e_mac_filter_info mac_filter;
2398         struct i40e_vsi *vsi;
2399         int ret;
2400
2401         /* If VMDQ not enabled or configured, return */
2402         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2403                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2404                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2405                         pool);
2406                 return;
2407         }
2408
2409         if (pool > pf->nb_cfg_vmdq_vsi) {
2410                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2411                                 pool, pf->nb_cfg_vmdq_vsi);
2412                 return;
2413         }
2414
2415         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2416         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2417
2418         if (pool == 0)
2419                 vsi = pf->main_vsi;
2420         else
2421                 vsi = pf->vmdq[pool - 1].vsi;
2422
2423         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2424         if (ret != I40E_SUCCESS) {
2425                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2426                 return;
2427         }
2428 }
2429
2430 /* Remove a MAC address, and update filters */
2431 static void
2432 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2433 {
2434         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2435         struct i40e_vsi *vsi;
2436         struct rte_eth_dev_data *data = dev->data;
2437         struct ether_addr *macaddr;
2438         int ret;
2439         uint32_t i;
2440         uint64_t pool_sel;
2441
2442         macaddr = &(data->mac_addrs[index]);
2443
2444         pool_sel = dev->data->mac_pool_sel[index];
2445
2446         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2447                 if (pool_sel & (1ULL << i)) {
2448                         if (i == 0)
2449                                 vsi = pf->main_vsi;
2450                         else {
2451                                 /* No VMDQ pool enabled or configured */
2452                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2453                                         (i > pf->nb_cfg_vmdq_vsi)) {
2454                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2455                                                         "/configured");
2456                                         return;
2457                                 }
2458                                 vsi = pf->vmdq[i - 1].vsi;
2459                         }
2460                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2461
2462                         if (ret) {
2463                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2464                                 return;
2465                         }
2466                 }
2467         }
2468 }
2469
2470 /* Set perfect match or hash match of MAC and VLAN for a VF */
2471 static int
2472 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2473                  struct rte_eth_mac_filter *filter,
2474                  bool add)
2475 {
2476         struct i40e_hw *hw;
2477         struct i40e_mac_filter_info mac_filter;
2478         struct ether_addr old_mac;
2479         struct ether_addr *new_mac;
2480         struct i40e_pf_vf *vf = NULL;
2481         uint16_t vf_id;
2482         int ret;
2483
2484         if (pf == NULL) {
2485                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2486                 return -EINVAL;
2487         }
2488         hw = I40E_PF_TO_HW(pf);
2489
2490         if (filter == NULL) {
2491                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2492                 return -EINVAL;
2493         }
2494
2495         new_mac = &filter->mac_addr;
2496
2497         if (is_zero_ether_addr(new_mac)) {
2498                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2499                 return -EINVAL;
2500         }
2501
2502         vf_id = filter->dst_id;
2503
2504         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2505                 PMD_DRV_LOG(ERR, "Invalid argument.");
2506                 return -EINVAL;
2507         }
2508         vf = &pf->vfs[vf_id];
2509
2510         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2511                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2512                 return -EINVAL;
2513         }
2514
2515         if (add) {
2516                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2517                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2518                                 ETHER_ADDR_LEN);
2519                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2520                                  ETHER_ADDR_LEN);
2521
2522                 mac_filter.filter_type = filter->filter_type;
2523                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2524                 if (ret != I40E_SUCCESS) {
2525                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2526                         return -1;
2527                 }
2528                 ether_addr_copy(new_mac, &pf->dev_addr);
2529         } else {
2530                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2531                                 ETHER_ADDR_LEN);
2532                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2533                 if (ret != I40E_SUCCESS) {
2534                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2535                         return -1;
2536                 }
2537
2538                 /* Clear device address as it has been removed */
2539                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2540                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2541         }
2542
2543         return 0;
2544 }
2545
2546 /* MAC filter handle */
2547 static int
2548 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2549                 void *arg)
2550 {
2551         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2552         struct rte_eth_mac_filter *filter;
2553         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2554         int ret = I40E_NOT_SUPPORTED;
2555
2556         filter = (struct rte_eth_mac_filter *)(arg);
2557
2558         switch (filter_op) {
2559         case RTE_ETH_FILTER_NOP:
2560                 ret = I40E_SUCCESS;
2561                 break;
2562         case RTE_ETH_FILTER_ADD:
2563                 i40e_pf_disable_irq0(hw);
2564                 if (filter->is_vf)
2565                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2566                 i40e_pf_enable_irq0(hw);
2567                 break;
2568         case RTE_ETH_FILTER_DELETE:
2569                 i40e_pf_disable_irq0(hw);
2570                 if (filter->is_vf)
2571                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2572                 i40e_pf_enable_irq0(hw);
2573                 break;
2574         default:
2575                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2576                 ret = I40E_ERR_PARAM;
2577                 break;
2578         }
2579
2580         return ret;
2581 }
2582
2583 static int
2584 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2585 {
2586         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2587         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2588         int ret;
2589
2590         if (!lut)
2591                 return -EINVAL;
2592
2593         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2594                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2595                                           lut, lut_size);
2596                 if (ret) {
2597                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2598                         return ret;
2599                 }
2600         } else {
2601                 uint32_t *lut_dw = (uint32_t *)lut;
2602                 uint16_t i, lut_size_dw = lut_size / 4;
2603
2604                 for (i = 0; i < lut_size_dw; i++)
2605                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2606         }
2607
2608         return 0;
2609 }
2610
2611 static int
2612 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2613 {
2614         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2615         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2616         int ret;
2617
2618         if (!vsi || !lut)
2619                 return -EINVAL;
2620
2621         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2622                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2623                                           lut, lut_size);
2624                 if (ret) {
2625                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2626                         return ret;
2627                 }
2628         } else {
2629                 uint32_t *lut_dw = (uint32_t *)lut;
2630                 uint16_t i, lut_size_dw = lut_size / 4;
2631
2632                 for (i = 0; i < lut_size_dw; i++)
2633                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2634                 I40E_WRITE_FLUSH(hw);
2635         }
2636
2637         return 0;
2638 }
2639
2640 static int
2641 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2642                          struct rte_eth_rss_reta_entry64 *reta_conf,
2643                          uint16_t reta_size)
2644 {
2645         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2646         uint16_t i, lut_size = pf->hash_lut_size;
2647         uint16_t idx, shift;
2648         uint8_t *lut;
2649         int ret;
2650
2651         if (reta_size != lut_size ||
2652                 reta_size > ETH_RSS_RETA_SIZE_512) {
2653                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2654                         "(%d) doesn't match the number hardware can supported "
2655                                         "(%d)\n", reta_size, lut_size);
2656                 return -EINVAL;
2657         }
2658
2659         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2660         if (!lut) {
2661                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2662                 return -ENOMEM;
2663         }
2664         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2665         if (ret)
2666                 goto out;
2667         for (i = 0; i < reta_size; i++) {
2668                 idx = i / RTE_RETA_GROUP_SIZE;
2669                 shift = i % RTE_RETA_GROUP_SIZE;
2670                 if (reta_conf[idx].mask & (1ULL << shift))
2671                         lut[i] = reta_conf[idx].reta[shift];
2672         }
2673         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2674
2675 out:
2676         rte_free(lut);
2677
2678         return ret;
2679 }
2680
2681 static int
2682 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2683                         struct rte_eth_rss_reta_entry64 *reta_conf,
2684                         uint16_t reta_size)
2685 {
2686         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2687         uint16_t i, lut_size = pf->hash_lut_size;
2688         uint16_t idx, shift;
2689         uint8_t *lut;
2690         int ret;
2691
2692         if (reta_size != lut_size ||
2693                 reta_size > ETH_RSS_RETA_SIZE_512) {
2694                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2695                         "(%d) doesn't match the number hardware can supported "
2696                                         "(%d)\n", reta_size, lut_size);
2697                 return -EINVAL;
2698         }
2699
2700         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2701         if (!lut) {
2702                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2703                 return -ENOMEM;
2704         }
2705
2706         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2707         if (ret)
2708                 goto out;
2709         for (i = 0; i < reta_size; i++) {
2710                 idx = i / RTE_RETA_GROUP_SIZE;
2711                 shift = i % RTE_RETA_GROUP_SIZE;
2712                 if (reta_conf[idx].mask & (1ULL << shift))
2713                         reta_conf[idx].reta[shift] = lut[i];
2714         }
2715
2716 out:
2717         rte_free(lut);
2718
2719         return ret;
2720 }
2721
2722 /**
2723  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2724  * @hw:   pointer to the HW structure
2725  * @mem:  pointer to mem struct to fill out
2726  * @size: size of memory requested
2727  * @alignment: what to align the allocation to
2728  **/
2729 enum i40e_status_code
2730 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2731                         struct i40e_dma_mem *mem,
2732                         u64 size,
2733                         u32 alignment)
2734 {
2735         static uint64_t id = 0;
2736         const struct rte_memzone *mz = NULL;
2737         char z_name[RTE_MEMZONE_NAMESIZE];
2738
2739         if (!mem)
2740                 return I40E_ERR_PARAM;
2741
2742         id++;
2743         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2744 #ifdef RTE_LIBRTE_XEN_DOM0
2745         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2746                                          alignment, RTE_PGSIZE_2M);
2747 #else
2748         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2749                                          alignment);
2750 #endif
2751         if (!mz)
2752                 return I40E_ERR_NO_MEMORY;
2753
2754         mem->id = id;
2755         mem->size = size;
2756         mem->va = mz->addr;
2757 #ifdef RTE_LIBRTE_XEN_DOM0
2758         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2759 #else
2760         mem->pa = mz->phys_addr;
2761 #endif
2762
2763         return I40E_SUCCESS;
2764 }
2765
2766 /**
2767  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2768  * @hw:   pointer to the HW structure
2769  * @mem:  ptr to mem struct to free
2770  **/
2771 enum i40e_status_code
2772 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2773                     struct i40e_dma_mem *mem)
2774 {
2775         if (!mem || !mem->va)
2776                 return I40E_ERR_PARAM;
2777
2778         mem->va = NULL;
2779         mem->pa = (u64)0;
2780
2781         return I40E_SUCCESS;
2782 }
2783
2784 /**
2785  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2786  * @hw:   pointer to the HW structure
2787  * @mem:  pointer to mem struct to fill out
2788  * @size: size of memory requested
2789  **/
2790 enum i40e_status_code
2791 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2792                          struct i40e_virt_mem *mem,
2793                          u32 size)
2794 {
2795         if (!mem)
2796                 return I40E_ERR_PARAM;
2797
2798         mem->size = size;
2799         mem->va = rte_zmalloc("i40e", size, 0);
2800
2801         if (mem->va)
2802                 return I40E_SUCCESS;
2803         else
2804                 return I40E_ERR_NO_MEMORY;
2805 }
2806
2807 /**
2808  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2809  * @hw:   pointer to the HW structure
2810  * @mem:  pointer to mem struct to free
2811  **/
2812 enum i40e_status_code
2813 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2814                      struct i40e_virt_mem *mem)
2815 {
2816         if (!mem)
2817                 return I40E_ERR_PARAM;
2818
2819         rte_free(mem->va);
2820         mem->va = NULL;
2821
2822         return I40E_SUCCESS;
2823 }
2824
2825 void
2826 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2827 {
2828         rte_spinlock_init(&sp->spinlock);
2829 }
2830
2831 void
2832 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2833 {
2834         rte_spinlock_lock(&sp->spinlock);
2835 }
2836
2837 void
2838 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2839 {
2840         rte_spinlock_unlock(&sp->spinlock);
2841 }
2842
2843 void
2844 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2845 {
2846         return;
2847 }
2848
2849 /**
2850  * Get the hardware capabilities, which will be parsed
2851  * and saved into struct i40e_hw.
2852  */
2853 static int
2854 i40e_get_cap(struct i40e_hw *hw)
2855 {
2856         struct i40e_aqc_list_capabilities_element_resp *buf;
2857         uint16_t len, size = 0;
2858         int ret;
2859
2860         /* Calculate a huge enough buff for saving response data temporarily */
2861         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2862                                                 I40E_MAX_CAP_ELE_NUM;
2863         buf = rte_zmalloc("i40e", len, 0);
2864         if (!buf) {
2865                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2866                 return I40E_ERR_NO_MEMORY;
2867         }
2868
2869         /* Get, parse the capabilities and save it to hw */
2870         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2871                         i40e_aqc_opc_list_func_capabilities, NULL);
2872         if (ret != I40E_SUCCESS)
2873                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2874
2875         /* Free the temporary buffer after being used */
2876         rte_free(buf);
2877
2878         return ret;
2879 }
2880
2881 static int
2882 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2883 {
2884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2885         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2886         uint16_t qp_count = 0, vsi_count = 0;
2887
2888         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2889                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2890                 return -EINVAL;
2891         }
2892         /* Add the parameter init for LFC */
2893         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2894         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2895         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2896
2897         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2898         pf->max_num_vsi = hw->func_caps.num_vsis;
2899         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
2900         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2901         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2902
2903         /* FDir queue/VSI allocation */
2904         pf->fdir_qp_offset = 0;
2905         if (hw->func_caps.fd) {
2906                 pf->flags |= I40E_FLAG_FDIR;
2907                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2908         } else {
2909                 pf->fdir_nb_qps = 0;
2910         }
2911         qp_count += pf->fdir_nb_qps;
2912         vsi_count += 1;
2913
2914         /* LAN queue/VSI allocation */
2915         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
2916         if (!hw->func_caps.rss) {
2917                 pf->lan_nb_qps = 1;
2918         } else {
2919                 pf->flags |= I40E_FLAG_RSS;
2920                 if (hw->mac.type == I40E_MAC_X722)
2921                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
2922                 pf->lan_nb_qps = pf->lan_nb_qp_max;
2923         }
2924         qp_count += pf->lan_nb_qps;
2925         vsi_count += 1;
2926
2927         /* VF queue/VSI allocation */
2928         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
2929         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2930                 pf->flags |= I40E_FLAG_SRIOV;
2931                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2932                 pf->vf_num = dev->pci_dev->max_vfs;
2933                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
2934                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
2935                             pf->vf_nb_qps * pf->vf_num);
2936         } else {
2937                 pf->vf_nb_qps = 0;
2938                 pf->vf_num = 0;
2939         }
2940         qp_count += pf->vf_nb_qps * pf->vf_num;
2941         vsi_count += pf->vf_num;
2942
2943         /* VMDq queue/VSI allocation */
2944         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
2945         if (hw->func_caps.vmdq) {
2946                 pf->flags |= I40E_FLAG_VMDQ;
2947                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
2948                 pf->max_nb_vmdq_vsi = 1;
2949                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues per VMDQ VSI, "
2950                             "in total %u queues", pf->max_nb_vmdq_vsi,
2951                             pf->vmdq_nb_qps,
2952                             pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
2953         } else {
2954                 pf->vmdq_nb_qps = 0;
2955                 pf->max_nb_vmdq_vsi = 0;
2956         }
2957         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2958         vsi_count += pf->max_nb_vmdq_vsi;
2959
2960         if (hw->func_caps.dcb)
2961                 pf->flags |= I40E_FLAG_DCB;
2962
2963         if (qp_count > hw->func_caps.num_tx_qp) {
2964                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
2965                             "the hardware maximum %u", qp_count,
2966                             hw->func_caps.num_tx_qp);
2967                 return -EINVAL;
2968         }
2969         if (vsi_count > hw->func_caps.num_vsis) {
2970                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
2971                             "the hardware maximum %u", vsi_count,
2972                             hw->func_caps.num_vsis);
2973                 return -EINVAL;
2974         }
2975
2976         return 0;
2977 }
2978
2979 static int
2980 i40e_pf_get_switch_config(struct i40e_pf *pf)
2981 {
2982         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2983         struct i40e_aqc_get_switch_config_resp *switch_config;
2984         struct i40e_aqc_switch_config_element_resp *element;
2985         uint16_t start_seid = 0, num_reported;
2986         int ret;
2987
2988         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2989                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2990         if (!switch_config) {
2991                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2992                 return -ENOMEM;
2993         }
2994
2995         /* Get the switch configurations */
2996         ret = i40e_aq_get_switch_config(hw, switch_config,
2997                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2998         if (ret != I40E_SUCCESS) {
2999                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3000                 goto fail;
3001         }
3002         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3003         if (num_reported != 1) { /* The number should be 1 */
3004                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3005                 goto fail;
3006         }
3007
3008         /* Parse the switch configuration elements */
3009         element = &(switch_config->element[0]);
3010         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3011                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3012                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3013         } else
3014                 PMD_DRV_LOG(INFO, "Unknown element type");
3015
3016 fail:
3017         rte_free(switch_config);
3018
3019         return ret;
3020 }
3021
3022 static int
3023 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3024                         uint32_t num)
3025 {
3026         struct pool_entry *entry;
3027
3028         if (pool == NULL || num == 0)
3029                 return -EINVAL;
3030
3031         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3032         if (entry == NULL) {
3033                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3034                 return -ENOMEM;
3035         }
3036
3037         /* queue heap initialize */
3038         pool->num_free = num;
3039         pool->num_alloc = 0;
3040         pool->base = base;
3041         LIST_INIT(&pool->alloc_list);
3042         LIST_INIT(&pool->free_list);
3043
3044         /* Initialize element  */
3045         entry->base = 0;
3046         entry->len = num;
3047
3048         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3049         return 0;
3050 }
3051
3052 static void
3053 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3054 {
3055         struct pool_entry *entry;
3056
3057         if (pool == NULL)
3058                 return;
3059
3060         LIST_FOREACH(entry, &pool->alloc_list, next) {
3061                 LIST_REMOVE(entry, next);
3062                 rte_free(entry);
3063         }
3064
3065         LIST_FOREACH(entry, &pool->free_list, next) {
3066                 LIST_REMOVE(entry, next);
3067                 rte_free(entry);
3068         }
3069
3070         pool->num_free = 0;
3071         pool->num_alloc = 0;
3072         pool->base = 0;
3073         LIST_INIT(&pool->alloc_list);
3074         LIST_INIT(&pool->free_list);
3075 }
3076
3077 static int
3078 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3079                        uint32_t base)
3080 {
3081         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3082         uint32_t pool_offset;
3083         int insert;
3084
3085         if (pool == NULL) {
3086                 PMD_DRV_LOG(ERR, "Invalid parameter");
3087                 return -EINVAL;
3088         }
3089
3090         pool_offset = base - pool->base;
3091         /* Lookup in alloc list */
3092         LIST_FOREACH(entry, &pool->alloc_list, next) {
3093                 if (entry->base == pool_offset) {
3094                         valid_entry = entry;
3095                         LIST_REMOVE(entry, next);
3096                         break;
3097                 }
3098         }
3099
3100         /* Not find, return */
3101         if (valid_entry == NULL) {
3102                 PMD_DRV_LOG(ERR, "Failed to find entry");
3103                 return -EINVAL;
3104         }
3105
3106         /**
3107          * Found it, move it to free list  and try to merge.
3108          * In order to make merge easier, always sort it by qbase.
3109          * Find adjacent prev and last entries.
3110          */
3111         prev = next = NULL;
3112         LIST_FOREACH(entry, &pool->free_list, next) {
3113                 if (entry->base > valid_entry->base) {
3114                         next = entry;
3115                         break;
3116                 }
3117                 prev = entry;
3118         }
3119
3120         insert = 0;
3121         /* Try to merge with next one*/
3122         if (next != NULL) {
3123                 /* Merge with next one */
3124                 if (valid_entry->base + valid_entry->len == next->base) {
3125                         next->base = valid_entry->base;
3126                         next->len += valid_entry->len;
3127                         rte_free(valid_entry);
3128                         valid_entry = next;
3129                         insert = 1;
3130                 }
3131         }
3132
3133         if (prev != NULL) {
3134                 /* Merge with previous one */
3135                 if (prev->base + prev->len == valid_entry->base) {
3136                         prev->len += valid_entry->len;
3137                         /* If it merge with next one, remove next node */
3138                         if (insert == 1) {
3139                                 LIST_REMOVE(valid_entry, next);
3140                                 rte_free(valid_entry);
3141                         } else {
3142                                 rte_free(valid_entry);
3143                                 insert = 1;
3144                         }
3145                 }
3146         }
3147
3148         /* Not find any entry to merge, insert */
3149         if (insert == 0) {
3150                 if (prev != NULL)
3151                         LIST_INSERT_AFTER(prev, valid_entry, next);
3152                 else if (next != NULL)
3153                         LIST_INSERT_BEFORE(next, valid_entry, next);
3154                 else /* It's empty list, insert to head */
3155                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3156         }
3157
3158         pool->num_free += valid_entry->len;
3159         pool->num_alloc -= valid_entry->len;
3160
3161         return 0;
3162 }
3163
3164 static int
3165 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3166                        uint16_t num)
3167 {
3168         struct pool_entry *entry, *valid_entry;
3169
3170         if (pool == NULL || num == 0) {
3171                 PMD_DRV_LOG(ERR, "Invalid parameter");
3172                 return -EINVAL;
3173         }
3174
3175         if (pool->num_free < num) {
3176                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3177                             num, pool->num_free);
3178                 return -ENOMEM;
3179         }
3180
3181         valid_entry = NULL;
3182         /* Lookup  in free list and find most fit one */
3183         LIST_FOREACH(entry, &pool->free_list, next) {
3184                 if (entry->len >= num) {
3185                         /* Find best one */
3186                         if (entry->len == num) {
3187                                 valid_entry = entry;
3188                                 break;
3189                         }
3190                         if (valid_entry == NULL || valid_entry->len > entry->len)
3191                                 valid_entry = entry;
3192                 }
3193         }
3194
3195         /* Not find one to satisfy the request, return */
3196         if (valid_entry == NULL) {
3197                 PMD_DRV_LOG(ERR, "No valid entry found");
3198                 return -ENOMEM;
3199         }
3200         /**
3201          * The entry have equal queue number as requested,
3202          * remove it from alloc_list.
3203          */
3204         if (valid_entry->len == num) {
3205                 LIST_REMOVE(valid_entry, next);
3206         } else {
3207                 /**
3208                  * The entry have more numbers than requested,
3209                  * create a new entry for alloc_list and minus its
3210                  * queue base and number in free_list.
3211                  */
3212                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3213                 if (entry == NULL) {
3214                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3215                                     "resource pool");
3216                         return -ENOMEM;
3217                 }
3218                 entry->base = valid_entry->base;
3219                 entry->len = num;
3220                 valid_entry->base += num;
3221                 valid_entry->len -= num;
3222                 valid_entry = entry;
3223         }
3224
3225         /* Insert it into alloc list, not sorted */
3226         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3227
3228         pool->num_free -= valid_entry->len;
3229         pool->num_alloc += valid_entry->len;
3230
3231         return (valid_entry->base + pool->base);
3232 }
3233
3234 /**
3235  * bitmap_is_subset - Check whether src2 is subset of src1
3236  **/
3237 static inline int
3238 bitmap_is_subset(uint8_t src1, uint8_t src2)
3239 {
3240         return !((src1 ^ src2) & src2);
3241 }
3242
3243 static int
3244 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3245 {
3246         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3247
3248         /* If DCB is not supported, only default TC is supported */
3249         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3250                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3251                 return -EINVAL;
3252         }
3253
3254         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3255                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3256                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3257                             enabled_tcmap);
3258                 return -EINVAL;
3259         }
3260         return I40E_SUCCESS;
3261 }
3262
3263 int
3264 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3265                                 struct i40e_vsi_vlan_pvid_info *info)
3266 {
3267         struct i40e_hw *hw;
3268         struct i40e_vsi_context ctxt;
3269         uint8_t vlan_flags = 0;
3270         int ret;
3271
3272         if (vsi == NULL || info == NULL) {
3273                 PMD_DRV_LOG(ERR, "invalid parameters");
3274                 return I40E_ERR_PARAM;
3275         }
3276
3277         if (info->on) {
3278                 vsi->info.pvid = info->config.pvid;
3279                 /**
3280                  * If insert pvid is enabled, only tagged pkts are
3281                  * allowed to be sent out.
3282                  */
3283                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3284                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3285         } else {
3286                 vsi->info.pvid = 0;
3287                 if (info->config.reject.tagged == 0)
3288                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3289
3290                 if (info->config.reject.untagged == 0)
3291                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3292         }
3293         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3294                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3295         vsi->info.port_vlan_flags |= vlan_flags;
3296         vsi->info.valid_sections =
3297                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3298         memset(&ctxt, 0, sizeof(ctxt));
3299         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3300         ctxt.seid = vsi->seid;
3301
3302         hw = I40E_VSI_TO_HW(vsi);
3303         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3304         if (ret != I40E_SUCCESS)
3305                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3306
3307         return ret;
3308 }
3309
3310 static int
3311 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3312 {
3313         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3314         int i, ret;
3315         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3316
3317         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3318         if (ret != I40E_SUCCESS)
3319                 return ret;
3320
3321         if (!vsi->seid) {
3322                 PMD_DRV_LOG(ERR, "seid not valid");
3323                 return -EINVAL;
3324         }
3325
3326         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3327         tc_bw_data.tc_valid_bits = enabled_tcmap;
3328         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3329                 tc_bw_data.tc_bw_credits[i] =
3330                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3331
3332         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3333         if (ret != I40E_SUCCESS) {
3334                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3335                 return ret;
3336         }
3337
3338         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3339                                         sizeof(vsi->info.qs_handle));
3340         return I40E_SUCCESS;
3341 }
3342
3343 static int
3344 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3345                                  struct i40e_aqc_vsi_properties_data *info,
3346                                  uint8_t enabled_tcmap)
3347 {
3348         int ret, i, total_tc = 0;
3349         uint16_t qpnum_per_tc, bsf, qp_idx;
3350
3351         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3352         if (ret != I40E_SUCCESS)
3353                 return ret;
3354
3355         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3356                 if (enabled_tcmap & (1 << i))
3357                         total_tc++;
3358         vsi->enabled_tc = enabled_tcmap;
3359
3360         /* Number of queues per enabled TC */
3361         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3362         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3363         bsf = rte_bsf32(qpnum_per_tc);
3364
3365         /* Adjust the queue number to actual queues that can be applied */
3366         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3367                 vsi->nb_qps = qpnum_per_tc * total_tc;
3368
3369         /**
3370          * Configure TC and queue mapping parameters, for enabled TC,
3371          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3372          * default queue will serve it.
3373          */
3374         qp_idx = 0;
3375         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3376                 if (vsi->enabled_tc & (1 << i)) {
3377                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3378                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3379                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3380                         qp_idx += qpnum_per_tc;
3381                 } else
3382                         info->tc_mapping[i] = 0;
3383         }
3384
3385         /* Associate queue number with VSI */
3386         if (vsi->type == I40E_VSI_SRIOV) {
3387                 info->mapping_flags |=
3388                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3389                 for (i = 0; i < vsi->nb_qps; i++)
3390                         info->queue_mapping[i] =
3391                                 rte_cpu_to_le_16(vsi->base_queue + i);
3392         } else {
3393                 info->mapping_flags |=
3394                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3395                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3396         }
3397         info->valid_sections |=
3398                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3399
3400         return I40E_SUCCESS;
3401 }
3402
3403 static int
3404 i40e_veb_release(struct i40e_veb *veb)
3405 {
3406         struct i40e_vsi *vsi;
3407         struct i40e_hw *hw;
3408
3409         if (veb == NULL || veb->associate_vsi == NULL)
3410                 return -EINVAL;
3411
3412         if (!TAILQ_EMPTY(&veb->head)) {
3413                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3414                 return -EACCES;
3415         }
3416
3417         vsi = veb->associate_vsi;
3418         hw = I40E_VSI_TO_HW(vsi);
3419
3420         vsi->uplink_seid = veb->uplink_seid;
3421         i40e_aq_delete_element(hw, veb->seid, NULL);
3422         rte_free(veb);
3423         vsi->veb = NULL;
3424         return I40E_SUCCESS;
3425 }
3426
3427 /* Setup a veb */
3428 static struct i40e_veb *
3429 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3430 {
3431         struct i40e_veb *veb;
3432         int ret;
3433         struct i40e_hw *hw;
3434
3435         if (NULL == pf || vsi == NULL) {
3436                 PMD_DRV_LOG(ERR, "veb setup failed, "
3437                             "associated VSI shouldn't null");
3438                 return NULL;
3439         }
3440         hw = I40E_PF_TO_HW(pf);
3441
3442         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3443         if (!veb) {
3444                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3445                 goto fail;
3446         }
3447
3448         veb->associate_vsi = vsi;
3449         TAILQ_INIT(&veb->head);
3450         veb->uplink_seid = vsi->uplink_seid;
3451
3452         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3453                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3454
3455         if (ret != I40E_SUCCESS) {
3456                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3457                             hw->aq.asq_last_status);
3458                 goto fail;
3459         }
3460
3461         /* get statistics index */
3462         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3463                                 &veb->stats_idx, NULL, NULL, NULL);
3464         if (ret != I40E_SUCCESS) {
3465                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3466                             hw->aq.asq_last_status);
3467                 goto fail;
3468         }
3469
3470         /* Get VEB bandwidth, to be implemented */
3471         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3472         vsi->uplink_seid = veb->seid;
3473
3474         return veb;
3475 fail:
3476         rte_free(veb);
3477         return NULL;
3478 }
3479
3480 int
3481 i40e_vsi_release(struct i40e_vsi *vsi)
3482 {
3483         struct i40e_pf *pf;
3484         struct i40e_hw *hw;
3485         struct i40e_vsi_list *vsi_list;
3486         int ret;
3487         struct i40e_mac_filter *f;
3488
3489         if (!vsi)
3490                 return I40E_SUCCESS;
3491
3492         pf = I40E_VSI_TO_PF(vsi);
3493         hw = I40E_VSI_TO_HW(vsi);
3494
3495         /* VSI has child to attach, release child first */
3496         if (vsi->veb) {
3497                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3498                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3499                                 return -1;
3500                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3501                 }
3502                 i40e_veb_release(vsi->veb);
3503         }
3504
3505         /* Remove all macvlan filters of the VSI */
3506         i40e_vsi_remove_all_macvlan_filter(vsi);
3507         TAILQ_FOREACH(f, &vsi->mac_list, next)
3508                 rte_free(f);
3509
3510         if (vsi->type != I40E_VSI_MAIN) {
3511                 /* Remove vsi from parent's sibling list */
3512                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3513                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3514                         return I40E_ERR_PARAM;
3515                 }
3516                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3517                                 &vsi->sib_vsi_list, list);
3518
3519                 /* Remove all switch element of the VSI */
3520                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3521                 if (ret != I40E_SUCCESS)
3522                         PMD_DRV_LOG(ERR, "Failed to delete element");
3523         }
3524         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3525
3526         if (vsi->type != I40E_VSI_SRIOV)
3527                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3528         rte_free(vsi);
3529
3530         return I40E_SUCCESS;
3531 }
3532
3533 static int
3534 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3535 {
3536         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3537         struct i40e_aqc_remove_macvlan_element_data def_filter;
3538         struct i40e_mac_filter_info filter;
3539         int ret;
3540
3541         if (vsi->type != I40E_VSI_MAIN)
3542                 return I40E_ERR_CONFIG;
3543         memset(&def_filter, 0, sizeof(def_filter));
3544         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3545                                         ETH_ADDR_LEN);
3546         def_filter.vlan_tag = 0;
3547         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3548                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3549         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3550         if (ret != I40E_SUCCESS) {
3551                 struct i40e_mac_filter *f;
3552                 struct ether_addr *mac;
3553
3554                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3555                             "macvlan filter");
3556                 /* It needs to add the permanent mac into mac list */
3557                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3558                 if (f == NULL) {
3559                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3560                         return I40E_ERR_NO_MEMORY;
3561                 }
3562                 mac = &f->mac_info.mac_addr;
3563                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3564                                 ETH_ADDR_LEN);
3565                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3566                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3567                 vsi->mac_num++;
3568
3569                 return ret;
3570         }
3571         (void)rte_memcpy(&filter.mac_addr,
3572                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3573         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3574         return i40e_vsi_add_mac(vsi, &filter);
3575 }
3576
3577 static int
3578 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3579 {
3580         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3581         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3582         struct i40e_hw *hw = &vsi->adapter->hw;
3583         i40e_status ret;
3584         int i;
3585
3586         memset(&bw_config, 0, sizeof(bw_config));
3587         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3588         if (ret != I40E_SUCCESS) {
3589                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3590                             hw->aq.asq_last_status);
3591                 return ret;
3592         }
3593
3594         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3595         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3596                                         &ets_sla_config, NULL);
3597         if (ret != I40E_SUCCESS) {
3598                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3599                             "configuration %u", hw->aq.asq_last_status);
3600                 return ret;
3601         }
3602
3603         /* Not store the info yet, just print out */
3604         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3605         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3606         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3607                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3608                             ets_sla_config.share_credits[i]);
3609                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3610                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3611                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3612                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3613                             (i * 4));
3614         }
3615
3616         return 0;
3617 }
3618
3619 /* Setup a VSI */
3620 struct i40e_vsi *
3621 i40e_vsi_setup(struct i40e_pf *pf,
3622                enum i40e_vsi_type type,
3623                struct i40e_vsi *uplink_vsi,
3624                uint16_t user_param)
3625 {
3626         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3627         struct i40e_vsi *vsi;
3628         struct i40e_mac_filter_info filter;
3629         int ret;
3630         struct i40e_vsi_context ctxt;
3631         struct ether_addr broadcast =
3632                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3633
3634         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3635                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3636                             "VSI link shouldn't be NULL");
3637                 return NULL;
3638         }
3639
3640         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3641                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3642                             "uplink VSI should be NULL");
3643                 return NULL;
3644         }
3645
3646         /* If uplink vsi didn't setup VEB, create one first */
3647         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3648                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3649
3650                 if (NULL == uplink_vsi->veb) {
3651                         PMD_DRV_LOG(ERR, "VEB setup failed");
3652                         return NULL;
3653                 }
3654         }
3655
3656         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3657         if (!vsi) {
3658                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3659                 return NULL;
3660         }
3661         TAILQ_INIT(&vsi->mac_list);
3662         vsi->type = type;
3663         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3664         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3665         vsi->parent_vsi = uplink_vsi;
3666         vsi->user_param = user_param;
3667         /* Allocate queues */
3668         switch (vsi->type) {
3669         case I40E_VSI_MAIN  :
3670                 vsi->nb_qps = pf->lan_nb_qps;
3671                 break;
3672         case I40E_VSI_SRIOV :
3673                 vsi->nb_qps = pf->vf_nb_qps;
3674                 break;
3675         case I40E_VSI_VMDQ2:
3676                 vsi->nb_qps = pf->vmdq_nb_qps;
3677                 break;
3678         case I40E_VSI_FDIR:
3679                 vsi->nb_qps = pf->fdir_nb_qps;
3680                 break;
3681         default:
3682                 goto fail_mem;
3683         }
3684         /*
3685          * The filter status descriptor is reported in rx queue 0,
3686          * while the tx queue for fdir filter programming has no
3687          * such constraints, can be non-zero queues.
3688          * To simplify it, choose FDIR vsi use queue 0 pair.
3689          * To make sure it will use queue 0 pair, queue allocation
3690          * need be done before this function is called
3691          */
3692         if (type != I40E_VSI_FDIR) {
3693                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3694                         if (ret < 0) {
3695                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3696                                                 vsi->seid, ret);
3697                                 goto fail_mem;
3698                         }
3699                         vsi->base_queue = ret;
3700         } else
3701                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3702
3703         /* VF has MSIX interrupt in VF range, don't allocate here */
3704         if (type != I40E_VSI_SRIOV) {
3705                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3706                 if (ret < 0) {
3707                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3708                         goto fail_queue_alloc;
3709                 }
3710                 vsi->msix_intr = ret;
3711         } else
3712                 vsi->msix_intr = 0;
3713         /* Add VSI */
3714         if (type == I40E_VSI_MAIN) {
3715                 /* For main VSI, no need to add since it's default one */
3716                 vsi->uplink_seid = pf->mac_seid;
3717                 vsi->seid = pf->main_vsi_seid;
3718                 /* Bind queues with specific MSIX interrupt */
3719                 /**
3720                  * Needs 2 interrupt at least, one for misc cause which will
3721                  * enabled from OS side, Another for queues binding the
3722                  * interrupt from device side only.
3723                  */
3724
3725                 /* Get default VSI parameters from hardware */
3726                 memset(&ctxt, 0, sizeof(ctxt));
3727                 ctxt.seid = vsi->seid;
3728                 ctxt.pf_num = hw->pf_id;
3729                 ctxt.uplink_seid = vsi->uplink_seid;
3730                 ctxt.vf_num = 0;
3731                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3732                 if (ret != I40E_SUCCESS) {
3733                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3734                         goto fail_msix_alloc;
3735                 }
3736                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3737                         sizeof(struct i40e_aqc_vsi_properties_data));
3738                 vsi->vsi_id = ctxt.vsi_number;
3739                 vsi->info.valid_sections = 0;
3740
3741                 /* Configure tc, enabled TC0 only */
3742                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3743                         I40E_SUCCESS) {
3744                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3745                         goto fail_msix_alloc;
3746                 }
3747
3748                 /* TC, queue mapping */
3749                 memset(&ctxt, 0, sizeof(ctxt));
3750                 vsi->info.valid_sections |=
3751                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3752                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3753                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3754                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3755                         sizeof(struct i40e_aqc_vsi_properties_data));
3756                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3757                                                 I40E_DEFAULT_TCMAP);
3758                 if (ret != I40E_SUCCESS) {
3759                         PMD_DRV_LOG(ERR, "Failed to configure "
3760                                     "TC queue mapping");
3761                         goto fail_msix_alloc;
3762                 }
3763                 ctxt.seid = vsi->seid;
3764                 ctxt.pf_num = hw->pf_id;
3765                 ctxt.uplink_seid = vsi->uplink_seid;
3766                 ctxt.vf_num = 0;
3767
3768                 /* Update VSI parameters */
3769                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3770                 if (ret != I40E_SUCCESS) {
3771                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3772                         goto fail_msix_alloc;
3773                 }
3774
3775                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3776                                                 sizeof(vsi->info.tc_mapping));
3777                 (void)rte_memcpy(&vsi->info.queue_mapping,
3778                                 &ctxt.info.queue_mapping,
3779                         sizeof(vsi->info.queue_mapping));
3780                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3781                 vsi->info.valid_sections = 0;
3782
3783                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3784                                 ETH_ADDR_LEN);
3785
3786                 /**
3787                  * Updating default filter settings are necessary to prevent
3788                  * reception of tagged packets.
3789                  * Some old firmware configurations load a default macvlan
3790                  * filter which accepts both tagged and untagged packets.
3791                  * The updating is to use a normal filter instead if needed.
3792                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3793                  * The firmware with correct configurations load the default
3794                  * macvlan filter which is expected and cannot be removed.
3795                  */
3796                 i40e_update_default_filter_setting(vsi);
3797                 i40e_config_qinq(hw, vsi);
3798         } else if (type == I40E_VSI_SRIOV) {
3799                 memset(&ctxt, 0, sizeof(ctxt));
3800                 /**
3801                  * For other VSI, the uplink_seid equals to uplink VSI's
3802                  * uplink_seid since they share same VEB
3803                  */
3804                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3805                 ctxt.pf_num = hw->pf_id;
3806                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3807                 ctxt.uplink_seid = vsi->uplink_seid;
3808                 ctxt.connection_type = 0x1;
3809                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3810
3811                 /**
3812                  * Do not configure switch ID to enable VEB switch by
3813                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3814                  * if the source mac address of packet sent from VF is not
3815                  * listed in the VEB's mac table, the VEB will switch the
3816                  * packet back to the VF. Need to enable it when HW issue
3817                  * is fixed.
3818                  */
3819
3820                 /* Configure port/vlan */
3821                 ctxt.info.valid_sections |=
3822                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3823                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3824                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3825                                                 I40E_DEFAULT_TCMAP);
3826                 if (ret != I40E_SUCCESS) {
3827                         PMD_DRV_LOG(ERR, "Failed to configure "
3828                                     "TC queue mapping");
3829                         goto fail_msix_alloc;
3830                 }
3831                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3832                 ctxt.info.valid_sections |=
3833                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3834                 /**
3835                  * Since VSI is not created yet, only configure parameter,
3836                  * will add vsi below.
3837                  */
3838
3839                 i40e_config_qinq(hw, vsi);
3840         } else if (type == I40E_VSI_VMDQ2) {
3841                 memset(&ctxt, 0, sizeof(ctxt));
3842                 /*
3843                  * For other VSI, the uplink_seid equals to uplink VSI's
3844                  * uplink_seid since they share same VEB
3845                  */
3846                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3847                 ctxt.pf_num = hw->pf_id;
3848                 ctxt.vf_num = 0;
3849                 ctxt.uplink_seid = vsi->uplink_seid;
3850                 ctxt.connection_type = 0x1;
3851                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3852
3853                 ctxt.info.valid_sections |=
3854                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3855                 /* user_param carries flag to enable loop back */
3856                 if (user_param) {
3857                         ctxt.info.switch_id =
3858                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3859                         ctxt.info.switch_id |=
3860                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3861                 }
3862
3863                 /* Configure port/vlan */
3864                 ctxt.info.valid_sections |=
3865                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3866                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3867                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3868                                                 I40E_DEFAULT_TCMAP);
3869                 if (ret != I40E_SUCCESS) {
3870                         PMD_DRV_LOG(ERR, "Failed to configure "
3871                                         "TC queue mapping");
3872                         goto fail_msix_alloc;
3873                 }
3874                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3875                 ctxt.info.valid_sections |=
3876                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3877         } else if (type == I40E_VSI_FDIR) {
3878                 memset(&ctxt, 0, sizeof(ctxt));
3879                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3880                 ctxt.pf_num = hw->pf_id;
3881                 ctxt.vf_num = 0;
3882                 ctxt.uplink_seid = vsi->uplink_seid;
3883                 ctxt.connection_type = 0x1;     /* regular data port */
3884                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3885                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3886                                                 I40E_DEFAULT_TCMAP);
3887                 if (ret != I40E_SUCCESS) {
3888                         PMD_DRV_LOG(ERR, "Failed to configure "
3889                                         "TC queue mapping.");
3890                         goto fail_msix_alloc;
3891                 }
3892                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3893                 ctxt.info.valid_sections |=
3894                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3895         } else {
3896                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3897                 goto fail_msix_alloc;
3898         }
3899
3900         if (vsi->type != I40E_VSI_MAIN) {
3901                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3902                 if (ret != I40E_SUCCESS) {
3903                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3904                                     hw->aq.asq_last_status);
3905                         goto fail_msix_alloc;
3906                 }
3907                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3908                 vsi->info.valid_sections = 0;
3909                 vsi->seid = ctxt.seid;
3910                 vsi->vsi_id = ctxt.vsi_number;
3911                 vsi->sib_vsi_list.vsi = vsi;
3912                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3913                                 &vsi->sib_vsi_list, list);
3914         }
3915
3916         /* MAC/VLAN configuration */
3917         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3918         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3919
3920         ret = i40e_vsi_add_mac(vsi, &filter);
3921         if (ret != I40E_SUCCESS) {
3922                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3923                 goto fail_msix_alloc;
3924         }
3925
3926         /* Get VSI BW information */
3927         i40e_vsi_dump_bw_config(vsi);
3928         return vsi;
3929 fail_msix_alloc:
3930         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3931 fail_queue_alloc:
3932         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3933 fail_mem:
3934         rte_free(vsi);
3935         return NULL;
3936 }
3937
3938 /* Configure vlan stripping on or off */
3939 int
3940 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3941 {
3942         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3943         struct i40e_vsi_context ctxt;
3944         uint8_t vlan_flags;
3945         int ret = I40E_SUCCESS;
3946
3947         /* Check if it has been already on or off */
3948         if (vsi->info.valid_sections &
3949                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3950                 if (on) {
3951                         if ((vsi->info.port_vlan_flags &
3952                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3953                                 return 0; /* already on */
3954                 } else {
3955                         if ((vsi->info.port_vlan_flags &
3956                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3957                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3958                                 return 0; /* already off */
3959                 }
3960         }
3961
3962         if (on)
3963                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3964         else
3965                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3966         vsi->info.valid_sections =
3967                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3968         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3969         vsi->info.port_vlan_flags |= vlan_flags;
3970         ctxt.seid = vsi->seid;
3971         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3972         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3973         if (ret)
3974                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3975                             on ? "enable" : "disable");
3976
3977         return ret;
3978 }
3979
3980 static int
3981 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3982 {
3983         struct rte_eth_dev_data *data = dev->data;
3984         int ret;
3985
3986         /* Apply vlan offload setting */
3987         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3988
3989         /* Apply double-vlan setting, not implemented yet */
3990
3991         /* Apply pvid setting */
3992         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3993                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3994         if (ret)
3995                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3996
3997         return ret;
3998 }
3999
4000 static int
4001 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4002 {
4003         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4004
4005         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4006 }
4007
4008 static int
4009 i40e_update_flow_control(struct i40e_hw *hw)
4010 {
4011 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4012         struct i40e_link_status link_status;
4013         uint32_t rxfc = 0, txfc = 0, reg;
4014         uint8_t an_info;
4015         int ret;
4016
4017         memset(&link_status, 0, sizeof(link_status));
4018         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4019         if (ret != I40E_SUCCESS) {
4020                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4021                 goto write_reg; /* Disable flow control */
4022         }
4023
4024         an_info = hw->phy.link_info.an_info;
4025         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4026                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4027                 ret = I40E_ERR_NOT_READY;
4028                 goto write_reg; /* Disable flow control */
4029         }
4030         /**
4031          * If link auto negotiation is enabled, flow control needs to
4032          * be configured according to it
4033          */
4034         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4035         case I40E_LINK_PAUSE_RXTX:
4036                 rxfc = 1;
4037                 txfc = 1;
4038                 hw->fc.current_mode = I40E_FC_FULL;
4039                 break;
4040         case I40E_AQ_LINK_PAUSE_RX:
4041                 rxfc = 1;
4042                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4043                 break;
4044         case I40E_AQ_LINK_PAUSE_TX:
4045                 txfc = 1;
4046                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4047                 break;
4048         default:
4049                 hw->fc.current_mode = I40E_FC_NONE;
4050                 break;
4051         }
4052
4053 write_reg:
4054         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4055                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4056         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4057         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4058         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4059         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4060
4061         return ret;
4062 }
4063
4064 /* PF setup */
4065 static int
4066 i40e_pf_setup(struct i40e_pf *pf)
4067 {
4068         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4069         struct i40e_filter_control_settings settings;
4070         struct i40e_vsi *vsi;
4071         int ret;
4072
4073         /* Clear all stats counters */
4074         pf->offset_loaded = FALSE;
4075         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4076         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4077
4078         ret = i40e_pf_get_switch_config(pf);
4079         if (ret != I40E_SUCCESS) {
4080                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4081                 return ret;
4082         }
4083         if (pf->flags & I40E_FLAG_FDIR) {
4084                 /* make queue allocated first, let FDIR use queue pair 0*/
4085                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4086                 if (ret != I40E_FDIR_QUEUE_ID) {
4087                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4088                                     " ret =%d", ret);
4089                         pf->flags &= ~I40E_FLAG_FDIR;
4090                 }
4091         }
4092         /*  main VSI setup */
4093         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4094         if (!vsi) {
4095                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4096                 return I40E_ERR_NOT_READY;
4097         }
4098         pf->main_vsi = vsi;
4099
4100         /* Configure filter control */
4101         memset(&settings, 0, sizeof(settings));
4102         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4103                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4104         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4105                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4106         else {
4107                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4108                                                 hw->func_caps.rss_table_size);
4109                 return I40E_ERR_PARAM;
4110         }
4111         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4112                         "size: %u\n", hw->func_caps.rss_table_size);
4113         pf->hash_lut_size = hw->func_caps.rss_table_size;
4114
4115         /* Enable ethtype and macvlan filters */
4116         settings.enable_ethtype = TRUE;
4117         settings.enable_macvlan = TRUE;
4118         ret = i40e_set_filter_control(hw, &settings);
4119         if (ret)
4120                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4121                                                                 ret);
4122
4123         /* Update flow control according to the auto negotiation */
4124         i40e_update_flow_control(hw);
4125
4126         return I40E_SUCCESS;
4127 }
4128
4129 int
4130 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4131 {
4132         uint32_t reg;
4133         uint16_t j;
4134
4135         /**
4136          * Set or clear TX Queue Disable flags,
4137          * which is required by hardware.
4138          */
4139         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4140         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4141
4142         /* Wait until the request is finished */
4143         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4144                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4145                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4146                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4147                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4148                                                         & 0x1))) {
4149                         break;
4150                 }
4151         }
4152         if (on) {
4153                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4154                         return I40E_SUCCESS; /* already on, skip next steps */
4155
4156                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4157                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4158         } else {
4159                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4160                         return I40E_SUCCESS; /* already off, skip next steps */
4161                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4162         }
4163         /* Write the register */
4164         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4165         /* Check the result */
4166         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4167                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4168                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4169                 if (on) {
4170                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4171                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4172                                 break;
4173                 } else {
4174                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4175                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4176                                 break;
4177                 }
4178         }
4179         /* Check if it is timeout */
4180         if (j >= I40E_CHK_Q_ENA_COUNT) {
4181                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4182                             (on ? "enable" : "disable"), q_idx);
4183                 return I40E_ERR_TIMEOUT;
4184         }
4185
4186         return I40E_SUCCESS;
4187 }
4188
4189 /* Swith on or off the tx queues */
4190 static int
4191 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4192 {
4193         struct rte_eth_dev_data *dev_data = pf->dev_data;
4194         struct i40e_tx_queue *txq;
4195         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4196         uint16_t i;
4197         int ret;
4198
4199         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4200                 txq = dev_data->tx_queues[i];
4201                 /* Don't operate the queue if not configured or
4202                  * if starting only per queue */
4203                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4204                         continue;
4205                 if (on)
4206                         ret = i40e_dev_tx_queue_start(dev, i);
4207                 else
4208                         ret = i40e_dev_tx_queue_stop(dev, i);
4209                 if ( ret != I40E_SUCCESS)
4210                         return ret;
4211         }
4212
4213         return I40E_SUCCESS;
4214 }
4215
4216 int
4217 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4218 {
4219         uint32_t reg;
4220         uint16_t j;
4221
4222         /* Wait until the request is finished */
4223         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4224                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4225                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4226                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4227                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4228                         break;
4229         }
4230
4231         if (on) {
4232                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4233                         return I40E_SUCCESS; /* Already on, skip next steps */
4234                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4235         } else {
4236                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4237                         return I40E_SUCCESS; /* Already off, skip next steps */
4238                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4239         }
4240
4241         /* Write the register */
4242         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4243         /* Check the result */
4244         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4245                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4246                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4247                 if (on) {
4248                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4249                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4250                                 break;
4251                 } else {
4252                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4253                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4254                                 break;
4255                 }
4256         }
4257
4258         /* Check if it is timeout */
4259         if (j >= I40E_CHK_Q_ENA_COUNT) {
4260                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4261                             (on ? "enable" : "disable"), q_idx);
4262                 return I40E_ERR_TIMEOUT;
4263         }
4264
4265         return I40E_SUCCESS;
4266 }
4267 /* Switch on or off the rx queues */
4268 static int
4269 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4270 {
4271         struct rte_eth_dev_data *dev_data = pf->dev_data;
4272         struct i40e_rx_queue *rxq;
4273         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4274         uint16_t i;
4275         int ret;
4276
4277         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4278                 rxq = dev_data->rx_queues[i];
4279                 /* Don't operate the queue if not configured or
4280                  * if starting only per queue */
4281                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4282                         continue;
4283                 if (on)
4284                         ret = i40e_dev_rx_queue_start(dev, i);
4285                 else
4286                         ret = i40e_dev_rx_queue_stop(dev, i);
4287                 if (ret != I40E_SUCCESS)
4288                         return ret;
4289         }
4290
4291         return I40E_SUCCESS;
4292 }
4293
4294 /* Switch on or off all the rx/tx queues */
4295 int
4296 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4297 {
4298         int ret;
4299
4300         if (on) {
4301                 /* enable rx queues before enabling tx queues */
4302                 ret = i40e_dev_switch_rx_queues(pf, on);
4303                 if (ret) {
4304                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4305                         return ret;
4306                 }
4307                 ret = i40e_dev_switch_tx_queues(pf, on);
4308         } else {
4309                 /* Stop tx queues before stopping rx queues */
4310                 ret = i40e_dev_switch_tx_queues(pf, on);
4311                 if (ret) {
4312                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4313                         return ret;
4314                 }
4315                 ret = i40e_dev_switch_rx_queues(pf, on);
4316         }
4317
4318         return ret;
4319 }
4320
4321 /* Initialize VSI for TX */
4322 static int
4323 i40e_dev_tx_init(struct i40e_pf *pf)
4324 {
4325         struct rte_eth_dev_data *data = pf->dev_data;
4326         uint16_t i;
4327         uint32_t ret = I40E_SUCCESS;
4328         struct i40e_tx_queue *txq;
4329
4330         for (i = 0; i < data->nb_tx_queues; i++) {
4331                 txq = data->tx_queues[i];
4332                 if (!txq || !txq->q_set)
4333                         continue;
4334                 ret = i40e_tx_queue_init(txq);
4335                 if (ret != I40E_SUCCESS)
4336                         break;
4337         }
4338         if (ret == I40E_SUCCESS)
4339                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4340                                      ->eth_dev);
4341
4342         return ret;
4343 }
4344
4345 /* Initialize VSI for RX */
4346 static int
4347 i40e_dev_rx_init(struct i40e_pf *pf)
4348 {
4349         struct rte_eth_dev_data *data = pf->dev_data;
4350         int ret = I40E_SUCCESS;
4351         uint16_t i;
4352         struct i40e_rx_queue *rxq;
4353
4354         i40e_pf_config_mq_rx(pf);
4355         for (i = 0; i < data->nb_rx_queues; i++) {
4356                 rxq = data->rx_queues[i];
4357                 if (!rxq || !rxq->q_set)
4358                         continue;
4359
4360                 ret = i40e_rx_queue_init(rxq);
4361                 if (ret != I40E_SUCCESS) {
4362                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4363                                     "initialization");
4364                         break;
4365                 }
4366         }
4367         if (ret == I40E_SUCCESS)
4368                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4369                                      ->eth_dev);
4370
4371         return ret;
4372 }
4373
4374 static int
4375 i40e_dev_rxtx_init(struct i40e_pf *pf)
4376 {
4377         int err;
4378
4379         err = i40e_dev_tx_init(pf);
4380         if (err) {
4381                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4382                 return err;
4383         }
4384         err = i40e_dev_rx_init(pf);
4385         if (err) {
4386                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4387                 return err;
4388         }
4389
4390         return err;
4391 }
4392
4393 static int
4394 i40e_vmdq_setup(struct rte_eth_dev *dev)
4395 {
4396         struct rte_eth_conf *conf = &dev->data->dev_conf;
4397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4398         int i, err, conf_vsis, j, loop;
4399         struct i40e_vsi *vsi;
4400         struct i40e_vmdq_info *vmdq_info;
4401         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4402         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4403
4404         /*
4405          * Disable interrupt to avoid message from VF. Furthermore, it will
4406          * avoid race condition in VSI creation/destroy.
4407          */
4408         i40e_pf_disable_irq0(hw);
4409
4410         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4411                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4412                 return -ENOTSUP;
4413         }
4414
4415         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4416         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4417                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4418                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4419                         pf->max_nb_vmdq_vsi);
4420                 return -ENOTSUP;
4421         }
4422
4423         if (pf->vmdq != NULL) {
4424                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4425                 return 0;
4426         }
4427
4428         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4429                                 sizeof(*vmdq_info) * conf_vsis, 0);
4430
4431         if (pf->vmdq == NULL) {
4432                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4433                 return -ENOMEM;
4434         }
4435
4436         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4437
4438         /* Create VMDQ VSI */
4439         for (i = 0; i < conf_vsis; i++) {
4440                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4441                                 vmdq_conf->enable_loop_back);
4442                 if (vsi == NULL) {
4443                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4444                         err = -1;
4445                         goto err_vsi_setup;
4446                 }
4447                 vmdq_info = &pf->vmdq[i];
4448                 vmdq_info->pf = pf;
4449                 vmdq_info->vsi = vsi;
4450         }
4451         pf->nb_cfg_vmdq_vsi = conf_vsis;
4452
4453         /* Configure Vlan */
4454         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4455         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4456                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4457                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4458                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4459                                         vmdq_conf->pool_map[i].vlan_id, j);
4460
4461                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4462                                                 vmdq_conf->pool_map[i].vlan_id);
4463                                 if (err) {
4464                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4465                                         err = -1;
4466                                         goto err_vsi_setup;
4467                                 }
4468                         }
4469                 }
4470         }
4471
4472         i40e_pf_enable_irq0(hw);
4473
4474         return 0;
4475
4476 err_vsi_setup:
4477         for (i = 0; i < conf_vsis; i++)
4478                 if (pf->vmdq[i].vsi == NULL)
4479                         break;
4480                 else
4481                         i40e_vsi_release(pf->vmdq[i].vsi);
4482
4483         rte_free(pf->vmdq);
4484         pf->vmdq = NULL;
4485         i40e_pf_enable_irq0(hw);
4486         return err;
4487 }
4488
4489 static void
4490 i40e_stat_update_32(struct i40e_hw *hw,
4491                    uint32_t reg,
4492                    bool offset_loaded,
4493                    uint64_t *offset,
4494                    uint64_t *stat)
4495 {
4496         uint64_t new_data;
4497
4498         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4499         if (!offset_loaded)
4500                 *offset = new_data;
4501
4502         if (new_data >= *offset)
4503                 *stat = (uint64_t)(new_data - *offset);
4504         else
4505                 *stat = (uint64_t)((new_data +
4506                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4507 }
4508
4509 static void
4510 i40e_stat_update_48(struct i40e_hw *hw,
4511                    uint32_t hireg,
4512                    uint32_t loreg,
4513                    bool offset_loaded,
4514                    uint64_t *offset,
4515                    uint64_t *stat)
4516 {
4517         uint64_t new_data;
4518
4519         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4520         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4521                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4522
4523         if (!offset_loaded)
4524                 *offset = new_data;
4525
4526         if (new_data >= *offset)
4527                 *stat = new_data - *offset;
4528         else
4529                 *stat = (uint64_t)((new_data +
4530                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4531
4532         *stat &= I40E_48_BIT_MASK;
4533 }
4534
4535 /* Disable IRQ0 */
4536 void
4537 i40e_pf_disable_irq0(struct i40e_hw *hw)
4538 {
4539         /* Disable all interrupt types */
4540         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4541         I40E_WRITE_FLUSH(hw);
4542 }
4543
4544 /* Enable IRQ0 */
4545 void
4546 i40e_pf_enable_irq0(struct i40e_hw *hw)
4547 {
4548         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4549                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4550                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4551                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4552         I40E_WRITE_FLUSH(hw);
4553 }
4554
4555 static void
4556 i40e_pf_config_irq0(struct i40e_hw *hw)
4557 {
4558         /* read pending request and disable first */
4559         i40e_pf_disable_irq0(hw);
4560         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4561         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4562                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4563
4564         /* Link no queues with irq0 */
4565         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4566                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4567 }
4568
4569 static void
4570 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4571 {
4572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4574         int i;
4575         uint16_t abs_vf_id;
4576         uint32_t index, offset, val;
4577
4578         if (!pf->vfs)
4579                 return;
4580         /**
4581          * Try to find which VF trigger a reset, use absolute VF id to access
4582          * since the reg is global register.
4583          */
4584         for (i = 0; i < pf->vf_num; i++) {
4585                 abs_vf_id = hw->func_caps.vf_base_id + i;
4586                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4587                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4588                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4589                 /* VFR event occured */
4590                 if (val & (0x1 << offset)) {
4591                         int ret;
4592
4593                         /* Clear the event first */
4594                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4595                                                         (0x1 << offset));
4596                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4597                         /**
4598                          * Only notify a VF reset event occured,
4599                          * don't trigger another SW reset
4600                          */
4601                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4602                         if (ret != I40E_SUCCESS)
4603                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4604                 }
4605         }
4606 }
4607
4608 static void
4609 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4610 {
4611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4612         struct i40e_arq_event_info info;
4613         uint16_t pending, opcode;
4614         int ret;
4615
4616         info.buf_len = I40E_AQ_BUF_SZ;
4617         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4618         if (!info.msg_buf) {
4619                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4620                 return;
4621         }
4622
4623         pending = 1;
4624         while (pending) {
4625                 ret = i40e_clean_arq_element(hw, &info, &pending);
4626
4627                 if (ret != I40E_SUCCESS) {
4628                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4629                                     "aq_err: %u", hw->aq.asq_last_status);
4630                         break;
4631                 }
4632                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4633
4634                 switch (opcode) {
4635                 case i40e_aqc_opc_send_msg_to_pf:
4636                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4637                         i40e_pf_host_handle_vf_msg(dev,
4638                                         rte_le_to_cpu_16(info.desc.retval),
4639                                         rte_le_to_cpu_32(info.desc.cookie_high),
4640                                         rte_le_to_cpu_32(info.desc.cookie_low),
4641                                         info.msg_buf,
4642                                         info.msg_len);
4643                         break;
4644                 default:
4645                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4646                                     opcode);
4647                         break;
4648                 }
4649         }
4650         rte_free(info.msg_buf);
4651 }
4652
4653 /*
4654  * Interrupt handler is registered as the alarm callback for handling LSC
4655  * interrupt in a definite of time, in order to wait the NIC into a stable
4656  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4657  * no need for link down interrupt.
4658  */
4659 static void
4660 i40e_dev_interrupt_delayed_handler(void *param)
4661 {
4662         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4663         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4664         uint32_t icr0;
4665
4666         /* read interrupt causes again */
4667         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4668
4669 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4670         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4671                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4672         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4673                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4674         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4675                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4676         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4677                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4678         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4679                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4680                                                                 "state\n");
4681         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4682                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4683         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4684                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4685 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4686
4687         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4688                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4689                 i40e_dev_handle_vfr_event(dev);
4690         }
4691         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4692                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4693                 i40e_dev_handle_aq_msg(dev);
4694         }
4695
4696         /* handle the link up interrupt in an alarm callback */
4697         i40e_dev_link_update(dev, 0);
4698         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4699
4700         i40e_pf_enable_irq0(hw);
4701         rte_intr_enable(&(dev->pci_dev->intr_handle));
4702 }
4703
4704 /**
4705  * Interrupt handler triggered by NIC  for handling
4706  * specific interrupt.
4707  *
4708  * @param handle
4709  *  Pointer to interrupt handle.
4710  * @param param
4711  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4712  *
4713  * @return
4714  *  void
4715  */
4716 static void
4717 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4718                            void *param)
4719 {
4720         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4721         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722         uint32_t icr0;
4723
4724         /* Disable interrupt */
4725         i40e_pf_disable_irq0(hw);
4726
4727         /* read out interrupt causes */
4728         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4729
4730         /* No interrupt event indicated */
4731         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4732                 PMD_DRV_LOG(INFO, "No interrupt event");
4733                 goto done;
4734         }
4735 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4736         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4737                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4738         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4739                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4740         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4741                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4742         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4743                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4744         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4745                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4746         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4747                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4748         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4749                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4750 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4751
4752         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4753                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4754                 i40e_dev_handle_vfr_event(dev);
4755         }
4756         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4757                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4758                 i40e_dev_handle_aq_msg(dev);
4759         }
4760
4761         /* Link Status Change interrupt */
4762         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4763 #define I40E_US_PER_SECOND 1000000
4764                 struct rte_eth_link link;
4765
4766                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4767                 memset(&link, 0, sizeof(link));
4768                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4769                 i40e_dev_link_update(dev, 0);
4770
4771                 /*
4772                  * For link up interrupt, it needs to wait 1 second to let the
4773                  * hardware be a stable state. Otherwise several consecutive
4774                  * interrupts can be observed.
4775                  * For link down interrupt, no need to wait.
4776                  */
4777                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4778                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4779                         return;
4780                 else
4781                         _rte_eth_dev_callback_process(dev,
4782                                 RTE_ETH_EVENT_INTR_LSC);
4783         }
4784
4785 done:
4786         /* Enable interrupt */
4787         i40e_pf_enable_irq0(hw);
4788         rte_intr_enable(&(dev->pci_dev->intr_handle));
4789 }
4790
4791 static int
4792 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4793                          struct i40e_macvlan_filter *filter,
4794                          int total)
4795 {
4796         int ele_num, ele_buff_size;
4797         int num, actual_num, i;
4798         uint16_t flags;
4799         int ret = I40E_SUCCESS;
4800         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4801         struct i40e_aqc_add_macvlan_element_data *req_list;
4802
4803         if (filter == NULL  || total == 0)
4804                 return I40E_ERR_PARAM;
4805         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4806         ele_buff_size = hw->aq.asq_buf_size;
4807
4808         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4809         if (req_list == NULL) {
4810                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4811                 return I40E_ERR_NO_MEMORY;
4812         }
4813
4814         num = 0;
4815         do {
4816                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4817                 memset(req_list, 0, ele_buff_size);
4818
4819                 for (i = 0; i < actual_num; i++) {
4820                         (void)rte_memcpy(req_list[i].mac_addr,
4821                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4822                         req_list[i].vlan_tag =
4823                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4824
4825                         switch (filter[num + i].filter_type) {
4826                         case RTE_MAC_PERFECT_MATCH:
4827                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4828                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4829                                 break;
4830                         case RTE_MACVLAN_PERFECT_MATCH:
4831                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4832                                 break;
4833                         case RTE_MAC_HASH_MATCH:
4834                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4835                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4836                                 break;
4837                         case RTE_MACVLAN_HASH_MATCH:
4838                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4839                                 break;
4840                         default:
4841                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4842                                 ret = I40E_ERR_PARAM;
4843                                 goto DONE;
4844                         }
4845
4846                         req_list[i].queue_number = 0;
4847
4848                         req_list[i].flags = rte_cpu_to_le_16(flags);
4849                 }
4850
4851                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4852                                                 actual_num, NULL);
4853                 if (ret != I40E_SUCCESS) {
4854                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4855                         goto DONE;
4856                 }
4857                 num += actual_num;
4858         } while (num < total);
4859
4860 DONE:
4861         rte_free(req_list);
4862         return ret;
4863 }
4864
4865 static int
4866 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4867                             struct i40e_macvlan_filter *filter,
4868                             int total)
4869 {
4870         int ele_num, ele_buff_size;
4871         int num, actual_num, i;
4872         uint16_t flags;
4873         int ret = I40E_SUCCESS;
4874         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4875         struct i40e_aqc_remove_macvlan_element_data *req_list;
4876
4877         if (filter == NULL  || total == 0)
4878                 return I40E_ERR_PARAM;
4879
4880         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4881         ele_buff_size = hw->aq.asq_buf_size;
4882
4883         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4884         if (req_list == NULL) {
4885                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4886                 return I40E_ERR_NO_MEMORY;
4887         }
4888
4889         num = 0;
4890         do {
4891                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4892                 memset(req_list, 0, ele_buff_size);
4893
4894                 for (i = 0; i < actual_num; i++) {
4895                         (void)rte_memcpy(req_list[i].mac_addr,
4896                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4897                         req_list[i].vlan_tag =
4898                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4899
4900                         switch (filter[num + i].filter_type) {
4901                         case RTE_MAC_PERFECT_MATCH:
4902                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4903                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4904                                 break;
4905                         case RTE_MACVLAN_PERFECT_MATCH:
4906                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4907                                 break;
4908                         case RTE_MAC_HASH_MATCH:
4909                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4910                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4911                                 break;
4912                         case RTE_MACVLAN_HASH_MATCH:
4913                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4914                                 break;
4915                         default:
4916                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4917                                 ret = I40E_ERR_PARAM;
4918                                 goto DONE;
4919                         }
4920                         req_list[i].flags = rte_cpu_to_le_16(flags);
4921                 }
4922
4923                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4924                                                 actual_num, NULL);
4925                 if (ret != I40E_SUCCESS) {
4926                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4927                         goto DONE;
4928                 }
4929                 num += actual_num;
4930         } while (num < total);
4931
4932 DONE:
4933         rte_free(req_list);
4934         return ret;
4935 }
4936
4937 /* Find out specific MAC filter */
4938 static struct i40e_mac_filter *
4939 i40e_find_mac_filter(struct i40e_vsi *vsi,
4940                          struct ether_addr *macaddr)
4941 {
4942         struct i40e_mac_filter *f;
4943
4944         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4945                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4946                         return f;
4947         }
4948
4949         return NULL;
4950 }
4951
4952 static bool
4953 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4954                          uint16_t vlan_id)
4955 {
4956         uint32_t vid_idx, vid_bit;
4957
4958         if (vlan_id > ETH_VLAN_ID_MAX)
4959                 return 0;
4960
4961         vid_idx = I40E_VFTA_IDX(vlan_id);
4962         vid_bit = I40E_VFTA_BIT(vlan_id);
4963
4964         if (vsi->vfta[vid_idx] & vid_bit)
4965                 return 1;
4966         else
4967                 return 0;
4968 }
4969
4970 static void
4971 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4972                          uint16_t vlan_id, bool on)
4973 {
4974         uint32_t vid_idx, vid_bit;
4975
4976         if (vlan_id > ETH_VLAN_ID_MAX)
4977                 return;
4978
4979         vid_idx = I40E_VFTA_IDX(vlan_id);
4980         vid_bit = I40E_VFTA_BIT(vlan_id);
4981
4982         if (on)
4983                 vsi->vfta[vid_idx] |= vid_bit;
4984         else
4985                 vsi->vfta[vid_idx] &= ~vid_bit;
4986 }
4987
4988 /**
4989  * Find all vlan options for specific mac addr,
4990  * return with actual vlan found.
4991  */
4992 static inline int
4993 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4994                            struct i40e_macvlan_filter *mv_f,
4995                            int num, struct ether_addr *addr)
4996 {
4997         int i;
4998         uint32_t j, k;
4999
5000         /**
5001          * Not to use i40e_find_vlan_filter to decrease the loop time,
5002          * although the code looks complex.
5003           */
5004         if (num < vsi->vlan_num)
5005                 return I40E_ERR_PARAM;
5006
5007         i = 0;
5008         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5009                 if (vsi->vfta[j]) {
5010                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5011                                 if (vsi->vfta[j] & (1 << k)) {
5012                                         if (i > num - 1) {
5013                                                 PMD_DRV_LOG(ERR, "vlan number "
5014                                                             "not match");
5015                                                 return I40E_ERR_PARAM;
5016                                         }
5017                                         (void)rte_memcpy(&mv_f[i].macaddr,
5018                                                         addr, ETH_ADDR_LEN);
5019                                         mv_f[i].vlan_id =
5020                                                 j * I40E_UINT32_BIT_SIZE + k;
5021                                         i++;
5022                                 }
5023                         }
5024                 }
5025         }
5026         return I40E_SUCCESS;
5027 }
5028
5029 static inline int
5030 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5031                            struct i40e_macvlan_filter *mv_f,
5032                            int num,
5033                            uint16_t vlan)
5034 {
5035         int i = 0;
5036         struct i40e_mac_filter *f;
5037
5038         if (num < vsi->mac_num)
5039                 return I40E_ERR_PARAM;
5040
5041         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5042                 if (i > num - 1) {
5043                         PMD_DRV_LOG(ERR, "buffer number not match");
5044                         return I40E_ERR_PARAM;
5045                 }
5046                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5047                                 ETH_ADDR_LEN);
5048                 mv_f[i].vlan_id = vlan;
5049                 mv_f[i].filter_type = f->mac_info.filter_type;
5050                 i++;
5051         }
5052
5053         return I40E_SUCCESS;
5054 }
5055
5056 static int
5057 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5058 {
5059         int i, num;
5060         struct i40e_mac_filter *f;
5061         struct i40e_macvlan_filter *mv_f;
5062         int ret = I40E_SUCCESS;
5063
5064         if (vsi == NULL || vsi->mac_num == 0)
5065                 return I40E_ERR_PARAM;
5066
5067         /* Case that no vlan is set */
5068         if (vsi->vlan_num == 0)
5069                 num = vsi->mac_num;
5070         else
5071                 num = vsi->mac_num * vsi->vlan_num;
5072
5073         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5074         if (mv_f == NULL) {
5075                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5076                 return I40E_ERR_NO_MEMORY;
5077         }
5078
5079         i = 0;
5080         if (vsi->vlan_num == 0) {
5081                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5082                         (void)rte_memcpy(&mv_f[i].macaddr,
5083                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5084                         mv_f[i].vlan_id = 0;
5085                         i++;
5086                 }
5087         } else {
5088                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5089                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5090                                         vsi->vlan_num, &f->mac_info.mac_addr);
5091                         if (ret != I40E_SUCCESS)
5092                                 goto DONE;
5093                         i += vsi->vlan_num;
5094                 }
5095         }
5096
5097         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5098 DONE:
5099         rte_free(mv_f);
5100
5101         return ret;
5102 }
5103
5104 int
5105 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5106 {
5107         struct i40e_macvlan_filter *mv_f;
5108         int mac_num;
5109         int ret = I40E_SUCCESS;
5110
5111         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5112                 return I40E_ERR_PARAM;
5113
5114         /* If it's already set, just return */
5115         if (i40e_find_vlan_filter(vsi,vlan))
5116                 return I40E_SUCCESS;
5117
5118         mac_num = vsi->mac_num;
5119
5120         if (mac_num == 0) {
5121                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5122                 return I40E_ERR_PARAM;
5123         }
5124
5125         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5126
5127         if (mv_f == NULL) {
5128                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5129                 return I40E_ERR_NO_MEMORY;
5130         }
5131
5132         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5133
5134         if (ret != I40E_SUCCESS)
5135                 goto DONE;
5136
5137         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5138
5139         if (ret != I40E_SUCCESS)
5140                 goto DONE;
5141
5142         i40e_set_vlan_filter(vsi, vlan, 1);
5143
5144         vsi->vlan_num++;
5145         ret = I40E_SUCCESS;
5146 DONE:
5147         rte_free(mv_f);
5148         return ret;
5149 }
5150
5151 int
5152 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5153 {
5154         struct i40e_macvlan_filter *mv_f;
5155         int mac_num;
5156         int ret = I40E_SUCCESS;
5157
5158         /**
5159          * Vlan 0 is the generic filter for untagged packets
5160          * and can't be removed.
5161          */
5162         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5163                 return I40E_ERR_PARAM;
5164
5165         /* If can't find it, just return */
5166         if (!i40e_find_vlan_filter(vsi, vlan))
5167                 return I40E_ERR_PARAM;
5168
5169         mac_num = vsi->mac_num;
5170
5171         if (mac_num == 0) {
5172                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5173                 return I40E_ERR_PARAM;
5174         }
5175
5176         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5177
5178         if (mv_f == NULL) {
5179                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5180                 return I40E_ERR_NO_MEMORY;
5181         }
5182
5183         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5184
5185         if (ret != I40E_SUCCESS)
5186                 goto DONE;
5187
5188         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5189
5190         if (ret != I40E_SUCCESS)
5191                 goto DONE;
5192
5193         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5194         if (vsi->vlan_num == 1) {
5195                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5196                 if (ret != I40E_SUCCESS)
5197                         goto DONE;
5198
5199                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5200                 if (ret != I40E_SUCCESS)
5201                         goto DONE;
5202         }
5203
5204         i40e_set_vlan_filter(vsi, vlan, 0);
5205
5206         vsi->vlan_num--;
5207         ret = I40E_SUCCESS;
5208 DONE:
5209         rte_free(mv_f);
5210         return ret;
5211 }
5212
5213 int
5214 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5215 {
5216         struct i40e_mac_filter *f;
5217         struct i40e_macvlan_filter *mv_f;
5218         int i, vlan_num = 0;
5219         int ret = I40E_SUCCESS;
5220
5221         /* If it's add and we've config it, return */
5222         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5223         if (f != NULL)
5224                 return I40E_SUCCESS;
5225         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5226                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5227
5228                 /**
5229                  * If vlan_num is 0, that's the first time to add mac,
5230                  * set mask for vlan_id 0.
5231                  */
5232                 if (vsi->vlan_num == 0) {
5233                         i40e_set_vlan_filter(vsi, 0, 1);
5234                         vsi->vlan_num = 1;
5235                 }
5236                 vlan_num = vsi->vlan_num;
5237         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5238                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5239                 vlan_num = 1;
5240
5241         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5242         if (mv_f == NULL) {
5243                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5244                 return I40E_ERR_NO_MEMORY;
5245         }
5246
5247         for (i = 0; i < vlan_num; i++) {
5248                 mv_f[i].filter_type = mac_filter->filter_type;
5249                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5250                                 ETH_ADDR_LEN);
5251         }
5252
5253         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5254                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5255                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5256                                         &mac_filter->mac_addr);
5257                 if (ret != I40E_SUCCESS)
5258                         goto DONE;
5259         }
5260
5261         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5262         if (ret != I40E_SUCCESS)
5263                 goto DONE;
5264
5265         /* Add the mac addr into mac list */
5266         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5267         if (f == NULL) {
5268                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5269                 ret = I40E_ERR_NO_MEMORY;
5270                 goto DONE;
5271         }
5272         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5273                         ETH_ADDR_LEN);
5274         f->mac_info.filter_type = mac_filter->filter_type;
5275         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5276         vsi->mac_num++;
5277
5278         ret = I40E_SUCCESS;
5279 DONE:
5280         rte_free(mv_f);
5281
5282         return ret;
5283 }
5284
5285 int
5286 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5287 {
5288         struct i40e_mac_filter *f;
5289         struct i40e_macvlan_filter *mv_f;
5290         int i, vlan_num;
5291         enum rte_mac_filter_type filter_type;
5292         int ret = I40E_SUCCESS;
5293
5294         /* Can't find it, return an error */
5295         f = i40e_find_mac_filter(vsi, addr);
5296         if (f == NULL)
5297                 return I40E_ERR_PARAM;
5298
5299         vlan_num = vsi->vlan_num;
5300         filter_type = f->mac_info.filter_type;
5301         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5302                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5303                 if (vlan_num == 0) {
5304                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5305                         return I40E_ERR_PARAM;
5306                 }
5307         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5308                         filter_type == RTE_MAC_HASH_MATCH)
5309                 vlan_num = 1;
5310
5311         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5312         if (mv_f == NULL) {
5313                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5314                 return I40E_ERR_NO_MEMORY;
5315         }
5316
5317         for (i = 0; i < vlan_num; i++) {
5318                 mv_f[i].filter_type = filter_type;
5319                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5320                                 ETH_ADDR_LEN);
5321         }
5322         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5323                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5324                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5325                 if (ret != I40E_SUCCESS)
5326                         goto DONE;
5327         }
5328
5329         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5330         if (ret != I40E_SUCCESS)
5331                 goto DONE;
5332
5333         /* Remove the mac addr into mac list */
5334         TAILQ_REMOVE(&vsi->mac_list, f, next);
5335         rte_free(f);
5336         vsi->mac_num--;
5337
5338         ret = I40E_SUCCESS;
5339 DONE:
5340         rte_free(mv_f);
5341         return ret;
5342 }
5343
5344 /* Configure hash enable flags for RSS */
5345 uint64_t
5346 i40e_config_hena(uint64_t flags)
5347 {
5348         uint64_t hena = 0;
5349
5350         if (!flags)
5351                 return hena;
5352
5353         if (flags & ETH_RSS_FRAG_IPV4)
5354                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5355         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5356                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5357         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5358                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5359         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5360                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5361         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5362                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5363         if (flags & ETH_RSS_FRAG_IPV6)
5364                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5365         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5366                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5367         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5368                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5369         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5370                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5371         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5372                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5373         if (flags & ETH_RSS_L2_PAYLOAD)
5374                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5375
5376         return hena;
5377 }
5378
5379 /* Parse the hash enable flags */
5380 uint64_t
5381 i40e_parse_hena(uint64_t flags)
5382 {
5383         uint64_t rss_hf = 0;
5384
5385         if (!flags)
5386                 return rss_hf;
5387         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5388                 rss_hf |= ETH_RSS_FRAG_IPV4;
5389         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5390                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5391         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5392                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5393         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5394                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5395         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5396                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5397         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5398                 rss_hf |= ETH_RSS_FRAG_IPV6;
5399         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5400                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5401         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5402                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5403         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5404                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5405         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5406                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5407         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5408                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5409
5410         return rss_hf;
5411 }
5412
5413 /* Disable RSS */
5414 static void
5415 i40e_pf_disable_rss(struct i40e_pf *pf)
5416 {
5417         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5418         uint64_t hena;
5419
5420         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5421         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5422         hena &= ~I40E_RSS_HENA_ALL;
5423         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5424         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5425         I40E_WRITE_FLUSH(hw);
5426 }
5427
5428 static int
5429 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5430 {
5431         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5432         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5433         int ret = 0;
5434
5435         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5436                 sizeof(uint32_t)))
5437                 return -EINVAL;
5438
5439         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5440                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5441                         (struct i40e_aqc_get_set_rss_key_data *)key;
5442
5443                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5444                 if (ret)
5445                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5446                                      "via AQ");
5447         } else {
5448                 uint32_t *hash_key = (uint32_t *)key;
5449                 uint16_t i;
5450
5451                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5452                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5453                 I40E_WRITE_FLUSH(hw);
5454         }
5455
5456         return ret;
5457 }
5458
5459 static int
5460 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5461 {
5462         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5463         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5464         int ret;
5465
5466         if (!key || !key_len)
5467                 return -EINVAL;
5468
5469         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5470                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5471                         (struct i40e_aqc_get_set_rss_key_data *)key);
5472                 if (ret) {
5473                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5474                         return ret;
5475                 }
5476         } else {
5477                 uint32_t *key_dw = (uint32_t *)key;
5478                 uint16_t i;
5479
5480                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5481                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5482         }
5483         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5484
5485         return 0;
5486 }
5487
5488 static int
5489 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5490 {
5491         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5492         uint64_t rss_hf;
5493         uint64_t hena;
5494         int ret;
5495
5496         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5497                                rss_conf->rss_key_len);
5498         if (ret)
5499                 return ret;
5500
5501         rss_hf = rss_conf->rss_hf;
5502         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5503         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5504         hena &= ~I40E_RSS_HENA_ALL;
5505         hena |= i40e_config_hena(rss_hf);
5506         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5507         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5508         I40E_WRITE_FLUSH(hw);
5509
5510         return 0;
5511 }
5512
5513 static int
5514 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5515                          struct rte_eth_rss_conf *rss_conf)
5516 {
5517         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5518         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5519         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5520         uint64_t hena;
5521
5522         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5523         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5524         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5525                 if (rss_hf != 0) /* Enable RSS */
5526                         return -EINVAL;
5527                 return 0; /* Nothing to do */
5528         }
5529         /* RSS enabled */
5530         if (rss_hf == 0) /* Disable RSS */
5531                 return -EINVAL;
5532
5533         return i40e_hw_rss_hash_set(pf, rss_conf);
5534 }
5535
5536 static int
5537 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5538                            struct rte_eth_rss_conf *rss_conf)
5539 {
5540         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5542         uint64_t hena;
5543
5544         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5545                          &rss_conf->rss_key_len);
5546
5547         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5548         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5549         rss_conf->rss_hf = i40e_parse_hena(hena);
5550
5551         return 0;
5552 }
5553
5554 static int
5555 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5556 {
5557         switch (filter_type) {
5558         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5559                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5560                 break;
5561         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5562                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5563                 break;
5564         case RTE_TUNNEL_FILTER_IMAC_TENID:
5565                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5566                 break;
5567         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5568                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5569                 break;
5570         case ETH_TUNNEL_FILTER_IMAC:
5571                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5572                 break;
5573         default:
5574                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5575                 return -EINVAL;
5576         }
5577
5578         return 0;
5579 }
5580
5581 static int
5582 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5583                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5584                         uint8_t add)
5585 {
5586         uint16_t ip_type;
5587         uint8_t tun_type = 0;
5588         int val, ret = 0;
5589         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5590         struct i40e_vsi *vsi = pf->main_vsi;
5591         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5592         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5593
5594         cld_filter = rte_zmalloc("tunnel_filter",
5595                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5596                 0);
5597
5598         if (NULL == cld_filter) {
5599                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5600                 return -EINVAL;
5601         }
5602         pfilter = cld_filter;
5603
5604         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5605                         sizeof(struct ether_addr));
5606         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5607                         sizeof(struct ether_addr));
5608
5609         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5610         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5611                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5612                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5613                                 &tunnel_filter->ip_addr,
5614                                 sizeof(pfilter->ipaddr.v4.data));
5615         } else {
5616                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5617                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5618                                 &tunnel_filter->ip_addr,
5619                                 sizeof(pfilter->ipaddr.v6.data));
5620         }
5621
5622         /* check tunneled type */
5623         switch (tunnel_filter->tunnel_type) {
5624         case RTE_TUNNEL_TYPE_VXLAN:
5625                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5626                 break;
5627         case RTE_TUNNEL_TYPE_NVGRE:
5628                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5629                 break;
5630         default:
5631                 /* Other tunnel types is not supported. */
5632                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5633                 rte_free(cld_filter);
5634                 return -EINVAL;
5635         }
5636
5637         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5638                                                 &pfilter->flags);
5639         if (val < 0) {
5640                 rte_free(cld_filter);
5641                 return -EINVAL;
5642         }
5643
5644         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5645                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5646         pfilter->tenant_id = tunnel_filter->tenant_id;
5647         pfilter->queue_number = tunnel_filter->queue_id;
5648
5649         if (add)
5650                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5651         else
5652                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5653                                                 cld_filter, 1);
5654
5655         rte_free(cld_filter);
5656         return ret;
5657 }
5658
5659 static int
5660 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5661 {
5662         uint8_t i;
5663
5664         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5665                 if (pf->vxlan_ports[i] == port)
5666                         return i;
5667         }
5668
5669         return -1;
5670 }
5671
5672 static int
5673 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5674 {
5675         int  idx, ret;
5676         uint8_t filter_idx;
5677         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5678
5679         idx = i40e_get_vxlan_port_idx(pf, port);
5680
5681         /* Check if port already exists */
5682         if (idx >= 0) {
5683                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5684                 return -EINVAL;
5685         }
5686
5687         /* Now check if there is space to add the new port */
5688         idx = i40e_get_vxlan_port_idx(pf, 0);
5689         if (idx < 0) {
5690                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5691                         "not adding port %d", port);
5692                 return -ENOSPC;
5693         }
5694
5695         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5696                                         &filter_idx, NULL);
5697         if (ret < 0) {
5698                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5699                 return -1;
5700         }
5701
5702         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5703                          port,  filter_idx);
5704
5705         /* New port: add it and mark its index in the bitmap */
5706         pf->vxlan_ports[idx] = port;
5707         pf->vxlan_bitmap |= (1 << idx);
5708
5709         if (!(pf->flags & I40E_FLAG_VXLAN))
5710                 pf->flags |= I40E_FLAG_VXLAN;
5711
5712         return 0;
5713 }
5714
5715 static int
5716 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5717 {
5718         int idx;
5719         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5720
5721         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5722                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5723                 return -EINVAL;
5724         }
5725
5726         idx = i40e_get_vxlan_port_idx(pf, port);
5727
5728         if (idx < 0) {
5729                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5730                 return -EINVAL;
5731         }
5732
5733         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5734                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5735                 return -1;
5736         }
5737
5738         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5739                         port, idx);
5740
5741         pf->vxlan_ports[idx] = 0;
5742         pf->vxlan_bitmap &= ~(1 << idx);
5743
5744         if (!pf->vxlan_bitmap)
5745                 pf->flags &= ~I40E_FLAG_VXLAN;
5746
5747         return 0;
5748 }
5749
5750 /* Add UDP tunneling port */
5751 static int
5752 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5753                         struct rte_eth_udp_tunnel *udp_tunnel)
5754 {
5755         int ret = 0;
5756         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5757
5758         if (udp_tunnel == NULL)
5759                 return -EINVAL;
5760
5761         switch (udp_tunnel->prot_type) {
5762         case RTE_TUNNEL_TYPE_VXLAN:
5763                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5764                 break;
5765
5766         case RTE_TUNNEL_TYPE_GENEVE:
5767         case RTE_TUNNEL_TYPE_TEREDO:
5768                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5769                 ret = -1;
5770                 break;
5771
5772         default:
5773                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5774                 ret = -1;
5775                 break;
5776         }
5777
5778         return ret;
5779 }
5780
5781 /* Remove UDP tunneling port */
5782 static int
5783 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5784                         struct rte_eth_udp_tunnel *udp_tunnel)
5785 {
5786         int ret = 0;
5787         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5788
5789         if (udp_tunnel == NULL)
5790                 return -EINVAL;
5791
5792         switch (udp_tunnel->prot_type) {
5793         case RTE_TUNNEL_TYPE_VXLAN:
5794                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5795                 break;
5796         case RTE_TUNNEL_TYPE_GENEVE:
5797         case RTE_TUNNEL_TYPE_TEREDO:
5798                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5799                 ret = -1;
5800                 break;
5801         default:
5802                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5803                 ret = -1;
5804                 break;
5805         }
5806
5807         return ret;
5808 }
5809
5810 /* Calculate the maximum number of contiguous PF queues that are configured */
5811 static int
5812 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5813 {
5814         struct rte_eth_dev_data *data = pf->dev_data;
5815         int i, num;
5816         struct i40e_rx_queue *rxq;
5817
5818         num = 0;
5819         for (i = 0; i < pf->lan_nb_qps; i++) {
5820                 rxq = data->rx_queues[i];
5821                 if (rxq && rxq->q_set)
5822                         num++;
5823                 else
5824                         break;
5825         }
5826
5827         return num;
5828 }
5829
5830 /* Configure RSS */
5831 static int
5832 i40e_pf_config_rss(struct i40e_pf *pf)
5833 {
5834         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5835         struct rte_eth_rss_conf rss_conf;
5836         uint32_t i, lut = 0;
5837         uint16_t j, num;
5838
5839         /*
5840          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5841          * It's necessary to calulate the actual PF queues that are configured.
5842          */
5843         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
5844                 num = i40e_pf_calc_configured_queues_num(pf);
5845         else
5846                 num = pf->dev_data->nb_rx_queues;
5847
5848         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
5849         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5850                         num);
5851
5852         if (num == 0) {
5853                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5854                 return -ENOTSUP;
5855         }
5856
5857         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5858                 if (j == num)
5859                         j = 0;
5860                 lut = (lut << 8) | (j & ((0x1 <<
5861                         hw->func_caps.rss_table_entry_width) - 1));
5862                 if ((i & 3) == 3)
5863                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5864         }
5865
5866         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5867         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5868                 i40e_pf_disable_rss(pf);
5869                 return 0;
5870         }
5871         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5872                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5873                 /* Random default keys */
5874                 static uint32_t rss_key_default[] = {0x6b793944,
5875                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5876                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5877                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5878
5879                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5880                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5881                                                         sizeof(uint32_t);
5882         }
5883
5884         return i40e_hw_rss_hash_set(pf, &rss_conf);
5885 }
5886
5887 static int
5888 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5889                         struct rte_eth_tunnel_filter_conf *filter)
5890 {
5891         if (pf == NULL || filter == NULL) {
5892                 PMD_DRV_LOG(ERR, "Invalid parameter");
5893                 return -EINVAL;
5894         }
5895
5896         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5897                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5898                 return -EINVAL;
5899         }
5900
5901         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5902                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5903                 return -EINVAL;
5904         }
5905
5906         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5907                 (is_zero_ether_addr(filter->outer_mac))) {
5908                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5909                 return -EINVAL;
5910         }
5911
5912         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5913                 (is_zero_ether_addr(filter->inner_mac))) {
5914                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5915                 return -EINVAL;
5916         }
5917
5918         return 0;
5919 }
5920
5921 static int
5922 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5923                         void *arg)
5924 {
5925         struct rte_eth_tunnel_filter_conf *filter;
5926         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5927         int ret = I40E_SUCCESS;
5928
5929         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5930
5931         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5932                 return I40E_ERR_PARAM;
5933
5934         switch (filter_op) {
5935         case RTE_ETH_FILTER_NOP:
5936                 if (!(pf->flags & I40E_FLAG_VXLAN))
5937                         ret = I40E_NOT_SUPPORTED;
5938         case RTE_ETH_FILTER_ADD:
5939                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5940                 break;
5941         case RTE_ETH_FILTER_DELETE:
5942                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5943                 break;
5944         default:
5945                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5946                 ret = I40E_ERR_PARAM;
5947                 break;
5948         }
5949
5950         return ret;
5951 }
5952
5953 static int
5954 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5955 {
5956         int ret = 0;
5957         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5958
5959         /* RSS setup */
5960         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5961                 ret = i40e_pf_config_rss(pf);
5962         else
5963                 i40e_pf_disable_rss(pf);
5964
5965         return ret;
5966 }
5967
5968 /* Get the symmetric hash enable configurations per port */
5969 static void
5970 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5971 {
5972         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5973
5974         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5975 }
5976
5977 /* Set the symmetric hash enable configurations per port */
5978 static void
5979 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5980 {
5981         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5982
5983         if (enable > 0) {
5984                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5985                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5986                                                         "been enabled");
5987                         return;
5988                 }
5989                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5990         } else {
5991                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5992                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5993                                                         "been disabled");
5994                         return;
5995                 }
5996                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5997         }
5998         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5999         I40E_WRITE_FLUSH(hw);
6000 }
6001
6002 /*
6003  * Get global configurations of hash function type and symmetric hash enable
6004  * per flow type (pctype). Note that global configuration means it affects all
6005  * the ports on the same NIC.
6006  */
6007 static int
6008 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6009                                    struct rte_eth_hash_global_conf *g_cfg)
6010 {
6011         uint32_t reg, mask = I40E_FLOW_TYPES;
6012         uint16_t i;
6013         enum i40e_filter_pctype pctype;
6014
6015         memset(g_cfg, 0, sizeof(*g_cfg));
6016         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6017         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6018                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6019         else
6020                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6021         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6022                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6023
6024         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6025                 if (!(mask & (1UL << i)))
6026                         continue;
6027                 mask &= ~(1UL << i);
6028                 /* Bit set indicats the coresponding flow type is supported */
6029                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6030                 pctype = i40e_flowtype_to_pctype(i);
6031                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6032                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6033                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6034         }
6035
6036         return 0;
6037 }
6038
6039 static int
6040 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6041 {
6042         uint32_t i;
6043         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6044
6045         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6046                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6047                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6048                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6049                                                 g_cfg->hash_func);
6050                 return -EINVAL;
6051         }
6052
6053         /*
6054          * As i40e supports less than 32 flow types, only first 32 bits need to
6055          * be checked.
6056          */
6057         mask0 = g_cfg->valid_bit_mask[0];
6058         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6059                 if (i == 0) {
6060                         /* Check if any unsupported flow type configured */
6061                         if ((mask0 | i40e_mask) ^ i40e_mask)
6062                                 goto mask_err;
6063                 } else {
6064                         if (g_cfg->valid_bit_mask[i])
6065                                 goto mask_err;
6066                 }
6067         }
6068
6069         return 0;
6070
6071 mask_err:
6072         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6073
6074         return -EINVAL;
6075 }
6076
6077 /*
6078  * Set global configurations of hash function type and symmetric hash enable
6079  * per flow type (pctype). Note any modifying global configuration will affect
6080  * all the ports on the same NIC.
6081  */
6082 static int
6083 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6084                                    struct rte_eth_hash_global_conf *g_cfg)
6085 {
6086         int ret;
6087         uint16_t i;
6088         uint32_t reg;
6089         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6090         enum i40e_filter_pctype pctype;
6091
6092         /* Check the input parameters */
6093         ret = i40e_hash_global_config_check(g_cfg);
6094         if (ret < 0)
6095                 return ret;
6096
6097         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6098                 if (!(mask0 & (1UL << i)))
6099                         continue;
6100                 mask0 &= ~(1UL << i);
6101                 pctype = i40e_flowtype_to_pctype(i);
6102                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6103                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6104                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6105         }
6106
6107         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6108         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6109                 /* Toeplitz */
6110                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6111                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6112                                                                 "Toeplitz");
6113                         goto out;
6114                 }
6115                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6116         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6117                 /* Simple XOR */
6118                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6119                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6120                                                         "Simple XOR");
6121                         goto out;
6122                 }
6123                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6124         } else
6125                 /* Use the default, and keep it as it is */
6126                 goto out;
6127
6128         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6129
6130 out:
6131         I40E_WRITE_FLUSH(hw);
6132
6133         return 0;
6134 }
6135
6136 /**
6137  * Valid input sets for hash and flow director filters per PCTYPE
6138  */
6139 static uint64_t
6140 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6141                 enum rte_filter_type filter)
6142 {
6143         uint64_t valid;
6144
6145         static const uint64_t valid_hash_inset_table[] = {
6146                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6147                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6148                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6149                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6150                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6151                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6152                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6153                         I40E_INSET_FLEX_PAYLOAD,
6154                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6155                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6156                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6157                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6158                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6159                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6160                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6161                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6162                         I40E_INSET_FLEX_PAYLOAD,
6163                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6164                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6165                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6166                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6167                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6168                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6169                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6170                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6171                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6172                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6173                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6174                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6175                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6176                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6177                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6178                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6179                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6180                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6181                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6182                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6183                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6184                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6185                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6186                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6187                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6188                         I40E_INSET_FLEX_PAYLOAD,
6189                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6190                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6191                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6192                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6193                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6194                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6195                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6196                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6197                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6198                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6199                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6200                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6201                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6202                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6203                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6204                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6205                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6206                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6207                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6208                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6209                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6210                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6211                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6212                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6213                         I40E_INSET_FLEX_PAYLOAD,
6214                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6215                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6216                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6217                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6218                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6219                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6220                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6221                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6222                         I40E_INSET_FLEX_PAYLOAD,
6223                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6224                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6225                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6226                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6227                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6228                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6229                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6230                         I40E_INSET_FLEX_PAYLOAD,
6231                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6232                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6233                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6234                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6235                         I40E_INSET_FLEX_PAYLOAD,
6236         };
6237
6238         /**
6239          * Flow director supports only fields defined in
6240          * union rte_eth_fdir_flow.
6241          */
6242         static const uint64_t valid_fdir_inset_table[] = {
6243                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6244                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6245                 I40E_INSET_FLEX_PAYLOAD,
6246                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6247                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6248                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6249                 I40E_INSET_FLEX_PAYLOAD,
6250                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6251                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6252                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6253                 I40E_INSET_FLEX_PAYLOAD,
6254                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6255                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6256                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6257                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6258                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6259                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6260                 I40E_INSET_FLEX_PAYLOAD,
6261                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6262                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6263                 I40E_INSET_FLEX_PAYLOAD,
6264                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6265                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6266                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6267                 I40E_INSET_FLEX_PAYLOAD,
6268                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6269                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6270                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6271                 I40E_INSET_FLEX_PAYLOAD,
6272                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6273                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6274                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6275                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6276                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6277                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6278                 I40E_INSET_FLEX_PAYLOAD,
6279                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6280                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6281         };
6282
6283         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6284                 return 0;
6285         if (filter == RTE_ETH_FILTER_HASH)
6286                 valid = valid_hash_inset_table[pctype];
6287         else
6288                 valid = valid_fdir_inset_table[pctype];
6289
6290         return valid;
6291 }
6292
6293 /**
6294  * Validate if the input set is allowed for a specific PCTYPE
6295  */
6296 static int
6297 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6298                 enum rte_filter_type filter, uint64_t inset)
6299 {
6300         uint64_t valid;
6301
6302         valid = i40e_get_valid_input_set(pctype, filter);
6303         if (inset & (~valid))
6304                 return -EINVAL;
6305
6306         return 0;
6307 }
6308
6309 /* default input set fields combination per pctype */
6310 static uint64_t
6311 i40e_get_default_input_set(uint16_t pctype)
6312 {
6313         static const uint64_t default_inset_table[] = {
6314                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6315                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6316                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6317                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6318                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6319                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6320                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6321                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6322                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6323                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6324                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6325                         I40E_INSET_SCTP_VT,
6326                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6327                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6328                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6329                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6330                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6331                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6332                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6333                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6334                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6335                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6336                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6337                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6338                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6339                         I40E_INSET_SCTP_VT,
6340                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6341                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6342                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6343                         I40E_INSET_LAST_ETHER_TYPE,
6344         };
6345
6346         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6347                 return 0;
6348
6349         return default_inset_table[pctype];
6350 }
6351
6352 /**
6353  * Parse the input set from index to logical bit masks
6354  */
6355 static int
6356 i40e_parse_input_set(uint64_t *inset,
6357                      enum i40e_filter_pctype pctype,
6358                      enum rte_eth_input_set_field *field,
6359                      uint16_t size)
6360 {
6361         uint16_t i, j;
6362         int ret = -EINVAL;
6363
6364         static const struct {
6365                 enum rte_eth_input_set_field field;
6366                 uint64_t inset;
6367         } inset_convert_table[] = {
6368                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6369                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6370                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6371                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6372                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6373                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6374                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6375                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6376                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6377                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6378                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6379                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6380                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6381                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6382                         I40E_INSET_IPV6_NEXT_HDR},
6383                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6384                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6385                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6386                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6387                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6388                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6389                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6390                         I40E_INSET_SCTP_VT},
6391                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6392                         I40E_INSET_TUNNEL_DMAC},
6393                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6394                         I40E_INSET_VLAN_TUNNEL},
6395                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6396                         I40E_INSET_TUNNEL_ID},
6397                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6398                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6399                         I40E_INSET_FLEX_PAYLOAD_W1},
6400                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6401                         I40E_INSET_FLEX_PAYLOAD_W2},
6402                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6403                         I40E_INSET_FLEX_PAYLOAD_W3},
6404                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6405                         I40E_INSET_FLEX_PAYLOAD_W4},
6406                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6407                         I40E_INSET_FLEX_PAYLOAD_W5},
6408                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6409                         I40E_INSET_FLEX_PAYLOAD_W6},
6410                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6411                         I40E_INSET_FLEX_PAYLOAD_W7},
6412                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6413                         I40E_INSET_FLEX_PAYLOAD_W8},
6414         };
6415
6416         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6417                 return ret;
6418
6419         /* Only one item allowed for default or all */
6420         if (size == 1) {
6421                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6422                         *inset = i40e_get_default_input_set(pctype);
6423                         return 0;
6424                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6425                         *inset = I40E_INSET_NONE;
6426                         return 0;
6427                 }
6428         }
6429
6430         for (i = 0, *inset = 0; i < size; i++) {
6431                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6432                         if (field[i] == inset_convert_table[j].field) {
6433                                 *inset |= inset_convert_table[j].inset;
6434                                 break;
6435                         }
6436                 }
6437
6438                 /* It contains unsupported input set, return immediately */
6439                 if (j == RTE_DIM(inset_convert_table))
6440                         return ret;
6441         }
6442
6443         return 0;
6444 }
6445
6446 /**
6447  * Translate the input set from bit masks to register aware bit masks
6448  * and vice versa
6449  */
6450 static uint64_t
6451 i40e_translate_input_set_reg(uint64_t input)
6452 {
6453         uint64_t val = 0;
6454         uint16_t i;
6455
6456         static const struct {
6457                 uint64_t inset;
6458                 uint64_t inset_reg;
6459         } inset_map[] = {
6460                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6461                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6462                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6463                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6464                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6465                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6466                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6467                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6468                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6469                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6470                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6471                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6472                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6473                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6474                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6475                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6476                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6477                 {I40E_INSET_TUNNEL_DMAC,
6478                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6479                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6480                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6481                 {I40E_INSET_TUNNEL_SRC_PORT,
6482                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6483                 {I40E_INSET_TUNNEL_DST_PORT,
6484                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6485                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6486                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6487                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6488                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6489                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6490                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6491                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6492                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6493                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6494         };
6495
6496         if (input == 0)
6497                 return val;
6498
6499         /* Translate input set to register aware inset */
6500         for (i = 0; i < RTE_DIM(inset_map); i++) {
6501                 if (input & inset_map[i].inset)
6502                         val |= inset_map[i].inset_reg;
6503         }
6504
6505         return val;
6506 }
6507
6508 static uint8_t
6509 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6510 {
6511         uint8_t i, idx = 0;
6512
6513         static const struct {
6514                 uint64_t inset;
6515                 uint32_t mask;
6516         } inset_mask_map[] = {
6517                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6518                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6519                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6520                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6521         };
6522
6523         if (!inset || !mask || !nb_elem)
6524                 return 0;
6525
6526         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6527                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6528                         mask[i] = 0;
6529                 return I40E_INSET_MASK_NUM_REG;
6530         }
6531
6532         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6533                 if (idx >= nb_elem)
6534                         break;
6535                 if (inset & inset_mask_map[i].inset) {
6536                         mask[idx] = inset_mask_map[i].mask;
6537                         idx++;
6538                 }
6539         }
6540
6541         return idx;
6542 }
6543
6544 static uint64_t
6545 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6546                             enum i40e_filter_pctype pctype)
6547 {
6548         uint64_t reg = 0;
6549
6550         if (filter == RTE_ETH_FILTER_HASH) {
6551                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6552                 reg <<= I40E_32_BIT_WIDTH;
6553                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6554         } else if (filter == RTE_ETH_FILTER_FDIR) {
6555                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6556                 reg <<= I40E_32_BIT_WIDTH;
6557                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6558         }
6559
6560         return reg;
6561 }
6562
6563 static void
6564 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6565 {
6566         uint32_t reg = I40E_READ_REG(hw, addr);
6567
6568         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6569         if (reg != val)
6570                 I40E_WRITE_REG(hw, addr, val);
6571         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6572                     (uint32_t)I40E_READ_REG(hw, addr));
6573 }
6574
6575 static int
6576 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6577                          enum i40e_filter_pctype pctype,
6578                          enum rte_filter_input_set_op op,
6579                          uint32_t *mask_reg,
6580                          uint8_t num)
6581 {
6582         uint32_t reg;
6583         uint8_t i;
6584
6585         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6586                 return -EINVAL;
6587
6588         if (op == RTE_ETH_INPUT_SET_SELECT) {
6589                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6590                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6591                                              0);
6592                         if (i >= num)
6593                                 continue;
6594                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6595                                              mask_reg[i]);
6596                 }
6597         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6598                 uint8_t j, count = 0;
6599
6600                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6601                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6602                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6603                                 count++;
6604                 }
6605                 if (count + num > I40E_INSET_MASK_NUM_REG)
6606                         return -EINVAL;
6607
6608                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6609                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6610                                              mask_reg[j]);
6611         }
6612
6613         return 0;
6614 }
6615
6616 static int
6617 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6618                        enum i40e_filter_pctype pctype,
6619                        enum rte_filter_input_set_op op,
6620                        uint32_t *mask_reg,
6621                        uint8_t num)
6622 {
6623         uint32_t reg;
6624         uint8_t i;
6625
6626         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6627                 return -EINVAL;
6628
6629         if (op == RTE_ETH_INPUT_SET_SELECT) {
6630                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6631                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6632                                              0);
6633                         if (i >= num)
6634                                 continue;
6635                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6636                                              mask_reg[i]);
6637                 }
6638         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6639                 uint8_t j, count = 0;
6640
6641                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6642                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6643                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6644                                 count++;
6645                 }
6646                 if (count + num > I40E_INSET_MASK_NUM_REG)
6647                         return -EINVAL;
6648
6649                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6650                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6651                                              mask_reg[j]);
6652         }
6653
6654         return 0;
6655 }
6656
6657 int
6658 i40e_filter_inset_select(struct i40e_hw *hw,
6659                          struct rte_eth_input_set_conf *conf,
6660                          enum rte_filter_type filter)
6661 {
6662         enum i40e_filter_pctype pctype;
6663         uint64_t inset_reg = 0, input_set;
6664         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6665         uint8_t num;
6666         int ret;
6667
6668         if (!hw || !conf) {
6669                 PMD_DRV_LOG(ERR, "Invalid pointer");
6670                 return -EFAULT;
6671         }
6672
6673         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6674         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6675                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6676                             conf->flow_type);
6677                 return -EINVAL;
6678         }
6679         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6680                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6681                 return -EINVAL;
6682         }
6683
6684         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6685                                    conf->inset_size);
6686         if (ret) {
6687                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6688                 return -EINVAL;
6689         }
6690         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6691                 PMD_DRV_LOG(ERR, "Invalid input set");
6692                 return -EINVAL;
6693         }
6694
6695         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6696                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6697         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6698                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6699                 return -EINVAL;
6700         }
6701         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6702                                            I40E_INSET_MASK_NUM_REG);
6703         inset_reg |= i40e_translate_input_set_reg(input_set);
6704
6705         if (filter == RTE_ETH_FILTER_HASH) {
6706                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
6707                                                num);
6708                 if (ret)
6709                         return -EINVAL;
6710
6711                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
6712                                       (uint32_t)(inset_reg & UINT32_MAX));
6713                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
6714                                      (uint32_t)((inset_reg >>
6715                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
6716         } else if (filter == RTE_ETH_FILTER_FDIR) {
6717                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
6718                                              num);
6719                 if (ret)
6720                         return -EINVAL;
6721
6722                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
6723                                       (uint32_t)(inset_reg & UINT32_MAX));
6724                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
6725                                      (uint32_t)((inset_reg >>
6726                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
6727         } else {
6728                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6729                 return -EINVAL;
6730         }
6731         I40E_WRITE_FLUSH(hw);
6732
6733         return 0;
6734 }
6735
6736 static int
6737 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6738 {
6739         int ret = 0;
6740
6741         if (!hw || !info) {
6742                 PMD_DRV_LOG(ERR, "Invalid pointer");
6743                 return -EFAULT;
6744         }
6745
6746         switch (info->info_type) {
6747         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6748                 i40e_get_symmetric_hash_enable_per_port(hw,
6749                                         &(info->info.enable));
6750                 break;
6751         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6752                 ret = i40e_get_hash_filter_global_config(hw,
6753                                 &(info->info.global_conf));
6754                 break;
6755         default:
6756                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6757                                                         info->info_type);
6758                 ret = -EINVAL;
6759                 break;
6760         }
6761
6762         return ret;
6763 }
6764
6765 static int
6766 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6767 {
6768         int ret = 0;
6769
6770         if (!hw || !info) {
6771                 PMD_DRV_LOG(ERR, "Invalid pointer");
6772                 return -EFAULT;
6773         }
6774
6775         switch (info->info_type) {
6776         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6777                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
6778                 break;
6779         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6780                 ret = i40e_set_hash_filter_global_config(hw,
6781                                 &(info->info.global_conf));
6782                 break;
6783         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
6784                 ret = i40e_filter_inset_select(hw,
6785                                                &(info->info.input_set_conf),
6786                                                RTE_ETH_FILTER_HASH);
6787                 break;
6788
6789         default:
6790                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6791                                                         info->info_type);
6792                 ret = -EINVAL;
6793                 break;
6794         }
6795
6796         return ret;
6797 }
6798
6799 /* Operations for hash function */
6800 static int
6801 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
6802                       enum rte_filter_op filter_op,
6803                       void *arg)
6804 {
6805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6806         int ret = 0;
6807
6808         switch (filter_op) {
6809         case RTE_ETH_FILTER_NOP:
6810                 break;
6811         case RTE_ETH_FILTER_GET:
6812                 ret = i40e_hash_filter_get(hw,
6813                         (struct rte_eth_hash_filter_info *)arg);
6814                 break;
6815         case RTE_ETH_FILTER_SET:
6816                 ret = i40e_hash_filter_set(hw,
6817                         (struct rte_eth_hash_filter_info *)arg);
6818                 break;
6819         default:
6820                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
6821                                                                 filter_op);
6822                 ret = -ENOTSUP;
6823                 break;
6824         }
6825
6826         return ret;
6827 }
6828
6829 /*
6830  * Configure ethertype filter, which can director packet by filtering
6831  * with mac address and ether_type or only ether_type
6832  */
6833 static int
6834 i40e_ethertype_filter_set(struct i40e_pf *pf,
6835                         struct rte_eth_ethertype_filter *filter,
6836                         bool add)
6837 {
6838         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6839         struct i40e_control_filter_stats stats;
6840         uint16_t flags = 0;
6841         int ret;
6842
6843         if (filter->queue >= pf->dev_data->nb_rx_queues) {
6844                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6845                 return -EINVAL;
6846         }
6847         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6848                 filter->ether_type == ETHER_TYPE_IPv6) {
6849                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6850                         " control packet filter.", filter->ether_type);
6851                 return -EINVAL;
6852         }
6853         if (filter->ether_type == ETHER_TYPE_VLAN)
6854                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
6855                         " not supported.");
6856
6857         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
6858                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
6859         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
6860                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
6861         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
6862
6863         memset(&stats, 0, sizeof(stats));
6864         ret = i40e_aq_add_rem_control_packet_filter(hw,
6865                         filter->mac_addr.addr_bytes,
6866                         filter->ether_type, flags,
6867                         pf->main_vsi->seid,
6868                         filter->queue, add, &stats, NULL);
6869
6870         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
6871                          " mac_etype_used = %u, etype_used = %u,"
6872                          " mac_etype_free = %u, etype_free = %u\n",
6873                          ret, stats.mac_etype_used, stats.etype_used,
6874                          stats.mac_etype_free, stats.etype_free);
6875         if (ret < 0)
6876                 return -ENOSYS;
6877         return 0;
6878 }
6879
6880 /*
6881  * Handle operations for ethertype filter.
6882  */
6883 static int
6884 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
6885                                 enum rte_filter_op filter_op,
6886                                 void *arg)
6887 {
6888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6889         int ret = 0;
6890
6891         if (filter_op == RTE_ETH_FILTER_NOP)
6892                 return ret;
6893
6894         if (arg == NULL) {
6895                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6896                             filter_op);
6897                 return -EINVAL;
6898         }
6899
6900         switch (filter_op) {
6901         case RTE_ETH_FILTER_ADD:
6902                 ret = i40e_ethertype_filter_set(pf,
6903                         (struct rte_eth_ethertype_filter *)arg,
6904                         TRUE);
6905                 break;
6906         case RTE_ETH_FILTER_DELETE:
6907                 ret = i40e_ethertype_filter_set(pf,
6908                         (struct rte_eth_ethertype_filter *)arg,
6909                         FALSE);
6910                 break;
6911         default:
6912                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6913                 ret = -ENOSYS;
6914                 break;
6915         }
6916         return ret;
6917 }
6918
6919 static int
6920 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
6921                      enum rte_filter_type filter_type,
6922                      enum rte_filter_op filter_op,
6923                      void *arg)
6924 {
6925         int ret = 0;
6926
6927         if (dev == NULL)
6928                 return -EINVAL;
6929
6930         switch (filter_type) {
6931         case RTE_ETH_FILTER_HASH:
6932                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
6933                 break;
6934         case RTE_ETH_FILTER_MACVLAN:
6935                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
6936                 break;
6937         case RTE_ETH_FILTER_ETHERTYPE:
6938                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
6939                 break;
6940         case RTE_ETH_FILTER_TUNNEL:
6941                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
6942                 break;
6943         case RTE_ETH_FILTER_FDIR:
6944                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
6945                 break;
6946         default:
6947                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6948                                                         filter_type);
6949                 ret = -EINVAL;
6950                 break;
6951         }
6952
6953         return ret;
6954 }
6955
6956 /*
6957  * As some registers wouldn't be reset unless a global hardware reset,
6958  * hardware initialization is needed to put those registers into an
6959  * expected initial state.
6960  */
6961 static void
6962 i40e_hw_init(struct i40e_hw *hw)
6963 {
6964         /* clear the PF Queue Filter control register */
6965         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
6966
6967         /* Disable symmetric hash per port */
6968         i40e_set_symmetric_hash_enable_per_port(hw, 0);
6969 }
6970
6971 enum i40e_filter_pctype
6972 i40e_flowtype_to_pctype(uint16_t flow_type)
6973 {
6974         static const enum i40e_filter_pctype pctype_table[] = {
6975                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
6976                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
6977                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
6978                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
6979                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
6980                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
6981                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
6982                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
6983                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
6984                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
6985                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
6986                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
6987                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
6988                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
6989                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
6990                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
6991                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
6992                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
6993                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
6994         };
6995
6996         return pctype_table[flow_type];
6997 }
6998
6999 uint16_t
7000 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7001 {
7002         static const uint16_t flowtype_table[] = {
7003                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7004                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7005                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7006                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7007                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7008                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7009                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7010                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7011                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7012                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7013                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7014                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7015                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7016                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7017                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7018                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7019                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7020                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7021                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7022         };
7023
7024         return flowtype_table[pctype];
7025 }
7026
7027 /*
7028  * On X710, performance number is far from the expectation on recent firmware
7029  * versions; on XL710, performance number is also far from the expectation on
7030  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7031  * mode is enabled and port MAC address is equal to the packet destination MAC
7032  * address. The fix for this issue may not be integrated in the following
7033  * firmware version. So the workaround in software driver is needed. It needs
7034  * to modify the initial values of 3 internal only registers for both X710 and
7035  * XL710. Note that the values for X710 or XL710 could be different, and the
7036  * workaround can be removed when it is fixed in firmware in the future.
7037  */
7038
7039 /* For both X710 and XL710 */
7040 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7041 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7042
7043 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7044 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7045
7046 /* For X710 */
7047 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7048 /* For XL710 */
7049 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7050 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7051
7052 static void
7053 i40e_configure_registers(struct i40e_hw *hw)
7054 {
7055         static struct {
7056                 uint32_t addr;
7057                 uint64_t val;
7058         } reg_table[] = {
7059                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7060                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7061                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7062         };
7063         uint64_t reg;
7064         uint32_t i;
7065         int ret;
7066
7067         for (i = 0; i < RTE_DIM(reg_table); i++) {
7068                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7069                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7070                                 reg_table[i].val =
7071                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7072                         else /* For X710 */
7073                                 reg_table[i].val =
7074                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7075                 }
7076
7077                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7078                                                         &reg, NULL);
7079                 if (ret < 0) {
7080                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7081                                                         reg_table[i].addr);
7082                         break;
7083                 }
7084                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7085                                                 reg_table[i].addr, reg);
7086                 if (reg == reg_table[i].val)
7087                         continue;
7088
7089                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7090                                                 reg_table[i].val, NULL);
7091                 if (ret < 0) {
7092                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7093                                 "address of 0x%"PRIx32, reg_table[i].val,
7094                                                         reg_table[i].addr);
7095                         break;
7096                 }
7097                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7098                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7099         }
7100 }
7101
7102 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7103 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7104 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7105 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7106 static int
7107 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7108 {
7109         uint32_t reg;
7110         int ret;
7111
7112         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7113                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7114                 return -EINVAL;
7115         }
7116
7117         /* Configure for double VLAN RX stripping */
7118         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7119         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7120                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7121                 ret = i40e_aq_debug_write_register(hw,
7122                                                    I40E_VSI_TSR(vsi->vsi_id),
7123                                                    reg, NULL);
7124                 if (ret < 0) {
7125                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7126                                     vsi->vsi_id);
7127                         return I40E_ERR_CONFIG;
7128                 }
7129         }
7130
7131         /* Configure for double VLAN TX insertion */
7132         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7133         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7134                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7135                 ret = i40e_aq_debug_write_register(hw,
7136                                                    I40E_VSI_L2TAGSTXVALID(
7137                                                    vsi->vsi_id), reg, NULL);
7138                 if (ret < 0) {
7139                         PMD_DRV_LOG(ERR, "Failed to update "
7140                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7141                         return I40E_ERR_CONFIG;
7142                 }
7143         }
7144
7145         return 0;
7146 }
7147
7148 /**
7149  * i40e_aq_add_mirror_rule
7150  * @hw: pointer to the hardware structure
7151  * @seid: VEB seid to add mirror rule to
7152  * @dst_id: destination vsi seid
7153  * @entries: Buffer which contains the entities to be mirrored
7154  * @count: number of entities contained in the buffer
7155  * @rule_id:the rule_id of the rule to be added
7156  *
7157  * Add a mirror rule for a given veb.
7158  *
7159  **/
7160 static enum i40e_status_code
7161 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7162                         uint16_t seid, uint16_t dst_id,
7163                         uint16_t rule_type, uint16_t *entries,
7164                         uint16_t count, uint16_t *rule_id)
7165 {
7166         struct i40e_aq_desc desc;
7167         struct i40e_aqc_add_delete_mirror_rule cmd;
7168         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7169                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7170                 &desc.params.raw;
7171         uint16_t buff_len;
7172         enum i40e_status_code status;
7173
7174         i40e_fill_default_direct_cmd_desc(&desc,
7175                                           i40e_aqc_opc_add_mirror_rule);
7176         memset(&cmd, 0, sizeof(cmd));
7177
7178         buff_len = sizeof(uint16_t) * count;
7179         desc.datalen = rte_cpu_to_le_16(buff_len);
7180         if (buff_len > 0)
7181                 desc.flags |= rte_cpu_to_le_16(
7182                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7183         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7184                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7185         cmd.num_entries = rte_cpu_to_le_16(count);
7186         cmd.seid = rte_cpu_to_le_16(seid);
7187         cmd.destination = rte_cpu_to_le_16(dst_id);
7188
7189         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7190         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7191         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7192                          "rule_id = %u"
7193                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7194                          hw->aq.asq_last_status, resp->rule_id,
7195                          resp->mirror_rules_used, resp->mirror_rules_free);
7196         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7197
7198         return status;
7199 }
7200
7201 /**
7202  * i40e_aq_del_mirror_rule
7203  * @hw: pointer to the hardware structure
7204  * @seid: VEB seid to add mirror rule to
7205  * @entries: Buffer which contains the entities to be mirrored
7206  * @count: number of entities contained in the buffer
7207  * @rule_id:the rule_id of the rule to be delete
7208  *
7209  * Delete a mirror rule for a given veb.
7210  *
7211  **/
7212 static enum i40e_status_code
7213 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7214                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7215                 uint16_t count, uint16_t rule_id)
7216 {
7217         struct i40e_aq_desc desc;
7218         struct i40e_aqc_add_delete_mirror_rule cmd;
7219         uint16_t buff_len = 0;
7220         enum i40e_status_code status;
7221         void *buff = NULL;
7222
7223         i40e_fill_default_direct_cmd_desc(&desc,
7224                                           i40e_aqc_opc_delete_mirror_rule);
7225         memset(&cmd, 0, sizeof(cmd));
7226         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7227                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7228                                                           I40E_AQ_FLAG_RD));
7229                 cmd.num_entries = count;
7230                 buff_len = sizeof(uint16_t) * count;
7231                 desc.datalen = rte_cpu_to_le_16(buff_len);
7232                 buff = (void *)entries;
7233         } else
7234                 /* rule id is filled in destination field for deleting mirror rule */
7235                 cmd.destination = rte_cpu_to_le_16(rule_id);
7236
7237         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7238                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7239         cmd.seid = rte_cpu_to_le_16(seid);
7240
7241         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7242         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7243
7244         return status;
7245 }
7246
7247 /**
7248  * i40e_mirror_rule_set
7249  * @dev: pointer to the hardware structure
7250  * @mirror_conf: mirror rule info
7251  * @sw_id: mirror rule's sw_id
7252  * @on: enable/disable
7253  *
7254  * set a mirror rule.
7255  *
7256  **/
7257 static int
7258 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7259                         struct rte_eth_mirror_conf *mirror_conf,
7260                         uint8_t sw_id, uint8_t on)
7261 {
7262         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7263         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7264         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7265         struct i40e_mirror_rule *parent = NULL;
7266         uint16_t seid, dst_seid, rule_id;
7267         uint16_t i, j = 0;
7268         int ret;
7269
7270         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7271
7272         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7273                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7274                         " without veb or vfs.");
7275                 return -ENOSYS;
7276         }
7277         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7278                 PMD_DRV_LOG(ERR, "mirror table is full.");
7279                 return -ENOSPC;
7280         }
7281         if (mirror_conf->dst_pool > pf->vf_num) {
7282                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7283                                  mirror_conf->dst_pool);
7284                 return -EINVAL;
7285         }
7286
7287         seid = pf->main_vsi->veb->seid;
7288
7289         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7290                 if (sw_id <= it->index) {
7291                         mirr_rule = it;
7292                         break;
7293                 }
7294                 parent = it;
7295         }
7296         if (mirr_rule && sw_id == mirr_rule->index) {
7297                 if (on) {
7298                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7299                         return -EEXIST;
7300                 } else {
7301                         ret = i40e_aq_del_mirror_rule(hw, seid,
7302                                         mirr_rule->rule_type,
7303                                         mirr_rule->entries,
7304                                         mirr_rule->num_entries, mirr_rule->id);
7305                         if (ret < 0) {
7306                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7307                                                    " ret = %d, aq_err = %d.",
7308                                                    ret, hw->aq.asq_last_status);
7309                                 return -ENOSYS;
7310                         }
7311                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7312                         rte_free(mirr_rule);
7313                         pf->nb_mirror_rule--;
7314                         return 0;
7315                 }
7316         } else if (!on) {
7317                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7318                 return -ENOENT;
7319         }
7320
7321         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7322                                 sizeof(struct i40e_mirror_rule) , 0);
7323         if (!mirr_rule) {
7324                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7325                 return I40E_ERR_NO_MEMORY;
7326         }
7327         switch (mirror_conf->rule_type) {
7328         case ETH_MIRROR_VLAN:
7329                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7330                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7331                                 mirr_rule->entries[j] =
7332                                         mirror_conf->vlan.vlan_id[i];
7333                                 j++;
7334                         }
7335                 }
7336                 if (j == 0) {
7337                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7338                         rte_free(mirr_rule);
7339                         return -EINVAL;
7340                 }
7341                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7342                 break;
7343         case ETH_MIRROR_VIRTUAL_POOL_UP:
7344         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7345                 /* check if the specified pool bit is out of range */
7346                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7347                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7348                         rte_free(mirr_rule);
7349                         return -EINVAL;
7350                 }
7351                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7352                         if (mirror_conf->pool_mask & (1ULL << i)) {
7353                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7354                                 j++;
7355                         }
7356                 }
7357                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7358                         /* add pf vsi to entries */
7359                         mirr_rule->entries[j] = pf->main_vsi_seid;
7360                         j++;
7361                 }
7362                 if (j == 0) {
7363                         PMD_DRV_LOG(ERR, "pool is not specified.");
7364                         rte_free(mirr_rule);
7365                         return -EINVAL;
7366                 }
7367                 /* egress and ingress in aq commands means from switch but not port */
7368                 mirr_rule->rule_type =
7369                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7370                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7371                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7372                 break;
7373         case ETH_MIRROR_UPLINK_PORT:
7374                 /* egress and ingress in aq commands means from switch but not port*/
7375                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7376                 break;
7377         case ETH_MIRROR_DOWNLINK_PORT:
7378                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7379                 break;
7380         default:
7381                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7382                         mirror_conf->rule_type);
7383                 rte_free(mirr_rule);
7384                 return -EINVAL;
7385         }
7386
7387         /* If the dst_pool is equal to vf_num, consider it as PF */
7388         if (mirror_conf->dst_pool == pf->vf_num)
7389                 dst_seid = pf->main_vsi_seid;
7390         else
7391                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7392
7393         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7394                                       mirr_rule->rule_type, mirr_rule->entries,
7395                                       j, &rule_id);
7396         if (ret < 0) {
7397                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7398                                    " ret = %d, aq_err = %d.",
7399                                    ret, hw->aq.asq_last_status);
7400                 rte_free(mirr_rule);
7401                 return -ENOSYS;
7402         }
7403
7404         mirr_rule->index = sw_id;
7405         mirr_rule->num_entries = j;
7406         mirr_rule->id = rule_id;
7407         mirr_rule->dst_vsi_seid = dst_seid;
7408
7409         if (parent)
7410                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7411         else
7412                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7413
7414         pf->nb_mirror_rule++;
7415         return 0;
7416 }
7417
7418 /**
7419  * i40e_mirror_rule_reset
7420  * @dev: pointer to the device
7421  * @sw_id: mirror rule's sw_id
7422  *
7423  * reset a mirror rule.
7424  *
7425  **/
7426 static int
7427 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7428 {
7429         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7430         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7431         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7432         uint16_t seid;
7433         int ret;
7434
7435         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7436
7437         seid = pf->main_vsi->veb->seid;
7438
7439         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7440                 if (sw_id == it->index) {
7441                         mirr_rule = it;
7442                         break;
7443                 }
7444         }
7445         if (mirr_rule) {
7446                 ret = i40e_aq_del_mirror_rule(hw, seid,
7447                                 mirr_rule->rule_type,
7448                                 mirr_rule->entries,
7449                                 mirr_rule->num_entries, mirr_rule->id);
7450                 if (ret < 0) {
7451                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7452                                            " status = %d, aq_err = %d.",
7453                                            ret, hw->aq.asq_last_status);
7454                         return -ENOSYS;
7455                 }
7456                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7457                 rte_free(mirr_rule);
7458                 pf->nb_mirror_rule--;
7459         } else {
7460                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7461                 return -ENOENT;
7462         }
7463         return 0;
7464 }
7465
7466 static int
7467 i40e_timesync_enable(struct rte_eth_dev *dev)
7468 {
7469         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470         struct rte_eth_link *link = &dev->data->dev_link;
7471         uint32_t tsync_ctl_l;
7472         uint32_t tsync_ctl_h;
7473         uint32_t tsync_inc_l;
7474         uint32_t tsync_inc_h;
7475
7476         switch (link->link_speed) {
7477         case ETH_LINK_SPEED_40G:
7478                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7479                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7480                 break;
7481         case ETH_LINK_SPEED_10G:
7482                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7483                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7484                 break;
7485         case ETH_LINK_SPEED_1000:
7486                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7487                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7488                 break;
7489         default:
7490                 tsync_inc_l = 0x0;
7491                 tsync_inc_h = 0x0;
7492         }
7493
7494         /* Clear timesync registers. */
7495         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7496         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7497         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7498         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7499         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7500         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7501         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7502
7503         /* Set the timesync increment value. */
7504         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7505         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7506
7507         /* Enable timestamping of PTP packets. */
7508         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7509         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7510
7511         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7512         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7513         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7514
7515         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7516         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7517
7518         return 0;
7519 }
7520
7521 static int
7522 i40e_timesync_disable(struct rte_eth_dev *dev)
7523 {
7524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7525         uint32_t tsync_ctl_l;
7526         uint32_t tsync_ctl_h;
7527
7528         /* Disable timestamping of transmitted PTP packets. */
7529         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7530         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7531
7532         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7533         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7534
7535         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7536         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7537
7538         /* Set the timesync increment value. */
7539         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7540         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7541
7542         return 0;
7543 }
7544
7545 static int
7546 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7547                                 struct timespec *timestamp, uint32_t flags)
7548 {
7549         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7550         uint32_t sync_status;
7551         uint32_t rx_stmpl;
7552         uint32_t rx_stmph;
7553         uint32_t index = flags & 0x03;
7554
7555         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7556         if ((sync_status & (1 << index)) == 0)
7557                 return -EINVAL;
7558
7559         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7560         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7561
7562         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7563         timestamp->tv_nsec = 0;
7564
7565         return  0;
7566 }
7567
7568 static int
7569 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7570                                 struct timespec *timestamp)
7571 {
7572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7573         uint32_t sync_status;
7574         uint32_t tx_stmpl;
7575         uint32_t tx_stmph;
7576
7577         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7578         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7579                 return -EINVAL;
7580
7581         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7582         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7583
7584         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7585         timestamp->tv_nsec = 0;
7586
7587         return  0;
7588 }
7589
7590 /*
7591  * i40e_parse_dcb_configure - parse dcb configure from user
7592  * @dev: the device being configured
7593  * @dcb_cfg: pointer of the result of parse
7594  * @*tc_map: bit map of enabled traffic classes
7595  *
7596  * Returns 0 on success, negative value on failure
7597  */
7598 static int
7599 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7600                          struct i40e_dcbx_config *dcb_cfg,
7601                          uint8_t *tc_map)
7602 {
7603         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7604         uint8_t i, tc_bw, bw_lf;
7605
7606         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7607
7608         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7609         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7610                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7611                 return -EINVAL;
7612         }
7613
7614         /* assume each tc has the same bw */
7615         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7616         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7617                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7618         /* to ensure the sum of tcbw is equal to 100 */
7619         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7620         for (i = 0; i < bw_lf; i++)
7621                 dcb_cfg->etscfg.tcbwtable[i]++;
7622
7623         /* assume each tc has the same Transmission Selection Algorithm */
7624         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7625                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7626
7627         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7628                 dcb_cfg->etscfg.prioritytable[i] =
7629                                 dcb_rx_conf->dcb_tc[i];
7630
7631         /* FW needs one App to configure HW */
7632         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7633         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7634         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7635         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7636
7637         if (dcb_rx_conf->nb_tcs == 0)
7638                 *tc_map = 1; /* tc0 only */
7639         else
7640                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7641
7642         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7643                 dcb_cfg->pfc.willing = 0;
7644                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7645                 dcb_cfg->pfc.pfcenable = *tc_map;
7646         }
7647         return 0;
7648 }
7649
7650 /*
7651  * i40e_vsi_get_bw_info - Query VSI BW Information
7652  * @vsi: the VSI being queried
7653  *
7654  * Returns 0 on success, negative value on failure
7655  */
7656 static int
7657 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7658 {
7659         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7660         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7661         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7662         int i, ret;
7663         uint32_t tc_bw_max;
7664
7665         /* Get the VSI level BW configuration */
7666         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7667         if (ret) {
7668                 PMD_INIT_LOG(ERR,
7669                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
7670                          i40e_stat_str(hw, ret),
7671                          i40e_aq_str(hw, hw->aq.asq_last_status));
7672                 return -EINVAL;
7673         }
7674
7675         /* Get the VSI level BW configuration per TC */
7676         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7677                                                   NULL);
7678         if (ret) {
7679                 PMD_INIT_LOG(ERR,
7680                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7681                          i40e_stat_str(hw, ret),
7682                          i40e_aq_str(hw, hw->aq.asq_last_status));
7683                 return -EINVAL;
7684         }
7685
7686         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7687                 PMD_INIT_LOG(WARNING,
7688                          "Enabled TCs mismatch from querying VSI BW info"
7689                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7690                          bw_ets_config.tc_valid_bits);
7691                 /* Still continuing */
7692         }
7693
7694         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
7695         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
7696         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
7697                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
7698         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7699                 vsi->bw_info.bw_ets_share_credits[i] =
7700                                 bw_ets_config.share_credits[i];
7701                 vsi->bw_info.bw_ets_limit_credits[i] =
7702                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
7703                 /* 3 bits out of 4 for each TC */
7704                 vsi->bw_info.bw_ets_max_quanta[i] =
7705                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
7706                 PMD_INIT_LOG(DEBUG,
7707                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
7708                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
7709         }
7710
7711         return 0;
7712 }
7713
7714 static int
7715 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
7716                               struct i40e_aqc_vsi_properties_data *info,
7717                               uint8_t enabled_tcmap)
7718 {
7719         int ret, i, total_tc = 0;
7720         uint16_t qpnum_per_tc, bsf, qp_idx;
7721         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
7722
7723         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
7724         if (ret != I40E_SUCCESS)
7725                 return ret;
7726
7727         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7728                 if (enabled_tcmap & (1 << i))
7729                         total_tc++;
7730         }
7731         if (total_tc == 0)
7732                 total_tc = 1;
7733         vsi->enabled_tc = enabled_tcmap;
7734
7735         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
7736         /* Number of queues per enabled TC */
7737         if (qpnum_per_tc == 0) {
7738                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
7739                 return I40E_ERR_INVALID_QP_ID;
7740         }
7741         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
7742                                 I40E_MAX_Q_PER_TC);
7743         bsf = rte_bsf32(qpnum_per_tc);
7744
7745         /**
7746          * Configure TC and queue mapping parameters, for enabled TC,
7747          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
7748          * default queue will serve it.
7749          */
7750         qp_idx = 0;
7751         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7752                 if (vsi->enabled_tc & (1 << i)) {
7753                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
7754                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
7755                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
7756                         qp_idx += qpnum_per_tc;
7757                 } else
7758                         info->tc_mapping[i] = 0;
7759         }
7760
7761         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
7762         if (vsi->type == I40E_VSI_SRIOV) {
7763                 info->mapping_flags |=
7764                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
7765                 for (i = 0; i < vsi->nb_qps; i++)
7766                         info->queue_mapping[i] =
7767                                 rte_cpu_to_le_16(vsi->base_queue + i);
7768         } else {
7769                 info->mapping_flags |=
7770                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
7771                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
7772         }
7773         info->valid_sections |=
7774                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
7775
7776         return I40E_SUCCESS;
7777 }
7778
7779 /*
7780  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
7781  * @vsi: VSI to be configured
7782  * @tc_map: enabled TC bitmap
7783  *
7784  * Returns 0 on success, negative value on failure
7785  */
7786 static int
7787 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
7788 {
7789         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
7790         struct i40e_vsi_context ctxt;
7791         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7792         int ret = 0;
7793         int i;
7794
7795         /* Check if enabled_tc is same as existing or new TCs */
7796         if (vsi->enabled_tc == tc_map)
7797                 return ret;
7798
7799         /* configure tc bandwidth */
7800         memset(&bw_data, 0, sizeof(bw_data));
7801         bw_data.tc_valid_bits = tc_map;
7802         /* Enable ETS TCs with equal BW Share for now across all VSIs */
7803         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7804                 if (tc_map & BIT_ULL(i))
7805                         bw_data.tc_bw_credits[i] = 1;
7806         }
7807         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
7808         if (ret) {
7809                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
7810                         " per TC failed = %d",
7811                         hw->aq.asq_last_status);
7812                 goto out;
7813         }
7814         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
7815                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
7816
7817         /* Update Queue Pairs Mapping for currently enabled UPs */
7818         ctxt.seid = vsi->seid;
7819         ctxt.pf_num = hw->pf_id;
7820         ctxt.vf_num = 0;
7821         ctxt.uplink_seid = vsi->uplink_seid;
7822         ctxt.info = vsi->info;
7823         i40e_get_cap(hw);
7824         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
7825         if (ret)
7826                 goto out;
7827
7828         /* Update the VSI after updating the VSI queue-mapping information */
7829         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7830         if (ret) {
7831                 PMD_INIT_LOG(ERR, "Failed to configure "
7832                             "TC queue mapping = %d",
7833                             hw->aq.asq_last_status);
7834                 goto out;
7835         }
7836         /* update the local VSI info with updated queue map */
7837         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
7838                                         sizeof(vsi->info.tc_mapping));
7839         (void)rte_memcpy(&vsi->info.queue_mapping,
7840                         &ctxt.info.queue_mapping,
7841                 sizeof(vsi->info.queue_mapping));
7842         vsi->info.mapping_flags = ctxt.info.mapping_flags;
7843         vsi->info.valid_sections = 0;
7844
7845         /* Update current VSI BW information */
7846         ret = i40e_vsi_get_bw_info(vsi);
7847         if (ret) {
7848                 PMD_INIT_LOG(ERR,
7849                          "Failed updating vsi bw info, err %s aq_err %s",
7850                          i40e_stat_str(hw, ret),
7851                          i40e_aq_str(hw, hw->aq.asq_last_status));
7852                 goto out;
7853         }
7854
7855         vsi->enabled_tc = tc_map;
7856
7857 out:
7858         return ret;
7859 }
7860
7861 /*
7862  * i40e_dcb_hw_configure - program the dcb setting to hw
7863  * @pf: pf the configuration is taken on
7864  * @new_cfg: new configuration
7865  * @tc_map: enabled TC bitmap
7866  *
7867  * Returns 0 on success, negative value on failure
7868  */
7869 static enum i40e_status_code
7870 i40e_dcb_hw_configure(struct i40e_pf *pf,
7871                       struct i40e_dcbx_config *new_cfg,
7872                       uint8_t tc_map)
7873 {
7874         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7875         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
7876         struct i40e_vsi *main_vsi = pf->main_vsi;
7877         struct i40e_vsi_list *vsi_list;
7878         int i, ret;
7879         uint32_t val;
7880
7881         /* Use the FW API if FW > v4.4*/
7882         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
7883                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
7884                                   " to configure DCB");
7885                 return I40E_ERR_FIRMWARE_API_VERSION;
7886         }
7887
7888         /* Check if need reconfiguration */
7889         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
7890                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
7891                 return I40E_SUCCESS;
7892         }
7893
7894         /* Copy the new config to the current config */
7895         *old_cfg = *new_cfg;
7896         old_cfg->etsrec = old_cfg->etscfg;
7897         ret = i40e_set_dcb_config(hw);
7898         if (ret) {
7899                 PMD_INIT_LOG(ERR,
7900                          "Set DCB Config failed, err %s aq_err %s\n",
7901                          i40e_stat_str(hw, ret),
7902                          i40e_aq_str(hw, hw->aq.asq_last_status));
7903                 return ret;
7904         }
7905         /* set receive Arbiter to RR mode and ETS scheme by default */
7906         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
7907                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
7908                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
7909                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
7910                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
7911                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
7912                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
7913                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
7914                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
7915                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
7916                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
7917                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
7918                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
7919         }
7920         /* get local mib to check whether it is configured correctly */
7921         /* IEEE mode */
7922         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
7923         /* Get Local DCB Config */
7924         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
7925                                      &hw->local_dcbx_config);
7926
7927         /* Update each VSI */
7928         i40e_vsi_config_tc(main_vsi, tc_map);
7929         if (main_vsi->veb) {
7930                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
7931                         /* Beside main VSI, only enable default
7932                          * TC for other VSIs
7933                          */
7934                         ret = i40e_vsi_config_tc(vsi_list->vsi,
7935                                                 I40E_DEFAULT_TCMAP);
7936                         if (ret)
7937                                 PMD_INIT_LOG(WARNING,
7938                                          "Failed configuring TC for VSI seid=%d\n",
7939                                          vsi_list->vsi->seid);
7940                         /* continue */
7941                 }
7942         }
7943         return I40E_SUCCESS;
7944 }
7945
7946 /*
7947  * i40e_dcb_init_configure - initial dcb config
7948  * @dev: device being configured
7949  * @sw_dcb: indicate whether dcb is sw configured or hw offload
7950  *
7951  * Returns 0 on success, negative value on failure
7952  */
7953 static int
7954 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
7955 {
7956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7958         int ret = 0;
7959
7960         if ((pf->flags & I40E_FLAG_DCB) == 0) {
7961                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7962                 return -ENOTSUP;
7963         }
7964
7965         /* DCB initialization:
7966          * Update DCB configuration from the Firmware and configure
7967          * LLDP MIB change event.
7968          */
7969         if (sw_dcb == TRUE) {
7970                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
7971                 if (ret != I40E_SUCCESS)
7972                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
7973
7974                 ret = i40e_init_dcb(hw);
7975                 /* if sw_dcb, lldp agent is stopped, the return from
7976                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
7977                  * adminq status.
7978                  */
7979                 if (ret != I40E_SUCCESS &&
7980                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
7981                         memset(&hw->local_dcbx_config, 0,
7982                                 sizeof(struct i40e_dcbx_config));
7983                         /* set dcb default configuration */
7984                         hw->local_dcbx_config.etscfg.willing = 0;
7985                         hw->local_dcbx_config.etscfg.maxtcs = 0;
7986                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
7987                         hw->local_dcbx_config.etscfg.tsatable[0] =
7988                                                 I40E_IEEE_TSA_ETS;
7989                         hw->local_dcbx_config.etsrec =
7990                                 hw->local_dcbx_config.etscfg;
7991                         hw->local_dcbx_config.pfc.willing = 0;
7992                         hw->local_dcbx_config.pfc.pfccap =
7993                                                 I40E_MAX_TRAFFIC_CLASS;
7994                         /* FW needs one App to configure HW */
7995                         hw->local_dcbx_config.numapps = 1;
7996                         hw->local_dcbx_config.app[0].selector =
7997                                                 I40E_APP_SEL_ETHTYPE;
7998                         hw->local_dcbx_config.app[0].priority = 3;
7999                         hw->local_dcbx_config.app[0].protocolid =
8000                                                 I40E_APP_PROTOID_FCOE;
8001                         ret = i40e_set_dcb_config(hw);
8002                         if (ret) {
8003                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8004                                         " err = %d, aq_err = %d.", ret,
8005                                           hw->aq.asq_last_status);
8006                                 return -ENOSYS;
8007                         }
8008                 } else {
8009                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8010                                           " aq_err = %d.", ret,
8011                                           hw->aq.asq_last_status);
8012                         return -ENOTSUP;
8013                 }
8014         } else {
8015                 ret = i40e_aq_start_lldp(hw, NULL);
8016                 if (ret != I40E_SUCCESS)
8017                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8018
8019                 ret = i40e_init_dcb(hw);
8020                 if (!ret) {
8021                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8022                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8023                                                   " DCBX offload.");
8024                                 return -ENOTSUP;
8025                         }
8026                 } else {
8027                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8028                                           " aq_err = %d.", ret,
8029                                           hw->aq.asq_last_status);
8030                         return -ENOTSUP;
8031                 }
8032         }
8033         return 0;
8034 }
8035
8036 /*
8037  * i40e_dcb_setup - setup dcb related config
8038  * @dev: device being configured
8039  *
8040  * Returns 0 on success, negative value on failure
8041  */
8042 static int
8043 i40e_dcb_setup(struct rte_eth_dev *dev)
8044 {
8045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8046         struct i40e_dcbx_config dcb_cfg;
8047         uint8_t tc_map = 0;
8048         int ret = 0;
8049
8050         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8051                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8052                 return -ENOTSUP;
8053         }
8054
8055         if (pf->vf_num != 0 ||
8056             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8057                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8058
8059         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8060         if (ret) {
8061                 PMD_INIT_LOG(ERR, "invalid dcb config");
8062                 return -EINVAL;
8063         }
8064         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8065         if (ret) {
8066                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8067                 return -ENOSYS;
8068         }
8069         return 0;
8070 }
8071
8072 static int
8073 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8074                       struct rte_eth_dcb_info *dcb_info)
8075 {
8076         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8077         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8078         struct i40e_vsi *vsi = pf->main_vsi;
8079         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8080         uint16_t bsf, tc_mapping;
8081         int i;
8082
8083         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8084                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8085         else
8086                 dcb_info->nb_tcs = 1;
8087         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8088                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8089         for (i = 0; i < dcb_info->nb_tcs; i++)
8090                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8091
8092         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8093                 if (vsi->enabled_tc & (1 << i)) {
8094                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8095                         /* only main vsi support multi TCs */
8096                         dcb_info->tc_queue.tc_rxq[0][i].base =
8097                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8098                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8099                         dcb_info->tc_queue.tc_txq[0][i].base =
8100                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8101                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8102                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8103                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8104                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8105                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8106                 }
8107         }
8108         return 0;
8109 }