4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
80 /* Flow control default timer */
81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
83 /* Flow control default high water */
84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
86 /* Flow control default low water */
87 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Receive Average Packet Size in Byte*/
99 #define I40E_PACKET_AVERAGE_SIZE 128
101 /* Mask of PF interrupt causes */
102 #define I40E_PFINT_ICR0_ENA_MASK ( \
103 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
104 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
105 I40E_PFINT_ICR0_ENA_GRST_MASK | \
106 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
107 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
109 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
111 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
112 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
114 #define I40E_FLOW_TYPES ( \
115 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
116 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
125 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
127 /* Additional timesync values. */
128 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
129 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
130 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
131 #define I40E_PRTTSYN_TSYNENA 0x80000000
132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
133 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
135 #define I40E_MAX_PERCENT 100
136 #define I40E_DEFAULT_DCB_APP_NUM 1
137 #define I40E_DEFAULT_DCB_APP_PRIO 3
139 #define I40E_INSET_NONE 0x00000000000000000ULL
142 #define I40E_INSET_DMAC 0x0000000000000001ULL
143 #define I40E_INSET_SMAC 0x0000000000000002ULL
144 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
145 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
146 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
149 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
150 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
151 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
152 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
153 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
154 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
155 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
157 /* bit 16 ~ bit 31 */
158 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
159 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
160 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
161 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
162 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
163 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
164 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
165 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
167 /* bit 32 ~ bit 47, tunnel fields */
168 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
169 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
170 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
171 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
172 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
173 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
175 /* bit 48 ~ bit 55 */
176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
178 /* bit 56 ~ bit 63, Flex Payload */
179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD \
188 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
189 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
190 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
191 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
194 * Below are values for writing un-exposed registers suggested
197 /* Destination MAC address */
198 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
199 /* Source MAC address */
200 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
202 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
205 /* Single VLAN tag in the inner L2 header */
206 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
207 /* Source IPv4 address */
208 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
209 /* Destination IPv4 address */
210 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
211 /* IPv4 Type of Service (TOS) */
212 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
214 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
215 /* IPv4 Time to Live */
216 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
217 /* Source IPv6 address */
218 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
219 /* Destination IPv6 address */
220 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
221 /* IPv6 Traffic Class (TC) */
222 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
223 /* IPv6 Next Header */
224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
228 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
229 /* Destination L4 port */
230 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
231 /* SCTP verification tag */
232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
235 /* Source port of tunneling UDP */
236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
237 /* Destination port of tunneling UDP */
238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
239 /* UDP Tunneling ID, NVGRE/GRE key */
240 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
241 /* Last ether type */
242 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
243 /* Tunneling outer destination IPv4 address */
244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
245 /* Tunneling outer destination IPv6 address */
246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
247 /* 1st word of flex payload */
248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
249 /* 2nd word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
251 /* 3rd word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
253 /* 4th word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
255 /* 5th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
257 /* 6th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
259 /* 7th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
261 /* 8th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
263 /* all 8 words flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
265 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
267 #define I40E_TRANSLATE_INSET 0
268 #define I40E_TRANSLATE_REG 1
270 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
271 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
272 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
273 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
275 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
277 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
280 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
282 /* PCI offset for querying capability */
283 #define PCI_DEV_CAP_REG 0xA4
284 /* PCI offset for enabling/disabling Extended Tag */
285 #define PCI_DEV_CTRL_REG 0xA8
286 /* Bit mask of Extended Tag capability */
287 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
288 /* Bit shift of Extended Tag enable/disable */
289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
290 /* Bit mask of Extended Tag enable/disable */
291 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
295 static int i40e_dev_configure(struct rte_eth_dev *dev);
296 static int i40e_dev_start(struct rte_eth_dev *dev);
297 static void i40e_dev_stop(struct rte_eth_dev *dev);
298 static void i40e_dev_close(struct rte_eth_dev *dev);
299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
306 struct rte_eth_stats *stats);
307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
308 struct rte_eth_xstats *xstats, unsigned n);
309 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
310 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
314 static void i40e_dev_info_get(struct rte_eth_dev *dev,
315 struct rte_eth_dev_info *dev_info);
316 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
319 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
320 enum rte_vlan_type vlan_type,
322 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
323 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
326 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
327 static int i40e_dev_led_on(struct rte_eth_dev *dev);
328 static int i40e_dev_led_off(struct rte_eth_dev *dev);
329 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
330 struct rte_eth_fc_conf *fc_conf);
331 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
332 struct rte_eth_fc_conf *fc_conf);
333 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
334 struct rte_eth_pfc_conf *pfc_conf);
335 static void i40e_macaddr_add(struct rte_eth_dev *dev,
336 struct ether_addr *mac_addr,
339 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
340 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
341 struct rte_eth_rss_reta_entry64 *reta_conf,
343 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
344 struct rte_eth_rss_reta_entry64 *reta_conf,
347 static int i40e_get_cap(struct i40e_hw *hw);
348 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
349 static int i40e_pf_setup(struct i40e_pf *pf);
350 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
351 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
352 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
353 static int i40e_dcb_setup(struct rte_eth_dev *dev);
354 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
355 bool offset_loaded, uint64_t *offset, uint64_t *stat);
356 static void i40e_stat_update_48(struct i40e_hw *hw,
362 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
363 static void i40e_dev_interrupt_handler(
364 __rte_unused struct rte_intr_handle *handle, void *param);
365 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
366 uint32_t base, uint32_t num);
367 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
368 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
370 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
372 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
373 static int i40e_veb_release(struct i40e_veb *veb);
374 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
375 struct i40e_vsi *vsi);
376 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
377 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
378 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
379 struct i40e_macvlan_filter *mv_f,
381 struct ether_addr *addr);
382 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
383 struct i40e_macvlan_filter *mv_f,
386 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
387 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
388 struct rte_eth_rss_conf *rss_conf);
389 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
390 struct rte_eth_rss_conf *rss_conf);
391 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
392 struct rte_eth_udp_tunnel *udp_tunnel);
393 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
394 struct rte_eth_udp_tunnel *udp_tunnel);
395 static void i40e_filter_input_set_init(struct i40e_pf *pf);
396 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
397 struct rte_eth_ethertype_filter *filter,
399 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
400 enum rte_filter_op filter_op,
402 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
403 enum rte_filter_type filter_type,
404 enum rte_filter_op filter_op,
406 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
407 struct rte_eth_dcb_info *dcb_info);
408 static void i40e_configure_registers(struct i40e_hw *hw);
409 static void i40e_hw_init(struct rte_eth_dev *dev);
410 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
411 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
412 struct rte_eth_mirror_conf *mirror_conf,
413 uint8_t sw_id, uint8_t on);
414 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
416 static int i40e_timesync_enable(struct rte_eth_dev *dev);
417 static int i40e_timesync_disable(struct rte_eth_dev *dev);
418 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
419 struct timespec *timestamp,
421 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
422 struct timespec *timestamp);
423 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
425 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
427 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
428 struct timespec *timestamp);
429 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
430 const struct timespec *timestamp);
432 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
434 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
437 static int i40e_get_reg_length(struct rte_eth_dev *dev);
439 static int i40e_get_regs(struct rte_eth_dev *dev,
440 struct rte_dev_reg_info *regs);
442 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
444 static int i40e_get_eeprom(struct rte_eth_dev *dev,
445 struct rte_dev_eeprom_info *eeprom);
447 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
448 struct ether_addr *mac_addr);
450 static const struct rte_pci_id pci_id_i40e_map[] = {
451 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
452 #include "rte_pci_dev_ids.h"
453 { .vendor_id = 0, /* sentinel */ },
456 static const struct eth_dev_ops i40e_eth_dev_ops = {
457 .dev_configure = i40e_dev_configure,
458 .dev_start = i40e_dev_start,
459 .dev_stop = i40e_dev_stop,
460 .dev_close = i40e_dev_close,
461 .promiscuous_enable = i40e_dev_promiscuous_enable,
462 .promiscuous_disable = i40e_dev_promiscuous_disable,
463 .allmulticast_enable = i40e_dev_allmulticast_enable,
464 .allmulticast_disable = i40e_dev_allmulticast_disable,
465 .dev_set_link_up = i40e_dev_set_link_up,
466 .dev_set_link_down = i40e_dev_set_link_down,
467 .link_update = i40e_dev_link_update,
468 .stats_get = i40e_dev_stats_get,
469 .xstats_get = i40e_dev_xstats_get,
470 .stats_reset = i40e_dev_stats_reset,
471 .xstats_reset = i40e_dev_stats_reset,
472 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
473 .dev_infos_get = i40e_dev_info_get,
474 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
475 .vlan_filter_set = i40e_vlan_filter_set,
476 .vlan_tpid_set = i40e_vlan_tpid_set,
477 .vlan_offload_set = i40e_vlan_offload_set,
478 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
479 .vlan_pvid_set = i40e_vlan_pvid_set,
480 .rx_queue_start = i40e_dev_rx_queue_start,
481 .rx_queue_stop = i40e_dev_rx_queue_stop,
482 .tx_queue_start = i40e_dev_tx_queue_start,
483 .tx_queue_stop = i40e_dev_tx_queue_stop,
484 .rx_queue_setup = i40e_dev_rx_queue_setup,
485 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
486 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
487 .rx_queue_release = i40e_dev_rx_queue_release,
488 .rx_queue_count = i40e_dev_rx_queue_count,
489 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .filter_ctrl = i40e_dev_filter_ctrl,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .mirror_rule_set = i40e_mirror_rule_set,
509 .mirror_rule_reset = i40e_mirror_rule_reset,
510 .timesync_enable = i40e_timesync_enable,
511 .timesync_disable = i40e_timesync_disable,
512 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
513 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
514 .get_dcb_info = i40e_dev_get_dcb_info,
515 .timesync_adjust_time = i40e_timesync_adjust_time,
516 .timesync_read_time = i40e_timesync_read_time,
517 .timesync_write_time = i40e_timesync_write_time,
518 .get_reg_length = i40e_get_reg_length,
519 .get_reg = i40e_get_regs,
520 .get_eeprom_length = i40e_get_eeprom_length,
521 .get_eeprom = i40e_get_eeprom,
522 .mac_addr_set = i40e_set_default_mac_addr,
525 /* store statistics names and its offset in stats structure */
526 struct rte_i40e_xstats_name_off {
527 char name[RTE_ETH_XSTATS_NAME_SIZE];
531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
532 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
533 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
534 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
535 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
536 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
537 rx_unknown_protocol)},
538 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
539 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
540 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
541 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
545 sizeof(rte_i40e_stats_strings[0]))
547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
548 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
549 tx_dropped_link_down)},
550 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
551 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
554 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
556 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
560 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
561 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
562 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
563 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
564 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
565 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
581 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
582 mac_short_packet_dropped)},
583 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
586 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
587 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
599 {"rx_flow_director_atr_match_packets",
600 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
601 {"rx_flow_director_sb_match_packets",
602 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
603 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
605 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
607 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
614 sizeof(rte_i40e_hw_port_strings[0]))
616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
617 {"xon_packets", offsetof(struct i40e_hw_port_stats,
619 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
624 sizeof(rte_i40e_rxq_prio_strings[0]))
626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
627 {"xon_packets", offsetof(struct i40e_hw_port_stats,
629 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
631 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
632 priority_xon_2_xoff)},
635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
636 sizeof(rte_i40e_txq_prio_strings[0]))
638 static struct eth_driver rte_i40e_pmd = {
640 .name = "rte_i40e_pmd",
641 .id_table = pci_id_i40e_map,
642 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
643 RTE_PCI_DRV_DETACHABLE,
645 .eth_dev_init = eth_i40e_dev_init,
646 .eth_dev_uninit = eth_i40e_dev_uninit,
647 .dev_private_size = sizeof(struct i40e_adapter),
651 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
652 struct rte_eth_link *link)
654 struct rte_eth_link *dst = link;
655 struct rte_eth_link *src = &(dev->data->dev_link);
657 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
658 *(uint64_t *)src) == 0)
665 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
666 struct rte_eth_link *link)
668 struct rte_eth_link *dst = &(dev->data->dev_link);
669 struct rte_eth_link *src = link;
671 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
672 *(uint64_t *)src) == 0)
679 * Driver initialization routine.
680 * Invoked once at EAL init time.
681 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
684 rte_i40e_pmd_init(const char *name __rte_unused,
685 const char *params __rte_unused)
687 PMD_INIT_FUNC_TRACE();
688 rte_eth_driver_register(&rte_i40e_pmd);
693 static struct rte_driver rte_i40e_driver = {
695 .init = rte_i40e_pmd_init,
698 PMD_REGISTER_DRIVER(rte_i40e_driver);
701 * Initialize registers for flexible payload, which should be set by NVM.
702 * This should be removed from code once it is fixed in NVM.
704 #ifndef I40E_GLQF_ORT
705 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
707 #ifndef I40E_GLQF_PIT
708 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
711 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
713 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
715 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
716 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
718 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
721 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
724 /* GLQF_PIT Registers */
725 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
726 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
729 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
732 * Add a ethertype filter to drop all flow control frames transmitted
736 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
739 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
740 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
741 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
744 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
745 I40E_FLOW_CONTROL_ETHERTYPE, flags,
746 pf->main_vsi_seid, 0,
749 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
750 " frames from VSIs.");
754 eth_i40e_dev_init(struct rte_eth_dev *dev)
756 struct rte_pci_device *pci_dev;
757 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
758 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
759 struct i40e_vsi *vsi;
764 PMD_INIT_FUNC_TRACE();
766 dev->dev_ops = &i40e_eth_dev_ops;
767 dev->rx_pkt_burst = i40e_recv_pkts;
768 dev->tx_pkt_burst = i40e_xmit_pkts;
770 /* for secondary processes, we don't initialise any further as primary
771 * has already done this work. Only check we don't need a different
773 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
774 i40e_set_rx_function(dev);
775 i40e_set_tx_function(dev);
778 pci_dev = dev->pci_dev;
780 rte_eth_copy_pci_info(dev, pci_dev);
782 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
783 pf->adapter->eth_dev = dev;
784 pf->dev_data = dev->data;
786 hw->back = I40E_PF_TO_ADAPTER(pf);
787 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
789 PMD_INIT_LOG(ERR, "Hardware is not available, "
790 "as address is NULL");
794 hw->vendor_id = pci_dev->id.vendor_id;
795 hw->device_id = pci_dev->id.device_id;
796 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
797 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
798 hw->bus.device = pci_dev->addr.devid;
799 hw->bus.func = pci_dev->addr.function;
800 hw->adapter_stopped = 0;
802 /* Make sure all is clean before doing PF reset */
805 /* Initialize the hardware */
808 /* Reset here to make sure all is clean for each PF */
809 ret = i40e_pf_reset(hw);
811 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
815 /* Initialize the shared code (base driver) */
816 ret = i40e_init_shared_code(hw);
818 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
823 * To work around the NVM issue,initialize registers
824 * for flexible payload by software.
825 * It should be removed once issues are fixed in NVM.
827 i40e_flex_payload_reg_init(hw);
829 /* Initialize the input set for filters (hash and fd) to default value */
830 i40e_filter_input_set_init(pf);
832 /* Initialize the parameters for adminq */
833 i40e_init_adminq_parameter(hw);
834 ret = i40e_init_adminq(hw);
835 if (ret != I40E_SUCCESS) {
836 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
839 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
840 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
841 hw->aq.api_maj_ver, hw->aq.api_min_ver,
842 ((hw->nvm.version >> 12) & 0xf),
843 ((hw->nvm.version >> 4) & 0xff),
844 (hw->nvm.version & 0xf), hw->nvm.eetrack);
847 i40e_clear_pxe_mode(hw);
850 * On X710, performance number is far from the expectation on recent
851 * firmware versions. The fix for this issue may not be integrated in
852 * the following firmware version. So the workaround in software driver
853 * is needed. It needs to modify the initial values of 3 internal only
854 * registers. Note that the workaround can be removed when it is fixed
855 * in firmware in the future.
857 i40e_configure_registers(hw);
859 /* Get hw capabilities */
860 ret = i40e_get_cap(hw);
861 if (ret != I40E_SUCCESS) {
862 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
863 goto err_get_capabilities;
866 /* Initialize parameters for PF */
867 ret = i40e_pf_parameter_init(dev);
869 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
870 goto err_parameter_init;
873 /* Initialize the queue management */
874 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
876 PMD_INIT_LOG(ERR, "Failed to init queue pool");
877 goto err_qp_pool_init;
879 ret = i40e_res_pool_init(&pf->msix_pool, 1,
880 hw->func_caps.num_msix_vectors - 1);
882 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
883 goto err_msix_pool_init;
886 /* Initialize lan hmc */
887 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
888 hw->func_caps.num_rx_qp, 0, 0);
889 if (ret != I40E_SUCCESS) {
890 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
891 goto err_init_lan_hmc;
894 /* Configure lan hmc */
895 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
896 if (ret != I40E_SUCCESS) {
897 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
898 goto err_configure_lan_hmc;
901 /* Get and check the mac address */
902 i40e_get_mac_addr(hw, hw->mac.addr);
903 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
904 PMD_INIT_LOG(ERR, "mac address is not valid");
906 goto err_get_mac_addr;
908 /* Copy the permanent MAC address */
909 ether_addr_copy((struct ether_addr *) hw->mac.addr,
910 (struct ether_addr *) hw->mac.perm_addr);
912 /* Disable flow control */
913 hw->fc.requested_mode = I40E_FC_NONE;
914 i40e_set_fc(hw, &aq_fail, TRUE);
916 /* Set the global registers with default ether type value */
917 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
918 if (ret != I40E_SUCCESS) {
919 PMD_INIT_LOG(ERR, "Failed to set the default outer "
921 goto err_setup_pf_switch;
923 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
924 if (ret != I40E_SUCCESS) {
925 PMD_INIT_LOG(ERR, "Failed to set the default outer "
927 goto err_setup_pf_switch;
930 /* PF setup, which includes VSI setup */
931 ret = i40e_pf_setup(pf);
933 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
934 goto err_setup_pf_switch;
939 /* Disable double vlan by default */
940 i40e_vsi_config_double_vlan(vsi, FALSE);
942 if (!vsi->max_macaddrs)
943 len = ETHER_ADDR_LEN;
945 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
947 /* Should be after VSI initialized */
948 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
949 if (!dev->data->mac_addrs) {
950 PMD_INIT_LOG(ERR, "Failed to allocated memory "
951 "for storing mac address");
954 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
955 &dev->data->mac_addrs[0]);
957 /* initialize pf host driver to setup SRIOV resource if applicable */
958 i40e_pf_host_init(dev);
960 /* register callback func to eal lib */
961 rte_intr_callback_register(&(pci_dev->intr_handle),
962 i40e_dev_interrupt_handler, (void *)dev);
964 /* configure and enable device interrupt */
965 i40e_pf_config_irq0(hw, TRUE);
966 i40e_pf_enable_irq0(hw);
968 /* enable uio intr after callback register */
969 rte_intr_enable(&(pci_dev->intr_handle));
971 * Add an ethertype filter to drop all flow control frames transmitted
972 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
975 i40e_add_tx_flow_control_drop_filter(pf);
977 /* Set the max frame size to 0x2600 by default,
978 * in case other drivers changed the default value.
980 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
982 /* initialize mirror rule list */
983 TAILQ_INIT(&pf->mirror_list);
985 /* Init dcb to sw mode by default */
986 ret = i40e_dcb_init_configure(dev, TRUE);
987 if (ret != I40E_SUCCESS) {
988 PMD_INIT_LOG(INFO, "Failed to init dcb.");
989 pf->flags &= ~I40E_FLAG_DCB;
995 i40e_vsi_release(pf->main_vsi);
998 err_configure_lan_hmc:
999 (void)i40e_shutdown_lan_hmc(hw);
1001 i40e_res_pool_destroy(&pf->msix_pool);
1003 i40e_res_pool_destroy(&pf->qp_pool);
1006 err_get_capabilities:
1007 (void)i40e_shutdown_adminq(hw);
1013 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1015 struct rte_pci_device *pci_dev;
1017 struct i40e_filter_control_settings settings;
1019 uint8_t aq_fail = 0;
1021 PMD_INIT_FUNC_TRACE();
1023 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1026 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027 pci_dev = dev->pci_dev;
1029 if (hw->adapter_stopped == 0)
1030 i40e_dev_close(dev);
1032 dev->dev_ops = NULL;
1033 dev->rx_pkt_burst = NULL;
1034 dev->tx_pkt_burst = NULL;
1037 ret = i40e_aq_stop_lldp(hw, true, NULL);
1038 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1039 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1041 /* Clear PXE mode */
1042 i40e_clear_pxe_mode(hw);
1044 /* Unconfigure filter control */
1045 memset(&settings, 0, sizeof(settings));
1046 ret = i40e_set_filter_control(hw, &settings);
1048 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1051 /* Disable flow control */
1052 hw->fc.requested_mode = I40E_FC_NONE;
1053 i40e_set_fc(hw, &aq_fail, TRUE);
1055 /* uninitialize pf host driver */
1056 i40e_pf_host_uninit(dev);
1058 rte_free(dev->data->mac_addrs);
1059 dev->data->mac_addrs = NULL;
1061 /* disable uio intr before callback unregister */
1062 rte_intr_disable(&(pci_dev->intr_handle));
1064 /* register callback func to eal lib */
1065 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1066 i40e_dev_interrupt_handler, (void *)dev);
1072 i40e_dev_configure(struct rte_eth_dev *dev)
1074 struct i40e_adapter *ad =
1075 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1076 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1077 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1080 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1081 * bulk allocation or vector Rx preconditions we will reset it.
1083 ad->rx_bulk_alloc_allowed = true;
1084 ad->rx_vec_allowed = true;
1085 ad->tx_simple_allowed = true;
1086 ad->tx_vec_allowed = true;
1088 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1089 ret = i40e_fdir_setup(pf);
1090 if (ret != I40E_SUCCESS) {
1091 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1094 ret = i40e_fdir_configure(dev);
1096 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1100 i40e_fdir_teardown(pf);
1102 ret = i40e_dev_init_vlan(dev);
1107 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1108 * RSS setting have different requirements.
1109 * General PMD driver call sequence are NIC init, configure,
1110 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1111 * will try to lookup the VSI that specific queue belongs to if VMDQ
1112 * applicable. So, VMDQ setting has to be done before
1113 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1114 * For RSS setting, it will try to calculate actual configured RX queue
1115 * number, which will be available after rx_queue_setup(). dev_start()
1116 * function is good to place RSS setup.
1118 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1119 ret = i40e_vmdq_setup(dev);
1124 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1125 ret = i40e_dcb_setup(dev);
1127 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1135 /* need to release vmdq resource if exists */
1136 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1137 i40e_vsi_release(pf->vmdq[i].vsi);
1138 pf->vmdq[i].vsi = NULL;
1143 /* need to release fdir resource if exists */
1144 i40e_fdir_teardown(pf);
1149 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1151 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1152 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1153 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1154 uint16_t msix_vect = vsi->msix_intr;
1157 for (i = 0; i < vsi->nb_qps; i++) {
1158 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1159 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1163 if (vsi->type != I40E_VSI_SRIOV) {
1164 if (!rte_intr_allow_others(intr_handle)) {
1165 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1166 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1168 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1171 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1172 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1174 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1179 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1180 vsi->user_param + (msix_vect - 1);
1182 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1183 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1185 I40E_WRITE_FLUSH(hw);
1189 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1190 int base_queue, int nb_queue)
1194 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1196 /* Bind all RX queues to allocated MSIX interrupt */
1197 for (i = 0; i < nb_queue; i++) {
1198 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1199 I40E_QINT_RQCTL_ITR_INDX_MASK |
1200 ((base_queue + i + 1) <<
1201 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1202 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1203 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1205 if (i == nb_queue - 1)
1206 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1207 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1210 /* Write first RX queue to Link list register as the head element */
1211 if (vsi->type != I40E_VSI_SRIOV) {
1213 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1215 if (msix_vect == I40E_MISC_VEC_ID) {
1216 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1218 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1220 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1222 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1225 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1227 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1229 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1231 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1238 if (msix_vect == I40E_MISC_VEC_ID) {
1240 I40E_VPINT_LNKLST0(vsi->user_param),
1242 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1244 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1246 /* num_msix_vectors_vf needs to minus irq0 */
1247 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1248 vsi->user_param + (msix_vect - 1);
1250 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1252 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1254 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1258 I40E_WRITE_FLUSH(hw);
1262 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1264 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1265 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1266 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1267 uint16_t msix_vect = vsi->msix_intr;
1268 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1269 uint16_t queue_idx = 0;
1274 for (i = 0; i < vsi->nb_qps; i++) {
1275 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1276 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1279 /* INTENA flag is not auto-cleared for interrupt */
1280 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1281 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1282 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1283 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1284 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1286 /* VF bind interrupt */
1287 if (vsi->type == I40E_VSI_SRIOV) {
1288 __vsi_queues_bind_intr(vsi, msix_vect,
1289 vsi->base_queue, vsi->nb_qps);
1293 /* PF & VMDq bind interrupt */
1294 if (rte_intr_dp_is_en(intr_handle)) {
1295 if (vsi->type == I40E_VSI_MAIN) {
1298 } else if (vsi->type == I40E_VSI_VMDQ2) {
1299 struct i40e_vsi *main_vsi =
1300 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1301 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1306 for (i = 0; i < vsi->nb_used_qps; i++) {
1308 if (!rte_intr_allow_others(intr_handle))
1309 /* allow to share MISC_VEC_ID */
1310 msix_vect = I40E_MISC_VEC_ID;
1312 /* no enough msix_vect, map all to one */
1313 __vsi_queues_bind_intr(vsi, msix_vect,
1314 vsi->base_queue + i,
1315 vsi->nb_used_qps - i);
1316 for (; !!record && i < vsi->nb_used_qps; i++)
1317 intr_handle->intr_vec[queue_idx + i] =
1321 /* 1:1 queue/msix_vect mapping */
1322 __vsi_queues_bind_intr(vsi, msix_vect,
1323 vsi->base_queue + i, 1);
1325 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1333 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1335 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1336 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1337 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1338 uint16_t interval = i40e_calc_itr_interval(\
1339 RTE_LIBRTE_I40E_ITR_INTERVAL);
1340 uint16_t msix_intr, i;
1342 if (rte_intr_allow_others(intr_handle))
1343 for (i = 0; i < vsi->nb_msix; i++) {
1344 msix_intr = vsi->msix_intr + i;
1345 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1346 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1347 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1348 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1350 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1353 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1354 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1355 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1356 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1358 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1360 I40E_WRITE_FLUSH(hw);
1364 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1366 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1367 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1368 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1369 uint16_t msix_intr, i;
1371 if (rte_intr_allow_others(intr_handle))
1372 for (i = 0; i < vsi->nb_msix; i++) {
1373 msix_intr = vsi->msix_intr + i;
1374 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1378 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1380 I40E_WRITE_FLUSH(hw);
1383 static inline uint8_t
1384 i40e_parse_link_speeds(uint16_t link_speeds)
1386 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1388 if (link_speeds & ETH_LINK_SPEED_40G)
1389 link_speed |= I40E_LINK_SPEED_40GB;
1390 if (link_speeds & ETH_LINK_SPEED_20G)
1391 link_speed |= I40E_LINK_SPEED_20GB;
1392 if (link_speeds & ETH_LINK_SPEED_10G)
1393 link_speed |= I40E_LINK_SPEED_10GB;
1394 if (link_speeds & ETH_LINK_SPEED_1G)
1395 link_speed |= I40E_LINK_SPEED_1GB;
1396 if (link_speeds & ETH_LINK_SPEED_100M)
1397 link_speed |= I40E_LINK_SPEED_100MB;
1403 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1404 __rte_unused uint8_t abilities,
1405 __rte_unused uint8_t force_speed)
1407 /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1408 * for the link control limitation of that all link control should be
1409 * handled by firmware. It should follow up if link control will be
1410 * opened to software driver in future firmware versions.
1412 return I40E_SUCCESS;
1416 i40e_apply_link_speed(struct rte_eth_dev *dev)
1419 uint8_t abilities = 0;
1420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421 struct rte_eth_conf *conf = &dev->data->dev_conf;
1423 speed = i40e_parse_link_speeds(conf->link_speeds);
1424 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1425 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1426 abilities |= I40E_AQ_PHY_AN_ENABLED;
1428 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1430 return i40e_phy_conf_link(hw, abilities, speed);
1434 i40e_dev_start(struct rte_eth_dev *dev)
1436 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1437 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1438 struct i40e_vsi *main_vsi = pf->main_vsi;
1440 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1441 uint32_t intr_vector = 0;
1443 hw->adapter_stopped = 0;
1445 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1446 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1447 dev->data->port_id);
1451 rte_intr_disable(intr_handle);
1453 if ((rte_intr_cap_multiple(intr_handle) ||
1454 !RTE_ETH_DEV_SRIOV(dev).active) &&
1455 dev->data->dev_conf.intr_conf.rxq != 0) {
1456 intr_vector = dev->data->nb_rx_queues;
1457 if (rte_intr_efd_enable(intr_handle, intr_vector))
1461 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1462 intr_handle->intr_vec =
1463 rte_zmalloc("intr_vec",
1464 dev->data->nb_rx_queues * sizeof(int),
1466 if (!intr_handle->intr_vec) {
1467 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1468 " intr_vec\n", dev->data->nb_rx_queues);
1473 /* Initialize VSI */
1474 ret = i40e_dev_rxtx_init(pf);
1475 if (ret != I40E_SUCCESS) {
1476 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1480 /* Map queues with MSIX interrupt */
1481 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1482 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1483 i40e_vsi_queues_bind_intr(main_vsi);
1484 i40e_vsi_enable_queues_intr(main_vsi);
1486 /* Map VMDQ VSI queues with MSIX interrupt */
1487 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1488 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1489 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1490 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1493 /* enable FDIR MSIX interrupt */
1494 if (pf->fdir.fdir_vsi) {
1495 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1496 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1499 /* Enable all queues which have been configured */
1500 ret = i40e_dev_switch_queues(pf, TRUE);
1501 if (ret != I40E_SUCCESS) {
1502 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1506 /* Enable receiving broadcast packets */
1507 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1508 if (ret != I40E_SUCCESS)
1509 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1511 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1512 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1514 if (ret != I40E_SUCCESS)
1515 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1518 /* Apply link configure */
1519 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1520 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1521 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1522 PMD_DRV_LOG(ERR, "Invalid link setting");
1525 ret = i40e_apply_link_speed(dev);
1526 if (I40E_SUCCESS != ret) {
1527 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1531 if (!rte_intr_allow_others(intr_handle)) {
1532 rte_intr_callback_unregister(intr_handle,
1533 i40e_dev_interrupt_handler,
1535 /* configure and enable device interrupt */
1536 i40e_pf_config_irq0(hw, FALSE);
1537 i40e_pf_enable_irq0(hw);
1539 if (dev->data->dev_conf.intr_conf.lsc != 0)
1540 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1541 " no intr multiplex\n");
1544 /* enable uio intr after callback register */
1545 rte_intr_enable(intr_handle);
1547 return I40E_SUCCESS;
1550 i40e_dev_switch_queues(pf, FALSE);
1551 i40e_dev_clear_queues(dev);
1557 i40e_dev_stop(struct rte_eth_dev *dev)
1559 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1560 struct i40e_vsi *main_vsi = pf->main_vsi;
1561 struct i40e_mirror_rule *p_mirror;
1562 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1565 /* Disable all queues */
1566 i40e_dev_switch_queues(pf, FALSE);
1568 /* un-map queues with interrupt registers */
1569 i40e_vsi_disable_queues_intr(main_vsi);
1570 i40e_vsi_queues_unbind_intr(main_vsi);
1572 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1573 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1574 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1577 if (pf->fdir.fdir_vsi) {
1578 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1579 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1581 /* Clear all queues and release memory */
1582 i40e_dev_clear_queues(dev);
1585 i40e_dev_set_link_down(dev);
1587 /* Remove all mirror rules */
1588 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1589 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1592 pf->nb_mirror_rule = 0;
1594 if (!rte_intr_allow_others(intr_handle))
1595 /* resume to the default handler */
1596 rte_intr_callback_register(intr_handle,
1597 i40e_dev_interrupt_handler,
1600 /* Clean datapath event and queue/vec mapping */
1601 rte_intr_efd_disable(intr_handle);
1602 if (intr_handle->intr_vec) {
1603 rte_free(intr_handle->intr_vec);
1604 intr_handle->intr_vec = NULL;
1609 i40e_dev_close(struct rte_eth_dev *dev)
1611 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1612 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616 PMD_INIT_FUNC_TRACE();
1619 hw->adapter_stopped = 1;
1620 i40e_dev_free_queues(dev);
1622 /* Disable interrupt */
1623 i40e_pf_disable_irq0(hw);
1624 rte_intr_disable(&(dev->pci_dev->intr_handle));
1626 /* shutdown and destroy the HMC */
1627 i40e_shutdown_lan_hmc(hw);
1629 /* release all the existing VSIs and VEBs */
1630 i40e_fdir_teardown(pf);
1631 i40e_vsi_release(pf->main_vsi);
1633 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1634 i40e_vsi_release(pf->vmdq[i].vsi);
1635 pf->vmdq[i].vsi = NULL;
1641 /* shutdown the adminq */
1642 i40e_aq_queue_shutdown(hw, true);
1643 i40e_shutdown_adminq(hw);
1645 i40e_res_pool_destroy(&pf->qp_pool);
1646 i40e_res_pool_destroy(&pf->msix_pool);
1648 /* force a PF reset to clean anything leftover */
1649 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1650 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1651 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1652 I40E_WRITE_FLUSH(hw);
1656 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1658 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660 struct i40e_vsi *vsi = pf->main_vsi;
1663 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1665 if (status != I40E_SUCCESS)
1666 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1668 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1670 if (status != I40E_SUCCESS)
1671 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1676 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1678 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1679 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 struct i40e_vsi *vsi = pf->main_vsi;
1683 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1685 if (status != I40E_SUCCESS)
1686 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1688 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1690 if (status != I40E_SUCCESS)
1691 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1695 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1697 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1698 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699 struct i40e_vsi *vsi = pf->main_vsi;
1702 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1703 if (ret != I40E_SUCCESS)
1704 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1708 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1710 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712 struct i40e_vsi *vsi = pf->main_vsi;
1715 if (dev->data->promiscuous == 1)
1716 return; /* must remain in all_multicast mode */
1718 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1719 vsi->seid, FALSE, NULL);
1720 if (ret != I40E_SUCCESS)
1721 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1725 * Set device link up.
1728 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1730 /* re-apply link speed setting */
1731 return i40e_apply_link_speed(dev);
1735 * Set device link down.
1738 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1740 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1741 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1744 return i40e_phy_conf_link(hw, abilities, speed);
1748 i40e_dev_link_update(struct rte_eth_dev *dev,
1749 int wait_to_complete)
1751 #define CHECK_INTERVAL 100 /* 100ms */
1752 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754 struct i40e_link_status link_status;
1755 struct rte_eth_link link, old;
1757 unsigned rep_cnt = MAX_REPEAT_TIME;
1759 memset(&link, 0, sizeof(link));
1760 memset(&old, 0, sizeof(old));
1761 memset(&link_status, 0, sizeof(link_status));
1762 rte_i40e_dev_atomic_read_link_status(dev, &old);
1765 /* Get link status information from hardware */
1766 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1767 if (status != I40E_SUCCESS) {
1768 link.link_speed = ETH_SPEED_NUM_100M;
1769 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1770 PMD_DRV_LOG(ERR, "Failed to get link info");
1774 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1775 if (!wait_to_complete)
1778 rte_delay_ms(CHECK_INTERVAL);
1779 } while (!link.link_status && rep_cnt--);
1781 if (!link.link_status)
1784 /* i40e uses full duplex only */
1785 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1787 /* Parse the link status */
1788 switch (link_status.link_speed) {
1789 case I40E_LINK_SPEED_100MB:
1790 link.link_speed = ETH_SPEED_NUM_100M;
1792 case I40E_LINK_SPEED_1GB:
1793 link.link_speed = ETH_SPEED_NUM_1G;
1795 case I40E_LINK_SPEED_10GB:
1796 link.link_speed = ETH_SPEED_NUM_10G;
1798 case I40E_LINK_SPEED_20GB:
1799 link.link_speed = ETH_SPEED_NUM_20G;
1801 case I40E_LINK_SPEED_40GB:
1802 link.link_speed = ETH_SPEED_NUM_40G;
1805 link.link_speed = ETH_SPEED_NUM_100M;
1809 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1810 ETH_LINK_SPEED_FIXED);
1813 rte_i40e_dev_atomic_write_link_status(dev, &link);
1814 if (link.link_status == old.link_status)
1820 /* Get all the statistics of a VSI */
1822 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1824 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1825 struct i40e_eth_stats *nes = &vsi->eth_stats;
1826 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1827 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1829 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1830 vsi->offset_loaded, &oes->rx_bytes,
1832 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1833 vsi->offset_loaded, &oes->rx_unicast,
1835 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1836 vsi->offset_loaded, &oes->rx_multicast,
1837 &nes->rx_multicast);
1838 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1839 vsi->offset_loaded, &oes->rx_broadcast,
1840 &nes->rx_broadcast);
1841 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1842 &oes->rx_discards, &nes->rx_discards);
1843 /* GLV_REPC not supported */
1844 /* GLV_RMPC not supported */
1845 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1846 &oes->rx_unknown_protocol,
1847 &nes->rx_unknown_protocol);
1848 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1849 vsi->offset_loaded, &oes->tx_bytes,
1851 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1852 vsi->offset_loaded, &oes->tx_unicast,
1854 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1855 vsi->offset_loaded, &oes->tx_multicast,
1856 &nes->tx_multicast);
1857 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1858 vsi->offset_loaded, &oes->tx_broadcast,
1859 &nes->tx_broadcast);
1860 /* GLV_TDPC not supported */
1861 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1862 &oes->tx_errors, &nes->tx_errors);
1863 vsi->offset_loaded = true;
1865 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1867 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1868 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1869 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1870 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1871 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1872 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1873 nes->rx_unknown_protocol);
1874 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1875 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1876 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1877 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1878 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1879 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1880 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1885 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1888 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1889 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1891 /* Get statistics of struct i40e_eth_stats */
1892 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1893 I40E_GLPRT_GORCL(hw->port),
1894 pf->offset_loaded, &os->eth.rx_bytes,
1896 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1897 I40E_GLPRT_UPRCL(hw->port),
1898 pf->offset_loaded, &os->eth.rx_unicast,
1899 &ns->eth.rx_unicast);
1900 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1901 I40E_GLPRT_MPRCL(hw->port),
1902 pf->offset_loaded, &os->eth.rx_multicast,
1903 &ns->eth.rx_multicast);
1904 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1905 I40E_GLPRT_BPRCL(hw->port),
1906 pf->offset_loaded, &os->eth.rx_broadcast,
1907 &ns->eth.rx_broadcast);
1908 /* Workaround: CRC size should not be included in byte statistics,
1909 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1911 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1912 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1914 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1915 pf->offset_loaded, &os->eth.rx_discards,
1916 &ns->eth.rx_discards);
1917 /* GLPRT_REPC not supported */
1918 /* GLPRT_RMPC not supported */
1919 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1921 &os->eth.rx_unknown_protocol,
1922 &ns->eth.rx_unknown_protocol);
1923 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1924 I40E_GLPRT_GOTCL(hw->port),
1925 pf->offset_loaded, &os->eth.tx_bytes,
1927 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1928 I40E_GLPRT_UPTCL(hw->port),
1929 pf->offset_loaded, &os->eth.tx_unicast,
1930 &ns->eth.tx_unicast);
1931 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1932 I40E_GLPRT_MPTCL(hw->port),
1933 pf->offset_loaded, &os->eth.tx_multicast,
1934 &ns->eth.tx_multicast);
1935 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1936 I40E_GLPRT_BPTCL(hw->port),
1937 pf->offset_loaded, &os->eth.tx_broadcast,
1938 &ns->eth.tx_broadcast);
1939 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1940 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1941 /* GLPRT_TEPC not supported */
1943 /* additional port specific stats */
1944 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1945 pf->offset_loaded, &os->tx_dropped_link_down,
1946 &ns->tx_dropped_link_down);
1947 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1948 pf->offset_loaded, &os->crc_errors,
1950 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1951 pf->offset_loaded, &os->illegal_bytes,
1952 &ns->illegal_bytes);
1953 /* GLPRT_ERRBC not supported */
1954 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1955 pf->offset_loaded, &os->mac_local_faults,
1956 &ns->mac_local_faults);
1957 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1958 pf->offset_loaded, &os->mac_remote_faults,
1959 &ns->mac_remote_faults);
1960 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1961 pf->offset_loaded, &os->rx_length_errors,
1962 &ns->rx_length_errors);
1963 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1964 pf->offset_loaded, &os->link_xon_rx,
1966 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1967 pf->offset_loaded, &os->link_xoff_rx,
1969 for (i = 0; i < 8; i++) {
1970 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1972 &os->priority_xon_rx[i],
1973 &ns->priority_xon_rx[i]);
1974 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1976 &os->priority_xoff_rx[i],
1977 &ns->priority_xoff_rx[i]);
1979 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1980 pf->offset_loaded, &os->link_xon_tx,
1982 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1983 pf->offset_loaded, &os->link_xoff_tx,
1985 for (i = 0; i < 8; i++) {
1986 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1988 &os->priority_xon_tx[i],
1989 &ns->priority_xon_tx[i]);
1990 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1992 &os->priority_xoff_tx[i],
1993 &ns->priority_xoff_tx[i]);
1994 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1996 &os->priority_xon_2_xoff[i],
1997 &ns->priority_xon_2_xoff[i]);
1999 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2000 I40E_GLPRT_PRC64L(hw->port),
2001 pf->offset_loaded, &os->rx_size_64,
2003 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2004 I40E_GLPRT_PRC127L(hw->port),
2005 pf->offset_loaded, &os->rx_size_127,
2007 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2008 I40E_GLPRT_PRC255L(hw->port),
2009 pf->offset_loaded, &os->rx_size_255,
2011 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2012 I40E_GLPRT_PRC511L(hw->port),
2013 pf->offset_loaded, &os->rx_size_511,
2015 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2016 I40E_GLPRT_PRC1023L(hw->port),
2017 pf->offset_loaded, &os->rx_size_1023,
2019 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2020 I40E_GLPRT_PRC1522L(hw->port),
2021 pf->offset_loaded, &os->rx_size_1522,
2023 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2024 I40E_GLPRT_PRC9522L(hw->port),
2025 pf->offset_loaded, &os->rx_size_big,
2027 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2028 pf->offset_loaded, &os->rx_undersize,
2030 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2031 pf->offset_loaded, &os->rx_fragments,
2033 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2034 pf->offset_loaded, &os->rx_oversize,
2036 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2037 pf->offset_loaded, &os->rx_jabber,
2039 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2040 I40E_GLPRT_PTC64L(hw->port),
2041 pf->offset_loaded, &os->tx_size_64,
2043 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2044 I40E_GLPRT_PTC127L(hw->port),
2045 pf->offset_loaded, &os->tx_size_127,
2047 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2048 I40E_GLPRT_PTC255L(hw->port),
2049 pf->offset_loaded, &os->tx_size_255,
2051 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2052 I40E_GLPRT_PTC511L(hw->port),
2053 pf->offset_loaded, &os->tx_size_511,
2055 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2056 I40E_GLPRT_PTC1023L(hw->port),
2057 pf->offset_loaded, &os->tx_size_1023,
2059 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2060 I40E_GLPRT_PTC1522L(hw->port),
2061 pf->offset_loaded, &os->tx_size_1522,
2063 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2064 I40E_GLPRT_PTC9522L(hw->port),
2065 pf->offset_loaded, &os->tx_size_big,
2067 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2069 &os->fd_sb_match, &ns->fd_sb_match);
2070 /* GLPRT_MSPDC not supported */
2071 /* GLPRT_XEC not supported */
2073 pf->offset_loaded = true;
2076 i40e_update_vsi_stats(pf->main_vsi);
2079 /* Get all statistics of a port */
2081 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2083 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2084 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2088 /* call read registers - updates values, now write them to struct */
2089 i40e_read_stats_registers(pf, hw);
2091 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2092 pf->main_vsi->eth_stats.rx_multicast +
2093 pf->main_vsi->eth_stats.rx_broadcast -
2094 pf->main_vsi->eth_stats.rx_discards;
2095 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2096 pf->main_vsi->eth_stats.tx_multicast +
2097 pf->main_vsi->eth_stats.tx_broadcast;
2098 stats->ibytes = ns->eth.rx_bytes;
2099 stats->obytes = ns->eth.tx_bytes;
2100 stats->oerrors = ns->eth.tx_errors +
2101 pf->main_vsi->eth_stats.tx_errors;
2104 stats->imissed = ns->eth.rx_discards +
2105 pf->main_vsi->eth_stats.rx_discards;
2106 stats->ierrors = ns->crc_errors +
2107 ns->rx_length_errors + ns->rx_undersize +
2108 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2110 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2111 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2112 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2113 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2114 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2115 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2116 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2117 ns->eth.rx_unknown_protocol);
2118 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2119 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2120 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2121 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2122 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2123 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2125 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2126 ns->tx_dropped_link_down);
2127 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2128 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2130 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2131 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2132 ns->mac_local_faults);
2133 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2134 ns->mac_remote_faults);
2135 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2136 ns->rx_length_errors);
2137 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2138 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2139 for (i = 0; i < 8; i++) {
2140 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2141 i, ns->priority_xon_rx[i]);
2142 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2143 i, ns->priority_xoff_rx[i]);
2145 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2146 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2147 for (i = 0; i < 8; i++) {
2148 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2149 i, ns->priority_xon_tx[i]);
2150 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2151 i, ns->priority_xoff_tx[i]);
2152 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2153 i, ns->priority_xon_2_xoff[i]);
2155 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2156 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2157 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2158 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2159 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2160 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2161 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2162 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2163 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2164 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2165 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2166 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2167 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2168 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2169 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2170 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2171 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2172 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2173 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2174 ns->mac_short_packet_dropped);
2175 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2176 ns->checksum_error);
2177 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2178 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2181 /* Reset the statistics */
2183 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2185 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2186 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2188 /* Mark PF and VSI stats to update the offset, aka "reset" */
2189 pf->offset_loaded = false;
2191 pf->main_vsi->offset_loaded = false;
2193 /* read the stats, reading current register values into offset */
2194 i40e_read_stats_registers(pf, hw);
2198 i40e_xstats_calc_num(void)
2200 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2201 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2202 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2206 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2209 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2210 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2211 unsigned i, count, prio;
2212 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2214 count = i40e_xstats_calc_num();
2218 i40e_read_stats_registers(pf, hw);
2225 /* Get stats from i40e_eth_stats struct */
2226 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2227 snprintf(xstats[count].name, sizeof(xstats[count].name),
2228 "%s", rte_i40e_stats_strings[i].name);
2229 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2230 rte_i40e_stats_strings[i].offset);
2234 /* Get individiual stats from i40e_hw_port struct */
2235 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2236 snprintf(xstats[count].name, sizeof(xstats[count].name),
2237 "%s", rte_i40e_hw_port_strings[i].name);
2238 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2239 rte_i40e_hw_port_strings[i].offset);
2243 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2244 for (prio = 0; prio < 8; prio++) {
2245 snprintf(xstats[count].name,
2246 sizeof(xstats[count].name),
2247 "rx_priority%u_%s", prio,
2248 rte_i40e_rxq_prio_strings[i].name);
2249 xstats[count].value =
2250 *(uint64_t *)(((char *)hw_stats) +
2251 rte_i40e_rxq_prio_strings[i].offset +
2252 (sizeof(uint64_t) * prio));
2257 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2258 for (prio = 0; prio < 8; prio++) {
2259 snprintf(xstats[count].name,
2260 sizeof(xstats[count].name),
2261 "tx_priority%u_%s", prio,
2262 rte_i40e_txq_prio_strings[i].name);
2263 xstats[count].value =
2264 *(uint64_t *)(((char *)hw_stats) +
2265 rte_i40e_txq_prio_strings[i].offset +
2266 (sizeof(uint64_t) * prio));
2275 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2276 __rte_unused uint16_t queue_id,
2277 __rte_unused uint8_t stat_idx,
2278 __rte_unused uint8_t is_rx)
2280 PMD_INIT_FUNC_TRACE();
2286 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2288 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2289 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2290 struct i40e_vsi *vsi = pf->main_vsi;
2292 dev_info->max_rx_queues = vsi->nb_qps;
2293 dev_info->max_tx_queues = vsi->nb_qps;
2294 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2295 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2296 dev_info->max_mac_addrs = vsi->max_macaddrs;
2297 dev_info->max_vfs = dev->pci_dev->max_vfs;
2298 dev_info->rx_offload_capa =
2299 DEV_RX_OFFLOAD_VLAN_STRIP |
2300 DEV_RX_OFFLOAD_QINQ_STRIP |
2301 DEV_RX_OFFLOAD_IPV4_CKSUM |
2302 DEV_RX_OFFLOAD_UDP_CKSUM |
2303 DEV_RX_OFFLOAD_TCP_CKSUM;
2304 dev_info->tx_offload_capa =
2305 DEV_TX_OFFLOAD_VLAN_INSERT |
2306 DEV_TX_OFFLOAD_QINQ_INSERT |
2307 DEV_TX_OFFLOAD_IPV4_CKSUM |
2308 DEV_TX_OFFLOAD_UDP_CKSUM |
2309 DEV_TX_OFFLOAD_TCP_CKSUM |
2310 DEV_TX_OFFLOAD_SCTP_CKSUM |
2311 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2312 DEV_TX_OFFLOAD_TCP_TSO;
2313 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2315 dev_info->reta_size = pf->hash_lut_size;
2316 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2318 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2320 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2321 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2322 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2324 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2328 dev_info->default_txconf = (struct rte_eth_txconf) {
2330 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2331 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2332 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2334 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2335 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2336 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2337 ETH_TXQ_FLAGS_NOOFFLOADS,
2340 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2341 .nb_max = I40E_MAX_RING_DESC,
2342 .nb_min = I40E_MIN_RING_DESC,
2343 .nb_align = I40E_ALIGN_RING_DESC,
2346 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2347 .nb_max = I40E_MAX_RING_DESC,
2348 .nb_min = I40E_MIN_RING_DESC,
2349 .nb_align = I40E_ALIGN_RING_DESC,
2352 if (pf->flags & I40E_FLAG_VMDQ) {
2353 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2354 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2355 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2356 pf->max_nb_vmdq_vsi;
2357 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2358 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2359 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2362 if (i40e_is_40G_device(hw->device_id))
2364 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2367 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2371 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2373 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2374 struct i40e_vsi *vsi = pf->main_vsi;
2375 PMD_INIT_FUNC_TRACE();
2378 return i40e_vsi_add_vlan(vsi, vlan_id);
2380 return i40e_vsi_delete_vlan(vsi, vlan_id);
2384 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2385 enum rte_vlan_type vlan_type,
2388 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 uint64_t reg_r = 0, reg_w = 0;
2390 uint16_t reg_id = 0;
2393 switch (vlan_type) {
2394 case ETH_VLAN_TYPE_OUTER:
2397 case ETH_VLAN_TYPE_INNER:
2402 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2405 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2407 if (ret != I40E_SUCCESS) {
2408 PMD_DRV_LOG(ERR, "Fail to debug read from "
2409 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2413 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2414 "0x%08"PRIx64"", reg_id, reg_r);
2416 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2417 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2418 if (reg_r == reg_w) {
2420 PMD_DRV_LOG(DEBUG, "No need to write");
2424 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2426 if (ret != I40E_SUCCESS) {
2428 PMD_DRV_LOG(ERR, "Fail to debug write to "
2429 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2432 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2433 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2439 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2441 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2442 struct i40e_vsi *vsi = pf->main_vsi;
2444 if (mask & ETH_VLAN_FILTER_MASK) {
2445 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2446 i40e_vsi_config_vlan_filter(vsi, TRUE);
2448 i40e_vsi_config_vlan_filter(vsi, FALSE);
2451 if (mask & ETH_VLAN_STRIP_MASK) {
2452 /* Enable or disable VLAN stripping */
2453 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2454 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2456 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2459 if (mask & ETH_VLAN_EXTEND_MASK) {
2460 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2461 i40e_vsi_config_double_vlan(vsi, TRUE);
2463 i40e_vsi_config_double_vlan(vsi, FALSE);
2468 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2469 __rte_unused uint16_t queue,
2470 __rte_unused int on)
2472 PMD_INIT_FUNC_TRACE();
2476 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2478 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2479 struct i40e_vsi *vsi = pf->main_vsi;
2480 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2481 struct i40e_vsi_vlan_pvid_info info;
2483 memset(&info, 0, sizeof(info));
2486 info.config.pvid = pvid;
2488 info.config.reject.tagged =
2489 data->dev_conf.txmode.hw_vlan_reject_tagged;
2490 info.config.reject.untagged =
2491 data->dev_conf.txmode.hw_vlan_reject_untagged;
2494 return i40e_vsi_vlan_pvid_set(vsi, &info);
2498 i40e_dev_led_on(struct rte_eth_dev *dev)
2500 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501 uint32_t mode = i40e_led_get(hw);
2504 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2510 i40e_dev_led_off(struct rte_eth_dev *dev)
2512 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513 uint32_t mode = i40e_led_get(hw);
2516 i40e_led_set(hw, 0, false);
2522 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2524 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2525 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2527 fc_conf->pause_time = pf->fc_conf.pause_time;
2528 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2529 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2531 /* Return current mode according to actual setting*/
2532 switch (hw->fc.current_mode) {
2534 fc_conf->mode = RTE_FC_FULL;
2536 case I40E_FC_TX_PAUSE:
2537 fc_conf->mode = RTE_FC_TX_PAUSE;
2539 case I40E_FC_RX_PAUSE:
2540 fc_conf->mode = RTE_FC_RX_PAUSE;
2544 fc_conf->mode = RTE_FC_NONE;
2551 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2553 uint32_t mflcn_reg, fctrl_reg, reg;
2554 uint32_t max_high_water;
2555 uint8_t i, aq_failure;
2559 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2560 [RTE_FC_NONE] = I40E_FC_NONE,
2561 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2562 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2563 [RTE_FC_FULL] = I40E_FC_FULL
2566 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2568 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2569 if ((fc_conf->high_water > max_high_water) ||
2570 (fc_conf->high_water < fc_conf->low_water)) {
2571 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2572 "High_water must <= %d.", max_high_water);
2576 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2578 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2580 pf->fc_conf.pause_time = fc_conf->pause_time;
2581 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2582 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2584 PMD_INIT_FUNC_TRACE();
2586 /* All the link flow control related enable/disable register
2587 * configuration is handle by the F/W
2589 err = i40e_set_fc(hw, &aq_failure, true);
2593 if (i40e_is_40G_device(hw->device_id)) {
2594 /* Configure flow control refresh threshold,
2595 * the value for stat_tx_pause_refresh_timer[8]
2596 * is used for global pause operation.
2600 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2601 pf->fc_conf.pause_time);
2603 /* configure the timer value included in transmitted pause
2605 * the value for stat_tx_pause_quanta[8] is used for global
2608 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2609 pf->fc_conf.pause_time);
2611 fctrl_reg = I40E_READ_REG(hw,
2612 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2614 if (fc_conf->mac_ctrl_frame_fwd != 0)
2615 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2617 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2619 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2622 /* Configure pause time (2 TCs per register) */
2623 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2624 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2625 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2627 /* Configure flow control refresh threshold value */
2628 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2629 pf->fc_conf.pause_time / 2);
2631 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2633 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2634 *depending on configuration
2636 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2637 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2638 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2640 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2641 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2644 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2647 /* config the water marker both based on the packets and bytes */
2648 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2649 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2650 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2651 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2652 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2653 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2654 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2655 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2657 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2658 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2661 I40E_WRITE_FLUSH(hw);
2667 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2668 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2670 PMD_INIT_FUNC_TRACE();
2675 /* Add a MAC address, and update filters */
2677 i40e_macaddr_add(struct rte_eth_dev *dev,
2678 struct ether_addr *mac_addr,
2679 __rte_unused uint32_t index,
2682 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2683 struct i40e_mac_filter_info mac_filter;
2684 struct i40e_vsi *vsi;
2687 /* If VMDQ not enabled or configured, return */
2688 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2689 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2690 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2695 if (pool > pf->nb_cfg_vmdq_vsi) {
2696 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2697 pool, pf->nb_cfg_vmdq_vsi);
2701 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2702 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2703 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2705 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2710 vsi = pf->vmdq[pool - 1].vsi;
2712 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2713 if (ret != I40E_SUCCESS) {
2714 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2719 /* Remove a MAC address, and update filters */
2721 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2723 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2724 struct i40e_vsi *vsi;
2725 struct rte_eth_dev_data *data = dev->data;
2726 struct ether_addr *macaddr;
2731 macaddr = &(data->mac_addrs[index]);
2733 pool_sel = dev->data->mac_pool_sel[index];
2735 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2736 if (pool_sel & (1ULL << i)) {
2740 /* No VMDQ pool enabled or configured */
2741 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2742 (i > pf->nb_cfg_vmdq_vsi)) {
2743 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2747 vsi = pf->vmdq[i - 1].vsi;
2749 ret = i40e_vsi_delete_mac(vsi, macaddr);
2752 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2759 /* Set perfect match or hash match of MAC and VLAN for a VF */
2761 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2762 struct rte_eth_mac_filter *filter,
2766 struct i40e_mac_filter_info mac_filter;
2767 struct ether_addr old_mac;
2768 struct ether_addr *new_mac;
2769 struct i40e_pf_vf *vf = NULL;
2774 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2777 hw = I40E_PF_TO_HW(pf);
2779 if (filter == NULL) {
2780 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2784 new_mac = &filter->mac_addr;
2786 if (is_zero_ether_addr(new_mac)) {
2787 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2791 vf_id = filter->dst_id;
2793 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2794 PMD_DRV_LOG(ERR, "Invalid argument.");
2797 vf = &pf->vfs[vf_id];
2799 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2800 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2805 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2806 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2808 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2811 mac_filter.filter_type = filter->filter_type;
2812 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2813 if (ret != I40E_SUCCESS) {
2814 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2817 ether_addr_copy(new_mac, &pf->dev_addr);
2819 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2821 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2822 if (ret != I40E_SUCCESS) {
2823 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2827 /* Clear device address as it has been removed */
2828 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2829 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2835 /* MAC filter handle */
2837 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2841 struct rte_eth_mac_filter *filter;
2842 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2843 int ret = I40E_NOT_SUPPORTED;
2845 filter = (struct rte_eth_mac_filter *)(arg);
2847 switch (filter_op) {
2848 case RTE_ETH_FILTER_NOP:
2851 case RTE_ETH_FILTER_ADD:
2852 i40e_pf_disable_irq0(hw);
2854 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2855 i40e_pf_enable_irq0(hw);
2857 case RTE_ETH_FILTER_DELETE:
2858 i40e_pf_disable_irq0(hw);
2860 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2861 i40e_pf_enable_irq0(hw);
2864 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2865 ret = I40E_ERR_PARAM;
2873 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2875 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2876 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2882 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2883 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2886 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2890 uint32_t *lut_dw = (uint32_t *)lut;
2891 uint16_t i, lut_size_dw = lut_size / 4;
2893 for (i = 0; i < lut_size_dw; i++)
2894 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2901 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2903 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2904 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2910 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2911 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2914 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2918 uint32_t *lut_dw = (uint32_t *)lut;
2919 uint16_t i, lut_size_dw = lut_size / 4;
2921 for (i = 0; i < lut_size_dw; i++)
2922 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2923 I40E_WRITE_FLUSH(hw);
2930 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2931 struct rte_eth_rss_reta_entry64 *reta_conf,
2934 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2935 uint16_t i, lut_size = pf->hash_lut_size;
2936 uint16_t idx, shift;
2940 if (reta_size != lut_size ||
2941 reta_size > ETH_RSS_RETA_SIZE_512) {
2942 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2943 "(%d) doesn't match the number hardware can supported "
2944 "(%d)\n", reta_size, lut_size);
2948 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2950 PMD_DRV_LOG(ERR, "No memory can be allocated");
2953 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2956 for (i = 0; i < reta_size; i++) {
2957 idx = i / RTE_RETA_GROUP_SIZE;
2958 shift = i % RTE_RETA_GROUP_SIZE;
2959 if (reta_conf[idx].mask & (1ULL << shift))
2960 lut[i] = reta_conf[idx].reta[shift];
2962 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2971 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2972 struct rte_eth_rss_reta_entry64 *reta_conf,
2975 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2976 uint16_t i, lut_size = pf->hash_lut_size;
2977 uint16_t idx, shift;
2981 if (reta_size != lut_size ||
2982 reta_size > ETH_RSS_RETA_SIZE_512) {
2983 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2984 "(%d) doesn't match the number hardware can supported "
2985 "(%d)\n", reta_size, lut_size);
2989 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2991 PMD_DRV_LOG(ERR, "No memory can be allocated");
2995 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2998 for (i = 0; i < reta_size; i++) {
2999 idx = i / RTE_RETA_GROUP_SIZE;
3000 shift = i % RTE_RETA_GROUP_SIZE;
3001 if (reta_conf[idx].mask & (1ULL << shift))
3002 reta_conf[idx].reta[shift] = lut[i];
3012 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3013 * @hw: pointer to the HW structure
3014 * @mem: pointer to mem struct to fill out
3015 * @size: size of memory requested
3016 * @alignment: what to align the allocation to
3018 enum i40e_status_code
3019 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3020 struct i40e_dma_mem *mem,
3024 const struct rte_memzone *mz = NULL;
3025 char z_name[RTE_MEMZONE_NAMESIZE];
3028 return I40E_ERR_PARAM;
3030 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3031 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3032 alignment, RTE_PGSIZE_2M);
3034 return I40E_ERR_NO_MEMORY;
3038 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3039 mem->zone = (const void *)mz;
3040 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3041 "%"PRIu64, mz->name, mem->pa);
3043 return I40E_SUCCESS;
3047 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3048 * @hw: pointer to the HW structure
3049 * @mem: ptr to mem struct to free
3051 enum i40e_status_code
3052 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3053 struct i40e_dma_mem *mem)
3056 return I40E_ERR_PARAM;
3058 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3059 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3061 rte_memzone_free((const struct rte_memzone *)mem->zone);
3066 return I40E_SUCCESS;
3070 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3071 * @hw: pointer to the HW structure
3072 * @mem: pointer to mem struct to fill out
3073 * @size: size of memory requested
3075 enum i40e_status_code
3076 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3077 struct i40e_virt_mem *mem,
3081 return I40E_ERR_PARAM;
3084 mem->va = rte_zmalloc("i40e", size, 0);
3087 return I40E_SUCCESS;
3089 return I40E_ERR_NO_MEMORY;
3093 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3094 * @hw: pointer to the HW structure
3095 * @mem: pointer to mem struct to free
3097 enum i40e_status_code
3098 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3099 struct i40e_virt_mem *mem)
3102 return I40E_ERR_PARAM;
3107 return I40E_SUCCESS;
3111 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3113 rte_spinlock_init(&sp->spinlock);
3117 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3119 rte_spinlock_lock(&sp->spinlock);
3123 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3125 rte_spinlock_unlock(&sp->spinlock);
3129 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3135 * Get the hardware capabilities, which will be parsed
3136 * and saved into struct i40e_hw.
3139 i40e_get_cap(struct i40e_hw *hw)
3141 struct i40e_aqc_list_capabilities_element_resp *buf;
3142 uint16_t len, size = 0;
3145 /* Calculate a huge enough buff for saving response data temporarily */
3146 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3147 I40E_MAX_CAP_ELE_NUM;
3148 buf = rte_zmalloc("i40e", len, 0);
3150 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3151 return I40E_ERR_NO_MEMORY;
3154 /* Get, parse the capabilities and save it to hw */
3155 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3156 i40e_aqc_opc_list_func_capabilities, NULL);
3157 if (ret != I40E_SUCCESS)
3158 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3160 /* Free the temporary buffer after being used */
3167 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3169 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3170 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3171 uint16_t qp_count = 0, vsi_count = 0;
3173 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3174 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3177 /* Add the parameter init for LFC */
3178 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3179 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3180 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3182 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3183 pf->max_num_vsi = hw->func_caps.num_vsis;
3184 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3185 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3186 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3188 /* FDir queue/VSI allocation */
3189 pf->fdir_qp_offset = 0;
3190 if (hw->func_caps.fd) {
3191 pf->flags |= I40E_FLAG_FDIR;
3192 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3194 pf->fdir_nb_qps = 0;
3196 qp_count += pf->fdir_nb_qps;
3199 /* LAN queue/VSI allocation */
3200 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3201 if (!hw->func_caps.rss) {
3204 pf->flags |= I40E_FLAG_RSS;
3205 if (hw->mac.type == I40E_MAC_X722)
3206 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3207 pf->lan_nb_qps = pf->lan_nb_qp_max;
3209 qp_count += pf->lan_nb_qps;
3212 /* VF queue/VSI allocation */
3213 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3214 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3215 pf->flags |= I40E_FLAG_SRIOV;
3216 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3217 pf->vf_num = dev->pci_dev->max_vfs;
3218 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3219 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3220 pf->vf_nb_qps * pf->vf_num);
3225 qp_count += pf->vf_nb_qps * pf->vf_num;
3226 vsi_count += pf->vf_num;
3228 /* VMDq queue/VSI allocation */
3229 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3230 pf->vmdq_nb_qps = 0;
3231 pf->max_nb_vmdq_vsi = 0;
3232 if (hw->func_caps.vmdq) {
3233 if (qp_count < hw->func_caps.num_tx_qp &&
3234 vsi_count < hw->func_caps.num_vsis) {
3235 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3236 qp_count) / pf->vmdq_nb_qp_max;
3238 /* Limit the maximum number of VMDq vsi to the maximum
3239 * ethdev can support
3241 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3242 hw->func_caps.num_vsis - vsi_count);
3243 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3245 if (pf->max_nb_vmdq_vsi) {
3246 pf->flags |= I40E_FLAG_VMDQ;
3247 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3248 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3249 "per VMDQ VSI, in total %u queues",
3250 pf->max_nb_vmdq_vsi,
3251 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3252 pf->max_nb_vmdq_vsi);
3254 PMD_DRV_LOG(INFO, "No enough queues left for "
3258 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3261 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3262 vsi_count += pf->max_nb_vmdq_vsi;
3264 if (hw->func_caps.dcb)
3265 pf->flags |= I40E_FLAG_DCB;
3267 if (qp_count > hw->func_caps.num_tx_qp) {
3268 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3269 "the hardware maximum %u", qp_count,
3270 hw->func_caps.num_tx_qp);
3273 if (vsi_count > hw->func_caps.num_vsis) {
3274 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3275 "the hardware maximum %u", vsi_count,
3276 hw->func_caps.num_vsis);
3284 i40e_pf_get_switch_config(struct i40e_pf *pf)
3286 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3287 struct i40e_aqc_get_switch_config_resp *switch_config;
3288 struct i40e_aqc_switch_config_element_resp *element;
3289 uint16_t start_seid = 0, num_reported;
3292 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3293 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3294 if (!switch_config) {
3295 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3299 /* Get the switch configurations */
3300 ret = i40e_aq_get_switch_config(hw, switch_config,
3301 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3302 if (ret != I40E_SUCCESS) {
3303 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3306 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3307 if (num_reported != 1) { /* The number should be 1 */
3308 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3312 /* Parse the switch configuration elements */
3313 element = &(switch_config->element[0]);
3314 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3315 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3316 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3318 PMD_DRV_LOG(INFO, "Unknown element type");
3321 rte_free(switch_config);
3327 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3330 struct pool_entry *entry;
3332 if (pool == NULL || num == 0)
3335 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3336 if (entry == NULL) {
3337 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3341 /* queue heap initialize */
3342 pool->num_free = num;
3343 pool->num_alloc = 0;
3345 LIST_INIT(&pool->alloc_list);
3346 LIST_INIT(&pool->free_list);
3348 /* Initialize element */
3352 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3357 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3359 struct pool_entry *entry, *next_entry;
3364 for (entry = LIST_FIRST(&pool->alloc_list);
3365 entry && (next_entry = LIST_NEXT(entry, next), 1);
3366 entry = next_entry) {
3367 LIST_REMOVE(entry, next);
3371 for (entry = LIST_FIRST(&pool->free_list);
3372 entry && (next_entry = LIST_NEXT(entry, next), 1);
3373 entry = next_entry) {
3374 LIST_REMOVE(entry, next);
3379 pool->num_alloc = 0;
3381 LIST_INIT(&pool->alloc_list);
3382 LIST_INIT(&pool->free_list);
3386 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3389 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3390 uint32_t pool_offset;
3394 PMD_DRV_LOG(ERR, "Invalid parameter");
3398 pool_offset = base - pool->base;
3399 /* Lookup in alloc list */
3400 LIST_FOREACH(entry, &pool->alloc_list, next) {
3401 if (entry->base == pool_offset) {
3402 valid_entry = entry;
3403 LIST_REMOVE(entry, next);
3408 /* Not find, return */
3409 if (valid_entry == NULL) {
3410 PMD_DRV_LOG(ERR, "Failed to find entry");
3415 * Found it, move it to free list and try to merge.
3416 * In order to make merge easier, always sort it by qbase.
3417 * Find adjacent prev and last entries.
3420 LIST_FOREACH(entry, &pool->free_list, next) {
3421 if (entry->base > valid_entry->base) {
3429 /* Try to merge with next one*/
3431 /* Merge with next one */
3432 if (valid_entry->base + valid_entry->len == next->base) {
3433 next->base = valid_entry->base;
3434 next->len += valid_entry->len;
3435 rte_free(valid_entry);
3442 /* Merge with previous one */
3443 if (prev->base + prev->len == valid_entry->base) {
3444 prev->len += valid_entry->len;
3445 /* If it merge with next one, remove next node */
3447 LIST_REMOVE(valid_entry, next);
3448 rte_free(valid_entry);
3450 rte_free(valid_entry);
3456 /* Not find any entry to merge, insert */
3459 LIST_INSERT_AFTER(prev, valid_entry, next);
3460 else if (next != NULL)
3461 LIST_INSERT_BEFORE(next, valid_entry, next);
3462 else /* It's empty list, insert to head */
3463 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3466 pool->num_free += valid_entry->len;
3467 pool->num_alloc -= valid_entry->len;
3473 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3476 struct pool_entry *entry, *valid_entry;
3478 if (pool == NULL || num == 0) {
3479 PMD_DRV_LOG(ERR, "Invalid parameter");
3483 if (pool->num_free < num) {
3484 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3485 num, pool->num_free);
3490 /* Lookup in free list and find most fit one */
3491 LIST_FOREACH(entry, &pool->free_list, next) {
3492 if (entry->len >= num) {
3494 if (entry->len == num) {
3495 valid_entry = entry;
3498 if (valid_entry == NULL || valid_entry->len > entry->len)
3499 valid_entry = entry;
3503 /* Not find one to satisfy the request, return */
3504 if (valid_entry == NULL) {
3505 PMD_DRV_LOG(ERR, "No valid entry found");
3509 * The entry have equal queue number as requested,
3510 * remove it from alloc_list.
3512 if (valid_entry->len == num) {
3513 LIST_REMOVE(valid_entry, next);
3516 * The entry have more numbers than requested,
3517 * create a new entry for alloc_list and minus its
3518 * queue base and number in free_list.
3520 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3521 if (entry == NULL) {
3522 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3526 entry->base = valid_entry->base;
3528 valid_entry->base += num;
3529 valid_entry->len -= num;
3530 valid_entry = entry;
3533 /* Insert it into alloc list, not sorted */
3534 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3536 pool->num_free -= valid_entry->len;
3537 pool->num_alloc += valid_entry->len;
3539 return valid_entry->base + pool->base;
3543 * bitmap_is_subset - Check whether src2 is subset of src1
3546 bitmap_is_subset(uint8_t src1, uint8_t src2)
3548 return !((src1 ^ src2) & src2);
3551 static enum i40e_status_code
3552 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3554 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3556 /* If DCB is not supported, only default TC is supported */
3557 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3558 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3559 return I40E_NOT_SUPPORTED;
3562 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3563 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3564 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3566 return I40E_NOT_SUPPORTED;
3568 return I40E_SUCCESS;
3572 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3573 struct i40e_vsi_vlan_pvid_info *info)
3576 struct i40e_vsi_context ctxt;
3577 uint8_t vlan_flags = 0;
3580 if (vsi == NULL || info == NULL) {
3581 PMD_DRV_LOG(ERR, "invalid parameters");
3582 return I40E_ERR_PARAM;
3586 vsi->info.pvid = info->config.pvid;
3588 * If insert pvid is enabled, only tagged pkts are
3589 * allowed to be sent out.
3591 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3592 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3595 if (info->config.reject.tagged == 0)
3596 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3598 if (info->config.reject.untagged == 0)
3599 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3601 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3602 I40E_AQ_VSI_PVLAN_MODE_MASK);
3603 vsi->info.port_vlan_flags |= vlan_flags;
3604 vsi->info.valid_sections =
3605 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3606 memset(&ctxt, 0, sizeof(ctxt));
3607 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3608 ctxt.seid = vsi->seid;
3610 hw = I40E_VSI_TO_HW(vsi);
3611 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3612 if (ret != I40E_SUCCESS)
3613 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3619 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3621 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3623 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3625 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3626 if (ret != I40E_SUCCESS)
3630 PMD_DRV_LOG(ERR, "seid not valid");
3634 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3635 tc_bw_data.tc_valid_bits = enabled_tcmap;
3636 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3637 tc_bw_data.tc_bw_credits[i] =
3638 (enabled_tcmap & (1 << i)) ? 1 : 0;
3640 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3641 if (ret != I40E_SUCCESS) {
3642 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3646 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3647 sizeof(vsi->info.qs_handle));
3648 return I40E_SUCCESS;
3651 static enum i40e_status_code
3652 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3653 struct i40e_aqc_vsi_properties_data *info,
3654 uint8_t enabled_tcmap)
3656 enum i40e_status_code ret;
3657 int i, total_tc = 0;
3658 uint16_t qpnum_per_tc, bsf, qp_idx;
3660 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3661 if (ret != I40E_SUCCESS)
3664 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3665 if (enabled_tcmap & (1 << i))
3667 vsi->enabled_tc = enabled_tcmap;
3669 /* Number of queues per enabled TC */
3670 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3671 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3672 bsf = rte_bsf32(qpnum_per_tc);
3674 /* Adjust the queue number to actual queues that can be applied */
3675 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3676 vsi->nb_qps = qpnum_per_tc * total_tc;
3679 * Configure TC and queue mapping parameters, for enabled TC,
3680 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3681 * default queue will serve it.
3684 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3685 if (vsi->enabled_tc & (1 << i)) {
3686 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3687 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3688 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3689 qp_idx += qpnum_per_tc;
3691 info->tc_mapping[i] = 0;
3694 /* Associate queue number with VSI */
3695 if (vsi->type == I40E_VSI_SRIOV) {
3696 info->mapping_flags |=
3697 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3698 for (i = 0; i < vsi->nb_qps; i++)
3699 info->queue_mapping[i] =
3700 rte_cpu_to_le_16(vsi->base_queue + i);
3702 info->mapping_flags |=
3703 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3704 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3706 info->valid_sections |=
3707 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3709 return I40E_SUCCESS;
3713 i40e_veb_release(struct i40e_veb *veb)
3715 struct i40e_vsi *vsi;
3718 if (veb == NULL || veb->associate_vsi == NULL)
3721 if (!TAILQ_EMPTY(&veb->head)) {
3722 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3726 vsi = veb->associate_vsi;
3727 hw = I40E_VSI_TO_HW(vsi);
3729 vsi->uplink_seid = veb->uplink_seid;
3730 i40e_aq_delete_element(hw, veb->seid, NULL);
3733 return I40E_SUCCESS;
3737 static struct i40e_veb *
3738 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3740 struct i40e_veb *veb;
3744 if (NULL == pf || vsi == NULL) {
3745 PMD_DRV_LOG(ERR, "veb setup failed, "
3746 "associated VSI shouldn't null");
3749 hw = I40E_PF_TO_HW(pf);
3751 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3753 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3757 veb->associate_vsi = vsi;
3758 TAILQ_INIT(&veb->head);
3759 veb->uplink_seid = vsi->uplink_seid;
3761 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3762 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3764 if (ret != I40E_SUCCESS) {
3765 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3766 hw->aq.asq_last_status);
3770 /* get statistics index */
3771 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3772 &veb->stats_idx, NULL, NULL, NULL);
3773 if (ret != I40E_SUCCESS) {
3774 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3775 hw->aq.asq_last_status);
3779 /* Get VEB bandwidth, to be implemented */
3780 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3781 vsi->uplink_seid = veb->seid;
3790 i40e_vsi_release(struct i40e_vsi *vsi)
3794 struct i40e_vsi_list *vsi_list;
3796 struct i40e_mac_filter *f;
3799 return I40E_SUCCESS;
3801 pf = I40E_VSI_TO_PF(vsi);
3802 hw = I40E_VSI_TO_HW(vsi);
3804 /* VSI has child to attach, release child first */
3806 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3807 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3809 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3811 i40e_veb_release(vsi->veb);
3814 /* Remove all macvlan filters of the VSI */
3815 i40e_vsi_remove_all_macvlan_filter(vsi);
3816 TAILQ_FOREACH(f, &vsi->mac_list, next)
3819 if (vsi->type != I40E_VSI_MAIN) {
3820 /* Remove vsi from parent's sibling list */
3821 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3822 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3823 return I40E_ERR_PARAM;
3825 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3826 &vsi->sib_vsi_list, list);
3828 /* Remove all switch element of the VSI */
3829 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3830 if (ret != I40E_SUCCESS)
3831 PMD_DRV_LOG(ERR, "Failed to delete element");
3833 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3835 if (vsi->type != I40E_VSI_SRIOV)
3836 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3839 return I40E_SUCCESS;
3843 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3845 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3846 struct i40e_aqc_remove_macvlan_element_data def_filter;
3847 struct i40e_mac_filter_info filter;
3850 if (vsi->type != I40E_VSI_MAIN)
3851 return I40E_ERR_CONFIG;
3852 memset(&def_filter, 0, sizeof(def_filter));
3853 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3855 def_filter.vlan_tag = 0;
3856 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3857 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3858 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3859 if (ret != I40E_SUCCESS) {
3860 struct i40e_mac_filter *f;
3861 struct ether_addr *mac;
3863 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3865 /* It needs to add the permanent mac into mac list */
3866 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3868 PMD_DRV_LOG(ERR, "failed to allocate memory");
3869 return I40E_ERR_NO_MEMORY;
3871 mac = &f->mac_info.mac_addr;
3872 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3874 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3875 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3880 (void)rte_memcpy(&filter.mac_addr,
3881 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3882 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3883 return i40e_vsi_add_mac(vsi, &filter);
3887 * i40e_vsi_get_bw_config - Query VSI BW Information
3888 * @vsi: the VSI to be queried
3890 * Returns 0 on success, negative value on failure
3892 static enum i40e_status_code
3893 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3895 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3896 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3897 struct i40e_hw *hw = &vsi->adapter->hw;
3902 memset(&bw_config, 0, sizeof(bw_config));
3903 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3904 if (ret != I40E_SUCCESS) {
3905 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3906 hw->aq.asq_last_status);
3910 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3911 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3912 &ets_sla_config, NULL);
3913 if (ret != I40E_SUCCESS) {
3914 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3915 "configuration %u", hw->aq.asq_last_status);
3919 /* store and print out BW info */
3920 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3921 vsi->bw_info.bw_max = bw_config.max_bw;
3922 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3923 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3924 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3925 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3927 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3928 vsi->bw_info.bw_ets_share_credits[i] =
3929 ets_sla_config.share_credits[i];
3930 vsi->bw_info.bw_ets_credits[i] =
3931 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3932 /* 4 bits per TC, 4th bit is reserved */
3933 vsi->bw_info.bw_ets_max[i] =
3934 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3935 RTE_LEN2MASK(3, uint8_t));
3936 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3937 vsi->bw_info.bw_ets_share_credits[i]);
3938 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3939 vsi->bw_info.bw_ets_credits[i]);
3940 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3941 vsi->bw_info.bw_ets_max[i]);
3944 return I40E_SUCCESS;
3947 /* i40e_enable_pf_lb
3948 * @pf: pointer to the pf structure
3950 * allow loopback on pf
3953 i40e_enable_pf_lb(struct i40e_pf *pf)
3955 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3956 struct i40e_vsi_context ctxt;
3959 /* Use the FW API if FW >= v5.0 */
3960 if (hw->aq.fw_maj_ver < 5) {
3961 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3965 memset(&ctxt, 0, sizeof(ctxt));
3966 ctxt.seid = pf->main_vsi_seid;
3967 ctxt.pf_num = hw->pf_id;
3968 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3970 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3971 ret, hw->aq.asq_last_status);
3974 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3975 ctxt.info.valid_sections =
3976 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3977 ctxt.info.switch_id |=
3978 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3980 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3982 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3983 hw->aq.asq_last_status);
3988 i40e_vsi_setup(struct i40e_pf *pf,
3989 enum i40e_vsi_type type,
3990 struct i40e_vsi *uplink_vsi,
3991 uint16_t user_param)
3993 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3994 struct i40e_vsi *vsi;
3995 struct i40e_mac_filter_info filter;
3997 struct i40e_vsi_context ctxt;
3998 struct ether_addr broadcast =
3999 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4001 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
4002 PMD_DRV_LOG(ERR, "VSI setup failed, "
4003 "VSI link shouldn't be NULL");
4007 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4008 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4009 "uplink VSI should be NULL");
4013 /* If uplink vsi didn't setup VEB, create one first */
4014 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4015 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4017 if (NULL == uplink_vsi->veb) {
4018 PMD_DRV_LOG(ERR, "VEB setup failed");
4021 /* set ALLOWLOOPBACk on pf, when veb is created */
4022 i40e_enable_pf_lb(pf);
4025 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4027 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4030 TAILQ_INIT(&vsi->mac_list);
4032 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4033 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4034 vsi->parent_vsi = uplink_vsi;
4035 vsi->user_param = user_param;
4036 /* Allocate queues */
4037 switch (vsi->type) {
4038 case I40E_VSI_MAIN :
4039 vsi->nb_qps = pf->lan_nb_qps;
4041 case I40E_VSI_SRIOV :
4042 vsi->nb_qps = pf->vf_nb_qps;
4044 case I40E_VSI_VMDQ2:
4045 vsi->nb_qps = pf->vmdq_nb_qps;
4048 vsi->nb_qps = pf->fdir_nb_qps;
4054 * The filter status descriptor is reported in rx queue 0,
4055 * while the tx queue for fdir filter programming has no
4056 * such constraints, can be non-zero queues.
4057 * To simplify it, choose FDIR vsi use queue 0 pair.
4058 * To make sure it will use queue 0 pair, queue allocation
4059 * need be done before this function is called
4061 if (type != I40E_VSI_FDIR) {
4062 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4064 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4068 vsi->base_queue = ret;
4070 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4072 /* VF has MSIX interrupt in VF range, don't allocate here */
4073 if (type == I40E_VSI_MAIN) {
4074 ret = i40e_res_pool_alloc(&pf->msix_pool,
4075 RTE_MIN(vsi->nb_qps,
4076 RTE_MAX_RXTX_INTR_VEC_ID));
4078 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4080 goto fail_queue_alloc;
4082 vsi->msix_intr = ret;
4083 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4084 } else if (type != I40E_VSI_SRIOV) {
4085 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4087 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4088 goto fail_queue_alloc;
4090 vsi->msix_intr = ret;
4098 if (type == I40E_VSI_MAIN) {
4099 /* For main VSI, no need to add since it's default one */
4100 vsi->uplink_seid = pf->mac_seid;
4101 vsi->seid = pf->main_vsi_seid;
4102 /* Bind queues with specific MSIX interrupt */
4104 * Needs 2 interrupt at least, one for misc cause which will
4105 * enabled from OS side, Another for queues binding the
4106 * interrupt from device side only.
4109 /* Get default VSI parameters from hardware */
4110 memset(&ctxt, 0, sizeof(ctxt));
4111 ctxt.seid = vsi->seid;
4112 ctxt.pf_num = hw->pf_id;
4113 ctxt.uplink_seid = vsi->uplink_seid;
4115 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4116 if (ret != I40E_SUCCESS) {
4117 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4118 goto fail_msix_alloc;
4120 (void)rte_memcpy(&vsi->info, &ctxt.info,
4121 sizeof(struct i40e_aqc_vsi_properties_data));
4122 vsi->vsi_id = ctxt.vsi_number;
4123 vsi->info.valid_sections = 0;
4125 /* Configure tc, enabled TC0 only */
4126 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4128 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4129 goto fail_msix_alloc;
4132 /* TC, queue mapping */
4133 memset(&ctxt, 0, sizeof(ctxt));
4134 vsi->info.valid_sections |=
4135 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4136 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4137 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4138 (void)rte_memcpy(&ctxt.info, &vsi->info,
4139 sizeof(struct i40e_aqc_vsi_properties_data));
4140 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4141 I40E_DEFAULT_TCMAP);
4142 if (ret != I40E_SUCCESS) {
4143 PMD_DRV_LOG(ERR, "Failed to configure "
4144 "TC queue mapping");
4145 goto fail_msix_alloc;
4147 ctxt.seid = vsi->seid;
4148 ctxt.pf_num = hw->pf_id;
4149 ctxt.uplink_seid = vsi->uplink_seid;
4152 /* Update VSI parameters */
4153 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4154 if (ret != I40E_SUCCESS) {
4155 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4156 goto fail_msix_alloc;
4159 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4160 sizeof(vsi->info.tc_mapping));
4161 (void)rte_memcpy(&vsi->info.queue_mapping,
4162 &ctxt.info.queue_mapping,
4163 sizeof(vsi->info.queue_mapping));
4164 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4165 vsi->info.valid_sections = 0;
4167 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4171 * Updating default filter settings are necessary to prevent
4172 * reception of tagged packets.
4173 * Some old firmware configurations load a default macvlan
4174 * filter which accepts both tagged and untagged packets.
4175 * The updating is to use a normal filter instead if needed.
4176 * For NVM 4.2.2 or after, the updating is not needed anymore.
4177 * The firmware with correct configurations load the default
4178 * macvlan filter which is expected and cannot be removed.
4180 i40e_update_default_filter_setting(vsi);
4181 i40e_config_qinq(hw, vsi);
4182 } else if (type == I40E_VSI_SRIOV) {
4183 memset(&ctxt, 0, sizeof(ctxt));
4185 * For other VSI, the uplink_seid equals to uplink VSI's
4186 * uplink_seid since they share same VEB
4188 vsi->uplink_seid = uplink_vsi->uplink_seid;
4189 ctxt.pf_num = hw->pf_id;
4190 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4191 ctxt.uplink_seid = vsi->uplink_seid;
4192 ctxt.connection_type = 0x1;
4193 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4195 /* Use the VEB configuration if FW >= v5.0 */
4196 if (hw->aq.fw_maj_ver >= 5) {
4197 /* Configure switch ID */
4198 ctxt.info.valid_sections |=
4199 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4200 ctxt.info.switch_id =
4201 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4204 /* Configure port/vlan */
4205 ctxt.info.valid_sections |=
4206 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4207 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4208 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4209 I40E_DEFAULT_TCMAP);
4210 if (ret != I40E_SUCCESS) {
4211 PMD_DRV_LOG(ERR, "Failed to configure "
4212 "TC queue mapping");
4213 goto fail_msix_alloc;
4215 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4216 ctxt.info.valid_sections |=
4217 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4219 * Since VSI is not created yet, only configure parameter,
4220 * will add vsi below.
4223 i40e_config_qinq(hw, vsi);
4224 } else if (type == I40E_VSI_VMDQ2) {
4225 memset(&ctxt, 0, sizeof(ctxt));
4227 * For other VSI, the uplink_seid equals to uplink VSI's
4228 * uplink_seid since they share same VEB
4230 vsi->uplink_seid = uplink_vsi->uplink_seid;
4231 ctxt.pf_num = hw->pf_id;
4233 ctxt.uplink_seid = vsi->uplink_seid;
4234 ctxt.connection_type = 0x1;
4235 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4237 ctxt.info.valid_sections |=
4238 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4239 /* user_param carries flag to enable loop back */
4241 ctxt.info.switch_id =
4242 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4243 ctxt.info.switch_id |=
4244 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4247 /* Configure port/vlan */
4248 ctxt.info.valid_sections |=
4249 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4250 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4251 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4252 I40E_DEFAULT_TCMAP);
4253 if (ret != I40E_SUCCESS) {
4254 PMD_DRV_LOG(ERR, "Failed to configure "
4255 "TC queue mapping");
4256 goto fail_msix_alloc;
4258 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4259 ctxt.info.valid_sections |=
4260 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4261 } else if (type == I40E_VSI_FDIR) {
4262 memset(&ctxt, 0, sizeof(ctxt));
4263 vsi->uplink_seid = uplink_vsi->uplink_seid;
4264 ctxt.pf_num = hw->pf_id;
4266 ctxt.uplink_seid = vsi->uplink_seid;
4267 ctxt.connection_type = 0x1; /* regular data port */
4268 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4269 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4270 I40E_DEFAULT_TCMAP);
4271 if (ret != I40E_SUCCESS) {
4272 PMD_DRV_LOG(ERR, "Failed to configure "
4273 "TC queue mapping.");
4274 goto fail_msix_alloc;
4276 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4277 ctxt.info.valid_sections |=
4278 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4280 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4281 goto fail_msix_alloc;
4284 if (vsi->type != I40E_VSI_MAIN) {
4285 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4286 if (ret != I40E_SUCCESS) {
4287 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4288 hw->aq.asq_last_status);
4289 goto fail_msix_alloc;
4291 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4292 vsi->info.valid_sections = 0;
4293 vsi->seid = ctxt.seid;
4294 vsi->vsi_id = ctxt.vsi_number;
4295 vsi->sib_vsi_list.vsi = vsi;
4296 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4297 &vsi->sib_vsi_list, list);
4300 /* MAC/VLAN configuration */
4301 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4302 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4304 ret = i40e_vsi_add_mac(vsi, &filter);
4305 if (ret != I40E_SUCCESS) {
4306 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4307 goto fail_msix_alloc;
4310 /* Get VSI BW information */
4311 i40e_vsi_get_bw_config(vsi);
4314 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4316 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4322 /* Configure vlan filter on or off */
4324 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4327 struct i40e_mac_filter *f;
4328 struct i40e_mac_filter_info *mac_filter;
4329 enum rte_mac_filter_type desired_filter;
4330 int ret = I40E_SUCCESS;
4333 /* Filter to match MAC and VLAN */
4334 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4336 /* Filter to match only MAC */
4337 desired_filter = RTE_MAC_PERFECT_MATCH;
4342 mac_filter = rte_zmalloc("mac_filter_info_data",
4343 num * sizeof(*mac_filter), 0);
4344 if (mac_filter == NULL) {
4345 PMD_DRV_LOG(ERR, "failed to allocate memory");
4346 return I40E_ERR_NO_MEMORY;
4351 /* Remove all existing mac */
4352 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4353 mac_filter[i] = f->mac_info;
4354 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4356 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4357 on ? "enable" : "disable");
4363 /* Override with new filter */
4364 for (i = 0; i < num; i++) {
4365 mac_filter[i].filter_type = desired_filter;
4366 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4368 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4369 on ? "enable" : "disable");
4375 rte_free(mac_filter);
4379 /* Configure vlan stripping on or off */
4381 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4383 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4384 struct i40e_vsi_context ctxt;
4386 int ret = I40E_SUCCESS;
4388 /* Check if it has been already on or off */
4389 if (vsi->info.valid_sections &
4390 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4392 if ((vsi->info.port_vlan_flags &
4393 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4394 return 0; /* already on */
4396 if ((vsi->info.port_vlan_flags &
4397 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4398 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4399 return 0; /* already off */
4404 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4406 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4407 vsi->info.valid_sections =
4408 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4409 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4410 vsi->info.port_vlan_flags |= vlan_flags;
4411 ctxt.seid = vsi->seid;
4412 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4413 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4415 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4416 on ? "enable" : "disable");
4422 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4424 struct rte_eth_dev_data *data = dev->data;
4428 /* Apply vlan offload setting */
4429 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4430 i40e_vlan_offload_set(dev, mask);
4432 /* Apply double-vlan setting, not implemented yet */
4434 /* Apply pvid setting */
4435 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4436 data->dev_conf.txmode.hw_vlan_insert_pvid);
4438 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4444 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4446 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4448 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4452 i40e_update_flow_control(struct i40e_hw *hw)
4454 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4455 struct i40e_link_status link_status;
4456 uint32_t rxfc = 0, txfc = 0, reg;
4460 memset(&link_status, 0, sizeof(link_status));
4461 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4462 if (ret != I40E_SUCCESS) {
4463 PMD_DRV_LOG(ERR, "Failed to get link status information");
4464 goto write_reg; /* Disable flow control */
4467 an_info = hw->phy.link_info.an_info;
4468 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4469 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4470 ret = I40E_ERR_NOT_READY;
4471 goto write_reg; /* Disable flow control */
4474 * If link auto negotiation is enabled, flow control needs to
4475 * be configured according to it
4477 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4478 case I40E_LINK_PAUSE_RXTX:
4481 hw->fc.current_mode = I40E_FC_FULL;
4483 case I40E_AQ_LINK_PAUSE_RX:
4485 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4487 case I40E_AQ_LINK_PAUSE_TX:
4489 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4492 hw->fc.current_mode = I40E_FC_NONE;
4497 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4498 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4499 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4500 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4501 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4502 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4509 i40e_pf_setup(struct i40e_pf *pf)
4511 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4512 struct i40e_filter_control_settings settings;
4513 struct i40e_vsi *vsi;
4516 /* Clear all stats counters */
4517 pf->offset_loaded = FALSE;
4518 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4519 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4521 ret = i40e_pf_get_switch_config(pf);
4522 if (ret != I40E_SUCCESS) {
4523 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4526 if (pf->flags & I40E_FLAG_FDIR) {
4527 /* make queue allocated first, let FDIR use queue pair 0*/
4528 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4529 if (ret != I40E_FDIR_QUEUE_ID) {
4530 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4532 pf->flags &= ~I40E_FLAG_FDIR;
4535 /* main VSI setup */
4536 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4538 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4539 return I40E_ERR_NOT_READY;
4543 /* Configure filter control */
4544 memset(&settings, 0, sizeof(settings));
4545 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4546 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4547 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4548 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4550 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4551 hw->func_caps.rss_table_size);
4552 return I40E_ERR_PARAM;
4554 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4555 "size: %u\n", hw->func_caps.rss_table_size);
4556 pf->hash_lut_size = hw->func_caps.rss_table_size;
4558 /* Enable ethtype and macvlan filters */
4559 settings.enable_ethtype = TRUE;
4560 settings.enable_macvlan = TRUE;
4561 ret = i40e_set_filter_control(hw, &settings);
4563 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4566 /* Update flow control according to the auto negotiation */
4567 i40e_update_flow_control(hw);
4569 return I40E_SUCCESS;
4573 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4579 * Set or clear TX Queue Disable flags,
4580 * which is required by hardware.
4582 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4583 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4585 /* Wait until the request is finished */
4586 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4587 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4588 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4589 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4590 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4596 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4597 return I40E_SUCCESS; /* already on, skip next steps */
4599 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4600 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4602 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4603 return I40E_SUCCESS; /* already off, skip next steps */
4604 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4606 /* Write the register */
4607 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4608 /* Check the result */
4609 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4610 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4611 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4613 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4614 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4617 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4618 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4622 /* Check if it is timeout */
4623 if (j >= I40E_CHK_Q_ENA_COUNT) {
4624 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4625 (on ? "enable" : "disable"), q_idx);
4626 return I40E_ERR_TIMEOUT;
4629 return I40E_SUCCESS;
4632 /* Swith on or off the tx queues */
4634 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4636 struct rte_eth_dev_data *dev_data = pf->dev_data;
4637 struct i40e_tx_queue *txq;
4638 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4642 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4643 txq = dev_data->tx_queues[i];
4644 /* Don't operate the queue if not configured or
4645 * if starting only per queue */
4646 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4649 ret = i40e_dev_tx_queue_start(dev, i);
4651 ret = i40e_dev_tx_queue_stop(dev, i);
4652 if ( ret != I40E_SUCCESS)
4656 return I40E_SUCCESS;
4660 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4665 /* Wait until the request is finished */
4666 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4667 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4668 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4669 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4670 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4675 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4676 return I40E_SUCCESS; /* Already on, skip next steps */
4677 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4679 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4680 return I40E_SUCCESS; /* Already off, skip next steps */
4681 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4684 /* Write the register */
4685 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4686 /* Check the result */
4687 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4688 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4689 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4691 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4692 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4695 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4696 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4701 /* Check if it is timeout */
4702 if (j >= I40E_CHK_Q_ENA_COUNT) {
4703 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4704 (on ? "enable" : "disable"), q_idx);
4705 return I40E_ERR_TIMEOUT;
4708 return I40E_SUCCESS;
4710 /* Switch on or off the rx queues */
4712 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4714 struct rte_eth_dev_data *dev_data = pf->dev_data;
4715 struct i40e_rx_queue *rxq;
4716 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4720 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4721 rxq = dev_data->rx_queues[i];
4722 /* Don't operate the queue if not configured or
4723 * if starting only per queue */
4724 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4727 ret = i40e_dev_rx_queue_start(dev, i);
4729 ret = i40e_dev_rx_queue_stop(dev, i);
4730 if (ret != I40E_SUCCESS)
4734 return I40E_SUCCESS;
4737 /* Switch on or off all the rx/tx queues */
4739 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4744 /* enable rx queues before enabling tx queues */
4745 ret = i40e_dev_switch_rx_queues(pf, on);
4747 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4750 ret = i40e_dev_switch_tx_queues(pf, on);
4752 /* Stop tx queues before stopping rx queues */
4753 ret = i40e_dev_switch_tx_queues(pf, on);
4755 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4758 ret = i40e_dev_switch_rx_queues(pf, on);
4764 /* Initialize VSI for TX */
4766 i40e_dev_tx_init(struct i40e_pf *pf)
4768 struct rte_eth_dev_data *data = pf->dev_data;
4770 uint32_t ret = I40E_SUCCESS;
4771 struct i40e_tx_queue *txq;
4773 for (i = 0; i < data->nb_tx_queues; i++) {
4774 txq = data->tx_queues[i];
4775 if (!txq || !txq->q_set)
4777 ret = i40e_tx_queue_init(txq);
4778 if (ret != I40E_SUCCESS)
4781 if (ret == I40E_SUCCESS)
4782 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4788 /* Initialize VSI for RX */
4790 i40e_dev_rx_init(struct i40e_pf *pf)
4792 struct rte_eth_dev_data *data = pf->dev_data;
4793 int ret = I40E_SUCCESS;
4795 struct i40e_rx_queue *rxq;
4797 i40e_pf_config_mq_rx(pf);
4798 for (i = 0; i < data->nb_rx_queues; i++) {
4799 rxq = data->rx_queues[i];
4800 if (!rxq || !rxq->q_set)
4803 ret = i40e_rx_queue_init(rxq);
4804 if (ret != I40E_SUCCESS) {
4805 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4810 if (ret == I40E_SUCCESS)
4811 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4818 i40e_dev_rxtx_init(struct i40e_pf *pf)
4822 err = i40e_dev_tx_init(pf);
4824 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4827 err = i40e_dev_rx_init(pf);
4829 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4837 i40e_vmdq_setup(struct rte_eth_dev *dev)
4839 struct rte_eth_conf *conf = &dev->data->dev_conf;
4840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4841 int i, err, conf_vsis, j, loop;
4842 struct i40e_vsi *vsi;
4843 struct i40e_vmdq_info *vmdq_info;
4844 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4845 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4848 * Disable interrupt to avoid message from VF. Furthermore, it will
4849 * avoid race condition in VSI creation/destroy.
4851 i40e_pf_disable_irq0(hw);
4853 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4854 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4858 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4859 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4860 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4861 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4862 pf->max_nb_vmdq_vsi);
4866 if (pf->vmdq != NULL) {
4867 PMD_INIT_LOG(INFO, "VMDQ already configured");
4871 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4872 sizeof(*vmdq_info) * conf_vsis, 0);
4874 if (pf->vmdq == NULL) {
4875 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4879 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4881 /* Create VMDQ VSI */
4882 for (i = 0; i < conf_vsis; i++) {
4883 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4884 vmdq_conf->enable_loop_back);
4886 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4890 vmdq_info = &pf->vmdq[i];
4892 vmdq_info->vsi = vsi;
4894 pf->nb_cfg_vmdq_vsi = conf_vsis;
4896 /* Configure Vlan */
4897 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4898 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4899 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4900 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4901 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4902 vmdq_conf->pool_map[i].vlan_id, j);
4904 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4905 vmdq_conf->pool_map[i].vlan_id);
4907 PMD_INIT_LOG(ERR, "Failed to add vlan");
4915 i40e_pf_enable_irq0(hw);
4920 for (i = 0; i < conf_vsis; i++)
4921 if (pf->vmdq[i].vsi == NULL)
4924 i40e_vsi_release(pf->vmdq[i].vsi);
4928 i40e_pf_enable_irq0(hw);
4933 i40e_stat_update_32(struct i40e_hw *hw,
4941 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4945 if (new_data >= *offset)
4946 *stat = (uint64_t)(new_data - *offset);
4948 *stat = (uint64_t)((new_data +
4949 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4953 i40e_stat_update_48(struct i40e_hw *hw,
4962 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4963 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4964 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4969 if (new_data >= *offset)
4970 *stat = new_data - *offset;
4972 *stat = (uint64_t)((new_data +
4973 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4975 *stat &= I40E_48_BIT_MASK;
4980 i40e_pf_disable_irq0(struct i40e_hw *hw)
4982 /* Disable all interrupt types */
4983 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4984 I40E_WRITE_FLUSH(hw);
4989 i40e_pf_enable_irq0(struct i40e_hw *hw)
4991 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4992 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4993 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4994 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4995 I40E_WRITE_FLUSH(hw);
4999 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5001 /* read pending request and disable first */
5002 i40e_pf_disable_irq0(hw);
5003 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5004 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5005 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5008 /* Link no queues with irq0 */
5009 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5010 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5014 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5016 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5017 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5020 uint32_t index, offset, val;
5025 * Try to find which VF trigger a reset, use absolute VF id to access
5026 * since the reg is global register.
5028 for (i = 0; i < pf->vf_num; i++) {
5029 abs_vf_id = hw->func_caps.vf_base_id + i;
5030 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5031 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5032 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5033 /* VFR event occured */
5034 if (val & (0x1 << offset)) {
5037 /* Clear the event first */
5038 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5040 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5042 * Only notify a VF reset event occured,
5043 * don't trigger another SW reset
5045 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5046 if (ret != I40E_SUCCESS)
5047 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5053 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5055 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5056 struct i40e_arq_event_info info;
5057 uint16_t pending, opcode;
5060 info.buf_len = I40E_AQ_BUF_SZ;
5061 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5062 if (!info.msg_buf) {
5063 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5069 ret = i40e_clean_arq_element(hw, &info, &pending);
5071 if (ret != I40E_SUCCESS) {
5072 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5073 "aq_err: %u", hw->aq.asq_last_status);
5076 opcode = rte_le_to_cpu_16(info.desc.opcode);
5079 case i40e_aqc_opc_send_msg_to_pf:
5080 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5081 i40e_pf_host_handle_vf_msg(dev,
5082 rte_le_to_cpu_16(info.desc.retval),
5083 rte_le_to_cpu_32(info.desc.cookie_high),
5084 rte_le_to_cpu_32(info.desc.cookie_low),
5089 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5094 rte_free(info.msg_buf);
5098 * Interrupt handler is registered as the alarm callback for handling LSC
5099 * interrupt in a definite of time, in order to wait the NIC into a stable
5100 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5101 * no need for link down interrupt.
5104 i40e_dev_interrupt_delayed_handler(void *param)
5106 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5107 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5110 /* read interrupt causes again */
5111 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5113 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5114 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5115 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5116 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5117 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5118 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5119 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5120 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5121 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5122 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5123 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5125 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5126 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5127 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5128 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5129 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5131 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5132 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5133 i40e_dev_handle_vfr_event(dev);
5135 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5136 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5137 i40e_dev_handle_aq_msg(dev);
5140 /* handle the link up interrupt in an alarm callback */
5141 i40e_dev_link_update(dev, 0);
5142 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5144 i40e_pf_enable_irq0(hw);
5145 rte_intr_enable(&(dev->pci_dev->intr_handle));
5149 * Interrupt handler triggered by NIC for handling
5150 * specific interrupt.
5153 * Pointer to interrupt handle.
5155 * The address of parameter (struct rte_eth_dev *) regsitered before.
5161 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5164 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5165 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5168 /* Disable interrupt */
5169 i40e_pf_disable_irq0(hw);
5171 /* read out interrupt causes */
5172 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5174 /* No interrupt event indicated */
5175 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5176 PMD_DRV_LOG(INFO, "No interrupt event");
5179 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5180 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5181 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5182 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5183 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5184 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5185 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5186 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5187 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5188 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5189 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5190 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5191 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5192 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5193 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5194 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5196 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5197 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5198 i40e_dev_handle_vfr_event(dev);
5200 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5201 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5202 i40e_dev_handle_aq_msg(dev);
5205 /* Link Status Change interrupt */
5206 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5207 #define I40E_US_PER_SECOND 1000000
5208 struct rte_eth_link link;
5210 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5211 memset(&link, 0, sizeof(link));
5212 rte_i40e_dev_atomic_read_link_status(dev, &link);
5213 i40e_dev_link_update(dev, 0);
5216 * For link up interrupt, it needs to wait 1 second to let the
5217 * hardware be a stable state. Otherwise several consecutive
5218 * interrupts can be observed.
5219 * For link down interrupt, no need to wait.
5221 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5222 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5225 _rte_eth_dev_callback_process(dev,
5226 RTE_ETH_EVENT_INTR_LSC);
5230 /* Enable interrupt */
5231 i40e_pf_enable_irq0(hw);
5232 rte_intr_enable(&(dev->pci_dev->intr_handle));
5236 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5237 struct i40e_macvlan_filter *filter,
5240 int ele_num, ele_buff_size;
5241 int num, actual_num, i;
5243 int ret = I40E_SUCCESS;
5244 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5245 struct i40e_aqc_add_macvlan_element_data *req_list;
5247 if (filter == NULL || total == 0)
5248 return I40E_ERR_PARAM;
5249 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5250 ele_buff_size = hw->aq.asq_buf_size;
5252 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5253 if (req_list == NULL) {
5254 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5255 return I40E_ERR_NO_MEMORY;
5260 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5261 memset(req_list, 0, ele_buff_size);
5263 for (i = 0; i < actual_num; i++) {
5264 (void)rte_memcpy(req_list[i].mac_addr,
5265 &filter[num + i].macaddr, ETH_ADDR_LEN);
5266 req_list[i].vlan_tag =
5267 rte_cpu_to_le_16(filter[num + i].vlan_id);
5269 switch (filter[num + i].filter_type) {
5270 case RTE_MAC_PERFECT_MATCH:
5271 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5272 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5274 case RTE_MACVLAN_PERFECT_MATCH:
5275 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5277 case RTE_MAC_HASH_MATCH:
5278 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5279 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5281 case RTE_MACVLAN_HASH_MATCH:
5282 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5285 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5286 ret = I40E_ERR_PARAM;
5290 req_list[i].queue_number = 0;
5292 req_list[i].flags = rte_cpu_to_le_16(flags);
5295 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5297 if (ret != I40E_SUCCESS) {
5298 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5302 } while (num < total);
5310 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5311 struct i40e_macvlan_filter *filter,
5314 int ele_num, ele_buff_size;
5315 int num, actual_num, i;
5317 int ret = I40E_SUCCESS;
5318 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5319 struct i40e_aqc_remove_macvlan_element_data *req_list;
5321 if (filter == NULL || total == 0)
5322 return I40E_ERR_PARAM;
5324 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5325 ele_buff_size = hw->aq.asq_buf_size;
5327 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5328 if (req_list == NULL) {
5329 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5330 return I40E_ERR_NO_MEMORY;
5335 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5336 memset(req_list, 0, ele_buff_size);
5338 for (i = 0; i < actual_num; i++) {
5339 (void)rte_memcpy(req_list[i].mac_addr,
5340 &filter[num + i].macaddr, ETH_ADDR_LEN);
5341 req_list[i].vlan_tag =
5342 rte_cpu_to_le_16(filter[num + i].vlan_id);
5344 switch (filter[num + i].filter_type) {
5345 case RTE_MAC_PERFECT_MATCH:
5346 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5347 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5349 case RTE_MACVLAN_PERFECT_MATCH:
5350 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5352 case RTE_MAC_HASH_MATCH:
5353 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5354 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5356 case RTE_MACVLAN_HASH_MATCH:
5357 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5360 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5361 ret = I40E_ERR_PARAM;
5364 req_list[i].flags = rte_cpu_to_le_16(flags);
5367 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5369 if (ret != I40E_SUCCESS) {
5370 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5374 } while (num < total);
5381 /* Find out specific MAC filter */
5382 static struct i40e_mac_filter *
5383 i40e_find_mac_filter(struct i40e_vsi *vsi,
5384 struct ether_addr *macaddr)
5386 struct i40e_mac_filter *f;
5388 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5389 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5397 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5400 uint32_t vid_idx, vid_bit;
5402 if (vlan_id > ETH_VLAN_ID_MAX)
5405 vid_idx = I40E_VFTA_IDX(vlan_id);
5406 vid_bit = I40E_VFTA_BIT(vlan_id);
5408 if (vsi->vfta[vid_idx] & vid_bit)
5415 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5416 uint16_t vlan_id, bool on)
5418 uint32_t vid_idx, vid_bit;
5420 if (vlan_id > ETH_VLAN_ID_MAX)
5423 vid_idx = I40E_VFTA_IDX(vlan_id);
5424 vid_bit = I40E_VFTA_BIT(vlan_id);
5427 vsi->vfta[vid_idx] |= vid_bit;
5429 vsi->vfta[vid_idx] &= ~vid_bit;
5433 * Find all vlan options for specific mac addr,
5434 * return with actual vlan found.
5437 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5438 struct i40e_macvlan_filter *mv_f,
5439 int num, struct ether_addr *addr)
5445 * Not to use i40e_find_vlan_filter to decrease the loop time,
5446 * although the code looks complex.
5448 if (num < vsi->vlan_num)
5449 return I40E_ERR_PARAM;
5452 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5454 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5455 if (vsi->vfta[j] & (1 << k)) {
5457 PMD_DRV_LOG(ERR, "vlan number "
5459 return I40E_ERR_PARAM;
5461 (void)rte_memcpy(&mv_f[i].macaddr,
5462 addr, ETH_ADDR_LEN);
5464 j * I40E_UINT32_BIT_SIZE + k;
5470 return I40E_SUCCESS;
5474 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5475 struct i40e_macvlan_filter *mv_f,
5480 struct i40e_mac_filter *f;
5482 if (num < vsi->mac_num)
5483 return I40E_ERR_PARAM;
5485 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5487 PMD_DRV_LOG(ERR, "buffer number not match");
5488 return I40E_ERR_PARAM;
5490 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5492 mv_f[i].vlan_id = vlan;
5493 mv_f[i].filter_type = f->mac_info.filter_type;
5497 return I40E_SUCCESS;
5501 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5504 struct i40e_mac_filter *f;
5505 struct i40e_macvlan_filter *mv_f;
5506 int ret = I40E_SUCCESS;
5508 if (vsi == NULL || vsi->mac_num == 0)
5509 return I40E_ERR_PARAM;
5511 /* Case that no vlan is set */
5512 if (vsi->vlan_num == 0)
5515 num = vsi->mac_num * vsi->vlan_num;
5517 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5519 PMD_DRV_LOG(ERR, "failed to allocate memory");
5520 return I40E_ERR_NO_MEMORY;
5524 if (vsi->vlan_num == 0) {
5525 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5526 (void)rte_memcpy(&mv_f[i].macaddr,
5527 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5528 mv_f[i].vlan_id = 0;
5532 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5533 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5534 vsi->vlan_num, &f->mac_info.mac_addr);
5535 if (ret != I40E_SUCCESS)
5541 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5549 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5551 struct i40e_macvlan_filter *mv_f;
5553 int ret = I40E_SUCCESS;
5555 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5556 return I40E_ERR_PARAM;
5558 /* If it's already set, just return */
5559 if (i40e_find_vlan_filter(vsi,vlan))
5560 return I40E_SUCCESS;
5562 mac_num = vsi->mac_num;
5565 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5566 return I40E_ERR_PARAM;
5569 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5572 PMD_DRV_LOG(ERR, "failed to allocate memory");
5573 return I40E_ERR_NO_MEMORY;
5576 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5578 if (ret != I40E_SUCCESS)
5581 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5583 if (ret != I40E_SUCCESS)
5586 i40e_set_vlan_filter(vsi, vlan, 1);
5596 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5598 struct i40e_macvlan_filter *mv_f;
5600 int ret = I40E_SUCCESS;
5603 * Vlan 0 is the generic filter for untagged packets
5604 * and can't be removed.
5606 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5607 return I40E_ERR_PARAM;
5609 /* If can't find it, just return */
5610 if (!i40e_find_vlan_filter(vsi, vlan))
5611 return I40E_ERR_PARAM;
5613 mac_num = vsi->mac_num;
5616 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5617 return I40E_ERR_PARAM;
5620 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5623 PMD_DRV_LOG(ERR, "failed to allocate memory");
5624 return I40E_ERR_NO_MEMORY;
5627 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5629 if (ret != I40E_SUCCESS)
5632 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5634 if (ret != I40E_SUCCESS)
5637 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5638 if (vsi->vlan_num == 1) {
5639 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5640 if (ret != I40E_SUCCESS)
5643 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5644 if (ret != I40E_SUCCESS)
5648 i40e_set_vlan_filter(vsi, vlan, 0);
5658 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5660 struct i40e_mac_filter *f;
5661 struct i40e_macvlan_filter *mv_f;
5662 int i, vlan_num = 0;
5663 int ret = I40E_SUCCESS;
5665 /* If it's add and we've config it, return */
5666 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5668 return I40E_SUCCESS;
5669 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5670 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5673 * If vlan_num is 0, that's the first time to add mac,
5674 * set mask for vlan_id 0.
5676 if (vsi->vlan_num == 0) {
5677 i40e_set_vlan_filter(vsi, 0, 1);
5680 vlan_num = vsi->vlan_num;
5681 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5682 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5685 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5687 PMD_DRV_LOG(ERR, "failed to allocate memory");
5688 return I40E_ERR_NO_MEMORY;
5691 for (i = 0; i < vlan_num; i++) {
5692 mv_f[i].filter_type = mac_filter->filter_type;
5693 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5697 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5698 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5699 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5700 &mac_filter->mac_addr);
5701 if (ret != I40E_SUCCESS)
5705 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5706 if (ret != I40E_SUCCESS)
5709 /* Add the mac addr into mac list */
5710 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5712 PMD_DRV_LOG(ERR, "failed to allocate memory");
5713 ret = I40E_ERR_NO_MEMORY;
5716 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5718 f->mac_info.filter_type = mac_filter->filter_type;
5719 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5730 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5732 struct i40e_mac_filter *f;
5733 struct i40e_macvlan_filter *mv_f;
5735 enum rte_mac_filter_type filter_type;
5736 int ret = I40E_SUCCESS;
5738 /* Can't find it, return an error */
5739 f = i40e_find_mac_filter(vsi, addr);
5741 return I40E_ERR_PARAM;
5743 vlan_num = vsi->vlan_num;
5744 filter_type = f->mac_info.filter_type;
5745 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5746 filter_type == RTE_MACVLAN_HASH_MATCH) {
5747 if (vlan_num == 0) {
5748 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5749 return I40E_ERR_PARAM;
5751 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5752 filter_type == RTE_MAC_HASH_MATCH)
5755 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5757 PMD_DRV_LOG(ERR, "failed to allocate memory");
5758 return I40E_ERR_NO_MEMORY;
5761 for (i = 0; i < vlan_num; i++) {
5762 mv_f[i].filter_type = filter_type;
5763 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5766 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5767 filter_type == RTE_MACVLAN_HASH_MATCH) {
5768 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5769 if (ret != I40E_SUCCESS)
5773 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5774 if (ret != I40E_SUCCESS)
5777 /* Remove the mac addr into mac list */
5778 TAILQ_REMOVE(&vsi->mac_list, f, next);
5788 /* Configure hash enable flags for RSS */
5790 i40e_config_hena(uint64_t flags)
5797 if (flags & ETH_RSS_FRAG_IPV4)
5798 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5799 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5800 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5801 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5802 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5803 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5804 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5805 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5806 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5807 if (flags & ETH_RSS_FRAG_IPV6)
5808 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5809 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5810 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5811 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5812 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5813 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5814 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5815 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5816 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5817 if (flags & ETH_RSS_L2_PAYLOAD)
5818 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5823 /* Parse the hash enable flags */
5825 i40e_parse_hena(uint64_t flags)
5827 uint64_t rss_hf = 0;
5831 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5832 rss_hf |= ETH_RSS_FRAG_IPV4;
5833 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5834 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5835 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5836 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5837 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5838 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5839 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5840 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5841 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5842 rss_hf |= ETH_RSS_FRAG_IPV6;
5843 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5844 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5845 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5846 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5847 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5848 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5849 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5850 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5851 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5852 rss_hf |= ETH_RSS_L2_PAYLOAD;
5859 i40e_pf_disable_rss(struct i40e_pf *pf)
5861 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5864 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5865 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5866 hena &= ~I40E_RSS_HENA_ALL;
5867 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5868 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5869 I40E_WRITE_FLUSH(hw);
5873 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5875 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5876 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5879 if (!key || key_len == 0) {
5880 PMD_DRV_LOG(DEBUG, "No key to be configured");
5882 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5884 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5888 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5889 struct i40e_aqc_get_set_rss_key_data *key_dw =
5890 (struct i40e_aqc_get_set_rss_key_data *)key;
5892 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5894 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5897 uint32_t *hash_key = (uint32_t *)key;
5900 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5901 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5902 I40E_WRITE_FLUSH(hw);
5909 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5911 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5912 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5915 if (!key || !key_len)
5918 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5919 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5920 (struct i40e_aqc_get_set_rss_key_data *)key);
5922 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5926 uint32_t *key_dw = (uint32_t *)key;
5929 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5930 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5932 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5938 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5940 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5945 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5946 rss_conf->rss_key_len);
5950 rss_hf = rss_conf->rss_hf;
5951 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5952 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5953 hena &= ~I40E_RSS_HENA_ALL;
5954 hena |= i40e_config_hena(rss_hf);
5955 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5956 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5957 I40E_WRITE_FLUSH(hw);
5963 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5964 struct rte_eth_rss_conf *rss_conf)
5966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5967 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5968 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5971 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5972 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5973 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5974 if (rss_hf != 0) /* Enable RSS */
5976 return 0; /* Nothing to do */
5979 if (rss_hf == 0) /* Disable RSS */
5982 return i40e_hw_rss_hash_set(pf, rss_conf);
5986 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5987 struct rte_eth_rss_conf *rss_conf)
5989 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5990 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5993 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5994 &rss_conf->rss_key_len);
5996 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5997 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5998 rss_conf->rss_hf = i40e_parse_hena(hena);
6004 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6006 switch (filter_type) {
6007 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6008 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6010 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6011 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6013 case RTE_TUNNEL_FILTER_IMAC_TENID:
6014 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6016 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6017 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6019 case ETH_TUNNEL_FILTER_IMAC:
6020 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6022 case ETH_TUNNEL_FILTER_OIP:
6023 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6025 case ETH_TUNNEL_FILTER_IIP:
6026 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6029 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6037 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6038 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6043 uint8_t i, tun_type = 0;
6044 /* internal varialbe to convert ipv6 byte order */
6045 uint32_t convert_ipv6[4];
6047 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6048 struct i40e_vsi *vsi = pf->main_vsi;
6049 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6050 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6052 cld_filter = rte_zmalloc("tunnel_filter",
6053 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6056 if (NULL == cld_filter) {
6057 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6060 pfilter = cld_filter;
6062 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6063 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6065 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6066 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6067 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6068 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6069 rte_memcpy(&pfilter->ipaddr.v4.data,
6070 &rte_cpu_to_le_32(ipv4_addr),
6071 sizeof(pfilter->ipaddr.v4.data));
6073 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6074 for (i = 0; i < 4; i++) {
6076 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6078 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6079 sizeof(pfilter->ipaddr.v6.data));
6082 /* check tunneled type */
6083 switch (tunnel_filter->tunnel_type) {
6084 case RTE_TUNNEL_TYPE_VXLAN:
6085 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6087 case RTE_TUNNEL_TYPE_NVGRE:
6088 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6090 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6091 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6094 /* Other tunnel types is not supported. */
6095 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6096 rte_free(cld_filter);
6100 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6103 rte_free(cld_filter);
6107 pfilter->flags |= rte_cpu_to_le_16(
6108 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6109 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6110 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6111 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6114 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6116 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6119 rte_free(cld_filter);
6124 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6128 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6129 if (pf->vxlan_ports[i] == port)
6137 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6141 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6143 idx = i40e_get_vxlan_port_idx(pf, port);
6145 /* Check if port already exists */
6147 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6151 /* Now check if there is space to add the new port */
6152 idx = i40e_get_vxlan_port_idx(pf, 0);
6154 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6155 "not adding port %d", port);
6159 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6162 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6166 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6169 /* New port: add it and mark its index in the bitmap */
6170 pf->vxlan_ports[idx] = port;
6171 pf->vxlan_bitmap |= (1 << idx);
6173 if (!(pf->flags & I40E_FLAG_VXLAN))
6174 pf->flags |= I40E_FLAG_VXLAN;
6180 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6183 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6185 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6186 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6190 idx = i40e_get_vxlan_port_idx(pf, port);
6193 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6197 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6198 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6202 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6205 pf->vxlan_ports[idx] = 0;
6206 pf->vxlan_bitmap &= ~(1 << idx);
6208 if (!pf->vxlan_bitmap)
6209 pf->flags &= ~I40E_FLAG_VXLAN;
6214 /* Add UDP tunneling port */
6216 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6217 struct rte_eth_udp_tunnel *udp_tunnel)
6220 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6222 if (udp_tunnel == NULL)
6225 switch (udp_tunnel->prot_type) {
6226 case RTE_TUNNEL_TYPE_VXLAN:
6227 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6230 case RTE_TUNNEL_TYPE_GENEVE:
6231 case RTE_TUNNEL_TYPE_TEREDO:
6232 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6237 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6245 /* Remove UDP tunneling port */
6247 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6248 struct rte_eth_udp_tunnel *udp_tunnel)
6251 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6253 if (udp_tunnel == NULL)
6256 switch (udp_tunnel->prot_type) {
6257 case RTE_TUNNEL_TYPE_VXLAN:
6258 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6260 case RTE_TUNNEL_TYPE_GENEVE:
6261 case RTE_TUNNEL_TYPE_TEREDO:
6262 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6266 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6274 /* Calculate the maximum number of contiguous PF queues that are configured */
6276 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6278 struct rte_eth_dev_data *data = pf->dev_data;
6280 struct i40e_rx_queue *rxq;
6283 for (i = 0; i < pf->lan_nb_qps; i++) {
6284 rxq = data->rx_queues[i];
6285 if (rxq && rxq->q_set)
6296 i40e_pf_config_rss(struct i40e_pf *pf)
6298 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6299 struct rte_eth_rss_conf rss_conf;
6300 uint32_t i, lut = 0;
6304 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6305 * It's necessary to calulate the actual PF queues that are configured.
6307 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6308 num = i40e_pf_calc_configured_queues_num(pf);
6310 num = pf->dev_data->nb_rx_queues;
6312 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6313 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6317 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6321 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6324 lut = (lut << 8) | (j & ((0x1 <<
6325 hw->func_caps.rss_table_entry_width) - 1));
6327 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6330 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6331 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6332 i40e_pf_disable_rss(pf);
6335 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6336 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6337 /* Random default keys */
6338 static uint32_t rss_key_default[] = {0x6b793944,
6339 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6340 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6341 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6343 rss_conf.rss_key = (uint8_t *)rss_key_default;
6344 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6348 return i40e_hw_rss_hash_set(pf, &rss_conf);
6352 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6353 struct rte_eth_tunnel_filter_conf *filter)
6355 if (pf == NULL || filter == NULL) {
6356 PMD_DRV_LOG(ERR, "Invalid parameter");
6360 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6361 PMD_DRV_LOG(ERR, "Invalid queue ID");
6365 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6366 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6370 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6371 (is_zero_ether_addr(&filter->outer_mac))) {
6372 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6376 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6377 (is_zero_ether_addr(&filter->inner_mac))) {
6378 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6385 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6386 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6388 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6393 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6394 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6397 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6398 } else if (len == 4) {
6399 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6401 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6406 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6413 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6414 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6420 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6427 switch (cfg->cfg_type) {
6428 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6429 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6432 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6440 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6441 enum rte_filter_op filter_op,
6444 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6445 int ret = I40E_ERR_PARAM;
6447 switch (filter_op) {
6448 case RTE_ETH_FILTER_SET:
6449 ret = i40e_dev_global_config_set(hw,
6450 (struct rte_eth_global_cfg *)arg);
6453 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6461 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6462 enum rte_filter_op filter_op,
6465 struct rte_eth_tunnel_filter_conf *filter;
6466 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6467 int ret = I40E_SUCCESS;
6469 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6471 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6472 return I40E_ERR_PARAM;
6474 switch (filter_op) {
6475 case RTE_ETH_FILTER_NOP:
6476 if (!(pf->flags & I40E_FLAG_VXLAN))
6477 ret = I40E_NOT_SUPPORTED;
6479 case RTE_ETH_FILTER_ADD:
6480 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6482 case RTE_ETH_FILTER_DELETE:
6483 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6486 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6487 ret = I40E_ERR_PARAM;
6495 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6498 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6501 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6502 ret = i40e_pf_config_rss(pf);
6504 i40e_pf_disable_rss(pf);
6509 /* Get the symmetric hash enable configurations per port */
6511 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6513 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6515 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6518 /* Set the symmetric hash enable configurations per port */
6520 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6522 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6525 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6526 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6530 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6532 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6533 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6537 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6539 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6540 I40E_WRITE_FLUSH(hw);
6544 * Get global configurations of hash function type and symmetric hash enable
6545 * per flow type (pctype). Note that global configuration means it affects all
6546 * the ports on the same NIC.
6549 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6550 struct rte_eth_hash_global_conf *g_cfg)
6552 uint32_t reg, mask = I40E_FLOW_TYPES;
6554 enum i40e_filter_pctype pctype;
6556 memset(g_cfg, 0, sizeof(*g_cfg));
6557 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6558 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6559 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6561 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6562 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6563 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6565 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6566 if (!(mask & (1UL << i)))
6568 mask &= ~(1UL << i);
6569 /* Bit set indicats the coresponding flow type is supported */
6570 g_cfg->valid_bit_mask[0] |= (1UL << i);
6571 pctype = i40e_flowtype_to_pctype(i);
6572 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6573 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6574 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6581 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6584 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6586 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6587 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6588 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6589 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6595 * As i40e supports less than 32 flow types, only first 32 bits need to
6598 mask0 = g_cfg->valid_bit_mask[0];
6599 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6601 /* Check if any unsupported flow type configured */
6602 if ((mask0 | i40e_mask) ^ i40e_mask)
6605 if (g_cfg->valid_bit_mask[i])
6613 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6619 * Set global configurations of hash function type and symmetric hash enable
6620 * per flow type (pctype). Note any modifying global configuration will affect
6621 * all the ports on the same NIC.
6624 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6625 struct rte_eth_hash_global_conf *g_cfg)
6630 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6631 enum i40e_filter_pctype pctype;
6633 /* Check the input parameters */
6634 ret = i40e_hash_global_config_check(g_cfg);
6638 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6639 if (!(mask0 & (1UL << i)))
6641 mask0 &= ~(1UL << i);
6642 pctype = i40e_flowtype_to_pctype(i);
6643 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6644 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6645 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6648 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6649 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6651 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6652 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6656 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6657 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6659 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6660 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6664 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6666 /* Use the default, and keep it as it is */
6669 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6672 I40E_WRITE_FLUSH(hw);
6678 * Valid input sets for hash and flow director filters per PCTYPE
6681 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6682 enum rte_filter_type filter)
6686 static const uint64_t valid_hash_inset_table[] = {
6687 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6688 I40E_INSET_DMAC | I40E_INSET_SMAC |
6689 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6690 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6691 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6692 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6693 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6694 I40E_INSET_FLEX_PAYLOAD,
6695 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6696 I40E_INSET_DMAC | I40E_INSET_SMAC |
6697 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6698 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6699 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6700 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6701 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6702 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6703 I40E_INSET_FLEX_PAYLOAD,
6704 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6705 I40E_INSET_DMAC | I40E_INSET_SMAC |
6706 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6707 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6708 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6709 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6710 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6711 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6712 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6713 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6714 I40E_INSET_DMAC | I40E_INSET_SMAC |
6715 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6716 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6717 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6718 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6719 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6720 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6721 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6722 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6723 I40E_INSET_DMAC | I40E_INSET_SMAC |
6724 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6725 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6726 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6727 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6728 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6729 I40E_INSET_FLEX_PAYLOAD,
6730 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6731 I40E_INSET_DMAC | I40E_INSET_SMAC |
6732 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6733 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6734 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6735 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6736 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6737 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6738 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6739 I40E_INSET_DMAC | I40E_INSET_SMAC |
6740 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6741 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6742 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6743 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6744 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6745 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6746 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6747 I40E_INSET_DMAC | I40E_INSET_SMAC |
6748 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6749 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6750 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6751 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6752 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6753 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6754 I40E_INSET_FLEX_PAYLOAD,
6755 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6756 I40E_INSET_DMAC | I40E_INSET_SMAC |
6757 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6758 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6759 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6760 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6761 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6762 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6763 I40E_INSET_FLEX_PAYLOAD,
6764 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6765 I40E_INSET_DMAC | I40E_INSET_SMAC |
6766 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6767 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6768 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6769 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6770 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6771 I40E_INSET_FLEX_PAYLOAD,
6772 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6773 I40E_INSET_DMAC | I40E_INSET_SMAC |
6774 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6775 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6776 I40E_INSET_FLEX_PAYLOAD,
6780 * Flow director supports only fields defined in
6781 * union rte_eth_fdir_flow.
6783 static const uint64_t valid_fdir_inset_table[] = {
6784 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6785 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6786 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6787 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6788 I40E_INSET_IPV4_TTL,
6789 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6790 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6791 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6792 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6793 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6794 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6795 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6796 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6797 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6798 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6799 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6800 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6801 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6802 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6803 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6805 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6806 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6807 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6808 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6809 I40E_INSET_IPV4_TTL,
6810 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6811 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6812 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6813 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6814 I40E_INSET_IPV6_HOP_LIMIT,
6815 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6816 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6817 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6818 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6819 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6820 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6821 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6822 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6823 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6824 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6825 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6826 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6827 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6828 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6829 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6831 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6832 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6833 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6834 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6835 I40E_INSET_IPV6_HOP_LIMIT,
6836 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6837 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6838 I40E_INSET_LAST_ETHER_TYPE,
6841 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6843 if (filter == RTE_ETH_FILTER_HASH)
6844 valid = valid_hash_inset_table[pctype];
6846 valid = valid_fdir_inset_table[pctype];
6852 * Validate if the input set is allowed for a specific PCTYPE
6855 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6856 enum rte_filter_type filter, uint64_t inset)
6860 valid = i40e_get_valid_input_set(pctype, filter);
6861 if (inset & (~valid))
6867 /* default input set fields combination per pctype */
6869 i40e_get_default_input_set(uint16_t pctype)
6871 static const uint64_t default_inset_table[] = {
6872 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6873 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6874 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6875 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6876 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6877 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6878 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6879 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6880 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6881 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6882 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6884 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6885 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6886 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6887 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6888 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6889 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6890 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6891 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6892 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6893 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6894 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6895 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6896 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6898 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6899 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6900 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6901 I40E_INSET_LAST_ETHER_TYPE,
6904 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6907 return default_inset_table[pctype];
6911 * Parse the input set from index to logical bit masks
6914 i40e_parse_input_set(uint64_t *inset,
6915 enum i40e_filter_pctype pctype,
6916 enum rte_eth_input_set_field *field,
6922 static const struct {
6923 enum rte_eth_input_set_field field;
6925 } inset_convert_table[] = {
6926 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6927 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6928 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6929 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6930 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6931 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6932 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6933 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6934 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6935 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6936 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
6937 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6938 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6939 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6940 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6941 I40E_INSET_IPV6_NEXT_HDR},
6942 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
6943 I40E_INSET_IPV6_HOP_LIMIT},
6944 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6945 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6946 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6947 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6948 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6949 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6950 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6951 I40E_INSET_SCTP_VT},
6952 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6953 I40E_INSET_TUNNEL_DMAC},
6954 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6955 I40E_INSET_VLAN_TUNNEL},
6956 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6957 I40E_INSET_TUNNEL_ID},
6958 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6959 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6960 I40E_INSET_FLEX_PAYLOAD_W1},
6961 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6962 I40E_INSET_FLEX_PAYLOAD_W2},
6963 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6964 I40E_INSET_FLEX_PAYLOAD_W3},
6965 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6966 I40E_INSET_FLEX_PAYLOAD_W4},
6967 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6968 I40E_INSET_FLEX_PAYLOAD_W5},
6969 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6970 I40E_INSET_FLEX_PAYLOAD_W6},
6971 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6972 I40E_INSET_FLEX_PAYLOAD_W7},
6973 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6974 I40E_INSET_FLEX_PAYLOAD_W8},
6977 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6980 /* Only one item allowed for default or all */
6982 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6983 *inset = i40e_get_default_input_set(pctype);
6985 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6986 *inset = I40E_INSET_NONE;
6991 for (i = 0, *inset = 0; i < size; i++) {
6992 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6993 if (field[i] == inset_convert_table[j].field) {
6994 *inset |= inset_convert_table[j].inset;
6999 /* It contains unsupported input set, return immediately */
7000 if (j == RTE_DIM(inset_convert_table))
7008 * Translate the input set from bit masks to register aware bit masks
7012 i40e_translate_input_set_reg(uint64_t input)
7017 static const struct {
7021 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7022 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7023 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7024 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7025 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7026 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7027 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7028 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7029 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7030 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7031 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7032 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7033 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7034 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7035 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7036 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7037 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7038 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7039 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7040 {I40E_INSET_TUNNEL_DMAC,
7041 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7042 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7043 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7044 {I40E_INSET_TUNNEL_SRC_PORT,
7045 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7046 {I40E_INSET_TUNNEL_DST_PORT,
7047 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7048 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7049 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7050 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7051 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7052 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7053 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7054 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7055 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7056 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7062 /* Translate input set to register aware inset */
7063 for (i = 0; i < RTE_DIM(inset_map); i++) {
7064 if (input & inset_map[i].inset)
7065 val |= inset_map[i].inset_reg;
7072 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7075 uint64_t inset_need_mask = inset;
7077 static const struct {
7080 } inset_mask_map[] = {
7081 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7082 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7083 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7084 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7085 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7086 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7087 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7088 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7091 if (!inset || !mask || !nb_elem)
7094 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7095 /* Clear the inset bit, if no MASK is required,
7096 * for example proto + ttl
7098 if ((inset & inset_mask_map[i].inset) ==
7099 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7100 inset_need_mask &= ~inset_mask_map[i].inset;
7101 if (!inset_need_mask)
7104 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7105 if ((inset_need_mask & inset_mask_map[i].inset) ==
7106 inset_mask_map[i].inset) {
7107 if (idx >= nb_elem) {
7108 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7111 mask[idx] = inset_mask_map[i].mask;
7120 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7122 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7124 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7126 i40e_write_rx_ctl(hw, addr, val);
7127 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7128 (uint32_t)i40e_read_rx_ctl(hw, addr));
7132 i40e_filter_input_set_init(struct i40e_pf *pf)
7134 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7135 enum i40e_filter_pctype pctype;
7136 uint64_t input_set, inset_reg;
7137 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7140 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7141 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7142 if (!I40E_VALID_PCTYPE(pctype))
7144 input_set = i40e_get_default_input_set(pctype);
7146 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7147 I40E_INSET_MASK_NUM_REG);
7150 inset_reg = i40e_translate_input_set_reg(input_set);
7152 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7153 (uint32_t)(inset_reg & UINT32_MAX));
7154 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7155 (uint32_t)((inset_reg >>
7156 I40E_32_BIT_WIDTH) & UINT32_MAX));
7157 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7158 (uint32_t)(inset_reg & UINT32_MAX));
7159 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7160 (uint32_t)((inset_reg >>
7161 I40E_32_BIT_WIDTH) & UINT32_MAX));
7163 for (i = 0; i < num; i++) {
7164 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7166 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7169 /*clear unused mask registers of the pctype */
7170 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7171 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7173 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7176 I40E_WRITE_FLUSH(hw);
7178 /* store the default input set */
7179 pf->hash_input_set[pctype] = input_set;
7180 pf->fdir.input_set[pctype] = input_set;
7185 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7186 struct rte_eth_input_set_conf *conf)
7188 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7189 enum i40e_filter_pctype pctype;
7190 uint64_t input_set, inset_reg = 0;
7191 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7195 PMD_DRV_LOG(ERR, "Invalid pointer");
7198 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7199 conf->op != RTE_ETH_INPUT_SET_ADD) {
7200 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7204 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7205 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7206 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7211 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7214 PMD_DRV_LOG(ERR, "Failed to parse input set");
7217 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7219 PMD_DRV_LOG(ERR, "Invalid input set");
7222 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7223 /* get inset value in register */
7224 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7225 inset_reg <<= I40E_32_BIT_WIDTH;
7226 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7227 input_set |= pf->hash_input_set[pctype];
7229 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7230 I40E_INSET_MASK_NUM_REG);
7234 inset_reg |= i40e_translate_input_set_reg(input_set);
7236 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7237 (uint32_t)(inset_reg & UINT32_MAX));
7238 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7239 (uint32_t)((inset_reg >>
7240 I40E_32_BIT_WIDTH) & UINT32_MAX));
7242 for (i = 0; i < num; i++)
7243 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7245 /*clear unused mask registers of the pctype */
7246 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7247 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7249 I40E_WRITE_FLUSH(hw);
7251 pf->hash_input_set[pctype] = input_set;
7256 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7257 struct rte_eth_input_set_conf *conf)
7259 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7260 enum i40e_filter_pctype pctype;
7261 uint64_t input_set, inset_reg = 0;
7262 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7266 PMD_DRV_LOG(ERR, "Invalid pointer");
7269 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7270 conf->op != RTE_ETH_INPUT_SET_ADD) {
7271 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7275 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7276 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7277 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7281 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7284 PMD_DRV_LOG(ERR, "Failed to parse input set");
7287 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7289 PMD_DRV_LOG(ERR, "Invalid input set");
7293 /* get inset value in register */
7294 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7295 inset_reg <<= I40E_32_BIT_WIDTH;
7296 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7298 /* Can not change the inset reg for flex payload for fdir,
7299 * it is done by writing I40E_PRTQF_FD_FLXINSET
7300 * in i40e_set_flex_mask_on_pctype.
7302 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7303 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7305 input_set |= pf->fdir.input_set[pctype];
7306 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7307 I40E_INSET_MASK_NUM_REG);
7311 inset_reg |= i40e_translate_input_set_reg(input_set);
7313 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7314 (uint32_t)(inset_reg & UINT32_MAX));
7315 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7316 (uint32_t)((inset_reg >>
7317 I40E_32_BIT_WIDTH) & UINT32_MAX));
7319 for (i = 0; i < num; i++)
7320 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7322 /*clear unused mask registers of the pctype */
7323 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7324 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7326 I40E_WRITE_FLUSH(hw);
7328 pf->fdir.input_set[pctype] = input_set;
7333 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7338 PMD_DRV_LOG(ERR, "Invalid pointer");
7342 switch (info->info_type) {
7343 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7344 i40e_get_symmetric_hash_enable_per_port(hw,
7345 &(info->info.enable));
7347 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7348 ret = i40e_get_hash_filter_global_config(hw,
7349 &(info->info.global_conf));
7352 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7362 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7367 PMD_DRV_LOG(ERR, "Invalid pointer");
7371 switch (info->info_type) {
7372 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7373 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7375 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7376 ret = i40e_set_hash_filter_global_config(hw,
7377 &(info->info.global_conf));
7379 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7380 ret = i40e_hash_filter_inset_select(hw,
7381 &(info->info.input_set_conf));
7385 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7394 /* Operations for hash function */
7396 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7397 enum rte_filter_op filter_op,
7400 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7403 switch (filter_op) {
7404 case RTE_ETH_FILTER_NOP:
7406 case RTE_ETH_FILTER_GET:
7407 ret = i40e_hash_filter_get(hw,
7408 (struct rte_eth_hash_filter_info *)arg);
7410 case RTE_ETH_FILTER_SET:
7411 ret = i40e_hash_filter_set(hw,
7412 (struct rte_eth_hash_filter_info *)arg);
7415 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7425 * Configure ethertype filter, which can director packet by filtering
7426 * with mac address and ether_type or only ether_type
7429 i40e_ethertype_filter_set(struct i40e_pf *pf,
7430 struct rte_eth_ethertype_filter *filter,
7433 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7434 struct i40e_control_filter_stats stats;
7438 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7439 PMD_DRV_LOG(ERR, "Invalid queue ID");
7442 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7443 filter->ether_type == ETHER_TYPE_IPv6) {
7444 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7445 " control packet filter.", filter->ether_type);
7448 if (filter->ether_type == ETHER_TYPE_VLAN)
7449 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7452 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7453 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7454 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7455 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7456 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7458 memset(&stats, 0, sizeof(stats));
7459 ret = i40e_aq_add_rem_control_packet_filter(hw,
7460 filter->mac_addr.addr_bytes,
7461 filter->ether_type, flags,
7463 filter->queue, add, &stats, NULL);
7465 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7466 " mac_etype_used = %u, etype_used = %u,"
7467 " mac_etype_free = %u, etype_free = %u\n",
7468 ret, stats.mac_etype_used, stats.etype_used,
7469 stats.mac_etype_free, stats.etype_free);
7476 * Handle operations for ethertype filter.
7479 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7480 enum rte_filter_op filter_op,
7483 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7486 if (filter_op == RTE_ETH_FILTER_NOP)
7490 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7495 switch (filter_op) {
7496 case RTE_ETH_FILTER_ADD:
7497 ret = i40e_ethertype_filter_set(pf,
7498 (struct rte_eth_ethertype_filter *)arg,
7501 case RTE_ETH_FILTER_DELETE:
7502 ret = i40e_ethertype_filter_set(pf,
7503 (struct rte_eth_ethertype_filter *)arg,
7507 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7515 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7516 enum rte_filter_type filter_type,
7517 enum rte_filter_op filter_op,
7525 switch (filter_type) {
7526 case RTE_ETH_FILTER_NONE:
7527 /* For global configuration */
7528 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7530 case RTE_ETH_FILTER_HASH:
7531 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7533 case RTE_ETH_FILTER_MACVLAN:
7534 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7536 case RTE_ETH_FILTER_ETHERTYPE:
7537 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7539 case RTE_ETH_FILTER_TUNNEL:
7540 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7542 case RTE_ETH_FILTER_FDIR:
7543 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7546 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7556 * Check and enable Extended Tag.
7557 * Enabling Extended Tag is important for 40G performance.
7560 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7565 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7568 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7572 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7573 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7578 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7581 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7585 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7586 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7589 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7590 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7593 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7600 * As some registers wouldn't be reset unless a global hardware reset,
7601 * hardware initialization is needed to put those registers into an
7602 * expected initial state.
7605 i40e_hw_init(struct rte_eth_dev *dev)
7607 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7609 i40e_enable_extended_tag(dev);
7611 /* clear the PF Queue Filter control register */
7612 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7614 /* Disable symmetric hash per port */
7615 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7618 enum i40e_filter_pctype
7619 i40e_flowtype_to_pctype(uint16_t flow_type)
7621 static const enum i40e_filter_pctype pctype_table[] = {
7622 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7623 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7624 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7625 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7626 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7627 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7628 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7629 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7630 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7631 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7632 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7633 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7634 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7635 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7636 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7637 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7638 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7639 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7640 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7643 return pctype_table[flow_type];
7647 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7649 static const uint16_t flowtype_table[] = {
7650 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7651 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7652 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7653 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7654 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7655 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7656 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7657 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7658 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7659 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7660 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7661 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7662 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7663 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7664 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7665 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7666 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7667 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7668 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7671 return flowtype_table[pctype];
7675 * On X710, performance number is far from the expectation on recent firmware
7676 * versions; on XL710, performance number is also far from the expectation on
7677 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7678 * mode is enabled and port MAC address is equal to the packet destination MAC
7679 * address. The fix for this issue may not be integrated in the following
7680 * firmware version. So the workaround in software driver is needed. It needs
7681 * to modify the initial values of 3 internal only registers for both X710 and
7682 * XL710. Note that the values for X710 or XL710 could be different, and the
7683 * workaround can be removed when it is fixed in firmware in the future.
7686 /* For both X710 and XL710 */
7687 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7688 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7690 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7691 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7694 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7696 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7697 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7700 i40e_configure_registers(struct i40e_hw *hw)
7706 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7707 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7708 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7714 for (i = 0; i < RTE_DIM(reg_table); i++) {
7715 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7716 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7718 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7721 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7724 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7727 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7731 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7732 reg_table[i].addr, reg);
7733 if (reg == reg_table[i].val)
7736 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7737 reg_table[i].val, NULL);
7739 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7740 "address of 0x%"PRIx32, reg_table[i].val,
7744 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7745 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7749 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7750 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7751 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7752 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7754 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7759 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7760 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7764 /* Configure for double VLAN RX stripping */
7765 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7766 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7767 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7768 ret = i40e_aq_debug_write_register(hw,
7769 I40E_VSI_TSR(vsi->vsi_id),
7772 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7774 return I40E_ERR_CONFIG;
7778 /* Configure for double VLAN TX insertion */
7779 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7780 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7781 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7782 ret = i40e_aq_debug_write_register(hw,
7783 I40E_VSI_L2TAGSTXVALID(
7784 vsi->vsi_id), reg, NULL);
7786 PMD_DRV_LOG(ERR, "Failed to update "
7787 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7788 return I40E_ERR_CONFIG;
7796 * i40e_aq_add_mirror_rule
7797 * @hw: pointer to the hardware structure
7798 * @seid: VEB seid to add mirror rule to
7799 * @dst_id: destination vsi seid
7800 * @entries: Buffer which contains the entities to be mirrored
7801 * @count: number of entities contained in the buffer
7802 * @rule_id:the rule_id of the rule to be added
7804 * Add a mirror rule for a given veb.
7807 static enum i40e_status_code
7808 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7809 uint16_t seid, uint16_t dst_id,
7810 uint16_t rule_type, uint16_t *entries,
7811 uint16_t count, uint16_t *rule_id)
7813 struct i40e_aq_desc desc;
7814 struct i40e_aqc_add_delete_mirror_rule cmd;
7815 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7816 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7819 enum i40e_status_code status;
7821 i40e_fill_default_direct_cmd_desc(&desc,
7822 i40e_aqc_opc_add_mirror_rule);
7823 memset(&cmd, 0, sizeof(cmd));
7825 buff_len = sizeof(uint16_t) * count;
7826 desc.datalen = rte_cpu_to_le_16(buff_len);
7828 desc.flags |= rte_cpu_to_le_16(
7829 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7830 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7831 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7832 cmd.num_entries = rte_cpu_to_le_16(count);
7833 cmd.seid = rte_cpu_to_le_16(seid);
7834 cmd.destination = rte_cpu_to_le_16(dst_id);
7836 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7837 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7838 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7840 " mirror_rules_used = %u, mirror_rules_free = %u,",
7841 hw->aq.asq_last_status, resp->rule_id,
7842 resp->mirror_rules_used, resp->mirror_rules_free);
7843 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7849 * i40e_aq_del_mirror_rule
7850 * @hw: pointer to the hardware structure
7851 * @seid: VEB seid to add mirror rule to
7852 * @entries: Buffer which contains the entities to be mirrored
7853 * @count: number of entities contained in the buffer
7854 * @rule_id:the rule_id of the rule to be delete
7856 * Delete a mirror rule for a given veb.
7859 static enum i40e_status_code
7860 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7861 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7862 uint16_t count, uint16_t rule_id)
7864 struct i40e_aq_desc desc;
7865 struct i40e_aqc_add_delete_mirror_rule cmd;
7866 uint16_t buff_len = 0;
7867 enum i40e_status_code status;
7870 i40e_fill_default_direct_cmd_desc(&desc,
7871 i40e_aqc_opc_delete_mirror_rule);
7872 memset(&cmd, 0, sizeof(cmd));
7873 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7874 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7876 cmd.num_entries = count;
7877 buff_len = sizeof(uint16_t) * count;
7878 desc.datalen = rte_cpu_to_le_16(buff_len);
7879 buff = (void *)entries;
7881 /* rule id is filled in destination field for deleting mirror rule */
7882 cmd.destination = rte_cpu_to_le_16(rule_id);
7884 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7885 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7886 cmd.seid = rte_cpu_to_le_16(seid);
7888 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7889 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7895 * i40e_mirror_rule_set
7896 * @dev: pointer to the hardware structure
7897 * @mirror_conf: mirror rule info
7898 * @sw_id: mirror rule's sw_id
7899 * @on: enable/disable
7901 * set a mirror rule.
7905 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7906 struct rte_eth_mirror_conf *mirror_conf,
7907 uint8_t sw_id, uint8_t on)
7909 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7910 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7911 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7912 struct i40e_mirror_rule *parent = NULL;
7913 uint16_t seid, dst_seid, rule_id;
7917 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7919 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7920 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7921 " without veb or vfs.");
7924 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7925 PMD_DRV_LOG(ERR, "mirror table is full.");
7928 if (mirror_conf->dst_pool > pf->vf_num) {
7929 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7930 mirror_conf->dst_pool);
7934 seid = pf->main_vsi->veb->seid;
7936 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7937 if (sw_id <= it->index) {
7943 if (mirr_rule && sw_id == mirr_rule->index) {
7945 PMD_DRV_LOG(ERR, "mirror rule exists.");
7948 ret = i40e_aq_del_mirror_rule(hw, seid,
7949 mirr_rule->rule_type,
7951 mirr_rule->num_entries, mirr_rule->id);
7953 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7954 " ret = %d, aq_err = %d.",
7955 ret, hw->aq.asq_last_status);
7958 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7959 rte_free(mirr_rule);
7960 pf->nb_mirror_rule--;
7964 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7968 mirr_rule = rte_zmalloc("i40e_mirror_rule",
7969 sizeof(struct i40e_mirror_rule) , 0);
7971 PMD_DRV_LOG(ERR, "failed to allocate memory");
7972 return I40E_ERR_NO_MEMORY;
7974 switch (mirror_conf->rule_type) {
7975 case ETH_MIRROR_VLAN:
7976 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7977 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7978 mirr_rule->entries[j] =
7979 mirror_conf->vlan.vlan_id[i];
7984 PMD_DRV_LOG(ERR, "vlan is not specified.");
7985 rte_free(mirr_rule);
7988 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7990 case ETH_MIRROR_VIRTUAL_POOL_UP:
7991 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7992 /* check if the specified pool bit is out of range */
7993 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7994 PMD_DRV_LOG(ERR, "pool mask is out of range.");
7995 rte_free(mirr_rule);
7998 for (i = 0, j = 0; i < pf->vf_num; i++) {
7999 if (mirror_conf->pool_mask & (1ULL << i)) {
8000 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8004 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8005 /* add pf vsi to entries */
8006 mirr_rule->entries[j] = pf->main_vsi_seid;
8010 PMD_DRV_LOG(ERR, "pool is not specified.");
8011 rte_free(mirr_rule);
8014 /* egress and ingress in aq commands means from switch but not port */
8015 mirr_rule->rule_type =
8016 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8017 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8018 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8020 case ETH_MIRROR_UPLINK_PORT:
8021 /* egress and ingress in aq commands means from switch but not port*/
8022 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8024 case ETH_MIRROR_DOWNLINK_PORT:
8025 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8028 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8029 mirror_conf->rule_type);
8030 rte_free(mirr_rule);
8034 /* If the dst_pool is equal to vf_num, consider it as PF */
8035 if (mirror_conf->dst_pool == pf->vf_num)
8036 dst_seid = pf->main_vsi_seid;
8038 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8040 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8041 mirr_rule->rule_type, mirr_rule->entries,
8044 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8045 " ret = %d, aq_err = %d.",
8046 ret, hw->aq.asq_last_status);
8047 rte_free(mirr_rule);
8051 mirr_rule->index = sw_id;
8052 mirr_rule->num_entries = j;
8053 mirr_rule->id = rule_id;
8054 mirr_rule->dst_vsi_seid = dst_seid;
8057 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8059 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8061 pf->nb_mirror_rule++;
8066 * i40e_mirror_rule_reset
8067 * @dev: pointer to the device
8068 * @sw_id: mirror rule's sw_id
8070 * reset a mirror rule.
8074 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8076 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8077 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8078 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8082 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8084 seid = pf->main_vsi->veb->seid;
8086 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8087 if (sw_id == it->index) {
8093 ret = i40e_aq_del_mirror_rule(hw, seid,
8094 mirr_rule->rule_type,
8096 mirr_rule->num_entries, mirr_rule->id);
8098 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8099 " status = %d, aq_err = %d.",
8100 ret, hw->aq.asq_last_status);
8103 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8104 rte_free(mirr_rule);
8105 pf->nb_mirror_rule--;
8107 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8114 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8116 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8117 uint64_t systim_cycles;
8119 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8120 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8123 return systim_cycles;
8127 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8129 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8132 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8133 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8140 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8145 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8146 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8153 i40e_start_timecounters(struct rte_eth_dev *dev)
8155 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8156 struct i40e_adapter *adapter =
8157 (struct i40e_adapter *)dev->data->dev_private;
8158 struct rte_eth_link link;
8159 uint32_t tsync_inc_l;
8160 uint32_t tsync_inc_h;
8162 /* Get current link speed. */
8163 memset(&link, 0, sizeof(link));
8164 i40e_dev_link_update(dev, 1);
8165 rte_i40e_dev_atomic_read_link_status(dev, &link);
8167 switch (link.link_speed) {
8168 case ETH_SPEED_NUM_40G:
8169 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8170 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8172 case ETH_SPEED_NUM_10G:
8173 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8174 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8176 case ETH_SPEED_NUM_1G:
8177 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8178 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8185 /* Set the timesync increment value. */
8186 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8187 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8189 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8190 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8191 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8193 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8194 adapter->systime_tc.cc_shift = 0;
8195 adapter->systime_tc.nsec_mask = 0;
8197 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8198 adapter->rx_tstamp_tc.cc_shift = 0;
8199 adapter->rx_tstamp_tc.nsec_mask = 0;
8201 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8202 adapter->tx_tstamp_tc.cc_shift = 0;
8203 adapter->tx_tstamp_tc.nsec_mask = 0;
8207 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8209 struct i40e_adapter *adapter =
8210 (struct i40e_adapter *)dev->data->dev_private;
8212 adapter->systime_tc.nsec += delta;
8213 adapter->rx_tstamp_tc.nsec += delta;
8214 adapter->tx_tstamp_tc.nsec += delta;
8220 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8223 struct i40e_adapter *adapter =
8224 (struct i40e_adapter *)dev->data->dev_private;
8226 ns = rte_timespec_to_ns(ts);
8228 /* Set the timecounters to a new value. */
8229 adapter->systime_tc.nsec = ns;
8230 adapter->rx_tstamp_tc.nsec = ns;
8231 adapter->tx_tstamp_tc.nsec = ns;
8237 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8239 uint64_t ns, systime_cycles;
8240 struct i40e_adapter *adapter =
8241 (struct i40e_adapter *)dev->data->dev_private;
8243 systime_cycles = i40e_read_systime_cyclecounter(dev);
8244 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8245 *ts = rte_ns_to_timespec(ns);
8251 i40e_timesync_enable(struct rte_eth_dev *dev)
8253 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8254 uint32_t tsync_ctl_l;
8255 uint32_t tsync_ctl_h;
8257 /* Stop the timesync system time. */
8258 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8259 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8260 /* Reset the timesync system time value. */
8261 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8262 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8264 i40e_start_timecounters(dev);
8266 /* Clear timesync registers. */
8267 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8268 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8269 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8270 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8271 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8272 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8274 /* Enable timestamping of PTP packets. */
8275 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8276 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8278 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8279 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8280 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8282 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8283 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8289 i40e_timesync_disable(struct rte_eth_dev *dev)
8291 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8292 uint32_t tsync_ctl_l;
8293 uint32_t tsync_ctl_h;
8295 /* Disable timestamping of transmitted PTP packets. */
8296 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8297 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8299 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8300 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8302 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8303 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8305 /* Reset the timesync increment value. */
8306 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8307 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8313 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8314 struct timespec *timestamp, uint32_t flags)
8316 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8317 struct i40e_adapter *adapter =
8318 (struct i40e_adapter *)dev->data->dev_private;
8320 uint32_t sync_status;
8321 uint32_t index = flags & 0x03;
8322 uint64_t rx_tstamp_cycles;
8325 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8326 if ((sync_status & (1 << index)) == 0)
8329 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8330 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8331 *timestamp = rte_ns_to_timespec(ns);
8337 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8338 struct timespec *timestamp)
8340 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8341 struct i40e_adapter *adapter =
8342 (struct i40e_adapter *)dev->data->dev_private;
8344 uint32_t sync_status;
8345 uint64_t tx_tstamp_cycles;
8348 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8349 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8352 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8353 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8354 *timestamp = rte_ns_to_timespec(ns);
8360 * i40e_parse_dcb_configure - parse dcb configure from user
8361 * @dev: the device being configured
8362 * @dcb_cfg: pointer of the result of parse
8363 * @*tc_map: bit map of enabled traffic classes
8365 * Returns 0 on success, negative value on failure
8368 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8369 struct i40e_dcbx_config *dcb_cfg,
8372 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8373 uint8_t i, tc_bw, bw_lf;
8375 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8377 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8378 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8379 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8383 /* assume each tc has the same bw */
8384 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8385 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8386 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8387 /* to ensure the sum of tcbw is equal to 100 */
8388 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8389 for (i = 0; i < bw_lf; i++)
8390 dcb_cfg->etscfg.tcbwtable[i]++;
8392 /* assume each tc has the same Transmission Selection Algorithm */
8393 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8394 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8396 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8397 dcb_cfg->etscfg.prioritytable[i] =
8398 dcb_rx_conf->dcb_tc[i];
8400 /* FW needs one App to configure HW */
8401 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8402 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8403 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8404 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8406 if (dcb_rx_conf->nb_tcs == 0)
8407 *tc_map = 1; /* tc0 only */
8409 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8411 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8412 dcb_cfg->pfc.willing = 0;
8413 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8414 dcb_cfg->pfc.pfcenable = *tc_map;
8420 static enum i40e_status_code
8421 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8422 struct i40e_aqc_vsi_properties_data *info,
8423 uint8_t enabled_tcmap)
8425 enum i40e_status_code ret;
8426 int i, total_tc = 0;
8427 uint16_t qpnum_per_tc, bsf, qp_idx;
8428 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8429 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8430 uint16_t used_queues;
8432 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8433 if (ret != I40E_SUCCESS)
8436 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8437 if (enabled_tcmap & (1 << i))
8442 vsi->enabled_tc = enabled_tcmap;
8444 /* different VSI has different queues assigned */
8445 if (vsi->type == I40E_VSI_MAIN)
8446 used_queues = dev_data->nb_rx_queues -
8447 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8448 else if (vsi->type == I40E_VSI_VMDQ2)
8449 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8451 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8452 return I40E_ERR_NO_AVAILABLE_VSI;
8455 qpnum_per_tc = used_queues / total_tc;
8456 /* Number of queues per enabled TC */
8457 if (qpnum_per_tc == 0) {
8458 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8459 return I40E_ERR_INVALID_QP_ID;
8461 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8463 bsf = rte_bsf32(qpnum_per_tc);
8466 * Configure TC and queue mapping parameters, for enabled TC,
8467 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8468 * default queue will serve it.
8471 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8472 if (vsi->enabled_tc & (1 << i)) {
8473 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8474 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8475 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8476 qp_idx += qpnum_per_tc;
8478 info->tc_mapping[i] = 0;
8481 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8482 if (vsi->type == I40E_VSI_SRIOV) {
8483 info->mapping_flags |=
8484 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8485 for (i = 0; i < vsi->nb_qps; i++)
8486 info->queue_mapping[i] =
8487 rte_cpu_to_le_16(vsi->base_queue + i);
8489 info->mapping_flags |=
8490 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8491 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8493 info->valid_sections |=
8494 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8496 return I40E_SUCCESS;
8500 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8501 * @veb: VEB to be configured
8502 * @tc_map: enabled TC bitmap
8504 * Returns 0 on success, negative value on failure
8506 static enum i40e_status_code
8507 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8509 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8510 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8511 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8512 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8513 enum i40e_status_code ret = I40E_SUCCESS;
8517 /* Check if enabled_tc is same as existing or new TCs */
8518 if (veb->enabled_tc == tc_map)
8521 /* configure tc bandwidth */
8522 memset(&veb_bw, 0, sizeof(veb_bw));
8523 veb_bw.tc_valid_bits = tc_map;
8524 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8525 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8526 if (tc_map & BIT_ULL(i))
8527 veb_bw.tc_bw_share_credits[i] = 1;
8529 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8532 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8533 " per TC failed = %d",
8534 hw->aq.asq_last_status);
8538 memset(&ets_query, 0, sizeof(ets_query));
8539 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8541 if (ret != I40E_SUCCESS) {
8542 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8543 " configuration %u", hw->aq.asq_last_status);
8546 memset(&bw_query, 0, sizeof(bw_query));
8547 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8549 if (ret != I40E_SUCCESS) {
8550 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8551 " configuration %u", hw->aq.asq_last_status);
8555 /* store and print out BW info */
8556 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8557 veb->bw_info.bw_max = ets_query.tc_bw_max;
8558 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8559 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8560 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8561 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8563 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8564 veb->bw_info.bw_ets_share_credits[i] =
8565 bw_query.tc_bw_share_credits[i];
8566 veb->bw_info.bw_ets_credits[i] =
8567 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8568 /* 4 bits per TC, 4th bit is reserved */
8569 veb->bw_info.bw_ets_max[i] =
8570 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8571 RTE_LEN2MASK(3, uint8_t));
8572 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8573 veb->bw_info.bw_ets_share_credits[i]);
8574 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8575 veb->bw_info.bw_ets_credits[i]);
8576 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8577 veb->bw_info.bw_ets_max[i]);
8580 veb->enabled_tc = tc_map;
8587 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8588 * @vsi: VSI to be configured
8589 * @tc_map: enabled TC bitmap
8591 * Returns 0 on success, negative value on failure
8593 static enum i40e_status_code
8594 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8596 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8597 struct i40e_vsi_context ctxt;
8598 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8599 enum i40e_status_code ret = I40E_SUCCESS;
8602 /* Check if enabled_tc is same as existing or new TCs */
8603 if (vsi->enabled_tc == tc_map)
8606 /* configure tc bandwidth */
8607 memset(&bw_data, 0, sizeof(bw_data));
8608 bw_data.tc_valid_bits = tc_map;
8609 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8610 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8611 if (tc_map & BIT_ULL(i))
8612 bw_data.tc_bw_credits[i] = 1;
8614 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8616 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8617 " per TC failed = %d",
8618 hw->aq.asq_last_status);
8621 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8622 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8624 /* Update Queue Pairs Mapping for currently enabled UPs */
8625 ctxt.seid = vsi->seid;
8626 ctxt.pf_num = hw->pf_id;
8628 ctxt.uplink_seid = vsi->uplink_seid;
8629 ctxt.info = vsi->info;
8631 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8635 /* Update the VSI after updating the VSI queue-mapping information */
8636 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8638 PMD_INIT_LOG(ERR, "Failed to configure "
8639 "TC queue mapping = %d",
8640 hw->aq.asq_last_status);
8643 /* update the local VSI info with updated queue map */
8644 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8645 sizeof(vsi->info.tc_mapping));
8646 (void)rte_memcpy(&vsi->info.queue_mapping,
8647 &ctxt.info.queue_mapping,
8648 sizeof(vsi->info.queue_mapping));
8649 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8650 vsi->info.valid_sections = 0;
8652 /* query and update current VSI BW information */
8653 ret = i40e_vsi_get_bw_config(vsi);
8656 "Failed updating vsi bw info, err %s aq_err %s",
8657 i40e_stat_str(hw, ret),
8658 i40e_aq_str(hw, hw->aq.asq_last_status));
8662 vsi->enabled_tc = tc_map;
8669 * i40e_dcb_hw_configure - program the dcb setting to hw
8670 * @pf: pf the configuration is taken on
8671 * @new_cfg: new configuration
8672 * @tc_map: enabled TC bitmap
8674 * Returns 0 on success, negative value on failure
8676 static enum i40e_status_code
8677 i40e_dcb_hw_configure(struct i40e_pf *pf,
8678 struct i40e_dcbx_config *new_cfg,
8681 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8682 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8683 struct i40e_vsi *main_vsi = pf->main_vsi;
8684 struct i40e_vsi_list *vsi_list;
8685 enum i40e_status_code ret;
8689 /* Use the FW API if FW > v4.4*/
8690 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8691 (hw->aq.fw_maj_ver >= 5))) {
8692 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8693 " to configure DCB");
8694 return I40E_ERR_FIRMWARE_API_VERSION;
8697 /* Check if need reconfiguration */
8698 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8699 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8700 return I40E_SUCCESS;
8703 /* Copy the new config to the current config */
8704 *old_cfg = *new_cfg;
8705 old_cfg->etsrec = old_cfg->etscfg;
8706 ret = i40e_set_dcb_config(hw);
8709 "Set DCB Config failed, err %s aq_err %s\n",
8710 i40e_stat_str(hw, ret),
8711 i40e_aq_str(hw, hw->aq.asq_last_status));
8714 /* set receive Arbiter to RR mode and ETS scheme by default */
8715 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8716 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8717 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8718 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8719 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8720 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8721 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8722 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8723 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8724 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8725 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8726 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8727 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8729 /* get local mib to check whether it is configured correctly */
8731 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8732 /* Get Local DCB Config */
8733 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8734 &hw->local_dcbx_config);
8736 /* if Veb is created, need to update TC of it at first */
8737 if (main_vsi->veb) {
8738 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8740 PMD_INIT_LOG(WARNING,
8741 "Failed configuring TC for VEB seid=%d\n",
8742 main_vsi->veb->seid);
8744 /* Update each VSI */
8745 i40e_vsi_config_tc(main_vsi, tc_map);
8746 if (main_vsi->veb) {
8747 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8748 /* Beside main VSI and VMDQ VSIs, only enable default
8751 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8752 ret = i40e_vsi_config_tc(vsi_list->vsi,
8755 ret = i40e_vsi_config_tc(vsi_list->vsi,
8756 I40E_DEFAULT_TCMAP);
8758 PMD_INIT_LOG(WARNING,
8759 "Failed configuring TC for VSI seid=%d\n",
8760 vsi_list->vsi->seid);
8764 return I40E_SUCCESS;
8768 * i40e_dcb_init_configure - initial dcb config
8769 * @dev: device being configured
8770 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8772 * Returns 0 on success, negative value on failure
8775 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8777 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8778 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8781 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8782 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8786 /* DCB initialization:
8787 * Update DCB configuration from the Firmware and configure
8788 * LLDP MIB change event.
8790 if (sw_dcb == TRUE) {
8791 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8792 if (ret != I40E_SUCCESS)
8793 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8795 ret = i40e_init_dcb(hw);
8796 /* if sw_dcb, lldp agent is stopped, the return from
8797 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8800 if (ret != I40E_SUCCESS &&
8801 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8802 memset(&hw->local_dcbx_config, 0,
8803 sizeof(struct i40e_dcbx_config));
8804 /* set dcb default configuration */
8805 hw->local_dcbx_config.etscfg.willing = 0;
8806 hw->local_dcbx_config.etscfg.maxtcs = 0;
8807 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8808 hw->local_dcbx_config.etscfg.tsatable[0] =
8810 hw->local_dcbx_config.etsrec =
8811 hw->local_dcbx_config.etscfg;
8812 hw->local_dcbx_config.pfc.willing = 0;
8813 hw->local_dcbx_config.pfc.pfccap =
8814 I40E_MAX_TRAFFIC_CLASS;
8815 /* FW needs one App to configure HW */
8816 hw->local_dcbx_config.numapps = 1;
8817 hw->local_dcbx_config.app[0].selector =
8818 I40E_APP_SEL_ETHTYPE;
8819 hw->local_dcbx_config.app[0].priority = 3;
8820 hw->local_dcbx_config.app[0].protocolid =
8821 I40E_APP_PROTOID_FCOE;
8822 ret = i40e_set_dcb_config(hw);
8824 PMD_INIT_LOG(ERR, "default dcb config fails."
8825 " err = %d, aq_err = %d.", ret,
8826 hw->aq.asq_last_status);
8830 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8831 " aq_err = %d.", ret,
8832 hw->aq.asq_last_status);
8836 ret = i40e_aq_start_lldp(hw, NULL);
8837 if (ret != I40E_SUCCESS)
8838 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8840 ret = i40e_init_dcb(hw);
8842 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8843 PMD_INIT_LOG(ERR, "HW doesn't support"
8848 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8849 " aq_err = %d.", ret,
8850 hw->aq.asq_last_status);
8858 * i40e_dcb_setup - setup dcb related config
8859 * @dev: device being configured
8861 * Returns 0 on success, negative value on failure
8864 i40e_dcb_setup(struct rte_eth_dev *dev)
8866 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8867 struct i40e_dcbx_config dcb_cfg;
8871 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8872 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8876 if (pf->vf_num != 0)
8877 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8879 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8881 PMD_INIT_LOG(ERR, "invalid dcb config");
8884 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8886 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8894 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8895 struct rte_eth_dcb_info *dcb_info)
8897 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8898 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8899 struct i40e_vsi *vsi = pf->main_vsi;
8900 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8901 uint16_t bsf, tc_mapping;
8904 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8905 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8907 dcb_info->nb_tcs = 1;
8908 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8909 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8910 for (i = 0; i < dcb_info->nb_tcs; i++)
8911 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8913 /* get queue mapping if vmdq is disabled */
8914 if (!pf->nb_cfg_vmdq_vsi) {
8915 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8916 if (!(vsi->enabled_tc & (1 << i)))
8918 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8919 dcb_info->tc_queue.tc_rxq[j][i].base =
8920 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8921 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8922 dcb_info->tc_queue.tc_txq[j][i].base =
8923 dcb_info->tc_queue.tc_rxq[j][i].base;
8924 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8925 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8926 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8927 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8928 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8933 /* get queue mapping if vmdq is enabled */
8935 vsi = pf->vmdq[j].vsi;
8936 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8937 if (!(vsi->enabled_tc & (1 << i)))
8939 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8940 dcb_info->tc_queue.tc_rxq[j][i].base =
8941 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8942 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8943 dcb_info->tc_queue.tc_txq[j][i].base =
8944 dcb_info->tc_queue.tc_rxq[j][i].base;
8945 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8946 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8947 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8948 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8949 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8952 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8957 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8959 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8962 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8965 msix_intr = intr_handle->intr_vec[queue_id];
8966 if (msix_intr == I40E_MISC_VEC_ID)
8967 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8968 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8969 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8970 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8972 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8975 I40E_PFINT_DYN_CTLN(msix_intr -
8977 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8978 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8979 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8981 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8983 I40E_WRITE_FLUSH(hw);
8984 rte_intr_enable(&dev->pci_dev->intr_handle);
8990 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8992 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8993 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8996 msix_intr = intr_handle->intr_vec[queue_id];
8997 if (msix_intr == I40E_MISC_VEC_ID)
8998 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9001 I40E_PFINT_DYN_CTLN(msix_intr -
9004 I40E_WRITE_FLUSH(hw);
9009 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9011 /* Highest base addr + 32-bit word */
9012 return I40E_GLGEN_STAT_CLEAR + 4;
9015 static int i40e_get_regs(struct rte_eth_dev *dev,
9016 struct rte_dev_reg_info *regs)
9018 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9019 uint32_t *ptr_data = regs->data;
9020 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9021 const struct i40e_reg_info *reg_info;
9023 /* The first few registers have to be read using AQ operations */
9025 while (i40e_regs_adminq[reg_idx].name) {
9026 reg_info = &i40e_regs_adminq[reg_idx++];
9027 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9029 arr_idx2 <= reg_info->count2;
9031 reg_offset = arr_idx * reg_info->stride1 +
9032 arr_idx2 * reg_info->stride2;
9033 reg_offset += reg_info->base_addr;
9034 ptr_data[reg_offset >> 2] =
9035 i40e_read_rx_ctl(hw, reg_offset);
9039 /* The remaining registers can be read using primitives */
9041 while (i40e_regs_others[reg_idx].name) {
9042 reg_info = &i40e_regs_others[reg_idx++];
9043 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9045 arr_idx2 <= reg_info->count2;
9047 reg_offset = arr_idx * reg_info->stride1 +
9048 arr_idx2 * reg_info->stride2;
9049 reg_offset += reg_info->base_addr;
9050 ptr_data[reg_offset >> 2] =
9051 I40E_READ_REG(hw, reg_offset);
9058 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9060 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9062 /* Convert word count to byte count */
9063 return hw->nvm.sr_size << 1;
9066 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9067 struct rte_dev_eeprom_info *eeprom)
9069 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9070 uint16_t *data = eeprom->data;
9071 uint16_t offset, length, cnt_words;
9074 offset = eeprom->offset >> 1;
9075 length = eeprom->length >> 1;
9078 if (offset > hw->nvm.sr_size ||
9079 offset + length > hw->nvm.sr_size) {
9080 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9084 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9086 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9087 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9088 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9095 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9096 struct ether_addr *mac_addr)
9098 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9100 if (!is_valid_assigned_ether_addr(mac_addr)) {
9101 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9105 /* Flags: 0x3 updates port address */
9106 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);