drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "base/i40e_dcb.h"
  60 #include "i40e_ethdev.h"
  61 #include "i40e_rxtx.h"
  62 #include "i40e_pf.h"
  63
  64 /* Maximun number of MAC addresses */
  65 #define I40E_NUM_MACADDR_MAX       64
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 /* Default queue interrupt throttling time in microseconds */
  79 #define I40E_ITR_INDEX_DEFAULT          0
  80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  81 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA  0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 143 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 144 static int i40e_dev_configure(struct rte_eth_dev *dev);
 145 static int i40e_dev_start(struct rte_eth_dev *dev);
 146 static void i40e_dev_stop(struct rte_eth_dev *dev);
 147 static void i40e_dev_close(struct rte_eth_dev *dev);
 148 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 149 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 150 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 151 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 152 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 153 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 154 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 155                                struct rte_eth_stats *stats);
 156 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 157 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 158                                             uint16_t queue_id,
 159                                             uint8_t stat_idx,
 160                                             uint8_t is_rx);
 161 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 162                               struct rte_eth_dev_info *dev_info);
 163 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 164                                 uint16_t vlan_id,
 165                                 int on);
 166 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 167 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 168 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 169                                       uint16_t queue,
 170                                       int on);
 171 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 172 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 173 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 174 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 175                               struct rte_eth_fc_conf *fc_conf);
 176 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 177                               struct rte_eth_fc_conf *fc_conf);
 178 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 179                                        struct rte_eth_pfc_conf *pfc_conf);
 180 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 181                           struct ether_addr *mac_addr,
 182                           uint32_t index,
 183                           uint32_t pool);
 184 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 185 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 186                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                     uint16_t reta_size);
 188 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 189                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 190                                    uint16_t reta_size);
 191
 192 static int i40e_get_cap(struct i40e_hw *hw);
 193 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 194 static int i40e_pf_setup(struct i40e_pf *pf);
 195 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 196 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 197 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 198 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 199 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 200                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 201 static void i40e_stat_update_48(struct i40e_hw *hw,
 202                                uint32_t hireg,
 203                                uint32_t loreg,
 204                                bool offset_loaded,
 205                                uint64_t *offset,
 206                                uint64_t *stat);
 207 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 208 static void i40e_dev_interrupt_handler(
 209                 __rte_unused struct rte_intr_handle *handle, void *param);
 210 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 211                                 uint32_t base, uint32_t num);
 212 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 213 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 214                         uint32_t base);
 215 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 216                         uint16_t num);
 217 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 218 static int i40e_veb_release(struct i40e_veb *veb);
 219 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 220                                                 struct i40e_vsi *vsi);
 221 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 222 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 223 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 224                                              struct i40e_macvlan_filter *mv_f,
 225                                              int num,
 226                                              struct ether_addr *addr);
 227 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 228                                              struct i40e_macvlan_filter *mv_f,
 229                                              int num,
 230                                              uint16_t vlan);
 231 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 232 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 233                                     struct rte_eth_rss_conf *rss_conf);
 234 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 235                                       struct rte_eth_rss_conf *rss_conf);
 236 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 237                                 struct rte_eth_udp_tunnel *udp_tunnel);
 238 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 239                                 struct rte_eth_udp_tunnel *udp_tunnel);
 240 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 241                         struct rte_eth_ethertype_filter *filter,
 242                         bool add);
 243 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 244                                 enum rte_filter_op filter_op,
 245                                 void *arg);
 246 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 247                                 enum rte_filter_type filter_type,
 248                                 enum rte_filter_op filter_op,
 249                                 void *arg);
 250 static void i40e_configure_registers(struct i40e_hw *hw);
 251 static void i40e_hw_init(struct i40e_hw *hw);
 252 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 253 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 254                         struct rte_eth_mirror_conf *mirror_conf,
 255                         uint8_t sw_id, uint8_t on);
 256 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 257
 258 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 259 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 260 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 261                                            struct timespec *timestamp,
 262                                            uint32_t flags);
 263 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 264                                            struct timespec *timestamp);
 265
 266 static const struct rte_pci_id pci_id_i40e_map[] = {
 267 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 268 #include "rte_pci_dev_ids.h"
 269 { .vendor_id = 0, /* sentinel */ },
 270 };
 271
 272 static const struct eth_dev_ops i40e_eth_dev_ops = {
 273         .dev_configure                = i40e_dev_configure,
 274         .dev_start                    = i40e_dev_start,
 275         .dev_stop                     = i40e_dev_stop,
 276         .dev_close                    = i40e_dev_close,
 277         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 278         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 279         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 280         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 281         .dev_set_link_up              = i40e_dev_set_link_up,
 282         .dev_set_link_down            = i40e_dev_set_link_down,
 283         .link_update                  = i40e_dev_link_update,
 284         .stats_get                    = i40e_dev_stats_get,
 285         .stats_reset                  = i40e_dev_stats_reset,
 286         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 287         .dev_infos_get                = i40e_dev_info_get,
 288         .vlan_filter_set              = i40e_vlan_filter_set,
 289         .vlan_tpid_set                = i40e_vlan_tpid_set,
 290         .vlan_offload_set             = i40e_vlan_offload_set,
 291         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 292         .vlan_pvid_set                = i40e_vlan_pvid_set,
 293         .rx_queue_start               = i40e_dev_rx_queue_start,
 294         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 295         .tx_queue_start               = i40e_dev_tx_queue_start,
 296         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 297         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 298         .rx_queue_release             = i40e_dev_rx_queue_release,
 299         .rx_queue_count               = i40e_dev_rx_queue_count,
 300         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 301         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 302         .tx_queue_release             = i40e_dev_tx_queue_release,
 303         .dev_led_on                   = i40e_dev_led_on,
 304         .dev_led_off                  = i40e_dev_led_off,
 305         .flow_ctrl_get                = i40e_flow_ctrl_get,
 306         .flow_ctrl_set                = i40e_flow_ctrl_set,
 307         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 308         .mac_addr_add                 = i40e_macaddr_add,
 309         .mac_addr_remove              = i40e_macaddr_remove,
 310         .reta_update                  = i40e_dev_rss_reta_update,
 311         .reta_query                   = i40e_dev_rss_reta_query,
 312         .rss_hash_update              = i40e_dev_rss_hash_update,
 313         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 314         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 315         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 316         .filter_ctrl                  = i40e_dev_filter_ctrl,
 317         .mirror_rule_set              = i40e_mirror_rule_set,
 318         .mirror_rule_reset            = i40e_mirror_rule_reset,
 319         .timesync_enable              = i40e_timesync_enable,
 320         .timesync_disable             = i40e_timesync_disable,
 321         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 322         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 323 };
 324
 325 static struct eth_driver rte_i40e_pmd = {
 326         .pci_drv = {
 327                 .name = "rte_i40e_pmd",
 328                 .id_table = pci_id_i40e_map,
 329                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 330                         RTE_PCI_DRV_DETACHABLE,
 331         },
 332         .eth_dev_init = eth_i40e_dev_init,
 333         .eth_dev_uninit = eth_i40e_dev_uninit,
 334         .dev_private_size = sizeof(struct i40e_adapter),
 335 };
 336
 337 static inline int
 338 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 339                                      struct rte_eth_link *link)
 340 {
 341         struct rte_eth_link *dst = link;
 342         struct rte_eth_link *src = &(dev->data->dev_link);
 343
 344         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 345                                         *(uint64_t *)src) == 0)
 346                 return -1;
 347
 348         return 0;
 349 }
 350
 351 static inline int
 352 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 353                                       struct rte_eth_link *link)
 354 {
 355         struct rte_eth_link *dst = &(dev->data->dev_link);
 356         struct rte_eth_link *src = link;
 357
 358         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 359                                         *(uint64_t *)src) == 0)
 360                 return -1;
 361
 362         return 0;
 363 }
 364
 365 /*
 366  * Driver initialization routine.
 367  * Invoked once at EAL init time.
 368  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 369  */
 370 static int
 371 rte_i40e_pmd_init(const char *name __rte_unused,
 372                   const char *params __rte_unused)
 373 {
 374         PMD_INIT_FUNC_TRACE();
 375         rte_eth_driver_register(&rte_i40e_pmd);
 376
 377         return 0;
 378 }
 379
 380 static struct rte_driver rte_i40e_driver = {
 381         .type = PMD_PDEV,
 382         .init = rte_i40e_pmd_init,
 383 };
 384
 385 PMD_REGISTER_DRIVER(rte_i40e_driver);
 386
 387 /*
 388  * Initialize registers for flexible payload, which should be set by NVM.
 389  * This should be removed from code once it is fixed in NVM.
 390  */
 391 #ifndef I40E_GLQF_ORT
 392 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 393 #endif
 394 #ifndef I40E_GLQF_PIT
 395 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 396 #endif
 397
 398 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 399 {
 400         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 401         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 402         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 403         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 404         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 405         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 406         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 407         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 408         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 409         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 410
 411         /* GLQF_PIT Registers */
 412         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 413         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 414 }
 415
 416 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 417
 418 /*
 419  * Add a ethertype filter to drop all flow control frames transmitted
 420  * from VSIs.
 421 */
 422 static void
 423 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 424 {
 425         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 426         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 427                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 428                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 429         int ret;
 430
 431         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 432                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 433                                 pf->main_vsi_seid, 0,
 434                                 TRUE, NULL, NULL);
 435         if (ret)
 436                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 437                                   " frames from VSIs.");
 438 }
 439
 440 static int
 441 eth_i40e_dev_init(struct rte_eth_dev *dev)
 442 {
 443         struct rte_pci_device *pci_dev;
 444         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 445         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 446         struct i40e_vsi *vsi;
 447         int ret;
 448         uint32_t len;
 449         uint8_t aq_fail = 0;
 450
 451         PMD_INIT_FUNC_TRACE();
 452
 453         dev->dev_ops = &i40e_eth_dev_ops;
 454         dev->rx_pkt_burst = i40e_recv_pkts;
 455         dev->tx_pkt_burst = i40e_xmit_pkts;
 456
 457         /* for secondary processes, we don't initialise any further as primary
 458          * has already done this work. Only check we don't need a different
 459          * RX function */
 460         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 461                 i40e_set_rx_function(dev);
 462                 i40e_set_tx_function(dev);
 463                 return 0;
 464         }
 465         pci_dev = dev->pci_dev;
 466         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 467         pf->adapter->eth_dev = dev;
 468         pf->dev_data = dev->data;
 469
 470         hw->back = I40E_PF_TO_ADAPTER(pf);
 471         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 472         if (!hw->hw_addr) {
 473                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 474                              "as address is NULL");
 475                 return -ENODEV;
 476         }
 477
 478         hw->vendor_id = pci_dev->id.vendor_id;
 479         hw->device_id = pci_dev->id.device_id;
 480         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 481         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 482         hw->bus.device = pci_dev->addr.devid;
 483         hw->bus.func = pci_dev->addr.function;
 484         hw->adapter_stopped = 0;
 485
 486         /* Make sure all is clean before doing PF reset */
 487         i40e_clear_hw(hw);
 488
 489         /* Initialize the hardware */
 490         i40e_hw_init(hw);
 491
 492         /* Reset here to make sure all is clean for each PF */
 493         ret = i40e_pf_reset(hw);
 494         if (ret) {
 495                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 496                 return ret;
 497         }
 498
 499         /* Initialize the shared code (base driver) */
 500         ret = i40e_init_shared_code(hw);
 501         if (ret) {
 502                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 503                 return ret;
 504         }
 505
 506         /*
 507          * To work around the NVM issue,initialize registers
 508          * for flexible payload by software.
 509          * It should be removed once issues are fixed in NVM.
 510          */
 511         i40e_flex_payload_reg_init(hw);
 512
 513         /* Initialize the parameters for adminq */
 514         i40e_init_adminq_parameter(hw);
 515         ret = i40e_init_adminq(hw);
 516         if (ret != I40E_SUCCESS) {
 517                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 518                 return -EIO;
 519         }
 520         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 521                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 522                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 523                      ((hw->nvm.version >> 12) & 0xf),
 524                      ((hw->nvm.version >> 4) & 0xff),
 525                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 526
 527         /* Clear PXE mode */
 528         i40e_clear_pxe_mode(hw);
 529
 530         /*
 531          * On X710, performance number is far from the expectation on recent
 532          * firmware versions. The fix for this issue may not be integrated in
 533          * the following firmware version. So the workaround in software driver
 534          * is needed. It needs to modify the initial values of 3 internal only
 535          * registers. Note that the workaround can be removed when it is fixed
 536          * in firmware in the future.
 537          */
 538         i40e_configure_registers(hw);
 539
 540         /* Get hw capabilities */
 541         ret = i40e_get_cap(hw);
 542         if (ret != I40E_SUCCESS) {
 543                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 544                 goto err_get_capabilities;
 545         }
 546
 547         /* Initialize parameters for PF */
 548         ret = i40e_pf_parameter_init(dev);
 549         if (ret != 0) {
 550                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 551                 goto err_parameter_init;
 552         }
 553
 554         /* Initialize the queue management */
 555         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 556         if (ret < 0) {
 557                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 558                 goto err_qp_pool_init;
 559         }
 560         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 561                                 hw->func_caps.num_msix_vectors - 1);
 562         if (ret < 0) {
 563                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 564                 goto err_msix_pool_init;
 565         }
 566
 567         /* Initialize lan hmc */
 568         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 569                                 hw->func_caps.num_rx_qp, 0, 0);
 570         if (ret != I40E_SUCCESS) {
 571                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 572                 goto err_init_lan_hmc;
 573         }
 574
 575         /* Configure lan hmc */
 576         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 577         if (ret != I40E_SUCCESS) {
 578                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 579                 goto err_configure_lan_hmc;
 580         }
 581
 582         /* Get and check the mac address */
 583         i40e_get_mac_addr(hw, hw->mac.addr);
 584         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 585                 PMD_INIT_LOG(ERR, "mac address is not valid");
 586                 ret = -EIO;
 587                 goto err_get_mac_addr;
 588         }
 589         /* Copy the permanent MAC address */
 590         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 591                         (struct ether_addr *) hw->mac.perm_addr);
 592
 593         /* Disable flow control */
 594         hw->fc.requested_mode = I40E_FC_NONE;
 595         i40e_set_fc(hw, &aq_fail, TRUE);
 596
 597         /* PF setup, which includes VSI setup */
 598         ret = i40e_pf_setup(pf);
 599         if (ret) {
 600                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 601                 goto err_setup_pf_switch;
 602         }
 603
 604         vsi = pf->main_vsi;
 605
 606         /* Disable double vlan by default */
 607         i40e_vsi_config_double_vlan(vsi, FALSE);
 608
 609         if (!vsi->max_macaddrs)
 610                 len = ETHER_ADDR_LEN;
 611         else
 612                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 613
 614         /* Should be after VSI initialized */
 615         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 616         if (!dev->data->mac_addrs) {
 617                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 618                                         "for storing mac address");
 619                 goto err_mac_alloc;
 620         }
 621         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 622                                         &dev->data->mac_addrs[0]);
 623
 624         /* initialize pf host driver to setup SRIOV resource if applicable */
 625         i40e_pf_host_init(dev);
 626
 627         /* register callback func to eal lib */
 628         rte_intr_callback_register(&(pci_dev->intr_handle),
 629                 i40e_dev_interrupt_handler, (void *)dev);
 630
 631         /* configure and enable device interrupt */
 632         i40e_pf_config_irq0(hw);
 633         i40e_pf_enable_irq0(hw);
 634
 635         /* enable uio intr after callback register */
 636         rte_intr_enable(&(pci_dev->intr_handle));
 637         /*
 638          * Add an ethertype filter to drop all flow control frames transmitted
 639          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 640          * frames to wire.
 641          */
 642         i40e_add_tx_flow_control_drop_filter(pf);
 643
 644         /* initialize mirror rule list */
 645         TAILQ_INIT(&pf->mirror_list);
 646
 647         /* Init dcb to sw mode by default */
 648         ret = i40e_dcb_init_configure(dev, TRUE);
 649         if (ret != I40E_SUCCESS) {
 650                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 651                 pf->flags &= ~I40E_FLAG_DCB;
 652         }
 653
 654         return 0;
 655
 656 err_mac_alloc:
 657         i40e_vsi_release(pf->main_vsi);
 658 err_setup_pf_switch:
 659 err_get_mac_addr:
 660 err_configure_lan_hmc:
 661         (void)i40e_shutdown_lan_hmc(hw);
 662 err_init_lan_hmc:
 663         i40e_res_pool_destroy(&pf->msix_pool);
 664 err_msix_pool_init:
 665         i40e_res_pool_destroy(&pf->qp_pool);
 666 err_qp_pool_init:
 667 err_parameter_init:
 668 err_get_capabilities:
 669         (void)i40e_shutdown_adminq(hw);
 670
 671         return ret;
 672 }
 673
 674 static int
 675 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 676 {
 677         struct rte_pci_device *pci_dev;
 678         struct i40e_hw *hw;
 679         struct i40e_filter_control_settings settings;
 680         int ret;
 681         uint8_t aq_fail = 0;
 682
 683         PMD_INIT_FUNC_TRACE();
 684
 685         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 686                 return 0;
 687
 688         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 689         pci_dev = dev->pci_dev;
 690
 691         if (hw->adapter_stopped == 0)
 692                 i40e_dev_close(dev);
 693
 694         dev->dev_ops = NULL;
 695         dev->rx_pkt_burst = NULL;
 696         dev->tx_pkt_burst = NULL;
 697
 698         /* Disable LLDP */
 699         ret = i40e_aq_stop_lldp(hw, true, NULL);
 700         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 701                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 702
 703         /* Clear PXE mode */
 704         i40e_clear_pxe_mode(hw);
 705
 706         /* Unconfigure filter control */
 707         memset(&settings, 0, sizeof(settings));
 708         ret = i40e_set_filter_control(hw, &settings);
 709         if (ret)
 710                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 711                                         ret);
 712
 713         /* Disable flow control */
 714         hw->fc.requested_mode = I40E_FC_NONE;
 715         i40e_set_fc(hw, &aq_fail, TRUE);
 716
 717         /* uninitialize pf host driver */
 718         i40e_pf_host_uninit(dev);
 719
 720         rte_free(dev->data->mac_addrs);
 721         dev->data->mac_addrs = NULL;
 722
 723         /* disable uio intr before callback unregister */
 724         rte_intr_disable(&(pci_dev->intr_handle));
 725
 726         /* register callback func to eal lib */
 727         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 728                 i40e_dev_interrupt_handler, (void *)dev);
 729
 730         return 0;
 731 }
 732
 733 static int
 734 i40e_dev_configure(struct rte_eth_dev *dev)
 735 {
 736         struct i40e_adapter *ad =
 737                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 738         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 739         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 740         int i, ret;
 741
 742         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 743          * bulk allocation or vector Rx preconditions we will reset it.
 744          */
 745         ad->rx_bulk_alloc_allowed = true;
 746         ad->rx_vec_allowed = true;
 747         ad->tx_simple_allowed = true;
 748         ad->tx_vec_allowed = true;
 749
 750         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 751                 ret = i40e_fdir_setup(pf);
 752                 if (ret != I40E_SUCCESS) {
 753                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 754                         return -ENOTSUP;
 755                 }
 756                 ret = i40e_fdir_configure(dev);
 757                 if (ret < 0) {
 758                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 759                         goto err;
 760                 }
 761         } else
 762                 i40e_fdir_teardown(pf);
 763
 764         ret = i40e_dev_init_vlan(dev);
 765         if (ret < 0)
 766                 goto err;
 767
 768         /* VMDQ setup.
 769          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 770          *  RSS setting have different requirements.
 771          *  General PMD driver call sequence are NIC init, configure,
 772          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 773          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 774          *  applicable. So, VMDQ setting has to be done before
 775          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 776          *  For RSS setting, it will try to calculate actual configured RX queue
 777          *  number, which will be available after rx_queue_setup(). dev_start()
 778          *  function is good to place RSS setup.
 779          */
 780         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 781                 ret = i40e_vmdq_setup(dev);
 782                 if (ret)
 783                         goto err;
 784         }
 785
 786         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
 787                 ret = i40e_dcb_setup(dev);
 788                 if (ret) {
 789                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
 790                         goto err_dcb;
 791                 }
 792         }
 793
 794         return 0;
 795
 796 err_dcb:
 797         /* need to release vmdq resource if exists */
 798         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 799                 i40e_vsi_release(pf->vmdq[i].vsi);
 800                 pf->vmdq[i].vsi = NULL;
 801         }
 802         rte_free(pf->vmdq);
 803         pf->vmdq = NULL;
 804 err:
 805         /* need to release fdir resource if exists */
 806         i40e_fdir_teardown(pf);
 807         return ret;
 808 }
 809
 810 void
 811 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 812 {
 813         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 814         uint16_t msix_vect = vsi->msix_intr;
 815         uint16_t i;
 816
 817         for (i = 0; i < vsi->nb_qps; i++) {
 818                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 819                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 820                 rte_wmb();
 821         }
 822
 823         if (vsi->type != I40E_VSI_SRIOV) {
 824                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 825                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 826                                 msix_vect - 1), 0);
 827         } else {
 828                 uint32_t reg;
 829                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 830                         vsi->user_param + (msix_vect - 1);
 831
 832                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 833         }
 834         I40E_WRITE_FLUSH(hw);
 835 }
 836
 837 static inline uint16_t
 838 i40e_calc_itr_interval(int16_t interval)
 839 {
 840         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 841                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 842
 843         /* Convert to hardware count, as writing each 1 represents 2 us */
 844         return (interval/2);
 845 }
 846
 847 void
 848 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 849 {
 850         uint32_t val;
 851         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 852         uint16_t msix_vect = vsi->msix_intr;
 853         int i;
 854
 855         for (i = 0; i < vsi->nb_qps; i++)
 856                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 857
 858         /* Bind all RX queues to allocated MSIX interrupt */
 859         for (i = 0; i < vsi->nb_qps; i++) {
 860                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 861                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 862                         ((vsi->base_queue + i + 1) <<
 863                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 864                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 865                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 866
 867                 if (i == vsi->nb_qps - 1)
 868                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 869                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 870         }
 871
 872         /* Write first RX queue to Link list register as the head element */
 873         if (vsi->type != I40E_VSI_SRIOV) {
 874                 uint16_t interval =
 875                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 876
 877                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 878                                                 (vsi->base_queue <<
 879                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 880                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 881
 882                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 883                                                 msix_vect - 1), interval);
 884
 885 #ifndef I40E_GLINT_CTL
 886 #define I40E_GLINT_CTL                     0x0003F800
 887 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 888 #endif
 889                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 890                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 891                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 892         } else {
 893                 uint32_t reg;
 894
 895                 /* num_msix_vectors_vf needs to minus irq0 */
 896                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 897                         vsi->user_param + (msix_vect - 1);
 898
 899                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 900                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 901                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 902         }
 903
 904         I40E_WRITE_FLUSH(hw);
 905 }
 906
 907 static void
 908 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 909 {
 910         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 911         uint16_t interval = i40e_calc_itr_interval(\
 912                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 913
 914         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 915                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 916                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 917                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 918                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 919 }
 920
 921 static void
 922 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 923 {
 924         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 925
 926         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 927 }
 928
 929 static inline uint8_t
 930 i40e_parse_link_speed(uint16_t eth_link_speed)
 931 {
 932         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 933
 934         switch (eth_link_speed) {
 935         case ETH_LINK_SPEED_40G:
 936                 link_speed = I40E_LINK_SPEED_40GB;
 937                 break;
 938         case ETH_LINK_SPEED_20G:
 939                 link_speed = I40E_LINK_SPEED_20GB;
 940                 break;
 941         case ETH_LINK_SPEED_10G:
 942                 link_speed = I40E_LINK_SPEED_10GB;
 943                 break;
 944         case ETH_LINK_SPEED_1000:
 945                 link_speed = I40E_LINK_SPEED_1GB;
 946                 break;
 947         case ETH_LINK_SPEED_100:
 948                 link_speed = I40E_LINK_SPEED_100MB;
 949                 break;
 950         }
 951
 952         return link_speed;
 953 }
 954
 955 static int
 956 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 957 {
 958         enum i40e_status_code status;
 959         struct i40e_aq_get_phy_abilities_resp phy_ab;
 960         struct i40e_aq_set_phy_config phy_conf;
 961         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 962                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 963                         I40E_AQ_PHY_FLAG_LOW_POWER;
 964         const uint8_t advt = I40E_LINK_SPEED_40GB |
 965                         I40E_LINK_SPEED_10GB |
 966                         I40E_LINK_SPEED_1GB |
 967                         I40E_LINK_SPEED_100MB;
 968         int ret = -ENOTSUP;
 969
 970         /* Skip it on 40G interfaces, as a workaround for the link issue */
 971         if (i40e_is_40G_device(hw->device_id))
 972                 return I40E_SUCCESS;
 973
 974         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 975                                               NULL);
 976         if (status)
 977                 return ret;
 978
 979         memset(&phy_conf, 0, sizeof(phy_conf));
 980
 981         /* bits 0-2 use the values from get_phy_abilities_resp */
 982         abilities &= ~mask;
 983         abilities |= phy_ab.abilities & mask;
 984
 985         /* update ablities and speed */
 986         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 987                 phy_conf.link_speed = advt;
 988         else
 989                 phy_conf.link_speed = force_speed;
 990
 991         phy_conf.abilities = abilities;
 992
 993         /* use get_phy_abilities_resp value for the rest */
 994         phy_conf.phy_type = phy_ab.phy_type;
 995         phy_conf.eee_capability = phy_ab.eee_capability;
 996         phy_conf.eeer = phy_ab.eeer_val;
 997         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 998
 999         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1000                     phy_ab.abilities, phy_ab.link_speed);
1001         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1002                     phy_conf.abilities, phy_conf.link_speed);
1003
1004         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1005         if (status)
1006                 return ret;
1007
1008         return I40E_SUCCESS;
1009 }
1010
1011 static int
1012 i40e_apply_link_speed(struct rte_eth_dev *dev)
1013 {
1014         uint8_t speed;
1015         uint8_t abilities = 0;
1016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017         struct rte_eth_conf *conf = &dev->data->dev_conf;
1018
1019         speed = i40e_parse_link_speed(conf->link_speed);
1020         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1021         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1022                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1023         else
1024                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1025
1026         return i40e_phy_conf_link(hw, abilities, speed);
1027 }
1028
1029 static int
1030 i40e_dev_start(struct rte_eth_dev *dev)
1031 {
1032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1033         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1034         struct i40e_vsi *main_vsi = pf->main_vsi;
1035         int ret, i;
1036
1037         hw->adapter_stopped = 0;
1038
1039         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1040                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1041                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1042                              dev->data->dev_conf.link_duplex,
1043                              dev->data->port_id);
1044                 return -EINVAL;
1045         }
1046
1047         /* Initialize VSI */
1048         ret = i40e_dev_rxtx_init(pf);
1049         if (ret != I40E_SUCCESS) {
1050                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1051                 goto err_up;
1052         }
1053
1054         /* Map queues with MSIX interrupt */
1055         i40e_vsi_queues_bind_intr(main_vsi);
1056         i40e_vsi_enable_queues_intr(main_vsi);
1057
1058         /* Map VMDQ VSI queues with MSIX interrupt */
1059         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1060                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1061                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1062         }
1063
1064         /* enable FDIR MSIX interrupt */
1065         if (pf->fdir.fdir_vsi) {
1066                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1067                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1068         }
1069
1070         /* Enable all queues which have been configured */
1071         ret = i40e_dev_switch_queues(pf, TRUE);
1072         if (ret != I40E_SUCCESS) {
1073                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1074                 goto err_up;
1075         }
1076
1077         /* Enable receiving broadcast packets */
1078         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1079         if (ret != I40E_SUCCESS)
1080                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1081
1082         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1083                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1084                                                 true, NULL);
1085                 if (ret != I40E_SUCCESS)
1086                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1087         }
1088
1089         /* Apply link configure */
1090         ret = i40e_apply_link_speed(dev);
1091         if (I40E_SUCCESS != ret) {
1092                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1093                 goto err_up;
1094         }
1095
1096         return I40E_SUCCESS;
1097
1098 err_up:
1099         i40e_dev_switch_queues(pf, FALSE);
1100         i40e_dev_clear_queues(dev);
1101
1102         return ret;
1103 }
1104
1105 static void
1106 i40e_dev_stop(struct rte_eth_dev *dev)
1107 {
1108         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1109         struct i40e_vsi *main_vsi = pf->main_vsi;
1110         struct i40e_mirror_rule *p_mirror;
1111         int i;
1112
1113         /* Disable all queues */
1114         i40e_dev_switch_queues(pf, FALSE);
1115
1116         /* un-map queues with interrupt registers */
1117         i40e_vsi_disable_queues_intr(main_vsi);
1118         i40e_vsi_queues_unbind_intr(main_vsi);
1119
1120         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1121                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1122                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1123         }
1124
1125         if (pf->fdir.fdir_vsi) {
1126                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1127                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1128         }
1129         /* Clear all queues and release memory */
1130         i40e_dev_clear_queues(dev);
1131
1132         /* Set link down */
1133         i40e_dev_set_link_down(dev);
1134
1135         /* Remove all mirror rules */
1136         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1137                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1138                 rte_free(p_mirror);
1139         }
1140         pf->nb_mirror_rule = 0;
1141
1142 }
1143
1144 static void
1145 i40e_dev_close(struct rte_eth_dev *dev)
1146 {
1147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1149         uint32_t reg;
1150         int i;
1151
1152         PMD_INIT_FUNC_TRACE();
1153
1154         i40e_dev_stop(dev);
1155         hw->adapter_stopped = 1;
1156         i40e_dev_free_queues(dev);
1157
1158         /* Disable interrupt */
1159         i40e_pf_disable_irq0(hw);
1160         rte_intr_disable(&(dev->pci_dev->intr_handle));
1161
1162         /* shutdown and destroy the HMC */
1163         i40e_shutdown_lan_hmc(hw);
1164
1165         /* release all the existing VSIs and VEBs */
1166         i40e_fdir_teardown(pf);
1167         i40e_vsi_release(pf->main_vsi);
1168
1169         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1170                 i40e_vsi_release(pf->vmdq[i].vsi);
1171                 pf->vmdq[i].vsi = NULL;
1172         }
1173
1174         rte_free(pf->vmdq);
1175         pf->vmdq = NULL;
1176
1177         /* shutdown the adminq */
1178         i40e_aq_queue_shutdown(hw, true);
1179         i40e_shutdown_adminq(hw);
1180
1181         i40e_res_pool_destroy(&pf->qp_pool);
1182         i40e_res_pool_destroy(&pf->msix_pool);
1183
1184         /* force a PF reset to clean anything leftover */
1185         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1186         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1187                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1188         I40E_WRITE_FLUSH(hw);
1189 }
1190
1191 static void
1192 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1193 {
1194         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1195         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196         struct i40e_vsi *vsi = pf->main_vsi;
1197         int status;
1198
1199         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1200                                                         true, NULL);
1201         if (status != I40E_SUCCESS)
1202                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1203
1204         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1205                                                         TRUE, NULL);
1206         if (status != I40E_SUCCESS)
1207                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1208
1209 }
1210
1211 static void
1212 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1213 {
1214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1215         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1216         struct i40e_vsi *vsi = pf->main_vsi;
1217         int status;
1218
1219         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1220                                                         false, NULL);
1221         if (status != I40E_SUCCESS)
1222                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1223
1224         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1225                                                         false, NULL);
1226         if (status != I40E_SUCCESS)
1227                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1228 }
1229
1230 static void
1231 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1232 {
1233         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1234         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1235         struct i40e_vsi *vsi = pf->main_vsi;
1236         int ret;
1237
1238         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1239         if (ret != I40E_SUCCESS)
1240                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1241 }
1242
1243 static void
1244 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1245 {
1246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248         struct i40e_vsi *vsi = pf->main_vsi;
1249         int ret;
1250
1251         if (dev->data->promiscuous == 1)
1252                 return; /* must remain in all_multicast mode */
1253
1254         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1255                                 vsi->seid, FALSE, NULL);
1256         if (ret != I40E_SUCCESS)
1257                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1258 }
1259
1260 /*
1261  * Set device link up.
1262  */
1263 static int
1264 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1265 {
1266         /* re-apply link speed setting */
1267         return i40e_apply_link_speed(dev);
1268 }
1269
1270 /*
1271  * Set device link down.
1272  */
1273 static int
1274 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1275 {
1276         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1277         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1278         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1279
1280         return i40e_phy_conf_link(hw, abilities, speed);
1281 }
1282
1283 int
1284 i40e_dev_link_update(struct rte_eth_dev *dev,
1285                      int wait_to_complete)
1286 {
1287 #define CHECK_INTERVAL 100  /* 100ms */
1288 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1289         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1290         struct i40e_link_status link_status;
1291         struct rte_eth_link link, old;
1292         int status;
1293         unsigned rep_cnt = MAX_REPEAT_TIME;
1294
1295         memset(&link, 0, sizeof(link));
1296         memset(&old, 0, sizeof(old));
1297         memset(&link_status, 0, sizeof(link_status));
1298         rte_i40e_dev_atomic_read_link_status(dev, &old);
1299
1300         do {
1301                 /* Get link status information from hardware */
1302                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1303                 if (status != I40E_SUCCESS) {
1304                         link.link_speed = ETH_LINK_SPEED_100;
1305                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1306                         PMD_DRV_LOG(ERR, "Failed to get link info");
1307                         goto out;
1308                 }
1309
1310                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1311                 if (!wait_to_complete)
1312                         break;
1313
1314                 rte_delay_ms(CHECK_INTERVAL);
1315         } while (!link.link_status && rep_cnt--);
1316
1317         if (!link.link_status)
1318                 goto out;
1319
1320         /* i40e uses full duplex only */
1321         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1322
1323         /* Parse the link status */
1324         switch (link_status.link_speed) {
1325         case I40E_LINK_SPEED_100MB:
1326                 link.link_speed = ETH_LINK_SPEED_100;
1327                 break;
1328         case I40E_LINK_SPEED_1GB:
1329                 link.link_speed = ETH_LINK_SPEED_1000;
1330                 break;
1331         case I40E_LINK_SPEED_10GB:
1332                 link.link_speed = ETH_LINK_SPEED_10G;
1333                 break;
1334         case I40E_LINK_SPEED_20GB:
1335                 link.link_speed = ETH_LINK_SPEED_20G;
1336                 break;
1337         case I40E_LINK_SPEED_40GB:
1338                 link.link_speed = ETH_LINK_SPEED_40G;
1339                 break;
1340         default:
1341                 link.link_speed = ETH_LINK_SPEED_100;
1342                 break;
1343         }
1344
1345 out:
1346         rte_i40e_dev_atomic_write_link_status(dev, &link);
1347         if (link.link_status == old.link_status)
1348                 return -1;
1349
1350         return 0;
1351 }
1352
1353 /* Get all the statistics of a VSI */
1354 void
1355 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1356 {
1357         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1358         struct i40e_eth_stats *nes = &vsi->eth_stats;
1359         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1360         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1361
1362         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1363                             vsi->offset_loaded, &oes->rx_bytes,
1364                             &nes->rx_bytes);
1365         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1366                             vsi->offset_loaded, &oes->rx_unicast,
1367                             &nes->rx_unicast);
1368         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1369                             vsi->offset_loaded, &oes->rx_multicast,
1370                             &nes->rx_multicast);
1371         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1372                             vsi->offset_loaded, &oes->rx_broadcast,
1373                             &nes->rx_broadcast);
1374         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1375                             &oes->rx_discards, &nes->rx_discards);
1376         /* GLV_REPC not supported */
1377         /* GLV_RMPC not supported */
1378         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1379                             &oes->rx_unknown_protocol,
1380                             &nes->rx_unknown_protocol);
1381         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1382                             vsi->offset_loaded, &oes->tx_bytes,
1383                             &nes->tx_bytes);
1384         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1385                             vsi->offset_loaded, &oes->tx_unicast,
1386                             &nes->tx_unicast);
1387         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1388                             vsi->offset_loaded, &oes->tx_multicast,
1389                             &nes->tx_multicast);
1390         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1391                             vsi->offset_loaded,  &oes->tx_broadcast,
1392                             &nes->tx_broadcast);
1393         /* GLV_TDPC not supported */
1394         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1395                             &oes->tx_errors, &nes->tx_errors);
1396         vsi->offset_loaded = true;
1397
1398         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1399                     vsi->vsi_id);
1400         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1401         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1402         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1403         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1404         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1405         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1406                     nes->rx_unknown_protocol);
1407         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1408         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1409         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1410         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1411         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1412         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1413         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1414                     vsi->vsi_id);
1415 }
1416
1417 /* Get all statistics of a port */
1418 static void
1419 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1420 {
1421         uint32_t i;
1422         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1423         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1424         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1425         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1426
1427         /* Get statistics of struct i40e_eth_stats */
1428         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1429                             I40E_GLPRT_GORCL(hw->port),
1430                             pf->offset_loaded, &os->eth.rx_bytes,
1431                             &ns->eth.rx_bytes);
1432         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1433                             I40E_GLPRT_UPRCL(hw->port),
1434                             pf->offset_loaded, &os->eth.rx_unicast,
1435                             &ns->eth.rx_unicast);
1436         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1437                             I40E_GLPRT_MPRCL(hw->port),
1438                             pf->offset_loaded, &os->eth.rx_multicast,
1439                             &ns->eth.rx_multicast);
1440         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1441                             I40E_GLPRT_BPRCL(hw->port),
1442                             pf->offset_loaded, &os->eth.rx_broadcast,
1443                             &ns->eth.rx_broadcast);
1444         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1445                             pf->offset_loaded, &os->eth.rx_discards,
1446                             &ns->eth.rx_discards);
1447         /* GLPRT_REPC not supported */
1448         /* GLPRT_RMPC not supported */
1449         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1450                             pf->offset_loaded,
1451                             &os->eth.rx_unknown_protocol,
1452                             &ns->eth.rx_unknown_protocol);
1453         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1454                             I40E_GLPRT_GOTCL(hw->port),
1455                             pf->offset_loaded, &os->eth.tx_bytes,
1456                             &ns->eth.tx_bytes);
1457         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1458                             I40E_GLPRT_UPTCL(hw->port),
1459                             pf->offset_loaded, &os->eth.tx_unicast,
1460                             &ns->eth.tx_unicast);
1461         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1462                             I40E_GLPRT_MPTCL(hw->port),
1463                             pf->offset_loaded, &os->eth.tx_multicast,
1464                             &ns->eth.tx_multicast);
1465         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1466                             I40E_GLPRT_BPTCL(hw->port),
1467                             pf->offset_loaded, &os->eth.tx_broadcast,
1468                             &ns->eth.tx_broadcast);
1469         /* GLPRT_TEPC not supported */
1470
1471         /* additional port specific stats */
1472         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1473                             pf->offset_loaded, &os->tx_dropped_link_down,
1474                             &ns->tx_dropped_link_down);
1475         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1476                             pf->offset_loaded, &os->crc_errors,
1477                             &ns->crc_errors);
1478         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1479                             pf->offset_loaded, &os->illegal_bytes,
1480                             &ns->illegal_bytes);
1481         /* GLPRT_ERRBC not supported */
1482         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1483                             pf->offset_loaded, &os->mac_local_faults,
1484                             &ns->mac_local_faults);
1485         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1486                             pf->offset_loaded, &os->mac_remote_faults,
1487                             &ns->mac_remote_faults);
1488         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1489                             pf->offset_loaded, &os->rx_length_errors,
1490                             &ns->rx_length_errors);
1491         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1492                             pf->offset_loaded, &os->link_xon_rx,
1493                             &ns->link_xon_rx);
1494         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1495                             pf->offset_loaded, &os->link_xoff_rx,
1496                             &ns->link_xoff_rx);
1497         for (i = 0; i < 8; i++) {
1498                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1499                                     pf->offset_loaded,
1500                                     &os->priority_xon_rx[i],
1501                                     &ns->priority_xon_rx[i]);
1502                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1503                                     pf->offset_loaded,
1504                                     &os->priority_xoff_rx[i],
1505                                     &ns->priority_xoff_rx[i]);
1506         }
1507         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1508                             pf->offset_loaded, &os->link_xon_tx,
1509                             &ns->link_xon_tx);
1510         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1511                             pf->offset_loaded, &os->link_xoff_tx,
1512                             &ns->link_xoff_tx);
1513         for (i = 0; i < 8; i++) {
1514                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1515                                     pf->offset_loaded,
1516                                     &os->priority_xon_tx[i],
1517                                     &ns->priority_xon_tx[i]);
1518                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1519                                     pf->offset_loaded,
1520                                     &os->priority_xoff_tx[i],
1521                                     &ns->priority_xoff_tx[i]);
1522                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1523                                     pf->offset_loaded,
1524                                     &os->priority_xon_2_xoff[i],
1525                                     &ns->priority_xon_2_xoff[i]);
1526         }
1527         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1528                             I40E_GLPRT_PRC64L(hw->port),
1529                             pf->offset_loaded, &os->rx_size_64,
1530                             &ns->rx_size_64);
1531         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1532                             I40E_GLPRT_PRC127L(hw->port),
1533                             pf->offset_loaded, &os->rx_size_127,
1534                             &ns->rx_size_127);
1535         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1536                             I40E_GLPRT_PRC255L(hw->port),
1537                             pf->offset_loaded, &os->rx_size_255,
1538                             &ns->rx_size_255);
1539         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1540                             I40E_GLPRT_PRC511L(hw->port),
1541                             pf->offset_loaded, &os->rx_size_511,
1542                             &ns->rx_size_511);
1543         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1544                             I40E_GLPRT_PRC1023L(hw->port),
1545                             pf->offset_loaded, &os->rx_size_1023,
1546                             &ns->rx_size_1023);
1547         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1548                             I40E_GLPRT_PRC1522L(hw->port),
1549                             pf->offset_loaded, &os->rx_size_1522,
1550                             &ns->rx_size_1522);
1551         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1552                             I40E_GLPRT_PRC9522L(hw->port),
1553                             pf->offset_loaded, &os->rx_size_big,
1554                             &ns->rx_size_big);
1555         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1556                             pf->offset_loaded, &os->rx_undersize,
1557                             &ns->rx_undersize);
1558         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1559                             pf->offset_loaded, &os->rx_fragments,
1560                             &ns->rx_fragments);
1561         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1562                             pf->offset_loaded, &os->rx_oversize,
1563                             &ns->rx_oversize);
1564         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1565                             pf->offset_loaded, &os->rx_jabber,
1566                             &ns->rx_jabber);
1567         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1568                             I40E_GLPRT_PTC64L(hw->port),
1569                             pf->offset_loaded, &os->tx_size_64,
1570                             &ns->tx_size_64);
1571         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1572                             I40E_GLPRT_PTC127L(hw->port),
1573                             pf->offset_loaded, &os->tx_size_127,
1574                             &ns->tx_size_127);
1575         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1576                             I40E_GLPRT_PTC255L(hw->port),
1577                             pf->offset_loaded, &os->tx_size_255,
1578                             &ns->tx_size_255);
1579         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1580                             I40E_GLPRT_PTC511L(hw->port),
1581                             pf->offset_loaded, &os->tx_size_511,
1582                             &ns->tx_size_511);
1583         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1584                             I40E_GLPRT_PTC1023L(hw->port),
1585                             pf->offset_loaded, &os->tx_size_1023,
1586                             &ns->tx_size_1023);
1587         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1588                             I40E_GLPRT_PTC1522L(hw->port),
1589                             pf->offset_loaded, &os->tx_size_1522,
1590                             &ns->tx_size_1522);
1591         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1592                             I40E_GLPRT_PTC9522L(hw->port),
1593                             pf->offset_loaded, &os->tx_size_big,
1594                             &ns->tx_size_big);
1595         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1596                            pf->offset_loaded,
1597                            &os->fd_sb_match, &ns->fd_sb_match);
1598         /* GLPRT_MSPDC not supported */
1599         /* GLPRT_XEC not supported */
1600
1601         pf->offset_loaded = true;
1602
1603         if (pf->main_vsi)
1604                 i40e_update_vsi_stats(pf->main_vsi);
1605
1606         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1607                                                 ns->eth.rx_broadcast;
1608         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1609                                                 ns->eth.tx_broadcast;
1610         stats->ibytes   = ns->eth.rx_bytes;
1611         stats->obytes   = ns->eth.tx_bytes;
1612         stats->oerrors  = ns->eth.tx_errors;
1613         stats->imcasts  = ns->eth.rx_multicast;
1614         stats->fdirmatch = ns->fd_sb_match;
1615
1616         /* Rx Errors */
1617         stats->ibadcrc  = ns->crc_errors;
1618         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1619                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1620         stats->imissed  = ns->eth.rx_discards;
1621         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1622
1623         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1624         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1625         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1626         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1627         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1628         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1629         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1630                     ns->eth.rx_unknown_protocol);
1631         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1632         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1633         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1634         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1635         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1636         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1637
1638         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1639                     ns->tx_dropped_link_down);
1640         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1641         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1642                     ns->illegal_bytes);
1643         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1644         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1645                     ns->mac_local_faults);
1646         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1647                     ns->mac_remote_faults);
1648         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1649                     ns->rx_length_errors);
1650         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1651         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1652         for (i = 0; i < 8; i++) {
1653                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1654                                 i, ns->priority_xon_rx[i]);
1655                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1656                                 i, ns->priority_xoff_rx[i]);
1657         }
1658         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1659         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1660         for (i = 0; i < 8; i++) {
1661                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1662                                 i, ns->priority_xon_tx[i]);
1663                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1664                                 i, ns->priority_xoff_tx[i]);
1665                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1666                                 i, ns->priority_xon_2_xoff[i]);
1667         }
1668         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1669         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1670         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1671         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1672         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1673         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1674         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1675         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1676         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1677         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1678         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1679         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1680         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1681         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1682         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1683         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1684         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1685         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1686         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1687                         ns->mac_short_packet_dropped);
1688         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1689                     ns->checksum_error);
1690         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1691         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1692 }
1693
1694 /* Reset the statistics */
1695 static void
1696 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1697 {
1698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699
1700         /* It results in reloading the start point of each counter */
1701         pf->offset_loaded = false;
1702 }
1703
1704 static int
1705 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1706                                  __rte_unused uint16_t queue_id,
1707                                  __rte_unused uint8_t stat_idx,
1708                                  __rte_unused uint8_t is_rx)
1709 {
1710         PMD_INIT_FUNC_TRACE();
1711
1712         return -ENOSYS;
1713 }
1714
1715 static void
1716 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1717 {
1718         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1719         struct i40e_vsi *vsi = pf->main_vsi;
1720
1721         dev_info->max_rx_queues = vsi->nb_qps;
1722         dev_info->max_tx_queues = vsi->nb_qps;
1723         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1724         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1725         dev_info->max_mac_addrs = vsi->max_macaddrs;
1726         dev_info->max_vfs = dev->pci_dev->max_vfs;
1727         dev_info->rx_offload_capa =
1728                 DEV_RX_OFFLOAD_VLAN_STRIP |
1729                 DEV_RX_OFFLOAD_QINQ_STRIP |
1730                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1731                 DEV_RX_OFFLOAD_UDP_CKSUM |
1732                 DEV_RX_OFFLOAD_TCP_CKSUM;
1733         dev_info->tx_offload_capa =
1734                 DEV_TX_OFFLOAD_VLAN_INSERT |
1735                 DEV_TX_OFFLOAD_QINQ_INSERT |
1736                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1737                 DEV_TX_OFFLOAD_UDP_CKSUM |
1738                 DEV_TX_OFFLOAD_TCP_CKSUM |
1739                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1740                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1741                 DEV_TX_OFFLOAD_TCP_TSO;
1742         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1743                                                 sizeof(uint32_t);
1744         dev_info->reta_size = pf->hash_lut_size;
1745         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1746
1747         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1748                 .rx_thresh = {
1749                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1750                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1751                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1752                 },
1753                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1754                 .rx_drop_en = 0,
1755         };
1756
1757         dev_info->default_txconf = (struct rte_eth_txconf) {
1758                 .tx_thresh = {
1759                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1760                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1761                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1762                 },
1763                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1764                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1765                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1766                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1767         };
1768
1769         if (pf->flags & I40E_FLAG_VMDQ) {
1770                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1771                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1772                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1773                                                 pf->max_nb_vmdq_vsi;
1774                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1775                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1776                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1777         }
1778 }
1779
1780 static int
1781 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1782 {
1783         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1784         struct i40e_vsi *vsi = pf->main_vsi;
1785         PMD_INIT_FUNC_TRACE();
1786
1787         if (on)
1788                 return i40e_vsi_add_vlan(vsi, vlan_id);
1789         else
1790                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1791 }
1792
1793 static void
1794 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1795                    __rte_unused uint16_t tpid)
1796 {
1797         PMD_INIT_FUNC_TRACE();
1798 }
1799
1800 static void
1801 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1802 {
1803         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1804         struct i40e_vsi *vsi = pf->main_vsi;
1805
1806         if (mask & ETH_VLAN_STRIP_MASK) {
1807                 /* Enable or disable VLAN stripping */
1808                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1809                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1810                 else
1811                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1812         }
1813
1814         if (mask & ETH_VLAN_EXTEND_MASK) {
1815                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1816                         i40e_vsi_config_double_vlan(vsi, TRUE);
1817                 else
1818                         i40e_vsi_config_double_vlan(vsi, FALSE);
1819         }
1820 }
1821
1822 static void
1823 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1824                           __rte_unused uint16_t queue,
1825                           __rte_unused int on)
1826 {
1827         PMD_INIT_FUNC_TRACE();
1828 }
1829
1830 static int
1831 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1832 {
1833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1834         struct i40e_vsi *vsi = pf->main_vsi;
1835         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1836         struct i40e_vsi_vlan_pvid_info info;
1837
1838         memset(&info, 0, sizeof(info));
1839         info.on = on;
1840         if (info.on)
1841                 info.config.pvid = pvid;
1842         else {
1843                 info.config.reject.tagged =
1844                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1845                 info.config.reject.untagged =
1846                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1847         }
1848
1849         return i40e_vsi_vlan_pvid_set(vsi, &info);
1850 }
1851
1852 static int
1853 i40e_dev_led_on(struct rte_eth_dev *dev)
1854 {
1855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856         uint32_t mode = i40e_led_get(hw);
1857
1858         if (mode == 0)
1859                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1860
1861         return 0;
1862 }
1863
1864 static int
1865 i40e_dev_led_off(struct rte_eth_dev *dev)
1866 {
1867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868         uint32_t mode = i40e_led_get(hw);
1869
1870         if (mode != 0)
1871                 i40e_led_set(hw, 0, false);
1872
1873         return 0;
1874 }
1875
1876 static int
1877 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1878 {
1879         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1880         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1881
1882         fc_conf->pause_time = pf->fc_conf.pause_time;
1883         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
1884         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
1885
1886          /* Return current mode according to actual setting*/
1887         switch (hw->fc.current_mode) {
1888         case I40E_FC_FULL:
1889                 fc_conf->mode = RTE_FC_FULL;
1890                 break;
1891         case I40E_FC_TX_PAUSE:
1892                 fc_conf->mode = RTE_FC_TX_PAUSE;
1893                 break;
1894         case I40E_FC_RX_PAUSE:
1895                 fc_conf->mode = RTE_FC_RX_PAUSE;
1896                 break;
1897         case I40E_FC_NONE:
1898         default:
1899                 fc_conf->mode = RTE_FC_NONE;
1900         };
1901
1902         return 0;
1903 }
1904
1905 static int
1906 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1907 {
1908         uint32_t mflcn_reg, fctrl_reg, reg;
1909         uint32_t max_high_water;
1910         uint8_t i, aq_failure;
1911         int err;
1912         struct i40e_hw *hw;
1913         struct i40e_pf *pf;
1914         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
1915                 [RTE_FC_NONE] = I40E_FC_NONE,
1916                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
1917                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
1918                 [RTE_FC_FULL] = I40E_FC_FULL
1919         };
1920
1921         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
1922
1923         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
1924         if ((fc_conf->high_water > max_high_water) ||
1925                         (fc_conf->high_water < fc_conf->low_water)) {
1926                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
1927                         "High_water must <= %d.", max_high_water);
1928                 return -EINVAL;
1929         }
1930
1931         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1932         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1933         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
1934
1935         pf->fc_conf.pause_time = fc_conf->pause_time;
1936         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
1937         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
1938
1939         PMD_INIT_FUNC_TRACE();
1940
1941         /* All the link flow control related enable/disable register
1942          * configuration is handle by the F/W
1943          */
1944         err = i40e_set_fc(hw, &aq_failure, true);
1945         if (err < 0)
1946                 return -ENOSYS;
1947
1948         if (i40e_is_40G_device(hw->device_id)) {
1949                 /* Configure flow control refresh threshold,
1950                  * the value for stat_tx_pause_refresh_timer[8]
1951                  * is used for global pause operation.
1952                  */
1953
1954                 I40E_WRITE_REG(hw,
1955                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
1956                                pf->fc_conf.pause_time);
1957
1958                 /* configure the timer value included in transmitted pause
1959                  * frame,
1960                  * the value for stat_tx_pause_quanta[8] is used for global
1961                  * pause operation
1962                  */
1963                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
1964                                pf->fc_conf.pause_time);
1965
1966                 fctrl_reg = I40E_READ_REG(hw,
1967                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
1968
1969                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1970                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
1971                 else
1972                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
1973
1974                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
1975                                fctrl_reg);
1976         } else {
1977                 /* Configure pause time (2 TCs per register) */
1978                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
1979                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
1980                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
1981
1982                 /* Configure flow control refresh threshold value */
1983                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
1984                                pf->fc_conf.pause_time / 2);
1985
1986                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
1987
1988                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
1989                  *depending on configuration
1990                  */
1991                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
1992                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
1993                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
1994                 } else {
1995                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
1996                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
1997                 }
1998
1999                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2000         }
2001
2002         /* config the water marker both based on the packets and bytes */
2003         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2004                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2005                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2006         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2007                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2008                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2009         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2010                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2011                        << I40E_KILOSHIFT);
2012         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2013                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2014                        << I40E_KILOSHIFT);
2015
2016         I40E_WRITE_FLUSH(hw);
2017
2018         return 0;
2019 }
2020
2021 static int
2022 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2023                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2024 {
2025         PMD_INIT_FUNC_TRACE();
2026
2027         return -ENOSYS;
2028 }
2029
2030 /* Add a MAC address, and update filters */
2031 static void
2032 i40e_macaddr_add(struct rte_eth_dev *dev,
2033                  struct ether_addr *mac_addr,
2034                  __rte_unused uint32_t index,
2035                  uint32_t pool)
2036 {
2037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2038         struct i40e_mac_filter_info mac_filter;
2039         struct i40e_vsi *vsi;
2040         int ret;
2041
2042         /* If VMDQ not enabled or configured, return */
2043         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2044                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2045                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2046                         pool);
2047                 return;
2048         }
2049
2050         if (pool > pf->nb_cfg_vmdq_vsi) {
2051                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2052                                 pool, pf->nb_cfg_vmdq_vsi);
2053                 return;
2054         }
2055
2056         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2057         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2058
2059         if (pool == 0)
2060                 vsi = pf->main_vsi;
2061         else
2062                 vsi = pf->vmdq[pool - 1].vsi;
2063
2064         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2065         if (ret != I40E_SUCCESS) {
2066                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2067                 return;
2068         }
2069 }
2070
2071 /* Remove a MAC address, and update filters */
2072 static void
2073 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2074 {
2075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2076         struct i40e_vsi *vsi;
2077         struct rte_eth_dev_data *data = dev->data;
2078         struct ether_addr *macaddr;
2079         int ret;
2080         uint32_t i;
2081         uint64_t pool_sel;
2082
2083         macaddr = &(data->mac_addrs[index]);
2084
2085         pool_sel = dev->data->mac_pool_sel[index];
2086
2087         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2088                 if (pool_sel & (1ULL << i)) {
2089                         if (i == 0)
2090                                 vsi = pf->main_vsi;
2091                         else {
2092                                 /* No VMDQ pool enabled or configured */
2093                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2094                                         (i > pf->nb_cfg_vmdq_vsi)) {
2095                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2096                                                         "/configured");
2097                                         return;
2098                                 }
2099                                 vsi = pf->vmdq[i - 1].vsi;
2100                         }
2101                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2102
2103                         if (ret) {
2104                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2105                                 return;
2106                         }
2107                 }
2108         }
2109 }
2110
2111 /* Set perfect match or hash match of MAC and VLAN for a VF */
2112 static int
2113 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2114                  struct rte_eth_mac_filter *filter,
2115                  bool add)
2116 {
2117         struct i40e_hw *hw;
2118         struct i40e_mac_filter_info mac_filter;
2119         struct ether_addr old_mac;
2120         struct ether_addr *new_mac;
2121         struct i40e_pf_vf *vf = NULL;
2122         uint16_t vf_id;
2123         int ret;
2124
2125         if (pf == NULL) {
2126                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2127                 return -EINVAL;
2128         }
2129         hw = I40E_PF_TO_HW(pf);
2130
2131         if (filter == NULL) {
2132                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2133                 return -EINVAL;
2134         }
2135
2136         new_mac = &filter->mac_addr;
2137
2138         if (is_zero_ether_addr(new_mac)) {
2139                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2140                 return -EINVAL;
2141         }
2142
2143         vf_id = filter->dst_id;
2144
2145         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2146                 PMD_DRV_LOG(ERR, "Invalid argument.");
2147                 return -EINVAL;
2148         }
2149         vf = &pf->vfs[vf_id];
2150
2151         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2152                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2153                 return -EINVAL;
2154         }
2155
2156         if (add) {
2157                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2158                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2159                                 ETHER_ADDR_LEN);
2160                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2161                                  ETHER_ADDR_LEN);
2162
2163                 mac_filter.filter_type = filter->filter_type;
2164                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2165                 if (ret != I40E_SUCCESS) {
2166                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2167                         return -1;
2168                 }
2169                 ether_addr_copy(new_mac, &pf->dev_addr);
2170         } else {
2171                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2172                                 ETHER_ADDR_LEN);
2173                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2174                 if (ret != I40E_SUCCESS) {
2175                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2176                         return -1;
2177                 }
2178
2179                 /* Clear device address as it has been removed */
2180                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2181                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2182         }
2183
2184         return 0;
2185 }
2186
2187 /* MAC filter handle */
2188 static int
2189 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2190                 void *arg)
2191 {
2192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193         struct rte_eth_mac_filter *filter;
2194         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2195         int ret = I40E_NOT_SUPPORTED;
2196
2197         filter = (struct rte_eth_mac_filter *)(arg);
2198
2199         switch (filter_op) {
2200         case RTE_ETH_FILTER_NOP:
2201                 ret = I40E_SUCCESS;
2202                 break;
2203         case RTE_ETH_FILTER_ADD:
2204                 i40e_pf_disable_irq0(hw);
2205                 if (filter->is_vf)
2206                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2207                 i40e_pf_enable_irq0(hw);
2208                 break;
2209         case RTE_ETH_FILTER_DELETE:
2210                 i40e_pf_disable_irq0(hw);
2211                 if (filter->is_vf)
2212                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2213                 i40e_pf_enable_irq0(hw);
2214                 break;
2215         default:
2216                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2217                 ret = I40E_ERR_PARAM;
2218                 break;
2219         }
2220
2221         return ret;
2222 }
2223
2224 static int
2225 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2226                          struct rte_eth_rss_reta_entry64 *reta_conf,
2227                          uint16_t reta_size)
2228 {
2229         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2230         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2231         uint32_t lut, l;
2232         uint16_t i, j, lut_size = pf->hash_lut_size;
2233         uint16_t idx, shift;
2234         uint8_t mask;
2235
2236         if (reta_size != lut_size ||
2237                 reta_size > ETH_RSS_RETA_SIZE_512) {
2238                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2239                         "(%d) doesn't match the number hardware can supported "
2240                                         "(%d)\n", reta_size, lut_size);
2241                 return -EINVAL;
2242         }
2243
2244         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2245                 idx = i / RTE_RETA_GROUP_SIZE;
2246                 shift = i % RTE_RETA_GROUP_SIZE;
2247                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2248                                                 I40E_4_BIT_MASK);
2249                 if (!mask)
2250                         continue;
2251                 if (mask == I40E_4_BIT_MASK)
2252                         l = 0;
2253                 else
2254                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2255                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2256                         if (mask & (0x1 << j))
2257                                 lut |= reta_conf[idx].reta[shift + j] <<
2258                                                         (CHAR_BIT * j);
2259                         else
2260                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2261                 }
2262                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2263         }
2264
2265         return 0;
2266 }
2267
2268 static int
2269 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2270                         struct rte_eth_rss_reta_entry64 *reta_conf,
2271                         uint16_t reta_size)
2272 {
2273         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2274         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275         uint32_t lut;
2276         uint16_t i, j, lut_size = pf->hash_lut_size;
2277         uint16_t idx, shift;
2278         uint8_t mask;
2279
2280         if (reta_size != lut_size ||
2281                 reta_size > ETH_RSS_RETA_SIZE_512) {
2282                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2283                         "(%d) doesn't match the number hardware can supported "
2284                                         "(%d)\n", reta_size, lut_size);
2285                 return -EINVAL;
2286         }
2287
2288         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2289                 idx = i / RTE_RETA_GROUP_SIZE;
2290                 shift = i % RTE_RETA_GROUP_SIZE;
2291                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2292                                                 I40E_4_BIT_MASK);
2293                 if (!mask)
2294                         continue;
2295
2296                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2297                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2298                         if (mask & (0x1 << j))
2299                                 reta_conf[idx].reta[shift + j] = ((lut >>
2300                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2301                 }
2302         }
2303
2304         return 0;
2305 }
2306
2307 /**
2308  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2309  * @hw:   pointer to the HW structure
2310  * @mem:  pointer to mem struct to fill out
2311  * @size: size of memory requested
2312  * @alignment: what to align the allocation to
2313  **/
2314 enum i40e_status_code
2315 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2316                         struct i40e_dma_mem *mem,
2317                         u64 size,
2318                         u32 alignment)
2319 {
2320         static uint64_t id = 0;
2321         const struct rte_memzone *mz = NULL;
2322         char z_name[RTE_MEMZONE_NAMESIZE];
2323
2324         if (!mem)
2325                 return I40E_ERR_PARAM;
2326
2327         id++;
2328         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2329 #ifdef RTE_LIBRTE_XEN_DOM0
2330         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2331                                          alignment, RTE_PGSIZE_2M);
2332 #else
2333         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2334                                          alignment);
2335 #endif
2336         if (!mz)
2337                 return I40E_ERR_NO_MEMORY;
2338
2339         mem->id = id;
2340         mem->size = size;
2341         mem->va = mz->addr;
2342 #ifdef RTE_LIBRTE_XEN_DOM0
2343         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2344 #else
2345         mem->pa = mz->phys_addr;
2346 #endif
2347
2348         return I40E_SUCCESS;
2349 }
2350
2351 /**
2352  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2353  * @hw:   pointer to the HW structure
2354  * @mem:  ptr to mem struct to free
2355  **/
2356 enum i40e_status_code
2357 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2358                     struct i40e_dma_mem *mem)
2359 {
2360         if (!mem || !mem->va)
2361                 return I40E_ERR_PARAM;
2362
2363         mem->va = NULL;
2364         mem->pa = (u64)0;
2365
2366         return I40E_SUCCESS;
2367 }
2368
2369 /**
2370  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2371  * @hw:   pointer to the HW structure
2372  * @mem:  pointer to mem struct to fill out
2373  * @size: size of memory requested
2374  **/
2375 enum i40e_status_code
2376 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2377                          struct i40e_virt_mem *mem,
2378                          u32 size)
2379 {
2380         if (!mem)
2381                 return I40E_ERR_PARAM;
2382
2383         mem->size = size;
2384         mem->va = rte_zmalloc("i40e", size, 0);
2385
2386         if (mem->va)
2387                 return I40E_SUCCESS;
2388         else
2389                 return I40E_ERR_NO_MEMORY;
2390 }
2391
2392 /**
2393  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2394  * @hw:   pointer to the HW structure
2395  * @mem:  pointer to mem struct to free
2396  **/
2397 enum i40e_status_code
2398 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2399                      struct i40e_virt_mem *mem)
2400 {
2401         if (!mem)
2402                 return I40E_ERR_PARAM;
2403
2404         rte_free(mem->va);
2405         mem->va = NULL;
2406
2407         return I40E_SUCCESS;
2408 }
2409
2410 void
2411 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2412 {
2413         rte_spinlock_init(&sp->spinlock);
2414 }
2415
2416 void
2417 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2418 {
2419         rte_spinlock_lock(&sp->spinlock);
2420 }
2421
2422 void
2423 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2424 {
2425         rte_spinlock_unlock(&sp->spinlock);
2426 }
2427
2428 void
2429 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2430 {
2431         return;
2432 }
2433
2434 /**
2435  * Get the hardware capabilities, which will be parsed
2436  * and saved into struct i40e_hw.
2437  */
2438 static int
2439 i40e_get_cap(struct i40e_hw *hw)
2440 {
2441         struct i40e_aqc_list_capabilities_element_resp *buf;
2442         uint16_t len, size = 0;
2443         int ret;
2444
2445         /* Calculate a huge enough buff for saving response data temporarily */
2446         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2447                                                 I40E_MAX_CAP_ELE_NUM;
2448         buf = rte_zmalloc("i40e", len, 0);
2449         if (!buf) {
2450                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2451                 return I40E_ERR_NO_MEMORY;
2452         }
2453
2454         /* Get, parse the capabilities and save it to hw */
2455         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2456                         i40e_aqc_opc_list_func_capabilities, NULL);
2457         if (ret != I40E_SUCCESS)
2458                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2459
2460         /* Free the temporary buffer after being used */
2461         rte_free(buf);
2462
2463         return ret;
2464 }
2465
2466 static int
2467 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2468 {
2469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2471         uint16_t sum_queues = 0, sum_vsis, left_queues;
2472
2473         /* First check if FW support SRIOV */
2474         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2475                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2476                 return -EINVAL;
2477         }
2478         /* Add the parameter init for LFC */
2479         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2480         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2481         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2482
2483         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2484         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2485         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2486         /* Allocate queues for pf */
2487         if (hw->func_caps.rss) {
2488                 pf->flags |= I40E_FLAG_RSS;
2489                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2490                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2491                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2492         } else
2493                 pf->lan_nb_qps = 1;
2494         sum_queues = pf->lan_nb_qps;
2495         /* Default VSI is not counted in */
2496         sum_vsis = 0;
2497         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2498
2499         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2500                 pf->flags |= I40E_FLAG_SRIOV;
2501                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2502                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2503                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2504                                      "max supported %u.",
2505                                      dev->pci_dev->max_vfs,
2506                                      hw->func_caps.num_vfs);
2507                         return -EINVAL;
2508                 }
2509                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2510                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2511                                      "max support %u queues.",
2512                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2513                         return -EINVAL;
2514                 }
2515                 pf->vf_num = dev->pci_dev->max_vfs;
2516                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2517                 sum_vsis   += pf->vf_num;
2518                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2519                              pf->vf_num, pf->vf_nb_qps);
2520         } else
2521                 pf->vf_num = 0;
2522
2523         if (hw->func_caps.vmdq) {
2524                 pf->flags |= I40E_FLAG_VMDQ;
2525                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2526                 pf->max_nb_vmdq_vsi = 1;
2527                 /*
2528                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2529                  * later.
2530                  */
2531                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2532                 sum_vsis += pf->max_nb_vmdq_vsi;
2533         } else {
2534                 pf->vmdq_nb_qps = 0;
2535                 pf->max_nb_vmdq_vsi = 0;
2536         }
2537         pf->nb_cfg_vmdq_vsi = 0;
2538
2539         if (hw->func_caps.fd) {
2540                 pf->flags |= I40E_FLAG_FDIR;
2541                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2542                 /**
2543                  * Each flow director consumes one VSI and one queue,
2544                  * but can't calculate out predictably here.
2545                  */
2546         }
2547
2548         if (hw->func_caps.dcb)
2549                 pf->flags |= I40E_FLAG_DCB;
2550
2551         if (sum_vsis > pf->max_num_vsi ||
2552                 sum_queues > hw->func_caps.num_rx_qp) {
2553                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2554                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2555                              pf->max_num_vsi, sum_vsis);
2556                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2557                              hw->func_caps.num_rx_qp, sum_queues);
2558                 return -EINVAL;
2559         }
2560
2561         /* Adjust VMDQ setting to support as many VMs as possible */
2562         if (pf->flags & I40E_FLAG_VMDQ) {
2563                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2564
2565                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2566                                         pf->max_num_vsi - sum_vsis);
2567
2568                 /* Limit the max VMDQ number that rte_ether that can support  */
2569                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2570                                         ETH_64_POOLS - 1);
2571
2572                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2573                                 pf->max_nb_vmdq_vsi);
2574                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2575         }
2576
2577         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2578          * cause */
2579         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2580                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2581                              sum_vsis, hw->func_caps.num_msix_vectors);
2582                 return -EINVAL;
2583         }
2584         return I40E_SUCCESS;
2585 }
2586
2587 static int
2588 i40e_pf_get_switch_config(struct i40e_pf *pf)
2589 {
2590         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2591         struct i40e_aqc_get_switch_config_resp *switch_config;
2592         struct i40e_aqc_switch_config_element_resp *element;
2593         uint16_t start_seid = 0, num_reported;
2594         int ret;
2595
2596         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2597                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2598         if (!switch_config) {
2599                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2600                 return -ENOMEM;
2601         }
2602
2603         /* Get the switch configurations */
2604         ret = i40e_aq_get_switch_config(hw, switch_config,
2605                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2606         if (ret != I40E_SUCCESS) {
2607                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2608                 goto fail;
2609         }
2610         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2611         if (num_reported != 1) { /* The number should be 1 */
2612                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2613                 goto fail;
2614         }
2615
2616         /* Parse the switch configuration elements */
2617         element = &(switch_config->element[0]);
2618         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2619                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2620                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2621         } else
2622                 PMD_DRV_LOG(INFO, "Unknown element type");
2623
2624 fail:
2625         rte_free(switch_config);
2626
2627         return ret;
2628 }
2629
2630 static int
2631 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2632                         uint32_t num)
2633 {
2634         struct pool_entry *entry;
2635
2636         if (pool == NULL || num == 0)
2637                 return -EINVAL;
2638
2639         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2640         if (entry == NULL) {
2641                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2642                 return -ENOMEM;
2643         }
2644
2645         /* queue heap initialize */
2646         pool->num_free = num;
2647         pool->num_alloc = 0;
2648         pool->base = base;
2649         LIST_INIT(&pool->alloc_list);
2650         LIST_INIT(&pool->free_list);
2651
2652         /* Initialize element  */
2653         entry->base = 0;
2654         entry->len = num;
2655
2656         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2657         return 0;
2658 }
2659
2660 static void
2661 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2662 {
2663         struct pool_entry *entry;
2664
2665         if (pool == NULL)
2666                 return;
2667
2668         LIST_FOREACH(entry, &pool->alloc_list, next) {
2669                 LIST_REMOVE(entry, next);
2670                 rte_free(entry);
2671         }
2672
2673         LIST_FOREACH(entry, &pool->free_list, next) {
2674                 LIST_REMOVE(entry, next);
2675                 rte_free(entry);
2676         }
2677
2678         pool->num_free = 0;
2679         pool->num_alloc = 0;
2680         pool->base = 0;
2681         LIST_INIT(&pool->alloc_list);
2682         LIST_INIT(&pool->free_list);
2683 }
2684
2685 static int
2686 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2687                        uint32_t base)
2688 {
2689         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2690         uint32_t pool_offset;
2691         int insert;
2692
2693         if (pool == NULL) {
2694                 PMD_DRV_LOG(ERR, "Invalid parameter");
2695                 return -EINVAL;
2696         }
2697
2698         pool_offset = base - pool->base;
2699         /* Lookup in alloc list */
2700         LIST_FOREACH(entry, &pool->alloc_list, next) {
2701                 if (entry->base == pool_offset) {
2702                         valid_entry = entry;
2703                         LIST_REMOVE(entry, next);
2704                         break;
2705                 }
2706         }
2707
2708         /* Not find, return */
2709         if (valid_entry == NULL) {
2710                 PMD_DRV_LOG(ERR, "Failed to find entry");
2711                 return -EINVAL;
2712         }
2713
2714         /**
2715          * Found it, move it to free list  and try to merge.
2716          * In order to make merge easier, always sort it by qbase.
2717          * Find adjacent prev and last entries.
2718          */
2719         prev = next = NULL;
2720         LIST_FOREACH(entry, &pool->free_list, next) {
2721                 if (entry->base > valid_entry->base) {
2722                         next = entry;
2723                         break;
2724                 }
2725                 prev = entry;
2726         }
2727
2728         insert = 0;
2729         /* Try to merge with next one*/
2730         if (next != NULL) {
2731                 /* Merge with next one */
2732                 if (valid_entry->base + valid_entry->len == next->base) {
2733                         next->base = valid_entry->base;
2734                         next->len += valid_entry->len;
2735                         rte_free(valid_entry);
2736                         valid_entry = next;
2737                         insert = 1;
2738                 }
2739         }
2740
2741         if (prev != NULL) {
2742                 /* Merge with previous one */
2743                 if (prev->base + prev->len == valid_entry->base) {
2744                         prev->len += valid_entry->len;
2745                         /* If it merge with next one, remove next node */
2746                         if (insert == 1) {
2747                                 LIST_REMOVE(valid_entry, next);
2748                                 rte_free(valid_entry);
2749                         } else {
2750                                 rte_free(valid_entry);
2751                                 insert = 1;
2752                         }
2753                 }
2754         }
2755
2756         /* Not find any entry to merge, insert */
2757         if (insert == 0) {
2758                 if (prev != NULL)
2759                         LIST_INSERT_AFTER(prev, valid_entry, next);
2760                 else if (next != NULL)
2761                         LIST_INSERT_BEFORE(next, valid_entry, next);
2762                 else /* It's empty list, insert to head */
2763                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2764         }
2765
2766         pool->num_free += valid_entry->len;
2767         pool->num_alloc -= valid_entry->len;
2768
2769         return 0;
2770 }
2771
2772 static int
2773 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2774                        uint16_t num)
2775 {
2776         struct pool_entry *entry, *valid_entry;
2777
2778         if (pool == NULL || num == 0) {
2779                 PMD_DRV_LOG(ERR, "Invalid parameter");
2780                 return -EINVAL;
2781         }
2782
2783         if (pool->num_free < num) {
2784                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2785                             num, pool->num_free);
2786                 return -ENOMEM;
2787         }
2788
2789         valid_entry = NULL;
2790         /* Lookup  in free list and find most fit one */
2791         LIST_FOREACH(entry, &pool->free_list, next) {
2792                 if (entry->len >= num) {
2793                         /* Find best one */
2794                         if (entry->len == num) {
2795                                 valid_entry = entry;
2796                                 break;
2797                         }
2798                         if (valid_entry == NULL || valid_entry->len > entry->len)
2799                                 valid_entry = entry;
2800                 }
2801         }
2802
2803         /* Not find one to satisfy the request, return */
2804         if (valid_entry == NULL) {
2805                 PMD_DRV_LOG(ERR, "No valid entry found");
2806                 return -ENOMEM;
2807         }
2808         /**
2809          * The entry have equal queue number as requested,
2810          * remove it from alloc_list.
2811          */
2812         if (valid_entry->len == num) {
2813                 LIST_REMOVE(valid_entry, next);
2814         } else {
2815                 /**
2816                  * The entry have more numbers than requested,
2817                  * create a new entry for alloc_list and minus its
2818                  * queue base and number in free_list.
2819                  */
2820                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2821                 if (entry == NULL) {
2822                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2823                                     "resource pool");
2824                         return -ENOMEM;
2825                 }
2826                 entry->base = valid_entry->base;
2827                 entry->len = num;
2828                 valid_entry->base += num;
2829                 valid_entry->len -= num;
2830                 valid_entry = entry;
2831         }
2832
2833         /* Insert it into alloc list, not sorted */
2834         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2835
2836         pool->num_free -= valid_entry->len;
2837         pool->num_alloc += valid_entry->len;
2838
2839         return (valid_entry->base + pool->base);
2840 }
2841
2842 /**
2843  * bitmap_is_subset - Check whether src2 is subset of src1
2844  **/
2845 static inline int
2846 bitmap_is_subset(uint8_t src1, uint8_t src2)
2847 {
2848         return !((src1 ^ src2) & src2);
2849 }
2850
2851 static int
2852 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2853 {
2854         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2855
2856         /* If DCB is not supported, only default TC is supported */
2857         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2858                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2859                 return -EINVAL;
2860         }
2861
2862         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2863                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2864                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2865                             enabled_tcmap);
2866                 return -EINVAL;
2867         }
2868         return I40E_SUCCESS;
2869 }
2870
2871 int
2872 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2873                                 struct i40e_vsi_vlan_pvid_info *info)
2874 {
2875         struct i40e_hw *hw;
2876         struct i40e_vsi_context ctxt;
2877         uint8_t vlan_flags = 0;
2878         int ret;
2879
2880         if (vsi == NULL || info == NULL) {
2881                 PMD_DRV_LOG(ERR, "invalid parameters");
2882                 return I40E_ERR_PARAM;
2883         }
2884
2885         if (info->on) {
2886                 vsi->info.pvid = info->config.pvid;
2887                 /**
2888                  * If insert pvid is enabled, only tagged pkts are
2889                  * allowed to be sent out.
2890                  */
2891                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2892                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2893         } else {
2894                 vsi->info.pvid = 0;
2895                 if (info->config.reject.tagged == 0)
2896                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2897
2898                 if (info->config.reject.untagged == 0)
2899                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2900         }
2901         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2902                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2903         vsi->info.port_vlan_flags |= vlan_flags;
2904         vsi->info.valid_sections =
2905                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2906         memset(&ctxt, 0, sizeof(ctxt));
2907         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2908         ctxt.seid = vsi->seid;
2909
2910         hw = I40E_VSI_TO_HW(vsi);
2911         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2912         if (ret != I40E_SUCCESS)
2913                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2914
2915         return ret;
2916 }
2917
2918 static int
2919 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2920 {
2921         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2922         int i, ret;
2923         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2924
2925         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2926         if (ret != I40E_SUCCESS)
2927                 return ret;
2928
2929         if (!vsi->seid) {
2930                 PMD_DRV_LOG(ERR, "seid not valid");
2931                 return -EINVAL;
2932         }
2933
2934         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2935         tc_bw_data.tc_valid_bits = enabled_tcmap;
2936         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2937                 tc_bw_data.tc_bw_credits[i] =
2938                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2939
2940         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2941         if (ret != I40E_SUCCESS) {
2942                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2943                 return ret;
2944         }
2945
2946         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2947                                         sizeof(vsi->info.qs_handle));
2948         return I40E_SUCCESS;
2949 }
2950
2951 static int
2952 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2953                                  struct i40e_aqc_vsi_properties_data *info,
2954                                  uint8_t enabled_tcmap)
2955 {
2956         int ret, i, total_tc = 0;
2957         uint16_t qpnum_per_tc, bsf, qp_idx;
2958
2959         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2960         if (ret != I40E_SUCCESS)
2961                 return ret;
2962
2963         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2964                 if (enabled_tcmap & (1 << i))
2965                         total_tc++;
2966         vsi->enabled_tc = enabled_tcmap;
2967
2968         /* Number of queues per enabled TC */
2969         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2970         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2971         bsf = rte_bsf32(qpnum_per_tc);
2972
2973         /* Adjust the queue number to actual queues that can be applied */
2974         vsi->nb_qps = qpnum_per_tc * total_tc;
2975
2976         /**
2977          * Configure TC and queue mapping parameters, for enabled TC,
2978          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2979          * default queue will serve it.
2980          */
2981         qp_idx = 0;
2982         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2983                 if (vsi->enabled_tc & (1 << i)) {
2984                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2985                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2986                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2987                         qp_idx += qpnum_per_tc;
2988                 } else
2989                         info->tc_mapping[i] = 0;
2990         }
2991
2992         /* Associate queue number with VSI */
2993         if (vsi->type == I40E_VSI_SRIOV) {
2994                 info->mapping_flags |=
2995                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2996                 for (i = 0; i < vsi->nb_qps; i++)
2997                         info->queue_mapping[i] =
2998                                 rte_cpu_to_le_16(vsi->base_queue + i);
2999         } else {
3000                 info->mapping_flags |=
3001                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3002                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3003         }
3004         info->valid_sections |=
3005                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3006
3007         return I40E_SUCCESS;
3008 }
3009
3010 static int
3011 i40e_veb_release(struct i40e_veb *veb)
3012 {
3013         struct i40e_vsi *vsi;
3014         struct i40e_hw *hw;
3015
3016         if (veb == NULL || veb->associate_vsi == NULL)
3017                 return -EINVAL;
3018
3019         if (!TAILQ_EMPTY(&veb->head)) {
3020                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3021                 return -EACCES;
3022         }
3023
3024         vsi = veb->associate_vsi;
3025         hw = I40E_VSI_TO_HW(vsi);
3026
3027         vsi->uplink_seid = veb->uplink_seid;
3028         i40e_aq_delete_element(hw, veb->seid, NULL);
3029         rte_free(veb);
3030         vsi->veb = NULL;
3031         return I40E_SUCCESS;
3032 }
3033
3034 /* Setup a veb */
3035 static struct i40e_veb *
3036 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3037 {
3038         struct i40e_veb *veb;
3039         int ret;
3040         struct i40e_hw *hw;
3041
3042         if (NULL == pf || vsi == NULL) {
3043                 PMD_DRV_LOG(ERR, "veb setup failed, "
3044                             "associated VSI shouldn't null");
3045                 return NULL;
3046         }
3047         hw = I40E_PF_TO_HW(pf);
3048
3049         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3050         if (!veb) {
3051                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3052                 goto fail;
3053         }
3054
3055         veb->associate_vsi = vsi;
3056         TAILQ_INIT(&veb->head);
3057         veb->uplink_seid = vsi->uplink_seid;
3058
3059         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3060                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3061
3062         if (ret != I40E_SUCCESS) {
3063                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3064                             hw->aq.asq_last_status);
3065                 goto fail;
3066         }
3067
3068         /* get statistics index */
3069         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3070                                 &veb->stats_idx, NULL, NULL, NULL);
3071         if (ret != I40E_SUCCESS) {
3072                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3073                             hw->aq.asq_last_status);
3074                 goto fail;
3075         }
3076
3077         /* Get VEB bandwidth, to be implemented */
3078         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3079         vsi->uplink_seid = veb->seid;
3080
3081         return veb;
3082 fail:
3083         rte_free(veb);
3084         return NULL;
3085 }
3086
3087 int
3088 i40e_vsi_release(struct i40e_vsi *vsi)
3089 {
3090         struct i40e_pf *pf;
3091         struct i40e_hw *hw;
3092         struct i40e_vsi_list *vsi_list;
3093         int ret;
3094         struct i40e_mac_filter *f;
3095
3096         if (!vsi)
3097                 return I40E_SUCCESS;
3098
3099         pf = I40E_VSI_TO_PF(vsi);
3100         hw = I40E_VSI_TO_HW(vsi);
3101
3102         /* VSI has child to attach, release child first */
3103         if (vsi->veb) {
3104                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3105                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3106                                 return -1;
3107                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3108                 }
3109                 i40e_veb_release(vsi->veb);
3110         }
3111
3112         /* Remove all macvlan filters of the VSI */
3113         i40e_vsi_remove_all_macvlan_filter(vsi);
3114         TAILQ_FOREACH(f, &vsi->mac_list, next)
3115                 rte_free(f);
3116
3117         if (vsi->type != I40E_VSI_MAIN) {
3118                 /* Remove vsi from parent's sibling list */
3119                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3120                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3121                         return I40E_ERR_PARAM;
3122                 }
3123                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3124                                 &vsi->sib_vsi_list, list);
3125
3126                 /* Remove all switch element of the VSI */
3127                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3128                 if (ret != I40E_SUCCESS)
3129                         PMD_DRV_LOG(ERR, "Failed to delete element");
3130         }
3131         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3132
3133         if (vsi->type != I40E_VSI_SRIOV)
3134                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3135         rte_free(vsi);
3136
3137         return I40E_SUCCESS;
3138 }
3139
3140 static int
3141 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3142 {
3143         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3144         struct i40e_aqc_remove_macvlan_element_data def_filter;
3145         struct i40e_mac_filter_info filter;
3146         int ret;
3147
3148         if (vsi->type != I40E_VSI_MAIN)
3149                 return I40E_ERR_CONFIG;
3150         memset(&def_filter, 0, sizeof(def_filter));
3151         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3152                                         ETH_ADDR_LEN);
3153         def_filter.vlan_tag = 0;
3154         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3155                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3156         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3157         if (ret != I40E_SUCCESS) {
3158                 struct i40e_mac_filter *f;
3159                 struct ether_addr *mac;
3160
3161                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3162                             "macvlan filter");
3163                 /* It needs to add the permanent mac into mac list */
3164                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3165                 if (f == NULL) {
3166                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3167                         return I40E_ERR_NO_MEMORY;
3168                 }
3169                 mac = &f->mac_info.mac_addr;
3170                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3171                                 ETH_ADDR_LEN);
3172                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3173                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3174                 vsi->mac_num++;
3175
3176                 return ret;
3177         }
3178         (void)rte_memcpy(&filter.mac_addr,
3179                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3180         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3181         return i40e_vsi_add_mac(vsi, &filter);
3182 }
3183
3184 static int
3185 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3186 {
3187         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3188         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3189         struct i40e_hw *hw = &vsi->adapter->hw;
3190         i40e_status ret;
3191         int i;
3192
3193         memset(&bw_config, 0, sizeof(bw_config));
3194         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3195         if (ret != I40E_SUCCESS) {
3196                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3197                             hw->aq.asq_last_status);
3198                 return ret;
3199         }
3200
3201         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3202         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3203                                         &ets_sla_config, NULL);
3204         if (ret != I40E_SUCCESS) {
3205                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3206                             "configuration %u", hw->aq.asq_last_status);
3207                 return ret;
3208         }
3209
3210         /* Not store the info yet, just print out */
3211         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3212         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3213         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3214                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3215                             ets_sla_config.share_credits[i]);
3216                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3217                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3218                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3219                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3220                             (i * 4));
3221         }
3222
3223         return 0;
3224 }
3225
3226 /* Setup a VSI */
3227 struct i40e_vsi *
3228 i40e_vsi_setup(struct i40e_pf *pf,
3229                enum i40e_vsi_type type,
3230                struct i40e_vsi *uplink_vsi,
3231                uint16_t user_param)
3232 {
3233         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3234         struct i40e_vsi *vsi;
3235         struct i40e_mac_filter_info filter;
3236         int ret;
3237         struct i40e_vsi_context ctxt;
3238         struct ether_addr broadcast =
3239                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3240
3241         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3242                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3243                             "VSI link shouldn't be NULL");
3244                 return NULL;
3245         }
3246
3247         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3248                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3249                             "uplink VSI should be NULL");
3250                 return NULL;
3251         }
3252
3253         /* If uplink vsi didn't setup VEB, create one first */
3254         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3255                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3256
3257                 if (NULL == uplink_vsi->veb) {
3258                         PMD_DRV_LOG(ERR, "VEB setup failed");
3259                         return NULL;
3260                 }
3261         }
3262
3263         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3264         if (!vsi) {
3265                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3266                 return NULL;
3267         }
3268         TAILQ_INIT(&vsi->mac_list);
3269         vsi->type = type;
3270         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3271         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3272         vsi->parent_vsi = uplink_vsi;
3273         vsi->user_param = user_param;
3274         /* Allocate queues */
3275         switch (vsi->type) {
3276         case I40E_VSI_MAIN  :
3277                 vsi->nb_qps = pf->lan_nb_qps;
3278                 break;
3279         case I40E_VSI_SRIOV :
3280                 vsi->nb_qps = pf->vf_nb_qps;
3281                 break;
3282         case I40E_VSI_VMDQ2:
3283                 vsi->nb_qps = pf->vmdq_nb_qps;
3284                 break;
3285         case I40E_VSI_FDIR:
3286                 vsi->nb_qps = pf->fdir_nb_qps;
3287                 break;
3288         default:
3289                 goto fail_mem;
3290         }
3291         /*
3292          * The filter status descriptor is reported in rx queue 0,
3293          * while the tx queue for fdir filter programming has no
3294          * such constraints, can be non-zero queues.
3295          * To simplify it, choose FDIR vsi use queue 0 pair.
3296          * To make sure it will use queue 0 pair, queue allocation
3297          * need be done before this function is called
3298          */
3299         if (type != I40E_VSI_FDIR) {
3300                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3301                         if (ret < 0) {
3302                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3303                                                 vsi->seid, ret);
3304                                 goto fail_mem;
3305                         }
3306                         vsi->base_queue = ret;
3307         } else
3308                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3309
3310         /* VF has MSIX interrupt in VF range, don't allocate here */
3311         if (type != I40E_VSI_SRIOV) {
3312                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3313                 if (ret < 0) {
3314                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3315                         goto fail_queue_alloc;
3316                 }
3317                 vsi->msix_intr = ret;
3318         } else
3319                 vsi->msix_intr = 0;
3320         /* Add VSI */
3321         if (type == I40E_VSI_MAIN) {
3322                 /* For main VSI, no need to add since it's default one */
3323                 vsi->uplink_seid = pf->mac_seid;
3324                 vsi->seid = pf->main_vsi_seid;
3325                 /* Bind queues with specific MSIX interrupt */
3326                 /**
3327                  * Needs 2 interrupt at least, one for misc cause which will
3328                  * enabled from OS side, Another for queues binding the
3329                  * interrupt from device side only.
3330                  */
3331
3332                 /* Get default VSI parameters from hardware */
3333                 memset(&ctxt, 0, sizeof(ctxt));
3334                 ctxt.seid = vsi->seid;
3335                 ctxt.pf_num = hw->pf_id;
3336                 ctxt.uplink_seid = vsi->uplink_seid;
3337                 ctxt.vf_num = 0;
3338                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3339                 if (ret != I40E_SUCCESS) {
3340                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3341                         goto fail_msix_alloc;
3342                 }
3343                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3344                         sizeof(struct i40e_aqc_vsi_properties_data));
3345                 vsi->vsi_id = ctxt.vsi_number;
3346                 vsi->info.valid_sections = 0;
3347
3348                 /* Configure tc, enabled TC0 only */
3349                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3350                         I40E_SUCCESS) {
3351                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3352                         goto fail_msix_alloc;
3353                 }
3354
3355                 /* TC, queue mapping */
3356                 memset(&ctxt, 0, sizeof(ctxt));
3357                 vsi->info.valid_sections |=
3358                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3359                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3360                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3361                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3362                         sizeof(struct i40e_aqc_vsi_properties_data));
3363                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3364                                                 I40E_DEFAULT_TCMAP);
3365                 if (ret != I40E_SUCCESS) {
3366                         PMD_DRV_LOG(ERR, "Failed to configure "
3367                                     "TC queue mapping");
3368                         goto fail_msix_alloc;
3369                 }
3370                 ctxt.seid = vsi->seid;
3371                 ctxt.pf_num = hw->pf_id;
3372                 ctxt.uplink_seid = vsi->uplink_seid;
3373                 ctxt.vf_num = 0;
3374
3375                 /* Update VSI parameters */
3376                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3377                 if (ret != I40E_SUCCESS) {
3378                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3379                         goto fail_msix_alloc;
3380                 }
3381
3382                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3383                                                 sizeof(vsi->info.tc_mapping));
3384                 (void)rte_memcpy(&vsi->info.queue_mapping,
3385                                 &ctxt.info.queue_mapping,
3386                         sizeof(vsi->info.queue_mapping));
3387                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3388                 vsi->info.valid_sections = 0;
3389
3390                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3391                                 ETH_ADDR_LEN);
3392
3393                 /**
3394                  * Updating default filter settings are necessary to prevent
3395                  * reception of tagged packets.
3396                  * Some old firmware configurations load a default macvlan
3397                  * filter which accepts both tagged and untagged packets.
3398                  * The updating is to use a normal filter instead if needed.
3399                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3400                  * The firmware with correct configurations load the default
3401                  * macvlan filter which is expected and cannot be removed.
3402                  */
3403                 i40e_update_default_filter_setting(vsi);
3404                 i40e_config_qinq(hw, vsi);
3405         } else if (type == I40E_VSI_SRIOV) {
3406                 memset(&ctxt, 0, sizeof(ctxt));
3407                 /**
3408                  * For other VSI, the uplink_seid equals to uplink VSI's
3409                  * uplink_seid since they share same VEB
3410                  */
3411                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3412                 ctxt.pf_num = hw->pf_id;
3413                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3414                 ctxt.uplink_seid = vsi->uplink_seid;
3415                 ctxt.connection_type = 0x1;
3416                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3417
3418                 /**
3419                  * Do not configure switch ID to enable VEB switch by
3420                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3421                  * if the source mac address of packet sent from VF is not
3422                  * listed in the VEB's mac table, the VEB will switch the
3423                  * packet back to the VF. Need to enable it when HW issue
3424                  * is fixed.
3425                  */
3426
3427                 /* Configure port/vlan */
3428                 ctxt.info.valid_sections |=
3429                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3430                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3431                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3432                                                 I40E_DEFAULT_TCMAP);
3433                 if (ret != I40E_SUCCESS) {
3434                         PMD_DRV_LOG(ERR, "Failed to configure "
3435                                     "TC queue mapping");
3436                         goto fail_msix_alloc;
3437                 }
3438                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3439                 ctxt.info.valid_sections |=
3440                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3441                 /**
3442                  * Since VSI is not created yet, only configure parameter,
3443                  * will add vsi below.
3444                  */
3445
3446                 i40e_config_qinq(hw, vsi);
3447         } else if (type == I40E_VSI_VMDQ2) {
3448                 memset(&ctxt, 0, sizeof(ctxt));
3449                 /*
3450                  * For other VSI, the uplink_seid equals to uplink VSI's
3451                  * uplink_seid since they share same VEB
3452                  */
3453                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3454                 ctxt.pf_num = hw->pf_id;
3455                 ctxt.vf_num = 0;
3456                 ctxt.uplink_seid = vsi->uplink_seid;
3457                 ctxt.connection_type = 0x1;
3458                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3459
3460                 ctxt.info.valid_sections |=
3461                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3462                 /* user_param carries flag to enable loop back */
3463                 if (user_param) {
3464                         ctxt.info.switch_id =
3465                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3466                         ctxt.info.switch_id |=
3467                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3468                 }
3469
3470                 /* Configure port/vlan */
3471                 ctxt.info.valid_sections |=
3472                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3473                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3474                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3475                                                 I40E_DEFAULT_TCMAP);
3476                 if (ret != I40E_SUCCESS) {
3477                         PMD_DRV_LOG(ERR, "Failed to configure "
3478                                         "TC queue mapping");
3479                         goto fail_msix_alloc;
3480                 }
3481                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3482                 ctxt.info.valid_sections |=
3483                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3484         } else if (type == I40E_VSI_FDIR) {
3485                 memset(&ctxt, 0, sizeof(ctxt));
3486                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3487                 ctxt.pf_num = hw->pf_id;
3488                 ctxt.vf_num = 0;
3489                 ctxt.uplink_seid = vsi->uplink_seid;
3490                 ctxt.connection_type = 0x1;     /* regular data port */
3491                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3492                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3493                                                 I40E_DEFAULT_TCMAP);
3494                 if (ret != I40E_SUCCESS) {
3495                         PMD_DRV_LOG(ERR, "Failed to configure "
3496                                         "TC queue mapping.");
3497                         goto fail_msix_alloc;
3498                 }
3499                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3500                 ctxt.info.valid_sections |=
3501                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3502         } else {
3503                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3504                 goto fail_msix_alloc;
3505         }
3506
3507         if (vsi->type != I40E_VSI_MAIN) {
3508                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3509                 if (ret != I40E_SUCCESS) {
3510                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3511                                     hw->aq.asq_last_status);
3512                         goto fail_msix_alloc;
3513                 }
3514                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3515                 vsi->info.valid_sections = 0;
3516                 vsi->seid = ctxt.seid;
3517                 vsi->vsi_id = ctxt.vsi_number;
3518                 vsi->sib_vsi_list.vsi = vsi;
3519                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3520                                 &vsi->sib_vsi_list, list);
3521         }
3522
3523         /* MAC/VLAN configuration */
3524         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3525         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3526
3527         ret = i40e_vsi_add_mac(vsi, &filter);
3528         if (ret != I40E_SUCCESS) {
3529                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3530                 goto fail_msix_alloc;
3531         }
3532
3533         /* Get VSI BW information */
3534         i40e_vsi_dump_bw_config(vsi);
3535         return vsi;
3536 fail_msix_alloc:
3537         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3538 fail_queue_alloc:
3539         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3540 fail_mem:
3541         rte_free(vsi);
3542         return NULL;
3543 }
3544
3545 /* Configure vlan stripping on or off */
3546 int
3547 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3548 {
3549         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3550         struct i40e_vsi_context ctxt;
3551         uint8_t vlan_flags;
3552         int ret = I40E_SUCCESS;
3553
3554         /* Check if it has been already on or off */
3555         if (vsi->info.valid_sections &
3556                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3557                 if (on) {
3558                         if ((vsi->info.port_vlan_flags &
3559                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3560                                 return 0; /* already on */
3561                 } else {
3562                         if ((vsi->info.port_vlan_flags &
3563                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3564                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3565                                 return 0; /* already off */
3566                 }
3567         }
3568
3569         if (on)
3570                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3571         else
3572                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3573         vsi->info.valid_sections =
3574                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3575         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3576         vsi->info.port_vlan_flags |= vlan_flags;
3577         ctxt.seid = vsi->seid;
3578         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3579         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3580         if (ret)
3581                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3582                             on ? "enable" : "disable");
3583
3584         return ret;
3585 }
3586
3587 static int
3588 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3589 {
3590         struct rte_eth_dev_data *data = dev->data;
3591         int ret;
3592
3593         /* Apply vlan offload setting */
3594         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3595
3596         /* Apply double-vlan setting, not implemented yet */
3597
3598         /* Apply pvid setting */
3599         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3600                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3601         if (ret)
3602                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3603
3604         return ret;
3605 }
3606
3607 static int
3608 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3609 {
3610         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3611
3612         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3613 }
3614
3615 static int
3616 i40e_update_flow_control(struct i40e_hw *hw)
3617 {
3618 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3619         struct i40e_link_status link_status;
3620         uint32_t rxfc = 0, txfc = 0, reg;
3621         uint8_t an_info;
3622         int ret;
3623
3624         memset(&link_status, 0, sizeof(link_status));
3625         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3626         if (ret != I40E_SUCCESS) {
3627                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3628                 goto write_reg; /* Disable flow control */
3629         }
3630
3631         an_info = hw->phy.link_info.an_info;
3632         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3633                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3634                 ret = I40E_ERR_NOT_READY;
3635                 goto write_reg; /* Disable flow control */
3636         }
3637         /**
3638          * If link auto negotiation is enabled, flow control needs to
3639          * be configured according to it
3640          */
3641         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3642         case I40E_LINK_PAUSE_RXTX:
3643                 rxfc = 1;
3644                 txfc = 1;
3645                 hw->fc.current_mode = I40E_FC_FULL;
3646                 break;
3647         case I40E_AQ_LINK_PAUSE_RX:
3648                 rxfc = 1;
3649                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3650                 break;
3651         case I40E_AQ_LINK_PAUSE_TX:
3652                 txfc = 1;
3653                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3654                 break;
3655         default:
3656                 hw->fc.current_mode = I40E_FC_NONE;
3657                 break;
3658         }
3659
3660 write_reg:
3661         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3662                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3663         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3664         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3665         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3666         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3667
3668         return ret;
3669 }
3670
3671 /* PF setup */
3672 static int
3673 i40e_pf_setup(struct i40e_pf *pf)
3674 {
3675         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3676         struct i40e_filter_control_settings settings;
3677         struct i40e_vsi *vsi;
3678         int ret;
3679
3680         /* Clear all stats counters */
3681         pf->offset_loaded = FALSE;
3682         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3683         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3684
3685         ret = i40e_pf_get_switch_config(pf);
3686         if (ret != I40E_SUCCESS) {
3687                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3688                 return ret;
3689         }
3690         if (pf->flags & I40E_FLAG_FDIR) {
3691                 /* make queue allocated first, let FDIR use queue pair 0*/
3692                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3693                 if (ret != I40E_FDIR_QUEUE_ID) {
3694                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3695                                     " ret =%d", ret);
3696                         pf->flags &= ~I40E_FLAG_FDIR;
3697                 }
3698         }
3699         /*  main VSI setup */
3700         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3701         if (!vsi) {
3702                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3703                 return I40E_ERR_NOT_READY;
3704         }
3705         pf->main_vsi = vsi;
3706
3707         /* Configure filter control */
3708         memset(&settings, 0, sizeof(settings));
3709         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3710                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3711         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3712                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3713         else {
3714                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3715                                                 hw->func_caps.rss_table_size);
3716                 return I40E_ERR_PARAM;
3717         }
3718         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3719                         "size: %u\n", hw->func_caps.rss_table_size);
3720         pf->hash_lut_size = hw->func_caps.rss_table_size;
3721
3722         /* Enable ethtype and macvlan filters */
3723         settings.enable_ethtype = TRUE;
3724         settings.enable_macvlan = TRUE;
3725         ret = i40e_set_filter_control(hw, &settings);
3726         if (ret)
3727                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3728                                                                 ret);
3729
3730         /* Update flow control according to the auto negotiation */
3731         i40e_update_flow_control(hw);
3732
3733         return I40E_SUCCESS;
3734 }
3735
3736 int
3737 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3738 {
3739         uint32_t reg;
3740         uint16_t j;
3741
3742         /**
3743          * Set or clear TX Queue Disable flags,
3744          * which is required by hardware.
3745          */
3746         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3747         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3748
3749         /* Wait until the request is finished */
3750         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3751                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3752                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3753                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3754                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3755                                                         & 0x1))) {
3756                         break;
3757                 }
3758         }
3759         if (on) {
3760                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3761                         return I40E_SUCCESS; /* already on, skip next steps */
3762
3763                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3764                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3765         } else {
3766                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3767                         return I40E_SUCCESS; /* already off, skip next steps */
3768                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3769         }
3770         /* Write the register */
3771         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3772         /* Check the result */
3773         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3774                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3775                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3776                 if (on) {
3777                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3778                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3779                                 break;
3780                 } else {
3781                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3782                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3783                                 break;
3784                 }
3785         }
3786         /* Check if it is timeout */
3787         if (j >= I40E_CHK_Q_ENA_COUNT) {
3788                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3789                             (on ? "enable" : "disable"), q_idx);
3790                 return I40E_ERR_TIMEOUT;
3791         }
3792
3793         return I40E_SUCCESS;
3794 }
3795
3796 /* Swith on or off the tx queues */
3797 static int
3798 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3799 {
3800         struct rte_eth_dev_data *dev_data = pf->dev_data;
3801         struct i40e_tx_queue *txq;
3802         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3803         uint16_t i;
3804         int ret;
3805
3806         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3807                 txq = dev_data->tx_queues[i];
3808                 /* Don't operate the queue if not configured or
3809                  * if starting only per queue */
3810                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3811                         continue;
3812                 if (on)
3813                         ret = i40e_dev_tx_queue_start(dev, i);
3814                 else
3815                         ret = i40e_dev_tx_queue_stop(dev, i);
3816                 if ( ret != I40E_SUCCESS)
3817                         return ret;
3818         }
3819
3820         return I40E_SUCCESS;
3821 }
3822
3823 int
3824 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3825 {
3826         uint32_t reg;
3827         uint16_t j;
3828
3829         /* Wait until the request is finished */
3830         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3831                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3832                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3833                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3834                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3835                         break;
3836         }
3837
3838         if (on) {
3839                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3840                         return I40E_SUCCESS; /* Already on, skip next steps */
3841                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3842         } else {
3843                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3844                         return I40E_SUCCESS; /* Already off, skip next steps */
3845                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3846         }
3847
3848         /* Write the register */
3849         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3850         /* Check the result */
3851         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3852                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3853                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3854                 if (on) {
3855                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3856                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3857                                 break;
3858                 } else {
3859                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3860                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3861                                 break;
3862                 }
3863         }
3864
3865         /* Check if it is timeout */
3866         if (j >= I40E_CHK_Q_ENA_COUNT) {
3867                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3868                             (on ? "enable" : "disable"), q_idx);
3869                 return I40E_ERR_TIMEOUT;
3870         }
3871
3872         return I40E_SUCCESS;
3873 }
3874 /* Switch on or off the rx queues */
3875 static int
3876 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3877 {
3878         struct rte_eth_dev_data *dev_data = pf->dev_data;
3879         struct i40e_rx_queue *rxq;
3880         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3881         uint16_t i;
3882         int ret;
3883
3884         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3885                 rxq = dev_data->rx_queues[i];
3886                 /* Don't operate the queue if not configured or
3887                  * if starting only per queue */
3888                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3889                         continue;
3890                 if (on)
3891                         ret = i40e_dev_rx_queue_start(dev, i);
3892                 else
3893                         ret = i40e_dev_rx_queue_stop(dev, i);
3894                 if (ret != I40E_SUCCESS)
3895                         return ret;
3896         }
3897
3898         return I40E_SUCCESS;
3899 }
3900
3901 /* Switch on or off all the rx/tx queues */
3902 int
3903 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3904 {
3905         int ret;
3906
3907         if (on) {
3908                 /* enable rx queues before enabling tx queues */
3909                 ret = i40e_dev_switch_rx_queues(pf, on);
3910                 if (ret) {
3911                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3912                         return ret;
3913                 }
3914                 ret = i40e_dev_switch_tx_queues(pf, on);
3915         } else {
3916                 /* Stop tx queues before stopping rx queues */
3917                 ret = i40e_dev_switch_tx_queues(pf, on);
3918                 if (ret) {
3919                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3920                         return ret;
3921                 }
3922                 ret = i40e_dev_switch_rx_queues(pf, on);
3923         }
3924
3925         return ret;
3926 }
3927
3928 /* Initialize VSI for TX */
3929 static int
3930 i40e_dev_tx_init(struct i40e_pf *pf)
3931 {
3932         struct rte_eth_dev_data *data = pf->dev_data;
3933         uint16_t i;
3934         uint32_t ret = I40E_SUCCESS;
3935         struct i40e_tx_queue *txq;
3936
3937         for (i = 0; i < data->nb_tx_queues; i++) {
3938                 txq = data->tx_queues[i];
3939                 if (!txq || !txq->q_set)
3940                         continue;
3941                 ret = i40e_tx_queue_init(txq);
3942                 if (ret != I40E_SUCCESS)
3943                         break;
3944         }
3945         if (ret == I40E_SUCCESS)
3946                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
3947                                      ->eth_dev);
3948
3949         return ret;
3950 }
3951
3952 /* Initialize VSI for RX */
3953 static int
3954 i40e_dev_rx_init(struct i40e_pf *pf)
3955 {
3956         struct rte_eth_dev_data *data = pf->dev_data;
3957         int ret = I40E_SUCCESS;
3958         uint16_t i;
3959         struct i40e_rx_queue *rxq;
3960
3961         i40e_pf_config_mq_rx(pf);
3962         for (i = 0; i < data->nb_rx_queues; i++) {
3963                 rxq = data->rx_queues[i];
3964                 if (!rxq || !rxq->q_set)
3965                         continue;
3966
3967                 ret = i40e_rx_queue_init(rxq);
3968                 if (ret != I40E_SUCCESS) {
3969                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3970                                     "initialization");
3971                         break;
3972                 }
3973         }
3974         if (ret == I40E_SUCCESS)
3975                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
3976                                      ->eth_dev);
3977
3978         return ret;
3979 }
3980
3981 static int
3982 i40e_dev_rxtx_init(struct i40e_pf *pf)
3983 {
3984         int err;
3985
3986         err = i40e_dev_tx_init(pf);
3987         if (err) {
3988                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3989                 return err;
3990         }
3991         err = i40e_dev_rx_init(pf);
3992         if (err) {
3993                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3994                 return err;
3995         }
3996
3997         return err;
3998 }
3999
4000 static int
4001 i40e_vmdq_setup(struct rte_eth_dev *dev)
4002 {
4003         struct rte_eth_conf *conf = &dev->data->dev_conf;
4004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4005         int i, err, conf_vsis, j, loop;
4006         struct i40e_vsi *vsi;
4007         struct i40e_vmdq_info *vmdq_info;
4008         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4009         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4010
4011         /*
4012          * Disable interrupt to avoid message from VF. Furthermore, it will
4013          * avoid race condition in VSI creation/destroy.
4014          */
4015         i40e_pf_disable_irq0(hw);
4016
4017         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4018                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4019                 return -ENOTSUP;
4020         }
4021
4022         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4023         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4024                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4025                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4026                         pf->max_nb_vmdq_vsi);
4027                 return -ENOTSUP;
4028         }
4029
4030         if (pf->vmdq != NULL) {
4031                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4032                 return 0;
4033         }
4034
4035         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4036                                 sizeof(*vmdq_info) * conf_vsis, 0);
4037
4038         if (pf->vmdq == NULL) {
4039                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4040                 return -ENOMEM;
4041         }
4042
4043         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4044
4045         /* Create VMDQ VSI */
4046         for (i = 0; i < conf_vsis; i++) {
4047                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4048                                 vmdq_conf->enable_loop_back);
4049                 if (vsi == NULL) {
4050                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4051                         err = -1;
4052                         goto err_vsi_setup;
4053                 }
4054                 vmdq_info = &pf->vmdq[i];
4055                 vmdq_info->pf = pf;
4056                 vmdq_info->vsi = vsi;
4057         }
4058         pf->nb_cfg_vmdq_vsi = conf_vsis;
4059
4060         /* Configure Vlan */
4061         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4062         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4063                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4064                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4065                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4066                                         vmdq_conf->pool_map[i].vlan_id, j);
4067
4068                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4069                                                 vmdq_conf->pool_map[i].vlan_id);
4070                                 if (err) {
4071                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4072                                         err = -1;
4073                                         goto err_vsi_setup;
4074                                 }
4075                         }
4076                 }
4077         }
4078
4079         i40e_pf_enable_irq0(hw);
4080
4081         return 0;
4082
4083 err_vsi_setup:
4084         for (i = 0; i < conf_vsis; i++)
4085                 if (pf->vmdq[i].vsi == NULL)
4086                         break;
4087                 else
4088                         i40e_vsi_release(pf->vmdq[i].vsi);
4089
4090         rte_free(pf->vmdq);
4091         pf->vmdq = NULL;
4092         i40e_pf_enable_irq0(hw);
4093         return err;
4094 }
4095
4096 static void
4097 i40e_stat_update_32(struct i40e_hw *hw,
4098                    uint32_t reg,
4099                    bool offset_loaded,
4100                    uint64_t *offset,
4101                    uint64_t *stat)
4102 {
4103         uint64_t new_data;
4104
4105         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4106         if (!offset_loaded)
4107                 *offset = new_data;
4108
4109         if (new_data >= *offset)
4110                 *stat = (uint64_t)(new_data - *offset);
4111         else
4112                 *stat = (uint64_t)((new_data +
4113                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4114 }
4115
4116 static void
4117 i40e_stat_update_48(struct i40e_hw *hw,
4118                    uint32_t hireg,
4119                    uint32_t loreg,
4120                    bool offset_loaded,
4121                    uint64_t *offset,
4122                    uint64_t *stat)
4123 {
4124         uint64_t new_data;
4125
4126         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4127         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4128                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4129
4130         if (!offset_loaded)
4131                 *offset = new_data;
4132
4133         if (new_data >= *offset)
4134                 *stat = new_data - *offset;
4135         else
4136                 *stat = (uint64_t)((new_data +
4137                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4138
4139         *stat &= I40E_48_BIT_MASK;
4140 }
4141
4142 /* Disable IRQ0 */
4143 void
4144 i40e_pf_disable_irq0(struct i40e_hw *hw)
4145 {
4146         /* Disable all interrupt types */
4147         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4148         I40E_WRITE_FLUSH(hw);
4149 }
4150
4151 /* Enable IRQ0 */
4152 void
4153 i40e_pf_enable_irq0(struct i40e_hw *hw)
4154 {
4155         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4156                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4157                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4158                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4159         I40E_WRITE_FLUSH(hw);
4160 }
4161
4162 static void
4163 i40e_pf_config_irq0(struct i40e_hw *hw)
4164 {
4165         /* read pending request and disable first */
4166         i40e_pf_disable_irq0(hw);
4167         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4168         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4169                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4170
4171         /* Link no queues with irq0 */
4172         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4173                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4174 }
4175
4176 static void
4177 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4178 {
4179         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4181         int i;
4182         uint16_t abs_vf_id;
4183         uint32_t index, offset, val;
4184
4185         if (!pf->vfs)
4186                 return;
4187         /**
4188          * Try to find which VF trigger a reset, use absolute VF id to access
4189          * since the reg is global register.
4190          */
4191         for (i = 0; i < pf->vf_num; i++) {
4192                 abs_vf_id = hw->func_caps.vf_base_id + i;
4193                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4194                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4195                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4196                 /* VFR event occured */
4197                 if (val & (0x1 << offset)) {
4198                         int ret;
4199
4200                         /* Clear the event first */
4201                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4202                                                         (0x1 << offset));
4203                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4204                         /**
4205                          * Only notify a VF reset event occured,
4206                          * don't trigger another SW reset
4207                          */
4208                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4209                         if (ret != I40E_SUCCESS)
4210                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4211                 }
4212         }
4213 }
4214
4215 static void
4216 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4217 {
4218         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4219         struct i40e_arq_event_info info;
4220         uint16_t pending, opcode;
4221         int ret;
4222
4223         info.buf_len = I40E_AQ_BUF_SZ;
4224         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4225         if (!info.msg_buf) {
4226                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4227                 return;
4228         }
4229
4230         pending = 1;
4231         while (pending) {
4232                 ret = i40e_clean_arq_element(hw, &info, &pending);
4233
4234                 if (ret != I40E_SUCCESS) {
4235                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4236                                     "aq_err: %u", hw->aq.asq_last_status);
4237                         break;
4238                 }
4239                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4240
4241                 switch (opcode) {
4242                 case i40e_aqc_opc_send_msg_to_pf:
4243                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4244                         i40e_pf_host_handle_vf_msg(dev,
4245                                         rte_le_to_cpu_16(info.desc.retval),
4246                                         rte_le_to_cpu_32(info.desc.cookie_high),
4247                                         rte_le_to_cpu_32(info.desc.cookie_low),
4248                                         info.msg_buf,
4249                                         info.msg_len);
4250                         break;
4251                 default:
4252                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4253                                     opcode);
4254                         break;
4255                 }
4256         }
4257         rte_free(info.msg_buf);
4258 }
4259
4260 /*
4261  * Interrupt handler is registered as the alarm callback for handling LSC
4262  * interrupt in a definite of time, in order to wait the NIC into a stable
4263  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4264  * no need for link down interrupt.
4265  */
4266 static void
4267 i40e_dev_interrupt_delayed_handler(void *param)
4268 {
4269         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4270         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4271         uint32_t icr0;
4272
4273         /* read interrupt causes again */
4274         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4275
4276 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4277         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4278                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4279         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4280                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4281         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4282                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4283         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4284                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4285         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4286                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4287                                                                 "state\n");
4288         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4289                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4290         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4291                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4292 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4293
4294         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4295                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4296                 i40e_dev_handle_vfr_event(dev);
4297         }
4298         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4299                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4300                 i40e_dev_handle_aq_msg(dev);
4301         }
4302
4303         /* handle the link up interrupt in an alarm callback */
4304         i40e_dev_link_update(dev, 0);
4305         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4306
4307         i40e_pf_enable_irq0(hw);
4308         rte_intr_enable(&(dev->pci_dev->intr_handle));
4309 }
4310
4311 /**
4312  * Interrupt handler triggered by NIC  for handling
4313  * specific interrupt.
4314  *
4315  * @param handle
4316  *  Pointer to interrupt handle.
4317  * @param param
4318  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4319  *
4320  * @return
4321  *  void
4322  */
4323 static void
4324 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4325                            void *param)
4326 {
4327         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4328         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4329         uint32_t icr0;
4330
4331         /* Disable interrupt */
4332         i40e_pf_disable_irq0(hw);
4333
4334         /* read out interrupt causes */
4335         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4336
4337         /* No interrupt event indicated */
4338         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4339                 PMD_DRV_LOG(INFO, "No interrupt event");
4340                 goto done;
4341         }
4342 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4343         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4344                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4345         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4346                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4347         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4348                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4349         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4350                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4351         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4352                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4353         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4354                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4355         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4356                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4357 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4358
4359         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4360                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4361                 i40e_dev_handle_vfr_event(dev);
4362         }
4363         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4364                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4365                 i40e_dev_handle_aq_msg(dev);
4366         }
4367
4368         /* Link Status Change interrupt */
4369         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4370 #define I40E_US_PER_SECOND 1000000
4371                 struct rte_eth_link link;
4372
4373                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4374                 memset(&link, 0, sizeof(link));
4375                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4376                 i40e_dev_link_update(dev, 0);
4377
4378                 /*
4379                  * For link up interrupt, it needs to wait 1 second to let the
4380                  * hardware be a stable state. Otherwise several consecutive
4381                  * interrupts can be observed.
4382                  * For link down interrupt, no need to wait.
4383                  */
4384                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4385                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4386                         return;
4387                 else
4388                         _rte_eth_dev_callback_process(dev,
4389                                 RTE_ETH_EVENT_INTR_LSC);
4390         }
4391
4392 done:
4393         /* Enable interrupt */
4394         i40e_pf_enable_irq0(hw);
4395         rte_intr_enable(&(dev->pci_dev->intr_handle));
4396 }
4397
4398 static int
4399 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4400                          struct i40e_macvlan_filter *filter,
4401                          int total)
4402 {
4403         int ele_num, ele_buff_size;
4404         int num, actual_num, i;
4405         uint16_t flags;
4406         int ret = I40E_SUCCESS;
4407         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4408         struct i40e_aqc_add_macvlan_element_data *req_list;
4409
4410         if (filter == NULL  || total == 0)
4411                 return I40E_ERR_PARAM;
4412         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4413         ele_buff_size = hw->aq.asq_buf_size;
4414
4415         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4416         if (req_list == NULL) {
4417                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4418                 return I40E_ERR_NO_MEMORY;
4419         }
4420
4421         num = 0;
4422         do {
4423                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4424                 memset(req_list, 0, ele_buff_size);
4425
4426                 for (i = 0; i < actual_num; i++) {
4427                         (void)rte_memcpy(req_list[i].mac_addr,
4428                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4429                         req_list[i].vlan_tag =
4430                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4431
4432                         switch (filter[num + i].filter_type) {
4433                         case RTE_MAC_PERFECT_MATCH:
4434                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4435                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4436                                 break;
4437                         case RTE_MACVLAN_PERFECT_MATCH:
4438                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4439                                 break;
4440                         case RTE_MAC_HASH_MATCH:
4441                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4442                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4443                                 break;
4444                         case RTE_MACVLAN_HASH_MATCH:
4445                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4446                                 break;
4447                         default:
4448                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4449                                 ret = I40E_ERR_PARAM;
4450                                 goto DONE;
4451                         }
4452
4453                         req_list[i].queue_number = 0;
4454
4455                         req_list[i].flags = rte_cpu_to_le_16(flags);
4456                 }
4457
4458                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4459                                                 actual_num, NULL);
4460                 if (ret != I40E_SUCCESS) {
4461                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4462                         goto DONE;
4463                 }
4464                 num += actual_num;
4465         } while (num < total);
4466
4467 DONE:
4468         rte_free(req_list);
4469         return ret;
4470 }
4471
4472 static int
4473 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4474                             struct i40e_macvlan_filter *filter,
4475                             int total)
4476 {
4477         int ele_num, ele_buff_size;
4478         int num, actual_num, i;
4479         uint16_t flags;
4480         int ret = I40E_SUCCESS;
4481         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4482         struct i40e_aqc_remove_macvlan_element_data *req_list;
4483
4484         if (filter == NULL  || total == 0)
4485                 return I40E_ERR_PARAM;
4486
4487         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4488         ele_buff_size = hw->aq.asq_buf_size;
4489
4490         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4491         if (req_list == NULL) {
4492                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4493                 return I40E_ERR_NO_MEMORY;
4494         }
4495
4496         num = 0;
4497         do {
4498                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4499                 memset(req_list, 0, ele_buff_size);
4500
4501                 for (i = 0; i < actual_num; i++) {
4502                         (void)rte_memcpy(req_list[i].mac_addr,
4503                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4504                         req_list[i].vlan_tag =
4505                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4506
4507                         switch (filter[num + i].filter_type) {
4508                         case RTE_MAC_PERFECT_MATCH:
4509                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4510                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4511                                 break;
4512                         case RTE_MACVLAN_PERFECT_MATCH:
4513                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4514                                 break;
4515                         case RTE_MAC_HASH_MATCH:
4516                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4517                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4518                                 break;
4519                         case RTE_MACVLAN_HASH_MATCH:
4520                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4521                                 break;
4522                         default:
4523                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4524                                 ret = I40E_ERR_PARAM;
4525                                 goto DONE;
4526                         }
4527                         req_list[i].flags = rte_cpu_to_le_16(flags);
4528                 }
4529
4530                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4531                                                 actual_num, NULL);
4532                 if (ret != I40E_SUCCESS) {
4533                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4534                         goto DONE;
4535                 }
4536                 num += actual_num;
4537         } while (num < total);
4538
4539 DONE:
4540         rte_free(req_list);
4541         return ret;
4542 }
4543
4544 /* Find out specific MAC filter */
4545 static struct i40e_mac_filter *
4546 i40e_find_mac_filter(struct i40e_vsi *vsi,
4547                          struct ether_addr *macaddr)
4548 {
4549         struct i40e_mac_filter *f;
4550
4551         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4552                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4553                         return f;
4554         }
4555
4556         return NULL;
4557 }
4558
4559 static bool
4560 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4561                          uint16_t vlan_id)
4562 {
4563         uint32_t vid_idx, vid_bit;
4564
4565         if (vlan_id > ETH_VLAN_ID_MAX)
4566                 return 0;
4567
4568         vid_idx = I40E_VFTA_IDX(vlan_id);
4569         vid_bit = I40E_VFTA_BIT(vlan_id);
4570
4571         if (vsi->vfta[vid_idx] & vid_bit)
4572                 return 1;
4573         else
4574                 return 0;
4575 }
4576
4577 static void
4578 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4579                          uint16_t vlan_id, bool on)
4580 {
4581         uint32_t vid_idx, vid_bit;
4582
4583         if (vlan_id > ETH_VLAN_ID_MAX)
4584                 return;
4585
4586         vid_idx = I40E_VFTA_IDX(vlan_id);
4587         vid_bit = I40E_VFTA_BIT(vlan_id);
4588
4589         if (on)
4590                 vsi->vfta[vid_idx] |= vid_bit;
4591         else
4592                 vsi->vfta[vid_idx] &= ~vid_bit;
4593 }
4594
4595 /**
4596  * Find all vlan options for specific mac addr,
4597  * return with actual vlan found.
4598  */
4599 static inline int
4600 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4601                            struct i40e_macvlan_filter *mv_f,
4602                            int num, struct ether_addr *addr)
4603 {
4604         int i;
4605         uint32_t j, k;
4606
4607         /**
4608          * Not to use i40e_find_vlan_filter to decrease the loop time,
4609          * although the code looks complex.
4610           */
4611         if (num < vsi->vlan_num)
4612                 return I40E_ERR_PARAM;
4613
4614         i = 0;
4615         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4616                 if (vsi->vfta[j]) {
4617                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4618                                 if (vsi->vfta[j] & (1 << k)) {
4619                                         if (i > num - 1) {
4620                                                 PMD_DRV_LOG(ERR, "vlan number "
4621                                                             "not match");
4622                                                 return I40E_ERR_PARAM;
4623                                         }
4624                                         (void)rte_memcpy(&mv_f[i].macaddr,
4625                                                         addr, ETH_ADDR_LEN);
4626                                         mv_f[i].vlan_id =
4627                                                 j * I40E_UINT32_BIT_SIZE + k;
4628                                         i++;
4629                                 }
4630                         }
4631                 }
4632         }
4633         return I40E_SUCCESS;
4634 }
4635
4636 static inline int
4637 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4638                            struct i40e_macvlan_filter *mv_f,
4639                            int num,
4640                            uint16_t vlan)
4641 {
4642         int i = 0;
4643         struct i40e_mac_filter *f;
4644
4645         if (num < vsi->mac_num)
4646                 return I40E_ERR_PARAM;
4647
4648         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4649                 if (i > num - 1) {
4650                         PMD_DRV_LOG(ERR, "buffer number not match");
4651                         return I40E_ERR_PARAM;
4652                 }
4653                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4654                                 ETH_ADDR_LEN);
4655                 mv_f[i].vlan_id = vlan;
4656                 mv_f[i].filter_type = f->mac_info.filter_type;
4657                 i++;
4658         }
4659
4660         return I40E_SUCCESS;
4661 }
4662
4663 static int
4664 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4665 {
4666         int i, num;
4667         struct i40e_mac_filter *f;
4668         struct i40e_macvlan_filter *mv_f;
4669         int ret = I40E_SUCCESS;
4670
4671         if (vsi == NULL || vsi->mac_num == 0)
4672                 return I40E_ERR_PARAM;
4673
4674         /* Case that no vlan is set */
4675         if (vsi->vlan_num == 0)
4676                 num = vsi->mac_num;
4677         else
4678                 num = vsi->mac_num * vsi->vlan_num;
4679
4680         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4681         if (mv_f == NULL) {
4682                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4683                 return I40E_ERR_NO_MEMORY;
4684         }
4685
4686         i = 0;
4687         if (vsi->vlan_num == 0) {
4688                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4689                         (void)rte_memcpy(&mv_f[i].macaddr,
4690                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4691                         mv_f[i].vlan_id = 0;
4692                         i++;
4693                 }
4694         } else {
4695                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4696                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4697                                         vsi->vlan_num, &f->mac_info.mac_addr);
4698                         if (ret != I40E_SUCCESS)
4699                                 goto DONE;
4700                         i += vsi->vlan_num;
4701                 }
4702         }
4703
4704         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4705 DONE:
4706         rte_free(mv_f);
4707
4708         return ret;
4709 }
4710
4711 int
4712 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4713 {
4714         struct i40e_macvlan_filter *mv_f;
4715         int mac_num;
4716         int ret = I40E_SUCCESS;
4717
4718         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4719                 return I40E_ERR_PARAM;
4720
4721         /* If it's already set, just return */
4722         if (i40e_find_vlan_filter(vsi,vlan))
4723                 return I40E_SUCCESS;
4724
4725         mac_num = vsi->mac_num;
4726
4727         if (mac_num == 0) {
4728                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4729                 return I40E_ERR_PARAM;
4730         }
4731
4732         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4733
4734         if (mv_f == NULL) {
4735                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4736                 return I40E_ERR_NO_MEMORY;
4737         }
4738
4739         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4740
4741         if (ret != I40E_SUCCESS)
4742                 goto DONE;
4743
4744         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4745
4746         if (ret != I40E_SUCCESS)
4747                 goto DONE;
4748
4749         i40e_set_vlan_filter(vsi, vlan, 1);
4750
4751         vsi->vlan_num++;
4752         ret = I40E_SUCCESS;
4753 DONE:
4754         rte_free(mv_f);
4755         return ret;
4756 }
4757
4758 int
4759 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4760 {
4761         struct i40e_macvlan_filter *mv_f;
4762         int mac_num;
4763         int ret = I40E_SUCCESS;
4764
4765         /**
4766          * Vlan 0 is the generic filter for untagged packets
4767          * and can't be removed.
4768          */
4769         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4770                 return I40E_ERR_PARAM;
4771
4772         /* If can't find it, just return */
4773         if (!i40e_find_vlan_filter(vsi, vlan))
4774                 return I40E_ERR_PARAM;
4775
4776         mac_num = vsi->mac_num;
4777
4778         if (mac_num == 0) {
4779                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4780                 return I40E_ERR_PARAM;
4781         }
4782
4783         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4784
4785         if (mv_f == NULL) {
4786                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4787                 return I40E_ERR_NO_MEMORY;
4788         }
4789
4790         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4791
4792         if (ret != I40E_SUCCESS)
4793                 goto DONE;
4794
4795         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4796
4797         if (ret != I40E_SUCCESS)
4798                 goto DONE;
4799
4800         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4801         if (vsi->vlan_num == 1) {
4802                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4803                 if (ret != I40E_SUCCESS)
4804                         goto DONE;
4805
4806                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4807                 if (ret != I40E_SUCCESS)
4808                         goto DONE;
4809         }
4810
4811         i40e_set_vlan_filter(vsi, vlan, 0);
4812
4813         vsi->vlan_num--;
4814         ret = I40E_SUCCESS;
4815 DONE:
4816         rte_free(mv_f);
4817         return ret;
4818 }
4819
4820 int
4821 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4822 {
4823         struct i40e_mac_filter *f;
4824         struct i40e_macvlan_filter *mv_f;
4825         int i, vlan_num = 0;
4826         int ret = I40E_SUCCESS;
4827
4828         /* If it's add and we've config it, return */
4829         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4830         if (f != NULL)
4831                 return I40E_SUCCESS;
4832         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4833                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4834
4835                 /**
4836                  * If vlan_num is 0, that's the first time to add mac,
4837                  * set mask for vlan_id 0.
4838                  */
4839                 if (vsi->vlan_num == 0) {
4840                         i40e_set_vlan_filter(vsi, 0, 1);
4841                         vsi->vlan_num = 1;
4842                 }
4843                 vlan_num = vsi->vlan_num;
4844         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4845                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4846                 vlan_num = 1;
4847
4848         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4849         if (mv_f == NULL) {
4850                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4851                 return I40E_ERR_NO_MEMORY;
4852         }
4853
4854         for (i = 0; i < vlan_num; i++) {
4855                 mv_f[i].filter_type = mac_filter->filter_type;
4856                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4857                                 ETH_ADDR_LEN);
4858         }
4859
4860         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4861                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4862                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4863                                         &mac_filter->mac_addr);
4864                 if (ret != I40E_SUCCESS)
4865                         goto DONE;
4866         }
4867
4868         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4869         if (ret != I40E_SUCCESS)
4870                 goto DONE;
4871
4872         /* Add the mac addr into mac list */
4873         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4874         if (f == NULL) {
4875                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4876                 ret = I40E_ERR_NO_MEMORY;
4877                 goto DONE;
4878         }
4879         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4880                         ETH_ADDR_LEN);
4881         f->mac_info.filter_type = mac_filter->filter_type;
4882         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4883         vsi->mac_num++;
4884
4885         ret = I40E_SUCCESS;
4886 DONE:
4887         rte_free(mv_f);
4888
4889         return ret;
4890 }
4891
4892 int
4893 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4894 {
4895         struct i40e_mac_filter *f;
4896         struct i40e_macvlan_filter *mv_f;
4897         int i, vlan_num;
4898         enum rte_mac_filter_type filter_type;
4899         int ret = I40E_SUCCESS;
4900
4901         /* Can't find it, return an error */
4902         f = i40e_find_mac_filter(vsi, addr);
4903         if (f == NULL)
4904                 return I40E_ERR_PARAM;
4905
4906         vlan_num = vsi->vlan_num;
4907         filter_type = f->mac_info.filter_type;
4908         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4909                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4910                 if (vlan_num == 0) {
4911                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4912                         return I40E_ERR_PARAM;
4913                 }
4914         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4915                         filter_type == RTE_MAC_HASH_MATCH)
4916                 vlan_num = 1;
4917
4918         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4919         if (mv_f == NULL) {
4920                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4921                 return I40E_ERR_NO_MEMORY;
4922         }
4923
4924         for (i = 0; i < vlan_num; i++) {
4925                 mv_f[i].filter_type = filter_type;
4926                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4927                                 ETH_ADDR_LEN);
4928         }
4929         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4930                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4931                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4932                 if (ret != I40E_SUCCESS)
4933                         goto DONE;
4934         }
4935
4936         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4937         if (ret != I40E_SUCCESS)
4938                 goto DONE;
4939
4940         /* Remove the mac addr into mac list */
4941         TAILQ_REMOVE(&vsi->mac_list, f, next);
4942         rte_free(f);
4943         vsi->mac_num--;
4944
4945         ret = I40E_SUCCESS;
4946 DONE:
4947         rte_free(mv_f);
4948         return ret;
4949 }
4950
4951 /* Configure hash enable flags for RSS */
4952 uint64_t
4953 i40e_config_hena(uint64_t flags)
4954 {
4955         uint64_t hena = 0;
4956
4957         if (!flags)
4958                 return hena;
4959
4960         if (flags & ETH_RSS_FRAG_IPV4)
4961                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4962         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4963                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4964         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4965                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4966         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4967                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4968         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4969                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4970         if (flags & ETH_RSS_FRAG_IPV6)
4971                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4972         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4973                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4974         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4975                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4976         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4977                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4978         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4979                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4980         if (flags & ETH_RSS_L2_PAYLOAD)
4981                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4982
4983         return hena;
4984 }
4985
4986 /* Parse the hash enable flags */
4987 uint64_t
4988 i40e_parse_hena(uint64_t flags)
4989 {
4990         uint64_t rss_hf = 0;
4991
4992         if (!flags)
4993                 return rss_hf;
4994         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4995                 rss_hf |= ETH_RSS_FRAG_IPV4;
4996         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4997                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4998         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4999                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5000         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5001                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5002         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5003                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5004         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5005                 rss_hf |= ETH_RSS_FRAG_IPV6;
5006         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5007                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5008         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5009                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5010         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5011                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5012         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5013                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5014         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5015                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5016
5017         return rss_hf;
5018 }
5019
5020 /* Disable RSS */
5021 static void
5022 i40e_pf_disable_rss(struct i40e_pf *pf)
5023 {
5024         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5025         uint64_t hena;
5026
5027         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5028         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5029         hena &= ~I40E_RSS_HENA_ALL;
5030         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5031         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5032         I40E_WRITE_FLUSH(hw);
5033 }
5034
5035 static int
5036 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
5037 {
5038         uint32_t *hash_key;
5039         uint8_t hash_key_len;
5040         uint64_t rss_hf;
5041         uint16_t i;
5042         uint64_t hena;
5043
5044         hash_key = (uint32_t *)(rss_conf->rss_key);
5045         hash_key_len = rss_conf->rss_key_len;
5046         if (hash_key != NULL && hash_key_len >=
5047                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5048                 /* Fill in RSS hash key */
5049                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5050                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5051         }
5052
5053         rss_hf = rss_conf->rss_hf;
5054         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5055         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5056         hena &= ~I40E_RSS_HENA_ALL;
5057         hena |= i40e_config_hena(rss_hf);
5058         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5059         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5060         I40E_WRITE_FLUSH(hw);
5061
5062         return 0;
5063 }
5064
5065 static int
5066 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5067                          struct rte_eth_rss_conf *rss_conf)
5068 {
5069         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5071         uint64_t hena;
5072
5073         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5074         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5075         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5076                 if (rss_hf != 0) /* Enable RSS */
5077                         return -EINVAL;
5078                 return 0; /* Nothing to do */
5079         }
5080         /* RSS enabled */
5081         if (rss_hf == 0) /* Disable RSS */
5082                 return -EINVAL;
5083
5084         return i40e_hw_rss_hash_set(hw, rss_conf);
5085 }
5086
5087 static int
5088 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5089                            struct rte_eth_rss_conf *rss_conf)
5090 {
5091         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5092         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
5093         uint64_t hena;
5094         uint16_t i;
5095
5096         if (hash_key != NULL) {
5097                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5098                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5099                 rss_conf->rss_key_len = i * sizeof(uint32_t);
5100         }
5101         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5102         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5103         rss_conf->rss_hf = i40e_parse_hena(hena);
5104
5105         return 0;
5106 }
5107
5108 static int
5109 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5110 {
5111         switch (filter_type) {
5112         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5113                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5114                 break;
5115         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5116                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5117                 break;
5118         case RTE_TUNNEL_FILTER_IMAC_TENID:
5119                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5120                 break;
5121         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5122                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5123                 break;
5124         case ETH_TUNNEL_FILTER_IMAC:
5125                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5126                 break;
5127         default:
5128                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5129                 return -EINVAL;
5130         }
5131
5132         return 0;
5133 }
5134
5135 static int
5136 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5137                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5138                         uint8_t add)
5139 {
5140         uint16_t ip_type;
5141         uint8_t tun_type = 0;
5142         int val, ret = 0;
5143         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5144         struct i40e_vsi *vsi = pf->main_vsi;
5145         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5146         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5147
5148         cld_filter = rte_zmalloc("tunnel_filter",
5149                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5150                 0);
5151
5152         if (NULL == cld_filter) {
5153                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5154                 return -EINVAL;
5155         }
5156         pfilter = cld_filter;
5157
5158         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5159                         sizeof(struct ether_addr));
5160         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5161                         sizeof(struct ether_addr));
5162
5163         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5164         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5165                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5166                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5167                                 &tunnel_filter->ip_addr,
5168                                 sizeof(pfilter->ipaddr.v4.data));
5169         } else {
5170                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5171                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5172                                 &tunnel_filter->ip_addr,
5173                                 sizeof(pfilter->ipaddr.v6.data));
5174         }
5175
5176         /* check tunneled type */
5177         switch (tunnel_filter->tunnel_type) {
5178         case RTE_TUNNEL_TYPE_VXLAN:
5179                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5180                 break;
5181         case RTE_TUNNEL_TYPE_NVGRE:
5182                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5183                 break;
5184         default:
5185                 /* Other tunnel types is not supported. */
5186                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5187                 rte_free(cld_filter);
5188                 return -EINVAL;
5189         }
5190
5191         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5192                                                 &pfilter->flags);
5193         if (val < 0) {
5194                 rte_free(cld_filter);
5195                 return -EINVAL;
5196         }
5197
5198         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5199                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5200         pfilter->tenant_id = tunnel_filter->tenant_id;
5201         pfilter->queue_number = tunnel_filter->queue_id;
5202
5203         if (add)
5204                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5205         else
5206                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5207                                                 cld_filter, 1);
5208
5209         rte_free(cld_filter);
5210         return ret;
5211 }
5212
5213 static int
5214 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5215 {
5216         uint8_t i;
5217
5218         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5219                 if (pf->vxlan_ports[i] == port)
5220                         return i;
5221         }
5222
5223         return -1;
5224 }
5225
5226 static int
5227 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5228 {
5229         int  idx, ret;
5230         uint8_t filter_idx;
5231         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5232
5233         idx = i40e_get_vxlan_port_idx(pf, port);
5234
5235         /* Check if port already exists */
5236         if (idx >= 0) {
5237                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5238                 return -EINVAL;
5239         }
5240
5241         /* Now check if there is space to add the new port */
5242         idx = i40e_get_vxlan_port_idx(pf, 0);
5243         if (idx < 0) {
5244                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5245                         "not adding port %d", port);
5246                 return -ENOSPC;
5247         }
5248
5249         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5250                                         &filter_idx, NULL);
5251         if (ret < 0) {
5252                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5253                 return -1;
5254         }
5255
5256         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5257                          port,  filter_idx);
5258
5259         /* New port: add it and mark its index in the bitmap */
5260         pf->vxlan_ports[idx] = port;
5261         pf->vxlan_bitmap |= (1 << idx);
5262
5263         if (!(pf->flags & I40E_FLAG_VXLAN))
5264                 pf->flags |= I40E_FLAG_VXLAN;
5265
5266         return 0;
5267 }
5268
5269 static int
5270 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5271 {
5272         int idx;
5273         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5274
5275         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5276                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5277                 return -EINVAL;
5278         }
5279
5280         idx = i40e_get_vxlan_port_idx(pf, port);
5281
5282         if (idx < 0) {
5283                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5284                 return -EINVAL;
5285         }
5286
5287         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5288                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5289                 return -1;
5290         }
5291
5292         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5293                         port, idx);
5294
5295         pf->vxlan_ports[idx] = 0;
5296         pf->vxlan_bitmap &= ~(1 << idx);
5297
5298         if (!pf->vxlan_bitmap)
5299                 pf->flags &= ~I40E_FLAG_VXLAN;
5300
5301         return 0;
5302 }
5303
5304 /* Add UDP tunneling port */
5305 static int
5306 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5307                         struct rte_eth_udp_tunnel *udp_tunnel)
5308 {
5309         int ret = 0;
5310         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5311
5312         if (udp_tunnel == NULL)
5313                 return -EINVAL;
5314
5315         switch (udp_tunnel->prot_type) {
5316         case RTE_TUNNEL_TYPE_VXLAN:
5317                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5318                 break;
5319
5320         case RTE_TUNNEL_TYPE_GENEVE:
5321         case RTE_TUNNEL_TYPE_TEREDO:
5322                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5323                 ret = -1;
5324                 break;
5325
5326         default:
5327                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5328                 ret = -1;
5329                 break;
5330         }
5331
5332         return ret;
5333 }
5334
5335 /* Remove UDP tunneling port */
5336 static int
5337 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5338                         struct rte_eth_udp_tunnel *udp_tunnel)
5339 {
5340         int ret = 0;
5341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5342
5343         if (udp_tunnel == NULL)
5344                 return -EINVAL;
5345
5346         switch (udp_tunnel->prot_type) {
5347         case RTE_TUNNEL_TYPE_VXLAN:
5348                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5349                 break;
5350         case RTE_TUNNEL_TYPE_GENEVE:
5351         case RTE_TUNNEL_TYPE_TEREDO:
5352                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5353                 ret = -1;
5354                 break;
5355         default:
5356                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5357                 ret = -1;
5358                 break;
5359         }
5360
5361         return ret;
5362 }
5363
5364 /* Calculate the maximum number of contiguous PF queues that are configured */
5365 static int
5366 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5367 {
5368         struct rte_eth_dev_data *data = pf->dev_data;
5369         int i, num;
5370         struct i40e_rx_queue *rxq;
5371
5372         num = 0;
5373         for (i = 0; i < pf->lan_nb_qps; i++) {
5374                 rxq = data->rx_queues[i];
5375                 if (rxq && rxq->q_set)
5376                         num++;
5377                 else
5378                         break;
5379         }
5380
5381         return num;
5382 }
5383
5384 /* Configure RSS */
5385 static int
5386 i40e_pf_config_rss(struct i40e_pf *pf)
5387 {
5388         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5389         struct rte_eth_rss_conf rss_conf;
5390         uint32_t i, lut = 0;
5391         uint16_t j, num;
5392
5393         /*
5394          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5395          * It's necessary to calulate the actual PF queues that are configured.
5396          */
5397         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5398                 num = i40e_pf_calc_configured_queues_num(pf);
5399                 num = i40e_align_floor(num);
5400         } else
5401                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5402
5403         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5404                         num);
5405
5406         if (num == 0) {
5407                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5408                 return -ENOTSUP;
5409         }
5410
5411         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5412                 if (j == num)
5413                         j = 0;
5414                 lut = (lut << 8) | (j & ((0x1 <<
5415                         hw->func_caps.rss_table_entry_width) - 1));
5416                 if ((i & 3) == 3)
5417                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5418         }
5419
5420         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5421         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5422                 i40e_pf_disable_rss(pf);
5423                 return 0;
5424         }
5425         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5426                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5427                 /* Random default keys */
5428                 static uint32_t rss_key_default[] = {0x6b793944,
5429                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5430                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5431                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5432
5433                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5434                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5435                                                         sizeof(uint32_t);
5436         }
5437
5438         return i40e_hw_rss_hash_set(hw, &rss_conf);
5439 }
5440
5441 static int
5442 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5443                         struct rte_eth_tunnel_filter_conf *filter)
5444 {
5445         if (pf == NULL || filter == NULL) {
5446                 PMD_DRV_LOG(ERR, "Invalid parameter");
5447                 return -EINVAL;
5448         }
5449
5450         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5451                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5452                 return -EINVAL;
5453         }
5454
5455         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5456                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5457                 return -EINVAL;
5458         }
5459
5460         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5461                 (is_zero_ether_addr(filter->outer_mac))) {
5462                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5463                 return -EINVAL;
5464         }
5465
5466         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5467                 (is_zero_ether_addr(filter->inner_mac))) {
5468                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5469                 return -EINVAL;
5470         }
5471
5472         return 0;
5473 }
5474
5475 static int
5476 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5477                         void *arg)
5478 {
5479         struct rte_eth_tunnel_filter_conf *filter;
5480         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5481         int ret = I40E_SUCCESS;
5482
5483         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5484
5485         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5486                 return I40E_ERR_PARAM;
5487
5488         switch (filter_op) {
5489         case RTE_ETH_FILTER_NOP:
5490                 if (!(pf->flags & I40E_FLAG_VXLAN))
5491                         ret = I40E_NOT_SUPPORTED;
5492         case RTE_ETH_FILTER_ADD:
5493                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5494                 break;
5495         case RTE_ETH_FILTER_DELETE:
5496                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5497                 break;
5498         default:
5499                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5500                 ret = I40E_ERR_PARAM;
5501                 break;
5502         }
5503
5504         return ret;
5505 }
5506
5507 static int
5508 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5509 {
5510         int ret = 0;
5511         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5512
5513         /* RSS setup */
5514         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5515                 ret = i40e_pf_config_rss(pf);
5516         else
5517                 i40e_pf_disable_rss(pf);
5518
5519         return ret;
5520 }
5521
5522 /* Get the symmetric hash enable configurations per port */
5523 static void
5524 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5525 {
5526         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5527
5528         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5529 }
5530
5531 /* Set the symmetric hash enable configurations per port */
5532 static void
5533 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5534 {
5535         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5536
5537         if (enable > 0) {
5538                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5539                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5540                                                         "been enabled");
5541                         return;
5542                 }
5543                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5544         } else {
5545                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5546                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5547                                                         "been disabled");
5548                         return;
5549                 }
5550                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5551         }
5552         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5553         I40E_WRITE_FLUSH(hw);
5554 }
5555
5556 /*
5557  * Get global configurations of hash function type and symmetric hash enable
5558  * per flow type (pctype). Note that global configuration means it affects all
5559  * the ports on the same NIC.
5560  */
5561 static int
5562 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5563                                    struct rte_eth_hash_global_conf *g_cfg)
5564 {
5565         uint32_t reg, mask = I40E_FLOW_TYPES;
5566         uint16_t i;
5567         enum i40e_filter_pctype pctype;
5568
5569         memset(g_cfg, 0, sizeof(*g_cfg));
5570         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5571         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5572                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5573         else
5574                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5575         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5576                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5577
5578         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5579                 if (!(mask & (1UL << i)))
5580                         continue;
5581                 mask &= ~(1UL << i);
5582                 /* Bit set indicats the coresponding flow type is supported */
5583                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5584                 pctype = i40e_flowtype_to_pctype(i);
5585                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5586                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5587                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5588         }
5589
5590         return 0;
5591 }
5592
5593 static int
5594 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5595 {
5596         uint32_t i;
5597         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5598
5599         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5600                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5601                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5602                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5603                                                 g_cfg->hash_func);
5604                 return -EINVAL;
5605         }
5606
5607         /*
5608          * As i40e supports less than 32 flow types, only first 32 bits need to
5609          * be checked.
5610          */
5611         mask0 = g_cfg->valid_bit_mask[0];
5612         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5613                 if (i == 0) {
5614                         /* Check if any unsupported flow type configured */
5615                         if ((mask0 | i40e_mask) ^ i40e_mask)
5616                                 goto mask_err;
5617                 } else {
5618                         if (g_cfg->valid_bit_mask[i])
5619                                 goto mask_err;
5620                 }
5621         }
5622
5623         return 0;
5624
5625 mask_err:
5626         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5627
5628         return -EINVAL;
5629 }
5630
5631 /*
5632  * Set global configurations of hash function type and symmetric hash enable
5633  * per flow type (pctype). Note any modifying global configuration will affect
5634  * all the ports on the same NIC.
5635  */
5636 static int
5637 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5638                                    struct rte_eth_hash_global_conf *g_cfg)
5639 {
5640         int ret;
5641         uint16_t i;
5642         uint32_t reg;
5643         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5644         enum i40e_filter_pctype pctype;
5645
5646         /* Check the input parameters */
5647         ret = i40e_hash_global_config_check(g_cfg);
5648         if (ret < 0)
5649                 return ret;
5650
5651         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5652                 if (!(mask0 & (1UL << i)))
5653                         continue;
5654                 mask0 &= ~(1UL << i);
5655                 pctype = i40e_flowtype_to_pctype(i);
5656                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5657                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5658                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5659         }
5660
5661         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5662         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5663                 /* Toeplitz */
5664                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5665                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5666                                                                 "Toeplitz");
5667                         goto out;
5668                 }
5669                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5670         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5671                 /* Simple XOR */
5672                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5673                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5674                                                         "Simple XOR");
5675                         goto out;
5676                 }
5677                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5678         } else
5679                 /* Use the default, and keep it as it is */
5680                 goto out;
5681
5682         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5683
5684 out:
5685         I40E_WRITE_FLUSH(hw);
5686
5687         return 0;
5688 }
5689
5690 static int
5691 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5692 {
5693         int ret = 0;
5694
5695         if (!hw || !info) {
5696                 PMD_DRV_LOG(ERR, "Invalid pointer");
5697                 return -EFAULT;
5698         }
5699
5700         switch (info->info_type) {
5701         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5702                 i40e_get_symmetric_hash_enable_per_port(hw,
5703                                         &(info->info.enable));
5704                 break;
5705         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5706                 ret = i40e_get_hash_filter_global_config(hw,
5707                                 &(info->info.global_conf));
5708                 break;
5709         default:
5710                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5711                                                         info->info_type);
5712                 ret = -EINVAL;
5713                 break;
5714         }
5715
5716         return ret;
5717 }
5718
5719 static int
5720 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5721 {
5722         int ret = 0;
5723
5724         if (!hw || !info) {
5725                 PMD_DRV_LOG(ERR, "Invalid pointer");
5726                 return -EFAULT;
5727         }
5728
5729         switch (info->info_type) {
5730         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5731                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5732                 break;
5733         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5734                 ret = i40e_set_hash_filter_global_config(hw,
5735                                 &(info->info.global_conf));
5736                 break;
5737         default:
5738                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5739                                                         info->info_type);
5740                 ret = -EINVAL;
5741                 break;
5742         }
5743
5744         return ret;
5745 }
5746
5747 /* Operations for hash function */
5748 static int
5749 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5750                       enum rte_filter_op filter_op,
5751                       void *arg)
5752 {
5753         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5754         int ret = 0;
5755
5756         switch (filter_op) {
5757         case RTE_ETH_FILTER_NOP:
5758                 break;
5759         case RTE_ETH_FILTER_GET:
5760                 ret = i40e_hash_filter_get(hw,
5761                         (struct rte_eth_hash_filter_info *)arg);
5762                 break;
5763         case RTE_ETH_FILTER_SET:
5764                 ret = i40e_hash_filter_set(hw,
5765                         (struct rte_eth_hash_filter_info *)arg);
5766                 break;
5767         default:
5768                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5769                                                                 filter_op);
5770                 ret = -ENOTSUP;
5771                 break;
5772         }
5773
5774         return ret;
5775 }
5776
5777 /*
5778  * Configure ethertype filter, which can director packet by filtering
5779  * with mac address and ether_type or only ether_type
5780  */
5781 static int
5782 i40e_ethertype_filter_set(struct i40e_pf *pf,
5783                         struct rte_eth_ethertype_filter *filter,
5784                         bool add)
5785 {
5786         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5787         struct i40e_control_filter_stats stats;
5788         uint16_t flags = 0;
5789         int ret;
5790
5791         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5792                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5793                 return -EINVAL;
5794         }
5795         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5796                 filter->ether_type == ETHER_TYPE_IPv6) {
5797                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5798                         " control packet filter.", filter->ether_type);
5799                 return -EINVAL;
5800         }
5801         if (filter->ether_type == ETHER_TYPE_VLAN)
5802                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5803                         " not supported.");
5804
5805         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5806                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5807         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5808                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5809         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5810
5811         memset(&stats, 0, sizeof(stats));
5812         ret = i40e_aq_add_rem_control_packet_filter(hw,
5813                         filter->mac_addr.addr_bytes,
5814                         filter->ether_type, flags,
5815                         pf->main_vsi->seid,
5816                         filter->queue, add, &stats, NULL);
5817
5818         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5819                          " mac_etype_used = %u, etype_used = %u,"
5820                          " mac_etype_free = %u, etype_free = %u\n",
5821                          ret, stats.mac_etype_used, stats.etype_used,
5822                          stats.mac_etype_free, stats.etype_free);
5823         if (ret < 0)
5824                 return -ENOSYS;
5825         return 0;
5826 }
5827
5828 /*
5829  * Handle operations for ethertype filter.
5830  */
5831 static int
5832 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5833                                 enum rte_filter_op filter_op,
5834                                 void *arg)
5835 {
5836         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5837         int ret = 0;
5838
5839         if (filter_op == RTE_ETH_FILTER_NOP)
5840                 return ret;
5841
5842         if (arg == NULL) {
5843                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5844                             filter_op);
5845                 return -EINVAL;
5846         }
5847
5848         switch (filter_op) {
5849         case RTE_ETH_FILTER_ADD:
5850                 ret = i40e_ethertype_filter_set(pf,
5851                         (struct rte_eth_ethertype_filter *)arg,
5852                         TRUE);
5853                 break;
5854         case RTE_ETH_FILTER_DELETE:
5855                 ret = i40e_ethertype_filter_set(pf,
5856                         (struct rte_eth_ethertype_filter *)arg,
5857                         FALSE);
5858                 break;
5859         default:
5860                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5861                 ret = -ENOSYS;
5862                 break;
5863         }
5864         return ret;
5865 }
5866
5867 static int
5868 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5869                      enum rte_filter_type filter_type,
5870                      enum rte_filter_op filter_op,
5871                      void *arg)
5872 {
5873         int ret = 0;
5874
5875         if (dev == NULL)
5876                 return -EINVAL;
5877
5878         switch (filter_type) {
5879         case RTE_ETH_FILTER_HASH:
5880                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5881                 break;
5882         case RTE_ETH_FILTER_MACVLAN:
5883                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5884                 break;
5885         case RTE_ETH_FILTER_ETHERTYPE:
5886                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5887                 break;
5888         case RTE_ETH_FILTER_TUNNEL:
5889                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5890                 break;
5891         case RTE_ETH_FILTER_FDIR:
5892                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5893                 break;
5894         default:
5895                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5896                                                         filter_type);
5897                 ret = -EINVAL;
5898                 break;
5899         }
5900
5901         return ret;
5902 }
5903
5904 /*
5905  * As some registers wouldn't be reset unless a global hardware reset,
5906  * hardware initialization is needed to put those registers into an
5907  * expected initial state.
5908  */
5909 static void
5910 i40e_hw_init(struct i40e_hw *hw)
5911 {
5912         /* clear the PF Queue Filter control register */
5913         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5914
5915         /* Disable symmetric hash per port */
5916         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5917 }
5918
5919 enum i40e_filter_pctype
5920 i40e_flowtype_to_pctype(uint16_t flow_type)
5921 {
5922         static const enum i40e_filter_pctype pctype_table[] = {
5923                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5924                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5925                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5926                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5927                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5928                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5929                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5930                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5931                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5932                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5933                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5934                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5935                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5936                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5937                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5938                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5939                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5940                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5941                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5942         };
5943
5944         return pctype_table[flow_type];
5945 }
5946
5947 uint16_t
5948 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5949 {
5950         static const uint16_t flowtype_table[] = {
5951                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5952                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5953                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5954                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5955                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5956                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5957                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5958                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5959                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5960                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5961                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5962                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5963                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5964                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5965                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5966                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5967                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5968                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5969                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5970         };
5971
5972         return flowtype_table[pctype];
5973 }
5974
5975 /*
5976  * On X710, performance number is far from the expectation on recent firmware
5977  * versions; on XL710, performance number is also far from the expectation on
5978  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5979  * mode is enabled and port MAC address is equal to the packet destination MAC
5980  * address. The fix for this issue may not be integrated in the following
5981  * firmware version. So the workaround in software driver is needed. It needs
5982  * to modify the initial values of 3 internal only registers for both X710 and
5983  * XL710. Note that the values for X710 or XL710 could be different, and the
5984  * workaround can be removed when it is fixed in firmware in the future.
5985  */
5986
5987 /* For both X710 and XL710 */
5988 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5989 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5990
5991 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5992 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5993
5994 /* For X710 */
5995 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5996 /* For XL710 */
5997 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5998 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5999
6000 static void
6001 i40e_configure_registers(struct i40e_hw *hw)
6002 {
6003         static struct {
6004                 uint32_t addr;
6005                 uint64_t val;
6006         } reg_table[] = {
6007                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
6008                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
6009                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
6010         };
6011         uint64_t reg;
6012         uint32_t i;
6013         int ret;
6014
6015         for (i = 0; i < RTE_DIM(reg_table); i++) {
6016                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
6017                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
6018                                 reg_table[i].val =
6019                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
6020                         else /* For X710 */
6021                                 reg_table[i].val =
6022                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
6023                 }
6024
6025                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
6026                                                         &reg, NULL);
6027                 if (ret < 0) {
6028                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
6029                                                         reg_table[i].addr);
6030                         break;
6031                 }
6032                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
6033                                                 reg_table[i].addr, reg);
6034                 if (reg == reg_table[i].val)
6035                         continue;
6036
6037                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
6038                                                 reg_table[i].val, NULL);
6039                 if (ret < 0) {
6040                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
6041                                 "address of 0x%"PRIx32, reg_table[i].val,
6042                                                         reg_table[i].addr);
6043                         break;
6044                 }
6045                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6046                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6047         }
6048 }
6049
6050 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
6051 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
6052 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
6053 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6054 static int
6055 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6056 {
6057         uint32_t reg;
6058         int ret;
6059
6060         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6061                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6062                 return -EINVAL;
6063         }
6064
6065         /* Configure for double VLAN RX stripping */
6066         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6067         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6068                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6069                 ret = i40e_aq_debug_write_register(hw,
6070                                                    I40E_VSI_TSR(vsi->vsi_id),
6071                                                    reg, NULL);
6072                 if (ret < 0) {
6073                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6074                                     vsi->vsi_id);
6075                         return I40E_ERR_CONFIG;
6076                 }
6077         }
6078
6079         /* Configure for double VLAN TX insertion */
6080         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6081         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6082                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6083                 ret = i40e_aq_debug_write_register(hw,
6084                                                    I40E_VSI_L2TAGSTXVALID(
6085                                                    vsi->vsi_id), reg, NULL);
6086                 if (ret < 0) {
6087                         PMD_DRV_LOG(ERR, "Failed to update "
6088                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6089                         return I40E_ERR_CONFIG;
6090                 }
6091         }
6092
6093         return 0;
6094 }
6095
6096 /**
6097  * i40e_aq_add_mirror_rule
6098  * @hw: pointer to the hardware structure
6099  * @seid: VEB seid to add mirror rule to
6100  * @dst_id: destination vsi seid
6101  * @entries: Buffer which contains the entities to be mirrored
6102  * @count: number of entities contained in the buffer
6103  * @rule_id:the rule_id of the rule to be added
6104  *
6105  * Add a mirror rule for a given veb.
6106  *
6107  **/
6108 static enum i40e_status_code
6109 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6110                         uint16_t seid, uint16_t dst_id,
6111                         uint16_t rule_type, uint16_t *entries,
6112                         uint16_t count, uint16_t *rule_id)
6113 {
6114         struct i40e_aq_desc desc;
6115         struct i40e_aqc_add_delete_mirror_rule cmd;
6116         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6117                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6118                 &desc.params.raw;
6119         uint16_t buff_len;
6120         enum i40e_status_code status;
6121
6122         i40e_fill_default_direct_cmd_desc(&desc,
6123                                           i40e_aqc_opc_add_mirror_rule);
6124         memset(&cmd, 0, sizeof(cmd));
6125
6126         buff_len = sizeof(uint16_t) * count;
6127         desc.datalen = rte_cpu_to_le_16(buff_len);
6128         if (buff_len > 0)
6129                 desc.flags |= rte_cpu_to_le_16(
6130                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6131         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6132                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6133         cmd.num_entries = rte_cpu_to_le_16(count);
6134         cmd.seid = rte_cpu_to_le_16(seid);
6135         cmd.destination = rte_cpu_to_le_16(dst_id);
6136
6137         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6138         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6139         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6140                          "rule_id = %u"
6141                          " mirror_rules_used = %u, mirror_rules_free = %u,",
6142                          hw->aq.asq_last_status, resp->rule_id,
6143                          resp->mirror_rules_used, resp->mirror_rules_free);
6144         *rule_id = rte_le_to_cpu_16(resp->rule_id);
6145
6146         return status;
6147 }
6148
6149 /**
6150  * i40e_aq_del_mirror_rule
6151  * @hw: pointer to the hardware structure
6152  * @seid: VEB seid to add mirror rule to
6153  * @entries: Buffer which contains the entities to be mirrored
6154  * @count: number of entities contained in the buffer
6155  * @rule_id:the rule_id of the rule to be delete
6156  *
6157  * Delete a mirror rule for a given veb.
6158  *
6159  **/
6160 static enum i40e_status_code
6161 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6162                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6163                 uint16_t count, uint16_t rule_id)
6164 {
6165         struct i40e_aq_desc desc;
6166         struct i40e_aqc_add_delete_mirror_rule cmd;
6167         uint16_t buff_len = 0;
6168         enum i40e_status_code status;
6169         void *buff = NULL;
6170
6171         i40e_fill_default_direct_cmd_desc(&desc,
6172                                           i40e_aqc_opc_delete_mirror_rule);
6173         memset(&cmd, 0, sizeof(cmd));
6174         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6175                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6176                                                           I40E_AQ_FLAG_RD));
6177                 cmd.num_entries = count;
6178                 buff_len = sizeof(uint16_t) * count;
6179                 desc.datalen = rte_cpu_to_le_16(buff_len);
6180                 buff = (void *)entries;
6181         } else
6182                 /* rule id is filled in destination field for deleting mirror rule */
6183                 cmd.destination = rte_cpu_to_le_16(rule_id);
6184
6185         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6186                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6187         cmd.seid = rte_cpu_to_le_16(seid);
6188
6189         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6190         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6191
6192         return status;
6193 }
6194
6195 /**
6196  * i40e_mirror_rule_set
6197  * @dev: pointer to the hardware structure
6198  * @mirror_conf: mirror rule info
6199  * @sw_id: mirror rule's sw_id
6200  * @on: enable/disable
6201  *
6202  * set a mirror rule.
6203  *
6204  **/
6205 static int
6206 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6207                         struct rte_eth_mirror_conf *mirror_conf,
6208                         uint8_t sw_id, uint8_t on)
6209 {
6210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6212         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6213         struct i40e_mirror_rule *parent = NULL;
6214         uint16_t seid, dst_seid, rule_id;
6215         uint16_t i, j = 0;
6216         int ret;
6217
6218         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6219
6220         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6221                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6222                         " without veb or vfs.");
6223                 return -ENOSYS;
6224         }
6225         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6226                 PMD_DRV_LOG(ERR, "mirror table is full.");
6227                 return -ENOSPC;
6228         }
6229         if (mirror_conf->dst_pool > pf->vf_num) {
6230                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6231                                  mirror_conf->dst_pool);
6232                 return -EINVAL;
6233         }
6234
6235         seid = pf->main_vsi->veb->seid;
6236
6237         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6238                 if (sw_id <= it->index) {
6239                         mirr_rule = it;
6240                         break;
6241                 }
6242                 parent = it;
6243         }
6244         if (mirr_rule && sw_id == mirr_rule->index) {
6245                 if (on) {
6246                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6247                         return -EEXIST;
6248                 } else {
6249                         ret = i40e_aq_del_mirror_rule(hw, seid,
6250                                         mirr_rule->rule_type,
6251                                         mirr_rule->entries,
6252                                         mirr_rule->num_entries, mirr_rule->id);
6253                         if (ret < 0) {
6254                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6255                                                    " ret = %d, aq_err = %d.",
6256                                                    ret, hw->aq.asq_last_status);
6257                                 return -ENOSYS;
6258                         }
6259                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6260                         rte_free(mirr_rule);
6261                         pf->nb_mirror_rule--;
6262                         return 0;
6263                 }
6264         } else if (!on) {
6265                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6266                 return -ENOENT;
6267         }
6268
6269         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6270                                 sizeof(struct i40e_mirror_rule) , 0);
6271         if (!mirr_rule) {
6272                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6273                 return I40E_ERR_NO_MEMORY;
6274         }
6275         switch (mirror_conf->rule_type) {
6276         case ETH_MIRROR_VLAN:
6277                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6278                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6279                                 mirr_rule->entries[j] =
6280                                         mirror_conf->vlan.vlan_id[i];
6281                                 j++;
6282                         }
6283                 }
6284                 if (j == 0) {
6285                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6286                         rte_free(mirr_rule);
6287                         return -EINVAL;
6288                 }
6289                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6290                 break;
6291         case ETH_MIRROR_VIRTUAL_POOL_UP:
6292         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6293                 /* check if the specified pool bit is out of range */
6294                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6295                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6296                         rte_free(mirr_rule);
6297                         return -EINVAL;
6298                 }
6299                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6300                         if (mirror_conf->pool_mask & (1ULL << i)) {
6301                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6302                                 j++;
6303                         }
6304                 }
6305                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6306                         /* add pf vsi to entries */
6307                         mirr_rule->entries[j] = pf->main_vsi_seid;
6308                         j++;
6309                 }
6310                 if (j == 0) {
6311                         PMD_DRV_LOG(ERR, "pool is not specified.");
6312                         rte_free(mirr_rule);
6313                         return -EINVAL;
6314                 }
6315                 /* egress and ingress in aq commands means from switch but not port */
6316                 mirr_rule->rule_type =
6317                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6318                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6319                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6320                 break;
6321         case ETH_MIRROR_UPLINK_PORT:
6322                 /* egress and ingress in aq commands means from switch but not port*/
6323                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6324                 break;
6325         case ETH_MIRROR_DOWNLINK_PORT:
6326                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6327                 break;
6328         default:
6329                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6330                         mirror_conf->rule_type);
6331                 rte_free(mirr_rule);
6332                 return -EINVAL;
6333         }
6334
6335         /* If the dst_pool is equal to vf_num, consider it as PF */
6336         if (mirror_conf->dst_pool == pf->vf_num)
6337                 dst_seid = pf->main_vsi_seid;
6338         else
6339                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6340
6341         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6342                                       mirr_rule->rule_type, mirr_rule->entries,
6343                                       j, &rule_id);
6344         if (ret < 0) {
6345                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6346                                    " ret = %d, aq_err = %d.",
6347                                    ret, hw->aq.asq_last_status);
6348                 rte_free(mirr_rule);
6349                 return -ENOSYS;
6350         }
6351
6352         mirr_rule->index = sw_id;
6353         mirr_rule->num_entries = j;
6354         mirr_rule->id = rule_id;
6355         mirr_rule->dst_vsi_seid = dst_seid;
6356
6357         if (parent)
6358                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6359         else
6360                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6361
6362         pf->nb_mirror_rule++;
6363         return 0;
6364 }
6365
6366 /**
6367  * i40e_mirror_rule_reset
6368  * @dev: pointer to the device
6369  * @sw_id: mirror rule's sw_id
6370  *
6371  * reset a mirror rule.
6372  *
6373  **/
6374 static int
6375 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6376 {
6377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6379         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6380         uint16_t seid;
6381         int ret;
6382
6383         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6384
6385         seid = pf->main_vsi->veb->seid;
6386
6387         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6388                 if (sw_id == it->index) {
6389                         mirr_rule = it;
6390                         break;
6391                 }
6392         }
6393         if (mirr_rule) {
6394                 ret = i40e_aq_del_mirror_rule(hw, seid,
6395                                 mirr_rule->rule_type,
6396                                 mirr_rule->entries,
6397                                 mirr_rule->num_entries, mirr_rule->id);
6398                 if (ret < 0) {
6399                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6400                                            " status = %d, aq_err = %d.",
6401                                            ret, hw->aq.asq_last_status);
6402                         return -ENOSYS;
6403                 }
6404                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6405                 rte_free(mirr_rule);
6406                 pf->nb_mirror_rule--;
6407         } else {
6408                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6409                 return -ENOENT;
6410         }
6411         return 0;
6412 }
6413
6414 static int
6415 i40e_timesync_enable(struct rte_eth_dev *dev)
6416 {
6417         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6418         struct rte_eth_link *link = &dev->data->dev_link;
6419         uint32_t tsync_ctl_l;
6420         uint32_t tsync_ctl_h;
6421         uint32_t tsync_inc_l;
6422         uint32_t tsync_inc_h;
6423
6424         switch (link->link_speed) {
6425         case ETH_LINK_SPEED_40G:
6426                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6427                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6428                 break;
6429         case ETH_LINK_SPEED_10G:
6430                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6431                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6432                 break;
6433         case ETH_LINK_SPEED_1000:
6434                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6435                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6436                 break;
6437         default:
6438                 tsync_inc_l = 0x0;
6439                 tsync_inc_h = 0x0;
6440         }
6441
6442         /* Clear timesync registers. */
6443         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6444         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6445         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6446         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6447         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6448         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6449         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6450
6451         /* Set the timesync increment value. */
6452         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6453         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6454
6455         /* Enable timestamping of PTP packets. */
6456         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6457         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6458
6459         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6460         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6461         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6462
6463         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6464         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6465
6466         return 0;
6467 }
6468
6469 static int
6470 i40e_timesync_disable(struct rte_eth_dev *dev)
6471 {
6472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6473         uint32_t tsync_ctl_l;
6474         uint32_t tsync_ctl_h;
6475
6476         /* Disable timestamping of transmitted PTP packets. */
6477         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6478         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6479
6480         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6481         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6482
6483         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6484         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6485
6486         /* Set the timesync increment value. */
6487         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6488         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6489
6490         return 0;
6491 }
6492
6493 static int
6494 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6495                                 struct timespec *timestamp, uint32_t flags)
6496 {
6497         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6498         uint32_t sync_status;
6499         uint32_t rx_stmpl;
6500         uint32_t rx_stmph;
6501         uint32_t index = flags & 0x03;
6502
6503         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6504         if ((sync_status & (1 << index)) == 0)
6505                 return -EINVAL;
6506
6507         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6508         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6509
6510         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6511         timestamp->tv_nsec = 0;
6512
6513         return  0;
6514 }
6515
6516 static int
6517 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6518                                 struct timespec *timestamp)
6519 {
6520         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6521         uint32_t sync_status;
6522         uint32_t tx_stmpl;
6523         uint32_t tx_stmph;
6524
6525         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6526         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6527                 return -EINVAL;
6528
6529         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6530         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6531
6532         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6533         timestamp->tv_nsec = 0;
6534
6535         return  0;
6536 }
6537
6538 /*
6539  * i40e_parse_dcb_configure - parse dcb configure from user
6540  * @dev: the device being configured
6541  * @dcb_cfg: pointer of the result of parse
6542  * @*tc_map: bit map of enabled traffic classes
6543  *
6544  * Returns 0 on success, negative value on failure
6545  */
6546 static int
6547 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
6548                          struct i40e_dcbx_config *dcb_cfg,
6549                          uint8_t *tc_map)
6550 {
6551         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
6552         uint8_t i, tc_bw, bw_lf;
6553
6554         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
6555
6556         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6557         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
6558                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
6559                 return -EINVAL;
6560         }
6561
6562         /* assume each tc has the same bw */
6563         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
6564         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6565                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
6566         /* to ensure the sum of tcbw is equal to 100 */
6567         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
6568         for (i = 0; i < bw_lf; i++)
6569                 dcb_cfg->etscfg.tcbwtable[i]++;
6570
6571         /* assume each tc has the same Transmission Selection Algorithm */
6572         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6573                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
6574
6575         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
6576                 dcb_cfg->etscfg.prioritytable[i] =
6577                                 dcb_rx_conf->dcb_tc[i];
6578
6579         /* FW needs one App to configure HW */
6580         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
6581         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
6582         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
6583         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
6584
6585         if (dcb_rx_conf->nb_tcs == 0)
6586                 *tc_map = 1; /* tc0 only */
6587         else
6588                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
6589
6590         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
6591                 dcb_cfg->pfc.willing = 0;
6592                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
6593                 dcb_cfg->pfc.pfcenable = *tc_map;
6594         }
6595         return 0;
6596 }
6597
6598 /*
6599  * i40e_vsi_get_bw_info - Query VSI BW Information
6600  * @vsi: the VSI being queried
6601  *
6602  * Returns 0 on success, negative value on failure
6603  */
6604 static int
6605 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
6606 {
6607         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
6608         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
6609         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6610         int i, ret;
6611         uint32_t tc_bw_max;
6612
6613         /* Get the VSI level BW configuration */
6614         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
6615         if (ret) {
6616                 PMD_INIT_LOG(ERR,
6617                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
6618                          i40e_stat_str(hw, ret),
6619                          i40e_aq_str(hw, hw->aq.asq_last_status));
6620                 return -EINVAL;
6621         }
6622
6623         /* Get the VSI level BW configuration per TC */
6624         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6625                                                   NULL);
6626         if (ret) {
6627                 PMD_INIT_LOG(ERR,
6628                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
6629                          i40e_stat_str(hw, ret),
6630                          i40e_aq_str(hw, hw->aq.asq_last_status));
6631                 return -EINVAL;
6632         }
6633
6634         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
6635                 PMD_INIT_LOG(WARNING,
6636                          "Enabled TCs mismatch from querying VSI BW info"
6637                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
6638                          bw_ets_config.tc_valid_bits);
6639                 /* Still continuing */
6640         }
6641
6642         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
6643         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
6644         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
6645                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
6646         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6647                 vsi->bw_info.bw_ets_share_credits[i] =
6648                                 bw_ets_config.share_credits[i];
6649                 vsi->bw_info.bw_ets_limit_credits[i] =
6650                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
6651                 /* 3 bits out of 4 for each TC */
6652                 vsi->bw_info.bw_ets_max_quanta[i] =
6653                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
6654                 PMD_INIT_LOG(DEBUG,
6655                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
6656                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
6657         }
6658
6659         return 0;
6660 }
6661
6662 static int
6663 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
6664                               struct i40e_aqc_vsi_properties_data *info,
6665                               uint8_t enabled_tcmap)
6666 {
6667         int ret, i, total_tc = 0;
6668         uint16_t qpnum_per_tc, bsf, qp_idx;
6669         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
6670
6671         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
6672         if (ret != I40E_SUCCESS)
6673                 return ret;
6674
6675         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6676                 if (enabled_tcmap & (1 << i))
6677                         total_tc++;
6678         }
6679         if (total_tc == 0)
6680                 total_tc = 1;
6681         vsi->enabled_tc = enabled_tcmap;
6682
6683         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
6684         /* Number of queues per enabled TC */
6685         if (qpnum_per_tc == 0) {
6686                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
6687                 return I40E_ERR_INVALID_QP_ID;
6688         }
6689         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
6690                                 I40E_MAX_Q_PER_TC);
6691         bsf = rte_bsf32(qpnum_per_tc);
6692
6693         /**
6694          * Configure TC and queue mapping parameters, for enabled TC,
6695          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
6696          * default queue will serve it.
6697          */
6698         qp_idx = 0;
6699         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6700                 if (vsi->enabled_tc & (1 << i)) {
6701                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
6702                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
6703                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
6704                         qp_idx += qpnum_per_tc;
6705                 } else
6706                         info->tc_mapping[i] = 0;
6707         }
6708
6709         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
6710         if (vsi->type == I40E_VSI_SRIOV) {
6711                 info->mapping_flags |=
6712                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
6713                 for (i = 0; i < vsi->nb_qps; i++)
6714                         info->queue_mapping[i] =
6715                                 rte_cpu_to_le_16(vsi->base_queue + i);
6716         } else {
6717                 info->mapping_flags |=
6718                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
6719                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
6720         }
6721         info->valid_sections |=
6722                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
6723
6724         return I40E_SUCCESS;
6725 }
6726
6727 /*
6728  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
6729  * @vsi: VSI to be configured
6730  * @tc_map: enabled TC bitmap
6731  *
6732  * Returns 0 on success, negative value on failure
6733  */
6734 static int
6735 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
6736 {
6737         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
6738         struct i40e_vsi_context ctxt;
6739         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6740         int ret = 0;
6741         int i;
6742
6743         /* Check if enabled_tc is same as existing or new TCs */
6744         if (vsi->enabled_tc == tc_map)
6745                 return ret;
6746
6747         /* configure tc bandwidth */
6748         memset(&bw_data, 0, sizeof(bw_data));
6749         bw_data.tc_valid_bits = tc_map;
6750         /* Enable ETS TCs with equal BW Share for now across all VSIs */
6751         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6752                 if (tc_map & BIT_ULL(i))
6753                         bw_data.tc_bw_credits[i] = 1;
6754         }
6755         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
6756         if (ret) {
6757                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
6758                         " per TC failed = %d",
6759                         hw->aq.asq_last_status);
6760                 goto out;
6761         }
6762         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
6763                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
6764
6765         /* Update Queue Pairs Mapping for currently enabled UPs */
6766         ctxt.seid = vsi->seid;
6767         ctxt.pf_num = hw->pf_id;
6768         ctxt.vf_num = 0;
6769         ctxt.uplink_seid = vsi->uplink_seid;
6770         ctxt.info = vsi->info;
6771         i40e_get_cap(hw);
6772         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
6773         if (ret)
6774                 goto out;
6775
6776         /* Update the VSI after updating the VSI queue-mapping information */
6777         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6778         if (ret) {
6779                 PMD_INIT_LOG(ERR, "Failed to configure "
6780                             "TC queue mapping = %d",
6781                             hw->aq.asq_last_status);
6782                 goto out;
6783         }
6784         /* update the local VSI info with updated queue map */
6785         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
6786                                         sizeof(vsi->info.tc_mapping));
6787         (void)rte_memcpy(&vsi->info.queue_mapping,
6788                         &ctxt.info.queue_mapping,
6789                 sizeof(vsi->info.queue_mapping));
6790         vsi->info.mapping_flags = ctxt.info.mapping_flags;
6791         vsi->info.valid_sections = 0;
6792
6793         /* Update current VSI BW information */
6794         ret = i40e_vsi_get_bw_info(vsi);
6795         if (ret) {
6796                 PMD_INIT_LOG(ERR,
6797                          "Failed updating vsi bw info, err %s aq_err %s",
6798                          i40e_stat_str(hw, ret),
6799                          i40e_aq_str(hw, hw->aq.asq_last_status));
6800                 goto out;
6801         }
6802
6803         vsi->enabled_tc = tc_map;
6804
6805 out:
6806         return ret;
6807 }
6808
6809 /*
6810  * i40e_dcb_hw_configure - program the dcb setting to hw
6811  * @pf: pf the configuration is taken on
6812  * @new_cfg: new configuration
6813  * @tc_map: enabled TC bitmap
6814  *
6815  * Returns 0 on success, negative value on failure
6816  */
6817 static enum i40e_status_code
6818 i40e_dcb_hw_configure(struct i40e_pf *pf,
6819                       struct i40e_dcbx_config *new_cfg,
6820                       uint8_t tc_map)
6821 {
6822         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6823         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
6824         struct i40e_vsi *main_vsi = pf->main_vsi;
6825         struct i40e_vsi_list *vsi_list;
6826         int i, ret;
6827         uint32_t val;
6828
6829         /* Use the FW API if FW > v4.4*/
6830         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
6831                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
6832                                   " to configure DCB");
6833                 return I40E_ERR_FIRMWARE_API_VERSION;
6834         }
6835
6836         /* Check if need reconfiguration */
6837         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
6838                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
6839                 return I40E_SUCCESS;
6840         }
6841
6842         /* Copy the new config to the current config */
6843         *old_cfg = *new_cfg;
6844         old_cfg->etsrec = old_cfg->etscfg;
6845         ret = i40e_set_dcb_config(hw);
6846         if (ret) {
6847                 PMD_INIT_LOG(ERR,
6848                          "Set DCB Config failed, err %s aq_err %s\n",
6849                          i40e_stat_str(hw, ret),
6850                          i40e_aq_str(hw, hw->aq.asq_last_status));
6851                 return ret;
6852         }
6853         /* set receive Arbiter to RR mode and ETS scheme by default */
6854         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
6855                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
6856                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
6857                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
6858                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
6859                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
6860                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
6861                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
6862                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
6863                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
6864                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
6865                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
6866                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
6867         }
6868         /* get local mib to check whether it is configured correctly */
6869         /* IEEE mode */
6870         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
6871         /* Get Local DCB Config */
6872         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
6873                                      &hw->local_dcbx_config);
6874
6875         /* Update each VSI */
6876         i40e_vsi_config_tc(main_vsi, tc_map);
6877         if (main_vsi->veb) {
6878                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
6879                         /* Beside main VSI, only enable default
6880                          * TC for other VSIs
6881                          */
6882                         ret = i40e_vsi_config_tc(vsi_list->vsi,
6883                                                 I40E_DEFAULT_TCMAP);
6884                         if (ret)
6885                                 PMD_INIT_LOG(WARNING,
6886                                          "Failed configuring TC for VSI seid=%d\n",
6887                                          vsi_list->vsi->seid);
6888                         /* continue */
6889                 }
6890         }
6891         return I40E_SUCCESS;
6892 }
6893
6894 /*
6895  * i40e_dcb_init_configure - initial dcb config
6896  * @dev: device being configured
6897  * @sw_dcb: indicate whether dcb is sw configured or hw offload
6898  *
6899  * Returns 0 on success, negative value on failure
6900  */
6901 static int
6902 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
6903 {
6904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6906         int ret = 0;
6907
6908         if ((pf->flags & I40E_FLAG_DCB) == 0) {
6909                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
6910                 return -ENOTSUP;
6911         }
6912
6913         /* DCB initialization:
6914          * Update DCB configuration from the Firmware and configure
6915          * LLDP MIB change event.
6916          */
6917         if (sw_dcb == TRUE) {
6918                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
6919                 if (ret != I40E_SUCCESS)
6920                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
6921
6922                 ret = i40e_init_dcb(hw);
6923                 /* if sw_dcb, lldp agent is stopped, the return from
6924                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
6925                  * adminq status.
6926                  */
6927                 if (ret != I40E_SUCCESS &&
6928                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
6929                         memset(&hw->local_dcbx_config, 0,
6930                                 sizeof(struct i40e_dcbx_config));
6931                         /* set dcb default configuration */
6932                         hw->local_dcbx_config.etscfg.willing = 0;
6933                         hw->local_dcbx_config.etscfg.maxtcs = 0;
6934                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
6935                         hw->local_dcbx_config.etscfg.tsatable[0] =
6936                                                 I40E_IEEE_TSA_ETS;
6937                         hw->local_dcbx_config.etsrec =
6938                                 hw->local_dcbx_config.etscfg;
6939                         hw->local_dcbx_config.pfc.willing = 0;
6940                         hw->local_dcbx_config.pfc.pfccap =
6941                                                 I40E_MAX_TRAFFIC_CLASS;
6942                         /* FW needs one App to configure HW */
6943                         hw->local_dcbx_config.numapps = 1;
6944                         hw->local_dcbx_config.app[0].selector =
6945                                                 I40E_APP_SEL_ETHTYPE;
6946                         hw->local_dcbx_config.app[0].priority = 3;
6947                         hw->local_dcbx_config.app[0].protocolid =
6948                                                 I40E_APP_PROTOID_FCOE;
6949                         ret = i40e_set_dcb_config(hw);
6950                         if (ret) {
6951                                 PMD_INIT_LOG(ERR, "default dcb config fails."
6952                                         " err = %d, aq_err = %d.", ret,
6953                                           hw->aq.asq_last_status);
6954                                 return -ENOSYS;
6955                         }
6956                 } else {
6957                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
6958                                           " aq_err = %d.", ret,
6959                                           hw->aq.asq_last_status);
6960                         return -ENOTSUP;
6961                 }
6962         } else {
6963                 ret = i40e_aq_start_lldp(hw, NULL);
6964                 if (ret != I40E_SUCCESS)
6965                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
6966
6967                 ret = i40e_init_dcb(hw);
6968                 if (!ret) {
6969                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
6970                                 PMD_INIT_LOG(ERR, "HW doesn't support"
6971                                                   " DCBX offload.");
6972                                 return -ENOTSUP;
6973                         }
6974                 } else {
6975                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
6976                                           " aq_err = %d.", ret,
6977                                           hw->aq.asq_last_status);
6978                         return -ENOTSUP;
6979                 }
6980         }
6981         return 0;
6982 }
6983
6984 /*
6985  * i40e_dcb_setup - setup dcb related config
6986  * @dev: device being configured
6987  *
6988  * Returns 0 on success, negative value on failure
6989  */
6990 static int
6991 i40e_dcb_setup(struct rte_eth_dev *dev)
6992 {
6993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6994         struct i40e_dcbx_config dcb_cfg;
6995         uint8_t tc_map = 0;
6996         int ret = 0;
6997
6998         if ((pf->flags & I40E_FLAG_DCB) == 0) {
6999                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7000                 return -ENOTSUP;
7001         }
7002
7003         if (pf->vf_num != 0 ||
7004             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
7005                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
7006
7007         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
7008         if (ret) {
7009                 PMD_INIT_LOG(ERR, "invalid dcb config");
7010                 return -EINVAL;
7011         }
7012         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
7013         if (ret) {
7014                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
7015                 return -ENOSYS;
7016         }
7017         return 0;
7018 }