drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  79
  80 /* Flow control default timer */
  81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  82
  83 /* Flow control default high water */
  84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  85
  86 /* Flow control default low water */
  87 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Receive Average Packet Size in Byte*/
  99 #define I40E_PACKET_AVERAGE_SIZE 128
 100
 101 /* Mask of PF interrupt causes */
 102 #define I40E_PFINT_ICR0_ENA_MASK ( \
 103                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 104                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 105                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 106                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 107                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 109                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 113
 114 #define I40E_FLOW_TYPES ( \
 115         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 116         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 126
 127 /* Additional timesync values. */
 128 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA     0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 133 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 134
 135 #define I40E_MAX_PERCENT            100
 136 #define I40E_DEFAULT_DCB_APP_NUM    1
 137 #define I40E_DEFAULT_DCB_APP_PRIO   3
 138
 139 #define I40E_INSET_NONE            0x00000000000000000ULL
 140
 141 /* bit0 ~ bit 7 */
 142 #define I40E_INSET_DMAC            0x0000000000000001ULL
 143 #define I40E_INSET_SMAC            0x0000000000000002ULL
 144 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 145 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 146 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 147
 148 /* bit 8 ~ bit 15 */
 149 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 150 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 151 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 152 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 153 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 154 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 155 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 156
 157 /* bit 16 ~ bit 31 */
 158 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 159 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 160 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 161 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 162 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 163 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 164 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 165 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 166
 167 /* bit 32 ~ bit 47, tunnel fields */
 168 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 169 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 170 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 171 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 172 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 173 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 174
 175 /* bit 48 ~ bit 55 */
 176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 177
 178 /* bit 56 ~ bit 63, Flex Payload */
 179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD \
 188         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 189         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 190         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 191         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 192
 193 /**
 194  * Below are values for writing un-exposed registers suggested
 195  * by silicon experts
 196  */
 197 /* Destination MAC address */
 198 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 199 /* Source MAC address */
 200 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 202 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 205 /* Single VLAN tag in the inner L2 header */
 206 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 207 /* Source IPv4 address */
 208 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 209 /* Destination IPv4 address */
 210 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 211 /* IPv4 Type of Service (TOS) */
 212 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 213 /* IPv4 Protocol */
 214 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 215 /* IPv4 Time to Live */
 216 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 217 /* Source IPv6 address */
 218 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 219 /* Destination IPv6 address */
 220 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 221 /* IPv6 Traffic Class (TC) */
 222 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 223 /* IPv6 Next Header */
 224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 225 /* IPv6 Hop Limit */
 226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263 /* all 8 words flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 265 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 266
 267 #define I40E_TRANSLATE_INSET 0
 268 #define I40E_TRANSLATE_REG   1
 269
 270 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 271 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 272 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 275 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 276
 277 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 280         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 281
 282 /* PCI offset for querying capability */
 283 #define PCI_DEV_CAP_REG            0xA4
 284 /* PCI offset for enabling/disabling Extended Tag */
 285 #define PCI_DEV_CTRL_REG           0xA8
 286 /* Bit mask of Extended Tag capability */
 287 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 288 /* Bit shift of Extended Tag enable/disable */
 289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 290 /* Bit mask of Extended Tag enable/disable */
 291 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 292
 293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 295 static int i40e_dev_configure(struct rte_eth_dev *dev);
 296 static int i40e_dev_start(struct rte_eth_dev *dev);
 297 static void i40e_dev_stop(struct rte_eth_dev *dev);
 298 static void i40e_dev_close(struct rte_eth_dev *dev);
 299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 306                                struct rte_eth_stats *stats);
 307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 308                                struct rte_eth_xstat *xstats, unsigned n);
 309 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 310                                      struct rte_eth_xstat_name *xstats_names,
 311                                      unsigned limit);
 312 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 313 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 314                                             uint16_t queue_id,
 315                                             uint8_t stat_idx,
 316                                             uint8_t is_rx);
 317 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 318                               struct rte_eth_dev_info *dev_info);
 319 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 320                                 uint16_t vlan_id,
 321                                 int on);
 322 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 323                               enum rte_vlan_type vlan_type,
 324                               uint16_t tpid);
 325 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 326 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 327                                       uint16_t queue,
 328                                       int on);
 329 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 330 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 331 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 332 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 333                               struct rte_eth_fc_conf *fc_conf);
 334 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 335                               struct rte_eth_fc_conf *fc_conf);
 336 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 337                                        struct rte_eth_pfc_conf *pfc_conf);
 338 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 339                           struct ether_addr *mac_addr,
 340                           uint32_t index,
 341                           uint32_t pool);
 342 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 343 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 344                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 345                                     uint16_t reta_size);
 346 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 347                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                    uint16_t reta_size);
 349
 350 static int i40e_get_cap(struct i40e_hw *hw);
 351 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 352 static int i40e_pf_setup(struct i40e_pf *pf);
 353 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 354 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 355 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 356 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 357 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 358                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 359 static void i40e_stat_update_48(struct i40e_hw *hw,
 360                                uint32_t hireg,
 361                                uint32_t loreg,
 362                                bool offset_loaded,
 363                                uint64_t *offset,
 364                                uint64_t *stat);
 365 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 366 static void i40e_dev_interrupt_handler(
 367                 __rte_unused struct rte_intr_handle *handle, void *param);
 368 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 369                                 uint32_t base, uint32_t num);
 370 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 371 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 372                         uint32_t base);
 373 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 374                         uint16_t num);
 375 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 376 static int i40e_veb_release(struct i40e_veb *veb);
 377 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 378                                                 struct i40e_vsi *vsi);
 379 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 380 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 381 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 382                                              struct i40e_macvlan_filter *mv_f,
 383                                              int num,
 384                                              struct ether_addr *addr);
 385 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 386                                              struct i40e_macvlan_filter *mv_f,
 387                                              int num,
 388                                              uint16_t vlan);
 389 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 390 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 391                                     struct rte_eth_rss_conf *rss_conf);
 392 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 393                                       struct rte_eth_rss_conf *rss_conf);
 394 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 395                                         struct rte_eth_udp_tunnel *udp_tunnel);
 396 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 397                                         struct rte_eth_udp_tunnel *udp_tunnel);
 398 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 399 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 400                         struct rte_eth_ethertype_filter *filter,
 401                         bool add);
 402 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 403                                 enum rte_filter_op filter_op,
 404                                 void *arg);
 405 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 406                                 enum rte_filter_type filter_type,
 407                                 enum rte_filter_op filter_op,
 408                                 void *arg);
 409 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 410                                   struct rte_eth_dcb_info *dcb_info);
 411 static void i40e_configure_registers(struct i40e_hw *hw);
 412 static void i40e_hw_init(struct rte_eth_dev *dev);
 413 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 414 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 415                         struct rte_eth_mirror_conf *mirror_conf,
 416                         uint8_t sw_id, uint8_t on);
 417 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 418
 419 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 420 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 421 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 422                                            struct timespec *timestamp,
 423                                            uint32_t flags);
 424 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp);
 426 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 427
 428 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 429
 430 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 431                                    struct timespec *timestamp);
 432 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 433                                     const struct timespec *timestamp);
 434
 435 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 436                                          uint16_t queue_id);
 437 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 438                                           uint16_t queue_id);
 439
 440 static int i40e_get_reg_length(struct rte_eth_dev *dev);
 441
 442 static int i40e_get_regs(struct rte_eth_dev *dev,
 443                          struct rte_dev_reg_info *regs);
 444
 445 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 446
 447 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 448                            struct rte_dev_eeprom_info *eeprom);
 449
 450 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 451                                       struct ether_addr *mac_addr);
 452
 453 static const struct rte_pci_id pci_id_i40e_map[] = {
 454 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 455 #include "rte_pci_dev_ids.h"
 456 { .vendor_id = 0, /* sentinel */ },
 457 };
 458
 459 static const struct eth_dev_ops i40e_eth_dev_ops = {
 460         .dev_configure                = i40e_dev_configure,
 461         .dev_start                    = i40e_dev_start,
 462         .dev_stop                     = i40e_dev_stop,
 463         .dev_close                    = i40e_dev_close,
 464         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 465         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 466         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 467         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 468         .dev_set_link_up              = i40e_dev_set_link_up,
 469         .dev_set_link_down            = i40e_dev_set_link_down,
 470         .link_update                  = i40e_dev_link_update,
 471         .stats_get                    = i40e_dev_stats_get,
 472         .xstats_get                   = i40e_dev_xstats_get,
 473         .xstats_get_names             = i40e_dev_xstats_get_names,
 474         .stats_reset                  = i40e_dev_stats_reset,
 475         .xstats_reset                 = i40e_dev_stats_reset,
 476         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 477         .dev_infos_get                = i40e_dev_info_get,
 478         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 479         .vlan_filter_set              = i40e_vlan_filter_set,
 480         .vlan_tpid_set                = i40e_vlan_tpid_set,
 481         .vlan_offload_set             = i40e_vlan_offload_set,
 482         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 483         .vlan_pvid_set                = i40e_vlan_pvid_set,
 484         .rx_queue_start               = i40e_dev_rx_queue_start,
 485         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 486         .tx_queue_start               = i40e_dev_tx_queue_start,
 487         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 488         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 489         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 490         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 491         .rx_queue_release             = i40e_dev_rx_queue_release,
 492         .rx_queue_count               = i40e_dev_rx_queue_count,
 493         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 494         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 495         .tx_queue_release             = i40e_dev_tx_queue_release,
 496         .dev_led_on                   = i40e_dev_led_on,
 497         .dev_led_off                  = i40e_dev_led_off,
 498         .flow_ctrl_get                = i40e_flow_ctrl_get,
 499         .flow_ctrl_set                = i40e_flow_ctrl_set,
 500         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 501         .mac_addr_add                 = i40e_macaddr_add,
 502         .mac_addr_remove              = i40e_macaddr_remove,
 503         .reta_update                  = i40e_dev_rss_reta_update,
 504         .reta_query                   = i40e_dev_rss_reta_query,
 505         .rss_hash_update              = i40e_dev_rss_hash_update,
 506         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 507         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 508         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 509         .filter_ctrl                  = i40e_dev_filter_ctrl,
 510         .rxq_info_get                 = i40e_rxq_info_get,
 511         .txq_info_get                 = i40e_txq_info_get,
 512         .mirror_rule_set              = i40e_mirror_rule_set,
 513         .mirror_rule_reset            = i40e_mirror_rule_reset,
 514         .timesync_enable              = i40e_timesync_enable,
 515         .timesync_disable             = i40e_timesync_disable,
 516         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 517         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 518         .get_dcb_info                 = i40e_dev_get_dcb_info,
 519         .timesync_adjust_time         = i40e_timesync_adjust_time,
 520         .timesync_read_time           = i40e_timesync_read_time,
 521         .timesync_write_time          = i40e_timesync_write_time,
 522         .get_reg_length               = i40e_get_reg_length,
 523         .get_reg                      = i40e_get_regs,
 524         .get_eeprom_length            = i40e_get_eeprom_length,
 525         .get_eeprom                   = i40e_get_eeprom,
 526         .mac_addr_set                 = i40e_set_default_mac_addr,
 527 };
 528
 529 /* store statistics names and its offset in stats structure */
 530 struct rte_i40e_xstats_name_off {
 531         char name[RTE_ETH_XSTATS_NAME_SIZE];
 532         unsigned offset;
 533 };
 534
 535 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 536         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 537         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 538         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 539         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 540         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 541                 rx_unknown_protocol)},
 542         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 543         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 544         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 545         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 546 };
 547
 548 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 549                 sizeof(rte_i40e_stats_strings[0]))
 550
 551 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 552         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 553                 tx_dropped_link_down)},
 554         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 555         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 556                 illegal_bytes)},
 557         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 558         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 559                 mac_local_faults)},
 560         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 561                 mac_remote_faults)},
 562         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 563                 rx_length_errors)},
 564         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 565         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 566         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 567         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 568         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 569         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_127)},
 571         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_255)},
 573         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_511)},
 575         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_1023)},
 577         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_1522)},
 579         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 580                 rx_size_big)},
 581         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_undersize)},
 583         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_oversize)},
 585         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 586                 mac_short_packet_dropped)},
 587         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 588                 rx_fragments)},
 589         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 590         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 591         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_127)},
 593         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_255)},
 595         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_511)},
 597         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_1023)},
 599         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_1522)},
 601         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 602                 tx_size_big)},
 603         {"rx_flow_director_atr_match_packets",
 604                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 605         {"rx_flow_director_sb_match_packets",
 606                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 607         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 608                 tx_lpi_status)},
 609         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 610                 rx_lpi_status)},
 611         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 612                 tx_lpi_count)},
 613         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 614                 rx_lpi_count)},
 615 };
 616
 617 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 618                 sizeof(rte_i40e_hw_port_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_rx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_rx)},
 625 };
 626
 627 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 628                 sizeof(rte_i40e_rxq_prio_strings[0]))
 629
 630 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 631         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xon_tx)},
 633         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 634                 priority_xoff_tx)},
 635         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 636                 priority_xon_2_xoff)},
 637 };
 638
 639 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 640                 sizeof(rte_i40e_txq_prio_strings[0]))
 641
 642 static struct eth_driver rte_i40e_pmd = {
 643         .pci_drv = {
 644                 .name = "rte_i40e_pmd",
 645                 .id_table = pci_id_i40e_map,
 646                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 647                         RTE_PCI_DRV_DETACHABLE,
 648         },
 649         .eth_dev_init = eth_i40e_dev_init,
 650         .eth_dev_uninit = eth_i40e_dev_uninit,
 651         .dev_private_size = sizeof(struct i40e_adapter),
 652 };
 653
 654 static inline int
 655 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 656                                      struct rte_eth_link *link)
 657 {
 658         struct rte_eth_link *dst = link;
 659         struct rte_eth_link *src = &(dev->data->dev_link);
 660
 661         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 662                                         *(uint64_t *)src) == 0)
 663                 return -1;
 664
 665         return 0;
 666 }
 667
 668 static inline int
 669 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 670                                       struct rte_eth_link *link)
 671 {
 672         struct rte_eth_link *dst = &(dev->data->dev_link);
 673         struct rte_eth_link *src = link;
 674
 675         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 676                                         *(uint64_t *)src) == 0)
 677                 return -1;
 678
 679         return 0;
 680 }
 681
 682 /*
 683  * Driver initialization routine.
 684  * Invoked once at EAL init time.
 685  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 686  */
 687 static int
 688 rte_i40e_pmd_init(const char *name __rte_unused,
 689                   const char *params __rte_unused)
 690 {
 691         PMD_INIT_FUNC_TRACE();
 692         rte_eth_driver_register(&rte_i40e_pmd);
 693
 694         return 0;
 695 }
 696
 697 static struct rte_driver rte_i40e_driver = {
 698         .type = PMD_PDEV,
 699         .init = rte_i40e_pmd_init,
 700 };
 701
 702 PMD_REGISTER_DRIVER(rte_i40e_driver);
 703
 704 /*
 705  * Initialize registers for flexible payload, which should be set by NVM.
 706  * This should be removed from code once it is fixed in NVM.
 707  */
 708 #ifndef I40E_GLQF_ORT
 709 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 710 #endif
 711 #ifndef I40E_GLQF_PIT
 712 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 713 #endif
 714
 715 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 716 {
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 720         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 727
 728         /* GLQF_PIT Registers */
 729         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 730         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 731 }
 732
 733 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 734
 735 /*
 736  * Add a ethertype filter to drop all flow control frames transmitted
 737  * from VSIs.
 738 */
 739 static void
 740 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 741 {
 742         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 743         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 744                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 745                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 746         int ret;
 747
 748         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 749                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 750                                 pf->main_vsi_seid, 0,
 751                                 TRUE, NULL, NULL);
 752         if (ret)
 753                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 754                                   " frames from VSIs.");
 755 }
 756
 757 static int
 758 eth_i40e_dev_init(struct rte_eth_dev *dev)
 759 {
 760         struct rte_pci_device *pci_dev;
 761         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 763         struct i40e_vsi *vsi;
 764         int ret;
 765         uint32_t len;
 766         uint8_t aq_fail = 0;
 767
 768         PMD_INIT_FUNC_TRACE();
 769
 770         dev->dev_ops = &i40e_eth_dev_ops;
 771         dev->rx_pkt_burst = i40e_recv_pkts;
 772         dev->tx_pkt_burst = i40e_xmit_pkts;
 773
 774         /* for secondary processes, we don't initialise any further as primary
 775          * has already done this work. Only check we don't need a different
 776          * RX function */
 777         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 778                 i40e_set_rx_function(dev);
 779                 i40e_set_tx_function(dev);
 780                 return 0;
 781         }
 782         pci_dev = dev->pci_dev;
 783
 784         rte_eth_copy_pci_info(dev, pci_dev);
 785
 786         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 787         pf->adapter->eth_dev = dev;
 788         pf->dev_data = dev->data;
 789
 790         hw->back = I40E_PF_TO_ADAPTER(pf);
 791         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 792         if (!hw->hw_addr) {
 793                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 794                              "as address is NULL");
 795                 return -ENODEV;
 796         }
 797
 798         hw->vendor_id = pci_dev->id.vendor_id;
 799         hw->device_id = pci_dev->id.device_id;
 800         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 801         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 802         hw->bus.device = pci_dev->addr.devid;
 803         hw->bus.func = pci_dev->addr.function;
 804         hw->adapter_stopped = 0;
 805
 806         /* Make sure all is clean before doing PF reset */
 807         i40e_clear_hw(hw);
 808
 809         /* Initialize the hardware */
 810         i40e_hw_init(dev);
 811
 812         /* Reset here to make sure all is clean for each PF */
 813         ret = i40e_pf_reset(hw);
 814         if (ret) {
 815                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 816                 return ret;
 817         }
 818
 819         /* Initialize the shared code (base driver) */
 820         ret = i40e_init_shared_code(hw);
 821         if (ret) {
 822                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 823                 return ret;
 824         }
 825
 826         /*
 827          * To work around the NVM issue,initialize registers
 828          * for flexible payload by software.
 829          * It should be removed once issues are fixed in NVM.
 830          */
 831         i40e_flex_payload_reg_init(hw);
 832
 833         /* Initialize the input set for filters (hash and fd) to default value */
 834         i40e_filter_input_set_init(pf);
 835
 836         /* Initialize the parameters for adminq */
 837         i40e_init_adminq_parameter(hw);
 838         ret = i40e_init_adminq(hw);
 839         if (ret != I40E_SUCCESS) {
 840                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 841                 return -EIO;
 842         }
 843         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 844                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 845                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 846                      ((hw->nvm.version >> 12) & 0xf),
 847                      ((hw->nvm.version >> 4) & 0xff),
 848                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 849
 850         /* Clear PXE mode */
 851         i40e_clear_pxe_mode(hw);
 852
 853         /*
 854          * On X710, performance number is far from the expectation on recent
 855          * firmware versions. The fix for this issue may not be integrated in
 856          * the following firmware version. So the workaround in software driver
 857          * is needed. It needs to modify the initial values of 3 internal only
 858          * registers. Note that the workaround can be removed when it is fixed
 859          * in firmware in the future.
 860          */
 861         i40e_configure_registers(hw);
 862
 863         /* Get hw capabilities */
 864         ret = i40e_get_cap(hw);
 865         if (ret != I40E_SUCCESS) {
 866                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 867                 goto err_get_capabilities;
 868         }
 869
 870         /* Initialize parameters for PF */
 871         ret = i40e_pf_parameter_init(dev);
 872         if (ret != 0) {
 873                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 874                 goto err_parameter_init;
 875         }
 876
 877         /* Initialize the queue management */
 878         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 879         if (ret < 0) {
 880                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 881                 goto err_qp_pool_init;
 882         }
 883         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 884                                 hw->func_caps.num_msix_vectors - 1);
 885         if (ret < 0) {
 886                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 887                 goto err_msix_pool_init;
 888         }
 889
 890         /* Initialize lan hmc */
 891         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 892                                 hw->func_caps.num_rx_qp, 0, 0);
 893         if (ret != I40E_SUCCESS) {
 894                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 895                 goto err_init_lan_hmc;
 896         }
 897
 898         /* Configure lan hmc */
 899         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 900         if (ret != I40E_SUCCESS) {
 901                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 902                 goto err_configure_lan_hmc;
 903         }
 904
 905         /* Get and check the mac address */
 906         i40e_get_mac_addr(hw, hw->mac.addr);
 907         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 908                 PMD_INIT_LOG(ERR, "mac address is not valid");
 909                 ret = -EIO;
 910                 goto err_get_mac_addr;
 911         }
 912         /* Copy the permanent MAC address */
 913         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 914                         (struct ether_addr *) hw->mac.perm_addr);
 915
 916         /* Disable flow control */
 917         hw->fc.requested_mode = I40E_FC_NONE;
 918         i40e_set_fc(hw, &aq_fail, TRUE);
 919
 920         /* Set the global registers with default ether type value */
 921         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 922         if (ret != I40E_SUCCESS) {
 923                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 924                              "VLAN ether type");
 925                 goto err_setup_pf_switch;
 926         }
 927         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 928         if (ret != I40E_SUCCESS) {
 929                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 930                              "VLAN ether type");
 931                 goto err_setup_pf_switch;
 932         }
 933
 934         /* PF setup, which includes VSI setup */
 935         ret = i40e_pf_setup(pf);
 936         if (ret) {
 937                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 938                 goto err_setup_pf_switch;
 939         }
 940
 941         /* reset all stats of the device, including pf and main vsi */
 942         i40e_dev_stats_reset(dev);
 943
 944         vsi = pf->main_vsi;
 945
 946         /* Disable double vlan by default */
 947         i40e_vsi_config_double_vlan(vsi, FALSE);
 948
 949         if (!vsi->max_macaddrs)
 950                 len = ETHER_ADDR_LEN;
 951         else
 952                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 953
 954         /* Should be after VSI initialized */
 955         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 956         if (!dev->data->mac_addrs) {
 957                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 958                                         "for storing mac address");
 959                 goto err_mac_alloc;
 960         }
 961         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 962                                         &dev->data->mac_addrs[0]);
 963
 964         /* initialize pf host driver to setup SRIOV resource if applicable */
 965         i40e_pf_host_init(dev);
 966
 967         /* register callback func to eal lib */
 968         rte_intr_callback_register(&(pci_dev->intr_handle),
 969                 i40e_dev_interrupt_handler, (void *)dev);
 970
 971         /* configure and enable device interrupt */
 972         i40e_pf_config_irq0(hw, TRUE);
 973         i40e_pf_enable_irq0(hw);
 974
 975         /* enable uio intr after callback register */
 976         rte_intr_enable(&(pci_dev->intr_handle));
 977         /*
 978          * Add an ethertype filter to drop all flow control frames transmitted
 979          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 980          * frames to wire.
 981          */
 982         i40e_add_tx_flow_control_drop_filter(pf);
 983
 984         /* Set the max frame size to 0x2600 by default,
 985          * in case other drivers changed the default value.
 986          */
 987         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 988
 989         /* initialize mirror rule list */
 990         TAILQ_INIT(&pf->mirror_list);
 991
 992         /* Init dcb to sw mode by default */
 993         ret = i40e_dcb_init_configure(dev, TRUE);
 994         if (ret != I40E_SUCCESS) {
 995                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 996                 pf->flags &= ~I40E_FLAG_DCB;
 997         }
 998
 999         return 0;
1000
1001 err_mac_alloc:
1002         i40e_vsi_release(pf->main_vsi);
1003 err_setup_pf_switch:
1004 err_get_mac_addr:
1005 err_configure_lan_hmc:
1006         (void)i40e_shutdown_lan_hmc(hw);
1007 err_init_lan_hmc:
1008         i40e_res_pool_destroy(&pf->msix_pool);
1009 err_msix_pool_init:
1010         i40e_res_pool_destroy(&pf->qp_pool);
1011 err_qp_pool_init:
1012 err_parameter_init:
1013 err_get_capabilities:
1014         (void)i40e_shutdown_adminq(hw);
1015
1016         return ret;
1017 }
1018
1019 static int
1020 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1021 {
1022         struct rte_pci_device *pci_dev;
1023         struct i40e_hw *hw;
1024         struct i40e_filter_control_settings settings;
1025         int ret;
1026         uint8_t aq_fail = 0;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1031                 return 0;
1032
1033         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1034         pci_dev = dev->pci_dev;
1035
1036         if (hw->adapter_stopped == 0)
1037                 i40e_dev_close(dev);
1038
1039         dev->dev_ops = NULL;
1040         dev->rx_pkt_burst = NULL;
1041         dev->tx_pkt_burst = NULL;
1042
1043         /* Disable LLDP */
1044         ret = i40e_aq_stop_lldp(hw, true, NULL);
1045         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1046                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1047
1048         /* Clear PXE mode */
1049         i40e_clear_pxe_mode(hw);
1050
1051         /* Unconfigure filter control */
1052         memset(&settings, 0, sizeof(settings));
1053         ret = i40e_set_filter_control(hw, &settings);
1054         if (ret)
1055                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1056                                         ret);
1057
1058         /* Disable flow control */
1059         hw->fc.requested_mode = I40E_FC_NONE;
1060         i40e_set_fc(hw, &aq_fail, TRUE);
1061
1062         /* uninitialize pf host driver */
1063         i40e_pf_host_uninit(dev);
1064
1065         rte_free(dev->data->mac_addrs);
1066         dev->data->mac_addrs = NULL;
1067
1068         /* disable uio intr before callback unregister */
1069         rte_intr_disable(&(pci_dev->intr_handle));
1070
1071         /* register callback func to eal lib */
1072         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1073                 i40e_dev_interrupt_handler, (void *)dev);
1074
1075         return 0;
1076 }
1077
1078 static int
1079 i40e_dev_configure(struct rte_eth_dev *dev)
1080 {
1081         struct i40e_adapter *ad =
1082                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1083         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1084         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1085         int i, ret;
1086
1087         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1088          * bulk allocation or vector Rx preconditions we will reset it.
1089          */
1090         ad->rx_bulk_alloc_allowed = true;
1091         ad->rx_vec_allowed = true;
1092         ad->tx_simple_allowed = true;
1093         ad->tx_vec_allowed = true;
1094
1095         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1096                 ret = i40e_fdir_setup(pf);
1097                 if (ret != I40E_SUCCESS) {
1098                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1099                         return -ENOTSUP;
1100                 }
1101                 ret = i40e_fdir_configure(dev);
1102                 if (ret < 0) {
1103                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1104                         goto err;
1105                 }
1106         } else
1107                 i40e_fdir_teardown(pf);
1108
1109         ret = i40e_dev_init_vlan(dev);
1110         if (ret < 0)
1111                 goto err;
1112
1113         /* VMDQ setup.
1114          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1115          *  RSS setting have different requirements.
1116          *  General PMD driver call sequence are NIC init, configure,
1117          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1118          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1119          *  applicable. So, VMDQ setting has to be done before
1120          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1121          *  For RSS setting, it will try to calculate actual configured RX queue
1122          *  number, which will be available after rx_queue_setup(). dev_start()
1123          *  function is good to place RSS setup.
1124          */
1125         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1126                 ret = i40e_vmdq_setup(dev);
1127                 if (ret)
1128                         goto err;
1129         }
1130
1131         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1132                 ret = i40e_dcb_setup(dev);
1133                 if (ret) {
1134                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1135                         goto err_dcb;
1136                 }
1137         }
1138
1139         return 0;
1140
1141 err_dcb:
1142         /* need to release vmdq resource if exists */
1143         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1144                 i40e_vsi_release(pf->vmdq[i].vsi);
1145                 pf->vmdq[i].vsi = NULL;
1146         }
1147         rte_free(pf->vmdq);
1148         pf->vmdq = NULL;
1149 err:
1150         /* need to release fdir resource if exists */
1151         i40e_fdir_teardown(pf);
1152         return ret;
1153 }
1154
1155 void
1156 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1157 {
1158         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1159         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1160         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1161         uint16_t msix_vect = vsi->msix_intr;
1162         uint16_t i;
1163
1164         for (i = 0; i < vsi->nb_qps; i++) {
1165                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1166                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1167                 rte_wmb();
1168         }
1169
1170         if (vsi->type != I40E_VSI_SRIOV) {
1171                 if (!rte_intr_allow_others(intr_handle)) {
1172                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1173                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1174                         I40E_WRITE_REG(hw,
1175                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1176                                        0);
1177                 } else {
1178                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1179                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1180                         I40E_WRITE_REG(hw,
1181                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1182                                                        msix_vect - 1), 0);
1183                 }
1184         } else {
1185                 uint32_t reg;
1186                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1187                         vsi->user_param + (msix_vect - 1);
1188
1189                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1190                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1191         }
1192         I40E_WRITE_FLUSH(hw);
1193 }
1194
1195 static void
1196 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1197                        int base_queue, int nb_queue)
1198 {
1199         int i;
1200         uint32_t val;
1201         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1202
1203         /* Bind all RX queues to allocated MSIX interrupt */
1204         for (i = 0; i < nb_queue; i++) {
1205                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1206                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1207                         ((base_queue + i + 1) <<
1208                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1209                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1210                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1211
1212                 if (i == nb_queue - 1)
1213                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1214                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1215         }
1216
1217         /* Write first RX queue to Link list register as the head element */
1218         if (vsi->type != I40E_VSI_SRIOV) {
1219                 uint16_t interval =
1220                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1221
1222                 if (msix_vect == I40E_MISC_VEC_ID) {
1223                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1224                                        (base_queue <<
1225                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1226                                        (0x0 <<
1227                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1228                         I40E_WRITE_REG(hw,
1229                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1230                                        interval);
1231                 } else {
1232                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1233                                        (base_queue <<
1234                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1235                                        (0x0 <<
1236                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1237                         I40E_WRITE_REG(hw,
1238                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1239                                                        msix_vect - 1),
1240                                        interval);
1241                 }
1242         } else {
1243                 uint32_t reg;
1244
1245                 if (msix_vect == I40E_MISC_VEC_ID) {
1246                         I40E_WRITE_REG(hw,
1247                                        I40E_VPINT_LNKLST0(vsi->user_param),
1248                                        (base_queue <<
1249                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1250                                        (0x0 <<
1251                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1252                 } else {
1253                         /* num_msix_vectors_vf needs to minus irq0 */
1254                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1255                                 vsi->user_param + (msix_vect - 1);
1256
1257                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1258                                        (base_queue <<
1259                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1260                                        (0x0 <<
1261                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1262                 }
1263         }
1264
1265         I40E_WRITE_FLUSH(hw);
1266 }
1267
1268 void
1269 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1270 {
1271         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1272         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1273         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1274         uint16_t msix_vect = vsi->msix_intr;
1275         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1276         uint16_t queue_idx = 0;
1277         int record = 0;
1278         uint32_t val;
1279         int i;
1280
1281         for (i = 0; i < vsi->nb_qps; i++) {
1282                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1283                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1284         }
1285
1286         /* INTENA flag is not auto-cleared for interrupt */
1287         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1288         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1289                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1290                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1291         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1292
1293         /* VF bind interrupt */
1294         if (vsi->type == I40E_VSI_SRIOV) {
1295                 __vsi_queues_bind_intr(vsi, msix_vect,
1296                                        vsi->base_queue, vsi->nb_qps);
1297                 return;
1298         }
1299
1300         /* PF & VMDq bind interrupt */
1301         if (rte_intr_dp_is_en(intr_handle)) {
1302                 if (vsi->type == I40E_VSI_MAIN) {
1303                         queue_idx = 0;
1304                         record = 1;
1305                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1306                         struct i40e_vsi *main_vsi =
1307                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1308                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1309                         record = 1;
1310                 }
1311         }
1312
1313         for (i = 0; i < vsi->nb_used_qps; i++) {
1314                 if (nb_msix <= 1) {
1315                         if (!rte_intr_allow_others(intr_handle))
1316                                 /* allow to share MISC_VEC_ID */
1317                                 msix_vect = I40E_MISC_VEC_ID;
1318
1319                         /* no enough msix_vect, map all to one */
1320                         __vsi_queues_bind_intr(vsi, msix_vect,
1321                                                vsi->base_queue + i,
1322                                                vsi->nb_used_qps - i);
1323                         for (; !!record && i < vsi->nb_used_qps; i++)
1324                                 intr_handle->intr_vec[queue_idx + i] =
1325                                         msix_vect;
1326                         break;
1327                 }
1328                 /* 1:1 queue/msix_vect mapping */
1329                 __vsi_queues_bind_intr(vsi, msix_vect,
1330                                        vsi->base_queue + i, 1);
1331                 if (!!record)
1332                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1333
1334                 msix_vect++;
1335                 nb_msix--;
1336         }
1337 }
1338
1339 static void
1340 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1341 {
1342         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1343         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1344         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1345         uint16_t interval = i40e_calc_itr_interval(\
1346                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1347         uint16_t msix_intr, i;
1348
1349         if (rte_intr_allow_others(intr_handle))
1350                 for (i = 0; i < vsi->nb_msix; i++) {
1351                         msix_intr = vsi->msix_intr + i;
1352                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1353                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1354                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1355                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1356                                 (interval <<
1357                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1358                 }
1359         else
1360                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1361                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1362                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1363                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1364                                (interval <<
1365                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1366
1367         I40E_WRITE_FLUSH(hw);
1368 }
1369
1370 static void
1371 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1372 {
1373         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1374         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1375         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1376         uint16_t msix_intr, i;
1377
1378         if (rte_intr_allow_others(intr_handle))
1379                 for (i = 0; i < vsi->nb_msix; i++) {
1380                         msix_intr = vsi->msix_intr + i;
1381                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1382                                        0);
1383                 }
1384         else
1385                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1386
1387         I40E_WRITE_FLUSH(hw);
1388 }
1389
1390 static inline uint8_t
1391 i40e_parse_link_speeds(uint16_t link_speeds)
1392 {
1393         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1394
1395         if (link_speeds & ETH_LINK_SPEED_40G)
1396                 link_speed |= I40E_LINK_SPEED_40GB;
1397         if (link_speeds & ETH_LINK_SPEED_20G)
1398                 link_speed |= I40E_LINK_SPEED_20GB;
1399         if (link_speeds & ETH_LINK_SPEED_10G)
1400                 link_speed |= I40E_LINK_SPEED_10GB;
1401         if (link_speeds & ETH_LINK_SPEED_1G)
1402                 link_speed |= I40E_LINK_SPEED_1GB;
1403         if (link_speeds & ETH_LINK_SPEED_100M)
1404                 link_speed |= I40E_LINK_SPEED_100MB;
1405
1406         return link_speed;
1407 }
1408
1409 static int
1410 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1411                    __rte_unused uint8_t abilities,
1412                    __rte_unused uint8_t force_speed)
1413 {
1414         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1415          * for the link control limitation of that all link control should be
1416          * handled by firmware. It should follow up if link control will be
1417          * opened to software driver in future firmware versions.
1418          */
1419         return I40E_SUCCESS;
1420 }
1421
1422 static int
1423 i40e_apply_link_speed(struct rte_eth_dev *dev)
1424 {
1425         uint8_t speed;
1426         uint8_t abilities = 0;
1427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428         struct rte_eth_conf *conf = &dev->data->dev_conf;
1429
1430         speed = i40e_parse_link_speeds(conf->link_speeds);
1431         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1432         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1433                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1434         else
1435                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1436
1437         return i40e_phy_conf_link(hw, abilities, speed);
1438 }
1439
1440 static int
1441 i40e_dev_start(struct rte_eth_dev *dev)
1442 {
1443         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1444         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1445         struct i40e_vsi *main_vsi = pf->main_vsi;
1446         int ret, i;
1447         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1448         uint32_t intr_vector = 0;
1449
1450         hw->adapter_stopped = 0;
1451
1452         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1453                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1454                              dev->data->port_id);
1455                 return -EINVAL;
1456         }
1457
1458         rte_intr_disable(intr_handle);
1459
1460         if ((rte_intr_cap_multiple(intr_handle) ||
1461              !RTE_ETH_DEV_SRIOV(dev).active) &&
1462             dev->data->dev_conf.intr_conf.rxq != 0) {
1463                 intr_vector = dev->data->nb_rx_queues;
1464                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1465                         return -1;
1466         }
1467
1468         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1469                 intr_handle->intr_vec =
1470                         rte_zmalloc("intr_vec",
1471                                     dev->data->nb_rx_queues * sizeof(int),
1472                                     0);
1473                 if (!intr_handle->intr_vec) {
1474                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1475                                      " intr_vec\n", dev->data->nb_rx_queues);
1476                         return -ENOMEM;
1477                 }
1478         }
1479
1480         /* Initialize VSI */
1481         ret = i40e_dev_rxtx_init(pf);
1482         if (ret != I40E_SUCCESS) {
1483                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1484                 goto err_up;
1485         }
1486
1487         /* Map queues with MSIX interrupt */
1488         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1489                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1490         i40e_vsi_queues_bind_intr(main_vsi);
1491         i40e_vsi_enable_queues_intr(main_vsi);
1492
1493         /* Map VMDQ VSI queues with MSIX interrupt */
1494         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1495                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1496                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1497                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1498         }
1499
1500         /* enable FDIR MSIX interrupt */
1501         if (pf->fdir.fdir_vsi) {
1502                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1503                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1504         }
1505
1506         /* Enable all queues which have been configured */
1507         ret = i40e_dev_switch_queues(pf, TRUE);
1508         if (ret != I40E_SUCCESS) {
1509                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1510                 goto err_up;
1511         }
1512
1513         /* Enable receiving broadcast packets */
1514         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1515         if (ret != I40E_SUCCESS)
1516                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1517
1518         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1519                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1520                                                 true, NULL);
1521                 if (ret != I40E_SUCCESS)
1522                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1523         }
1524
1525         /* Apply link configure */
1526         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1527                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1528                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1529                 PMD_DRV_LOG(ERR, "Invalid link setting");
1530                 goto err_up;
1531         }
1532         ret = i40e_apply_link_speed(dev);
1533         if (I40E_SUCCESS != ret) {
1534                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1535                 goto err_up;
1536         }
1537
1538         if (!rte_intr_allow_others(intr_handle)) {
1539                 rte_intr_callback_unregister(intr_handle,
1540                                              i40e_dev_interrupt_handler,
1541                                              (void *)dev);
1542                 /* configure and enable device interrupt */
1543                 i40e_pf_config_irq0(hw, FALSE);
1544                 i40e_pf_enable_irq0(hw);
1545
1546                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1547                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1548                                      " no intr multiplex\n");
1549         }
1550
1551         /* enable uio intr after callback register */
1552         rte_intr_enable(intr_handle);
1553
1554         return I40E_SUCCESS;
1555
1556 err_up:
1557         i40e_dev_switch_queues(pf, FALSE);
1558         i40e_dev_clear_queues(dev);
1559
1560         return ret;
1561 }
1562
1563 static void
1564 i40e_dev_stop(struct rte_eth_dev *dev)
1565 {
1566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1567         struct i40e_vsi *main_vsi = pf->main_vsi;
1568         struct i40e_mirror_rule *p_mirror;
1569         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1570         int i;
1571
1572         /* Disable all queues */
1573         i40e_dev_switch_queues(pf, FALSE);
1574
1575         /* un-map queues with interrupt registers */
1576         i40e_vsi_disable_queues_intr(main_vsi);
1577         i40e_vsi_queues_unbind_intr(main_vsi);
1578
1579         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1580                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1581                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1582         }
1583
1584         if (pf->fdir.fdir_vsi) {
1585                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1586                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1587         }
1588         /* Clear all queues and release memory */
1589         i40e_dev_clear_queues(dev);
1590
1591         /* Set link down */
1592         i40e_dev_set_link_down(dev);
1593
1594         /* Remove all mirror rules */
1595         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1596                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1597                 rte_free(p_mirror);
1598         }
1599         pf->nb_mirror_rule = 0;
1600
1601         if (!rte_intr_allow_others(intr_handle))
1602                 /* resume to the default handler */
1603                 rte_intr_callback_register(intr_handle,
1604                                            i40e_dev_interrupt_handler,
1605                                            (void *)dev);
1606
1607         /* Clean datapath event and queue/vec mapping */
1608         rte_intr_efd_disable(intr_handle);
1609         if (intr_handle->intr_vec) {
1610                 rte_free(intr_handle->intr_vec);
1611                 intr_handle->intr_vec = NULL;
1612         }
1613 }
1614
1615 static void
1616 i40e_dev_close(struct rte_eth_dev *dev)
1617 {
1618         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1619         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1620         uint32_t reg;
1621         int i;
1622
1623         PMD_INIT_FUNC_TRACE();
1624
1625         i40e_dev_stop(dev);
1626         hw->adapter_stopped = 1;
1627         i40e_dev_free_queues(dev);
1628
1629         /* Disable interrupt */
1630         i40e_pf_disable_irq0(hw);
1631         rte_intr_disable(&(dev->pci_dev->intr_handle));
1632
1633         /* shutdown and destroy the HMC */
1634         i40e_shutdown_lan_hmc(hw);
1635
1636         /* release all the existing VSIs and VEBs */
1637         i40e_fdir_teardown(pf);
1638         i40e_vsi_release(pf->main_vsi);
1639
1640         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1641                 i40e_vsi_release(pf->vmdq[i].vsi);
1642                 pf->vmdq[i].vsi = NULL;
1643         }
1644
1645         rte_free(pf->vmdq);
1646         pf->vmdq = NULL;
1647
1648         /* shutdown the adminq */
1649         i40e_aq_queue_shutdown(hw, true);
1650         i40e_shutdown_adminq(hw);
1651
1652         i40e_res_pool_destroy(&pf->qp_pool);
1653         i40e_res_pool_destroy(&pf->msix_pool);
1654
1655         /* force a PF reset to clean anything leftover */
1656         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1657         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1658                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1659         I40E_WRITE_FLUSH(hw);
1660 }
1661
1662 static void
1663 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1664 {
1665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667         struct i40e_vsi *vsi = pf->main_vsi;
1668         int status;
1669
1670         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1671                                                         true, NULL);
1672         if (status != I40E_SUCCESS)
1673                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1674
1675         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1676                                                         TRUE, NULL);
1677         if (status != I40E_SUCCESS)
1678                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1679
1680 }
1681
1682 static void
1683 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1684 {
1685         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1686         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         struct i40e_vsi *vsi = pf->main_vsi;
1688         int status;
1689
1690         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1691                                                         false, NULL);
1692         if (status != I40E_SUCCESS)
1693                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1694
1695         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1696                                                         false, NULL);
1697         if (status != I40E_SUCCESS)
1698                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1699 }
1700
1701 static void
1702 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1703 {
1704         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1705         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706         struct i40e_vsi *vsi = pf->main_vsi;
1707         int ret;
1708
1709         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1710         if (ret != I40E_SUCCESS)
1711                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1712 }
1713
1714 static void
1715 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1716 {
1717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719         struct i40e_vsi *vsi = pf->main_vsi;
1720         int ret;
1721
1722         if (dev->data->promiscuous == 1)
1723                 return; /* must remain in all_multicast mode */
1724
1725         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1726                                 vsi->seid, FALSE, NULL);
1727         if (ret != I40E_SUCCESS)
1728                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1729 }
1730
1731 /*
1732  * Set device link up.
1733  */
1734 static int
1735 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1736 {
1737         /* re-apply link speed setting */
1738         return i40e_apply_link_speed(dev);
1739 }
1740
1741 /*
1742  * Set device link down.
1743  */
1744 static int
1745 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1746 {
1747         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1748         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750
1751         return i40e_phy_conf_link(hw, abilities, speed);
1752 }
1753
1754 int
1755 i40e_dev_link_update(struct rte_eth_dev *dev,
1756                      int wait_to_complete)
1757 {
1758 #define CHECK_INTERVAL 100  /* 100ms */
1759 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1760         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761         struct i40e_link_status link_status;
1762         struct rte_eth_link link, old;
1763         int status;
1764         unsigned rep_cnt = MAX_REPEAT_TIME;
1765
1766         memset(&link, 0, sizeof(link));
1767         memset(&old, 0, sizeof(old));
1768         memset(&link_status, 0, sizeof(link_status));
1769         rte_i40e_dev_atomic_read_link_status(dev, &old);
1770
1771         do {
1772                 /* Get link status information from hardware */
1773                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1774                 if (status != I40E_SUCCESS) {
1775                         link.link_speed = ETH_SPEED_NUM_100M;
1776                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1777                         PMD_DRV_LOG(ERR, "Failed to get link info");
1778                         goto out;
1779                 }
1780
1781                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1782                 if (!wait_to_complete)
1783                         break;
1784
1785                 rte_delay_ms(CHECK_INTERVAL);
1786         } while (!link.link_status && rep_cnt--);
1787
1788         if (!link.link_status)
1789                 goto out;
1790
1791         /* i40e uses full duplex only */
1792         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1793
1794         /* Parse the link status */
1795         switch (link_status.link_speed) {
1796         case I40E_LINK_SPEED_100MB:
1797                 link.link_speed = ETH_SPEED_NUM_100M;
1798                 break;
1799         case I40E_LINK_SPEED_1GB:
1800                 link.link_speed = ETH_SPEED_NUM_1G;
1801                 break;
1802         case I40E_LINK_SPEED_10GB:
1803                 link.link_speed = ETH_SPEED_NUM_10G;
1804                 break;
1805         case I40E_LINK_SPEED_20GB:
1806                 link.link_speed = ETH_SPEED_NUM_20G;
1807                 break;
1808         case I40E_LINK_SPEED_40GB:
1809                 link.link_speed = ETH_SPEED_NUM_40G;
1810                 break;
1811         default:
1812                 link.link_speed = ETH_SPEED_NUM_100M;
1813                 break;
1814         }
1815
1816         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1817                         ETH_LINK_SPEED_FIXED);
1818
1819 out:
1820         rte_i40e_dev_atomic_write_link_status(dev, &link);
1821         if (link.link_status == old.link_status)
1822                 return -1;
1823
1824         return 0;
1825 }
1826
1827 /* Get all the statistics of a VSI */
1828 void
1829 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1830 {
1831         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1832         struct i40e_eth_stats *nes = &vsi->eth_stats;
1833         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1834         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1835
1836         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1837                             vsi->offset_loaded, &oes->rx_bytes,
1838                             &nes->rx_bytes);
1839         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1840                             vsi->offset_loaded, &oes->rx_unicast,
1841                             &nes->rx_unicast);
1842         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1843                             vsi->offset_loaded, &oes->rx_multicast,
1844                             &nes->rx_multicast);
1845         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1846                             vsi->offset_loaded, &oes->rx_broadcast,
1847                             &nes->rx_broadcast);
1848         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1849                             &oes->rx_discards, &nes->rx_discards);
1850         /* GLV_REPC not supported */
1851         /* GLV_RMPC not supported */
1852         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1853                             &oes->rx_unknown_protocol,
1854                             &nes->rx_unknown_protocol);
1855         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1856                             vsi->offset_loaded, &oes->tx_bytes,
1857                             &nes->tx_bytes);
1858         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1859                             vsi->offset_loaded, &oes->tx_unicast,
1860                             &nes->tx_unicast);
1861         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1862                             vsi->offset_loaded, &oes->tx_multicast,
1863                             &nes->tx_multicast);
1864         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1865                             vsi->offset_loaded,  &oes->tx_broadcast,
1866                             &nes->tx_broadcast);
1867         /* GLV_TDPC not supported */
1868         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1869                             &oes->tx_errors, &nes->tx_errors);
1870         vsi->offset_loaded = true;
1871
1872         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1873                     vsi->vsi_id);
1874         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1875         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1876         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1877         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1878         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1879         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1880                     nes->rx_unknown_protocol);
1881         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1882         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1883         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1884         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1885         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1886         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1887         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1888                     vsi->vsi_id);
1889 }
1890
1891 static void
1892 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1893 {
1894         unsigned int i;
1895         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1896         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1897
1898         /* Get statistics of struct i40e_eth_stats */
1899         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1900                             I40E_GLPRT_GORCL(hw->port),
1901                             pf->offset_loaded, &os->eth.rx_bytes,
1902                             &ns->eth.rx_bytes);
1903         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1904                             I40E_GLPRT_UPRCL(hw->port),
1905                             pf->offset_loaded, &os->eth.rx_unicast,
1906                             &ns->eth.rx_unicast);
1907         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1908                             I40E_GLPRT_MPRCL(hw->port),
1909                             pf->offset_loaded, &os->eth.rx_multicast,
1910                             &ns->eth.rx_multicast);
1911         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1912                             I40E_GLPRT_BPRCL(hw->port),
1913                             pf->offset_loaded, &os->eth.rx_broadcast,
1914                             &ns->eth.rx_broadcast);
1915         /* Workaround: CRC size should not be included in byte statistics,
1916          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1917          */
1918         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1919                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1920
1921         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1922                             pf->offset_loaded, &os->eth.rx_discards,
1923                             &ns->eth.rx_discards);
1924         /* GLPRT_REPC not supported */
1925         /* GLPRT_RMPC not supported */
1926         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1927                             pf->offset_loaded,
1928                             &os->eth.rx_unknown_protocol,
1929                             &ns->eth.rx_unknown_protocol);
1930         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1931                             I40E_GLPRT_GOTCL(hw->port),
1932                             pf->offset_loaded, &os->eth.tx_bytes,
1933                             &ns->eth.tx_bytes);
1934         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1935                             I40E_GLPRT_UPTCL(hw->port),
1936                             pf->offset_loaded, &os->eth.tx_unicast,
1937                             &ns->eth.tx_unicast);
1938         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1939                             I40E_GLPRT_MPTCL(hw->port),
1940                             pf->offset_loaded, &os->eth.tx_multicast,
1941                             &ns->eth.tx_multicast);
1942         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1943                             I40E_GLPRT_BPTCL(hw->port),
1944                             pf->offset_loaded, &os->eth.tx_broadcast,
1945                             &ns->eth.tx_broadcast);
1946         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1947                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1948         /* GLPRT_TEPC not supported */
1949
1950         /* additional port specific stats */
1951         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1952                             pf->offset_loaded, &os->tx_dropped_link_down,
1953                             &ns->tx_dropped_link_down);
1954         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1955                             pf->offset_loaded, &os->crc_errors,
1956                             &ns->crc_errors);
1957         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1958                             pf->offset_loaded, &os->illegal_bytes,
1959                             &ns->illegal_bytes);
1960         /* GLPRT_ERRBC not supported */
1961         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1962                             pf->offset_loaded, &os->mac_local_faults,
1963                             &ns->mac_local_faults);
1964         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1965                             pf->offset_loaded, &os->mac_remote_faults,
1966                             &ns->mac_remote_faults);
1967         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1968                             pf->offset_loaded, &os->rx_length_errors,
1969                             &ns->rx_length_errors);
1970         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1971                             pf->offset_loaded, &os->link_xon_rx,
1972                             &ns->link_xon_rx);
1973         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1974                             pf->offset_loaded, &os->link_xoff_rx,
1975                             &ns->link_xoff_rx);
1976         for (i = 0; i < 8; i++) {
1977                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1978                                     pf->offset_loaded,
1979                                     &os->priority_xon_rx[i],
1980                                     &ns->priority_xon_rx[i]);
1981                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1982                                     pf->offset_loaded,
1983                                     &os->priority_xoff_rx[i],
1984                                     &ns->priority_xoff_rx[i]);
1985         }
1986         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1987                             pf->offset_loaded, &os->link_xon_tx,
1988                             &ns->link_xon_tx);
1989         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1990                             pf->offset_loaded, &os->link_xoff_tx,
1991                             &ns->link_xoff_tx);
1992         for (i = 0; i < 8; i++) {
1993                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1994                                     pf->offset_loaded,
1995                                     &os->priority_xon_tx[i],
1996                                     &ns->priority_xon_tx[i]);
1997                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1998                                     pf->offset_loaded,
1999                                     &os->priority_xoff_tx[i],
2000                                     &ns->priority_xoff_tx[i]);
2001                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2002                                     pf->offset_loaded,
2003                                     &os->priority_xon_2_xoff[i],
2004                                     &ns->priority_xon_2_xoff[i]);
2005         }
2006         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2007                             I40E_GLPRT_PRC64L(hw->port),
2008                             pf->offset_loaded, &os->rx_size_64,
2009                             &ns->rx_size_64);
2010         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2011                             I40E_GLPRT_PRC127L(hw->port),
2012                             pf->offset_loaded, &os->rx_size_127,
2013                             &ns->rx_size_127);
2014         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2015                             I40E_GLPRT_PRC255L(hw->port),
2016                             pf->offset_loaded, &os->rx_size_255,
2017                             &ns->rx_size_255);
2018         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2019                             I40E_GLPRT_PRC511L(hw->port),
2020                             pf->offset_loaded, &os->rx_size_511,
2021                             &ns->rx_size_511);
2022         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2023                             I40E_GLPRT_PRC1023L(hw->port),
2024                             pf->offset_loaded, &os->rx_size_1023,
2025                             &ns->rx_size_1023);
2026         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2027                             I40E_GLPRT_PRC1522L(hw->port),
2028                             pf->offset_loaded, &os->rx_size_1522,
2029                             &ns->rx_size_1522);
2030         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2031                             I40E_GLPRT_PRC9522L(hw->port),
2032                             pf->offset_loaded, &os->rx_size_big,
2033                             &ns->rx_size_big);
2034         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2035                             pf->offset_loaded, &os->rx_undersize,
2036                             &ns->rx_undersize);
2037         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2038                             pf->offset_loaded, &os->rx_fragments,
2039                             &ns->rx_fragments);
2040         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2041                             pf->offset_loaded, &os->rx_oversize,
2042                             &ns->rx_oversize);
2043         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2044                             pf->offset_loaded, &os->rx_jabber,
2045                             &ns->rx_jabber);
2046         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2047                             I40E_GLPRT_PTC64L(hw->port),
2048                             pf->offset_loaded, &os->tx_size_64,
2049                             &ns->tx_size_64);
2050         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2051                             I40E_GLPRT_PTC127L(hw->port),
2052                             pf->offset_loaded, &os->tx_size_127,
2053                             &ns->tx_size_127);
2054         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2055                             I40E_GLPRT_PTC255L(hw->port),
2056                             pf->offset_loaded, &os->tx_size_255,
2057                             &ns->tx_size_255);
2058         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2059                             I40E_GLPRT_PTC511L(hw->port),
2060                             pf->offset_loaded, &os->tx_size_511,
2061                             &ns->tx_size_511);
2062         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2063                             I40E_GLPRT_PTC1023L(hw->port),
2064                             pf->offset_loaded, &os->tx_size_1023,
2065                             &ns->tx_size_1023);
2066         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2067                             I40E_GLPRT_PTC1522L(hw->port),
2068                             pf->offset_loaded, &os->tx_size_1522,
2069                             &ns->tx_size_1522);
2070         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2071                             I40E_GLPRT_PTC9522L(hw->port),
2072                             pf->offset_loaded, &os->tx_size_big,
2073                             &ns->tx_size_big);
2074         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2075                            pf->offset_loaded,
2076                            &os->fd_sb_match, &ns->fd_sb_match);
2077         /* GLPRT_MSPDC not supported */
2078         /* GLPRT_XEC not supported */
2079
2080         pf->offset_loaded = true;
2081
2082         if (pf->main_vsi)
2083                 i40e_update_vsi_stats(pf->main_vsi);
2084 }
2085
2086 /* Get all statistics of a port */
2087 static void
2088 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2089 {
2090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2091         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2093         unsigned i;
2094
2095         /* call read registers - updates values, now write them to struct */
2096         i40e_read_stats_registers(pf, hw);
2097
2098         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2099                         pf->main_vsi->eth_stats.rx_multicast +
2100                         pf->main_vsi->eth_stats.rx_broadcast -
2101                         pf->main_vsi->eth_stats.rx_discards;
2102         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2103                         pf->main_vsi->eth_stats.tx_multicast +
2104                         pf->main_vsi->eth_stats.tx_broadcast;
2105         stats->ibytes   = ns->eth.rx_bytes;
2106         stats->obytes   = ns->eth.tx_bytes;
2107         stats->oerrors  = ns->eth.tx_errors +
2108                         pf->main_vsi->eth_stats.tx_errors;
2109
2110         /* Rx Errors */
2111         stats->imissed  = ns->eth.rx_discards +
2112                         pf->main_vsi->eth_stats.rx_discards;
2113         stats->ierrors  = ns->crc_errors +
2114                         ns->rx_length_errors + ns->rx_undersize +
2115                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2116
2117         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2118         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2119         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2120         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2121         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2122         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2123         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2124                     ns->eth.rx_unknown_protocol);
2125         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2126         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2127         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2128         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2129         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2130         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2131
2132         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2133                     ns->tx_dropped_link_down);
2134         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2135         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2136                     ns->illegal_bytes);
2137         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2138         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2139                     ns->mac_local_faults);
2140         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2141                     ns->mac_remote_faults);
2142         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2143                     ns->rx_length_errors);
2144         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2145         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2146         for (i = 0; i < 8; i++) {
2147                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2148                                 i, ns->priority_xon_rx[i]);
2149                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2150                                 i, ns->priority_xoff_rx[i]);
2151         }
2152         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2153         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2154         for (i = 0; i < 8; i++) {
2155                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2156                                 i, ns->priority_xon_tx[i]);
2157                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2158                                 i, ns->priority_xoff_tx[i]);
2159                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2160                                 i, ns->priority_xon_2_xoff[i]);
2161         }
2162         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2163         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2164         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2165         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2166         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2167         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2168         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2169         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2170         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2171         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2172         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2173         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2174         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2175         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2176         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2177         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2178         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2179         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2180         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2181                         ns->mac_short_packet_dropped);
2182         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2183                     ns->checksum_error);
2184         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2185         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2186 }
2187
2188 /* Reset the statistics */
2189 static void
2190 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2191 {
2192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194
2195         /* Mark PF and VSI stats to update the offset, aka "reset" */
2196         pf->offset_loaded = false;
2197         if (pf->main_vsi)
2198                 pf->main_vsi->offset_loaded = false;
2199
2200         /* read the stats, reading current register values into offset */
2201         i40e_read_stats_registers(pf, hw);
2202 }
2203
2204 static uint32_t
2205 i40e_xstats_calc_num(void)
2206 {
2207         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2208                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2209                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2210 }
2211
2212 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2213                                      struct rte_eth_xstat_name *xstats_names,
2214                                      __rte_unused unsigned limit)
2215 {
2216         unsigned count = 0;
2217         unsigned i, prio;
2218
2219         if (xstats_names == NULL)
2220                 return i40e_xstats_calc_num();
2221
2222         /* Note: limit checked in rte_eth_xstats_names() */
2223
2224         /* Get stats from i40e_eth_stats struct */
2225         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2226                 snprintf(xstats_names[count].name,
2227                          sizeof(xstats_names[count].name),
2228                          "%s", rte_i40e_stats_strings[i].name);
2229                 xstats_names[count].id = count;
2230                 count++;
2231         }
2232
2233         /* Get individiual stats from i40e_hw_port struct */
2234         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2235                 snprintf(xstats_names[count].name,
2236                         sizeof(xstats_names[count].name),
2237                          "%s", rte_i40e_hw_port_strings[i].name);
2238                 xstats_names[count].id = count;
2239                 count++;
2240         }
2241
2242         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2243                 for (prio = 0; prio < 8; prio++) {
2244                         snprintf(xstats_names[count].name,
2245                                  sizeof(xstats_names[count].name),
2246                                  "rx_priority%u_%s", prio,
2247                                  rte_i40e_rxq_prio_strings[i].name);
2248                         xstats_names[count].id = count;
2249                         count++;
2250                 }
2251         }
2252
2253         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2254                 for (prio = 0; prio < 8; prio++) {
2255                         snprintf(xstats_names[count].name,
2256                                  sizeof(xstats_names[count].name),
2257                                  "tx_priority%u_%s", prio,
2258                                  rte_i40e_txq_prio_strings[i].name);
2259                         xstats_names[count].id = count;
2260                         count++;
2261                 }
2262         }
2263         return count;
2264 }
2265
2266 static int
2267 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2268                     unsigned n)
2269 {
2270         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2271         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272         unsigned i, count, prio;
2273         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2274
2275         count = i40e_xstats_calc_num();
2276         if (n < count)
2277                 return count;
2278
2279         i40e_read_stats_registers(pf, hw);
2280
2281         if (xstats == NULL)
2282                 return 0;
2283
2284         count = 0;
2285
2286         /* Get stats from i40e_eth_stats struct */
2287         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2288                 xstats[count].id = count;
2289                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2290                         rte_i40e_stats_strings[i].offset);
2291                 count++;
2292         }
2293
2294         /* Get individiual stats from i40e_hw_port struct */
2295         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2296                 xstats[count].id = count;
2297                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2298                         rte_i40e_hw_port_strings[i].offset);
2299                 count++;
2300         }
2301
2302         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2303                 for (prio = 0; prio < 8; prio++) {
2304                         xstats[count].id = count;
2305                         xstats[count].value =
2306                                 *(uint64_t *)(((char *)hw_stats) +
2307                                 rte_i40e_rxq_prio_strings[i].offset +
2308                                 (sizeof(uint64_t) * prio));
2309                         count++;
2310                 }
2311         }
2312
2313         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2314                 for (prio = 0; prio < 8; prio++) {
2315                         xstats[count].id = count;
2316                         xstats[count].value =
2317                                 *(uint64_t *)(((char *)hw_stats) +
2318                                 rte_i40e_txq_prio_strings[i].offset +
2319                                 (sizeof(uint64_t) * prio));
2320                         count++;
2321                 }
2322         }
2323
2324         return count;
2325 }
2326
2327 static int
2328 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2329                                  __rte_unused uint16_t queue_id,
2330                                  __rte_unused uint8_t stat_idx,
2331                                  __rte_unused uint8_t is_rx)
2332 {
2333         PMD_INIT_FUNC_TRACE();
2334
2335         return -ENOSYS;
2336 }
2337
2338 static void
2339 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2340 {
2341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         struct i40e_vsi *vsi = pf->main_vsi;
2344
2345         dev_info->max_rx_queues = vsi->nb_qps;
2346         dev_info->max_tx_queues = vsi->nb_qps;
2347         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2348         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2349         dev_info->max_mac_addrs = vsi->max_macaddrs;
2350         dev_info->max_vfs = dev->pci_dev->max_vfs;
2351         dev_info->rx_offload_capa =
2352                 DEV_RX_OFFLOAD_VLAN_STRIP |
2353                 DEV_RX_OFFLOAD_QINQ_STRIP |
2354                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2355                 DEV_RX_OFFLOAD_UDP_CKSUM |
2356                 DEV_RX_OFFLOAD_TCP_CKSUM;
2357         dev_info->tx_offload_capa =
2358                 DEV_TX_OFFLOAD_VLAN_INSERT |
2359                 DEV_TX_OFFLOAD_QINQ_INSERT |
2360                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2361                 DEV_TX_OFFLOAD_UDP_CKSUM |
2362                 DEV_TX_OFFLOAD_TCP_CKSUM |
2363                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2364                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2365                 DEV_TX_OFFLOAD_TCP_TSO;
2366         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2367                                                 sizeof(uint32_t);
2368         dev_info->reta_size = pf->hash_lut_size;
2369         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2370
2371         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2372                 .rx_thresh = {
2373                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2374                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2375                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2376                 },
2377                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2378                 .rx_drop_en = 0,
2379         };
2380
2381         dev_info->default_txconf = (struct rte_eth_txconf) {
2382                 .tx_thresh = {
2383                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2384                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2385                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2386                 },
2387                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2388                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2389                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2390                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2391         };
2392
2393         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2394                 .nb_max = I40E_MAX_RING_DESC,
2395                 .nb_min = I40E_MIN_RING_DESC,
2396                 .nb_align = I40E_ALIGN_RING_DESC,
2397         };
2398
2399         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2400                 .nb_max = I40E_MAX_RING_DESC,
2401                 .nb_min = I40E_MIN_RING_DESC,
2402                 .nb_align = I40E_ALIGN_RING_DESC,
2403         };
2404
2405         if (pf->flags & I40E_FLAG_VMDQ) {
2406                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2407                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2408                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2409                                                 pf->max_nb_vmdq_vsi;
2410                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2411                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2412                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2413         }
2414
2415         if (i40e_is_40G_device(hw->device_id))
2416                 /* For XL710 */
2417                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2418         else
2419                 /* For X710 */
2420                 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2421 }
2422
2423 static int
2424 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2425 {
2426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2427         struct i40e_vsi *vsi = pf->main_vsi;
2428         PMD_INIT_FUNC_TRACE();
2429
2430         if (on)
2431                 return i40e_vsi_add_vlan(vsi, vlan_id);
2432         else
2433                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2434 }
2435
2436 static int
2437 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2438                    enum rte_vlan_type vlan_type,
2439                    uint16_t tpid)
2440 {
2441         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442         uint64_t reg_r = 0, reg_w = 0;
2443         uint16_t reg_id = 0;
2444         int ret = 0;
2445
2446         switch (vlan_type) {
2447         case ETH_VLAN_TYPE_OUTER:
2448                 reg_id = 2;
2449                 break;
2450         case ETH_VLAN_TYPE_INNER:
2451                 reg_id = 3;
2452                 break;
2453         default:
2454                 ret = -EINVAL;
2455                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2456                 return ret;
2457         }
2458         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2459                                           &reg_r, NULL);
2460         if (ret != I40E_SUCCESS) {
2461                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2462                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2463                 ret = -EIO;
2464                 return ret;
2465         }
2466         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2467                     "0x%08"PRIx64"", reg_id, reg_r);
2468
2469         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2470         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2471         if (reg_r == reg_w) {
2472                 ret = 0;
2473                 PMD_DRV_LOG(DEBUG, "No need to write");
2474                 return ret;
2475         }
2476
2477         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2478                                            reg_w, NULL);
2479         if (ret != I40E_SUCCESS) {
2480                 ret = -EIO;
2481                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2482                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2483                 return ret;
2484         }
2485         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2486                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2487
2488         return ret;
2489 }
2490
2491 static void
2492 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2493 {
2494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2495         struct i40e_vsi *vsi = pf->main_vsi;
2496
2497         if (mask & ETH_VLAN_FILTER_MASK) {
2498                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2499                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2500                 else
2501                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2502         }
2503
2504         if (mask & ETH_VLAN_STRIP_MASK) {
2505                 /* Enable or disable VLAN stripping */
2506                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2507                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2508                 else
2509                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2510         }
2511
2512         if (mask & ETH_VLAN_EXTEND_MASK) {
2513                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2514                         i40e_vsi_config_double_vlan(vsi, TRUE);
2515                 else
2516                         i40e_vsi_config_double_vlan(vsi, FALSE);
2517         }
2518 }
2519
2520 static void
2521 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2522                           __rte_unused uint16_t queue,
2523                           __rte_unused int on)
2524 {
2525         PMD_INIT_FUNC_TRACE();
2526 }
2527
2528 static int
2529 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2530 {
2531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2532         struct i40e_vsi *vsi = pf->main_vsi;
2533         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2534         struct i40e_vsi_vlan_pvid_info info;
2535
2536         memset(&info, 0, sizeof(info));
2537         info.on = on;
2538         if (info.on)
2539                 info.config.pvid = pvid;
2540         else {
2541                 info.config.reject.tagged =
2542                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2543                 info.config.reject.untagged =
2544                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2545         }
2546
2547         return i40e_vsi_vlan_pvid_set(vsi, &info);
2548 }
2549
2550 static int
2551 i40e_dev_led_on(struct rte_eth_dev *dev)
2552 {
2553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2554         uint32_t mode = i40e_led_get(hw);
2555
2556         if (mode == 0)
2557                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2558
2559         return 0;
2560 }
2561
2562 static int
2563 i40e_dev_led_off(struct rte_eth_dev *dev)
2564 {
2565         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2566         uint32_t mode = i40e_led_get(hw);
2567
2568         if (mode != 0)
2569                 i40e_led_set(hw, 0, false);
2570
2571         return 0;
2572 }
2573
2574 static int
2575 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2576 {
2577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2579
2580         fc_conf->pause_time = pf->fc_conf.pause_time;
2581         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2582         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2583
2584          /* Return current mode according to actual setting*/
2585         switch (hw->fc.current_mode) {
2586         case I40E_FC_FULL:
2587                 fc_conf->mode = RTE_FC_FULL;
2588                 break;
2589         case I40E_FC_TX_PAUSE:
2590                 fc_conf->mode = RTE_FC_TX_PAUSE;
2591                 break;
2592         case I40E_FC_RX_PAUSE:
2593                 fc_conf->mode = RTE_FC_RX_PAUSE;
2594                 break;
2595         case I40E_FC_NONE:
2596         default:
2597                 fc_conf->mode = RTE_FC_NONE;
2598         };
2599
2600         return 0;
2601 }
2602
2603 static int
2604 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2605 {
2606         uint32_t mflcn_reg, fctrl_reg, reg;
2607         uint32_t max_high_water;
2608         uint8_t i, aq_failure;
2609         int err;
2610         struct i40e_hw *hw;
2611         struct i40e_pf *pf;
2612         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2613                 [RTE_FC_NONE] = I40E_FC_NONE,
2614                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2615                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2616                 [RTE_FC_FULL] = I40E_FC_FULL
2617         };
2618
2619         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2620
2621         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2622         if ((fc_conf->high_water > max_high_water) ||
2623                         (fc_conf->high_water < fc_conf->low_water)) {
2624                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2625                         "High_water must <= %d.", max_high_water);
2626                 return -EINVAL;
2627         }
2628
2629         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2631         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2632
2633         pf->fc_conf.pause_time = fc_conf->pause_time;
2634         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2635         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2636
2637         PMD_INIT_FUNC_TRACE();
2638
2639         /* All the link flow control related enable/disable register
2640          * configuration is handle by the F/W
2641          */
2642         err = i40e_set_fc(hw, &aq_failure, true);
2643         if (err < 0)
2644                 return -ENOSYS;
2645
2646         if (i40e_is_40G_device(hw->device_id)) {
2647                 /* Configure flow control refresh threshold,
2648                  * the value for stat_tx_pause_refresh_timer[8]
2649                  * is used for global pause operation.
2650                  */
2651
2652                 I40E_WRITE_REG(hw,
2653                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2654                                pf->fc_conf.pause_time);
2655
2656                 /* configure the timer value included in transmitted pause
2657                  * frame,
2658                  * the value for stat_tx_pause_quanta[8] is used for global
2659                  * pause operation
2660                  */
2661                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2662                                pf->fc_conf.pause_time);
2663
2664                 fctrl_reg = I40E_READ_REG(hw,
2665                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2666
2667                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2668                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2669                 else
2670                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2671
2672                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2673                                fctrl_reg);
2674         } else {
2675                 /* Configure pause time (2 TCs per register) */
2676                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2677                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2678                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2679
2680                 /* Configure flow control refresh threshold value */
2681                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2682                                pf->fc_conf.pause_time / 2);
2683
2684                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2685
2686                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2687                  *depending on configuration
2688                  */
2689                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2690                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2691                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2692                 } else {
2693                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2694                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2695                 }
2696
2697                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2698         }
2699
2700         /* config the water marker both based on the packets and bytes */
2701         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2702                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2703                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2704         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2705                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2706                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2707         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2708                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2709                        << I40E_KILOSHIFT);
2710         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2711                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2712                        << I40E_KILOSHIFT);
2713
2714         I40E_WRITE_FLUSH(hw);
2715
2716         return 0;
2717 }
2718
2719 static int
2720 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2721                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2722 {
2723         PMD_INIT_FUNC_TRACE();
2724
2725         return -ENOSYS;
2726 }
2727
2728 /* Add a MAC address, and update filters */
2729 static void
2730 i40e_macaddr_add(struct rte_eth_dev *dev,
2731                  struct ether_addr *mac_addr,
2732                  __rte_unused uint32_t index,
2733                  uint32_t pool)
2734 {
2735         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2736         struct i40e_mac_filter_info mac_filter;
2737         struct i40e_vsi *vsi;
2738         int ret;
2739
2740         /* If VMDQ not enabled or configured, return */
2741         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2742                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2743                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2744                         pool);
2745                 return;
2746         }
2747
2748         if (pool > pf->nb_cfg_vmdq_vsi) {
2749                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2750                                 pool, pf->nb_cfg_vmdq_vsi);
2751                 return;
2752         }
2753
2754         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2755         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2756                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2757         else
2758                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2759
2760         if (pool == 0)
2761                 vsi = pf->main_vsi;
2762         else
2763                 vsi = pf->vmdq[pool - 1].vsi;
2764
2765         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2766         if (ret != I40E_SUCCESS) {
2767                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2768                 return;
2769         }
2770 }
2771
2772 /* Remove a MAC address, and update filters */
2773 static void
2774 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2775 {
2776         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2777         struct i40e_vsi *vsi;
2778         struct rte_eth_dev_data *data = dev->data;
2779         struct ether_addr *macaddr;
2780         int ret;
2781         uint32_t i;
2782         uint64_t pool_sel;
2783
2784         macaddr = &(data->mac_addrs[index]);
2785
2786         pool_sel = dev->data->mac_pool_sel[index];
2787
2788         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2789                 if (pool_sel & (1ULL << i)) {
2790                         if (i == 0)
2791                                 vsi = pf->main_vsi;
2792                         else {
2793                                 /* No VMDQ pool enabled or configured */
2794                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2795                                         (i > pf->nb_cfg_vmdq_vsi)) {
2796                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2797                                                         "/configured");
2798                                         return;
2799                                 }
2800                                 vsi = pf->vmdq[i - 1].vsi;
2801                         }
2802                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2803
2804                         if (ret) {
2805                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2806                                 return;
2807                         }
2808                 }
2809         }
2810 }
2811
2812 /* Set perfect match or hash match of MAC and VLAN for a VF */
2813 static int
2814 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2815                  struct rte_eth_mac_filter *filter,
2816                  bool add)
2817 {
2818         struct i40e_hw *hw;
2819         struct i40e_mac_filter_info mac_filter;
2820         struct ether_addr old_mac;
2821         struct ether_addr *new_mac;
2822         struct i40e_pf_vf *vf = NULL;
2823         uint16_t vf_id;
2824         int ret;
2825
2826         if (pf == NULL) {
2827                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2828                 return -EINVAL;
2829         }
2830         hw = I40E_PF_TO_HW(pf);
2831
2832         if (filter == NULL) {
2833                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2834                 return -EINVAL;
2835         }
2836
2837         new_mac = &filter->mac_addr;
2838
2839         if (is_zero_ether_addr(new_mac)) {
2840                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2841                 return -EINVAL;
2842         }
2843
2844         vf_id = filter->dst_id;
2845
2846         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2847                 PMD_DRV_LOG(ERR, "Invalid argument.");
2848                 return -EINVAL;
2849         }
2850         vf = &pf->vfs[vf_id];
2851
2852         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2853                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2854                 return -EINVAL;
2855         }
2856
2857         if (add) {
2858                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2859                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2860                                 ETHER_ADDR_LEN);
2861                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2862                                  ETHER_ADDR_LEN);
2863
2864                 mac_filter.filter_type = filter->filter_type;
2865                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2866                 if (ret != I40E_SUCCESS) {
2867                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2868                         return -1;
2869                 }
2870                 ether_addr_copy(new_mac, &pf->dev_addr);
2871         } else {
2872                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2873                                 ETHER_ADDR_LEN);
2874                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2875                 if (ret != I40E_SUCCESS) {
2876                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2877                         return -1;
2878                 }
2879
2880                 /* Clear device address as it has been removed */
2881                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2882                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2883         }
2884
2885         return 0;
2886 }
2887
2888 /* MAC filter handle */
2889 static int
2890 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2891                 void *arg)
2892 {
2893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2894         struct rte_eth_mac_filter *filter;
2895         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2896         int ret = I40E_NOT_SUPPORTED;
2897
2898         filter = (struct rte_eth_mac_filter *)(arg);
2899
2900         switch (filter_op) {
2901         case RTE_ETH_FILTER_NOP:
2902                 ret = I40E_SUCCESS;
2903                 break;
2904         case RTE_ETH_FILTER_ADD:
2905                 i40e_pf_disable_irq0(hw);
2906                 if (filter->is_vf)
2907                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2908                 i40e_pf_enable_irq0(hw);
2909                 break;
2910         case RTE_ETH_FILTER_DELETE:
2911                 i40e_pf_disable_irq0(hw);
2912                 if (filter->is_vf)
2913                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2914                 i40e_pf_enable_irq0(hw);
2915                 break;
2916         default:
2917                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2918                 ret = I40E_ERR_PARAM;
2919                 break;
2920         }
2921
2922         return ret;
2923 }
2924
2925 static int
2926 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2927 {
2928         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2929         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2930         int ret;
2931
2932         if (!lut)
2933                 return -EINVAL;
2934
2935         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2936                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2937                                           lut, lut_size);
2938                 if (ret) {
2939                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2940                         return ret;
2941                 }
2942         } else {
2943                 uint32_t *lut_dw = (uint32_t *)lut;
2944                 uint16_t i, lut_size_dw = lut_size / 4;
2945
2946                 for (i = 0; i < lut_size_dw; i++)
2947                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2948         }
2949
2950         return 0;
2951 }
2952
2953 static int
2954 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2955 {
2956         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2957         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2958         int ret;
2959
2960         if (!vsi || !lut)
2961                 return -EINVAL;
2962
2963         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2964                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2965                                           lut, lut_size);
2966                 if (ret) {
2967                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2968                         return ret;
2969                 }
2970         } else {
2971                 uint32_t *lut_dw = (uint32_t *)lut;
2972                 uint16_t i, lut_size_dw = lut_size / 4;
2973
2974                 for (i = 0; i < lut_size_dw; i++)
2975                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2976                 I40E_WRITE_FLUSH(hw);
2977         }
2978
2979         return 0;
2980 }
2981
2982 static int
2983 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2984                          struct rte_eth_rss_reta_entry64 *reta_conf,
2985                          uint16_t reta_size)
2986 {
2987         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2988         uint16_t i, lut_size = pf->hash_lut_size;
2989         uint16_t idx, shift;
2990         uint8_t *lut;
2991         int ret;
2992
2993         if (reta_size != lut_size ||
2994                 reta_size > ETH_RSS_RETA_SIZE_512) {
2995                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2996                         "(%d) doesn't match the number hardware can supported "
2997                                         "(%d)\n", reta_size, lut_size);
2998                 return -EINVAL;
2999         }
3000
3001         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3002         if (!lut) {
3003                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3004                 return -ENOMEM;
3005         }
3006         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3007         if (ret)
3008                 goto out;
3009         for (i = 0; i < reta_size; i++) {
3010                 idx = i / RTE_RETA_GROUP_SIZE;
3011                 shift = i % RTE_RETA_GROUP_SIZE;
3012                 if (reta_conf[idx].mask & (1ULL << shift))
3013                         lut[i] = reta_conf[idx].reta[shift];
3014         }
3015         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3016
3017 out:
3018         rte_free(lut);
3019
3020         return ret;
3021 }
3022
3023 static int
3024 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3025                         struct rte_eth_rss_reta_entry64 *reta_conf,
3026                         uint16_t reta_size)
3027 {
3028         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3029         uint16_t i, lut_size = pf->hash_lut_size;
3030         uint16_t idx, shift;
3031         uint8_t *lut;
3032         int ret;
3033
3034         if (reta_size != lut_size ||
3035                 reta_size > ETH_RSS_RETA_SIZE_512) {
3036                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3037                         "(%d) doesn't match the number hardware can supported "
3038                                         "(%d)\n", reta_size, lut_size);
3039                 return -EINVAL;
3040         }
3041
3042         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3043         if (!lut) {
3044                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3045                 return -ENOMEM;
3046         }
3047
3048         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3049         if (ret)
3050                 goto out;
3051         for (i = 0; i < reta_size; i++) {
3052                 idx = i / RTE_RETA_GROUP_SIZE;
3053                 shift = i % RTE_RETA_GROUP_SIZE;
3054                 if (reta_conf[idx].mask & (1ULL << shift))
3055                         reta_conf[idx].reta[shift] = lut[i];
3056         }
3057
3058 out:
3059         rte_free(lut);
3060
3061         return ret;
3062 }
3063
3064 /**
3065  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3066  * @hw:   pointer to the HW structure
3067  * @mem:  pointer to mem struct to fill out
3068  * @size: size of memory requested
3069  * @alignment: what to align the allocation to
3070  **/
3071 enum i40e_status_code
3072 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3073                         struct i40e_dma_mem *mem,
3074                         u64 size,
3075                         u32 alignment)
3076 {
3077         const struct rte_memzone *mz = NULL;
3078         char z_name[RTE_MEMZONE_NAMESIZE];
3079
3080         if (!mem)
3081                 return I40E_ERR_PARAM;
3082
3083         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3084         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3085                                          alignment, RTE_PGSIZE_2M);
3086         if (!mz)
3087                 return I40E_ERR_NO_MEMORY;
3088
3089         mem->size = size;
3090         mem->va = mz->addr;
3091         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3092         mem->zone = (const void *)mz;
3093         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3094                     "%"PRIu64, mz->name, mem->pa);
3095
3096         return I40E_SUCCESS;
3097 }
3098
3099 /**
3100  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3101  * @hw:   pointer to the HW structure
3102  * @mem:  ptr to mem struct to free
3103  **/
3104 enum i40e_status_code
3105 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3106                     struct i40e_dma_mem *mem)
3107 {
3108         if (!mem)
3109                 return I40E_ERR_PARAM;
3110
3111         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3112                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3113                     mem->pa);
3114         rte_memzone_free((const struct rte_memzone *)mem->zone);
3115         mem->zone = NULL;
3116         mem->va = NULL;
3117         mem->pa = (u64)0;
3118
3119         return I40E_SUCCESS;
3120 }
3121
3122 /**
3123  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3124  * @hw:   pointer to the HW structure
3125  * @mem:  pointer to mem struct to fill out
3126  * @size: size of memory requested
3127  **/
3128 enum i40e_status_code
3129 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3130                          struct i40e_virt_mem *mem,
3131                          u32 size)
3132 {
3133         if (!mem)
3134                 return I40E_ERR_PARAM;
3135
3136         mem->size = size;
3137         mem->va = rte_zmalloc("i40e", size, 0);
3138
3139         if (mem->va)
3140                 return I40E_SUCCESS;
3141         else
3142                 return I40E_ERR_NO_MEMORY;
3143 }
3144
3145 /**
3146  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3147  * @hw:   pointer to the HW structure
3148  * @mem:  pointer to mem struct to free
3149  **/
3150 enum i40e_status_code
3151 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3152                      struct i40e_virt_mem *mem)
3153 {
3154         if (!mem)
3155                 return I40E_ERR_PARAM;
3156
3157         rte_free(mem->va);
3158         mem->va = NULL;
3159
3160         return I40E_SUCCESS;
3161 }
3162
3163 void
3164 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3165 {
3166         rte_spinlock_init(&sp->spinlock);
3167 }
3168
3169 void
3170 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3171 {
3172         rte_spinlock_lock(&sp->spinlock);
3173 }
3174
3175 void
3176 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3177 {
3178         rte_spinlock_unlock(&sp->spinlock);
3179 }
3180
3181 void
3182 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3183 {
3184         return;
3185 }
3186
3187 /**
3188  * Get the hardware capabilities, which will be parsed
3189  * and saved into struct i40e_hw.
3190  */
3191 static int
3192 i40e_get_cap(struct i40e_hw *hw)
3193 {
3194         struct i40e_aqc_list_capabilities_element_resp *buf;
3195         uint16_t len, size = 0;
3196         int ret;
3197
3198         /* Calculate a huge enough buff for saving response data temporarily */
3199         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3200                                                 I40E_MAX_CAP_ELE_NUM;
3201         buf = rte_zmalloc("i40e", len, 0);
3202         if (!buf) {
3203                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3204                 return I40E_ERR_NO_MEMORY;
3205         }
3206
3207         /* Get, parse the capabilities and save it to hw */
3208         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3209                         i40e_aqc_opc_list_func_capabilities, NULL);
3210         if (ret != I40E_SUCCESS)
3211                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3212
3213         /* Free the temporary buffer after being used */
3214         rte_free(buf);
3215
3216         return ret;
3217 }
3218
3219 static int
3220 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3221 {
3222         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3223         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3224         uint16_t qp_count = 0, vsi_count = 0;
3225
3226         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3227                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3228                 return -EINVAL;
3229         }
3230         /* Add the parameter init for LFC */
3231         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3232         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3233         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3234
3235         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3236         pf->max_num_vsi = hw->func_caps.num_vsis;
3237         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3238         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3239         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3240
3241         /* FDir queue/VSI allocation */
3242         pf->fdir_qp_offset = 0;
3243         if (hw->func_caps.fd) {
3244                 pf->flags |= I40E_FLAG_FDIR;
3245                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3246         } else {
3247                 pf->fdir_nb_qps = 0;
3248         }
3249         qp_count += pf->fdir_nb_qps;
3250         vsi_count += 1;
3251
3252         /* LAN queue/VSI allocation */
3253         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3254         if (!hw->func_caps.rss) {
3255                 pf->lan_nb_qps = 1;
3256         } else {
3257                 pf->flags |= I40E_FLAG_RSS;
3258                 if (hw->mac.type == I40E_MAC_X722)
3259                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3260                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3261         }
3262         qp_count += pf->lan_nb_qps;
3263         vsi_count += 1;
3264
3265         /* VF queue/VSI allocation */
3266         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3267         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3268                 pf->flags |= I40E_FLAG_SRIOV;
3269                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3270                 pf->vf_num = dev->pci_dev->max_vfs;
3271                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3272                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3273                             pf->vf_nb_qps * pf->vf_num);
3274         } else {
3275                 pf->vf_nb_qps = 0;
3276                 pf->vf_num = 0;
3277         }
3278         qp_count += pf->vf_nb_qps * pf->vf_num;
3279         vsi_count += pf->vf_num;
3280
3281         /* VMDq queue/VSI allocation */
3282         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3283         pf->vmdq_nb_qps = 0;
3284         pf->max_nb_vmdq_vsi = 0;
3285         if (hw->func_caps.vmdq) {
3286                 if (qp_count < hw->func_caps.num_tx_qp &&
3287                         vsi_count < hw->func_caps.num_vsis) {
3288                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3289                                 qp_count) / pf->vmdq_nb_qp_max;
3290
3291                         /* Limit the maximum number of VMDq vsi to the maximum
3292                          * ethdev can support
3293                          */
3294                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3295                                 hw->func_caps.num_vsis - vsi_count);
3296                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3297                                 ETH_64_POOLS);
3298                         if (pf->max_nb_vmdq_vsi) {
3299                                 pf->flags |= I40E_FLAG_VMDQ;
3300                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3301                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3302                                             "per VMDQ VSI, in total %u queues",
3303                                             pf->max_nb_vmdq_vsi,
3304                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3305                                             pf->max_nb_vmdq_vsi);
3306                         } else {
3307                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3308                                             "VMDq");
3309                         }
3310                 } else {
3311                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3312                 }
3313         }
3314         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3315         vsi_count += pf->max_nb_vmdq_vsi;
3316
3317         if (hw->func_caps.dcb)
3318                 pf->flags |= I40E_FLAG_DCB;
3319
3320         if (qp_count > hw->func_caps.num_tx_qp) {
3321                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3322                             "the hardware maximum %u", qp_count,
3323                             hw->func_caps.num_tx_qp);
3324                 return -EINVAL;
3325         }
3326         if (vsi_count > hw->func_caps.num_vsis) {
3327                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3328                             "the hardware maximum %u", vsi_count,
3329                             hw->func_caps.num_vsis);
3330                 return -EINVAL;
3331         }
3332
3333         return 0;
3334 }
3335
3336 static int
3337 i40e_pf_get_switch_config(struct i40e_pf *pf)
3338 {
3339         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3340         struct i40e_aqc_get_switch_config_resp *switch_config;
3341         struct i40e_aqc_switch_config_element_resp *element;
3342         uint16_t start_seid = 0, num_reported;
3343         int ret;
3344
3345         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3346                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3347         if (!switch_config) {
3348                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3349                 return -ENOMEM;
3350         }
3351
3352         /* Get the switch configurations */
3353         ret = i40e_aq_get_switch_config(hw, switch_config,
3354                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3355         if (ret != I40E_SUCCESS) {
3356                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3357                 goto fail;
3358         }
3359         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3360         if (num_reported != 1) { /* The number should be 1 */
3361                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3362                 goto fail;
3363         }
3364
3365         /* Parse the switch configuration elements */
3366         element = &(switch_config->element[0]);
3367         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3368                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3369                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3370         } else
3371                 PMD_DRV_LOG(INFO, "Unknown element type");
3372
3373 fail:
3374         rte_free(switch_config);
3375
3376         return ret;
3377 }
3378
3379 static int
3380 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3381                         uint32_t num)
3382 {
3383         struct pool_entry *entry;
3384
3385         if (pool == NULL || num == 0)
3386                 return -EINVAL;
3387
3388         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3389         if (entry == NULL) {
3390                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3391                 return -ENOMEM;
3392         }
3393
3394         /* queue heap initialize */
3395         pool->num_free = num;
3396         pool->num_alloc = 0;
3397         pool->base = base;
3398         LIST_INIT(&pool->alloc_list);
3399         LIST_INIT(&pool->free_list);
3400
3401         /* Initialize element  */
3402         entry->base = 0;
3403         entry->len = num;
3404
3405         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3406         return 0;
3407 }
3408
3409 static void
3410 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3411 {
3412         struct pool_entry *entry, *next_entry;
3413
3414         if (pool == NULL)
3415                 return;
3416
3417         for (entry = LIST_FIRST(&pool->alloc_list);
3418                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3419                         entry = next_entry) {
3420                 LIST_REMOVE(entry, next);
3421                 rte_free(entry);
3422         }
3423
3424         for (entry = LIST_FIRST(&pool->free_list);
3425                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3426                         entry = next_entry) {
3427                 LIST_REMOVE(entry, next);
3428                 rte_free(entry);
3429         }
3430
3431         pool->num_free = 0;
3432         pool->num_alloc = 0;
3433         pool->base = 0;
3434         LIST_INIT(&pool->alloc_list);
3435         LIST_INIT(&pool->free_list);
3436 }
3437
3438 static int
3439 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3440                        uint32_t base)
3441 {
3442         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3443         uint32_t pool_offset;
3444         int insert;
3445
3446         if (pool == NULL) {
3447                 PMD_DRV_LOG(ERR, "Invalid parameter");
3448                 return -EINVAL;
3449         }
3450
3451         pool_offset = base - pool->base;
3452         /* Lookup in alloc list */
3453         LIST_FOREACH(entry, &pool->alloc_list, next) {
3454                 if (entry->base == pool_offset) {
3455                         valid_entry = entry;
3456                         LIST_REMOVE(entry, next);
3457                         break;
3458                 }
3459         }
3460
3461         /* Not find, return */
3462         if (valid_entry == NULL) {
3463                 PMD_DRV_LOG(ERR, "Failed to find entry");
3464                 return -EINVAL;
3465         }
3466
3467         /**
3468          * Found it, move it to free list  and try to merge.
3469          * In order to make merge easier, always sort it by qbase.
3470          * Find adjacent prev and last entries.
3471          */
3472         prev = next = NULL;
3473         LIST_FOREACH(entry, &pool->free_list, next) {
3474                 if (entry->base > valid_entry->base) {
3475                         next = entry;
3476                         break;
3477                 }
3478                 prev = entry;
3479         }
3480
3481         insert = 0;
3482         /* Try to merge with next one*/
3483         if (next != NULL) {
3484                 /* Merge with next one */
3485                 if (valid_entry->base + valid_entry->len == next->base) {
3486                         next->base = valid_entry->base;
3487                         next->len += valid_entry->len;
3488                         rte_free(valid_entry);
3489                         valid_entry = next;
3490                         insert = 1;
3491                 }
3492         }
3493
3494         if (prev != NULL) {
3495                 /* Merge with previous one */
3496                 if (prev->base + prev->len == valid_entry->base) {
3497                         prev->len += valid_entry->len;
3498                         /* If it merge with next one, remove next node */
3499                         if (insert == 1) {
3500                                 LIST_REMOVE(valid_entry, next);
3501                                 rte_free(valid_entry);
3502                         } else {
3503                                 rte_free(valid_entry);
3504                                 insert = 1;
3505                         }
3506                 }
3507         }
3508
3509         /* Not find any entry to merge, insert */
3510         if (insert == 0) {
3511                 if (prev != NULL)
3512                         LIST_INSERT_AFTER(prev, valid_entry, next);
3513                 else if (next != NULL)
3514                         LIST_INSERT_BEFORE(next, valid_entry, next);
3515                 else /* It's empty list, insert to head */
3516                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3517         }
3518
3519         pool->num_free += valid_entry->len;
3520         pool->num_alloc -= valid_entry->len;
3521
3522         return 0;
3523 }
3524
3525 static int
3526 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3527                        uint16_t num)
3528 {
3529         struct pool_entry *entry, *valid_entry;
3530
3531         if (pool == NULL || num == 0) {
3532                 PMD_DRV_LOG(ERR, "Invalid parameter");
3533                 return -EINVAL;
3534         }
3535
3536         if (pool->num_free < num) {
3537                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3538                             num, pool->num_free);
3539                 return -ENOMEM;
3540         }
3541
3542         valid_entry = NULL;
3543         /* Lookup  in free list and find most fit one */
3544         LIST_FOREACH(entry, &pool->free_list, next) {
3545                 if (entry->len >= num) {
3546                         /* Find best one */
3547                         if (entry->len == num) {
3548                                 valid_entry = entry;
3549                                 break;
3550                         }
3551                         if (valid_entry == NULL || valid_entry->len > entry->len)
3552                                 valid_entry = entry;
3553                 }
3554         }
3555
3556         /* Not find one to satisfy the request, return */
3557         if (valid_entry == NULL) {
3558                 PMD_DRV_LOG(ERR, "No valid entry found");
3559                 return -ENOMEM;
3560         }
3561         /**
3562          * The entry have equal queue number as requested,
3563          * remove it from alloc_list.
3564          */
3565         if (valid_entry->len == num) {
3566                 LIST_REMOVE(valid_entry, next);
3567         } else {
3568                 /**
3569                  * The entry have more numbers than requested,
3570                  * create a new entry for alloc_list and minus its
3571                  * queue base and number in free_list.
3572                  */
3573                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3574                 if (entry == NULL) {
3575                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3576                                     "resource pool");
3577                         return -ENOMEM;
3578                 }
3579                 entry->base = valid_entry->base;
3580                 entry->len = num;
3581                 valid_entry->base += num;
3582                 valid_entry->len -= num;
3583                 valid_entry = entry;
3584         }
3585
3586         /* Insert it into alloc list, not sorted */
3587         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3588
3589         pool->num_free -= valid_entry->len;
3590         pool->num_alloc += valid_entry->len;
3591
3592         return valid_entry->base + pool->base;
3593 }
3594
3595 /**
3596  * bitmap_is_subset - Check whether src2 is subset of src1
3597  **/
3598 static inline int
3599 bitmap_is_subset(uint8_t src1, uint8_t src2)
3600 {
3601         return !((src1 ^ src2) & src2);
3602 }
3603
3604 static enum i40e_status_code
3605 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3606 {
3607         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3608
3609         /* If DCB is not supported, only default TC is supported */
3610         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3611                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3612                 return I40E_NOT_SUPPORTED;
3613         }
3614
3615         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3616                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3617                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3618                             enabled_tcmap);
3619                 return I40E_NOT_SUPPORTED;
3620         }
3621         return I40E_SUCCESS;
3622 }
3623
3624 int
3625 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3626                                 struct i40e_vsi_vlan_pvid_info *info)
3627 {
3628         struct i40e_hw *hw;
3629         struct i40e_vsi_context ctxt;
3630         uint8_t vlan_flags = 0;
3631         int ret;
3632
3633         if (vsi == NULL || info == NULL) {
3634                 PMD_DRV_LOG(ERR, "invalid parameters");
3635                 return I40E_ERR_PARAM;
3636         }
3637
3638         if (info->on) {
3639                 vsi->info.pvid = info->config.pvid;
3640                 /**
3641                  * If insert pvid is enabled, only tagged pkts are
3642                  * allowed to be sent out.
3643                  */
3644                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3645                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3646         } else {
3647                 vsi->info.pvid = 0;
3648                 if (info->config.reject.tagged == 0)
3649                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3650
3651                 if (info->config.reject.untagged == 0)
3652                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3653         }
3654         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3655                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3656         vsi->info.port_vlan_flags |= vlan_flags;
3657         vsi->info.valid_sections =
3658                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3659         memset(&ctxt, 0, sizeof(ctxt));
3660         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3661         ctxt.seid = vsi->seid;
3662
3663         hw = I40E_VSI_TO_HW(vsi);
3664         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3665         if (ret != I40E_SUCCESS)
3666                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3667
3668         return ret;
3669 }
3670
3671 static int
3672 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3673 {
3674         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3675         int i, ret;
3676         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3677
3678         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3679         if (ret != I40E_SUCCESS)
3680                 return ret;
3681
3682         if (!vsi->seid) {
3683                 PMD_DRV_LOG(ERR, "seid not valid");
3684                 return -EINVAL;
3685         }
3686
3687         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3688         tc_bw_data.tc_valid_bits = enabled_tcmap;
3689         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3690                 tc_bw_data.tc_bw_credits[i] =
3691                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3692
3693         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3694         if (ret != I40E_SUCCESS) {
3695                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3696                 return ret;
3697         }
3698
3699         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3700                                         sizeof(vsi->info.qs_handle));
3701         return I40E_SUCCESS;
3702 }
3703
3704 static enum i40e_status_code
3705 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3706                                  struct i40e_aqc_vsi_properties_data *info,
3707                                  uint8_t enabled_tcmap)
3708 {
3709         enum i40e_status_code ret;
3710         int i, total_tc = 0;
3711         uint16_t qpnum_per_tc, bsf, qp_idx;
3712
3713         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3714         if (ret != I40E_SUCCESS)
3715                 return ret;
3716
3717         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3718                 if (enabled_tcmap & (1 << i))
3719                         total_tc++;
3720         vsi->enabled_tc = enabled_tcmap;
3721
3722         /* Number of queues per enabled TC */
3723         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3724         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3725         bsf = rte_bsf32(qpnum_per_tc);
3726
3727         /* Adjust the queue number to actual queues that can be applied */
3728         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3729                 vsi->nb_qps = qpnum_per_tc * total_tc;
3730
3731         /**
3732          * Configure TC and queue mapping parameters, for enabled TC,
3733          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3734          * default queue will serve it.
3735          */
3736         qp_idx = 0;
3737         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3738                 if (vsi->enabled_tc & (1 << i)) {
3739                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3740                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3741                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3742                         qp_idx += qpnum_per_tc;
3743                 } else
3744                         info->tc_mapping[i] = 0;
3745         }
3746
3747         /* Associate queue number with VSI */
3748         if (vsi->type == I40E_VSI_SRIOV) {
3749                 info->mapping_flags |=
3750                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3751                 for (i = 0; i < vsi->nb_qps; i++)
3752                         info->queue_mapping[i] =
3753                                 rte_cpu_to_le_16(vsi->base_queue + i);
3754         } else {
3755                 info->mapping_flags |=
3756                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3757                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3758         }
3759         info->valid_sections |=
3760                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3761
3762         return I40E_SUCCESS;
3763 }
3764
3765 static int
3766 i40e_veb_release(struct i40e_veb *veb)
3767 {
3768         struct i40e_vsi *vsi;
3769         struct i40e_hw *hw;
3770
3771         if (veb == NULL || veb->associate_vsi == NULL)
3772                 return -EINVAL;
3773
3774         if (!TAILQ_EMPTY(&veb->head)) {
3775                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3776                 return -EACCES;
3777         }
3778
3779         vsi = veb->associate_vsi;
3780         hw = I40E_VSI_TO_HW(vsi);
3781
3782         vsi->uplink_seid = veb->uplink_seid;
3783         i40e_aq_delete_element(hw, veb->seid, NULL);
3784         rte_free(veb);
3785         vsi->veb = NULL;
3786         return I40E_SUCCESS;
3787 }
3788
3789 /* Setup a veb */
3790 static struct i40e_veb *
3791 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3792 {
3793         struct i40e_veb *veb;
3794         int ret;
3795         struct i40e_hw *hw;
3796
3797         if (NULL == pf || vsi == NULL) {
3798                 PMD_DRV_LOG(ERR, "veb setup failed, "
3799                             "associated VSI shouldn't null");
3800                 return NULL;
3801         }
3802         hw = I40E_PF_TO_HW(pf);
3803
3804         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3805         if (!veb) {
3806                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3807                 goto fail;
3808         }
3809
3810         veb->associate_vsi = vsi;
3811         TAILQ_INIT(&veb->head);
3812         veb->uplink_seid = vsi->uplink_seid;
3813
3814         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3815                 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3816
3817         if (ret != I40E_SUCCESS) {
3818                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3819                             hw->aq.asq_last_status);
3820                 goto fail;
3821         }
3822
3823         /* get statistics index */
3824         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3825                                 &veb->stats_idx, NULL, NULL, NULL);
3826         if (ret != I40E_SUCCESS) {
3827                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3828                             hw->aq.asq_last_status);
3829                 goto fail;
3830         }
3831
3832         /* Get VEB bandwidth, to be implemented */
3833         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3834         vsi->uplink_seid = veb->seid;
3835
3836         return veb;
3837 fail:
3838         rte_free(veb);
3839         return NULL;
3840 }
3841
3842 int
3843 i40e_vsi_release(struct i40e_vsi *vsi)
3844 {
3845         struct i40e_pf *pf;
3846         struct i40e_hw *hw;
3847         struct i40e_vsi_list *vsi_list;
3848         int ret;
3849         struct i40e_mac_filter *f;
3850
3851         if (!vsi)
3852                 return I40E_SUCCESS;
3853
3854         pf = I40E_VSI_TO_PF(vsi);
3855         hw = I40E_VSI_TO_HW(vsi);
3856
3857         /* VSI has child to attach, release child first */
3858         if (vsi->veb) {
3859                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3860                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3861                                 return -1;
3862                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3863                 }
3864                 i40e_veb_release(vsi->veb);
3865         }
3866
3867         /* Remove all macvlan filters of the VSI */
3868         i40e_vsi_remove_all_macvlan_filter(vsi);
3869         TAILQ_FOREACH(f, &vsi->mac_list, next)
3870                 rte_free(f);
3871
3872         if (vsi->type != I40E_VSI_MAIN) {
3873                 /* Remove vsi from parent's sibling list */
3874                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3875                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3876                         return I40E_ERR_PARAM;
3877                 }
3878                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3879                                 &vsi->sib_vsi_list, list);
3880
3881                 /* Remove all switch element of the VSI */
3882                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3883                 if (ret != I40E_SUCCESS)
3884                         PMD_DRV_LOG(ERR, "Failed to delete element");
3885         }
3886         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3887
3888         if (vsi->type != I40E_VSI_SRIOV)
3889                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3890         rte_free(vsi);
3891
3892         return I40E_SUCCESS;
3893 }
3894
3895 static int
3896 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3897 {
3898         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3899         struct i40e_aqc_remove_macvlan_element_data def_filter;
3900         struct i40e_mac_filter_info filter;
3901         int ret;
3902
3903         if (vsi->type != I40E_VSI_MAIN)
3904                 return I40E_ERR_CONFIG;
3905         memset(&def_filter, 0, sizeof(def_filter));
3906         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3907                                         ETH_ADDR_LEN);
3908         def_filter.vlan_tag = 0;
3909         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3910                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3911         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3912         if (ret != I40E_SUCCESS) {
3913                 struct i40e_mac_filter *f;
3914                 struct ether_addr *mac;
3915
3916                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3917                             "macvlan filter");
3918                 /* It needs to add the permanent mac into mac list */
3919                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3920                 if (f == NULL) {
3921                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3922                         return I40E_ERR_NO_MEMORY;
3923                 }
3924                 mac = &f->mac_info.mac_addr;
3925                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3926                                 ETH_ADDR_LEN);
3927                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3928                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3929                 vsi->mac_num++;
3930
3931                 return ret;
3932         }
3933         (void)rte_memcpy(&filter.mac_addr,
3934                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3935         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3936         return i40e_vsi_add_mac(vsi, &filter);
3937 }
3938
3939 /*
3940  * i40e_vsi_get_bw_config - Query VSI BW Information
3941  * @vsi: the VSI to be queried
3942  *
3943  * Returns 0 on success, negative value on failure
3944  */
3945 static enum i40e_status_code
3946 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3947 {
3948         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3949         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3950         struct i40e_hw *hw = &vsi->adapter->hw;
3951         i40e_status ret;
3952         int i;
3953         uint32_t bw_max;
3954
3955         memset(&bw_config, 0, sizeof(bw_config));
3956         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3957         if (ret != I40E_SUCCESS) {
3958                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3959                             hw->aq.asq_last_status);
3960                 return ret;
3961         }
3962
3963         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3964         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3965                                         &ets_sla_config, NULL);
3966         if (ret != I40E_SUCCESS) {
3967                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3968                             "configuration %u", hw->aq.asq_last_status);
3969                 return ret;
3970         }
3971
3972         /* store and print out BW info */
3973         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3974         vsi->bw_info.bw_max = bw_config.max_bw;
3975         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3976         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3977         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3978                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3979                      I40E_16_BIT_WIDTH);
3980         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3981                 vsi->bw_info.bw_ets_share_credits[i] =
3982                                 ets_sla_config.share_credits[i];
3983                 vsi->bw_info.bw_ets_credits[i] =
3984                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3985                 /* 4 bits per TC, 4th bit is reserved */
3986                 vsi->bw_info.bw_ets_max[i] =
3987                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3988                                   RTE_LEN2MASK(3, uint8_t));
3989                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3990                             vsi->bw_info.bw_ets_share_credits[i]);
3991                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3992                             vsi->bw_info.bw_ets_credits[i]);
3993                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3994                             vsi->bw_info.bw_ets_max[i]);
3995         }
3996
3997         return I40E_SUCCESS;
3998 }
3999
4000 /* i40e_enable_pf_lb
4001  * @pf: pointer to the pf structure
4002  *
4003  * allow loopback on pf
4004  */
4005 static inline void
4006 i40e_enable_pf_lb(struct i40e_pf *pf)
4007 {
4008         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4009         struct i40e_vsi_context ctxt;
4010         int ret;
4011
4012         /* Use the FW API if FW >= v5.0 */
4013         if (hw->aq.fw_maj_ver < 5) {
4014                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4015                 return;
4016         }
4017
4018         memset(&ctxt, 0, sizeof(ctxt));
4019         ctxt.seid = pf->main_vsi_seid;
4020         ctxt.pf_num = hw->pf_id;
4021         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4022         if (ret) {
4023                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4024                             ret, hw->aq.asq_last_status);
4025                 return;
4026         }
4027         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4028         ctxt.info.valid_sections =
4029                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4030         ctxt.info.switch_id |=
4031                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4032
4033         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4034         if (ret)
4035                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4036                             hw->aq.asq_last_status);
4037 }
4038
4039 /* Setup a VSI */
4040 struct i40e_vsi *
4041 i40e_vsi_setup(struct i40e_pf *pf,
4042                enum i40e_vsi_type type,
4043                struct i40e_vsi *uplink_vsi,
4044                uint16_t user_param)
4045 {
4046         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4047         struct i40e_vsi *vsi;
4048         struct i40e_mac_filter_info filter;
4049         int ret;
4050         struct i40e_vsi_context ctxt;
4051         struct ether_addr broadcast =
4052                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4053
4054         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
4055                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4056                             "VSI link shouldn't be NULL");
4057                 return NULL;
4058         }
4059
4060         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4061                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4062                             "uplink VSI should be NULL");
4063                 return NULL;
4064         }
4065
4066         /* If uplink vsi didn't setup VEB, create one first */
4067         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4068                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4069
4070                 if (NULL == uplink_vsi->veb) {
4071                         PMD_DRV_LOG(ERR, "VEB setup failed");
4072                         return NULL;
4073                 }
4074                 /* set ALLOWLOOPBACk on pf, when veb is created */
4075                 i40e_enable_pf_lb(pf);
4076         }
4077
4078         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4079         if (!vsi) {
4080                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4081                 return NULL;
4082         }
4083         TAILQ_INIT(&vsi->mac_list);
4084         vsi->type = type;
4085         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4086         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4087         vsi->parent_vsi = uplink_vsi;
4088         vsi->user_param = user_param;
4089         /* Allocate queues */
4090         switch (vsi->type) {
4091         case I40E_VSI_MAIN  :
4092                 vsi->nb_qps = pf->lan_nb_qps;
4093                 break;
4094         case I40E_VSI_SRIOV :
4095                 vsi->nb_qps = pf->vf_nb_qps;
4096                 break;
4097         case I40E_VSI_VMDQ2:
4098                 vsi->nb_qps = pf->vmdq_nb_qps;
4099                 break;
4100         case I40E_VSI_FDIR:
4101                 vsi->nb_qps = pf->fdir_nb_qps;
4102                 break;
4103         default:
4104                 goto fail_mem;
4105         }
4106         /*
4107          * The filter status descriptor is reported in rx queue 0,
4108          * while the tx queue for fdir filter programming has no
4109          * such constraints, can be non-zero queues.
4110          * To simplify it, choose FDIR vsi use queue 0 pair.
4111          * To make sure it will use queue 0 pair, queue allocation
4112          * need be done before this function is called
4113          */
4114         if (type != I40E_VSI_FDIR) {
4115                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4116                         if (ret < 0) {
4117                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4118                                                 vsi->seid, ret);
4119                                 goto fail_mem;
4120                         }
4121                         vsi->base_queue = ret;
4122         } else
4123                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4124
4125         /* VF has MSIX interrupt in VF range, don't allocate here */
4126         if (type == I40E_VSI_MAIN) {
4127                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4128                                           RTE_MIN(vsi->nb_qps,
4129                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4130                 if (ret < 0) {
4131                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4132                                     vsi->seid, ret);
4133                         goto fail_queue_alloc;
4134                 }
4135                 vsi->msix_intr = ret;
4136                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4137         } else if (type != I40E_VSI_SRIOV) {
4138                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4139                 if (ret < 0) {
4140                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4141                         goto fail_queue_alloc;
4142                 }
4143                 vsi->msix_intr = ret;
4144                 vsi->nb_msix = 1;
4145         } else {
4146                 vsi->msix_intr = 0;
4147                 vsi->nb_msix = 0;
4148         }
4149
4150         /* Add VSI */
4151         if (type == I40E_VSI_MAIN) {
4152                 /* For main VSI, no need to add since it's default one */
4153                 vsi->uplink_seid = pf->mac_seid;
4154                 vsi->seid = pf->main_vsi_seid;
4155                 /* Bind queues with specific MSIX interrupt */
4156                 /**
4157                  * Needs 2 interrupt at least, one for misc cause which will
4158                  * enabled from OS side, Another for queues binding the
4159                  * interrupt from device side only.
4160                  */
4161
4162                 /* Get default VSI parameters from hardware */
4163                 memset(&ctxt, 0, sizeof(ctxt));
4164                 ctxt.seid = vsi->seid;
4165                 ctxt.pf_num = hw->pf_id;
4166                 ctxt.uplink_seid = vsi->uplink_seid;
4167                 ctxt.vf_num = 0;
4168                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4169                 if (ret != I40E_SUCCESS) {
4170                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4171                         goto fail_msix_alloc;
4172                 }
4173                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4174                         sizeof(struct i40e_aqc_vsi_properties_data));
4175                 vsi->vsi_id = ctxt.vsi_number;
4176                 vsi->info.valid_sections = 0;
4177
4178                 /* Configure tc, enabled TC0 only */
4179                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4180                         I40E_SUCCESS) {
4181                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4182                         goto fail_msix_alloc;
4183                 }
4184
4185                 /* TC, queue mapping */
4186                 memset(&ctxt, 0, sizeof(ctxt));
4187                 vsi->info.valid_sections |=
4188                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4189                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4190                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4191                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4192                         sizeof(struct i40e_aqc_vsi_properties_data));
4193                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4194                                                 I40E_DEFAULT_TCMAP);
4195                 if (ret != I40E_SUCCESS) {
4196                         PMD_DRV_LOG(ERR, "Failed to configure "
4197                                     "TC queue mapping");
4198                         goto fail_msix_alloc;
4199                 }
4200                 ctxt.seid = vsi->seid;
4201                 ctxt.pf_num = hw->pf_id;
4202                 ctxt.uplink_seid = vsi->uplink_seid;
4203                 ctxt.vf_num = 0;
4204
4205                 /* Update VSI parameters */
4206                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4207                 if (ret != I40E_SUCCESS) {
4208                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4209                         goto fail_msix_alloc;
4210                 }
4211
4212                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4213                                                 sizeof(vsi->info.tc_mapping));
4214                 (void)rte_memcpy(&vsi->info.queue_mapping,
4215                                 &ctxt.info.queue_mapping,
4216                         sizeof(vsi->info.queue_mapping));
4217                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4218                 vsi->info.valid_sections = 0;
4219
4220                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4221                                 ETH_ADDR_LEN);
4222
4223                 /**
4224                  * Updating default filter settings are necessary to prevent
4225                  * reception of tagged packets.
4226                  * Some old firmware configurations load a default macvlan
4227                  * filter which accepts both tagged and untagged packets.
4228                  * The updating is to use a normal filter instead if needed.
4229                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4230                  * The firmware with correct configurations load the default
4231                  * macvlan filter which is expected and cannot be removed.
4232                  */
4233                 i40e_update_default_filter_setting(vsi);
4234                 i40e_config_qinq(hw, vsi);
4235         } else if (type == I40E_VSI_SRIOV) {
4236                 memset(&ctxt, 0, sizeof(ctxt));
4237                 /**
4238                  * For other VSI, the uplink_seid equals to uplink VSI's
4239                  * uplink_seid since they share same VEB
4240                  */
4241                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4242                 ctxt.pf_num = hw->pf_id;
4243                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4244                 ctxt.uplink_seid = vsi->uplink_seid;
4245                 ctxt.connection_type = 0x1;
4246                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4247
4248                 /* Use the VEB configuration if FW >= v5.0 */
4249                 if (hw->aq.fw_maj_ver >= 5) {
4250                         /* Configure switch ID */
4251                         ctxt.info.valid_sections |=
4252                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4253                         ctxt.info.switch_id =
4254                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4255                 }
4256
4257                 /* Configure port/vlan */
4258                 ctxt.info.valid_sections |=
4259                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4260                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4261                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4262                                                 I40E_DEFAULT_TCMAP);
4263                 if (ret != I40E_SUCCESS) {
4264                         PMD_DRV_LOG(ERR, "Failed to configure "
4265                                     "TC queue mapping");
4266                         goto fail_msix_alloc;
4267                 }
4268                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4269                 ctxt.info.valid_sections |=
4270                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4271                 /**
4272                  * Since VSI is not created yet, only configure parameter,
4273                  * will add vsi below.
4274                  */
4275
4276                 i40e_config_qinq(hw, vsi);
4277         } else if (type == I40E_VSI_VMDQ2) {
4278                 memset(&ctxt, 0, sizeof(ctxt));
4279                 /*
4280                  * For other VSI, the uplink_seid equals to uplink VSI's
4281                  * uplink_seid since they share same VEB
4282                  */
4283                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4284                 ctxt.pf_num = hw->pf_id;
4285                 ctxt.vf_num = 0;
4286                 ctxt.uplink_seid = vsi->uplink_seid;
4287                 ctxt.connection_type = 0x1;
4288                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4289
4290                 ctxt.info.valid_sections |=
4291                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4292                 /* user_param carries flag to enable loop back */
4293                 if (user_param) {
4294                         ctxt.info.switch_id =
4295                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4296                         ctxt.info.switch_id |=
4297                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4298                 }
4299
4300                 /* Configure port/vlan */
4301                 ctxt.info.valid_sections |=
4302                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4303                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4304                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4305                                                 I40E_DEFAULT_TCMAP);
4306                 if (ret != I40E_SUCCESS) {
4307                         PMD_DRV_LOG(ERR, "Failed to configure "
4308                                         "TC queue mapping");
4309                         goto fail_msix_alloc;
4310                 }
4311                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4312                 ctxt.info.valid_sections |=
4313                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4314         } else if (type == I40E_VSI_FDIR) {
4315                 memset(&ctxt, 0, sizeof(ctxt));
4316                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4317                 ctxt.pf_num = hw->pf_id;
4318                 ctxt.vf_num = 0;
4319                 ctxt.uplink_seid = vsi->uplink_seid;
4320                 ctxt.connection_type = 0x1;     /* regular data port */
4321                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4322                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4323                                                 I40E_DEFAULT_TCMAP);
4324                 if (ret != I40E_SUCCESS) {
4325                         PMD_DRV_LOG(ERR, "Failed to configure "
4326                                         "TC queue mapping.");
4327                         goto fail_msix_alloc;
4328                 }
4329                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4330                 ctxt.info.valid_sections |=
4331                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4332         } else {
4333                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4334                 goto fail_msix_alloc;
4335         }
4336
4337         if (vsi->type != I40E_VSI_MAIN) {
4338                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4339                 if (ret != I40E_SUCCESS) {
4340                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4341                                     hw->aq.asq_last_status);
4342                         goto fail_msix_alloc;
4343                 }
4344                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4345                 vsi->info.valid_sections = 0;
4346                 vsi->seid = ctxt.seid;
4347                 vsi->vsi_id = ctxt.vsi_number;
4348                 vsi->sib_vsi_list.vsi = vsi;
4349                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4350                                 &vsi->sib_vsi_list, list);
4351         }
4352
4353         /* MAC/VLAN configuration */
4354         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4355         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4356
4357         ret = i40e_vsi_add_mac(vsi, &filter);
4358         if (ret != I40E_SUCCESS) {
4359                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4360                 goto fail_msix_alloc;
4361         }
4362
4363         /* Get VSI BW information */
4364         i40e_vsi_get_bw_config(vsi);
4365         return vsi;
4366 fail_msix_alloc:
4367         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4368 fail_queue_alloc:
4369         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4370 fail_mem:
4371         rte_free(vsi);
4372         return NULL;
4373 }
4374
4375 /* Configure vlan filter on or off */
4376 int
4377 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4378 {
4379         int i, num;
4380         struct i40e_mac_filter *f;
4381         struct i40e_mac_filter_info *mac_filter;
4382         enum rte_mac_filter_type desired_filter;
4383         int ret = I40E_SUCCESS;
4384
4385         if (on) {
4386                 /* Filter to match MAC and VLAN */
4387                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4388         } else {
4389                 /* Filter to match only MAC */
4390                 desired_filter = RTE_MAC_PERFECT_MATCH;
4391         }
4392
4393         num = vsi->mac_num;
4394
4395         mac_filter = rte_zmalloc("mac_filter_info_data",
4396                                  num * sizeof(*mac_filter), 0);
4397         if (mac_filter == NULL) {
4398                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4399                 return I40E_ERR_NO_MEMORY;
4400         }
4401
4402         i = 0;
4403
4404         /* Remove all existing mac */
4405         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4406                 mac_filter[i] = f->mac_info;
4407                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4408                 if (ret) {
4409                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4410                                     on ? "enable" : "disable");
4411                         goto DONE;
4412                 }
4413                 i++;
4414         }
4415
4416         /* Override with new filter */
4417         for (i = 0; i < num; i++) {
4418                 mac_filter[i].filter_type = desired_filter;
4419                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4420                 if (ret) {
4421                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4422                                     on ? "enable" : "disable");
4423                         goto DONE;
4424                 }
4425         }
4426
4427 DONE:
4428         rte_free(mac_filter);
4429         return ret;
4430 }
4431
4432 /* Configure vlan stripping on or off */
4433 int
4434 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4435 {
4436         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4437         struct i40e_vsi_context ctxt;
4438         uint8_t vlan_flags;
4439         int ret = I40E_SUCCESS;
4440
4441         /* Check if it has been already on or off */
4442         if (vsi->info.valid_sections &
4443                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4444                 if (on) {
4445                         if ((vsi->info.port_vlan_flags &
4446                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4447                                 return 0; /* already on */
4448                 } else {
4449                         if ((vsi->info.port_vlan_flags &
4450                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4451                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4452                                 return 0; /* already off */
4453                 }
4454         }
4455
4456         if (on)
4457                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4458         else
4459                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4460         vsi->info.valid_sections =
4461                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4462         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4463         vsi->info.port_vlan_flags |= vlan_flags;
4464         ctxt.seid = vsi->seid;
4465         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4466         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4467         if (ret)
4468                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4469                             on ? "enable" : "disable");
4470
4471         return ret;
4472 }
4473
4474 static int
4475 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4476 {
4477         struct rte_eth_dev_data *data = dev->data;
4478         int ret;
4479         int mask = 0;
4480
4481         /* Apply vlan offload setting */
4482         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4483         i40e_vlan_offload_set(dev, mask);
4484
4485         /* Apply double-vlan setting, not implemented yet */
4486
4487         /* Apply pvid setting */
4488         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4489                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4490         if (ret)
4491                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4492
4493         return ret;
4494 }
4495
4496 static int
4497 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4498 {
4499         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4500
4501         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4502 }
4503
4504 static int
4505 i40e_update_flow_control(struct i40e_hw *hw)
4506 {
4507 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4508         struct i40e_link_status link_status;
4509         uint32_t rxfc = 0, txfc = 0, reg;
4510         uint8_t an_info;
4511         int ret;
4512
4513         memset(&link_status, 0, sizeof(link_status));
4514         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4515         if (ret != I40E_SUCCESS) {
4516                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4517                 goto write_reg; /* Disable flow control */
4518         }
4519
4520         an_info = hw->phy.link_info.an_info;
4521         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4522                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4523                 ret = I40E_ERR_NOT_READY;
4524                 goto write_reg; /* Disable flow control */
4525         }
4526         /**
4527          * If link auto negotiation is enabled, flow control needs to
4528          * be configured according to it
4529          */
4530         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4531         case I40E_LINK_PAUSE_RXTX:
4532                 rxfc = 1;
4533                 txfc = 1;
4534                 hw->fc.current_mode = I40E_FC_FULL;
4535                 break;
4536         case I40E_AQ_LINK_PAUSE_RX:
4537                 rxfc = 1;
4538                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4539                 break;
4540         case I40E_AQ_LINK_PAUSE_TX:
4541                 txfc = 1;
4542                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4543                 break;
4544         default:
4545                 hw->fc.current_mode = I40E_FC_NONE;
4546                 break;
4547         }
4548
4549 write_reg:
4550         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4551                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4552         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4553         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4554         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4555         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4556
4557         return ret;
4558 }
4559
4560 /* PF setup */
4561 static int
4562 i40e_pf_setup(struct i40e_pf *pf)
4563 {
4564         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4565         struct i40e_filter_control_settings settings;
4566         struct i40e_vsi *vsi;
4567         int ret;
4568
4569         /* Clear all stats counters */
4570         pf->offset_loaded = FALSE;
4571         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4572         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4573
4574         ret = i40e_pf_get_switch_config(pf);
4575         if (ret != I40E_SUCCESS) {
4576                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4577                 return ret;
4578         }
4579         if (pf->flags & I40E_FLAG_FDIR) {
4580                 /* make queue allocated first, let FDIR use queue pair 0*/
4581                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4582                 if (ret != I40E_FDIR_QUEUE_ID) {
4583                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4584                                     " ret =%d", ret);
4585                         pf->flags &= ~I40E_FLAG_FDIR;
4586                 }
4587         }
4588         /*  main VSI setup */
4589         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4590         if (!vsi) {
4591                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4592                 return I40E_ERR_NOT_READY;
4593         }
4594         pf->main_vsi = vsi;
4595
4596         /* Configure filter control */
4597         memset(&settings, 0, sizeof(settings));
4598         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4599                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4600         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4601                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4602         else {
4603                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4604                                                 hw->func_caps.rss_table_size);
4605                 return I40E_ERR_PARAM;
4606         }
4607         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4608                         "size: %u\n", hw->func_caps.rss_table_size);
4609         pf->hash_lut_size = hw->func_caps.rss_table_size;
4610
4611         /* Enable ethtype and macvlan filters */
4612         settings.enable_ethtype = TRUE;
4613         settings.enable_macvlan = TRUE;
4614         ret = i40e_set_filter_control(hw, &settings);
4615         if (ret)
4616                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4617                                                                 ret);
4618
4619         /* Update flow control according to the auto negotiation */
4620         i40e_update_flow_control(hw);
4621
4622         return I40E_SUCCESS;
4623 }
4624
4625 int
4626 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4627 {
4628         uint32_t reg;
4629         uint16_t j;
4630
4631         /**
4632          * Set or clear TX Queue Disable flags,
4633          * which is required by hardware.
4634          */
4635         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4636         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4637
4638         /* Wait until the request is finished */
4639         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4640                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4641                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4642                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4643                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4644                                                         & 0x1))) {
4645                         break;
4646                 }
4647         }
4648         if (on) {
4649                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4650                         return I40E_SUCCESS; /* already on, skip next steps */
4651
4652                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4653                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4654         } else {
4655                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4656                         return I40E_SUCCESS; /* already off, skip next steps */
4657                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4658         }
4659         /* Write the register */
4660         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4661         /* Check the result */
4662         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4663                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4664                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4665                 if (on) {
4666                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4667                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4668                                 break;
4669                 } else {
4670                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4671                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4672                                 break;
4673                 }
4674         }
4675         /* Check if it is timeout */
4676         if (j >= I40E_CHK_Q_ENA_COUNT) {
4677                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4678                             (on ? "enable" : "disable"), q_idx);
4679                 return I40E_ERR_TIMEOUT;
4680         }
4681
4682         return I40E_SUCCESS;
4683 }
4684
4685 /* Swith on or off the tx queues */
4686 static int
4687 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4688 {
4689         struct rte_eth_dev_data *dev_data = pf->dev_data;
4690         struct i40e_tx_queue *txq;
4691         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4692         uint16_t i;
4693         int ret;
4694
4695         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4696                 txq = dev_data->tx_queues[i];
4697                 /* Don't operate the queue if not configured or
4698                  * if starting only per queue */
4699                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4700                         continue;
4701                 if (on)
4702                         ret = i40e_dev_tx_queue_start(dev, i);
4703                 else
4704                         ret = i40e_dev_tx_queue_stop(dev, i);
4705                 if ( ret != I40E_SUCCESS)
4706                         return ret;
4707         }
4708
4709         return I40E_SUCCESS;
4710 }
4711
4712 int
4713 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4714 {
4715         uint32_t reg;
4716         uint16_t j;
4717
4718         /* Wait until the request is finished */
4719         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4720                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4721                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4722                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4723                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4724                         break;
4725         }
4726
4727         if (on) {
4728                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4729                         return I40E_SUCCESS; /* Already on, skip next steps */
4730                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4731         } else {
4732                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4733                         return I40E_SUCCESS; /* Already off, skip next steps */
4734                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4735         }
4736
4737         /* Write the register */
4738         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4739         /* Check the result */
4740         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4741                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4742                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4743                 if (on) {
4744                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4745                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4746                                 break;
4747                 } else {
4748                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4749                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4750                                 break;
4751                 }
4752         }
4753
4754         /* Check if it is timeout */
4755         if (j >= I40E_CHK_Q_ENA_COUNT) {
4756                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4757                             (on ? "enable" : "disable"), q_idx);
4758                 return I40E_ERR_TIMEOUT;
4759         }
4760
4761         return I40E_SUCCESS;
4762 }
4763 /* Switch on or off the rx queues */
4764 static int
4765 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4766 {
4767         struct rte_eth_dev_data *dev_data = pf->dev_data;
4768         struct i40e_rx_queue *rxq;
4769         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4770         uint16_t i;
4771         int ret;
4772
4773         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4774                 rxq = dev_data->rx_queues[i];
4775                 /* Don't operate the queue if not configured or
4776                  * if starting only per queue */
4777                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4778                         continue;
4779                 if (on)
4780                         ret = i40e_dev_rx_queue_start(dev, i);
4781                 else
4782                         ret = i40e_dev_rx_queue_stop(dev, i);
4783                 if (ret != I40E_SUCCESS)
4784                         return ret;
4785         }
4786
4787         return I40E_SUCCESS;
4788 }
4789
4790 /* Switch on or off all the rx/tx queues */
4791 int
4792 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4793 {
4794         int ret;
4795
4796         if (on) {
4797                 /* enable rx queues before enabling tx queues */
4798                 ret = i40e_dev_switch_rx_queues(pf, on);
4799                 if (ret) {
4800                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4801                         return ret;
4802                 }
4803                 ret = i40e_dev_switch_tx_queues(pf, on);
4804         } else {
4805                 /* Stop tx queues before stopping rx queues */
4806                 ret = i40e_dev_switch_tx_queues(pf, on);
4807                 if (ret) {
4808                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4809                         return ret;
4810                 }
4811                 ret = i40e_dev_switch_rx_queues(pf, on);
4812         }
4813
4814         return ret;
4815 }
4816
4817 /* Initialize VSI for TX */
4818 static int
4819 i40e_dev_tx_init(struct i40e_pf *pf)
4820 {
4821         struct rte_eth_dev_data *data = pf->dev_data;
4822         uint16_t i;
4823         uint32_t ret = I40E_SUCCESS;
4824         struct i40e_tx_queue *txq;
4825
4826         for (i = 0; i < data->nb_tx_queues; i++) {
4827                 txq = data->tx_queues[i];
4828                 if (!txq || !txq->q_set)
4829                         continue;
4830                 ret = i40e_tx_queue_init(txq);
4831                 if (ret != I40E_SUCCESS)
4832                         break;
4833         }
4834         if (ret == I40E_SUCCESS)
4835                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4836                                      ->eth_dev);
4837
4838         return ret;
4839 }
4840
4841 /* Initialize VSI for RX */
4842 static int
4843 i40e_dev_rx_init(struct i40e_pf *pf)
4844 {
4845         struct rte_eth_dev_data *data = pf->dev_data;
4846         int ret = I40E_SUCCESS;
4847         uint16_t i;
4848         struct i40e_rx_queue *rxq;
4849
4850         i40e_pf_config_mq_rx(pf);
4851         for (i = 0; i < data->nb_rx_queues; i++) {
4852                 rxq = data->rx_queues[i];
4853                 if (!rxq || !rxq->q_set)
4854                         continue;
4855
4856                 ret = i40e_rx_queue_init(rxq);
4857                 if (ret != I40E_SUCCESS) {
4858                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4859                                     "initialization");
4860                         break;
4861                 }
4862         }
4863         if (ret == I40E_SUCCESS)
4864                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4865                                      ->eth_dev);
4866
4867         return ret;
4868 }
4869
4870 static int
4871 i40e_dev_rxtx_init(struct i40e_pf *pf)
4872 {
4873         int err;
4874
4875         err = i40e_dev_tx_init(pf);
4876         if (err) {
4877                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4878                 return err;
4879         }
4880         err = i40e_dev_rx_init(pf);
4881         if (err) {
4882                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4883                 return err;
4884         }
4885
4886         return err;
4887 }
4888
4889 static int
4890 i40e_vmdq_setup(struct rte_eth_dev *dev)
4891 {
4892         struct rte_eth_conf *conf = &dev->data->dev_conf;
4893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4894         int i, err, conf_vsis, j, loop;
4895         struct i40e_vsi *vsi;
4896         struct i40e_vmdq_info *vmdq_info;
4897         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4898         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4899
4900         /*
4901          * Disable interrupt to avoid message from VF. Furthermore, it will
4902          * avoid race condition in VSI creation/destroy.
4903          */
4904         i40e_pf_disable_irq0(hw);
4905
4906         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4907                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4908                 return -ENOTSUP;
4909         }
4910
4911         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4912         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4913                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4914                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4915                         pf->max_nb_vmdq_vsi);
4916                 return -ENOTSUP;
4917         }
4918
4919         if (pf->vmdq != NULL) {
4920                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4921                 return 0;
4922         }
4923
4924         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4925                                 sizeof(*vmdq_info) * conf_vsis, 0);
4926
4927         if (pf->vmdq == NULL) {
4928                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4929                 return -ENOMEM;
4930         }
4931
4932         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4933
4934         /* Create VMDQ VSI */
4935         for (i = 0; i < conf_vsis; i++) {
4936                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4937                                 vmdq_conf->enable_loop_back);
4938                 if (vsi == NULL) {
4939                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4940                         err = -1;
4941                         goto err_vsi_setup;
4942                 }
4943                 vmdq_info = &pf->vmdq[i];
4944                 vmdq_info->pf = pf;
4945                 vmdq_info->vsi = vsi;
4946         }
4947         pf->nb_cfg_vmdq_vsi = conf_vsis;
4948
4949         /* Configure Vlan */
4950         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4951         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4952                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4953                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4954                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4955                                         vmdq_conf->pool_map[i].vlan_id, j);
4956
4957                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4958                                                 vmdq_conf->pool_map[i].vlan_id);
4959                                 if (err) {
4960                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4961                                         err = -1;
4962                                         goto err_vsi_setup;
4963                                 }
4964                         }
4965                 }
4966         }
4967
4968         i40e_pf_enable_irq0(hw);
4969
4970         return 0;
4971
4972 err_vsi_setup:
4973         for (i = 0; i < conf_vsis; i++)
4974                 if (pf->vmdq[i].vsi == NULL)
4975                         break;
4976                 else
4977                         i40e_vsi_release(pf->vmdq[i].vsi);
4978
4979         rte_free(pf->vmdq);
4980         pf->vmdq = NULL;
4981         i40e_pf_enable_irq0(hw);
4982         return err;
4983 }
4984
4985 static void
4986 i40e_stat_update_32(struct i40e_hw *hw,
4987                    uint32_t reg,
4988                    bool offset_loaded,
4989                    uint64_t *offset,
4990                    uint64_t *stat)
4991 {
4992         uint64_t new_data;
4993
4994         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4995         if (!offset_loaded)
4996                 *offset = new_data;
4997
4998         if (new_data >= *offset)
4999                 *stat = (uint64_t)(new_data - *offset);
5000         else
5001                 *stat = (uint64_t)((new_data +
5002                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5003 }
5004
5005 static void
5006 i40e_stat_update_48(struct i40e_hw *hw,
5007                    uint32_t hireg,
5008                    uint32_t loreg,
5009                    bool offset_loaded,
5010                    uint64_t *offset,
5011                    uint64_t *stat)
5012 {
5013         uint64_t new_data;
5014
5015         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5016         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5017                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5018
5019         if (!offset_loaded)
5020                 *offset = new_data;
5021
5022         if (new_data >= *offset)
5023                 *stat = new_data - *offset;
5024         else
5025                 *stat = (uint64_t)((new_data +
5026                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5027
5028         *stat &= I40E_48_BIT_MASK;
5029 }
5030
5031 /* Disable IRQ0 */
5032 void
5033 i40e_pf_disable_irq0(struct i40e_hw *hw)
5034 {
5035         /* Disable all interrupt types */
5036         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5037         I40E_WRITE_FLUSH(hw);
5038 }
5039
5040 /* Enable IRQ0 */
5041 void
5042 i40e_pf_enable_irq0(struct i40e_hw *hw)
5043 {
5044         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5045                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5046                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5047                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5048         I40E_WRITE_FLUSH(hw);
5049 }
5050
5051 static void
5052 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5053 {
5054         /* read pending request and disable first */
5055         i40e_pf_disable_irq0(hw);
5056         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5057         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5058                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5059
5060         if (no_queue)
5061                 /* Link no queues with irq0 */
5062                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5063                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5064 }
5065
5066 static void
5067 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5068 {
5069         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5071         int i;
5072         uint16_t abs_vf_id;
5073         uint32_t index, offset, val;
5074
5075         if (!pf->vfs)
5076                 return;
5077         /**
5078          * Try to find which VF trigger a reset, use absolute VF id to access
5079          * since the reg is global register.
5080          */
5081         for (i = 0; i < pf->vf_num; i++) {
5082                 abs_vf_id = hw->func_caps.vf_base_id + i;
5083                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5084                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5085                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5086                 /* VFR event occured */
5087                 if (val & (0x1 << offset)) {
5088                         int ret;
5089
5090                         /* Clear the event first */
5091                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5092                                                         (0x1 << offset));
5093                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5094                         /**
5095                          * Only notify a VF reset event occured,
5096                          * don't trigger another SW reset
5097                          */
5098                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5099                         if (ret != I40E_SUCCESS)
5100                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5101                 }
5102         }
5103 }
5104
5105 static void
5106 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5107 {
5108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         struct i40e_arq_event_info info;
5110         uint16_t pending, opcode;
5111         int ret;
5112
5113         info.buf_len = I40E_AQ_BUF_SZ;
5114         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5115         if (!info.msg_buf) {
5116                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5117                 return;
5118         }
5119
5120         pending = 1;
5121         while (pending) {
5122                 ret = i40e_clean_arq_element(hw, &info, &pending);
5123
5124                 if (ret != I40E_SUCCESS) {
5125                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5126                                     "aq_err: %u", hw->aq.asq_last_status);
5127                         break;
5128                 }
5129                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5130
5131                 switch (opcode) {
5132                 case i40e_aqc_opc_send_msg_to_pf:
5133                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5134                         i40e_pf_host_handle_vf_msg(dev,
5135                                         rte_le_to_cpu_16(info.desc.retval),
5136                                         rte_le_to_cpu_32(info.desc.cookie_high),
5137                                         rte_le_to_cpu_32(info.desc.cookie_low),
5138                                         info.msg_buf,
5139                                         info.msg_len);
5140                         break;
5141                 default:
5142                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5143                                     opcode);
5144                         break;
5145                 }
5146         }
5147         rte_free(info.msg_buf);
5148 }
5149
5150 /*
5151  * Interrupt handler is registered as the alarm callback for handling LSC
5152  * interrupt in a definite of time, in order to wait the NIC into a stable
5153  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5154  * no need for link down interrupt.
5155  */
5156 static void
5157 i40e_dev_interrupt_delayed_handler(void *param)
5158 {
5159         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5160         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5161         uint32_t icr0;
5162
5163         /* read interrupt causes again */
5164         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5165
5166 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5167         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5168                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5169         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5170                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5171         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5172                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5173         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5174                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5175         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5176                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5177                                                                 "state\n");
5178         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5179                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5180         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5181                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5182 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5183
5184         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5185                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5186                 i40e_dev_handle_vfr_event(dev);
5187         }
5188         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5189                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5190                 i40e_dev_handle_aq_msg(dev);
5191         }
5192
5193         /* handle the link up interrupt in an alarm callback */
5194         i40e_dev_link_update(dev, 0);
5195         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5196
5197         i40e_pf_enable_irq0(hw);
5198         rte_intr_enable(&(dev->pci_dev->intr_handle));
5199 }
5200
5201 /**
5202  * Interrupt handler triggered by NIC  for handling
5203  * specific interrupt.
5204  *
5205  * @param handle
5206  *  Pointer to interrupt handle.
5207  * @param param
5208  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5209  *
5210  * @return
5211  *  void
5212  */
5213 static void
5214 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5215                            void *param)
5216 {
5217         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5218         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5219         uint32_t icr0;
5220
5221         /* Disable interrupt */
5222         i40e_pf_disable_irq0(hw);
5223
5224         /* read out interrupt causes */
5225         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5226
5227         /* No interrupt event indicated */
5228         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5229                 PMD_DRV_LOG(INFO, "No interrupt event");
5230                 goto done;
5231         }
5232 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5233         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5234                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5235         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5236                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5237         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5238                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5239         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5240                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5241         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5242                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5243         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5244                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5245         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5246                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5247 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5248
5249         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5250                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5251                 i40e_dev_handle_vfr_event(dev);
5252         }
5253         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5254                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5255                 i40e_dev_handle_aq_msg(dev);
5256         }
5257
5258         /* Link Status Change interrupt */
5259         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5260 #define I40E_US_PER_SECOND 1000000
5261                 struct rte_eth_link link;
5262
5263                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5264                 memset(&link, 0, sizeof(link));
5265                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5266                 i40e_dev_link_update(dev, 0);
5267
5268                 /*
5269                  * For link up interrupt, it needs to wait 1 second to let the
5270                  * hardware be a stable state. Otherwise several consecutive
5271                  * interrupts can be observed.
5272                  * For link down interrupt, no need to wait.
5273                  */
5274                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5275                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5276                         return;
5277                 else
5278                         _rte_eth_dev_callback_process(dev,
5279                                 RTE_ETH_EVENT_INTR_LSC);
5280         }
5281
5282 done:
5283         /* Enable interrupt */
5284         i40e_pf_enable_irq0(hw);
5285         rte_intr_enable(&(dev->pci_dev->intr_handle));
5286 }
5287
5288 static int
5289 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5290                          struct i40e_macvlan_filter *filter,
5291                          int total)
5292 {
5293         int ele_num, ele_buff_size;
5294         int num, actual_num, i;
5295         uint16_t flags;
5296         int ret = I40E_SUCCESS;
5297         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5298         struct i40e_aqc_add_macvlan_element_data *req_list;
5299
5300         if (filter == NULL  || total == 0)
5301                 return I40E_ERR_PARAM;
5302         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5303         ele_buff_size = hw->aq.asq_buf_size;
5304
5305         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5306         if (req_list == NULL) {
5307                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5308                 return I40E_ERR_NO_MEMORY;
5309         }
5310
5311         num = 0;
5312         do {
5313                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5314                 memset(req_list, 0, ele_buff_size);
5315
5316                 for (i = 0; i < actual_num; i++) {
5317                         (void)rte_memcpy(req_list[i].mac_addr,
5318                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5319                         req_list[i].vlan_tag =
5320                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5321
5322                         switch (filter[num + i].filter_type) {
5323                         case RTE_MAC_PERFECT_MATCH:
5324                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5325                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5326                                 break;
5327                         case RTE_MACVLAN_PERFECT_MATCH:
5328                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5329                                 break;
5330                         case RTE_MAC_HASH_MATCH:
5331                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5332                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5333                                 break;
5334                         case RTE_MACVLAN_HASH_MATCH:
5335                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5336                                 break;
5337                         default:
5338                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5339                                 ret = I40E_ERR_PARAM;
5340                                 goto DONE;
5341                         }
5342
5343                         req_list[i].queue_number = 0;
5344
5345                         req_list[i].flags = rte_cpu_to_le_16(flags);
5346                 }
5347
5348                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5349                                                 actual_num, NULL);
5350                 if (ret != I40E_SUCCESS) {
5351                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5352                         goto DONE;
5353                 }
5354                 num += actual_num;
5355         } while (num < total);
5356
5357 DONE:
5358         rte_free(req_list);
5359         return ret;
5360 }
5361
5362 static int
5363 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5364                             struct i40e_macvlan_filter *filter,
5365                             int total)
5366 {
5367         int ele_num, ele_buff_size;
5368         int num, actual_num, i;
5369         uint16_t flags;
5370         int ret = I40E_SUCCESS;
5371         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5372         struct i40e_aqc_remove_macvlan_element_data *req_list;
5373
5374         if (filter == NULL  || total == 0)
5375                 return I40E_ERR_PARAM;
5376
5377         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5378         ele_buff_size = hw->aq.asq_buf_size;
5379
5380         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5381         if (req_list == NULL) {
5382                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5383                 return I40E_ERR_NO_MEMORY;
5384         }
5385
5386         num = 0;
5387         do {
5388                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5389                 memset(req_list, 0, ele_buff_size);
5390
5391                 for (i = 0; i < actual_num; i++) {
5392                         (void)rte_memcpy(req_list[i].mac_addr,
5393                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5394                         req_list[i].vlan_tag =
5395                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5396
5397                         switch (filter[num + i].filter_type) {
5398                         case RTE_MAC_PERFECT_MATCH:
5399                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5400                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5401                                 break;
5402                         case RTE_MACVLAN_PERFECT_MATCH:
5403                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5404                                 break;
5405                         case RTE_MAC_HASH_MATCH:
5406                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5407                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5408                                 break;
5409                         case RTE_MACVLAN_HASH_MATCH:
5410                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5411                                 break;
5412                         default:
5413                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5414                                 ret = I40E_ERR_PARAM;
5415                                 goto DONE;
5416                         }
5417                         req_list[i].flags = rte_cpu_to_le_16(flags);
5418                 }
5419
5420                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5421                                                 actual_num, NULL);
5422                 if (ret != I40E_SUCCESS) {
5423                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5424                         goto DONE;
5425                 }
5426                 num += actual_num;
5427         } while (num < total);
5428
5429 DONE:
5430         rte_free(req_list);
5431         return ret;
5432 }
5433
5434 /* Find out specific MAC filter */
5435 static struct i40e_mac_filter *
5436 i40e_find_mac_filter(struct i40e_vsi *vsi,
5437                          struct ether_addr *macaddr)
5438 {
5439         struct i40e_mac_filter *f;
5440
5441         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5442                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5443                         return f;
5444         }
5445
5446         return NULL;
5447 }
5448
5449 static bool
5450 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5451                          uint16_t vlan_id)
5452 {
5453         uint32_t vid_idx, vid_bit;
5454
5455         if (vlan_id > ETH_VLAN_ID_MAX)
5456                 return 0;
5457
5458         vid_idx = I40E_VFTA_IDX(vlan_id);
5459         vid_bit = I40E_VFTA_BIT(vlan_id);
5460
5461         if (vsi->vfta[vid_idx] & vid_bit)
5462                 return 1;
5463         else
5464                 return 0;
5465 }
5466
5467 static void
5468 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5469                          uint16_t vlan_id, bool on)
5470 {
5471         uint32_t vid_idx, vid_bit;
5472
5473         if (vlan_id > ETH_VLAN_ID_MAX)
5474                 return;
5475
5476         vid_idx = I40E_VFTA_IDX(vlan_id);
5477         vid_bit = I40E_VFTA_BIT(vlan_id);
5478
5479         if (on)
5480                 vsi->vfta[vid_idx] |= vid_bit;
5481         else
5482                 vsi->vfta[vid_idx] &= ~vid_bit;
5483 }
5484
5485 /**
5486  * Find all vlan options for specific mac addr,
5487  * return with actual vlan found.
5488  */
5489 static inline int
5490 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5491                            struct i40e_macvlan_filter *mv_f,
5492                            int num, struct ether_addr *addr)
5493 {
5494         int i;
5495         uint32_t j, k;
5496
5497         /**
5498          * Not to use i40e_find_vlan_filter to decrease the loop time,
5499          * although the code looks complex.
5500           */
5501         if (num < vsi->vlan_num)
5502                 return I40E_ERR_PARAM;
5503
5504         i = 0;
5505         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5506                 if (vsi->vfta[j]) {
5507                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5508                                 if (vsi->vfta[j] & (1 << k)) {
5509                                         if (i > num - 1) {
5510                                                 PMD_DRV_LOG(ERR, "vlan number "
5511                                                             "not match");
5512                                                 return I40E_ERR_PARAM;
5513                                         }
5514                                         (void)rte_memcpy(&mv_f[i].macaddr,
5515                                                         addr, ETH_ADDR_LEN);
5516                                         mv_f[i].vlan_id =
5517                                                 j * I40E_UINT32_BIT_SIZE + k;
5518                                         i++;
5519                                 }
5520                         }
5521                 }
5522         }
5523         return I40E_SUCCESS;
5524 }
5525
5526 static inline int
5527 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5528                            struct i40e_macvlan_filter *mv_f,
5529                            int num,
5530                            uint16_t vlan)
5531 {
5532         int i = 0;
5533         struct i40e_mac_filter *f;
5534
5535         if (num < vsi->mac_num)
5536                 return I40E_ERR_PARAM;
5537
5538         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5539                 if (i > num - 1) {
5540                         PMD_DRV_LOG(ERR, "buffer number not match");
5541                         return I40E_ERR_PARAM;
5542                 }
5543                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5544                                 ETH_ADDR_LEN);
5545                 mv_f[i].vlan_id = vlan;
5546                 mv_f[i].filter_type = f->mac_info.filter_type;
5547                 i++;
5548         }
5549
5550         return I40E_SUCCESS;
5551 }
5552
5553 static int
5554 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5555 {
5556         int i, num;
5557         struct i40e_mac_filter *f;
5558         struct i40e_macvlan_filter *mv_f;
5559         int ret = I40E_SUCCESS;
5560
5561         if (vsi == NULL || vsi->mac_num == 0)
5562                 return I40E_ERR_PARAM;
5563
5564         /* Case that no vlan is set */
5565         if (vsi->vlan_num == 0)
5566                 num = vsi->mac_num;
5567         else
5568                 num = vsi->mac_num * vsi->vlan_num;
5569
5570         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5571         if (mv_f == NULL) {
5572                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5573                 return I40E_ERR_NO_MEMORY;
5574         }
5575
5576         i = 0;
5577         if (vsi->vlan_num == 0) {
5578                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5579                         (void)rte_memcpy(&mv_f[i].macaddr,
5580                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5581                         mv_f[i].vlan_id = 0;
5582                         i++;
5583                 }
5584         } else {
5585                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5586                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5587                                         vsi->vlan_num, &f->mac_info.mac_addr);
5588                         if (ret != I40E_SUCCESS)
5589                                 goto DONE;
5590                         i += vsi->vlan_num;
5591                 }
5592         }
5593
5594         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5595 DONE:
5596         rte_free(mv_f);
5597
5598         return ret;
5599 }
5600
5601 int
5602 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5603 {
5604         struct i40e_macvlan_filter *mv_f;
5605         int mac_num;
5606         int ret = I40E_SUCCESS;
5607
5608         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5609                 return I40E_ERR_PARAM;
5610
5611         /* If it's already set, just return */
5612         if (i40e_find_vlan_filter(vsi,vlan))
5613                 return I40E_SUCCESS;
5614
5615         mac_num = vsi->mac_num;
5616
5617         if (mac_num == 0) {
5618                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5619                 return I40E_ERR_PARAM;
5620         }
5621
5622         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5623
5624         if (mv_f == NULL) {
5625                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5626                 return I40E_ERR_NO_MEMORY;
5627         }
5628
5629         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5630
5631         if (ret != I40E_SUCCESS)
5632                 goto DONE;
5633
5634         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5635
5636         if (ret != I40E_SUCCESS)
5637                 goto DONE;
5638
5639         i40e_set_vlan_filter(vsi, vlan, 1);
5640
5641         vsi->vlan_num++;
5642         ret = I40E_SUCCESS;
5643 DONE:
5644         rte_free(mv_f);
5645         return ret;
5646 }
5647
5648 int
5649 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5650 {
5651         struct i40e_macvlan_filter *mv_f;
5652         int mac_num;
5653         int ret = I40E_SUCCESS;
5654
5655         /**
5656          * Vlan 0 is the generic filter for untagged packets
5657          * and can't be removed.
5658          */
5659         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5660                 return I40E_ERR_PARAM;
5661
5662         /* If can't find it, just return */
5663         if (!i40e_find_vlan_filter(vsi, vlan))
5664                 return I40E_ERR_PARAM;
5665
5666         mac_num = vsi->mac_num;
5667
5668         if (mac_num == 0) {
5669                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5670                 return I40E_ERR_PARAM;
5671         }
5672
5673         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5674
5675         if (mv_f == NULL) {
5676                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5677                 return I40E_ERR_NO_MEMORY;
5678         }
5679
5680         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5681
5682         if (ret != I40E_SUCCESS)
5683                 goto DONE;
5684
5685         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5686
5687         if (ret != I40E_SUCCESS)
5688                 goto DONE;
5689
5690         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5691         if (vsi->vlan_num == 1) {
5692                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5693                 if (ret != I40E_SUCCESS)
5694                         goto DONE;
5695
5696                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5697                 if (ret != I40E_SUCCESS)
5698                         goto DONE;
5699         }
5700
5701         i40e_set_vlan_filter(vsi, vlan, 0);
5702
5703         vsi->vlan_num--;
5704         ret = I40E_SUCCESS;
5705 DONE:
5706         rte_free(mv_f);
5707         return ret;
5708 }
5709
5710 int
5711 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5712 {
5713         struct i40e_mac_filter *f;
5714         struct i40e_macvlan_filter *mv_f;
5715         int i, vlan_num = 0;
5716         int ret = I40E_SUCCESS;
5717
5718         /* If it's add and we've config it, return */
5719         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5720         if (f != NULL)
5721                 return I40E_SUCCESS;
5722         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5723                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5724
5725                 /**
5726                  * If vlan_num is 0, that's the first time to add mac,
5727                  * set mask for vlan_id 0.
5728                  */
5729                 if (vsi->vlan_num == 0) {
5730                         i40e_set_vlan_filter(vsi, 0, 1);
5731                         vsi->vlan_num = 1;
5732                 }
5733                 vlan_num = vsi->vlan_num;
5734         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5735                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5736                 vlan_num = 1;
5737
5738         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5739         if (mv_f == NULL) {
5740                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5741                 return I40E_ERR_NO_MEMORY;
5742         }
5743
5744         for (i = 0; i < vlan_num; i++) {
5745                 mv_f[i].filter_type = mac_filter->filter_type;
5746                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5747                                 ETH_ADDR_LEN);
5748         }
5749
5750         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5751                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5752                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5753                                         &mac_filter->mac_addr);
5754                 if (ret != I40E_SUCCESS)
5755                         goto DONE;
5756         }
5757
5758         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5759         if (ret != I40E_SUCCESS)
5760                 goto DONE;
5761
5762         /* Add the mac addr into mac list */
5763         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5764         if (f == NULL) {
5765                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5766                 ret = I40E_ERR_NO_MEMORY;
5767                 goto DONE;
5768         }
5769         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5770                         ETH_ADDR_LEN);
5771         f->mac_info.filter_type = mac_filter->filter_type;
5772         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5773         vsi->mac_num++;
5774
5775         ret = I40E_SUCCESS;
5776 DONE:
5777         rte_free(mv_f);
5778
5779         return ret;
5780 }
5781
5782 int
5783 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5784 {
5785         struct i40e_mac_filter *f;
5786         struct i40e_macvlan_filter *mv_f;
5787         int i, vlan_num;
5788         enum rte_mac_filter_type filter_type;
5789         int ret = I40E_SUCCESS;
5790
5791         /* Can't find it, return an error */
5792         f = i40e_find_mac_filter(vsi, addr);
5793         if (f == NULL)
5794                 return I40E_ERR_PARAM;
5795
5796         vlan_num = vsi->vlan_num;
5797         filter_type = f->mac_info.filter_type;
5798         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5799                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5800                 if (vlan_num == 0) {
5801                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5802                         return I40E_ERR_PARAM;
5803                 }
5804         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5805                         filter_type == RTE_MAC_HASH_MATCH)
5806                 vlan_num = 1;
5807
5808         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5809         if (mv_f == NULL) {
5810                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5811                 return I40E_ERR_NO_MEMORY;
5812         }
5813
5814         for (i = 0; i < vlan_num; i++) {
5815                 mv_f[i].filter_type = filter_type;
5816                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5817                                 ETH_ADDR_LEN);
5818         }
5819         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5820                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5821                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5822                 if (ret != I40E_SUCCESS)
5823                         goto DONE;
5824         }
5825
5826         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5827         if (ret != I40E_SUCCESS)
5828                 goto DONE;
5829
5830         /* Remove the mac addr into mac list */
5831         TAILQ_REMOVE(&vsi->mac_list, f, next);
5832         rte_free(f);
5833         vsi->mac_num--;
5834
5835         ret = I40E_SUCCESS;
5836 DONE:
5837         rte_free(mv_f);
5838         return ret;
5839 }
5840
5841 /* Configure hash enable flags for RSS */
5842 uint64_t
5843 i40e_config_hena(uint64_t flags)
5844 {
5845         uint64_t hena = 0;
5846
5847         if (!flags)
5848                 return hena;
5849
5850         if (flags & ETH_RSS_FRAG_IPV4)
5851                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5852         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5853                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5854         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5855                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5856         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5857                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5858         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5859                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5860         if (flags & ETH_RSS_FRAG_IPV6)
5861                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5862         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5863                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5864         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5865                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5866         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5867                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5868         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5869                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5870         if (flags & ETH_RSS_L2_PAYLOAD)
5871                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5872
5873         return hena;
5874 }
5875
5876 /* Parse the hash enable flags */
5877 uint64_t
5878 i40e_parse_hena(uint64_t flags)
5879 {
5880         uint64_t rss_hf = 0;
5881
5882         if (!flags)
5883                 return rss_hf;
5884         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5885                 rss_hf |= ETH_RSS_FRAG_IPV4;
5886         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5887                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5888         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5889                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5890         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5891                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5892         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5893                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5894         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5895                 rss_hf |= ETH_RSS_FRAG_IPV6;
5896         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5897                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5898         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5899                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5900         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5901                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5902         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5903                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5904         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5905                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5906
5907         return rss_hf;
5908 }
5909
5910 /* Disable RSS */
5911 static void
5912 i40e_pf_disable_rss(struct i40e_pf *pf)
5913 {
5914         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5915         uint64_t hena;
5916
5917         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5918         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5919         hena &= ~I40E_RSS_HENA_ALL;
5920         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5921         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5922         I40E_WRITE_FLUSH(hw);
5923 }
5924
5925 static int
5926 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5927 {
5928         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5929         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5930         int ret = 0;
5931
5932         if (!key || key_len == 0) {
5933                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5934                 return 0;
5935         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5936                 sizeof(uint32_t)) {
5937                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5938                 return -EINVAL;
5939         }
5940
5941         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5942                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5943                         (struct i40e_aqc_get_set_rss_key_data *)key;
5944
5945                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5946                 if (ret)
5947                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5948                                      "via AQ");
5949         } else {
5950                 uint32_t *hash_key = (uint32_t *)key;
5951                 uint16_t i;
5952
5953                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5954                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5955                 I40E_WRITE_FLUSH(hw);
5956         }
5957
5958         return ret;
5959 }
5960
5961 static int
5962 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5963 {
5964         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5965         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5966         int ret;
5967
5968         if (!key || !key_len)
5969                 return -EINVAL;
5970
5971         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5972                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5973                         (struct i40e_aqc_get_set_rss_key_data *)key);
5974                 if (ret) {
5975                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5976                         return ret;
5977                 }
5978         } else {
5979                 uint32_t *key_dw = (uint32_t *)key;
5980                 uint16_t i;
5981
5982                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5983                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5984         }
5985         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5986
5987         return 0;
5988 }
5989
5990 static int
5991 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5992 {
5993         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5994         uint64_t rss_hf;
5995         uint64_t hena;
5996         int ret;
5997
5998         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5999                                rss_conf->rss_key_len);
6000         if (ret)
6001                 return ret;
6002
6003         rss_hf = rss_conf->rss_hf;
6004         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6005         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6006         hena &= ~I40E_RSS_HENA_ALL;
6007         hena |= i40e_config_hena(rss_hf);
6008         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6009         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6010         I40E_WRITE_FLUSH(hw);
6011
6012         return 0;
6013 }
6014
6015 static int
6016 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6017                          struct rte_eth_rss_conf *rss_conf)
6018 {
6019         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6020         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6021         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6022         uint64_t hena;
6023
6024         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6025         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6026         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6027                 if (rss_hf != 0) /* Enable RSS */
6028                         return -EINVAL;
6029                 return 0; /* Nothing to do */
6030         }
6031         /* RSS enabled */
6032         if (rss_hf == 0) /* Disable RSS */
6033                 return -EINVAL;
6034
6035         return i40e_hw_rss_hash_set(pf, rss_conf);
6036 }
6037
6038 static int
6039 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6040                            struct rte_eth_rss_conf *rss_conf)
6041 {
6042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6044         uint64_t hena;
6045
6046         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6047                          &rss_conf->rss_key_len);
6048
6049         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6050         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6051         rss_conf->rss_hf = i40e_parse_hena(hena);
6052
6053         return 0;
6054 }
6055
6056 static int
6057 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6058 {
6059         switch (filter_type) {
6060         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6061                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6062                 break;
6063         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6064                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6065                 break;
6066         case RTE_TUNNEL_FILTER_IMAC_TENID:
6067                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6068                 break;
6069         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6070                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6071                 break;
6072         case ETH_TUNNEL_FILTER_IMAC:
6073                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6074                 break;
6075         case ETH_TUNNEL_FILTER_OIP:
6076                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6077                 break;
6078         case ETH_TUNNEL_FILTER_IIP:
6079                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6080                 break;
6081         default:
6082                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6083                 return -EINVAL;
6084         }
6085
6086         return 0;
6087 }
6088
6089 static int
6090 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6091                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6092                         uint8_t add)
6093 {
6094         uint16_t ip_type;
6095         uint32_t ipv4_addr;
6096         uint8_t i, tun_type = 0;
6097         /* internal varialbe to convert ipv6 byte order */
6098         uint32_t convert_ipv6[4];
6099         int val, ret = 0;
6100         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6101         struct i40e_vsi *vsi = pf->main_vsi;
6102         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6103         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6104
6105         cld_filter = rte_zmalloc("tunnel_filter",
6106                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6107                 0);
6108
6109         if (NULL == cld_filter) {
6110                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6111                 return -EINVAL;
6112         }
6113         pfilter = cld_filter;
6114
6115         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6116         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6117
6118         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6119         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6120                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6121                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6122                 rte_memcpy(&pfilter->ipaddr.v4.data,
6123                                 &rte_cpu_to_le_32(ipv4_addr),
6124                                 sizeof(pfilter->ipaddr.v4.data));
6125         } else {
6126                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6127                 for (i = 0; i < 4; i++) {
6128                         convert_ipv6[i] =
6129                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6130                 }
6131                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6132                                 sizeof(pfilter->ipaddr.v6.data));
6133         }
6134
6135         /* check tunneled type */
6136         switch (tunnel_filter->tunnel_type) {
6137         case RTE_TUNNEL_TYPE_VXLAN:
6138                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6139                 break;
6140         case RTE_TUNNEL_TYPE_NVGRE:
6141                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6142                 break;
6143         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6144                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6145                 break;
6146         default:
6147                 /* Other tunnel types is not supported. */
6148                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6149                 rte_free(cld_filter);
6150                 return -EINVAL;
6151         }
6152
6153         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6154                                                 &pfilter->flags);
6155         if (val < 0) {
6156                 rte_free(cld_filter);
6157                 return -EINVAL;
6158         }
6159
6160         pfilter->flags |= rte_cpu_to_le_16(
6161                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6162                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6163         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6164         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6165
6166         if (add)
6167                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6168         else
6169                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6170                                                 cld_filter, 1);
6171
6172         rte_free(cld_filter);
6173         return ret;
6174 }
6175
6176 static int
6177 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6178 {
6179         uint8_t i;
6180
6181         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6182                 if (pf->vxlan_ports[i] == port)
6183                         return i;
6184         }
6185
6186         return -1;
6187 }
6188
6189 static int
6190 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6191 {
6192         int  idx, ret;
6193         uint8_t filter_idx;
6194         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6195
6196         idx = i40e_get_vxlan_port_idx(pf, port);
6197
6198         /* Check if port already exists */
6199         if (idx >= 0) {
6200                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6201                 return -EINVAL;
6202         }
6203
6204         /* Now check if there is space to add the new port */
6205         idx = i40e_get_vxlan_port_idx(pf, 0);
6206         if (idx < 0) {
6207                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6208                         "not adding port %d", port);
6209                 return -ENOSPC;
6210         }
6211
6212         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6213                                         &filter_idx, NULL);
6214         if (ret < 0) {
6215                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6216                 return -1;
6217         }
6218
6219         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6220                          port,  filter_idx);
6221
6222         /* New port: add it and mark its index in the bitmap */
6223         pf->vxlan_ports[idx] = port;
6224         pf->vxlan_bitmap |= (1 << idx);
6225
6226         if (!(pf->flags & I40E_FLAG_VXLAN))
6227                 pf->flags |= I40E_FLAG_VXLAN;
6228
6229         return 0;
6230 }
6231
6232 static int
6233 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6234 {
6235         int idx;
6236         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6237
6238         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6239                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6240                 return -EINVAL;
6241         }
6242
6243         idx = i40e_get_vxlan_port_idx(pf, port);
6244
6245         if (idx < 0) {
6246                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6247                 return -EINVAL;
6248         }
6249
6250         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6251                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6252                 return -1;
6253         }
6254
6255         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6256                         port, idx);
6257
6258         pf->vxlan_ports[idx] = 0;
6259         pf->vxlan_bitmap &= ~(1 << idx);
6260
6261         if (!pf->vxlan_bitmap)
6262                 pf->flags &= ~I40E_FLAG_VXLAN;
6263
6264         return 0;
6265 }
6266
6267 /* Add UDP tunneling port */
6268 static int
6269 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6270                              struct rte_eth_udp_tunnel *udp_tunnel)
6271 {
6272         int ret = 0;
6273         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6274
6275         if (udp_tunnel == NULL)
6276                 return -EINVAL;
6277
6278         switch (udp_tunnel->prot_type) {
6279         case RTE_TUNNEL_TYPE_VXLAN:
6280                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6281                 break;
6282
6283         case RTE_TUNNEL_TYPE_GENEVE:
6284         case RTE_TUNNEL_TYPE_TEREDO:
6285                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6286                 ret = -1;
6287                 break;
6288
6289         default:
6290                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6291                 ret = -1;
6292                 break;
6293         }
6294
6295         return ret;
6296 }
6297
6298 /* Remove UDP tunneling port */
6299 static int
6300 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6301                              struct rte_eth_udp_tunnel *udp_tunnel)
6302 {
6303         int ret = 0;
6304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6305
6306         if (udp_tunnel == NULL)
6307                 return -EINVAL;
6308
6309         switch (udp_tunnel->prot_type) {
6310         case RTE_TUNNEL_TYPE_VXLAN:
6311                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6312                 break;
6313         case RTE_TUNNEL_TYPE_GENEVE:
6314         case RTE_TUNNEL_TYPE_TEREDO:
6315                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6316                 ret = -1;
6317                 break;
6318         default:
6319                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6320                 ret = -1;
6321                 break;
6322         }
6323
6324         return ret;
6325 }
6326
6327 /* Calculate the maximum number of contiguous PF queues that are configured */
6328 static int
6329 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6330 {
6331         struct rte_eth_dev_data *data = pf->dev_data;
6332         int i, num;
6333         struct i40e_rx_queue *rxq;
6334
6335         num = 0;
6336         for (i = 0; i < pf->lan_nb_qps; i++) {
6337                 rxq = data->rx_queues[i];
6338                 if (rxq && rxq->q_set)
6339                         num++;
6340                 else
6341                         break;
6342         }
6343
6344         return num;
6345 }
6346
6347 /* Configure RSS */
6348 static int
6349 i40e_pf_config_rss(struct i40e_pf *pf)
6350 {
6351         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6352         struct rte_eth_rss_conf rss_conf;
6353         uint32_t i, lut = 0;
6354         uint16_t j, num;
6355
6356         /*
6357          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6358          * It's necessary to calulate the actual PF queues that are configured.
6359          */
6360         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6361                 num = i40e_pf_calc_configured_queues_num(pf);
6362         else
6363                 num = pf->dev_data->nb_rx_queues;
6364
6365         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6366         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6367                         num);
6368
6369         if (num == 0) {
6370                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6371                 return -ENOTSUP;
6372         }
6373
6374         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6375                 if (j == num)
6376                         j = 0;
6377                 lut = (lut << 8) | (j & ((0x1 <<
6378                         hw->func_caps.rss_table_entry_width) - 1));
6379                 if ((i & 3) == 3)
6380                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6381         }
6382
6383         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6384         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6385                 i40e_pf_disable_rss(pf);
6386                 return 0;
6387         }
6388         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6389                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6390                 /* Random default keys */
6391                 static uint32_t rss_key_default[] = {0x6b793944,
6392                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6393                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6394                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6395
6396                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6397                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6398                                                         sizeof(uint32_t);
6399         }
6400
6401         return i40e_hw_rss_hash_set(pf, &rss_conf);
6402 }
6403
6404 static int
6405 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6406                                struct rte_eth_tunnel_filter_conf *filter)
6407 {
6408         if (pf == NULL || filter == NULL) {
6409                 PMD_DRV_LOG(ERR, "Invalid parameter");
6410                 return -EINVAL;
6411         }
6412
6413         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6414                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6415                 return -EINVAL;
6416         }
6417
6418         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6419                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6420                 return -EINVAL;
6421         }
6422
6423         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6424                 (is_zero_ether_addr(&filter->outer_mac))) {
6425                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6426                 return -EINVAL;
6427         }
6428
6429         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6430                 (is_zero_ether_addr(&filter->inner_mac))) {
6431                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6432                 return -EINVAL;
6433         }
6434
6435         return 0;
6436 }
6437
6438 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6439 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6440 static int
6441 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6442 {
6443         uint32_t val, reg;
6444         int ret = -EINVAL;
6445
6446         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6447         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6448
6449         if (len == 3) {
6450                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6451         } else if (len == 4) {
6452                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6453         } else {
6454                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6455                 return ret;
6456         }
6457
6458         if (reg != val) {
6459                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6460                                                    reg, NULL);
6461                 if (ret != 0)
6462                         return ret;
6463         } else {
6464                 ret = 0;
6465         }
6466         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6467                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6468
6469         return ret;
6470 }
6471
6472 static int
6473 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6474 {
6475         int ret = -EINVAL;
6476
6477         if (!hw || !cfg)
6478                 return -EINVAL;
6479
6480         switch (cfg->cfg_type) {
6481         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6482                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6483                 break;
6484         default:
6485                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6486                 break;
6487         }
6488
6489         return ret;
6490 }
6491
6492 static int
6493 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6494                                enum rte_filter_op filter_op,
6495                                void *arg)
6496 {
6497         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6498         int ret = I40E_ERR_PARAM;
6499
6500         switch (filter_op) {
6501         case RTE_ETH_FILTER_SET:
6502                 ret = i40e_dev_global_config_set(hw,
6503                         (struct rte_eth_global_cfg *)arg);
6504                 break;
6505         default:
6506                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6507                 break;
6508         }
6509
6510         return ret;
6511 }
6512
6513 static int
6514 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6515                           enum rte_filter_op filter_op,
6516                           void *arg)
6517 {
6518         struct rte_eth_tunnel_filter_conf *filter;
6519         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6520         int ret = I40E_SUCCESS;
6521
6522         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6523
6524         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6525                 return I40E_ERR_PARAM;
6526
6527         switch (filter_op) {
6528         case RTE_ETH_FILTER_NOP:
6529                 if (!(pf->flags & I40E_FLAG_VXLAN))
6530                         ret = I40E_NOT_SUPPORTED;
6531                 break;
6532         case RTE_ETH_FILTER_ADD:
6533                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6534                 break;
6535         case RTE_ETH_FILTER_DELETE:
6536                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6537                 break;
6538         default:
6539                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6540                 ret = I40E_ERR_PARAM;
6541                 break;
6542         }
6543
6544         return ret;
6545 }
6546
6547 static int
6548 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6549 {
6550         int ret = 0;
6551         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6552
6553         /* RSS setup */
6554         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6555                 ret = i40e_pf_config_rss(pf);
6556         else
6557                 i40e_pf_disable_rss(pf);
6558
6559         return ret;
6560 }
6561
6562 /* Get the symmetric hash enable configurations per port */
6563 static void
6564 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6565 {
6566         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6567
6568         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6569 }
6570
6571 /* Set the symmetric hash enable configurations per port */
6572 static void
6573 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6574 {
6575         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6576
6577         if (enable > 0) {
6578                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6579                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6580                                                         "been enabled");
6581                         return;
6582                 }
6583                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6584         } else {
6585                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6586                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6587                                                         "been disabled");
6588                         return;
6589                 }
6590                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6591         }
6592         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6593         I40E_WRITE_FLUSH(hw);
6594 }
6595
6596 /*
6597  * Get global configurations of hash function type and symmetric hash enable
6598  * per flow type (pctype). Note that global configuration means it affects all
6599  * the ports on the same NIC.
6600  */
6601 static int
6602 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6603                                    struct rte_eth_hash_global_conf *g_cfg)
6604 {
6605         uint32_t reg, mask = I40E_FLOW_TYPES;
6606         uint16_t i;
6607         enum i40e_filter_pctype pctype;
6608
6609         memset(g_cfg, 0, sizeof(*g_cfg));
6610         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6611         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6612                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6613         else
6614                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6615         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6616                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6617
6618         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6619                 if (!(mask & (1UL << i)))
6620                         continue;
6621                 mask &= ~(1UL << i);
6622                 /* Bit set indicats the coresponding flow type is supported */
6623                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6624                 pctype = i40e_flowtype_to_pctype(i);
6625                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6626                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6627                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6628         }
6629
6630         return 0;
6631 }
6632
6633 static int
6634 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6635 {
6636         uint32_t i;
6637         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6638
6639         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6640                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6641                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6642                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6643                                                 g_cfg->hash_func);
6644                 return -EINVAL;
6645         }
6646
6647         /*
6648          * As i40e supports less than 32 flow types, only first 32 bits need to
6649          * be checked.
6650          */
6651         mask0 = g_cfg->valid_bit_mask[0];
6652         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6653                 if (i == 0) {
6654                         /* Check if any unsupported flow type configured */
6655                         if ((mask0 | i40e_mask) ^ i40e_mask)
6656                                 goto mask_err;
6657                 } else {
6658                         if (g_cfg->valid_bit_mask[i])
6659                                 goto mask_err;
6660                 }
6661         }
6662
6663         return 0;
6664
6665 mask_err:
6666         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6667
6668         return -EINVAL;
6669 }
6670
6671 /*
6672  * Set global configurations of hash function type and symmetric hash enable
6673  * per flow type (pctype). Note any modifying global configuration will affect
6674  * all the ports on the same NIC.
6675  */
6676 static int
6677 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6678                                    struct rte_eth_hash_global_conf *g_cfg)
6679 {
6680         int ret;
6681         uint16_t i;
6682         uint32_t reg;
6683         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6684         enum i40e_filter_pctype pctype;
6685
6686         /* Check the input parameters */
6687         ret = i40e_hash_global_config_check(g_cfg);
6688         if (ret < 0)
6689                 return ret;
6690
6691         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6692                 if (!(mask0 & (1UL << i)))
6693                         continue;
6694                 mask0 &= ~(1UL << i);
6695                 pctype = i40e_flowtype_to_pctype(i);
6696                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6697                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6698                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6699         }
6700
6701         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6702         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6703                 /* Toeplitz */
6704                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6705                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6706                                                                 "Toeplitz");
6707                         goto out;
6708                 }
6709                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6710         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6711                 /* Simple XOR */
6712                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6713                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6714                                                         "Simple XOR");
6715                         goto out;
6716                 }
6717                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6718         } else
6719                 /* Use the default, and keep it as it is */
6720                 goto out;
6721
6722         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6723
6724 out:
6725         I40E_WRITE_FLUSH(hw);
6726
6727         return 0;
6728 }
6729
6730 /**
6731  * Valid input sets for hash and flow director filters per PCTYPE
6732  */
6733 static uint64_t
6734 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6735                 enum rte_filter_type filter)
6736 {
6737         uint64_t valid;
6738
6739         static const uint64_t valid_hash_inset_table[] = {
6740                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6741                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6742                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6743                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6744                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6745                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6746                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6747                         I40E_INSET_FLEX_PAYLOAD,
6748                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6749                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6750                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6751                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6752                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6753                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6754                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6756                         I40E_INSET_FLEX_PAYLOAD,
6757                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6758                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6759                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6760                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6761                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6762                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6763                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6764                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6765                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6766                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6767                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6768                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6769                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6770                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6771                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6772                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6773                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6774                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6775                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6776                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6777                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6778                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6779                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6780                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6781                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6782                         I40E_INSET_FLEX_PAYLOAD,
6783                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6784                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6785                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6786                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6787                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6788                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6789                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6790                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6791                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6792                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6793                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6794                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6795                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6796                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6797                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6798                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6799                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6800                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6801                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6802                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6803                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6804                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6805                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6806                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6807                         I40E_INSET_FLEX_PAYLOAD,
6808                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6809                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6810                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6811                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6812                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6813                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6814                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6815                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6816                         I40E_INSET_FLEX_PAYLOAD,
6817                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6818                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6819                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6820                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6821                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6822                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6823                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6824                         I40E_INSET_FLEX_PAYLOAD,
6825                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6826                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6827                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6828                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6829                         I40E_INSET_FLEX_PAYLOAD,
6830         };
6831
6832         /**
6833          * Flow director supports only fields defined in
6834          * union rte_eth_fdir_flow.
6835          */
6836         static const uint64_t valid_fdir_inset_table[] = {
6837                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6838                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6839                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6840                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6841                 I40E_INSET_IPV4_TTL,
6842                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6843                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6844                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6845                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6846                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6847                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6848                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6849                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6850                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6851                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6852                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6853                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6854                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6855                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6856                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6857                 I40E_INSET_SCTP_VT,
6858                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6859                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6860                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6861                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6862                 I40E_INSET_IPV4_TTL,
6863                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6864                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6865                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6866                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6867                 I40E_INSET_IPV6_HOP_LIMIT,
6868                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6869                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6870                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6871                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6872                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6873                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6874                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6875                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6876                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6877                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6878                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6879                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6880                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6881                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6882                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6883                 I40E_INSET_SCTP_VT,
6884                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6885                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6886                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6887                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6888                 I40E_INSET_IPV6_HOP_LIMIT,
6889                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6890                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6891                 I40E_INSET_LAST_ETHER_TYPE,
6892         };
6893
6894         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6895                 return 0;
6896         if (filter == RTE_ETH_FILTER_HASH)
6897                 valid = valid_hash_inset_table[pctype];
6898         else
6899                 valid = valid_fdir_inset_table[pctype];
6900
6901         return valid;
6902 }
6903
6904 /**
6905  * Validate if the input set is allowed for a specific PCTYPE
6906  */
6907 static int
6908 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6909                 enum rte_filter_type filter, uint64_t inset)
6910 {
6911         uint64_t valid;
6912
6913         valid = i40e_get_valid_input_set(pctype, filter);
6914         if (inset & (~valid))
6915                 return -EINVAL;
6916
6917         return 0;
6918 }
6919
6920 /* default input set fields combination per pctype */
6921 static uint64_t
6922 i40e_get_default_input_set(uint16_t pctype)
6923 {
6924         static const uint64_t default_inset_table[] = {
6925                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6926                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6927                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6928                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6929                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6930                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6931                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6932                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6933                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6934                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6935                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6936                         I40E_INSET_SCTP_VT,
6937                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6938                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6939                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6940                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6941                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6942                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6943                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6944                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6945                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6946                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6947                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6948                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6949                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6950                         I40E_INSET_SCTP_VT,
6951                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6952                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6953                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6954                         I40E_INSET_LAST_ETHER_TYPE,
6955         };
6956
6957         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6958                 return 0;
6959
6960         return default_inset_table[pctype];
6961 }
6962
6963 /**
6964  * Parse the input set from index to logical bit masks
6965  */
6966 static int
6967 i40e_parse_input_set(uint64_t *inset,
6968                      enum i40e_filter_pctype pctype,
6969                      enum rte_eth_input_set_field *field,
6970                      uint16_t size)
6971 {
6972         uint16_t i, j;
6973         int ret = -EINVAL;
6974
6975         static const struct {
6976                 enum rte_eth_input_set_field field;
6977                 uint64_t inset;
6978         } inset_convert_table[] = {
6979                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6980                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6981                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6982                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6983                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6984                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6985                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6986                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6987                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6988                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6989                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
6990                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6991                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6992                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6993                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6994                         I40E_INSET_IPV6_NEXT_HDR},
6995                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
6996                         I40E_INSET_IPV6_HOP_LIMIT},
6997                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6998                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6999                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7000                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7001                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7002                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7003                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7004                         I40E_INSET_SCTP_VT},
7005                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7006                         I40E_INSET_TUNNEL_DMAC},
7007                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7008                         I40E_INSET_VLAN_TUNNEL},
7009                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7010                         I40E_INSET_TUNNEL_ID},
7011                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7012                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7013                         I40E_INSET_FLEX_PAYLOAD_W1},
7014                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7015                         I40E_INSET_FLEX_PAYLOAD_W2},
7016                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7017                         I40E_INSET_FLEX_PAYLOAD_W3},
7018                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7019                         I40E_INSET_FLEX_PAYLOAD_W4},
7020                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7021                         I40E_INSET_FLEX_PAYLOAD_W5},
7022                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7023                         I40E_INSET_FLEX_PAYLOAD_W6},
7024                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7025                         I40E_INSET_FLEX_PAYLOAD_W7},
7026                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7027                         I40E_INSET_FLEX_PAYLOAD_W8},
7028         };
7029
7030         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7031                 return ret;
7032
7033         /* Only one item allowed for default or all */
7034         if (size == 1) {
7035                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7036                         *inset = i40e_get_default_input_set(pctype);
7037                         return 0;
7038                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7039                         *inset = I40E_INSET_NONE;
7040                         return 0;
7041                 }
7042         }
7043
7044         for (i = 0, *inset = 0; i < size; i++) {
7045                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7046                         if (field[i] == inset_convert_table[j].field) {
7047                                 *inset |= inset_convert_table[j].inset;
7048                                 break;
7049                         }
7050                 }
7051
7052                 /* It contains unsupported input set, return immediately */
7053                 if (j == RTE_DIM(inset_convert_table))
7054                         return ret;
7055         }
7056
7057         return 0;
7058 }
7059
7060 /**
7061  * Translate the input set from bit masks to register aware bit masks
7062  * and vice versa
7063  */
7064 static uint64_t
7065 i40e_translate_input_set_reg(uint64_t input)
7066 {
7067         uint64_t val = 0;
7068         uint16_t i;
7069
7070         static const struct {
7071                 uint64_t inset;
7072                 uint64_t inset_reg;
7073         } inset_map[] = {
7074                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7075                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7076                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7077                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7078                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7079                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7080                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7081                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7082                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7083                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7084                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7085                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7086                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7087                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7088                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7089                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7090                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7091                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7092                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7093                 {I40E_INSET_TUNNEL_DMAC,
7094                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7095                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7096                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7097                 {I40E_INSET_TUNNEL_SRC_PORT,
7098                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7099                 {I40E_INSET_TUNNEL_DST_PORT,
7100                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7101                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7102                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7103                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7104                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7105                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7106                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7107                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7108                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7109                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7110         };
7111
7112         if (input == 0)
7113                 return val;
7114
7115         /* Translate input set to register aware inset */
7116         for (i = 0; i < RTE_DIM(inset_map); i++) {
7117                 if (input & inset_map[i].inset)
7118                         val |= inset_map[i].inset_reg;
7119         }
7120
7121         return val;
7122 }
7123
7124 static int
7125 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7126 {
7127         uint8_t i, idx = 0;
7128         uint64_t inset_need_mask = inset;
7129
7130         static const struct {
7131                 uint64_t inset;
7132                 uint32_t mask;
7133         } inset_mask_map[] = {
7134                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7135                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7136                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7137                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7138                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7139                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7140                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7141                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7142         };
7143
7144         if (!inset || !mask || !nb_elem)
7145                 return 0;
7146
7147         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7148                 /* Clear the inset bit, if no MASK is required,
7149                  * for example proto + ttl
7150                  */
7151                 if ((inset & inset_mask_map[i].inset) ==
7152                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7153                         inset_need_mask &= ~inset_mask_map[i].inset;
7154                 if (!inset_need_mask)
7155                         return 0;
7156         }
7157         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7158                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7159                     inset_mask_map[i].inset) {
7160                         if (idx >= nb_elem) {
7161                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7162                                 return -EINVAL;
7163                         }
7164                         mask[idx] = inset_mask_map[i].mask;
7165                         idx++;
7166                 }
7167         }
7168
7169         return idx;
7170 }
7171
7172 static void
7173 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7174 {
7175         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7176
7177         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7178         if (reg != val)
7179                 i40e_write_rx_ctl(hw, addr, val);
7180         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7181                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7182 }
7183
7184 static void
7185 i40e_filter_input_set_init(struct i40e_pf *pf)
7186 {
7187         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7188         enum i40e_filter_pctype pctype;
7189         uint64_t input_set, inset_reg;
7190         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7191         int num, i;
7192
7193         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7194              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7195                 if (!I40E_VALID_PCTYPE(pctype))
7196                         continue;
7197                 input_set = i40e_get_default_input_set(pctype);
7198
7199                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7200                                                    I40E_INSET_MASK_NUM_REG);
7201                 if (num < 0)
7202                         return;
7203                 inset_reg = i40e_translate_input_set_reg(input_set);
7204
7205                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7206                                       (uint32_t)(inset_reg & UINT32_MAX));
7207                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7208                                      (uint32_t)((inset_reg >>
7209                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7210                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7211                                       (uint32_t)(inset_reg & UINT32_MAX));
7212                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7213                                      (uint32_t)((inset_reg >>
7214                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7215
7216                 for (i = 0; i < num; i++) {
7217                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7218                                              mask_reg[i]);
7219                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7220                                              mask_reg[i]);
7221                 }
7222                 /*clear unused mask registers of the pctype */
7223                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7224                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7225                                              0);
7226                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7227                                              0);
7228                 }
7229                 I40E_WRITE_FLUSH(hw);
7230
7231                 /* store the default input set */
7232                 pf->hash_input_set[pctype] = input_set;
7233                 pf->fdir.input_set[pctype] = input_set;
7234         }
7235 }
7236
7237 int
7238 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7239                          struct rte_eth_input_set_conf *conf)
7240 {
7241         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7242         enum i40e_filter_pctype pctype;
7243         uint64_t input_set, inset_reg = 0;
7244         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7245         int ret, i, num;
7246
7247         if (!conf) {
7248                 PMD_DRV_LOG(ERR, "Invalid pointer");
7249                 return -EFAULT;
7250         }
7251         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7252             conf->op != RTE_ETH_INPUT_SET_ADD) {
7253                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7254                 return -EINVAL;
7255         }
7256
7257         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7258         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7259                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7260                             conf->flow_type);
7261                 return -EINVAL;
7262         }
7263
7264         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7265                                    conf->inset_size);
7266         if (ret) {
7267                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7268                 return -EINVAL;
7269         }
7270         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7271                                     input_set) != 0) {
7272                 PMD_DRV_LOG(ERR, "Invalid input set");
7273                 return -EINVAL;
7274         }
7275         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7276                 /* get inset value in register */
7277                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7278                 inset_reg <<= I40E_32_BIT_WIDTH;
7279                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7280                 input_set |= pf->hash_input_set[pctype];
7281         }
7282         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7283                                            I40E_INSET_MASK_NUM_REG);
7284         if (num < 0)
7285                 return -EINVAL;
7286
7287         inset_reg |= i40e_translate_input_set_reg(input_set);
7288
7289         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7290                               (uint32_t)(inset_reg & UINT32_MAX));
7291         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7292                              (uint32_t)((inset_reg >>
7293                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7294
7295         for (i = 0; i < num; i++)
7296                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7297                                      mask_reg[i]);
7298         /*clear unused mask registers of the pctype */
7299         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7300                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7301                                      0);
7302         I40E_WRITE_FLUSH(hw);
7303
7304         pf->hash_input_set[pctype] = input_set;
7305         return 0;
7306 }
7307
7308 int
7309 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7310                          struct rte_eth_input_set_conf *conf)
7311 {
7312         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7313         enum i40e_filter_pctype pctype;
7314         uint64_t input_set, inset_reg = 0;
7315         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7316         int ret, i, num;
7317
7318         if (!hw || !conf) {
7319                 PMD_DRV_LOG(ERR, "Invalid pointer");
7320                 return -EFAULT;
7321         }
7322         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7323             conf->op != RTE_ETH_INPUT_SET_ADD) {
7324                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7325                 return -EINVAL;
7326         }
7327
7328         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7329         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7330                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7331                             conf->flow_type);
7332                 return -EINVAL;
7333         }
7334         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7335                                    conf->inset_size);
7336         if (ret) {
7337                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7338                 return -EINVAL;
7339         }
7340         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7341                                     input_set) != 0) {
7342                 PMD_DRV_LOG(ERR, "Invalid input set");
7343                 return -EINVAL;
7344         }
7345
7346         /* get inset value in register */
7347         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7348         inset_reg <<= I40E_32_BIT_WIDTH;
7349         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7350
7351         /* Can not change the inset reg for flex payload for fdir,
7352          * it is done by writing I40E_PRTQF_FD_FLXINSET
7353          * in i40e_set_flex_mask_on_pctype.
7354          */
7355         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7356                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7357         else
7358                 input_set |= pf->fdir.input_set[pctype];
7359         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7360                                            I40E_INSET_MASK_NUM_REG);
7361         if (num < 0)
7362                 return -EINVAL;
7363
7364         inset_reg |= i40e_translate_input_set_reg(input_set);
7365
7366         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7367                               (uint32_t)(inset_reg & UINT32_MAX));
7368         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7369                              (uint32_t)((inset_reg >>
7370                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7371
7372         for (i = 0; i < num; i++)
7373                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7374                                      mask_reg[i]);
7375         /*clear unused mask registers of the pctype */
7376         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7377                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7378                                      0);
7379         I40E_WRITE_FLUSH(hw);
7380
7381         pf->fdir.input_set[pctype] = input_set;
7382         return 0;
7383 }
7384
7385 static int
7386 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7387 {
7388         int ret = 0;
7389
7390         if (!hw || !info) {
7391                 PMD_DRV_LOG(ERR, "Invalid pointer");
7392                 return -EFAULT;
7393         }
7394
7395         switch (info->info_type) {
7396         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7397                 i40e_get_symmetric_hash_enable_per_port(hw,
7398                                         &(info->info.enable));
7399                 break;
7400         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7401                 ret = i40e_get_hash_filter_global_config(hw,
7402                                 &(info->info.global_conf));
7403                 break;
7404         default:
7405                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7406                                                         info->info_type);
7407                 ret = -EINVAL;
7408                 break;
7409         }
7410
7411         return ret;
7412 }
7413
7414 static int
7415 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7416 {
7417         int ret = 0;
7418
7419         if (!hw || !info) {
7420                 PMD_DRV_LOG(ERR, "Invalid pointer");
7421                 return -EFAULT;
7422         }
7423
7424         switch (info->info_type) {
7425         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7426                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7427                 break;
7428         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7429                 ret = i40e_set_hash_filter_global_config(hw,
7430                                 &(info->info.global_conf));
7431                 break;
7432         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7433                 ret = i40e_hash_filter_inset_select(hw,
7434                                                &(info->info.input_set_conf));
7435                 break;
7436
7437         default:
7438                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7439                                                         info->info_type);
7440                 ret = -EINVAL;
7441                 break;
7442         }
7443
7444         return ret;
7445 }
7446
7447 /* Operations for hash function */
7448 static int
7449 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7450                       enum rte_filter_op filter_op,
7451                       void *arg)
7452 {
7453         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7454         int ret = 0;
7455
7456         switch (filter_op) {
7457         case RTE_ETH_FILTER_NOP:
7458                 break;
7459         case RTE_ETH_FILTER_GET:
7460                 ret = i40e_hash_filter_get(hw,
7461                         (struct rte_eth_hash_filter_info *)arg);
7462                 break;
7463         case RTE_ETH_FILTER_SET:
7464                 ret = i40e_hash_filter_set(hw,
7465                         (struct rte_eth_hash_filter_info *)arg);
7466                 break;
7467         default:
7468                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7469                                                                 filter_op);
7470                 ret = -ENOTSUP;
7471                 break;
7472         }
7473
7474         return ret;
7475 }
7476
7477 /*
7478  * Configure ethertype filter, which can director packet by filtering
7479  * with mac address and ether_type or only ether_type
7480  */
7481 static int
7482 i40e_ethertype_filter_set(struct i40e_pf *pf,
7483                         struct rte_eth_ethertype_filter *filter,
7484                         bool add)
7485 {
7486         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7487         struct i40e_control_filter_stats stats;
7488         uint16_t flags = 0;
7489         int ret;
7490
7491         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7492                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7493                 return -EINVAL;
7494         }
7495         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7496                 filter->ether_type == ETHER_TYPE_IPv6) {
7497                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7498                         " control packet filter.", filter->ether_type);
7499                 return -EINVAL;
7500         }
7501         if (filter->ether_type == ETHER_TYPE_VLAN)
7502                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7503                         " not supported.");
7504
7505         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7506                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7507         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7508                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7509         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7510
7511         memset(&stats, 0, sizeof(stats));
7512         ret = i40e_aq_add_rem_control_packet_filter(hw,
7513                         filter->mac_addr.addr_bytes,
7514                         filter->ether_type, flags,
7515                         pf->main_vsi->seid,
7516                         filter->queue, add, &stats, NULL);
7517
7518         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7519                          " mac_etype_used = %u, etype_used = %u,"
7520                          " mac_etype_free = %u, etype_free = %u\n",
7521                          ret, stats.mac_etype_used, stats.etype_used,
7522                          stats.mac_etype_free, stats.etype_free);
7523         if (ret < 0)
7524                 return -ENOSYS;
7525         return 0;
7526 }
7527
7528 /*
7529  * Handle operations for ethertype filter.
7530  */
7531 static int
7532 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7533                                 enum rte_filter_op filter_op,
7534                                 void *arg)
7535 {
7536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7537         int ret = 0;
7538
7539         if (filter_op == RTE_ETH_FILTER_NOP)
7540                 return ret;
7541
7542         if (arg == NULL) {
7543                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7544                             filter_op);
7545                 return -EINVAL;
7546         }
7547
7548         switch (filter_op) {
7549         case RTE_ETH_FILTER_ADD:
7550                 ret = i40e_ethertype_filter_set(pf,
7551                         (struct rte_eth_ethertype_filter *)arg,
7552                         TRUE);
7553                 break;
7554         case RTE_ETH_FILTER_DELETE:
7555                 ret = i40e_ethertype_filter_set(pf,
7556                         (struct rte_eth_ethertype_filter *)arg,
7557                         FALSE);
7558                 break;
7559         default:
7560                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7561                 ret = -ENOSYS;
7562                 break;
7563         }
7564         return ret;
7565 }
7566
7567 static int
7568 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7569                      enum rte_filter_type filter_type,
7570                      enum rte_filter_op filter_op,
7571                      void *arg)
7572 {
7573         int ret = 0;
7574
7575         if (dev == NULL)
7576                 return -EINVAL;
7577
7578         switch (filter_type) {
7579         case RTE_ETH_FILTER_NONE:
7580                 /* For global configuration */
7581                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7582                 break;
7583         case RTE_ETH_FILTER_HASH:
7584                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7585                 break;
7586         case RTE_ETH_FILTER_MACVLAN:
7587                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7588                 break;
7589         case RTE_ETH_FILTER_ETHERTYPE:
7590                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7591                 break;
7592         case RTE_ETH_FILTER_TUNNEL:
7593                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7594                 break;
7595         case RTE_ETH_FILTER_FDIR:
7596                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7597                 break;
7598         default:
7599                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7600                                                         filter_type);
7601                 ret = -EINVAL;
7602                 break;
7603         }
7604
7605         return ret;
7606 }
7607
7608 /*
7609  * Check and enable Extended Tag.
7610  * Enabling Extended Tag is important for 40G performance.
7611  */
7612 static void
7613 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7614 {
7615         uint32_t buf = 0;
7616         int ret;
7617
7618         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7619                                       PCI_DEV_CAP_REG);
7620         if (ret < 0) {
7621                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7622                             PCI_DEV_CAP_REG);
7623                 return;
7624         }
7625         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7626                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7627                 return;
7628         }
7629
7630         buf = 0;
7631         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7632                                       PCI_DEV_CTRL_REG);
7633         if (ret < 0) {
7634                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7635                             PCI_DEV_CTRL_REG);
7636                 return;
7637         }
7638         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7639                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7640                 return;
7641         }
7642         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7643         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7644                                        PCI_DEV_CTRL_REG);
7645         if (ret < 0) {
7646                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7647                             PCI_DEV_CTRL_REG);
7648                 return;
7649         }
7650 }
7651
7652 /*
7653  * As some registers wouldn't be reset unless a global hardware reset,
7654  * hardware initialization is needed to put those registers into an
7655  * expected initial state.
7656  */
7657 static void
7658 i40e_hw_init(struct rte_eth_dev *dev)
7659 {
7660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7661
7662         i40e_enable_extended_tag(dev);
7663
7664         /* clear the PF Queue Filter control register */
7665         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7666
7667         /* Disable symmetric hash per port */
7668         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7669 }
7670
7671 enum i40e_filter_pctype
7672 i40e_flowtype_to_pctype(uint16_t flow_type)
7673 {
7674         static const enum i40e_filter_pctype pctype_table[] = {
7675                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7676                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7677                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7678                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7679                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7680                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7681                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7682                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7683                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7684                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7685                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7686                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7687                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7688                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7689                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7690                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7691                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7692                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7693                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7694         };
7695
7696         return pctype_table[flow_type];
7697 }
7698
7699 uint16_t
7700 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7701 {
7702         static const uint16_t flowtype_table[] = {
7703                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7704                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7705                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7706                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7707                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7708                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7709                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7710                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7711                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7712                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7713                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7714                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7715                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7716                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7717                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7718                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7719                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7720                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7721                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7722         };
7723
7724         return flowtype_table[pctype];
7725 }
7726
7727 /*
7728  * On X710, performance number is far from the expectation on recent firmware
7729  * versions; on XL710, performance number is also far from the expectation on
7730  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7731  * mode is enabled and port MAC address is equal to the packet destination MAC
7732  * address. The fix for this issue may not be integrated in the following
7733  * firmware version. So the workaround in software driver is needed. It needs
7734  * to modify the initial values of 3 internal only registers for both X710 and
7735  * XL710. Note that the values for X710 or XL710 could be different, and the
7736  * workaround can be removed when it is fixed in firmware in the future.
7737  */
7738
7739 /* For both X710 and XL710 */
7740 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7741 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7742
7743 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7744 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7745
7746 /* For X710 */
7747 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7748 /* For XL710 */
7749 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7750 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7751
7752 static void
7753 i40e_configure_registers(struct i40e_hw *hw)
7754 {
7755         static struct {
7756                 uint32_t addr;
7757                 uint64_t val;
7758         } reg_table[] = {
7759                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7760                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7761                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7762         };
7763         uint64_t reg;
7764         uint32_t i;
7765         int ret;
7766
7767         for (i = 0; i < RTE_DIM(reg_table); i++) {
7768                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7769                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7770                                 reg_table[i].val =
7771                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7772                         else /* For X710 */
7773                                 reg_table[i].val =
7774                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7775                 }
7776
7777                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7778                                                         &reg, NULL);
7779                 if (ret < 0) {
7780                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7781                                                         reg_table[i].addr);
7782                         break;
7783                 }
7784                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7785                                                 reg_table[i].addr, reg);
7786                 if (reg == reg_table[i].val)
7787                         continue;
7788
7789                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7790                                                 reg_table[i].val, NULL);
7791                 if (ret < 0) {
7792                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7793                                 "address of 0x%"PRIx32, reg_table[i].val,
7794                                                         reg_table[i].addr);
7795                         break;
7796                 }
7797                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7798                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7799         }
7800 }
7801
7802 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7803 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7804 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7805 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7806 static int
7807 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7808 {
7809         uint32_t reg;
7810         int ret;
7811
7812         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7813                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7814                 return -EINVAL;
7815         }
7816
7817         /* Configure for double VLAN RX stripping */
7818         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7819         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7820                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7821                 ret = i40e_aq_debug_write_register(hw,
7822                                                    I40E_VSI_TSR(vsi->vsi_id),
7823                                                    reg, NULL);
7824                 if (ret < 0) {
7825                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7826                                     vsi->vsi_id);
7827                         return I40E_ERR_CONFIG;
7828                 }
7829         }
7830
7831         /* Configure for double VLAN TX insertion */
7832         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7833         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7834                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7835                 ret = i40e_aq_debug_write_register(hw,
7836                                                    I40E_VSI_L2TAGSTXVALID(
7837                                                    vsi->vsi_id), reg, NULL);
7838                 if (ret < 0) {
7839                         PMD_DRV_LOG(ERR, "Failed to update "
7840                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7841                         return I40E_ERR_CONFIG;
7842                 }
7843         }
7844
7845         return 0;
7846 }
7847
7848 /**
7849  * i40e_aq_add_mirror_rule
7850  * @hw: pointer to the hardware structure
7851  * @seid: VEB seid to add mirror rule to
7852  * @dst_id: destination vsi seid
7853  * @entries: Buffer which contains the entities to be mirrored
7854  * @count: number of entities contained in the buffer
7855  * @rule_id:the rule_id of the rule to be added
7856  *
7857  * Add a mirror rule for a given veb.
7858  *
7859  **/
7860 static enum i40e_status_code
7861 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7862                         uint16_t seid, uint16_t dst_id,
7863                         uint16_t rule_type, uint16_t *entries,
7864                         uint16_t count, uint16_t *rule_id)
7865 {
7866         struct i40e_aq_desc desc;
7867         struct i40e_aqc_add_delete_mirror_rule cmd;
7868         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7869                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7870                 &desc.params.raw;
7871         uint16_t buff_len;
7872         enum i40e_status_code status;
7873
7874         i40e_fill_default_direct_cmd_desc(&desc,
7875                                           i40e_aqc_opc_add_mirror_rule);
7876         memset(&cmd, 0, sizeof(cmd));
7877
7878         buff_len = sizeof(uint16_t) * count;
7879         desc.datalen = rte_cpu_to_le_16(buff_len);
7880         if (buff_len > 0)
7881                 desc.flags |= rte_cpu_to_le_16(
7882                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7883         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7884                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7885         cmd.num_entries = rte_cpu_to_le_16(count);
7886         cmd.seid = rte_cpu_to_le_16(seid);
7887         cmd.destination = rte_cpu_to_le_16(dst_id);
7888
7889         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7890         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7891         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7892                          "rule_id = %u"
7893                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7894                          hw->aq.asq_last_status, resp->rule_id,
7895                          resp->mirror_rules_used, resp->mirror_rules_free);
7896         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7897
7898         return status;
7899 }
7900
7901 /**
7902  * i40e_aq_del_mirror_rule
7903  * @hw: pointer to the hardware structure
7904  * @seid: VEB seid to add mirror rule to
7905  * @entries: Buffer which contains the entities to be mirrored
7906  * @count: number of entities contained in the buffer
7907  * @rule_id:the rule_id of the rule to be delete
7908  *
7909  * Delete a mirror rule for a given veb.
7910  *
7911  **/
7912 static enum i40e_status_code
7913 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7914                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7915                 uint16_t count, uint16_t rule_id)
7916 {
7917         struct i40e_aq_desc desc;
7918         struct i40e_aqc_add_delete_mirror_rule cmd;
7919         uint16_t buff_len = 0;
7920         enum i40e_status_code status;
7921         void *buff = NULL;
7922
7923         i40e_fill_default_direct_cmd_desc(&desc,
7924                                           i40e_aqc_opc_delete_mirror_rule);
7925         memset(&cmd, 0, sizeof(cmd));
7926         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7927                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7928                                                           I40E_AQ_FLAG_RD));
7929                 cmd.num_entries = count;
7930                 buff_len = sizeof(uint16_t) * count;
7931                 desc.datalen = rte_cpu_to_le_16(buff_len);
7932                 buff = (void *)entries;
7933         } else
7934                 /* rule id is filled in destination field for deleting mirror rule */
7935                 cmd.destination = rte_cpu_to_le_16(rule_id);
7936
7937         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7938                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7939         cmd.seid = rte_cpu_to_le_16(seid);
7940
7941         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7942         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7943
7944         return status;
7945 }
7946
7947 /**
7948  * i40e_mirror_rule_set
7949  * @dev: pointer to the hardware structure
7950  * @mirror_conf: mirror rule info
7951  * @sw_id: mirror rule's sw_id
7952  * @on: enable/disable
7953  *
7954  * set a mirror rule.
7955  *
7956  **/
7957 static int
7958 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7959                         struct rte_eth_mirror_conf *mirror_conf,
7960                         uint8_t sw_id, uint8_t on)
7961 {
7962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7964         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7965         struct i40e_mirror_rule *parent = NULL;
7966         uint16_t seid, dst_seid, rule_id;
7967         uint16_t i, j = 0;
7968         int ret;
7969
7970         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7971
7972         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7973                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7974                         " without veb or vfs.");
7975                 return -ENOSYS;
7976         }
7977         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7978                 PMD_DRV_LOG(ERR, "mirror table is full.");
7979                 return -ENOSPC;
7980         }
7981         if (mirror_conf->dst_pool > pf->vf_num) {
7982                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7983                                  mirror_conf->dst_pool);
7984                 return -EINVAL;
7985         }
7986
7987         seid = pf->main_vsi->veb->seid;
7988
7989         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7990                 if (sw_id <= it->index) {
7991                         mirr_rule = it;
7992                         break;
7993                 }
7994                 parent = it;
7995         }
7996         if (mirr_rule && sw_id == mirr_rule->index) {
7997                 if (on) {
7998                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7999                         return -EEXIST;
8000                 } else {
8001                         ret = i40e_aq_del_mirror_rule(hw, seid,
8002                                         mirr_rule->rule_type,
8003                                         mirr_rule->entries,
8004                                         mirr_rule->num_entries, mirr_rule->id);
8005                         if (ret < 0) {
8006                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8007                                                    " ret = %d, aq_err = %d.",
8008                                                    ret, hw->aq.asq_last_status);
8009                                 return -ENOSYS;
8010                         }
8011                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8012                         rte_free(mirr_rule);
8013                         pf->nb_mirror_rule--;
8014                         return 0;
8015                 }
8016         } else if (!on) {
8017                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8018                 return -ENOENT;
8019         }
8020
8021         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8022                                 sizeof(struct i40e_mirror_rule) , 0);
8023         if (!mirr_rule) {
8024                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8025                 return I40E_ERR_NO_MEMORY;
8026         }
8027         switch (mirror_conf->rule_type) {
8028         case ETH_MIRROR_VLAN:
8029                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8030                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8031                                 mirr_rule->entries[j] =
8032                                         mirror_conf->vlan.vlan_id[i];
8033                                 j++;
8034                         }
8035                 }
8036                 if (j == 0) {
8037                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8038                         rte_free(mirr_rule);
8039                         return -EINVAL;
8040                 }
8041                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8042                 break;
8043         case ETH_MIRROR_VIRTUAL_POOL_UP:
8044         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8045                 /* check if the specified pool bit is out of range */
8046                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8047                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8048                         rte_free(mirr_rule);
8049                         return -EINVAL;
8050                 }
8051                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8052                         if (mirror_conf->pool_mask & (1ULL << i)) {
8053                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8054                                 j++;
8055                         }
8056                 }
8057                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8058                         /* add pf vsi to entries */
8059                         mirr_rule->entries[j] = pf->main_vsi_seid;
8060                         j++;
8061                 }
8062                 if (j == 0) {
8063                         PMD_DRV_LOG(ERR, "pool is not specified.");
8064                         rte_free(mirr_rule);
8065                         return -EINVAL;
8066                 }
8067                 /* egress and ingress in aq commands means from switch but not port */
8068                 mirr_rule->rule_type =
8069                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8070                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8071                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8072                 break;
8073         case ETH_MIRROR_UPLINK_PORT:
8074                 /* egress and ingress in aq commands means from switch but not port*/
8075                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8076                 break;
8077         case ETH_MIRROR_DOWNLINK_PORT:
8078                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8079                 break;
8080         default:
8081                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8082                         mirror_conf->rule_type);
8083                 rte_free(mirr_rule);
8084                 return -EINVAL;
8085         }
8086
8087         /* If the dst_pool is equal to vf_num, consider it as PF */
8088         if (mirror_conf->dst_pool == pf->vf_num)
8089                 dst_seid = pf->main_vsi_seid;
8090         else
8091                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8092
8093         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8094                                       mirr_rule->rule_type, mirr_rule->entries,
8095                                       j, &rule_id);
8096         if (ret < 0) {
8097                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8098                                    " ret = %d, aq_err = %d.",
8099                                    ret, hw->aq.asq_last_status);
8100                 rte_free(mirr_rule);
8101                 return -ENOSYS;
8102         }
8103
8104         mirr_rule->index = sw_id;
8105         mirr_rule->num_entries = j;
8106         mirr_rule->id = rule_id;
8107         mirr_rule->dst_vsi_seid = dst_seid;
8108
8109         if (parent)
8110                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8111         else
8112                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8113
8114         pf->nb_mirror_rule++;
8115         return 0;
8116 }
8117
8118 /**
8119  * i40e_mirror_rule_reset
8120  * @dev: pointer to the device
8121  * @sw_id: mirror rule's sw_id
8122  *
8123  * reset a mirror rule.
8124  *
8125  **/
8126 static int
8127 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8128 {
8129         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8131         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8132         uint16_t seid;
8133         int ret;
8134
8135         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8136
8137         seid = pf->main_vsi->veb->seid;
8138
8139         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8140                 if (sw_id == it->index) {
8141                         mirr_rule = it;
8142                         break;
8143                 }
8144         }
8145         if (mirr_rule) {
8146                 ret = i40e_aq_del_mirror_rule(hw, seid,
8147                                 mirr_rule->rule_type,
8148                                 mirr_rule->entries,
8149                                 mirr_rule->num_entries, mirr_rule->id);
8150                 if (ret < 0) {
8151                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8152                                            " status = %d, aq_err = %d.",
8153                                            ret, hw->aq.asq_last_status);
8154                         return -ENOSYS;
8155                 }
8156                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8157                 rte_free(mirr_rule);
8158                 pf->nb_mirror_rule--;
8159         } else {
8160                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8161                 return -ENOENT;
8162         }
8163         return 0;
8164 }
8165
8166 static uint64_t
8167 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8168 {
8169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8170         uint64_t systim_cycles;
8171
8172         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8173         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8174                         << 32;
8175
8176         return systim_cycles;
8177 }
8178
8179 static uint64_t
8180 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8181 {
8182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8183         uint64_t rx_tstamp;
8184
8185         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8186         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8187                         << 32;
8188
8189         return rx_tstamp;
8190 }
8191
8192 static uint64_t
8193 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8194 {
8195         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8196         uint64_t tx_tstamp;
8197
8198         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8199         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8200                         << 32;
8201
8202         return tx_tstamp;
8203 }
8204
8205 static void
8206 i40e_start_timecounters(struct rte_eth_dev *dev)
8207 {
8208         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8209         struct i40e_adapter *adapter =
8210                         (struct i40e_adapter *)dev->data->dev_private;
8211         struct rte_eth_link link;
8212         uint32_t tsync_inc_l;
8213         uint32_t tsync_inc_h;
8214
8215         /* Get current link speed. */
8216         memset(&link, 0, sizeof(link));
8217         i40e_dev_link_update(dev, 1);
8218         rte_i40e_dev_atomic_read_link_status(dev, &link);
8219
8220         switch (link.link_speed) {
8221         case ETH_SPEED_NUM_40G:
8222                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8223                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8224                 break;
8225         case ETH_SPEED_NUM_10G:
8226                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8227                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8228                 break;
8229         case ETH_SPEED_NUM_1G:
8230                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8231                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8232                 break;
8233         default:
8234                 tsync_inc_l = 0x0;
8235                 tsync_inc_h = 0x0;
8236         }
8237
8238         /* Set the timesync increment value. */
8239         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8240         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8241
8242         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8243         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8244         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8245
8246         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8247         adapter->systime_tc.cc_shift = 0;
8248         adapter->systime_tc.nsec_mask = 0;
8249
8250         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8251         adapter->rx_tstamp_tc.cc_shift = 0;
8252         adapter->rx_tstamp_tc.nsec_mask = 0;
8253
8254         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8255         adapter->tx_tstamp_tc.cc_shift = 0;
8256         adapter->tx_tstamp_tc.nsec_mask = 0;
8257 }
8258
8259 static int
8260 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8261 {
8262         struct i40e_adapter *adapter =
8263                         (struct i40e_adapter *)dev->data->dev_private;
8264
8265         adapter->systime_tc.nsec += delta;
8266         adapter->rx_tstamp_tc.nsec += delta;
8267         adapter->tx_tstamp_tc.nsec += delta;
8268
8269         return 0;
8270 }
8271
8272 static int
8273 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8274 {
8275         uint64_t ns;
8276         struct i40e_adapter *adapter =
8277                         (struct i40e_adapter *)dev->data->dev_private;
8278
8279         ns = rte_timespec_to_ns(ts);
8280
8281         /* Set the timecounters to a new value. */
8282         adapter->systime_tc.nsec = ns;
8283         adapter->rx_tstamp_tc.nsec = ns;
8284         adapter->tx_tstamp_tc.nsec = ns;
8285
8286         return 0;
8287 }
8288
8289 static int
8290 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8291 {
8292         uint64_t ns, systime_cycles;
8293         struct i40e_adapter *adapter =
8294                         (struct i40e_adapter *)dev->data->dev_private;
8295
8296         systime_cycles = i40e_read_systime_cyclecounter(dev);
8297         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8298         *ts = rte_ns_to_timespec(ns);
8299
8300         return 0;
8301 }
8302
8303 static int
8304 i40e_timesync_enable(struct rte_eth_dev *dev)
8305 {
8306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8307         uint32_t tsync_ctl_l;
8308         uint32_t tsync_ctl_h;
8309
8310         /* Stop the timesync system time. */
8311         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8312         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8313         /* Reset the timesync system time value. */
8314         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8315         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8316
8317         i40e_start_timecounters(dev);
8318
8319         /* Clear timesync registers. */
8320         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8321         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8322         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8323         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8324         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8325         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8326
8327         /* Enable timestamping of PTP packets. */
8328         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8329         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8330
8331         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8332         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8333         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8334
8335         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8336         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8337
8338         return 0;
8339 }
8340
8341 static int
8342 i40e_timesync_disable(struct rte_eth_dev *dev)
8343 {
8344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8345         uint32_t tsync_ctl_l;
8346         uint32_t tsync_ctl_h;
8347
8348         /* Disable timestamping of transmitted PTP packets. */
8349         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8350         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8351
8352         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8353         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8354
8355         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8356         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8357
8358         /* Reset the timesync increment value. */
8359         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8360         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8361
8362         return 0;
8363 }
8364
8365 static int
8366 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8367                                 struct timespec *timestamp, uint32_t flags)
8368 {
8369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8370         struct i40e_adapter *adapter =
8371                 (struct i40e_adapter *)dev->data->dev_private;
8372
8373         uint32_t sync_status;
8374         uint32_t index = flags & 0x03;
8375         uint64_t rx_tstamp_cycles;
8376         uint64_t ns;
8377
8378         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8379         if ((sync_status & (1 << index)) == 0)
8380                 return -EINVAL;
8381
8382         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8383         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8384         *timestamp = rte_ns_to_timespec(ns);
8385
8386         return 0;
8387 }
8388
8389 static int
8390 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8391                                 struct timespec *timestamp)
8392 {
8393         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8394         struct i40e_adapter *adapter =
8395                 (struct i40e_adapter *)dev->data->dev_private;
8396
8397         uint32_t sync_status;
8398         uint64_t tx_tstamp_cycles;
8399         uint64_t ns;
8400
8401         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8402         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8403                 return -EINVAL;
8404
8405         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8406         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8407         *timestamp = rte_ns_to_timespec(ns);
8408
8409         return 0;
8410 }
8411
8412 /*
8413  * i40e_parse_dcb_configure - parse dcb configure from user
8414  * @dev: the device being configured
8415  * @dcb_cfg: pointer of the result of parse
8416  * @*tc_map: bit map of enabled traffic classes
8417  *
8418  * Returns 0 on success, negative value on failure
8419  */
8420 static int
8421 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8422                          struct i40e_dcbx_config *dcb_cfg,
8423                          uint8_t *tc_map)
8424 {
8425         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8426         uint8_t i, tc_bw, bw_lf;
8427
8428         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8429
8430         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8431         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8432                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8433                 return -EINVAL;
8434         }
8435
8436         /* assume each tc has the same bw */
8437         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8438         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8439                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8440         /* to ensure the sum of tcbw is equal to 100 */
8441         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8442         for (i = 0; i < bw_lf; i++)
8443                 dcb_cfg->etscfg.tcbwtable[i]++;
8444
8445         /* assume each tc has the same Transmission Selection Algorithm */
8446         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8447                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8448
8449         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8450                 dcb_cfg->etscfg.prioritytable[i] =
8451                                 dcb_rx_conf->dcb_tc[i];
8452
8453         /* FW needs one App to configure HW */
8454         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8455         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8456         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8457         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8458
8459         if (dcb_rx_conf->nb_tcs == 0)
8460                 *tc_map = 1; /* tc0 only */
8461         else
8462                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8463
8464         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8465                 dcb_cfg->pfc.willing = 0;
8466                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8467                 dcb_cfg->pfc.pfcenable = *tc_map;
8468         }
8469         return 0;
8470 }
8471
8472
8473 static enum i40e_status_code
8474 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8475                               struct i40e_aqc_vsi_properties_data *info,
8476                               uint8_t enabled_tcmap)
8477 {
8478         enum i40e_status_code ret;
8479         int i, total_tc = 0;
8480         uint16_t qpnum_per_tc, bsf, qp_idx;
8481         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8482         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8483         uint16_t used_queues;
8484
8485         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8486         if (ret != I40E_SUCCESS)
8487                 return ret;
8488
8489         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8490                 if (enabled_tcmap & (1 << i))
8491                         total_tc++;
8492         }
8493         if (total_tc == 0)
8494                 total_tc = 1;
8495         vsi->enabled_tc = enabled_tcmap;
8496
8497         /* different VSI has different queues assigned */
8498         if (vsi->type == I40E_VSI_MAIN)
8499                 used_queues = dev_data->nb_rx_queues -
8500                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8501         else if (vsi->type == I40E_VSI_VMDQ2)
8502                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8503         else {
8504                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8505                 return I40E_ERR_NO_AVAILABLE_VSI;
8506         }
8507
8508         qpnum_per_tc = used_queues / total_tc;
8509         /* Number of queues per enabled TC */
8510         if (qpnum_per_tc == 0) {
8511                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8512                 return I40E_ERR_INVALID_QP_ID;
8513         }
8514         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8515                                 I40E_MAX_Q_PER_TC);
8516         bsf = rte_bsf32(qpnum_per_tc);
8517
8518         /**
8519          * Configure TC and queue mapping parameters, for enabled TC,
8520          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8521          * default queue will serve it.
8522          */
8523         qp_idx = 0;
8524         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8525                 if (vsi->enabled_tc & (1 << i)) {
8526                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8527                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8528                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8529                         qp_idx += qpnum_per_tc;
8530                 } else
8531                         info->tc_mapping[i] = 0;
8532         }
8533
8534         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8535         if (vsi->type == I40E_VSI_SRIOV) {
8536                 info->mapping_flags |=
8537                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8538                 for (i = 0; i < vsi->nb_qps; i++)
8539                         info->queue_mapping[i] =
8540                                 rte_cpu_to_le_16(vsi->base_queue + i);
8541         } else {
8542                 info->mapping_flags |=
8543                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8544                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8545         }
8546         info->valid_sections |=
8547                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8548
8549         return I40E_SUCCESS;
8550 }
8551
8552 /*
8553  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8554  * @veb: VEB to be configured
8555  * @tc_map: enabled TC bitmap
8556  *
8557  * Returns 0 on success, negative value on failure
8558  */
8559 static enum i40e_status_code
8560 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8561 {
8562         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8563         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8564         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8565         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8566         enum i40e_status_code ret = I40E_SUCCESS;
8567         int i;
8568         uint32_t bw_max;
8569
8570         /* Check if enabled_tc is same as existing or new TCs */
8571         if (veb->enabled_tc == tc_map)
8572                 return ret;
8573
8574         /* configure tc bandwidth */
8575         memset(&veb_bw, 0, sizeof(veb_bw));
8576         veb_bw.tc_valid_bits = tc_map;
8577         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8578         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8579                 if (tc_map & BIT_ULL(i))
8580                         veb_bw.tc_bw_share_credits[i] = 1;
8581         }
8582         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8583                                                    &veb_bw, NULL);
8584         if (ret) {
8585                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8586                                   " per TC failed = %d",
8587                                   hw->aq.asq_last_status);
8588                 return ret;
8589         }
8590
8591         memset(&ets_query, 0, sizeof(ets_query));
8592         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8593                                                    &ets_query, NULL);
8594         if (ret != I40E_SUCCESS) {
8595                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8596                                  " configuration %u", hw->aq.asq_last_status);
8597                 return ret;
8598         }
8599         memset(&bw_query, 0, sizeof(bw_query));
8600         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8601                                                   &bw_query, NULL);
8602         if (ret != I40E_SUCCESS) {
8603                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8604                                  " configuration %u", hw->aq.asq_last_status);
8605                 return ret;
8606         }
8607
8608         /* store and print out BW info */
8609         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8610         veb->bw_info.bw_max = ets_query.tc_bw_max;
8611         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8612         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8613         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8614                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8615                      I40E_16_BIT_WIDTH);
8616         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8617                 veb->bw_info.bw_ets_share_credits[i] =
8618                                 bw_query.tc_bw_share_credits[i];
8619                 veb->bw_info.bw_ets_credits[i] =
8620                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8621                 /* 4 bits per TC, 4th bit is reserved */
8622                 veb->bw_info.bw_ets_max[i] =
8623                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8624                                   RTE_LEN2MASK(3, uint8_t));
8625                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8626                             veb->bw_info.bw_ets_share_credits[i]);
8627                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8628                             veb->bw_info.bw_ets_credits[i]);
8629                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8630                             veb->bw_info.bw_ets_max[i]);
8631         }
8632
8633         veb->enabled_tc = tc_map;
8634
8635         return ret;
8636 }
8637
8638
8639 /*
8640  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8641  * @vsi: VSI to be configured
8642  * @tc_map: enabled TC bitmap
8643  *
8644  * Returns 0 on success, negative value on failure
8645  */
8646 static enum i40e_status_code
8647 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8648 {
8649         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8650         struct i40e_vsi_context ctxt;
8651         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8652         enum i40e_status_code ret = I40E_SUCCESS;
8653         int i;
8654
8655         /* Check if enabled_tc is same as existing or new TCs */
8656         if (vsi->enabled_tc == tc_map)
8657                 return ret;
8658
8659         /* configure tc bandwidth */
8660         memset(&bw_data, 0, sizeof(bw_data));
8661         bw_data.tc_valid_bits = tc_map;
8662         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8663         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8664                 if (tc_map & BIT_ULL(i))
8665                         bw_data.tc_bw_credits[i] = 1;
8666         }
8667         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8668         if (ret) {
8669                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8670                         " per TC failed = %d",
8671                         hw->aq.asq_last_status);
8672                 goto out;
8673         }
8674         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8675                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8676
8677         /* Update Queue Pairs Mapping for currently enabled UPs */
8678         ctxt.seid = vsi->seid;
8679         ctxt.pf_num = hw->pf_id;
8680         ctxt.vf_num = 0;
8681         ctxt.uplink_seid = vsi->uplink_seid;
8682         ctxt.info = vsi->info;
8683         i40e_get_cap(hw);
8684         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8685         if (ret)
8686                 goto out;
8687
8688         /* Update the VSI after updating the VSI queue-mapping information */
8689         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8690         if (ret) {
8691                 PMD_INIT_LOG(ERR, "Failed to configure "
8692                             "TC queue mapping = %d",
8693                             hw->aq.asq_last_status);
8694                 goto out;
8695         }
8696         /* update the local VSI info with updated queue map */
8697         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8698                                         sizeof(vsi->info.tc_mapping));
8699         (void)rte_memcpy(&vsi->info.queue_mapping,
8700                         &ctxt.info.queue_mapping,
8701                 sizeof(vsi->info.queue_mapping));
8702         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8703         vsi->info.valid_sections = 0;
8704
8705         /* query and update current VSI BW information */
8706         ret = i40e_vsi_get_bw_config(vsi);
8707         if (ret) {
8708                 PMD_INIT_LOG(ERR,
8709                          "Failed updating vsi bw info, err %s aq_err %s",
8710                          i40e_stat_str(hw, ret),
8711                          i40e_aq_str(hw, hw->aq.asq_last_status));
8712                 goto out;
8713         }
8714
8715         vsi->enabled_tc = tc_map;
8716
8717 out:
8718         return ret;
8719 }
8720
8721 /*
8722  * i40e_dcb_hw_configure - program the dcb setting to hw
8723  * @pf: pf the configuration is taken on
8724  * @new_cfg: new configuration
8725  * @tc_map: enabled TC bitmap
8726  *
8727  * Returns 0 on success, negative value on failure
8728  */
8729 static enum i40e_status_code
8730 i40e_dcb_hw_configure(struct i40e_pf *pf,
8731                       struct i40e_dcbx_config *new_cfg,
8732                       uint8_t tc_map)
8733 {
8734         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8735         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8736         struct i40e_vsi *main_vsi = pf->main_vsi;
8737         struct i40e_vsi_list *vsi_list;
8738         enum i40e_status_code ret;
8739         int i;
8740         uint32_t val;
8741
8742         /* Use the FW API if FW > v4.4*/
8743         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8744               (hw->aq.fw_maj_ver >= 5))) {
8745                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8746                                   " to configure DCB");
8747                 return I40E_ERR_FIRMWARE_API_VERSION;
8748         }
8749
8750         /* Check if need reconfiguration */
8751         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8752                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8753                 return I40E_SUCCESS;
8754         }
8755
8756         /* Copy the new config to the current config */
8757         *old_cfg = *new_cfg;
8758         old_cfg->etsrec = old_cfg->etscfg;
8759         ret = i40e_set_dcb_config(hw);
8760         if (ret) {
8761                 PMD_INIT_LOG(ERR,
8762                          "Set DCB Config failed, err %s aq_err %s\n",
8763                          i40e_stat_str(hw, ret),
8764                          i40e_aq_str(hw, hw->aq.asq_last_status));
8765                 return ret;
8766         }
8767         /* set receive Arbiter to RR mode and ETS scheme by default */
8768         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8769                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8770                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8771                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8772                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8773                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8774                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8775                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8776                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8777                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8778                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8779                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8780                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8781         }
8782         /* get local mib to check whether it is configured correctly */
8783         /* IEEE mode */
8784         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8785         /* Get Local DCB Config */
8786         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8787                                      &hw->local_dcbx_config);
8788
8789         /* if Veb is created, need to update TC of it at first */
8790         if (main_vsi->veb) {
8791                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8792                 if (ret)
8793                         PMD_INIT_LOG(WARNING,
8794                                  "Failed configuring TC for VEB seid=%d\n",
8795                                  main_vsi->veb->seid);
8796         }
8797         /* Update each VSI */
8798         i40e_vsi_config_tc(main_vsi, tc_map);
8799         if (main_vsi->veb) {
8800                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8801                         /* Beside main VSI and VMDQ VSIs, only enable default
8802                          * TC for other VSIs
8803                          */
8804                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8805                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8806                                                          tc_map);
8807                         else
8808                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8809                                                          I40E_DEFAULT_TCMAP);
8810                         if (ret)
8811                                 PMD_INIT_LOG(WARNING,
8812                                          "Failed configuring TC for VSI seid=%d\n",
8813                                          vsi_list->vsi->seid);
8814                         /* continue */
8815                 }
8816         }
8817         return I40E_SUCCESS;
8818 }
8819
8820 /*
8821  * i40e_dcb_init_configure - initial dcb config
8822  * @dev: device being configured
8823  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8824  *
8825  * Returns 0 on success, negative value on failure
8826  */
8827 static int
8828 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8829 {
8830         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8832         int ret = 0;
8833
8834         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8835                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8836                 return -ENOTSUP;
8837         }
8838
8839         /* DCB initialization:
8840          * Update DCB configuration from the Firmware and configure
8841          * LLDP MIB change event.
8842          */
8843         if (sw_dcb == TRUE) {
8844                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8845                 if (ret != I40E_SUCCESS)
8846                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8847
8848                 ret = i40e_init_dcb(hw);
8849                 /* if sw_dcb, lldp agent is stopped, the return from
8850                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8851                  * adminq status.
8852                  */
8853                 if (ret != I40E_SUCCESS &&
8854                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8855                         memset(&hw->local_dcbx_config, 0,
8856                                 sizeof(struct i40e_dcbx_config));
8857                         /* set dcb default configuration */
8858                         hw->local_dcbx_config.etscfg.willing = 0;
8859                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8860                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8861                         hw->local_dcbx_config.etscfg.tsatable[0] =
8862                                                 I40E_IEEE_TSA_ETS;
8863                         hw->local_dcbx_config.etsrec =
8864                                 hw->local_dcbx_config.etscfg;
8865                         hw->local_dcbx_config.pfc.willing = 0;
8866                         hw->local_dcbx_config.pfc.pfccap =
8867                                                 I40E_MAX_TRAFFIC_CLASS;
8868                         /* FW needs one App to configure HW */
8869                         hw->local_dcbx_config.numapps = 1;
8870                         hw->local_dcbx_config.app[0].selector =
8871                                                 I40E_APP_SEL_ETHTYPE;
8872                         hw->local_dcbx_config.app[0].priority = 3;
8873                         hw->local_dcbx_config.app[0].protocolid =
8874                                                 I40E_APP_PROTOID_FCOE;
8875                         ret = i40e_set_dcb_config(hw);
8876                         if (ret) {
8877                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8878                                         " err = %d, aq_err = %d.", ret,
8879                                           hw->aq.asq_last_status);
8880                                 return -ENOSYS;
8881                         }
8882                 } else {
8883                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8884                                           " aq_err = %d.", ret,
8885                                           hw->aq.asq_last_status);
8886                         return -ENOTSUP;
8887                 }
8888         } else {
8889                 ret = i40e_aq_start_lldp(hw, NULL);
8890                 if (ret != I40E_SUCCESS)
8891                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8892
8893                 ret = i40e_init_dcb(hw);
8894                 if (!ret) {
8895                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8896                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8897                                                   " DCBX offload.");
8898                                 return -ENOTSUP;
8899                         }
8900                 } else {
8901                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8902                                           " aq_err = %d.", ret,
8903                                           hw->aq.asq_last_status);
8904                         return -ENOTSUP;
8905                 }
8906         }
8907         return 0;
8908 }
8909
8910 /*
8911  * i40e_dcb_setup - setup dcb related config
8912  * @dev: device being configured
8913  *
8914  * Returns 0 on success, negative value on failure
8915  */
8916 static int
8917 i40e_dcb_setup(struct rte_eth_dev *dev)
8918 {
8919         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8920         struct i40e_dcbx_config dcb_cfg;
8921         uint8_t tc_map = 0;
8922         int ret = 0;
8923
8924         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8925                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8926                 return -ENOTSUP;
8927         }
8928
8929         if (pf->vf_num != 0)
8930                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8931
8932         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8933         if (ret) {
8934                 PMD_INIT_LOG(ERR, "invalid dcb config");
8935                 return -EINVAL;
8936         }
8937         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8938         if (ret) {
8939                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8940                 return -ENOSYS;
8941         }
8942
8943         return 0;
8944 }
8945
8946 static int
8947 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8948                       struct rte_eth_dcb_info *dcb_info)
8949 {
8950         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8951         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8952         struct i40e_vsi *vsi = pf->main_vsi;
8953         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8954         uint16_t bsf, tc_mapping;
8955         int i, j = 0;
8956
8957         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8958                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8959         else
8960                 dcb_info->nb_tcs = 1;
8961         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8962                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8963         for (i = 0; i < dcb_info->nb_tcs; i++)
8964                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8965
8966         /* get queue mapping if vmdq is disabled */
8967         if (!pf->nb_cfg_vmdq_vsi) {
8968                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8969                         if (!(vsi->enabled_tc & (1 << i)))
8970                                 continue;
8971                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8972                         dcb_info->tc_queue.tc_rxq[j][i].base =
8973                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8974                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8975                         dcb_info->tc_queue.tc_txq[j][i].base =
8976                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8977                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8978                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8979                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8980                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8981                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8982                 }
8983                 return 0;
8984         }
8985
8986         /* get queue mapping if vmdq is enabled */
8987         do {
8988                 vsi = pf->vmdq[j].vsi;
8989                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8990                         if (!(vsi->enabled_tc & (1 << i)))
8991                                 continue;
8992                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8993                         dcb_info->tc_queue.tc_rxq[j][i].base =
8994                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8995                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8996                         dcb_info->tc_queue.tc_txq[j][i].base =
8997                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8998                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8999                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9000                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9001                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9002                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9003                 }
9004                 j++;
9005         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9006         return 0;
9007 }
9008
9009 static int
9010 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9011 {
9012         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9013         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9014         uint16_t interval =
9015                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9016         uint16_t msix_intr;
9017
9018         msix_intr = intr_handle->intr_vec[queue_id];
9019         if (msix_intr == I40E_MISC_VEC_ID)
9020                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9021                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9022                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9023                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9024                                (interval <<
9025                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9026         else
9027                 I40E_WRITE_REG(hw,
9028                                I40E_PFINT_DYN_CTLN(msix_intr -
9029                                                    I40E_RX_VEC_START),
9030                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9031                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9032                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9033                                (interval <<
9034                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9035
9036         I40E_WRITE_FLUSH(hw);
9037         rte_intr_enable(&dev->pci_dev->intr_handle);
9038
9039         return 0;
9040 }
9041
9042 static int
9043 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9044 {
9045         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9046         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9047         uint16_t msix_intr;
9048
9049         msix_intr = intr_handle->intr_vec[queue_id];
9050         if (msix_intr == I40E_MISC_VEC_ID)
9051                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9052         else
9053                 I40E_WRITE_REG(hw,
9054                                I40E_PFINT_DYN_CTLN(msix_intr -
9055                                                    I40E_RX_VEC_START),
9056                                0);
9057         I40E_WRITE_FLUSH(hw);
9058
9059         return 0;
9060 }
9061
9062 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9063 {
9064         /* Highest base addr + 32-bit word */
9065         return I40E_GLGEN_STAT_CLEAR + 4;
9066 }
9067
9068 static int i40e_get_regs(struct rte_eth_dev *dev,
9069                          struct rte_dev_reg_info *regs)
9070 {
9071         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9072         uint32_t *ptr_data = regs->data;
9073         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9074         const struct i40e_reg_info *reg_info;
9075
9076         /* The first few registers have to be read using AQ operations */
9077         reg_idx = 0;
9078         while (i40e_regs_adminq[reg_idx].name) {
9079                 reg_info = &i40e_regs_adminq[reg_idx++];
9080                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9081                         for (arr_idx2 = 0;
9082                                         arr_idx2 <= reg_info->count2;
9083                                         arr_idx2++) {
9084                                 reg_offset = arr_idx * reg_info->stride1 +
9085                                         arr_idx2 * reg_info->stride2;
9086                                 reg_offset += reg_info->base_addr;
9087                                 ptr_data[reg_offset >> 2] =
9088                                         i40e_read_rx_ctl(hw, reg_offset);
9089                         }
9090         }
9091
9092         /* The remaining registers can be read using primitives */
9093         reg_idx = 0;
9094         while (i40e_regs_others[reg_idx].name) {
9095                 reg_info = &i40e_regs_others[reg_idx++];
9096                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9097                         for (arr_idx2 = 0;
9098                                         arr_idx2 <= reg_info->count2;
9099                                         arr_idx2++) {
9100                                 reg_offset = arr_idx * reg_info->stride1 +
9101                                         arr_idx2 * reg_info->stride2;
9102                                 reg_offset += reg_info->base_addr;
9103                                 ptr_data[reg_offset >> 2] =
9104                                         I40E_READ_REG(hw, reg_offset);
9105                         }
9106         }
9107
9108         return 0;
9109 }
9110
9111 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9112 {
9113         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9114
9115         /* Convert word count to byte count */
9116         return hw->nvm.sr_size << 1;
9117 }
9118
9119 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9120                            struct rte_dev_eeprom_info *eeprom)
9121 {
9122         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9123         uint16_t *data = eeprom->data;
9124         uint16_t offset, length, cnt_words;
9125         int ret_code;
9126
9127         offset = eeprom->offset >> 1;
9128         length = eeprom->length >> 1;
9129         cnt_words = length;
9130
9131         if (offset > hw->nvm.sr_size ||
9132                 offset + length > hw->nvm.sr_size) {
9133                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9134                 return -EINVAL;
9135         }
9136
9137         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9138
9139         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9140         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9141                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9142                 return -EIO;
9143         }
9144
9145         return 0;
9146 }
9147
9148 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9149                                       struct ether_addr *mac_addr)
9150 {
9151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9152
9153         if (!is_valid_assigned_ether_addr(mac_addr)) {
9154                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9155                 return;
9156         }
9157
9158         /* Flags: 0x3 updates port address */
9159         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9160 }