drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_atomic.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum i40e_virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum i40e_virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   __rte_unused int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
 123                                 int on);
 124 static void i40evf_dev_close(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 129 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 130 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 131                                      uint16_t rx_queue_id);
 132 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 133                                     uint16_t rx_queue_id);
 134 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 135                                      uint16_t tx_queue_id);
 136 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 137                                     uint16_t tx_queue_id);
 138 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
 139                                 struct ether_addr *addr,
 140                                 uint32_t index,
 141                                 uint32_t pool);
 142 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 143 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 144                         struct rte_eth_rss_reta_entry64 *reta_conf,
 145                         uint16_t reta_size);
 146 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 147                         struct rte_eth_rss_reta_entry64 *reta_conf,
 148                         uint16_t reta_size);
 149 static int i40evf_config_rss(struct i40e_vf *vf);
 150 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 151                                       struct rte_eth_rss_conf *rss_conf);
 152 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 153                                         struct rte_eth_rss_conf *rss_conf);
 154 static int
 155 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 156 static int
 157 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
 159                                    uint8_t *msg,
 160                                    uint16_t msglen);
 161
 162 /* Default hash key buffer for RSS */
 163 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 164
 165 struct rte_i40evf_xstats_name_off {
 166         char name[RTE_ETH_XSTATS_NAME_SIZE];
 167         unsigned offset;
 168 };
 169
 170 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 171         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 172         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 173         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 174         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 175         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 176         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 177                 rx_unknown_protocol)},
 178         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 179         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 180         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 181         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 182         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 183         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 184 };
 185
 186 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 187                 sizeof(rte_i40evf_stats_strings[0]))
 188
 189 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 190         .dev_configure        = i40evf_dev_configure,
 191         .dev_start            = i40evf_dev_start,
 192         .dev_stop             = i40evf_dev_stop,
 193         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 194         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 195         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 196         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 197         .link_update          = i40evf_dev_link_update,
 198         .stats_get            = i40evf_dev_stats_get,
 199         .xstats_get           = i40evf_dev_xstats_get,
 200         .xstats_get_names     = i40evf_dev_xstats_get_names,
 201         .xstats_reset         = i40evf_dev_xstats_reset,
 202         .dev_close            = i40evf_dev_close,
 203         .dev_infos_get        = i40evf_dev_info_get,
 204         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 205         .vlan_filter_set      = i40evf_vlan_filter_set,
 206         .vlan_offload_set     = i40evf_vlan_offload_set,
 207         .vlan_pvid_set        = i40evf_vlan_pvid_set,
 208         .rx_queue_start       = i40evf_dev_rx_queue_start,
 209         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 210         .tx_queue_start       = i40evf_dev_tx_queue_start,
 211         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 212         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 213         .rx_queue_release     = i40e_dev_rx_queue_release,
 214         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 215         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 216         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 217         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 218         .tx_queue_release     = i40e_dev_tx_queue_release,
 219         .rx_queue_count       = i40e_dev_rx_queue_count,
 220         .rxq_info_get         = i40e_rxq_info_get,
 221         .txq_info_get         = i40e_txq_info_get,
 222         .mac_addr_add         = i40evf_add_mac_addr,
 223         .mac_addr_remove      = i40evf_del_mac_addr,
 224         .reta_update          = i40evf_dev_rss_reta_update,
 225         .reta_query           = i40evf_dev_rss_reta_query,
 226         .rss_hash_update      = i40evf_dev_rss_hash_update,
 227         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 228 };
 229
 230 /*
 231  * Read data in admin queue to get msg from pf driver
 232  */
 233 static enum i40evf_aq_result
 234 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 235 {
 236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 237         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 238         struct i40e_arq_event_info event;
 239         enum i40e_virtchnl_ops opcode;
 240         enum i40e_status_code retval;
 241         int ret;
 242         enum i40evf_aq_result result = I40EVF_MSG_NON;
 243
 244         event.buf_len = data->buf_len;
 245         event.msg_buf = data->msg;
 246         ret = i40e_clean_arq_element(hw, &event, NULL);
 247         /* Can't read any msg from adminQ */
 248         if (ret) {
 249                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 250                         result = I40EVF_MSG_ERR;
 251                 return result;
 252         }
 253
 254         opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 255         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 256         /* pf sys event */
 257         if (opcode == I40E_VIRTCHNL_OP_EVENT) {
 258                 struct i40e_virtchnl_pf_event *vpe =
 259                         (struct i40e_virtchnl_pf_event *)event.msg_buf;
 260
 261                 result = I40EVF_MSG_SYS;
 262                 switch (vpe->event) {
 263                 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
 264                         vf->link_up =
 265                                 vpe->event_data.link_event.link_status;
 266                         vf->link_speed =
 267                                 vpe->event_data.link_event.link_speed;
 268                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 269                         PMD_DRV_LOG(INFO, "Link status update:%s",
 270                                     vf->link_up ? "up" : "down");
 271                         break;
 272                 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
 273                         vf->vf_reset = true;
 274                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 275                         PMD_DRV_LOG(INFO, "vf is reseting");
 276                         break;
 277                 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 278                         vf->dev_closed = true;
 279                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 280                         PMD_DRV_LOG(INFO, "PF driver closed");
 281                         break;
 282                 default:
 283                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 284                                     __func__, vpe->event);
 285                 }
 286         } else {
 287                 /* async reply msg on command issued by vf previously */
 288                 result = I40EVF_MSG_CMD;
 289                 /* Actual data length read from PF */
 290                 data->msg_len = event.msg_len;
 291         }
 292
 293         data->result = retval;
 294         data->ops = opcode;
 295
 296         return result;
 297 }
 298
 299 /**
 300  * clear current command. Only call in case execute
 301  * _atomic_set_cmd successfully.
 302  */
 303 static inline void
 304 _clear_cmd(struct i40e_vf *vf)
 305 {
 306         rte_wmb();
 307         vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
 308 }
 309
 310 /*
 311  * Check there is pending cmd in execution. If none, set new command.
 312  */
 313 static inline int
 314 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
 315 {
 316         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 317                         I40E_VIRTCHNL_OP_UNKNOWN, ops);
 318
 319         if (!ret)
 320                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 321
 322         return !ret;
 323 }
 324
 325 #define MAX_TRY_TIMES 200
 326 #define ASQ_DELAY_MS  10
 327
 328 static int
 329 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 330 {
 331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 332         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 333         struct i40evf_arq_msg_info info;
 334         enum i40evf_aq_result ret;
 335         int err, i = 0;
 336
 337         if (_atomic_set_cmd(vf, args->ops))
 338                 return -1;
 339
 340         info.msg = args->out_buffer;
 341         info.buf_len = args->out_size;
 342         info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
 343         info.result = I40E_SUCCESS;
 344
 345         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 346                      args->in_args, args->in_args_size, NULL);
 347         if (err) {
 348                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 349                 _clear_cmd(vf);
 350                 return err;
 351         }
 352
 353         switch (args->ops) {
 354         case I40E_VIRTCHNL_OP_RESET_VF:
 355                 /*no need to process in this function */
 356                 err = 0;
 357                 break;
 358         case I40E_VIRTCHNL_OP_VERSION:
 359         case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
 360                 /* for init adminq commands, need to poll the response */
 361                 err = -1;
 362                 do {
 363                         ret = i40evf_read_pfmsg(dev, &info);
 364                         if (ret == I40EVF_MSG_CMD) {
 365                                 err = 0;
 366                                 break;
 367                         } else if (ret == I40EVF_MSG_ERR)
 368                                 break;
 369                         rte_delay_ms(ASQ_DELAY_MS);
 370                         /* If don't read msg or read sys event, continue */
 371                 } while (i++ < MAX_TRY_TIMES);
 372                 _clear_cmd(vf);
 373                 break;
 374
 375         default:
 376                 /* for other adminq in running time, waiting the cmd done flag */
 377                 err = -1;
 378                 do {
 379                         if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
 380                                 err = 0;
 381                                 break;
 382                         }
 383                         rte_delay_ms(ASQ_DELAY_MS);
 384                         /* If don't read msg or read sys event, continue */
 385                 } while (i++ < MAX_TRY_TIMES);
 386                 break;
 387         }
 388
 389         return err | vf->cmd_retval;
 390 }
 391
 392 /*
 393  * Check API version with sync wait until version read or fail from admin queue
 394  */
 395 static int
 396 i40evf_check_api_version(struct rte_eth_dev *dev)
 397 {
 398         struct i40e_virtchnl_version_info version, *pver;
 399         int err;
 400         struct vf_cmd_info args;
 401         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 402
 403         version.major = I40E_VIRTCHNL_VERSION_MAJOR;
 404         version.minor = I40E_VIRTCHNL_VERSION_MINOR;
 405
 406         args.ops = I40E_VIRTCHNL_OP_VERSION;
 407         args.in_args = (uint8_t *)&version;
 408         args.in_args_size = sizeof(version);
 409         args.out_buffer = vf->aq_resp;
 410         args.out_size = I40E_AQ_BUF_SZ;
 411
 412         err = i40evf_execute_vf_cmd(dev, &args);
 413         if (err) {
 414                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 415                 return err;
 416         }
 417
 418         pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
 419         vf->version_major = pver->major;
 420         vf->version_minor = pver->minor;
 421         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 422                 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
 423         else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
 424                 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
 425                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 426         else {
 427                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 428                                         vf->version_major, vf->version_minor,
 429                                                 I40E_VIRTCHNL_VERSION_MAJOR,
 430                                                 I40E_VIRTCHNL_VERSION_MINOR);
 431                 return -1;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int
 438 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 439 {
 440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 441         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 442         int err;
 443         struct vf_cmd_info args;
 444         uint32_t caps, len;
 445
 446         args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
 447         args.out_buffer = vf->aq_resp;
 448         args.out_size = I40E_AQ_BUF_SZ;
 449         if (PF_IS_V11(vf)) {
 450                 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
 451                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 452                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
 453                        I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
 454                        I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 455                 args.in_args = (uint8_t *)&caps;
 456                 args.in_args_size = sizeof(caps);
 457         } else {
 458                 args.in_args = NULL;
 459                 args.in_args_size = 0;
 460         }
 461         err = i40evf_execute_vf_cmd(dev, &args);
 462
 463         if (err) {
 464                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 465                 return err;
 466         }
 467
 468         len =  sizeof(struct i40e_virtchnl_vf_resource) +
 469                 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
 470
 471         (void)rte_memcpy(vf->vf_res, args.out_buffer,
 472                         RTE_MIN(args.out_size, len));
 473         i40e_vf_parse_hw_config(hw, vf->vf_res);
 474
 475         return 0;
 476 }
 477
 478 static int
 479 i40evf_config_promisc(struct rte_eth_dev *dev,
 480                       bool enable_unicast,
 481                       bool enable_multicast)
 482 {
 483         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 484         int err;
 485         struct vf_cmd_info args;
 486         struct i40e_virtchnl_promisc_info promisc;
 487
 488         promisc.flags = 0;
 489         promisc.vsi_id = vf->vsi_res->vsi_id;
 490
 491         if (enable_unicast)
 492                 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
 493
 494         if (enable_multicast)
 495                 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
 496
 497         args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 498         args.in_args = (uint8_t *)&promisc;
 499         args.in_args_size = sizeof(promisc);
 500         args.out_buffer = vf->aq_resp;
 501         args.out_size = I40E_AQ_BUF_SZ;
 502
 503         err = i40evf_execute_vf_cmd(dev, &args);
 504
 505         if (err)
 506                 PMD_DRV_LOG(ERR, "fail to execute command "
 507                             "CONFIG_PROMISCUOUS_MODE");
 508         return err;
 509 }
 510
 511 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
 512 static int
 513 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
 514                                 bool enable_vlan_strip)
 515 {
 516         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 517         int err;
 518         struct vf_cmd_info args;
 519         struct i40e_virtchnl_vlan_offload_info offload;
 520
 521         offload.vsi_id = vf->vsi_res->vsi_id;
 522         offload.enable_vlan_strip = enable_vlan_strip;
 523
 524         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
 525         args.in_args = (uint8_t *)&offload;
 526         args.in_args_size = sizeof(offload);
 527         args.out_buffer = vf->aq_resp;
 528         args.out_size = I40E_AQ_BUF_SZ;
 529
 530         err = i40evf_execute_vf_cmd(dev, &args);
 531         if (err)
 532                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
 533
 534         return err;
 535 }
 536
 537 static int
 538 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
 539                                 struct i40e_vsi_vlan_pvid_info *info)
 540 {
 541         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 542         int err;
 543         struct vf_cmd_info args;
 544         struct i40e_virtchnl_pvid_info tpid_info;
 545
 546         if (info == NULL) {
 547                 PMD_DRV_LOG(ERR, "invalid parameters");
 548                 return I40E_ERR_PARAM;
 549         }
 550
 551         memset(&tpid_info, 0, sizeof(tpid_info));
 552         tpid_info.vsi_id = vf->vsi_res->vsi_id;
 553         (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
 554
 555         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
 556         args.in_args = (uint8_t *)&tpid_info;
 557         args.in_args_size = sizeof(tpid_info);
 558         args.out_buffer = vf->aq_resp;
 559         args.out_size = I40E_AQ_BUF_SZ;
 560
 561         err = i40evf_execute_vf_cmd(dev, &args);
 562         if (err)
 563                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
 564
 565         return err;
 566 }
 567
 568 static void
 569 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
 570                                   uint16_t vsi_id,
 571                                   uint16_t queue_id,
 572                                   uint16_t nb_txq,
 573                                   struct i40e_tx_queue *txq)
 574 {
 575         txq_info->vsi_id = vsi_id;
 576         txq_info->queue_id = queue_id;
 577         if (queue_id < nb_txq) {
 578                 txq_info->ring_len = txq->nb_tx_desc;
 579                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 580         }
 581 }
 582
 583 static void
 584 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
 585                                   uint16_t vsi_id,
 586                                   uint16_t queue_id,
 587                                   uint16_t nb_rxq,
 588                                   uint32_t max_pkt_size,
 589                                   struct i40e_rx_queue *rxq)
 590 {
 591         rxq_info->vsi_id = vsi_id;
 592         rxq_info->queue_id = queue_id;
 593         rxq_info->max_pkt_size = max_pkt_size;
 594         if (queue_id < nb_rxq) {
 595                 rxq_info->ring_len = rxq->nb_rx_desc;
 596                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 597                 rxq_info->databuffer_size =
 598                         (rte_pktmbuf_data_room_size(rxq->mp) -
 599                                 RTE_PKTMBUF_HEADROOM);
 600         }
 601 }
 602
 603 /* It configures VSI queues to co-work with Linux PF host */
 604 static int
 605 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 606 {
 607         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 608         struct i40e_rx_queue **rxq =
 609                 (struct i40e_rx_queue **)dev->data->rx_queues;
 610         struct i40e_tx_queue **txq =
 611                 (struct i40e_tx_queue **)dev->data->tx_queues;
 612         struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
 613         struct i40e_virtchnl_queue_pair_info *vc_qpi;
 614         struct vf_cmd_info args;
 615         uint16_t i, nb_qp = vf->num_queue_pairs;
 616         const uint32_t size =
 617                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 618         uint8_t buff[size];
 619         int ret;
 620
 621         memset(buff, 0, sizeof(buff));
 622         vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
 623         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 624         vc_vqci->num_queue_pairs = nb_qp;
 625
 626         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 627                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 628                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 629                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 630                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 631                                         vf->max_pkt_len, rxq[i]);
 632         }
 633         memset(&args, 0, sizeof(args));
 634         args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 635         args.in_args = (uint8_t *)vc_vqci;
 636         args.in_args_size = size;
 637         args.out_buffer = vf->aq_resp;
 638         args.out_size = I40E_AQ_BUF_SZ;
 639         ret = i40evf_execute_vf_cmd(dev, &args);
 640         if (ret)
 641                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 642                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
 643
 644         return ret;
 645 }
 646
 647 /* It configures VSI queues to co-work with DPDK PF host */
 648 static int
 649 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
 650 {
 651         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 652         struct i40e_rx_queue **rxq =
 653                 (struct i40e_rx_queue **)dev->data->rx_queues;
 654         struct i40e_tx_queue **txq =
 655                 (struct i40e_tx_queue **)dev->data->tx_queues;
 656         struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
 657         struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
 658         struct vf_cmd_info args;
 659         uint16_t i, nb_qp = vf->num_queue_pairs;
 660         const uint32_t size =
 661                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
 662         uint8_t buff[size];
 663         int ret;
 664
 665         memset(buff, 0, sizeof(buff));
 666         vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
 667         vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
 668         vc_vqcei->num_queue_pairs = nb_qp;
 669         vc_qpei = vc_vqcei->qpair;
 670         for (i = 0; i < nb_qp; i++, vc_qpei++) {
 671                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
 672                         vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 673                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
 674                         vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
 675                                         vf->max_pkt_len, rxq[i]);
 676                 if (i < dev->data->nb_rx_queues)
 677                         /*
 678                          * It adds extra info for configuring VSI queues, which
 679                          * is needed to enable the configurable crc stripping
 680                          * in VF.
 681                          */
 682                         vc_qpei->rxq_ext.crcstrip =
 683                                 dev->data->dev_conf.rxmode.hw_strip_crc;
 684         }
 685         memset(&args, 0, sizeof(args));
 686         args.ops =
 687                 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
 688         args.in_args = (uint8_t *)vc_vqcei;
 689         args.in_args_size = size;
 690         args.out_buffer = vf->aq_resp;
 691         args.out_size = I40E_AQ_BUF_SZ;
 692         ret = i40evf_execute_vf_cmd(dev, &args);
 693         if (ret)
 694                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 695                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
 696
 697         return ret;
 698 }
 699
 700 static int
 701 i40evf_configure_queues(struct rte_eth_dev *dev)
 702 {
 703         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 704
 705         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 706                 /* To support DPDK PF host */
 707                 return i40evf_configure_vsi_queues_ext(dev);
 708         else
 709                 /* To support Linux PF host */
 710                 return i40evf_configure_vsi_queues(dev);
 711 }
 712
 713 static int
 714 i40evf_config_irq_map(struct rte_eth_dev *dev)
 715 {
 716         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 717         struct vf_cmd_info args;
 718         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
 719                 sizeof(struct i40e_virtchnl_vector_map)];
 720         struct i40e_virtchnl_irq_map_info *map_info;
 721         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 722         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 723         uint32_t vector_id;
 724         int i, err;
 725
 726         if (rte_intr_allow_others(intr_handle)) {
 727                 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 728                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
 729                 else
 730                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 731         } else {
 732                 vector_id = I40E_MISC_VEC_ID;
 733         }
 734
 735         map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
 736         map_info->num_vectors = 1;
 737         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 738         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 739         /* Alway use default dynamic MSIX interrupt */
 740         map_info->vecmap[0].vector_id = vector_id;
 741         /* Don't map any tx queue */
 742         map_info->vecmap[0].txq_map = 0;
 743         map_info->vecmap[0].rxq_map = 0;
 744         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 745                 map_info->vecmap[0].rxq_map |= 1 << i;
 746                 if (rte_intr_dp_is_en(intr_handle))
 747                         intr_handle->intr_vec[i] = vector_id;
 748         }
 749
 750         args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
 751         args.in_args = (u8 *)cmd_buffer;
 752         args.in_args_size = sizeof(cmd_buffer);
 753         args.out_buffer = vf->aq_resp;
 754         args.out_size = I40E_AQ_BUF_SZ;
 755         err = i40evf_execute_vf_cmd(dev, &args);
 756         if (err)
 757                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 758
 759         return err;
 760 }
 761
 762 static int
 763 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 764                                 bool on)
 765 {
 766         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 767         struct i40e_virtchnl_queue_select queue_select;
 768         int err;
 769         struct vf_cmd_info args;
 770         memset(&queue_select, 0, sizeof(queue_select));
 771         queue_select.vsi_id = vf->vsi_res->vsi_id;
 772
 773         if (isrx)
 774                 queue_select.rx_queues |= 1 << qid;
 775         else
 776                 queue_select.tx_queues |= 1 << qid;
 777
 778         if (on)
 779                 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
 780         else
 781                 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
 782         args.in_args = (u8 *)&queue_select;
 783         args.in_args_size = sizeof(queue_select);
 784         args.out_buffer = vf->aq_resp;
 785         args.out_size = I40E_AQ_BUF_SZ;
 786         err = i40evf_execute_vf_cmd(dev, &args);
 787         if (err)
 788                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 789                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 790
 791         return err;
 792 }
 793
 794 static int
 795 i40evf_start_queues(struct rte_eth_dev *dev)
 796 {
 797         struct rte_eth_dev_data *dev_data = dev->data;
 798         int i;
 799         struct i40e_rx_queue *rxq;
 800         struct i40e_tx_queue *txq;
 801
 802         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 803                 rxq = dev_data->rx_queues[i];
 804                 if (rxq->rx_deferred_start)
 805                         continue;
 806                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 807                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 808                         return -1;
 809                 }
 810         }
 811
 812         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 813                 txq = dev_data->tx_queues[i];
 814                 if (txq->tx_deferred_start)
 815                         continue;
 816                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 817                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 818                         return -1;
 819                 }
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int
 826 i40evf_stop_queues(struct rte_eth_dev *dev)
 827 {
 828         int i;
 829
 830         /* Stop TX queues first */
 831         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 832                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 833                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 834                         return -1;
 835                 }
 836         }
 837
 838         /* Then stop RX queues */
 839         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 840                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 841                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 842                         return -1;
 843                 }
 844         }
 845
 846         return 0;
 847 }
 848
 849 static void
 850 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 851                     struct ether_addr *addr,
 852                     __rte_unused uint32_t index,
 853                     __rte_unused uint32_t pool)
 854 {
 855         struct i40e_virtchnl_ether_addr_list *list;
 856         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 857         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 858                         sizeof(struct i40e_virtchnl_ether_addr)];
 859         int err;
 860         struct vf_cmd_info args;
 861
 862         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 863                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 864                             addr->addr_bytes[0], addr->addr_bytes[1],
 865                             addr->addr_bytes[2], addr->addr_bytes[3],
 866                             addr->addr_bytes[4], addr->addr_bytes[5]);
 867                 return;
 868         }
 869
 870         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 871         list->vsi_id = vf->vsi_res->vsi_id;
 872         list->num_elements = 1;
 873         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 874                                         sizeof(addr->addr_bytes));
 875
 876         args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
 877         args.in_args = cmd_buffer;
 878         args.in_args_size = sizeof(cmd_buffer);
 879         args.out_buffer = vf->aq_resp;
 880         args.out_size = I40E_AQ_BUF_SZ;
 881         err = i40evf_execute_vf_cmd(dev, &args);
 882         if (err)
 883                 PMD_DRV_LOG(ERR, "fail to execute command "
 884                             "OP_ADD_ETHER_ADDRESS");
 885
 886         return;
 887 }
 888
 889 static void
 890 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 891 {
 892         struct i40e_virtchnl_ether_addr_list *list;
 893         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 894         struct rte_eth_dev_data *data = dev->data;
 895         struct ether_addr *addr;
 896         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 897                         sizeof(struct i40e_virtchnl_ether_addr)];
 898         int err;
 899         struct vf_cmd_info args;
 900
 901         addr = &(data->mac_addrs[index]);
 902
 903         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 904                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 905                             addr->addr_bytes[0], addr->addr_bytes[1],
 906                             addr->addr_bytes[2], addr->addr_bytes[3],
 907                             addr->addr_bytes[4], addr->addr_bytes[5]);
 908                 return;
 909         }
 910
 911         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 912         list->vsi_id = vf->vsi_res->vsi_id;
 913         list->num_elements = 1;
 914         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 915                         sizeof(addr->addr_bytes));
 916
 917         args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
 918         args.in_args = cmd_buffer;
 919         args.in_args_size = sizeof(cmd_buffer);
 920         args.out_buffer = vf->aq_resp;
 921         args.out_size = I40E_AQ_BUF_SZ;
 922         err = i40evf_execute_vf_cmd(dev, &args);
 923         if (err)
 924                 PMD_DRV_LOG(ERR, "fail to execute command "
 925                             "OP_DEL_ETHER_ADDRESS");
 926         return;
 927 }
 928
 929 static int
 930 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 931 {
 932         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 933         struct i40e_virtchnl_queue_select q_stats;
 934         int err;
 935         struct vf_cmd_info args;
 936
 937         memset(&q_stats, 0, sizeof(q_stats));
 938         q_stats.vsi_id = vf->vsi_res->vsi_id;
 939         args.ops = I40E_VIRTCHNL_OP_GET_STATS;
 940         args.in_args = (u8 *)&q_stats;
 941         args.in_args_size = sizeof(q_stats);
 942         args.out_buffer = vf->aq_resp;
 943         args.out_size = I40E_AQ_BUF_SZ;
 944
 945         err = i40evf_execute_vf_cmd(dev, &args);
 946         if (err) {
 947                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 948                 *pstats = NULL;
 949                 return err;
 950         }
 951         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 952         return 0;
 953 }
 954
 955 static int
 956 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 957 {
 958         int ret;
 959         struct i40e_eth_stats *pstats = NULL;
 960
 961         ret = i40evf_update_stats(dev, &pstats);
 962         if (ret != 0)
 963                 return 0;
 964
 965         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 966                                                 pstats->rx_broadcast;
 967         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 968                                                 pstats->tx_unicast;
 969         stats->ierrors = pstats->rx_discards;
 970         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 971         stats->ibytes = pstats->rx_bytes;
 972         stats->obytes = pstats->tx_bytes;
 973
 974         return 0;
 975 }
 976
 977 static void
 978 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 979 {
 980         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 981         struct i40e_eth_stats *pstats = NULL;
 982
 983         /* read stat values to clear hardware registers */
 984         i40evf_update_stats(dev, &pstats);
 985
 986         /* set stats offset base on current values */
 987         vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
 988 }
 989
 990 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 991                                       struct rte_eth_xstat_name *xstats_names,
 992                                       __rte_unused unsigned limit)
 993 {
 994         unsigned i;
 995
 996         if (xstats_names != NULL)
 997                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 998                         snprintf(xstats_names[i].name,
 999                                 sizeof(xstats_names[i].name),
1000                                 "%s", rte_i40evf_stats_strings[i].name);
1001                 }
1002         return I40EVF_NB_XSTATS;
1003 }
1004
1005 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1006                                  struct rte_eth_xstat *xstats, unsigned n)
1007 {
1008         int ret;
1009         unsigned i;
1010         struct i40e_eth_stats *pstats = NULL;
1011
1012         if (n < I40EVF_NB_XSTATS)
1013                 return I40EVF_NB_XSTATS;
1014
1015         ret = i40evf_update_stats(dev, &pstats);
1016         if (ret != 0)
1017                 return 0;
1018
1019         if (!xstats)
1020                 return 0;
1021
1022         /* loop over xstats array and values from pstats */
1023         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1024                 xstats[i].id = i;
1025                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1026                         rte_i40evf_stats_strings[i].offset);
1027         }
1028
1029         return I40EVF_NB_XSTATS;
1030 }
1031
1032 static int
1033 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1034 {
1035         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1036         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1037         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1038                                                         sizeof(uint16_t)];
1039         int err;
1040         struct vf_cmd_info args;
1041
1042         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1043         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1044         vlan_list->num_elements = 1;
1045         vlan_list->vlan_id[0] = vlanid;
1046
1047         args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1048         args.in_args = (u8 *)&cmd_buffer;
1049         args.in_args_size = sizeof(cmd_buffer);
1050         args.out_buffer = vf->aq_resp;
1051         args.out_size = I40E_AQ_BUF_SZ;
1052         err = i40evf_execute_vf_cmd(dev, &args);
1053         if (err)
1054                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1055
1056         return err;
1057 }
1058
1059 static int
1060 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1061 {
1062         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1063         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1064         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1065                                                         sizeof(uint16_t)];
1066         int err;
1067         struct vf_cmd_info args;
1068
1069         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1070         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1071         vlan_list->num_elements = 1;
1072         vlan_list->vlan_id[0] = vlanid;
1073
1074         args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1075         args.in_args = (u8 *)&cmd_buffer;
1076         args.in_args_size = sizeof(cmd_buffer);
1077         args.out_buffer = vf->aq_resp;
1078         args.out_size = I40E_AQ_BUF_SZ;
1079         err = i40evf_execute_vf_cmd(dev, &args);
1080         if (err)
1081                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1082
1083         return err;
1084 }
1085
1086 static const struct rte_pci_id pci_id_i40evf_map[] = {
1087         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1088         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1089         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1090         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1091         { .vendor_id = 0, /* sentinel */ },
1092 };
1093
1094 static inline int
1095 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1096                                     struct rte_eth_link *link)
1097 {
1098         struct rte_eth_link *dst = &(dev->data->dev_link);
1099         struct rte_eth_link *src = link;
1100
1101         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1102                                         *(uint64_t *)src) == 0)
1103                 return -1;
1104
1105         return 0;
1106 }
1107
1108 /* Disable IRQ0 */
1109 static inline void
1110 i40evf_disable_irq0(struct i40e_hw *hw)
1111 {
1112         /* Disable all interrupt types */
1113         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1114         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1115                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1116         I40EVF_WRITE_FLUSH(hw);
1117 }
1118
1119 /* Enable IRQ0 */
1120 static inline void
1121 i40evf_enable_irq0(struct i40e_hw *hw)
1122 {
1123         /* Enable admin queue interrupt trigger */
1124         uint32_t val;
1125
1126         i40evf_disable_irq0(hw);
1127         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1128         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1129                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1130         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1131
1132         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1133                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1134                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1135                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1136
1137         I40EVF_WRITE_FLUSH(hw);
1138 }
1139
1140 static int
1141 i40evf_reset_vf(struct i40e_hw *hw)
1142 {
1143         int i, reset;
1144
1145         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1147                 return -1;
1148         }
1149         /**
1150           * After issuing vf reset command to pf, pf won't necessarily
1151           * reset vf, it depends on what state it exactly is. If it's not
1152           * initialized yet, it won't have vf reset since it's in a certain
1153           * state. If not, it will try to reset. Even vf is reset, pf will
1154           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1155           * it to ACTIVE. In this duration, vf may not catch the moment that
1156           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1157           */
1158         rte_delay_ms(200);
1159
1160         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1161                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1162                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1163                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1164                 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1165                         break;
1166                 else
1167                         rte_delay_ms(50);
1168         }
1169
1170         if (i >= MAX_RESET_WAIT_CNT) {
1171                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1172                 return -1;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int
1179 i40evf_init_vf(struct rte_eth_dev *dev)
1180 {
1181         int i, err, bufsz;
1182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1183         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1184         struct ether_addr *p_mac_addr;
1185         uint16_t interval =
1186                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1187
1188         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1189         vf->dev_data = dev->data;
1190         err = i40e_set_mac_type(hw);
1191         if (err) {
1192                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1193                 goto err;
1194         }
1195
1196         i40e_init_adminq_parameter(hw);
1197         err = i40e_init_adminq(hw);
1198         if (err) {
1199                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1200                 goto err;
1201         }
1202
1203         /* Reset VF and wait until it's complete */
1204         if (i40evf_reset_vf(hw)) {
1205                 PMD_INIT_LOG(ERR, "reset NIC failed");
1206                 goto err_aq;
1207         }
1208
1209         /* VF reset, shutdown admin queue and initialize again */
1210         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1211                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1212                 return -1;
1213         }
1214
1215         i40e_init_adminq_parameter(hw);
1216         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1217                 PMD_INIT_LOG(ERR, "init_adminq failed");
1218                 return -1;
1219         }
1220         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1221         if (!vf->aq_resp) {
1222                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1223                         goto err_aq;
1224         }
1225         if (i40evf_check_api_version(dev) != 0) {
1226                 PMD_INIT_LOG(ERR, "check_api version failed");
1227                 goto err_aq;
1228         }
1229         bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1230                 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1231         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1232         if (!vf->vf_res) {
1233                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1234                         goto err_aq;
1235         }
1236
1237         if (i40evf_get_vf_resource(dev) != 0) {
1238                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1239                 goto err_alloc;
1240         }
1241
1242         /* got VF config message back from PF, now we can parse it */
1243         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1244                 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1245                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1246         }
1247
1248         if (!vf->vsi_res) {
1249                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1250                 goto err_alloc;
1251         }
1252
1253         if (hw->mac.type == I40E_MAC_X722_VF)
1254                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1255         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1256         vf->vsi.type = vf->vsi_res->vsi_type;
1257         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1258         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1259
1260         /* Store the MAC address configured by host, or generate random one */
1261         p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1262         if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1263                 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1264         else
1265                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1266
1267         /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1268         if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1269                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1270                                (I40E_ITR_INDEX_DEFAULT <<
1271                                 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1272                                (interval <<
1273                                 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1274                 I40EVF_WRITE_FLUSH(hw);
1275         }
1276
1277         return 0;
1278
1279 err_alloc:
1280         rte_free(vf->vf_res);
1281 err_aq:
1282         i40e_shutdown_adminq(hw); /* ignore error */
1283 err:
1284         return -1;
1285 }
1286
1287 static int
1288 i40evf_uninit_vf(struct rte_eth_dev *dev)
1289 {
1290         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1291         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1292
1293         PMD_INIT_FUNC_TRACE();
1294
1295         if (hw->adapter_stopped == 0)
1296                 i40evf_dev_close(dev);
1297         rte_free(vf->vf_res);
1298         vf->vf_res = NULL;
1299         rte_free(vf->aq_resp);
1300         vf->aq_resp = NULL;
1301
1302         return 0;
1303 }
1304
1305 static void
1306 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1307                            uint8_t *msg,
1308                            __rte_unused uint16_t msglen)
1309 {
1310         struct i40e_virtchnl_pf_event *pf_msg =
1311                         (struct i40e_virtchnl_pf_event *)msg;
1312         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1313
1314         switch (pf_msg->event) {
1315         case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1316                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1317                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1318                 break;
1319         case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1320                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1321                 vf->link_up = pf_msg->event_data.link_event.link_status;
1322                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1323                 break;
1324         case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1325                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1326                 break;
1327         default:
1328                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1329                 break;
1330         }
1331 }
1332
1333 static void
1334 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1335 {
1336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1337         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1338         struct i40e_arq_event_info info;
1339         uint16_t pending, aq_opc;
1340         enum i40e_virtchnl_ops msg_opc;
1341         enum i40e_status_code msg_ret;
1342         int ret;
1343
1344         info.buf_len = I40E_AQ_BUF_SZ;
1345         if (!vf->aq_resp) {
1346                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1347                 return;
1348         }
1349         info.msg_buf = vf->aq_resp;
1350
1351         pending = 1;
1352         while (pending) {
1353                 ret = i40e_clean_arq_element(hw, &info, &pending);
1354
1355                 if (ret != I40E_SUCCESS) {
1356                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1357                                     "ret: %d", ret);
1358                         break;
1359                 }
1360                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1361                 /* For the message sent from pf to vf, opcode is stored in
1362                  * cookie_high of struct i40e_aq_desc, while return error code
1363                  * are stored in cookie_low, Which is done by
1364                  * i40e_aq_send_msg_to_vf in PF driver.*/
1365                 msg_opc = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(
1366                                                   info.desc.cookie_high);
1367                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1368                                                   info.desc.cookie_low);
1369                 switch (aq_opc) {
1370                 case i40e_aqc_opc_send_msg_to_vf:
1371                         if (msg_opc == I40E_VIRTCHNL_OP_EVENT)
1372                                 /* process event*/
1373                                 i40evf_handle_pf_event(dev, info.msg_buf,
1374                                                        info.msg_len);
1375                         else {
1376                                 /* read message and it's expected one */
1377                                 if (msg_opc == vf->pend_cmd) {
1378                                         vf->cmd_retval = msg_ret;
1379                                         /* prevent compiler reordering */
1380                                         rte_compiler_barrier();
1381                                         _clear_cmd(vf);
1382                                 } else
1383                                         PMD_DRV_LOG(ERR, "command mismatch,"
1384                                                 "expect %u, get %u",
1385                                                 vf->pend_cmd, msg_opc);
1386                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1387                                              " opcode = %d\n", msg_opc);
1388                         }
1389                         break;
1390                 default:
1391                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1392                                     aq_opc);
1393                         break;
1394                 }
1395         }
1396 }
1397
1398 /**
1399  * Interrupt handler triggered by NIC  for handling
1400  * specific interrupt. Only adminq interrupt is processed in VF.
1401  *
1402  * @param handle
1403  *  Pointer to interrupt handle.
1404  * @param param
1405  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1406  *
1407  * @return
1408  *  void
1409  */
1410 static void
1411 i40evf_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
1412                              void *param)
1413 {
1414         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1416         uint32_t icr0;
1417
1418         i40evf_disable_irq0(hw);
1419
1420         /* read out interrupt causes */
1421         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1422
1423         /* No interrupt event indicated */
1424         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1425                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1426                 goto done;
1427         }
1428
1429         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1430                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1431                 i40evf_handle_aq_msg(dev);
1432         }
1433
1434         /* Link Status Change interrupt */
1435         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1436                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1437                                    " do nothing\n");
1438
1439 done:
1440         i40evf_enable_irq0(hw);
1441         rte_intr_enable(intr_handle);
1442 }
1443
1444 static int
1445 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1446 {
1447         struct i40e_hw *hw
1448                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1449         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(eth_dev);
1450
1451         PMD_INIT_FUNC_TRACE();
1452
1453         /* assign ops func pointer */
1454         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1455         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1456         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1457
1458         /*
1459          * For secondary processes, we don't initialise any further as primary
1460          * has already done this work.
1461          */
1462         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1463                 i40e_set_rx_function(eth_dev);
1464                 i40e_set_tx_function(eth_dev);
1465                 return 0;
1466         }
1467
1468         rte_eth_copy_pci_info(eth_dev, pci_dev);
1469         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1470
1471         hw->vendor_id = pci_dev->id.vendor_id;
1472         hw->device_id = pci_dev->id.device_id;
1473         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1474         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1475         hw->bus.device = pci_dev->addr.devid;
1476         hw->bus.func = pci_dev->addr.function;
1477         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1478         hw->adapter_stopped = 0;
1479
1480         if(i40evf_init_vf(eth_dev) != 0) {
1481                 PMD_INIT_LOG(ERR, "Init vf failed");
1482                 return -1;
1483         }
1484
1485         /* register callback func to eal lib */
1486         rte_intr_callback_register(&pci_dev->intr_handle,
1487                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1488
1489         /* enable uio intr after callback register */
1490         rte_intr_enable(&pci_dev->intr_handle);
1491
1492         /* configure and enable device interrupt */
1493         i40evf_enable_irq0(hw);
1494
1495         /* copy mac addr */
1496         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1497                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1498                                         0);
1499         if (eth_dev->data->mac_addrs == NULL) {
1500                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1501                                 " store MAC addresses",
1502                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1503                 return -ENOMEM;
1504         }
1505         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1506                         &eth_dev->data->mac_addrs[0]);
1507
1508         return 0;
1509 }
1510
1511 static int
1512 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1513 {
1514         PMD_INIT_FUNC_TRACE();
1515
1516         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1517                 return -EPERM;
1518
1519         eth_dev->dev_ops = NULL;
1520         eth_dev->rx_pkt_burst = NULL;
1521         eth_dev->tx_pkt_burst = NULL;
1522
1523         if (i40evf_uninit_vf(eth_dev) != 0) {
1524                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1525                 return -1;
1526         }
1527
1528         rte_free(eth_dev->data->mac_addrs);
1529         eth_dev->data->mac_addrs = NULL;
1530
1531         return 0;
1532 }
1533 /*
1534  * virtual function driver struct
1535  */
1536 static struct eth_driver rte_i40evf_pmd = {
1537         .pci_drv = {
1538                 .id_table = pci_id_i40evf_map,
1539                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1540                 .probe = rte_eth_dev_pci_probe,
1541                 .remove = rte_eth_dev_pci_remove,
1542         },
1543         .eth_dev_init = i40evf_dev_init,
1544         .eth_dev_uninit = i40evf_dev_uninit,
1545         .dev_private_size = sizeof(struct i40e_adapter),
1546 };
1547
1548 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv);
1549 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1550 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio");
1551
1552 static int
1553 i40evf_dev_configure(struct rte_eth_dev *dev)
1554 {
1555         struct i40e_adapter *ad =
1556                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1557         struct rte_eth_conf *conf = &dev->data->dev_conf;
1558         struct i40e_vf *vf;
1559
1560         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1561          * allocation or vector Rx preconditions we will reset it.
1562          */
1563         ad->rx_bulk_alloc_allowed = true;
1564         ad->rx_vec_allowed = true;
1565         ad->tx_simple_allowed = true;
1566         ad->tx_vec_allowed = true;
1567
1568         /* For non-DPDK PF drivers, VF has no ability to disable HW
1569          * CRC strip, and is implicitly enabled by the PF.
1570          */
1571         if (!conf->rxmode.hw_strip_crc) {
1572                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1573                 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1574                     (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1575                         /* Peer is running non-DPDK PF driver. */
1576                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1577                         return -EINVAL;
1578                 }
1579         }
1580
1581         return i40evf_init_vlan(dev);
1582 }
1583
1584 static int
1585 i40evf_init_vlan(struct rte_eth_dev *dev)
1586 {
1587         struct rte_eth_dev_data *data = dev->data;
1588         int ret;
1589
1590         /* Apply vlan offload setting */
1591         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1592
1593         /* Apply pvid setting */
1594         ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1595                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
1596         return ret;
1597 }
1598
1599 static void
1600 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1601 {
1602         bool enable_vlan_strip = 0;
1603         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1604         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1605
1606         /* Linux pf host doesn't support vlan offload yet */
1607         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1608                 /* Vlan stripping setting */
1609                 if (mask & ETH_VLAN_STRIP_MASK) {
1610                         /* Enable or disable VLAN stripping */
1611                         if (dev_conf->rxmode.hw_vlan_strip)
1612                                 enable_vlan_strip = 1;
1613                         else
1614                                 enable_vlan_strip = 0;
1615
1616                         i40evf_config_vlan_offload(dev, enable_vlan_strip);
1617                 }
1618         }
1619 }
1620
1621 static int
1622 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1623 {
1624         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1625         struct i40e_vsi_vlan_pvid_info info;
1626         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1627
1628         memset(&info, 0, sizeof(info));
1629         info.on = on;
1630
1631         /* Linux pf host don't support vlan offload yet */
1632         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1633                 if (info.on)
1634                         info.config.pvid = pvid;
1635                 else {
1636                         info.config.reject.tagged =
1637                                 dev_conf->txmode.hw_vlan_reject_tagged;
1638                         info.config.reject.untagged =
1639                                 dev_conf->txmode.hw_vlan_reject_untagged;
1640                 }
1641                 return i40evf_config_vlan_pvid(dev, &info);
1642         }
1643
1644         return 0;
1645 }
1646
1647 static int
1648 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1649 {
1650         struct i40e_rx_queue *rxq;
1651         int err = 0;
1652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653
1654         PMD_INIT_FUNC_TRACE();
1655
1656         if (rx_queue_id < dev->data->nb_rx_queues) {
1657                 rxq = dev->data->rx_queues[rx_queue_id];
1658
1659                 err = i40e_alloc_rx_queue_mbufs(rxq);
1660                 if (err) {
1661                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1662                         return err;
1663                 }
1664
1665                 rte_wmb();
1666
1667                 /* Init the RX tail register. */
1668                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1669                 I40EVF_WRITE_FLUSH(hw);
1670
1671                 /* Ready to switch the queue on */
1672                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1673
1674                 if (err)
1675                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1676                                     rx_queue_id);
1677                 else
1678                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1679         }
1680
1681         return err;
1682 }
1683
1684 static int
1685 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1686 {
1687         struct i40e_rx_queue *rxq;
1688         int err;
1689
1690         if (rx_queue_id < dev->data->nb_rx_queues) {
1691                 rxq = dev->data->rx_queues[rx_queue_id];
1692
1693                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1694
1695                 if (err) {
1696                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1697                                     rx_queue_id);
1698                         return err;
1699                 }
1700
1701                 i40e_rx_queue_release_mbufs(rxq);
1702                 i40e_reset_rx_queue(rxq);
1703                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1704         }
1705
1706         return 0;
1707 }
1708
1709 static int
1710 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1711 {
1712         int err = 0;
1713
1714         PMD_INIT_FUNC_TRACE();
1715
1716         if (tx_queue_id < dev->data->nb_tx_queues) {
1717
1718                 /* Ready to switch the queue on */
1719                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1720
1721                 if (err)
1722                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1723                                     tx_queue_id);
1724                 else
1725                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1726         }
1727
1728         return err;
1729 }
1730
1731 static int
1732 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1733 {
1734         struct i40e_tx_queue *txq;
1735         int err;
1736
1737         if (tx_queue_id < dev->data->nb_tx_queues) {
1738                 txq = dev->data->tx_queues[tx_queue_id];
1739
1740                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1741
1742                 if (err) {
1743                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1744                                     tx_queue_id);
1745                         return err;
1746                 }
1747
1748                 i40e_tx_queue_release_mbufs(txq);
1749                 i40e_reset_tx_queue(txq);
1750                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1751         }
1752
1753         return 0;
1754 }
1755
1756 static int
1757 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1758 {
1759         int ret;
1760
1761         if (on)
1762                 ret = i40evf_add_vlan(dev, vlan_id);
1763         else
1764                 ret = i40evf_del_vlan(dev,vlan_id);
1765
1766         return ret;
1767 }
1768
1769 static int
1770 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1771 {
1772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773         struct rte_eth_dev_data *dev_data = dev->data;
1774         struct rte_pktmbuf_pool_private *mbp_priv;
1775         uint16_t buf_size, len;
1776
1777         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1778         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1779         I40EVF_WRITE_FLUSH(hw);
1780
1781         /* Calculate the maximum packet length allowed */
1782         mbp_priv = rte_mempool_get_priv(rxq->mp);
1783         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1784                                         RTE_PKTMBUF_HEADROOM);
1785         rxq->hs_mode = i40e_header_split_none;
1786         rxq->rx_hdr_len = 0;
1787         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1788         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1789         rxq->max_pkt_len = RTE_MIN(len,
1790                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1791
1792         /**
1793          * Check if the jumbo frame and maximum packet length are set correctly
1794          */
1795         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1796                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1797                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1798                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1799                                 "larger than %u and smaller than %u, as jumbo "
1800                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1801                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1802                         return I40E_ERR_CONFIG;
1803                 }
1804         } else {
1805                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1806                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1807                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1808                                 "larger than %u and smaller than %u, as jumbo "
1809                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1810                                                 (uint32_t)ETHER_MAX_LEN);
1811                         return I40E_ERR_CONFIG;
1812                 }
1813         }
1814
1815         if (dev_data->dev_conf.rxmode.enable_scatter ||
1816             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1817                 dev_data->scattered_rx = 1;
1818         }
1819
1820         return 0;
1821 }
1822
1823 static int
1824 i40evf_rx_init(struct rte_eth_dev *dev)
1825 {
1826         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1827         uint16_t i;
1828         int ret = I40E_SUCCESS;
1829         struct i40e_rx_queue **rxq =
1830                 (struct i40e_rx_queue **)dev->data->rx_queues;
1831
1832         i40evf_config_rss(vf);
1833         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1834                 if (!rxq[i] || !rxq[i]->q_set)
1835                         continue;
1836                 ret = i40evf_rxq_init(dev, rxq[i]);
1837                 if (ret != I40E_SUCCESS)
1838                         break;
1839         }
1840         if (ret == I40E_SUCCESS)
1841                 i40e_set_rx_function(dev);
1842
1843         return ret;
1844 }
1845
1846 static void
1847 i40evf_tx_init(struct rte_eth_dev *dev)
1848 {
1849         uint16_t i;
1850         struct i40e_tx_queue **txq =
1851                 (struct i40e_tx_queue **)dev->data->tx_queues;
1852         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853
1854         for (i = 0; i < dev->data->nb_tx_queues; i++)
1855                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1856
1857         i40e_set_tx_function(dev);
1858 }
1859
1860 static inline void
1861 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1862 {
1863         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1866         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1867
1868         if (!rte_intr_allow_others(intr_handle)) {
1869                 I40E_WRITE_REG(hw,
1870                                I40E_VFINT_DYN_CTL01,
1871                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1872                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1873                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1874                 I40EVF_WRITE_FLUSH(hw);
1875                 return;
1876         }
1877
1878         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1879                 /* To support DPDK PF host */
1880                 I40E_WRITE_REG(hw,
1881                         I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1882                         I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1883                         I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1884         /* If host driver is kernel driver, do nothing.
1885          * Interrupt 0 is used for rx packets, but don't set
1886          * I40E_VFINT_DYN_CTL01,
1887          * because it is already done in i40evf_enable_irq0.
1888          */
1889
1890         I40EVF_WRITE_FLUSH(hw);
1891 }
1892
1893 static inline void
1894 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1895 {
1896         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1899         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1900
1901         if (!rte_intr_allow_others(intr_handle)) {
1902                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1903                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1904                 I40EVF_WRITE_FLUSH(hw);
1905                 return;
1906         }
1907
1908         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1909                 I40E_WRITE_REG(hw,
1910                                I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1911                                                     - 1),
1912                                0);
1913         /* If host driver is kernel driver, do nothing.
1914          * Interrupt 0 is used for rx packets, but don't zero
1915          * I40E_VFINT_DYN_CTL01,
1916          * because interrupt 0 is also used for adminq processing.
1917          */
1918
1919         I40EVF_WRITE_FLUSH(hw);
1920 }
1921
1922 static int
1923 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1924 {
1925         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1926         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         uint16_t interval =
1929                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1930         uint16_t msix_intr;
1931
1932         msix_intr = intr_handle->intr_vec[queue_id];
1933         if (msix_intr == I40E_MISC_VEC_ID)
1934                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1935                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1936                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1937                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1938                                (interval <<
1939                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1940         else
1941                 I40E_WRITE_REG(hw,
1942                                I40E_VFINT_DYN_CTLN1(msix_intr -
1943                                                     I40E_RX_VEC_START),
1944                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1945                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1946                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1947                                (interval <<
1948                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1949
1950         I40EVF_WRITE_FLUSH(hw);
1951
1952         rte_intr_enable(&pci_dev->intr_handle);
1953
1954         return 0;
1955 }
1956
1957 static int
1958 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1959 {
1960         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1961         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1962         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963         uint16_t msix_intr;
1964
1965         msix_intr = intr_handle->intr_vec[queue_id];
1966         if (msix_intr == I40E_MISC_VEC_ID)
1967                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1968         else
1969                 I40E_WRITE_REG(hw,
1970                                I40E_VFINT_DYN_CTLN1(msix_intr -
1971                                                     I40E_RX_VEC_START),
1972                                0);
1973
1974         I40EVF_WRITE_FLUSH(hw);
1975
1976         return 0;
1977 }
1978
1979 static void
1980 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1981 {
1982         struct i40e_virtchnl_ether_addr_list *list;
1983         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1984         int err, i, j;
1985         int next_begin = 0;
1986         int begin = 0;
1987         uint32_t len;
1988         struct ether_addr *addr;
1989         struct vf_cmd_info args;
1990
1991         do {
1992                 j = 0;
1993                 len = sizeof(struct i40e_virtchnl_ether_addr_list);
1994                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1995                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1996                                 continue;
1997                         len += sizeof(struct i40e_virtchnl_ether_addr);
1998                         if (len >= I40E_AQ_BUF_SZ) {
1999                                 next_begin = i + 1;
2000                                 break;
2001                         }
2002                 }
2003
2004                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2005
2006                 for (i = begin; i < next_begin; i++) {
2007                         addr = &dev->data->mac_addrs[i];
2008                         if (is_zero_ether_addr(addr))
2009                                 continue;
2010                         (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2011                                          sizeof(addr->addr_bytes));
2012                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2013                                     addr->addr_bytes[0], addr->addr_bytes[1],
2014                                     addr->addr_bytes[2], addr->addr_bytes[3],
2015                                     addr->addr_bytes[4], addr->addr_bytes[5]);
2016                         j++;
2017                 }
2018                 list->vsi_id = vf->vsi_res->vsi_id;
2019                 list->num_elements = j;
2020                 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2021                            I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2022                 args.in_args = (uint8_t *)list;
2023                 args.in_args_size = len;
2024                 args.out_buffer = vf->aq_resp;
2025                 args.out_size = I40E_AQ_BUF_SZ;
2026                 err = i40evf_execute_vf_cmd(dev, &args);
2027                 if (err)
2028                         PMD_DRV_LOG(ERR, "fail to execute command %s",
2029                                     add ? "OP_ADD_ETHER_ADDRESS" :
2030                                     "OP_DEL_ETHER_ADDRESS");
2031                 rte_free(list);
2032                 begin = next_begin;
2033         } while (begin < I40E_NUM_MACADDR_MAX);
2034 }
2035
2036 static int
2037 i40evf_dev_start(struct rte_eth_dev *dev)
2038 {
2039         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2040         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2042         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2043         uint32_t intr_vector = 0;
2044
2045         PMD_INIT_FUNC_TRACE();
2046
2047         hw->adapter_stopped = 0;
2048
2049         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2050         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2051                                         dev->data->nb_tx_queues);
2052
2053         /* check and configure queue intr-vector mapping */
2054         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2055                 intr_vector = dev->data->nb_rx_queues;
2056                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2057                         return -1;
2058         }
2059
2060         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2061                 intr_handle->intr_vec =
2062                         rte_zmalloc("intr_vec",
2063                                     dev->data->nb_rx_queues * sizeof(int), 0);
2064                 if (!intr_handle->intr_vec) {
2065                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2066                                      " intr_vec\n", dev->data->nb_rx_queues);
2067                         return -ENOMEM;
2068                 }
2069         }
2070
2071         if (i40evf_rx_init(dev) != 0){
2072                 PMD_DRV_LOG(ERR, "failed to do RX init");
2073                 return -1;
2074         }
2075
2076         i40evf_tx_init(dev);
2077
2078         if (i40evf_configure_queues(dev) != 0) {
2079                 PMD_DRV_LOG(ERR, "configure queues failed");
2080                 goto err_queue;
2081         }
2082         if (i40evf_config_irq_map(dev)) {
2083                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2084                 goto err_queue;
2085         }
2086
2087         /* Set all mac addrs */
2088         i40evf_add_del_all_mac_addr(dev, TRUE);
2089
2090         if (i40evf_start_queues(dev) != 0) {
2091                 PMD_DRV_LOG(ERR, "enable queues failed");
2092                 goto err_mac;
2093         }
2094
2095         i40evf_enable_queues_intr(dev);
2096         return 0;
2097
2098 err_mac:
2099         i40evf_add_del_all_mac_addr(dev, FALSE);
2100 err_queue:
2101         return -1;
2102 }
2103
2104 static void
2105 i40evf_dev_stop(struct rte_eth_dev *dev)
2106 {
2107         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2108         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2109
2110         PMD_INIT_FUNC_TRACE();
2111
2112         i40evf_stop_queues(dev);
2113         i40evf_disable_queues_intr(dev);
2114         i40e_dev_clear_queues(dev);
2115
2116         /* Clean datapath event and queue/vec mapping */
2117         rte_intr_efd_disable(intr_handle);
2118         if (intr_handle->intr_vec) {
2119                 rte_free(intr_handle->intr_vec);
2120                 intr_handle->intr_vec = NULL;
2121         }
2122         /* remove all mac addrs */
2123         i40evf_add_del_all_mac_addr(dev, FALSE);
2124
2125 }
2126
2127 static int
2128 i40evf_dev_link_update(struct rte_eth_dev *dev,
2129                        __rte_unused int wait_to_complete)
2130 {
2131         struct rte_eth_link new_link;
2132         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2133         /*
2134          * DPDK pf host provide interfacet to acquire link status
2135          * while Linux driver does not
2136          */
2137
2138         /* Linux driver PF host */
2139         switch (vf->link_speed) {
2140         case I40E_LINK_SPEED_100MB:
2141                 new_link.link_speed = ETH_SPEED_NUM_100M;
2142                 break;
2143         case I40E_LINK_SPEED_1GB:
2144                 new_link.link_speed = ETH_SPEED_NUM_1G;
2145                 break;
2146         case I40E_LINK_SPEED_10GB:
2147                 new_link.link_speed = ETH_SPEED_NUM_10G;
2148                 break;
2149         case I40E_LINK_SPEED_20GB:
2150                 new_link.link_speed = ETH_SPEED_NUM_20G;
2151                 break;
2152         case I40E_LINK_SPEED_40GB:
2153                 new_link.link_speed = ETH_SPEED_NUM_40G;
2154                 break;
2155         default:
2156                 new_link.link_speed = ETH_SPEED_NUM_100M;
2157                 break;
2158         }
2159         /* full duplex only */
2160         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2161         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2162                                              ETH_LINK_DOWN;
2163
2164         i40evf_dev_atomic_write_link_status(dev, &new_link);
2165
2166         return 0;
2167 }
2168
2169 static void
2170 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2171 {
2172         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2173         int ret;
2174
2175         /* If enabled, just return */
2176         if (vf->promisc_unicast_enabled)
2177                 return;
2178
2179         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2180         if (ret == 0)
2181                 vf->promisc_unicast_enabled = TRUE;
2182 }
2183
2184 static void
2185 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2186 {
2187         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2188         int ret;
2189
2190         /* If disabled, just return */
2191         if (!vf->promisc_unicast_enabled)
2192                 return;
2193
2194         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2195         if (ret == 0)
2196                 vf->promisc_unicast_enabled = FALSE;
2197 }
2198
2199 static void
2200 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2201 {
2202         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2203         int ret;
2204
2205         /* If enabled, just return */
2206         if (vf->promisc_multicast_enabled)
2207                 return;
2208
2209         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2210         if (ret == 0)
2211                 vf->promisc_multicast_enabled = TRUE;
2212 }
2213
2214 static void
2215 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2216 {
2217         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2218         int ret;
2219
2220         /* If enabled, just return */
2221         if (!vf->promisc_multicast_enabled)
2222                 return;
2223
2224         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2225         if (ret == 0)
2226                 vf->promisc_multicast_enabled = FALSE;
2227 }
2228
2229 static void
2230 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2231 {
2232         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2233
2234         memset(dev_info, 0, sizeof(*dev_info));
2235         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2236         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2237         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2238         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2239         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2240         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2241         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2242         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2243         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2244         dev_info->rx_offload_capa =
2245                 DEV_RX_OFFLOAD_VLAN_STRIP |
2246                 DEV_RX_OFFLOAD_QINQ_STRIP |
2247                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2248                 DEV_RX_OFFLOAD_UDP_CKSUM |
2249                 DEV_RX_OFFLOAD_TCP_CKSUM;
2250         dev_info->tx_offload_capa =
2251                 DEV_TX_OFFLOAD_VLAN_INSERT |
2252                 DEV_TX_OFFLOAD_QINQ_INSERT |
2253                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2254                 DEV_TX_OFFLOAD_UDP_CKSUM |
2255                 DEV_TX_OFFLOAD_TCP_CKSUM |
2256                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2257
2258         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2259                 .rx_thresh = {
2260                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2261                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2262                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2263                 },
2264                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2265                 .rx_drop_en = 0,
2266         };
2267
2268         dev_info->default_txconf = (struct rte_eth_txconf) {
2269                 .tx_thresh = {
2270                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2271                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2272                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2273                 },
2274                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2275                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2276                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2277                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2278         };
2279
2280         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2281                 .nb_max = I40E_MAX_RING_DESC,
2282                 .nb_min = I40E_MIN_RING_DESC,
2283                 .nb_align = I40E_ALIGN_RING_DESC,
2284         };
2285
2286         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2287                 .nb_max = I40E_MAX_RING_DESC,
2288                 .nb_min = I40E_MIN_RING_DESC,
2289                 .nb_align = I40E_ALIGN_RING_DESC,
2290         };
2291 }
2292
2293 static void
2294 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2295 {
2296         if (i40evf_get_statistics(dev, stats))
2297                 PMD_DRV_LOG(ERR, "Get statistics failed");
2298 }
2299
2300 static void
2301 i40evf_dev_close(struct rte_eth_dev *dev)
2302 {
2303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2305         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2306
2307         i40evf_dev_stop(dev);
2308         hw->adapter_stopped = 1;
2309         i40e_dev_free_queues(dev);
2310         i40evf_reset_vf(hw);
2311         i40e_shutdown_adminq(hw);
2312         /* disable uio intr before callback unregister */
2313         rte_intr_disable(intr_handle);
2314
2315         /* unregister callback func from eal lib */
2316         rte_intr_callback_unregister(intr_handle,
2317                                      i40evf_dev_interrupt_handler, dev);
2318         i40evf_disable_irq0(hw);
2319 }
2320
2321 static int
2322 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2323 {
2324         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2325         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2326         int ret;
2327
2328         if (!lut)
2329                 return -EINVAL;
2330
2331         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2332                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2333                                           lut, lut_size);
2334                 if (ret) {
2335                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2336                         return ret;
2337                 }
2338         } else {
2339                 uint32_t *lut_dw = (uint32_t *)lut;
2340                 uint16_t i, lut_size_dw = lut_size / 4;
2341
2342                 for (i = 0; i < lut_size_dw; i++)
2343                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2344         }
2345
2346         return 0;
2347 }
2348
2349 static int
2350 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2351 {
2352         struct i40e_vf *vf;
2353         struct i40e_hw *hw;
2354         int ret;
2355
2356         if (!vsi || !lut)
2357                 return -EINVAL;
2358
2359         vf = I40E_VSI_TO_VF(vsi);
2360         hw = I40E_VSI_TO_HW(vsi);
2361
2362         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2363                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2364                                           lut, lut_size);
2365                 if (ret) {
2366                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2367                         return ret;
2368                 }
2369         } else {
2370                 uint32_t *lut_dw = (uint32_t *)lut;
2371                 uint16_t i, lut_size_dw = lut_size / 4;
2372
2373                 for (i = 0; i < lut_size_dw; i++)
2374                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2375                 I40EVF_WRITE_FLUSH(hw);
2376         }
2377
2378         return 0;
2379 }
2380
2381 static int
2382 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2383                            struct rte_eth_rss_reta_entry64 *reta_conf,
2384                            uint16_t reta_size)
2385 {
2386         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2387         uint8_t *lut;
2388         uint16_t i, idx, shift;
2389         int ret;
2390
2391         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2392                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2393                         "(%d) doesn't match the number of hardware can "
2394                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2395                 return -EINVAL;
2396         }
2397
2398         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2399         if (!lut) {
2400                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2401                 return -ENOMEM;
2402         }
2403         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2404         if (ret)
2405                 goto out;
2406         for (i = 0; i < reta_size; i++) {
2407                 idx = i / RTE_RETA_GROUP_SIZE;
2408                 shift = i % RTE_RETA_GROUP_SIZE;
2409                 if (reta_conf[idx].mask & (1ULL << shift))
2410                         lut[i] = reta_conf[idx].reta[shift];
2411         }
2412         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2413
2414 out:
2415         rte_free(lut);
2416
2417         return ret;
2418 }
2419
2420 static int
2421 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2422                           struct rte_eth_rss_reta_entry64 *reta_conf,
2423                           uint16_t reta_size)
2424 {
2425         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2426         uint16_t i, idx, shift;
2427         uint8_t *lut;
2428         int ret;
2429
2430         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2431                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2432                         "(%d) doesn't match the number of hardware can "
2433                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2434                 return -EINVAL;
2435         }
2436
2437         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2438         if (!lut) {
2439                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2440                 return -ENOMEM;
2441         }
2442
2443         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2444         if (ret)
2445                 goto out;
2446         for (i = 0; i < reta_size; i++) {
2447                 idx = i / RTE_RETA_GROUP_SIZE;
2448                 shift = i % RTE_RETA_GROUP_SIZE;
2449                 if (reta_conf[idx].mask & (1ULL << shift))
2450                         reta_conf[idx].reta[shift] = lut[i];
2451         }
2452
2453 out:
2454         rte_free(lut);
2455
2456         return ret;
2457 }
2458
2459 static int
2460 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2461 {
2462         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2463         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2464         int ret = 0;
2465
2466         if (!key || key_len == 0) {
2467                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2468                 return 0;
2469         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2470                 sizeof(uint32_t)) {
2471                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2472                 return -EINVAL;
2473         }
2474
2475         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2476                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2477                         (struct i40e_aqc_get_set_rss_key_data *)key;
2478
2479                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2480                 if (ret)
2481                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2482                                      "via AQ");
2483         } else {
2484                 uint32_t *hash_key = (uint32_t *)key;
2485                 uint16_t i;
2486
2487                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2488                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2489                 I40EVF_WRITE_FLUSH(hw);
2490         }
2491
2492         return ret;
2493 }
2494
2495 static int
2496 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2497 {
2498         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2499         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2500         int ret;
2501
2502         if (!key || !key_len)
2503                 return -EINVAL;
2504
2505         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2506                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2507                         (struct i40e_aqc_get_set_rss_key_data *)key);
2508                 if (ret) {
2509                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2510                         return ret;
2511                 }
2512         } else {
2513                 uint32_t *key_dw = (uint32_t *)key;
2514                 uint16_t i;
2515
2516                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2517                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2518         }
2519         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2520
2521         return 0;
2522 }
2523
2524 static int
2525 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2526 {
2527         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2528         uint64_t rss_hf, hena;
2529         int ret;
2530
2531         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2532                                  rss_conf->rss_key_len);
2533         if (ret)
2534                 return ret;
2535
2536         rss_hf = rss_conf->rss_hf;
2537         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2538         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2539         if (hw->mac.type == I40E_MAC_X722)
2540                 hena &= ~I40E_RSS_HENA_ALL_X722;
2541         else
2542                 hena &= ~I40E_RSS_HENA_ALL;
2543         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2544         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2545         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2546         I40EVF_WRITE_FLUSH(hw);
2547
2548         return 0;
2549 }
2550
2551 static void
2552 i40evf_disable_rss(struct i40e_vf *vf)
2553 {
2554         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2555         uint64_t hena;
2556
2557         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2558         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2559         if (hw->mac.type == I40E_MAC_X722)
2560                 hena &= ~I40E_RSS_HENA_ALL_X722;
2561         else
2562                 hena &= ~I40E_RSS_HENA_ALL;
2563         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2564         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2565         I40EVF_WRITE_FLUSH(hw);
2566 }
2567
2568 static int
2569 i40evf_config_rss(struct i40e_vf *vf)
2570 {
2571         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2572         struct rte_eth_rss_conf rss_conf;
2573         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2574         uint16_t num;
2575
2576         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2577                 i40evf_disable_rss(vf);
2578                 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2579                 return 0;
2580         }
2581
2582         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2583         /* Fill out the look up table */
2584         for (i = 0, j = 0; i < nb_q; i++, j++) {
2585                 if (j >= num)
2586                         j = 0;
2587                 lut = (lut << 8) | j;
2588                 if ((i & 3) == 3)
2589                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2590         }
2591
2592         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2593         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2594                 i40evf_disable_rss(vf);
2595                 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2596                 return 0;
2597         }
2598
2599         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2600                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2601                 /* Calculate the default hash key */
2602                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2603                         rss_key_default[i] = (uint32_t)rte_rand();
2604                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2605                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2606                         sizeof(uint32_t);
2607         }
2608
2609         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2610 }
2611
2612 static int
2613 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2614                            struct rte_eth_rss_conf *rss_conf)
2615 {
2616         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2617         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2619         uint64_t hena;
2620
2621         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2622         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2623         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2624                  ? I40E_RSS_HENA_ALL_X722
2625                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2626                 if (rss_hf != 0) /* Enable RSS */
2627                         return -EINVAL;
2628                 return 0;
2629         }
2630
2631         /* RSS enabled */
2632         if (rss_hf == 0) /* Disable RSS */
2633                 return -EINVAL;
2634
2635         return i40evf_hw_rss_hash_set(vf, rss_conf);
2636 }
2637
2638 static int
2639 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2640                              struct rte_eth_rss_conf *rss_conf)
2641 {
2642         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2643         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2644         uint64_t hena;
2645
2646         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2647                            &rss_conf->rss_key_len);
2648
2649         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2650         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2651         rss_conf->rss_hf = i40e_parse_hena(hena);
2652
2653         return 0;
2654 }