drivers/net/i40e/i40e_fdir.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2015 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_ether.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_log.h>
  16 #include <rte_memzone.h>
  17 #include <rte_malloc.h>
  18 #include <rte_arp.h>
  19 #include <rte_ip.h>
  20 #include <rte_udp.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_hash_crc.h>
  24
  25 #include "i40e_logs.h"
  26 #include "base/i40e_type.h"
  27 #include "base/i40e_prototype.h"
  28 #include "i40e_ethdev.h"
  29 #include "i40e_rxtx.h"
  30
  31 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  32 #ifndef IPV6_ADDR_LEN
  33 #define IPV6_ADDR_LEN              16
  34 #endif
  35
  36 #ifndef IPPROTO_L2TP
  37 #define IPPROTO_L2TP              115
  38 #endif
  39
  40 #define I40E_FDIR_PKT_LEN                   512
  41 #define I40E_FDIR_IP_DEFAULT_LEN            420
  42 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  43 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  44 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  45 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  46
  47 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  48 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  49 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  50 #define I40E_FDIR_GTP_DEFAULT_LEN           384
  51 #define I40E_FDIR_INNER_IP_DEFAULT_LEN      384
  52 #define I40E_FDIR_INNER_IPV6_DEFAULT_LEN    344
  53
  54 #define I40E_FDIR_GTPC_DST_PORT             2123
  55 #define I40E_FDIR_GTPU_DST_PORT             2152
  56 #define I40E_FDIR_GTP_VER_FLAG_0X30         0x30
  57 #define I40E_FDIR_GTP_VER_FLAG_0X32         0x32
  58 #define I40E_FDIR_GTP_MSG_TYPE_0X01         0x01
  59 #define I40E_FDIR_GTP_MSG_TYPE_0XFF         0xFF
  60
  61 #define I40E_FDIR_ESP_DST_PORT              4500
  62
  63 /* Wait time for fdir filter programming */
  64 #define I40E_FDIR_MAX_WAIT_US 10000
  65
  66 /* Wait count and interval for fdir filter flush */
  67 #define I40E_FDIR_FLUSH_RETRY       50
  68 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  69
  70 #define I40E_COUNTER_PF           2
  71 /* Statistic counter index for one pf */
  72 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  73
  74 #define I40E_FDIR_FLOWS ( \
  75         (1ULL << RTE_ETH_FLOW_FRAG_IPV4) | \
  76         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  77         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  78         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  79         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  80         (1ULL << RTE_ETH_FLOW_FRAG_IPV6) | \
  81         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
  82         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
  83         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
  84         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
  85         (1ULL << RTE_ETH_FLOW_L2_PAYLOAD))
  86
  87 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
  88                         enum i40e_filter_pctype pctype,
  89                         const struct rte_eth_fdir_filter *filter,
  90                         bool add);
  91 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
  92                          struct i40e_fdir_filter *filter);
  93 static struct i40e_fdir_filter *
  94 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
  95                         const struct i40e_fdir_input *input);
  96 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
  97                                    struct i40e_fdir_filter *filter);
  98 static int
  99 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
 100                                   enum i40e_filter_pctype pctype,
 101                                   const struct i40e_fdir_filter_conf *filter,
 102                                   bool add);
 103
 104 static int
 105 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 106 {
 107         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 108         struct i40e_hmc_obj_rxq rx_ctx;
 109         int err = I40E_SUCCESS;
 110
 111         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 112         /* Init the RX queue in hardware */
 113         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 114         rx_ctx.hbuff = 0;
 115         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 116         rx_ctx.qlen = rxq->nb_rx_desc;
 117 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 118         rx_ctx.dsize = 1;
 119 #endif
 120         rx_ctx.dtype = i40e_header_split_none;
 121         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 122         rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
 123         rx_ctx.tphrdesc_ena = 1;
 124         rx_ctx.tphwdesc_ena = 1;
 125         rx_ctx.tphdata_ena = 1;
 126         rx_ctx.tphhead_ena = 1;
 127         rx_ctx.lrxqthresh = 2;
 128         rx_ctx.crcstrip = 0;
 129         rx_ctx.l2tsel = 1;
 130         rx_ctx.showiv = 0;
 131         rx_ctx.prefena = 1;
 132
 133         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 134         if (err != I40E_SUCCESS) {
 135                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 136                 return err;
 137         }
 138         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 139         if (err != I40E_SUCCESS) {
 140                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 141                 return err;
 142         }
 143         rxq->qrx_tail = hw->hw_addr +
 144                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 145
 146         rte_wmb();
 147         /* Init the RX tail regieter. */
 148         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 149
 150         return err;
 151 }
 152
 153 /*
 154  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 155  * @pf: board private structure
 156  */
 157 int
 158 i40e_fdir_setup(struct i40e_pf *pf)
 159 {
 160         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 161         struct i40e_vsi *vsi;
 162         int err = I40E_SUCCESS;
 163         char z_name[RTE_MEMZONE_NAMESIZE];
 164         const struct rte_memzone *mz = NULL;
 165         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 166
 167         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 168                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 169                 return I40E_NOT_SUPPORTED;
 170         }
 171
 172         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 173                         " num_filters_best_effort = %u.",
 174                         hw->func_caps.fd_filters_guaranteed,
 175                         hw->func_caps.fd_filters_best_effort);
 176
 177         vsi = pf->fdir.fdir_vsi;
 178         if (vsi) {
 179                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 180                 return I40E_SUCCESS;
 181         }
 182         /* make new FDIR VSI */
 183         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 184         if (!vsi) {
 185                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 186                 return I40E_ERR_NO_AVAILABLE_VSI;
 187         }
 188         pf->fdir.fdir_vsi = vsi;
 189
 190         /*Fdir tx queue setup*/
 191         err = i40e_fdir_setup_tx_resources(pf);
 192         if (err) {
 193                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 194                 goto fail_setup_tx;
 195         }
 196
 197         /*Fdir rx queue setup*/
 198         err = i40e_fdir_setup_rx_resources(pf);
 199         if (err) {
 200                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 201                 goto fail_setup_rx;
 202         }
 203
 204         err = i40e_tx_queue_init(pf->fdir.txq);
 205         if (err) {
 206                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 207                 goto fail_mem;
 208         }
 209
 210         /* need switch on before dev start*/
 211         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 212         if (err) {
 213                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 214                 goto fail_mem;
 215         }
 216
 217         /* Init the rx queue in hardware */
 218         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 219         if (err) {
 220                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 221                 goto fail_mem;
 222         }
 223
 224         /* switch on rx queue */
 225         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 226         if (err) {
 227                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 228                 goto fail_mem;
 229         }
 230
 231         /* reserve memory for the fdir programming packet */
 232         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 233                         eth_dev->device->driver->name,
 234                         I40E_FDIR_MZ_NAME,
 235                         eth_dev->data->port_id);
 236         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 237         if (!mz) {
 238                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 239                                  "flow director program packet.");
 240                 err = I40E_ERR_NO_MEMORY;
 241                 goto fail_mem;
 242         }
 243         pf->fdir.prg_pkt = mz->addr;
 244         pf->fdir.dma_addr = mz->iova;
 245
 246         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 247         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 248                     vsi->base_queue);
 249         return I40E_SUCCESS;
 250
 251 fail_mem:
 252         i40e_dev_rx_queue_release(pf->fdir.rxq);
 253         pf->fdir.rxq = NULL;
 254 fail_setup_rx:
 255         i40e_dev_tx_queue_release(pf->fdir.txq);
 256         pf->fdir.txq = NULL;
 257 fail_setup_tx:
 258         i40e_vsi_release(vsi);
 259         pf->fdir.fdir_vsi = NULL;
 260         return err;
 261 }
 262
 263 /*
 264  * i40e_fdir_teardown - release the Flow Director resources
 265  * @pf: board private structure
 266  */
 267 void
 268 i40e_fdir_teardown(struct i40e_pf *pf)
 269 {
 270         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 271         struct i40e_vsi *vsi;
 272
 273         vsi = pf->fdir.fdir_vsi;
 274         if (!vsi)
 275                 return;
 276         int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 277         if (err)
 278                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
 279         err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 280         if (err)
 281                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
 282         i40e_dev_rx_queue_release(pf->fdir.rxq);
 283         pf->fdir.rxq = NULL;
 284         i40e_dev_tx_queue_release(pf->fdir.txq);
 285         pf->fdir.txq = NULL;
 286         i40e_vsi_release(vsi);
 287         pf->fdir.fdir_vsi = NULL;
 288 }
 289
 290 /* check whether the flow director table in empty */
 291 static inline int
 292 i40e_fdir_empty(struct i40e_hw *hw)
 293 {
 294         uint32_t guarant_cnt, best_cnt;
 295
 296         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 297                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 298                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 299         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 300                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 301                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 302         if (best_cnt + guarant_cnt > 0)
 303                 return -1;
 304
 305         return 0;
 306 }
 307
 308 /*
 309  * Initialize the configuration about bytes stream extracted as flexible payload
 310  * and mask setting
 311  */
 312 static inline void
 313 i40e_init_flx_pld(struct i40e_pf *pf)
 314 {
 315         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 316         uint8_t pctype;
 317         int i, index;
 318         uint16_t flow_type;
 319
 320         /*
 321          * Define the bytes stream extracted as flexible payload in
 322          * field vector. By default, select 8 words from the beginning
 323          * of payload as flexible payload.
 324          */
 325         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 326                 index = i * I40E_MAX_FLXPLD_FIED;
 327                 pf->fdir.flex_set[index].src_offset = 0;
 328                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 329                 pf->fdir.flex_set[index].dst_offset = 0;
 330                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 331                 I40E_WRITE_REG(hw,
 332                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 333                 I40E_WRITE_REG(hw,
 334                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 335         }
 336
 337         /* initialize the masks */
 338         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 339              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 340                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
 341
 342                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
 343                         continue;
 344                 pf->fdir.flex_mask[pctype].word_mask = 0;
 345                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 346                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 347                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 348                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 349                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 350                 }
 351         }
 352 }
 353
 354 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 355         if ((flex_pit2).src_offset < \
 356                 (flex_pit1).src_offset + (flex_pit1).size) { \
 357                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 358                         " less than than previous offset" \
 359                         " + previous FSIZE."); \
 360                 return -EINVAL; \
 361         } \
 362 } while (0)
 363
 364 /*
 365  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 366  * and the flex_pit will be sorted by it's src_offset value
 367  */
 368 static inline uint16_t
 369 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 370                         struct i40e_fdir_flex_pit *flex_pit)
 371 {
 372         uint16_t src_tmp, size, num = 0;
 373         uint16_t i, k, j = 0;
 374
 375         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 376                 size = 1;
 377                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 378                         if (src_offset[j + 1] == src_offset[j] + 1)
 379                                 size++;
 380                         else
 381                                 break;
 382                 }
 383                 src_tmp = src_offset[j] + 1 - size;
 384                 /* the flex_pit need to be sort by src_offset */
 385                 for (i = 0; i < num; i++) {
 386                         if (src_tmp < flex_pit[i].src_offset)
 387                                 break;
 388                 }
 389                 /* if insert required, move backward */
 390                 for (k = num; k > i; k--)
 391                         flex_pit[k] = flex_pit[k - 1];
 392                 /* insert */
 393                 flex_pit[i].dst_offset = j + 1 - size;
 394                 flex_pit[i].src_offset = src_tmp;
 395                 flex_pit[i].size = size;
 396                 j++;
 397                 num++;
 398         }
 399         return num;
 400 }
 401
 402 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 403 static inline int
 404 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 405 {
 406         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 407         uint16_t num, i;
 408
 409         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 410                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 411                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 412                         return -EINVAL;
 413                 }
 414         }
 415
 416         memset(flex_pit, 0, sizeof(flex_pit));
 417         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 418         if (num > I40E_MAX_FLXPLD_FIED) {
 419                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 420                 return -EINVAL;
 421         }
 422         for (i = 0; i < num; i++) {
 423                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 424                         flex_pit[i].src_offset & 0x01) {
 425                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 426                                 " in word");
 427                         return -EINVAL;
 428                 }
 429                 if (i != num - 1)
 430                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 431         }
 432         return 0;
 433 }
 434
 435 /*
 436  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 437  * arguments are valid
 438  */
 439 static int
 440 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
 441                           const struct rte_eth_fdir_flex_conf *conf)
 442 {
 443         const struct rte_eth_flex_payload_cfg *flex_cfg;
 444         const struct rte_eth_fdir_flex_mask *flex_mask;
 445         uint16_t mask_tmp;
 446         uint8_t nb_bitmask;
 447         uint16_t i, j;
 448         int ret = 0;
 449         enum i40e_filter_pctype pctype;
 450
 451         if (conf == NULL) {
 452                 PMD_DRV_LOG(INFO, "NULL pointer.");
 453                 return -EINVAL;
 454         }
 455         /* check flexible payload setting configuration */
 456         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 457                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 458                 return -EINVAL;
 459         }
 460         for (i = 0; i < conf->nb_payloads; i++) {
 461                 flex_cfg = &conf->flex_set[i];
 462                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 463                         PMD_DRV_LOG(ERR, "invalid payload type.");
 464                         return -EINVAL;
 465                 }
 466                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 467                 if (ret < 0) {
 468                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 469                         return -EINVAL;
 470                 }
 471         }
 472
 473         /* check flex mask setting configuration */
 474         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 475                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 476                 return -EINVAL;
 477         }
 478         for (i = 0; i < conf->nb_flexmasks; i++) {
 479                 flex_mask = &conf->flex_mask[i];
 480                 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
 481                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
 482                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 483                         return -EINVAL;
 484                 }
 485                 nb_bitmask = 0;
 486                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 487                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 488                                              flex_mask->mask[j + 1]);
 489                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 490                                 nb_bitmask++;
 491                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 492                                         PMD_DRV_LOG(ERR, " exceed maximal"
 493                                                 " number of bitmasks.");
 494                                         return -EINVAL;
 495                                 }
 496                         }
 497                 }
 498         }
 499         return 0;
 500 }
 501
 502 /*
 503  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 504  * @pf: board private structure
 505  * @cfg: the rule how bytes stream is extracted as flexible payload
 506  */
 507 static void
 508 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 509                          const struct rte_eth_flex_payload_cfg *cfg)
 510 {
 511         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 512         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 513         uint32_t flx_pit, flx_ort;
 514         uint16_t num, min_next_off;  /* in words */
 515         uint8_t field_idx = 0;
 516         uint8_t layer_idx = 0;
 517         uint16_t i;
 518
 519         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 520                 layer_idx = I40E_FLXPLD_L2_IDX;
 521         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 522                 layer_idx = I40E_FLXPLD_L3_IDX;
 523         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 524                 layer_idx = I40E_FLXPLD_L4_IDX;
 525
 526         memset(flex_pit, 0, sizeof(flex_pit));
 527         num = RTE_MIN(i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit),
 528                       RTE_DIM(flex_pit));
 529
 530         if (num) {
 531                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
 532                           (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
 533                           (layer_idx * I40E_MAX_FLXPLD_FIED);
 534                 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
 535         }
 536
 537         for (i = 0; i < num; i++) {
 538                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 539                 /* record the info in fdir structure */
 540                 pf->fdir.flex_set[field_idx].src_offset =
 541                         flex_pit[i].src_offset / sizeof(uint16_t);
 542                 pf->fdir.flex_set[field_idx].size =
 543                         flex_pit[i].size / sizeof(uint16_t);
 544                 pf->fdir.flex_set[field_idx].dst_offset =
 545                         flex_pit[i].dst_offset / sizeof(uint16_t);
 546                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 547                                 pf->fdir.flex_set[field_idx].size,
 548                                 pf->fdir.flex_set[field_idx].dst_offset);
 549
 550                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 551         }
 552         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 553                                 pf->fdir.flex_set[field_idx].size;
 554
 555         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 556                 /* set the non-used register obeying register's constrain */
 557                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 558                            NONUSE_FLX_PIT_DEST_OFF);
 559                 I40E_WRITE_REG(hw,
 560                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 561                         flx_pit);
 562                 min_next_off++;
 563         }
 564 }
 565
 566 /*
 567  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 568  * @pf: board private structure
 569  * @pctype: packet classify type
 570  * @flex_masks: mask for flexible payload
 571  */
 572 static void
 573 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 574                 enum i40e_filter_pctype pctype,
 575                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 576 {
 577         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 578         struct i40e_fdir_flex_mask *flex_mask;
 579         uint32_t flxinset, fd_mask;
 580         uint16_t mask_tmp;
 581         uint8_t i, nb_bitmask = 0;
 582
 583         flex_mask = &pf->fdir.flex_mask[pctype];
 584         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 585         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 586                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 587                 if (mask_tmp != 0x0) {
 588                         flex_mask->word_mask |=
 589                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 590                         if (mask_tmp != UINT16_MAX) {
 591                                 /* set bit mask */
 592                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 593                                 flex_mask->bitmask[nb_bitmask].offset =
 594                                         i / sizeof(uint16_t);
 595                                 nb_bitmask++;
 596                         }
 597                 }
 598         }
 599         /* write mask to hw */
 600         flxinset = (flex_mask->word_mask <<
 601                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 602                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 603         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 604
 605         for (i = 0; i < nb_bitmask; i++) {
 606                 fd_mask = (flex_mask->bitmask[i].mask <<
 607                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 608                         I40E_PRTQF_FD_MSK_MASK_MASK;
 609                 fd_mask |= ((flex_mask->bitmask[i].offset +
 610                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 611                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 612                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 613                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 614         }
 615 }
 616
 617 /*
 618  * Enable/disable flow director RX processing in vector routines.
 619  */
 620 void
 621 i40e_fdir_rx_proc_enable(struct rte_eth_dev *dev, bool on)
 622 {
 623         int32_t i;
 624
 625         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 626                 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
 627                 if (!rxq)
 628                         continue;
 629                 rxq->fdir_enabled = on;
 630         }
 631         PMD_DRV_LOG(DEBUG, "Flow Director processing on RX set to %d", on);
 632 }
 633
 634 /*
 635  * Configure flow director related setting
 636  */
 637 int
 638 i40e_fdir_configure(struct rte_eth_dev *dev)
 639 {
 640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 642         struct rte_eth_fdir_flex_conf *conf;
 643         enum i40e_filter_pctype pctype;
 644         uint32_t val;
 645         uint8_t i;
 646         int ret = 0;
 647
 648         /*
 649         * configuration need to be done before
 650         * flow director filters are added
 651         * If filters exist, flush them.
 652         */
 653         if (i40e_fdir_empty(hw) < 0) {
 654                 ret = i40e_fdir_flush(dev);
 655                 if (ret) {
 656                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 657                         return ret;
 658                 }
 659         }
 660
 661         /* enable FDIR filter */
 662         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 663         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 664         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 665
 666         i40e_init_flx_pld(pf); /* set flex config to default value */
 667
 668         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 669         ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
 670         if (ret < 0) {
 671                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 672                 return -EINVAL;
 673         }
 674
 675         if (!pf->support_multi_driver) {
 676                 /* configure flex payload */
 677                 for (i = 0; i < conf->nb_payloads; i++)
 678                         i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 679                 /* configure flex mask*/
 680                 for (i = 0; i < conf->nb_flexmasks; i++) {
 681                         if (hw->mac.type == I40E_MAC_X722) {
 682                                 /* get pctype value in fd pctype register */
 683                                 pctype = (enum i40e_filter_pctype)
 684                                           i40e_read_rx_ctl(hw,
 685                                                 I40E_GLQF_FD_PCTYPES(
 686                                                 (int)i40e_flowtype_to_pctype(
 687                                                 pf->adapter,
 688                                                 conf->flex_mask[i].flow_type)));
 689                         } else {
 690                                 pctype = i40e_flowtype_to_pctype(pf->adapter,
 691                                                   conf->flex_mask[i].flow_type);
 692                         }
 693
 694                         i40e_set_flex_mask_on_pctype(pf, pctype,
 695                                                      &conf->flex_mask[i]);
 696                 }
 697         } else {
 698                 PMD_DRV_LOG(ERR, "Not support flexible payload.");
 699         }
 700
 701         /* Enable FDIR processing in RX routines */
 702         i40e_fdir_rx_proc_enable(dev, 1);
 703
 704         return ret;
 705 }
 706
 707 static inline int
 708 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 709                            unsigned char *raw_pkt,
 710                            bool vlan)
 711 {
 712         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 713         uint16_t *ether_type;
 714         uint8_t len = 2 * sizeof(struct rte_ether_addr);
 715         struct rte_ipv4_hdr *ip;
 716         struct rte_ipv6_hdr *ip6;
 717         static const uint8_t next_proto[] = {
 718                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 719                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 720                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 721                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 722                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 723                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 724                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 725                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 726                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 727                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 728         };
 729
 730         raw_pkt += 2 * sizeof(struct rte_ether_addr);
 731         if (vlan && fdir_input->flow_ext.vlan_tci) {
 732                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 733                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 734                            &fdir_input->flow_ext.vlan_tci,
 735                            sizeof(uint16_t));
 736                 raw_pkt += sizeof(vlan_frame);
 737                 len += sizeof(vlan_frame);
 738         }
 739         ether_type = (uint16_t *)raw_pkt;
 740         raw_pkt += sizeof(uint16_t);
 741         len += sizeof(uint16_t);
 742
 743         switch (fdir_input->flow_type) {
 744         case RTE_ETH_FLOW_L2_PAYLOAD:
 745                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 746                 break;
 747         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 748         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 749         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 750         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 751         case RTE_ETH_FLOW_FRAG_IPV4:
 752                 ip = (struct rte_ipv4_hdr *)raw_pkt;
 753
 754                 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
 755                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 756                 /* set len to by default */
 757                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 758                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 759                                         fdir_input->flow.ip4_flow.proto :
 760                                         next_proto[fdir_input->flow_type];
 761                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 762                                         fdir_input->flow.ip4_flow.ttl :
 763                                         I40E_FDIR_IP_DEFAULT_TTL;
 764                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 765                 /*
 766                  * The source and destination fields in the transmitted packet
 767                  * need to be presented in a reversed order with respect
 768                  * to the expected received packets.
 769                  */
 770                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 771                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 772                 len += sizeof(struct rte_ipv4_hdr);
 773                 break;
 774         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 775         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 776         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 777         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 778         case RTE_ETH_FLOW_FRAG_IPV6:
 779                 ip6 = (struct rte_ipv6_hdr *)raw_pkt;
 780
 781                 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
 782                 ip6->vtc_flow =
 783                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 784                                          (fdir_input->flow.ipv6_flow.tc <<
 785                                           I40E_FDIR_IPv6_TC_OFFSET));
 786                 ip6->payload_len =
 787                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 788                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 789                                         fdir_input->flow.ipv6_flow.proto :
 790                                         next_proto[fdir_input->flow_type];
 791                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 792                                         fdir_input->flow.ipv6_flow.hop_limits :
 793                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 794                 /*
 795                  * The source and destination fields in the transmitted packet
 796                  * need to be presented in a reversed order with respect
 797                  * to the expected received packets.
 798                  */
 799                 rte_memcpy(&(ip6->src_addr),
 800                            &(fdir_input->flow.ipv6_flow.dst_ip),
 801                            IPV6_ADDR_LEN);
 802                 rte_memcpy(&(ip6->dst_addr),
 803                            &(fdir_input->flow.ipv6_flow.src_ip),
 804                            IPV6_ADDR_LEN);
 805                 len += sizeof(struct rte_ipv6_hdr);
 806                 break;
 807         default:
 808                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 809                             fdir_input->flow_type);
 810                 return -1;
 811         }
 812         return len;
 813 }
 814
 815
 816 /*
 817  * i40e_fdir_construct_pkt - construct packet based on fields in input
 818  * @pf: board private structure
 819  * @fdir_input: input set of the flow director entry
 820  * @raw_pkt: a packet to be constructed
 821  */
 822 static int
 823 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 824                              const struct rte_eth_fdir_input *fdir_input,
 825                              unsigned char *raw_pkt)
 826 {
 827         unsigned char *payload, *ptr;
 828         struct rte_udp_hdr *udp;
 829         struct rte_tcp_hdr *tcp;
 830         struct rte_sctp_hdr *sctp;
 831         uint8_t size, dst = 0;
 832         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 833         int len;
 834
 835         /* fill the ethernet and IP head */
 836         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 837                                          !!fdir_input->flow_ext.vlan_tci);
 838         if (len < 0)
 839                 return -EINVAL;
 840
 841         /* fill the L4 head */
 842         switch (fdir_input->flow_type) {
 843         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 844                 udp = (struct rte_udp_hdr *)(raw_pkt + len);
 845                 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
 846                 /*
 847                  * The source and destination fields in the transmitted packet
 848                  * need to be presented in a reversed order with respect
 849                  * to the expected received packets.
 850                  */
 851                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 852                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 853                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 854                 break;
 855
 856         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 857                 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
 858                 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
 859                 /*
 860                  * The source and destination fields in the transmitted packet
 861                  * need to be presented in a reversed order with respect
 862                  * to the expected received packets.
 863                  */
 864                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 865                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 866                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 867                 break;
 868
 869         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 870                 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
 871                 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
 872                 /*
 873                  * The source and destination fields in the transmitted packet
 874                  * need to be presented in a reversed order with respect
 875                  * to the expected received packets.
 876                  */
 877                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 878                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 879                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 880                 break;
 881
 882         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 883         case RTE_ETH_FLOW_FRAG_IPV4:
 884                 payload = raw_pkt + len;
 885                 set_idx = I40E_FLXPLD_L3_IDX;
 886                 break;
 887
 888         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 889                 udp = (struct rte_udp_hdr *)(raw_pkt + len);
 890                 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
 891                 /*
 892                  * The source and destination fields in the transmitted packet
 893                  * need to be presented in a reversed order with respect
 894                  * to the expected received packets.
 895                  */
 896                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 897                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 898                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 899                 break;
 900
 901         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 902                 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
 903                 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
 904                 /*
 905                  * The source and destination fields in the transmitted packet
 906                  * need to be presented in a reversed order with respect
 907                  * to the expected received packets.
 908                  */
 909                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 910                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 911                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 912                 break;
 913
 914         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 915                 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
 916                 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
 917                 /*
 918                  * The source and destination fields in the transmitted packet
 919                  * need to be presented in a reversed order with respect
 920                  * to the expected received packets.
 921                  */
 922                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 923                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 924                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 925                 break;
 926
 927         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 928         case RTE_ETH_FLOW_FRAG_IPV6:
 929                 payload = raw_pkt + len;
 930                 set_idx = I40E_FLXPLD_L3_IDX;
 931                 break;
 932         case RTE_ETH_FLOW_L2_PAYLOAD:
 933                 payload = raw_pkt + len;
 934                 /*
 935                  * ARP packet is a special case on which the payload
 936                  * starts after the whole ARP header
 937                  */
 938                 if (fdir_input->flow.l2_flow.ether_type ==
 939                                 rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
 940                         payload += sizeof(struct rte_arp_hdr);
 941                 set_idx = I40E_FLXPLD_L2_IDX;
 942                 break;
 943         default:
 944                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 945                 return -EINVAL;
 946         }
 947
 948         /* fill the flexbytes to payload */
 949         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 950                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 951                 size = pf->fdir.flex_set[pit_idx].size;
 952                 if (size == 0)
 953                         continue;
 954                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 955                 ptr = payload +
 956                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 957                 rte_memcpy(ptr,
 958                                  &fdir_input->flow_ext.flexbytes[dst],
 959                                  size * sizeof(uint16_t));
 960         }
 961
 962         return 0;
 963 }
 964
 965 static struct i40e_customized_pctype *
 966 i40e_flow_fdir_find_customized_pctype(struct i40e_pf *pf, uint8_t pctype)
 967 {
 968         struct i40e_customized_pctype *cus_pctype;
 969         enum i40e_new_pctype i = I40E_CUSTOMIZED_GTPC;
 970
 971         for (; i < I40E_CUSTOMIZED_MAX; i++) {
 972                 cus_pctype = &pf->customized_pctype[i];
 973                 if (pctype == cus_pctype->pctype)
 974                         return cus_pctype;
 975         }
 976         return NULL;
 977 }
 978
 979 static inline int
 980 fill_ip6_head(const struct i40e_fdir_input *fdir_input, unsigned char *raw_pkt,
 981                 uint8_t next_proto, uint8_t len, uint16_t *ether_type)
 982 {
 983         struct rte_ipv6_hdr *ip6;
 984
 985         ip6 = (struct rte_ipv6_hdr *)raw_pkt;
 986
 987         *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
 988         ip6->vtc_flow = rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 989                 (fdir_input->flow.ipv6_flow.tc << I40E_FDIR_IPv6_TC_OFFSET));
 990         ip6->payload_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 991         ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 992                 fdir_input->flow.ipv6_flow.proto : next_proto;
 993         ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 994                 fdir_input->flow.ipv6_flow.hop_limits :
 995                 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 996         /**
 997          * The source and destination fields in the transmitted packet
 998          * need to be presented in a reversed order with respect
 999          * to the expected received packets.
1000          */
1001         rte_memcpy(&ip6->src_addr, &fdir_input->flow.ipv6_flow.dst_ip,
1002                 IPV6_ADDR_LEN);
1003         rte_memcpy(&ip6->dst_addr, &fdir_input->flow.ipv6_flow.src_ip,
1004                 IPV6_ADDR_LEN);
1005         len += sizeof(struct rte_ipv6_hdr);
1006
1007         return len;
1008 }
1009
1010 static inline int
1011 i40e_flow_fdir_fill_eth_ip_head(struct i40e_pf *pf,
1012                                 const struct i40e_fdir_input *fdir_input,
1013                                 unsigned char *raw_pkt,
1014                                 bool vlan)
1015 {
1016         struct i40e_customized_pctype *cus_pctype = NULL;
1017         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
1018         uint16_t *ether_type;
1019         uint8_t len = 2 * sizeof(struct rte_ether_addr);
1020         struct rte_ipv4_hdr *ip;
1021         struct rte_ipv6_hdr *ip6;
1022         uint8_t pctype = fdir_input->pctype;
1023         bool is_customized_pctype = fdir_input->flow_ext.customized_pctype;
1024         static const uint8_t next_proto[] = {
1025                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
1026                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
1027                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
1028                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
1029                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
1030                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
1031                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
1032                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
1033                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
1034                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
1035         };
1036
1037         raw_pkt += 2 * sizeof(struct rte_ether_addr);
1038         if (vlan && fdir_input->flow_ext.vlan_tci) {
1039                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
1040                 rte_memcpy(raw_pkt + sizeof(uint16_t),
1041                            &fdir_input->flow_ext.vlan_tci,
1042                            sizeof(uint16_t));
1043                 raw_pkt += sizeof(vlan_frame);
1044                 len += sizeof(vlan_frame);
1045         }
1046         ether_type = (uint16_t *)raw_pkt;
1047         raw_pkt += sizeof(uint16_t);
1048         len += sizeof(uint16_t);
1049
1050         if (is_customized_pctype) {
1051                 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1052                 if (!cus_pctype) {
1053                         PMD_DRV_LOG(ERR, "unknown pctype %u.",
1054                                     fdir_input->pctype);
1055                         return -1;
1056                 }
1057         }
1058
1059         if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1060                 *ether_type = fdir_input->flow.l2_flow.ether_type;
1061         else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
1062                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
1063                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
1064                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1065                  pctype == I40E_FILTER_PCTYPE_FRAG_IPV4 ||
1066                  ((is_customized_pctype) &&
1067                   ((cus_pctype->index == I40E_CUSTOMIZED_GTPC) ||
1068                    (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4) ||
1069                    (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6) ||
1070                    (cus_pctype->index == I40E_CUSTOMIZED_GTPU) ||
1071                    (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3)))) {
1072                 ip = (struct rte_ipv4_hdr *)raw_pkt;
1073
1074                 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);
1075                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1076                 /* set len to by default */
1077                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
1078                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
1079                         fdir_input->flow.ip4_flow.ttl :
1080                         I40E_FDIR_IP_DEFAULT_TTL;
1081                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
1082                 /**
1083                  * The source and destination fields in the transmitted packet
1084                  * need to be presented in a reversed order with respect
1085                  * to the expected received packets.
1086                  */
1087                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
1088                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
1089
1090                 if (!is_customized_pctype) {
1091                         ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
1092                                 fdir_input->flow.ip4_flow.proto :
1093                                 next_proto[fdir_input->pctype];
1094                         len += sizeof(struct rte_ipv4_hdr);
1095                 } else if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1096                          cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1097                          cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1098                          cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1099                         ip->next_proto_id = IPPROTO_UDP;
1100                         len += sizeof(struct rte_ipv4_hdr);
1101                 } else if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3) {
1102                         ip->next_proto_id = IPPROTO_L2TP;
1103                         len += sizeof(struct rte_ipv4_hdr);
1104                 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4) {
1105                         ip->next_proto_id = IPPROTO_ESP;
1106                         len += sizeof(struct rte_ipv4_hdr);
1107                 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1108                         ip->next_proto_id = IPPROTO_UDP;
1109                         len += sizeof(struct rte_ipv4_hdr);
1110                 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6)
1111                         len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_ESP,
1112                                         len, ether_type);
1113                 else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6_UDP)
1114                         len = fill_ip6_head(fdir_input, raw_pkt, IPPROTO_UDP,
1115                                         len, ether_type);
1116         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
1117                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
1118                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
1119                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1120                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV6 ||
1121                    ((is_customized_pctype) &&
1122                     (cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3))) {
1123                 ip6 = (struct rte_ipv6_hdr *)raw_pkt;
1124
1125                 *ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);
1126                 ip6->vtc_flow =
1127                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1128                                          (fdir_input->flow.ipv6_flow.tc <<
1129                                           I40E_FDIR_IPv6_TC_OFFSET));
1130                 ip6->payload_len =
1131                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1132                 if (!is_customized_pctype)
1133                         ip6->proto = fdir_input->flow.ipv6_flow.proto ?
1134                                 fdir_input->flow.ipv6_flow.proto :
1135                                 next_proto[fdir_input->pctype];
1136                 else if (cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3)
1137                         ip6->proto = IPPROTO_L2TP;
1138                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
1139                         fdir_input->flow.ipv6_flow.hop_limits :
1140                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1141                 /**
1142                  * The source and destination fields in the transmitted packet
1143                  * need to be presented in a reversed order with respect
1144                  * to the expected received packets.
1145                  */
1146                 rte_memcpy(&ip6->src_addr,
1147                            &fdir_input->flow.ipv6_flow.dst_ip,
1148                            IPV6_ADDR_LEN);
1149                 rte_memcpy(&ip6->dst_addr,
1150                            &fdir_input->flow.ipv6_flow.src_ip,
1151                            IPV6_ADDR_LEN);
1152                 len += sizeof(struct rte_ipv6_hdr);
1153         } else {
1154                 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1155                 return -1;
1156         }
1157
1158         return len;
1159 }
1160
1161 /**
1162  * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
1163  * @pf: board private structure
1164  * @fdir_input: input set of the flow director entry
1165  * @raw_pkt: a packet to be constructed
1166  */
1167 static int
1168 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
1169                              const struct i40e_fdir_input *fdir_input,
1170                              unsigned char *raw_pkt)
1171 {
1172         unsigned char *payload = NULL;
1173         unsigned char *ptr;
1174         struct rte_udp_hdr *udp;
1175         struct rte_tcp_hdr *tcp;
1176         struct rte_sctp_hdr *sctp;
1177         struct rte_flow_item_gtp *gtp;
1178         struct rte_ipv4_hdr *gtp_ipv4;
1179         struct rte_ipv6_hdr *gtp_ipv6;
1180         struct rte_flow_item_l2tpv3oip *l2tpv3oip;
1181         struct rte_flow_item_esp *esp;
1182         struct rte_ipv4_hdr *esp_ipv4;
1183         struct rte_ipv6_hdr *esp_ipv6;
1184
1185         uint8_t size, dst = 0;
1186         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
1187         int len;
1188         uint8_t pctype = fdir_input->pctype;
1189         struct i40e_customized_pctype *cus_pctype;
1190
1191         /* raw pcket template - just copy contents of the raw packet */
1192         if (fdir_input->flow_ext.pkt_template) {
1193                 memcpy(raw_pkt, fdir_input->flow.raw_flow.packet,
1194                        fdir_input->flow.raw_flow.length);
1195                 return 0;
1196         }
1197
1198         /* fill the ethernet and IP head */
1199         len = i40e_flow_fdir_fill_eth_ip_head(pf, fdir_input, raw_pkt,
1200                                               !!fdir_input->flow_ext.vlan_tci);
1201         if (len < 0)
1202                 return -EINVAL;
1203
1204         /* fill the L4 head */
1205         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
1206                 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1207                 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
1208                 /**
1209                  * The source and destination fields in the transmitted packet
1210                  * need to be presented in a reversed order with respect
1211                  * to the expected received packets.
1212                  */
1213                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
1214                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
1215                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1216         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
1217                 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
1218                 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
1219                 /**
1220                  * The source and destination fields in the transmitted packet
1221                  * need to be presented in a reversed order with respect
1222                  * to the expected received packets.
1223                  */
1224                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
1225                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
1226                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1227         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) {
1228                 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
1229                 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
1230                 /**
1231                  * The source and destination fields in the transmitted packet
1232                  * need to be presented in a reversed order with respect
1233                  * to the expected received packets.
1234                  */
1235                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
1236                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1237                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1238         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1239                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1240                 payload = raw_pkt + len;
1241                 set_idx = I40E_FLXPLD_L3_IDX;
1242         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
1243                 udp = (struct rte_udp_hdr *)(raw_pkt + len);
1244                 payload = (unsigned char *)udp + sizeof(struct rte_udp_hdr);
1245                 /**
1246                  * The source and destination fields in the transmitted packet
1247                  * need to be presented in a reversed order with respect
1248                  * to the expected received packets.
1249                  */
1250                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1251                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1252                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1253         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
1254                 tcp = (struct rte_tcp_hdr *)(raw_pkt + len);
1255                 payload = (unsigned char *)tcp + sizeof(struct rte_tcp_hdr);
1256                 /**
1257                  * The source and destination fields in the transmitted packet
1258                  * need to be presented in a reversed order with respect
1259                  * to the expected received packets.
1260                  */
1261                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1262                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1263                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1264         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) {
1265                 sctp = (struct rte_sctp_hdr *)(raw_pkt + len);
1266                 payload = (unsigned char *)sctp + sizeof(struct rte_sctp_hdr);
1267                 /**
1268                  * The source and destination fields in the transmitted packet
1269                  * need to be presented in a reversed order with respect
1270                  * to the expected received packets.
1271                  */
1272                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1273                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1274                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1275         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1276                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1277                 payload = raw_pkt + len;
1278                 set_idx = I40E_FLXPLD_L3_IDX;
1279         } else if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD) {
1280                 payload = raw_pkt + len;
1281                 /**
1282                  * ARP packet is a special case on which the payload
1283                  * starts after the whole ARP header
1284                  */
1285                 if (fdir_input->flow.l2_flow.ether_type ==
1286                                 rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP))
1287                         payload += sizeof(struct rte_arp_hdr);
1288                 set_idx = I40E_FLXPLD_L2_IDX;
1289         } else if (fdir_input->flow_ext.customized_pctype) {
1290                 /* If customized pctype is used */
1291                 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1292                 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1293                     cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1294                     cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1295                     cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1296                         udp = (struct rte_udp_hdr *)(raw_pkt + len);
1297                         udp->dgram_len =
1298                                 rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1299
1300                         gtp = (struct rte_flow_item_gtp *)
1301                                 ((unsigned char *)udp +
1302                                         sizeof(struct rte_udp_hdr));
1303                         gtp->msg_len =
1304                                 rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);
1305                         gtp->teid = fdir_input->flow.gtp_flow.teid;
1306                         gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0X01;
1307
1308                         /* GTP-C message type is not supported. */
1309                         if (cus_pctype->index == I40E_CUSTOMIZED_GTPC) {
1310                                 udp->dst_port =
1311                                       rte_cpu_to_be_16(I40E_FDIR_GTPC_DST_PORT);
1312                                 gtp->v_pt_rsv_flags =
1313                                         I40E_FDIR_GTP_VER_FLAG_0X32;
1314                         } else {
1315                                 udp->dst_port =
1316                                       rte_cpu_to_be_16(I40E_FDIR_GTPU_DST_PORT);
1317                                 gtp->v_pt_rsv_flags =
1318                                         I40E_FDIR_GTP_VER_FLAG_0X30;
1319                         }
1320
1321                         if (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4) {
1322                                 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1323                                 gtp_ipv4 = (struct rte_ipv4_hdr *)
1324                                         ((unsigned char *)gtp +
1325                                          sizeof(struct rte_flow_item_gtp));
1326                                 gtp_ipv4->version_ihl =
1327                                         I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1328                                 gtp_ipv4->next_proto_id = IPPROTO_IP;
1329                                 gtp_ipv4->total_length =
1330                                         rte_cpu_to_be_16(
1331                                                 I40E_FDIR_INNER_IP_DEFAULT_LEN);
1332                                 payload = (unsigned char *)gtp_ipv4 +
1333                                         sizeof(struct rte_ipv4_hdr);
1334                         } else if (cus_pctype->index ==
1335                                    I40E_CUSTOMIZED_GTPU_IPV6) {
1336                                 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1337                                 gtp_ipv6 = (struct rte_ipv6_hdr *)
1338                                         ((unsigned char *)gtp +
1339                                          sizeof(struct rte_flow_item_gtp));
1340                                 gtp_ipv6->vtc_flow =
1341                                         rte_cpu_to_be_32(
1342                                                I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1343                                                (0 << I40E_FDIR_IPv6_TC_OFFSET));
1344                                 gtp_ipv6->proto = IPPROTO_NONE;
1345                                 gtp_ipv6->payload_len =
1346                                         rte_cpu_to_be_16(
1347                                               I40E_FDIR_INNER_IPV6_DEFAULT_LEN);
1348                                 gtp_ipv6->hop_limits =
1349                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1350                                 payload = (unsigned char *)gtp_ipv6 +
1351                                         sizeof(struct rte_ipv6_hdr);
1352                         } else
1353                                 payload = (unsigned char *)gtp +
1354                                         sizeof(struct rte_flow_item_gtp);
1355                 } else if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3 ||
1356                            cus_pctype->index == I40E_CUSTOMIZED_IPV6_L2TPV3) {
1357                         l2tpv3oip = (struct rte_flow_item_l2tpv3oip *)(raw_pkt
1358                                                                        + len);
1359
1360                         if (cus_pctype->index == I40E_CUSTOMIZED_IPV4_L2TPV3)
1361                                 l2tpv3oip->session_id =
1362                                  fdir_input->flow.ip4_l2tpv3oip_flow.session_id;
1363                         else
1364                                 l2tpv3oip->session_id =
1365                                  fdir_input->flow.ip6_l2tpv3oip_flow.session_id;
1366                         payload = (unsigned char *)l2tpv3oip +
1367                                 sizeof(struct rte_flow_item_l2tpv3oip);
1368                 } else if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4 ||
1369                         cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6 ||
1370                         cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4_UDP ||
1371                         cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV6_UDP) {
1372                         if (cus_pctype->index == I40E_CUSTOMIZED_ESP_IPV4) {
1373                                 esp_ipv4 = (struct rte_ipv4_hdr *)
1374                                         (raw_pkt + len);
1375                                 esp = (struct rte_flow_item_esp *)esp_ipv4;
1376                                 esp->hdr.spi =
1377                                         fdir_input->flow.esp_ipv4_flow.spi;
1378                                 payload = (unsigned char *)esp +
1379                                         sizeof(struct rte_esp_hdr);
1380                                 len += sizeof(struct rte_esp_hdr);
1381                         } else if (cus_pctype->index ==
1382                                         I40E_CUSTOMIZED_ESP_IPV4_UDP) {
1383                                 esp_ipv4 = (struct rte_ipv4_hdr *)
1384                                         (raw_pkt + len);
1385                                 udp = (struct rte_udp_hdr *)esp_ipv4;
1386                                 udp->dst_port = rte_cpu_to_be_16
1387                                         (I40E_FDIR_ESP_DST_PORT);
1388
1389                                 udp->dgram_len = rte_cpu_to_be_16
1390                                                 (I40E_FDIR_UDP_DEFAULT_LEN);
1391                                 esp = (struct rte_flow_item_esp *)
1392                                         ((unsigned char *)esp_ipv4 +
1393                                                 sizeof(struct rte_udp_hdr));
1394                                 esp->hdr.spi =
1395                                         fdir_input->flow.esp_ipv4_udp_flow.spi;
1396                                 payload = (unsigned char *)esp +
1397                                         sizeof(struct rte_esp_hdr);
1398                                 len += sizeof(struct rte_udp_hdr) +
1399                                                 sizeof(struct rte_esp_hdr);
1400                         } else if (cus_pctype->index ==
1401                                         I40E_CUSTOMIZED_ESP_IPV6) {
1402                                 esp_ipv6 = (struct rte_ipv6_hdr *)
1403                                         (raw_pkt + len);
1404                                 esp = (struct rte_flow_item_esp *)esp_ipv6;
1405                                 esp->hdr.spi =
1406                                         fdir_input->flow.esp_ipv6_flow.spi;
1407                                 payload = (unsigned char *)esp +
1408                                         sizeof(struct rte_esp_hdr);
1409                                 len += sizeof(struct rte_esp_hdr);
1410                         } else if (cus_pctype->index ==
1411                                         I40E_CUSTOMIZED_ESP_IPV6_UDP) {
1412                                 esp_ipv6 = (struct rte_ipv6_hdr *)
1413                                         (raw_pkt + len);
1414                                 udp = (struct rte_udp_hdr *)esp_ipv6;
1415                                 udp->dst_port = rte_cpu_to_be_16
1416                                         (I40E_FDIR_ESP_DST_PORT);
1417
1418                                 udp->dgram_len = rte_cpu_to_be_16
1419                                         (I40E_FDIR_UDP_DEFAULT_LEN);
1420                                 esp = (struct rte_flow_item_esp *)
1421                                         ((unsigned char *)esp_ipv6 +
1422                                                 sizeof(struct rte_udp_hdr));
1423                                 esp->hdr.spi =
1424                                         fdir_input->flow.esp_ipv6_udp_flow.spi;
1425                                 payload = (unsigned char *)esp +
1426                                         sizeof(struct rte_esp_hdr);
1427                                 len += sizeof(struct rte_udp_hdr) +
1428                                                 sizeof(struct rte_esp_hdr);
1429                         }
1430                 }
1431         } else {
1432                 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1433                 return -1;
1434         }
1435
1436         /* fill the flexbytes to payload */
1437         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1438                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1439                 size = pf->fdir.flex_set[pit_idx].size;
1440                 if (size == 0)
1441                         continue;
1442                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1443                 ptr = payload +
1444                       pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1445                 (void)rte_memcpy(ptr,
1446                                  &fdir_input->flow_ext.flexbytes[dst],
1447                                  size * sizeof(uint16_t));
1448         }
1449
1450         return 0;
1451 }
1452
1453 /* Construct the tx flags */
1454 static inline uint64_t
1455 i40e_build_ctob(uint32_t td_cmd,
1456                 uint32_t td_offset,
1457                 unsigned int size,
1458                 uint32_t td_tag)
1459 {
1460         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1461                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
1462                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1463                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1464                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
1465 }
1466
1467 /*
1468  * check the programming status descriptor in rx queue.
1469  * done after Programming Flow Director is programmed on
1470  * tx queue
1471  */
1472 static inline int
1473 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1474 {
1475         volatile union i40e_rx_desc *rxdp;
1476         uint64_t qword1;
1477         uint32_t rx_status;
1478         uint32_t len, id;
1479         uint32_t error;
1480         int ret = 0;
1481
1482         rxdp = &rxq->rx_ring[rxq->rx_tail];
1483         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1484         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1485                         >> I40E_RXD_QW1_STATUS_SHIFT;
1486
1487         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1488                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1489                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1490                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1491
1492                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1493                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1494                         error = (qword1 &
1495                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1496                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1497                         if (error == (0x1 <<
1498                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1499                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1500                                             " (FD_ID %u): programming status"
1501                                             " reported.",
1502                                             rxdp->wb.qword0.hi_dword.fd_id);
1503                                 ret = -1;
1504                         } else if (error == (0x1 <<
1505                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1506                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1507                                             " (FD_ID %u): programming status"
1508                                             " reported.",
1509                                             rxdp->wb.qword0.hi_dword.fd_id);
1510                                 ret = -1;
1511                         } else
1512                                 PMD_DRV_LOG(ERR, "invalid programming status"
1513                                             " reported, error = %u.", error);
1514                 } else
1515                         PMD_DRV_LOG(INFO, "unknown programming status"
1516                                     " reported, len = %d, id = %u.", len, id);
1517                 rxdp->wb.qword1.status_error_len = 0;
1518                 rxq->rx_tail++;
1519                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1520                         rxq->rx_tail = 0;
1521                 if (rxq->rx_tail == 0)
1522                         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1523                 else
1524                         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
1525         }
1526
1527         return ret;
1528 }
1529
1530 static int
1531 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1532                          struct i40e_fdir_filter *filter)
1533 {
1534         rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1535         if (input->input.flow_ext.pkt_template) {
1536                 filter->fdir.input.flow.raw_flow.packet = NULL;
1537                 filter->fdir.input.flow.raw_flow.length =
1538                         rte_hash_crc(input->input.flow.raw_flow.packet,
1539                                      input->input.flow.raw_flow.length,
1540                                      input->input.flow.raw_flow.pctype);
1541         }
1542         return 0;
1543 }
1544
1545 /* Check if there exists the flow director filter */
1546 static struct i40e_fdir_filter *
1547 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1548                         const struct i40e_fdir_input *input)
1549 {
1550         int ret;
1551
1552         if (input->flow_ext.pkt_template)
1553                 ret = rte_hash_lookup_with_hash(fdir_info->hash_table,
1554                                                 (const void *)input,
1555                                                 input->flow.raw_flow.length);
1556         else
1557                 ret = rte_hash_lookup(fdir_info->hash_table,
1558                                       (const void *)input);
1559         if (ret < 0)
1560                 return NULL;
1561
1562         return fdir_info->hash_map[ret];
1563 }
1564
1565 /* Add a flow director filter into the SW list */
1566 static int
1567 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1568 {
1569         struct i40e_fdir_info *fdir_info = &pf->fdir;
1570         int ret;
1571
1572         if (filter->fdir.input.flow_ext.pkt_template)
1573                 ret = rte_hash_add_key_with_hash(fdir_info->hash_table,
1574                                  &filter->fdir.input,
1575                                  filter->fdir.input.flow.raw_flow.length);
1576         else
1577                 ret = rte_hash_add_key(fdir_info->hash_table,
1578                                        &filter->fdir.input);
1579         if (ret < 0) {
1580                 PMD_DRV_LOG(ERR,
1581                             "Failed to insert fdir filter to hash table %d!",
1582                             ret);
1583                 return ret;
1584         }
1585         fdir_info->hash_map[ret] = filter;
1586
1587         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1588
1589         return 0;
1590 }
1591
1592 /* Delete a flow director filter from the SW list */
1593 int
1594 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1595 {
1596         struct i40e_fdir_info *fdir_info = &pf->fdir;
1597         struct i40e_fdir_filter *filter;
1598         int ret;
1599
1600         if (input->flow_ext.pkt_template)
1601                 ret = rte_hash_del_key_with_hash(fdir_info->hash_table,
1602                                                  input,
1603                                                  input->flow.raw_flow.length);
1604         else
1605                 ret = rte_hash_del_key(fdir_info->hash_table, input);
1606         if (ret < 0) {
1607                 PMD_DRV_LOG(ERR,
1608                             "Failed to delete fdir filter to hash table %d!",
1609                             ret);
1610                 return ret;
1611         }
1612         filter = fdir_info->hash_map[ret];
1613         fdir_info->hash_map[ret] = NULL;
1614
1615         TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1616         rte_free(filter);
1617
1618         return 0;
1619 }
1620
1621 /*
1622  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1623  * @pf: board private structure
1624  * @filter: fdir filter entry
1625  * @add: 0 - delete, 1 - add
1626  */
1627 int
1628 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1629                          const struct rte_eth_fdir_filter *filter,
1630                          bool add)
1631 {
1632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1634         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1635         enum i40e_filter_pctype pctype;
1636         int ret = 0;
1637
1638         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1639                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1640                         " check the mode in fdir_conf.");
1641                 return -ENOTSUP;
1642         }
1643
1644         pctype = i40e_flowtype_to_pctype(pf->adapter, filter->input.flow_type);
1645         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
1646                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1647                 return -EINVAL;
1648         }
1649         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1650                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1651                 return -EINVAL;
1652         }
1653         if (filter->input.flow_ext.is_vf &&
1654                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1655                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1656                 return -EINVAL;
1657         }
1658
1659         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1660
1661         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1662         if (ret < 0) {
1663                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1664                 return ret;
1665         }
1666
1667         if (hw->mac.type == I40E_MAC_X722) {
1668                 /* get translated pctype value in fd pctype register */
1669                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1670                         hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1671         }
1672
1673         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1674         if (ret < 0) {
1675                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1676                             pctype);
1677                 return ret;
1678         }
1679
1680         return ret;
1681 }
1682
1683 /**
1684  * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1685  * @pf: board private structure
1686  * @filter: fdir filter entry
1687  * @add: 0 - delete, 1 - add
1688  */
1689 int
1690 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1691                               const struct i40e_fdir_filter_conf *filter,
1692                               bool add)
1693 {
1694         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1695         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1696         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1697         enum i40e_filter_pctype pctype;
1698         struct i40e_fdir_info *fdir_info = &pf->fdir;
1699         struct i40e_fdir_filter *fdir_filter, *node;
1700         struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1701         int ret = 0;
1702
1703         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1704                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please check the mode in fdir_conf.");
1705                 return -ENOTSUP;
1706         }
1707
1708         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1709                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1710                 return -EINVAL;
1711         }
1712         if (filter->input.flow_ext.is_vf &&
1713             filter->input.flow_ext.dst_id >= pf->vf_num) {
1714                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1715                 return -EINVAL;
1716         }
1717         if (filter->input.flow_ext.pkt_template) {
1718                 if (filter->input.flow.raw_flow.length > I40E_FDIR_PKT_LEN ||
1719                     !filter->input.flow.raw_flow.packet) {
1720                         PMD_DRV_LOG(ERR, "Invalid raw packet template"
1721                                 " flow filter parameters!");
1722                         return -EINVAL;
1723                 }
1724                 pctype = filter->input.flow.raw_flow.pctype;
1725         } else {
1726                 pctype = filter->input.pctype;
1727         }
1728
1729         /* Check if there is the filter in SW list */
1730         memset(&check_filter, 0, sizeof(check_filter));
1731         i40e_fdir_filter_convert(filter, &check_filter);
1732         node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1733         if (add && node) {
1734                 PMD_DRV_LOG(ERR,
1735                             "Conflict with existing flow director rules!");
1736                 return -EINVAL;
1737         }
1738
1739         if (!add && !node) {
1740                 PMD_DRV_LOG(ERR,
1741                             "There's no corresponding flow firector filter!");
1742                 return -EINVAL;
1743         }
1744
1745         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1746
1747         ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1748         if (ret < 0) {
1749                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1750                 return ret;
1751         }
1752
1753         if (hw->mac.type == I40E_MAC_X722) {
1754                 /* get translated pctype value in fd pctype register */
1755                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1756                         hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1757         }
1758
1759         ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add);
1760         if (ret < 0) {
1761                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1762                             pctype);
1763                 return ret;
1764         }
1765
1766         if (add) {
1767                 fdir_filter = rte_zmalloc("fdir_filter",
1768                                           sizeof(*fdir_filter), 0);
1769                 if (fdir_filter == NULL) {
1770                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
1771                         return -ENOMEM;
1772                 }
1773
1774                 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1775                 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1776                 if (ret < 0)
1777                         rte_free(fdir_filter);
1778         } else {
1779                 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1780         }
1781
1782         return ret;
1783 }
1784
1785 /*
1786  * i40e_fdir_filter_programming - Program a flow director filter rule.
1787  * Is done by Flow Director Programming Descriptor followed by packet
1788  * structure that contains the filter fields need to match.
1789  * @pf: board private structure
1790  * @pctype: pctype
1791  * @filter: fdir filter entry
1792  * @add: 0 - delete, 1 - add
1793  */
1794 static int
1795 i40e_fdir_filter_programming(struct i40e_pf *pf,
1796                         enum i40e_filter_pctype pctype,
1797                         const struct rte_eth_fdir_filter *filter,
1798                         bool add)
1799 {
1800         struct i40e_tx_queue *txq = pf->fdir.txq;
1801         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1802         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1803         volatile struct i40e_tx_desc *txdp;
1804         volatile struct i40e_filter_program_desc *fdirdp;
1805         uint32_t td_cmd;
1806         uint16_t vsi_id, i;
1807         uint8_t dest;
1808
1809         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1810         fdirdp = (volatile struct i40e_filter_program_desc *)
1811                         (&(txq->tx_ring[txq->tx_tail]));
1812
1813         fdirdp->qindex_flex_ptype_vsi =
1814                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1815                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1816                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1817
1818         fdirdp->qindex_flex_ptype_vsi |=
1819                         rte_cpu_to_le_32((fdir_action->flex_off <<
1820                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1821                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1822
1823         fdirdp->qindex_flex_ptype_vsi |=
1824                         rte_cpu_to_le_32((pctype <<
1825                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1826                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1827
1828         if (filter->input.flow_ext.is_vf)
1829                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1830         else
1831                 /* Use LAN VSI Id by default */
1832                 vsi_id = pf->main_vsi->vsi_id;
1833         fdirdp->qindex_flex_ptype_vsi |=
1834                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1835                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1836                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1837
1838         fdirdp->dtype_cmd_cntindex =
1839                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1840
1841         if (add)
1842                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1843                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1844                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1845         else
1846                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1847                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1848                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1849
1850         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1851                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1852         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1853                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1854         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1855                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1856         else {
1857                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1858                             " unsupported fdir behavior.");
1859                 return -EINVAL;
1860         }
1861
1862         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1863                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1864                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1865
1866         fdirdp->dtype_cmd_cntindex |=
1867                 rte_cpu_to_le_32((fdir_action->report_status<<
1868                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1869                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1870
1871         fdirdp->dtype_cmd_cntindex |=
1872                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1873         fdirdp->dtype_cmd_cntindex |=
1874                         rte_cpu_to_le_32(
1875                         ((uint32_t)pf->fdir.match_counter_index <<
1876                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1877                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1878
1879         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1880
1881         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1882         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1883         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1884         td_cmd = I40E_TX_DESC_CMD_EOP |
1885                  I40E_TX_DESC_CMD_RS  |
1886                  I40E_TX_DESC_CMD_DUMMY;
1887
1888         txdp->cmd_type_offset_bsz =
1889                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1890
1891         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1892         if (txq->tx_tail >= txq->nb_tx_desc)
1893                 txq->tx_tail = 0;
1894         /* Update the tx tail register */
1895         rte_wmb();
1896         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1897         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1898                 if ((txdp->cmd_type_offset_bsz &
1899                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1900                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1901                         break;
1902                 rte_delay_us(1);
1903         }
1904         if (i >= I40E_FDIR_MAX_WAIT_US) {
1905                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1906                             " time out to get DD on tx queue.");
1907                 return -ETIMEDOUT;
1908         }
1909         /* totally delay 10 ms to check programming status*/
1910         for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1911                 if (i40e_check_fdir_programming_status(rxq) >= 0)
1912                         return 0;
1913                 rte_delay_us(1);
1914         }
1915         PMD_DRV_LOG(ERR,
1916                 "Failed to program FDIR filter: programming status reported.");
1917         return -ETIMEDOUT;
1918 }
1919
1920 /*
1921  * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
1922  * Is done by Flow Director Programming Descriptor followed by packet
1923  * structure that contains the filter fields need to match.
1924  * @pf: board private structure
1925  * @pctype: pctype
1926  * @filter: fdir filter entry
1927  * @add: 0 - delete, 1 - add
1928  */
1929 static int
1930 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
1931                                   enum i40e_filter_pctype pctype,
1932                                   const struct i40e_fdir_filter_conf *filter,
1933                                   bool add)
1934 {
1935         struct i40e_tx_queue *txq = pf->fdir.txq;
1936         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1937         const struct i40e_fdir_action *fdir_action = &filter->action;
1938         volatile struct i40e_tx_desc *txdp;
1939         volatile struct i40e_filter_program_desc *fdirdp;
1940         uint32_t td_cmd;
1941         uint16_t vsi_id, i;
1942         uint8_t dest;
1943
1944         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1945         fdirdp = (volatile struct i40e_filter_program_desc *)
1946                                 (&txq->tx_ring[txq->tx_tail]);
1947
1948         fdirdp->qindex_flex_ptype_vsi =
1949                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1950                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1951                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1952
1953         fdirdp->qindex_flex_ptype_vsi |=
1954                         rte_cpu_to_le_32((fdir_action->flex_off <<
1955                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1956                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1957
1958         fdirdp->qindex_flex_ptype_vsi |=
1959                         rte_cpu_to_le_32((pctype <<
1960                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1961                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1962
1963         if (filter->input.flow_ext.is_vf)
1964                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1965         else
1966                 /* Use LAN VSI Id by default */
1967                 vsi_id = pf->main_vsi->vsi_id;
1968         fdirdp->qindex_flex_ptype_vsi |=
1969                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1970                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1971                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1972
1973         fdirdp->dtype_cmd_cntindex =
1974                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1975
1976         if (add)
1977                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1978                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1979                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1980         else
1981                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1982                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1983                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1984
1985         if (fdir_action->behavior == I40E_FDIR_REJECT)
1986                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1987         else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
1988                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1989         else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
1990                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1991         else {
1992                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
1993                 return -EINVAL;
1994         }
1995
1996         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1997                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1998                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1999
2000         fdirdp->dtype_cmd_cntindex |=
2001                 rte_cpu_to_le_32((fdir_action->report_status <<
2002                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
2003                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
2004
2005         fdirdp->dtype_cmd_cntindex |=
2006                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
2007         fdirdp->dtype_cmd_cntindex |=
2008                         rte_cpu_to_le_32(
2009                         ((uint32_t)pf->fdir.match_counter_index <<
2010                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2011                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
2012
2013         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
2014
2015         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
2016         txdp = &txq->tx_ring[txq->tx_tail + 1];
2017         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
2018         td_cmd = I40E_TX_DESC_CMD_EOP |
2019                  I40E_TX_DESC_CMD_RS  |
2020                  I40E_TX_DESC_CMD_DUMMY;
2021
2022         txdp->cmd_type_offset_bsz =
2023                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
2024
2025         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
2026         if (txq->tx_tail >= txq->nb_tx_desc)
2027                 txq->tx_tail = 0;
2028         /* Update the tx tail register */
2029         rte_wmb();
2030         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2031         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
2032                 if ((txdp->cmd_type_offset_bsz &
2033                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
2034                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
2035                         break;
2036                 rte_delay_us(1);
2037         }
2038         if (i >= I40E_FDIR_MAX_WAIT_US) {
2039                 PMD_DRV_LOG(ERR,
2040                     "Failed to program FDIR filter: time out to get DD on tx queue.");
2041                 return -ETIMEDOUT;
2042         }
2043         /* totally delay 10 ms to check programming status*/
2044         rte_delay_us(I40E_FDIR_MAX_WAIT_US);
2045         if (i40e_check_fdir_programming_status(rxq) < 0) {
2046                 PMD_DRV_LOG(ERR,
2047                     "Failed to program FDIR filter: programming status reported.");
2048                 return -ETIMEDOUT;
2049         }
2050
2051         return 0;
2052 }
2053
2054 /*
2055  * i40e_fdir_flush - clear all filters of Flow Director table
2056  * @pf: board private structure
2057  */
2058 int
2059 i40e_fdir_flush(struct rte_eth_dev *dev)
2060 {
2061         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2062         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2063         uint32_t reg;
2064         uint16_t guarant_cnt, best_cnt;
2065         uint16_t i;
2066
2067         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
2068         I40E_WRITE_FLUSH(hw);
2069
2070         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
2071                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
2072                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
2073                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
2074                         break;
2075         }
2076         if (i >= I40E_FDIR_FLUSH_RETRY) {
2077                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
2078                 return -ETIMEDOUT;
2079         }
2080         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
2081                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2082                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2083         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
2084                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2085                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2086         if (guarant_cnt != 0 || best_cnt != 0) {
2087                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
2088                 return -ENOSYS;
2089         } else
2090                 PMD_DRV_LOG(INFO, "FD table Flush success.");
2091         return 0;
2092 }
2093
2094 static inline void
2095 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
2096                         struct rte_eth_flex_payload_cfg *flex_set,
2097                         uint16_t *num)
2098 {
2099         struct i40e_fdir_flex_pit *flex_pit;
2100         struct rte_eth_flex_payload_cfg *ptr = flex_set;
2101         uint16_t src, dst, size, j, k;
2102         uint8_t i, layer_idx;
2103
2104         for (layer_idx = I40E_FLXPLD_L2_IDX;
2105              layer_idx <= I40E_FLXPLD_L4_IDX;
2106              layer_idx++) {
2107                 if (layer_idx == I40E_FLXPLD_L2_IDX)
2108                         ptr->type = RTE_ETH_L2_PAYLOAD;
2109                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
2110                         ptr->type = RTE_ETH_L3_PAYLOAD;
2111                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
2112                         ptr->type = RTE_ETH_L4_PAYLOAD;
2113
2114                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
2115                         flex_pit = &pf->fdir.flex_set[layer_idx *
2116                                 I40E_MAX_FLXPLD_FIED + i];
2117                         if (flex_pit->size == 0)
2118                                 continue;
2119                         src = flex_pit->src_offset * sizeof(uint16_t);
2120                         dst = flex_pit->dst_offset * sizeof(uint16_t);
2121                         size = flex_pit->size * sizeof(uint16_t);
2122                         for (j = src, k = dst; j < src + size; j++, k++)
2123                                 ptr->src_offset[k] = j;
2124                 }
2125                 (*num)++;
2126                 ptr++;
2127         }
2128 }
2129
2130 static inline void
2131 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
2132                         struct rte_eth_fdir_flex_mask *flex_mask,
2133                         uint16_t *num)
2134 {
2135         struct i40e_fdir_flex_mask *mask;
2136         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
2137         uint16_t flow_type;
2138         uint8_t i, j;
2139         uint16_t off_bytes, mask_tmp;
2140
2141         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2142              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
2143              i++) {
2144                 mask =  &pf->fdir.flex_mask[i];
2145                 flow_type = i40e_pctype_to_flowtype(pf->adapter,
2146                                                     (enum i40e_filter_pctype)i);
2147                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
2148                         continue;
2149
2150                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
2151                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
2152                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
2153                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
2154                         } else {
2155                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
2156                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
2157                         }
2158                 }
2159                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
2160                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
2161                         mask_tmp = ~mask->bitmask[j].mask;
2162                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
2163                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
2164                 }
2165                 ptr->flow_type = flow_type;
2166                 ptr++;
2167                 (*num)++;
2168         }
2169 }
2170
2171 /*
2172  * i40e_fdir_info_get - get information of Flow Director
2173  * @pf: ethernet device to get info from
2174  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
2175  *    the flow director information.
2176  */
2177 static void
2178 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
2179 {
2180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2181         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2182         uint16_t num_flex_set = 0;
2183         uint16_t num_flex_mask = 0;
2184         uint16_t i;
2185
2186         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
2187                 fdir->mode = RTE_FDIR_MODE_PERFECT;
2188         else
2189                 fdir->mode = RTE_FDIR_MODE_NONE;
2190
2191         fdir->guarant_spc =
2192                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
2193         fdir->best_spc =
2194                 (uint32_t)hw->func_caps.fd_filters_best_effort;
2195         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
2196         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
2197         for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
2198                 fdir->flow_types_mask[i] = 0ULL;
2199         fdir->flex_payload_unit = sizeof(uint16_t);
2200         fdir->flex_bitmask_unit = sizeof(uint16_t);
2201         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
2202         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
2203         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
2204
2205         i40e_fdir_info_get_flex_set(pf,
2206                                 fdir->flex_conf.flex_set,
2207                                 &num_flex_set);
2208         i40e_fdir_info_get_flex_mask(pf,
2209                                 fdir->flex_conf.flex_mask,
2210                                 &num_flex_mask);
2211
2212         fdir->flex_conf.nb_payloads = num_flex_set;
2213         fdir->flex_conf.nb_flexmasks = num_flex_mask;
2214 }
2215
2216 /*
2217  * i40e_fdir_stat_get - get statistics of Flow Director
2218  * @pf: ethernet device to get info from
2219  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
2220  *    the flow director statistics.
2221  */
2222 static void
2223 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
2224 {
2225         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2226         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2227         uint32_t fdstat;
2228
2229         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2230         stat->guarant_cnt =
2231                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2232                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2233         stat->best_cnt =
2234                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2235                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2236 }
2237
2238 static int
2239 i40e_fdir_filter_set(struct rte_eth_dev *dev,
2240                      struct rte_eth_fdir_filter_info *info)
2241 {
2242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2243         int ret = 0;
2244
2245         if (!info) {
2246                 PMD_DRV_LOG(ERR, "Invalid pointer");
2247                 return -EFAULT;
2248         }
2249
2250         switch (info->info_type) {
2251         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
2252                 ret = i40e_fdir_filter_inset_select(pf,
2253                                 &(info->info.input_set_conf));
2254                 break;
2255         default:
2256                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
2257                             info->info_type);
2258                 return -EINVAL;
2259         }
2260
2261         return ret;
2262 }
2263
2264 /*
2265  * i40e_fdir_ctrl_func - deal with all operations on flow director.
2266  * @pf: board private structure
2267  * @filter_op:operation will be taken.
2268  * @arg: a pointer to specific structure corresponding to the filter_op
2269  */
2270 int
2271 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
2272                        enum rte_filter_op filter_op,
2273                        void *arg)
2274 {
2275         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276         int ret = 0;
2277
2278         if ((pf->flags & I40E_FLAG_FDIR) == 0)
2279                 return -ENOTSUP;
2280
2281         if (filter_op == RTE_ETH_FILTER_NOP)
2282                 return 0;
2283
2284         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2285                 return -EINVAL;
2286
2287         switch (filter_op) {
2288         case RTE_ETH_FILTER_ADD:
2289                 ret = i40e_add_del_fdir_filter(dev,
2290                         (struct rte_eth_fdir_filter *)arg,
2291                         TRUE);
2292                 break;
2293         case RTE_ETH_FILTER_DELETE:
2294                 ret = i40e_add_del_fdir_filter(dev,
2295                         (struct rte_eth_fdir_filter *)arg,
2296                         FALSE);
2297                 break;
2298         case RTE_ETH_FILTER_FLUSH:
2299                 ret = i40e_fdir_flush(dev);
2300                 break;
2301         case RTE_ETH_FILTER_INFO:
2302                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
2303                 break;
2304         case RTE_ETH_FILTER_SET:
2305                 ret = i40e_fdir_filter_set(dev,
2306                         (struct rte_eth_fdir_filter_info *)arg);
2307                 break;
2308         case RTE_ETH_FILTER_STATS:
2309                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
2310                 break;
2311         default:
2312                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
2313                 ret = -EINVAL;
2314                 break;
2315         }
2316         return ret;
2317 }
2318
2319 /* Restore flow director filter */
2320 void
2321 i40e_fdir_filter_restore(struct i40e_pf *pf)
2322 {
2323         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2324         struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2325         struct i40e_fdir_filter *f;
2326         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2327         uint32_t fdstat;
2328         uint32_t guarant_cnt;  /**< Number of filters in guaranteed spaces. */
2329         uint32_t best_cnt;     /**< Number of filters in best effort spaces. */
2330
2331         TAILQ_FOREACH(f, fdir_list, rules)
2332                 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2333
2334         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2335         guarant_cnt =
2336                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2337                            I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2338         best_cnt =
2339                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2340                            I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2341
2342         PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d,  Best count: %d",
2343                     guarant_cnt, best_cnt);
2344 }