drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_arp.h>
  48 #include <rte_ip.h>
  49 #include <rte_udp.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52
  53 #include "i40e_logs.h"
  54 #include "base/i40e_type.h"
  55 #include "i40e_ethdev.h"
  56 #include "i40e_rxtx.h"
  57
  58 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  59 #ifndef IPV6_ADDR_LEN
  60 #define IPV6_ADDR_LEN              16
  61 #endif
  62
  63 #define I40E_FDIR_PKT_LEN                   512
  64 #define I40E_FDIR_IP_DEFAULT_LEN            420
  65 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  66 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  67 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  68 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60300000
  69 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  70 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  71 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  72
  73 /* Wait count and interval for fdir filter programming */
  74 #define I40E_FDIR_WAIT_COUNT       10
  75 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  76
  77 /* Wait count and interval for fdir filter flush */
  78 #define I40E_FDIR_FLUSH_RETRY       50
  79 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  80
  81 #define I40E_COUNTER_PF           2
  82 /* Statistic counter index for one pf */
  83 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  84 #define I40E_MAX_FLX_SOURCE_OFF           480
  85 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  86
  87 #define NONUSE_FLX_PIT_DEST_OFF 63
  88 #define NONUSE_FLX_PIT_FSIZE    1
  89 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  90         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  91                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  92         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  93                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  94         ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
  95                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
  96                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
  97
  98 #define I40E_FDIR_FLOWS ( \
  99         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
 100         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 101         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 102         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 103         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 104         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
 105         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 106         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 107         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 108         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 109         (1 << RTE_ETH_FLOW_L2_PAYLOAD))
 110
 111 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 112
 113 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);
 114 static int i40e_check_fdir_flex_conf(
 115         const struct rte_eth_fdir_flex_conf *conf);
 116 static void i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 117                          const struct rte_eth_flex_payload_cfg *cfg);
 118 static void i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 119                 enum i40e_filter_pctype pctype,
 120                 const struct rte_eth_fdir_flex_mask *mask_cfg);
 121 static int i40e_fdir_construct_pkt(struct i40e_pf *pf,
 122                                      const struct rte_eth_fdir_input *fdir_input,
 123                                      unsigned char *raw_pkt);
 124 static int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 125                             const struct rte_eth_fdir_filter *filter,
 126                             bool add);
 127 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 128                         enum i40e_filter_pctype pctype,
 129                         const struct rte_eth_fdir_filter *filter,
 130                         bool add);
 131 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 132 static void i40e_fdir_info_get(struct rte_eth_dev *dev,
 133                            struct rte_eth_fdir_info *fdir);
 134 static void i40e_fdir_stats_get(struct rte_eth_dev *dev,
 135                            struct rte_eth_fdir_stats *stat);
 136
 137 static int
 138 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 139 {
 140         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 141         struct i40e_hmc_obj_rxq rx_ctx;
 142         int err = I40E_SUCCESS;
 143
 144         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 145         /* Init the RX queue in hardware */
 146         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 147         rx_ctx.hbuff = 0;
 148         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 149         rx_ctx.qlen = rxq->nb_rx_desc;
 150 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 151         rx_ctx.dsize = 1;
 152 #endif
 153         rx_ctx.dtype = i40e_header_split_none;
 154         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 155         rx_ctx.rxmax = ETHER_MAX_LEN;
 156         rx_ctx.tphrdesc_ena = 1;
 157         rx_ctx.tphwdesc_ena = 1;
 158         rx_ctx.tphdata_ena = 1;
 159         rx_ctx.tphhead_ena = 1;
 160         rx_ctx.lrxqthresh = 2;
 161         rx_ctx.crcstrip = 0;
 162         rx_ctx.l2tsel = 1;
 163         rx_ctx.showiv = 1;
 164         rx_ctx.prefena = 1;
 165
 166         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 167         if (err != I40E_SUCCESS) {
 168                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 169                 return err;
 170         }
 171         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 172         if (err != I40E_SUCCESS) {
 173                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 174                 return err;
 175         }
 176         rxq->qrx_tail = hw->hw_addr +
 177                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 178
 179         rte_wmb();
 180         /* Init the RX tail regieter. */
 181         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 182         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 183
 184         return err;
 185 }
 186
 187 /*
 188  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 189  * @pf: board private structure
 190  */
 191 int
 192 i40e_fdir_setup(struct i40e_pf *pf)
 193 {
 194         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 195         struct i40e_vsi *vsi;
 196         int err = I40E_SUCCESS;
 197         char z_name[RTE_MEMZONE_NAMESIZE];
 198         const struct rte_memzone *mz = NULL;
 199         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 200
 201         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 202                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 203                 return I40E_NOT_SUPPORTED;
 204         }
 205
 206         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 207                         " num_filters_best_effort = %u.",
 208                         hw->func_caps.fd_filters_guaranteed,
 209                         hw->func_caps.fd_filters_best_effort);
 210
 211         vsi = pf->fdir.fdir_vsi;
 212         if (vsi) {
 213                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 214                 return I40E_SUCCESS;
 215         }
 216         /* make new FDIR VSI */
 217         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 218         if (!vsi) {
 219                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 220                 return I40E_ERR_NO_AVAILABLE_VSI;
 221         }
 222         pf->fdir.fdir_vsi = vsi;
 223
 224         /*Fdir tx queue setup*/
 225         err = i40e_fdir_setup_tx_resources(pf);
 226         if (err) {
 227                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 228                 goto fail_setup_tx;
 229         }
 230
 231         /*Fdir rx queue setup*/
 232         err = i40e_fdir_setup_rx_resources(pf);
 233         if (err) {
 234                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 235                 goto fail_setup_rx;
 236         }
 237
 238         err = i40e_tx_queue_init(pf->fdir.txq);
 239         if (err) {
 240                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 241                 goto fail_mem;
 242         }
 243
 244         /* need switch on before dev start*/
 245         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 246         if (err) {
 247                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 248                 goto fail_mem;
 249         }
 250
 251         /* Init the rx queue in hardware */
 252         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 253         if (err) {
 254                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 255                 goto fail_mem;
 256         }
 257
 258         /* switch on rx queue */
 259         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 260         if (err) {
 261                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 262                 goto fail_mem;
 263         }
 264
 265         /* reserve memory for the fdir programming packet */
 266         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 267                         eth_dev->driver->pci_drv.name,
 268                         I40E_FDIR_MZ_NAME,
 269                         eth_dev->data->port_id);
 270         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 271         if (!mz) {
 272                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 273                                  "flow director program packet.");
 274                 err = I40E_ERR_NO_MEMORY;
 275                 goto fail_mem;
 276         }
 277         pf->fdir.prg_pkt = mz->addr;
 278         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 279
 280         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 281         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 282                     vsi->base_queue);
 283         return I40E_SUCCESS;
 284
 285 fail_mem:
 286         i40e_dev_rx_queue_release(pf->fdir.rxq);
 287         pf->fdir.rxq = NULL;
 288 fail_setup_rx:
 289         i40e_dev_tx_queue_release(pf->fdir.txq);
 290         pf->fdir.txq = NULL;
 291 fail_setup_tx:
 292         i40e_vsi_release(vsi);
 293         pf->fdir.fdir_vsi = NULL;
 294         return err;
 295 }
 296
 297 /*
 298  * i40e_fdir_teardown - release the Flow Director resources
 299  * @pf: board private structure
 300  */
 301 void
 302 i40e_fdir_teardown(struct i40e_pf *pf)
 303 {
 304         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 305         struct i40e_vsi *vsi;
 306
 307         vsi = pf->fdir.fdir_vsi;
 308         if (!vsi)
 309                 return;
 310         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 311         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 312         i40e_dev_rx_queue_release(pf->fdir.rxq);
 313         pf->fdir.rxq = NULL;
 314         i40e_dev_tx_queue_release(pf->fdir.txq);
 315         pf->fdir.txq = NULL;
 316         i40e_vsi_release(vsi);
 317         pf->fdir.fdir_vsi = NULL;
 318 }
 319
 320 /* check whether the flow director table in empty */
 321 static inline int
 322 i40e_fdir_empty(struct i40e_hw *hw)
 323 {
 324         uint32_t guarant_cnt, best_cnt;
 325
 326         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 327                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 328                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 329         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 330                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 331                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 332         if (best_cnt + guarant_cnt > 0)
 333                 return -1;
 334
 335         return 0;
 336 }
 337
 338 /*
 339  * Initialize the configuration about bytes stream extracted as flexible payload
 340  * and mask setting
 341  */
 342 static inline void
 343 i40e_init_flx_pld(struct i40e_pf *pf)
 344 {
 345         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 346         uint8_t pctype;
 347         int i, index;
 348
 349         /*
 350          * Define the bytes stream extracted as flexible payload in
 351          * field vector. By default, select 8 words from the beginning
 352          * of payload as flexible payload.
 353          */
 354         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 355                 index = i * I40E_MAX_FLXPLD_FIED;
 356                 pf->fdir.flex_set[index].src_offset = 0;
 357                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 358                 pf->fdir.flex_set[index].dst_offset = 0;
 359                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 360                 I40E_WRITE_REG(hw,
 361                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 362                 I40E_WRITE_REG(hw,
 363                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 364         }
 365
 366         /* initialize the masks */
 367         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 368              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 369                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)pctype))
 370                         continue;
 371                 pf->fdir.flex_mask[pctype].word_mask = 0;
 372                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 373                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 374                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 375                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 376                         I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 377                 }
 378         }
 379 }
 380
 381 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 382
 383 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 384         if ((flex_pit2).src_offset < \
 385                 (flex_pit1).src_offset + (flex_pit1).size) { \
 386                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 387                         " less than than previous offset" \
 388                         " + previous FSIZE."); \
 389                 return -EINVAL; \
 390         } \
 391 } while (0)
 392
 393 /*
 394  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 395  * and the flex_pit will be sorted by it's src_offset value
 396  */
 397 static inline uint16_t
 398 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 399                         struct i40e_fdir_flex_pit *flex_pit)
 400 {
 401         uint16_t src_tmp, size, num = 0;
 402         uint16_t i, k, j = 0;
 403
 404         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 405                 size = 1;
 406                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 407                         if (src_offset[j + 1] == src_offset[j] + 1)
 408                                 size++;
 409                         else
 410                                 break;
 411                 }
 412                 src_tmp = src_offset[j] + 1 - size;
 413                 /* the flex_pit need to be sort by src_offset */
 414                 for (i = 0; i < num; i++) {
 415                         if (src_tmp < flex_pit[i].src_offset)
 416                                 break;
 417                 }
 418                 /* if insert required, move backward */
 419                 for (k = num; k > i; k--)
 420                         flex_pit[k] = flex_pit[k - 1];
 421                 /* insert */
 422                 flex_pit[i].dst_offset = j + 1 - size;
 423                 flex_pit[i].src_offset = src_tmp;
 424                 flex_pit[i].size = size;
 425                 j++;
 426                 num++;
 427         }
 428         return num;
 429 }
 430
 431 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 432 static inline int
 433 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 434 {
 435         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 436         uint16_t num, i;
 437
 438         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 439                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 440                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 441                         return -EINVAL;
 442                 }
 443         }
 444
 445         memset(flex_pit, 0, sizeof(flex_pit));
 446         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 447         if (num > I40E_MAX_FLXPLD_FIED) {
 448                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 449                 return -EINVAL;
 450         }
 451         for (i = 0; i < num; i++) {
 452                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 453                         flex_pit[i].src_offset & 0x01) {
 454                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 455                                 " in word");
 456                         return -EINVAL;
 457                 }
 458                 if (i != num - 1)
 459                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 460         }
 461         return 0;
 462 }
 463
 464 /*
 465  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 466  * arguments are valid
 467  */
 468 static int
 469 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 470 {
 471         const struct rte_eth_flex_payload_cfg *flex_cfg;
 472         const struct rte_eth_fdir_flex_mask *flex_mask;
 473         uint16_t mask_tmp;
 474         uint8_t nb_bitmask;
 475         uint16_t i, j;
 476         int ret = 0;
 477
 478         if (conf == NULL) {
 479                 PMD_DRV_LOG(INFO, "NULL pointer.");
 480                 return -EINVAL;
 481         }
 482         /* check flexible payload setting configuration */
 483         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 484                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 485                 return -EINVAL;
 486         }
 487         for (i = 0; i < conf->nb_payloads; i++) {
 488                 flex_cfg = &conf->flex_set[i];
 489                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 490                         PMD_DRV_LOG(ERR, "invalid payload type.");
 491                         return -EINVAL;
 492                 }
 493                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 494                 if (ret < 0) {
 495                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 496                         return -EINVAL;
 497                 }
 498         }
 499
 500         /* check flex mask setting configuration */
 501         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 502                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 503                 return -EINVAL;
 504         }
 505         for (i = 0; i < conf->nb_flexmasks; i++) {
 506                 flex_mask = &conf->flex_mask[i];
 507                 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
 508                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 509                         return -EINVAL;
 510                 }
 511                 nb_bitmask = 0;
 512                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 513                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 514                                              flex_mask->mask[j + 1]);
 515                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 516                                 nb_bitmask++;
 517                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 518                                         PMD_DRV_LOG(ERR, " exceed maximal"
 519                                                 " number of bitmasks.");
 520                                         return -EINVAL;
 521                                 }
 522                         }
 523                 }
 524         }
 525         return 0;
 526 }
 527
 528 /*
 529  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 530  * @pf: board private structure
 531  * @cfg: the rule how bytes stream is extracted as flexible payload
 532  */
 533 static void
 534 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 535                          const struct rte_eth_flex_payload_cfg *cfg)
 536 {
 537         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 538         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 539         uint32_t flx_pit;
 540         uint16_t num, min_next_off;  /* in words */
 541         uint8_t field_idx = 0;
 542         uint8_t layer_idx = 0;
 543         uint16_t i;
 544
 545         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 546                 layer_idx = I40E_FLXPLD_L2_IDX;
 547         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 548                 layer_idx = I40E_FLXPLD_L3_IDX;
 549         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 550                 layer_idx = I40E_FLXPLD_L4_IDX;
 551
 552         memset(flex_pit, 0, sizeof(flex_pit));
 553         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 554
 555         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 556                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 557                 /* record the info in fdir structure */
 558                 pf->fdir.flex_set[field_idx].src_offset =
 559                         flex_pit[i].src_offset / sizeof(uint16_t);
 560                 pf->fdir.flex_set[field_idx].size =
 561                         flex_pit[i].size / sizeof(uint16_t);
 562                 pf->fdir.flex_set[field_idx].dst_offset =
 563                         flex_pit[i].dst_offset / sizeof(uint16_t);
 564                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 565                                 pf->fdir.flex_set[field_idx].size,
 566                                 pf->fdir.flex_set[field_idx].dst_offset);
 567
 568                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 569         }
 570         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 571                                 pf->fdir.flex_set[field_idx].size;
 572
 573         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 574                 /* set the non-used register obeying register's constrain */
 575                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 576                            NONUSE_FLX_PIT_DEST_OFF);
 577                 I40E_WRITE_REG(hw,
 578                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 579                         flx_pit);
 580                 min_next_off++;
 581         }
 582 }
 583
 584 /*
 585  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 586  * @pf: board private structure
 587  * @pctype: packet classify type
 588  * @flex_masks: mask for flexible payload
 589  */
 590 static void
 591 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 592                 enum i40e_filter_pctype pctype,
 593                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 594 {
 595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 596         struct i40e_fdir_flex_mask *flex_mask;
 597         uint32_t flxinset, fd_mask;
 598         uint16_t mask_tmp;
 599         uint8_t i, nb_bitmask = 0;
 600
 601         flex_mask = &pf->fdir.flex_mask[pctype];
 602         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 603         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 604                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 605                 if (mask_tmp != 0x0) {
 606                         flex_mask->word_mask |=
 607                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 608                         if (mask_tmp != UINT16_MAX) {
 609                                 /* set bit mask */
 610                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 611                                 flex_mask->bitmask[nb_bitmask].offset =
 612                                         i / sizeof(uint16_t);
 613                                 nb_bitmask++;
 614                         }
 615                 }
 616         }
 617         /* write mask to hw */
 618         flxinset = (flex_mask->word_mask <<
 619                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 620                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 621         I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 622
 623         for (i = 0; i < nb_bitmask; i++) {
 624                 fd_mask = (flex_mask->bitmask[i].mask <<
 625                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 626                         I40E_PRTQF_FD_MSK_MASK_MASK;
 627                 fd_mask |= ((flex_mask->bitmask[i].offset +
 628                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 629                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 630                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 631                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 632         }
 633 }
 634
 635 /*
 636  * Configure flow director related setting
 637  */
 638 int
 639 i40e_fdir_configure(struct rte_eth_dev *dev)
 640 {
 641         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 642         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 643         struct rte_eth_fdir_flex_conf *conf;
 644         enum i40e_filter_pctype pctype;
 645         uint32_t val;
 646         uint8_t i;
 647         int ret = 0;
 648
 649         /*
 650         * configuration need to be done before
 651         * flow director filters are added
 652         * If filters exist, flush them.
 653         */
 654         if (i40e_fdir_empty(hw) < 0) {
 655                 ret = i40e_fdir_flush(dev);
 656                 if (ret) {
 657                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 658                         return ret;
 659                 }
 660         }
 661
 662         /* enable FDIR filter */
 663         val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
 664         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 665         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 666
 667         i40e_init_flx_pld(pf); /* set flex config to default value */
 668
 669         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 670         ret = i40e_check_fdir_flex_conf(conf);
 671         if (ret < 0) {
 672                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 673                 return -EINVAL;
 674         }
 675         /* configure flex payload */
 676         for (i = 0; i < conf->nb_payloads; i++)
 677                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 678         /* configure flex mask*/
 679         for (i = 0; i < conf->nb_flexmasks; i++) {
 680                 pctype = i40e_flowtype_to_pctype(conf->flex_mask[i].flow_type);
 681                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 682         }
 683
 684         return ret;
 685 }
 686
 687 static inline void
 688 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 689                                unsigned char *raw_pkt)
 690 {
 691         struct ether_hdr *ether = (struct ether_hdr *)raw_pkt;
 692         struct ipv4_hdr *ip;
 693         struct ipv6_hdr *ip6;
 694         static const uint8_t next_proto[] = {
 695                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 696                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 697                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 698                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 699                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 700                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 701                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 702                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 703                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 704                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 705         };
 706
 707         switch (fdir_input->flow_type) {
 708         case RTE_ETH_FLOW_L2_PAYLOAD:
 709                 ether->ether_type = fdir_input->flow.l2_flow.ether_type;
 710                 break;
 711         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 712         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 713         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 714         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 715         case RTE_ETH_FLOW_FRAG_IPV4:
 716                 ip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 717
 718                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 719                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 720                 /* set len to by default */
 721                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 722                 ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
 723                 /*
 724                  * The source and destination fields in the transmitted packet
 725                  * need to be presented in a reversed order with respect
 726                  * to the expected received packets.
 727                  */
 728                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 729                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 730                 ip->next_proto_id = next_proto[fdir_input->flow_type];
 731                 break;
 732         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 733         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 734         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 735         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 736         case RTE_ETH_FLOW_FRAG_IPV6:
 737                 ip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 738
 739                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 740                 ip6->vtc_flow =
 741                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
 742                 ip6->payload_len =
 743                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 744                 ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 745
 746                 /*
 747                  * The source and destination fields in the transmitted packet
 748                  * need to be presented in a reversed order with respect
 749                  * to the expected received packets.
 750                  */
 751                 rte_memcpy(&(ip6->src_addr),
 752                            &(fdir_input->flow.ipv6_flow.dst_ip),
 753                            IPV6_ADDR_LEN);
 754                 rte_memcpy(&(ip6->dst_addr),
 755                            &(fdir_input->flow.ipv6_flow.src_ip),
 756                            IPV6_ADDR_LEN);
 757                 ip6->proto = next_proto[fdir_input->flow_type];
 758                 break;
 759         default:
 760                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 761                             fdir_input->flow_type);
 762                 break;
 763         }
 764 }
 765
 766
 767 /*
 768  * i40e_fdir_construct_pkt - construct packet based on fields in input
 769  * @pf: board private structure
 770  * @fdir_input: input set of the flow director entry
 771  * @raw_pkt: a packet to be constructed
 772  */
 773 static int
 774 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 775                              const struct rte_eth_fdir_input *fdir_input,
 776                              unsigned char *raw_pkt)
 777 {
 778         unsigned char *payload, *ptr;
 779         struct udp_hdr *udp;
 780         struct tcp_hdr *tcp;
 781         struct sctp_hdr *sctp;
 782         uint8_t size, dst = 0;
 783         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 784
 785         /* fill the ethernet and IP head */
 786         i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);
 787
 788         /* fill the L4 head */
 789         switch (fdir_input->flow_type) {
 790         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 791                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 792                                 sizeof(struct ipv4_hdr));
 793                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 794                 /*
 795                  * The source and destination fields in the transmitted packet
 796                  * need to be presented in a reversed order with respect
 797                  * to the expected received packets.
 798                  */
 799                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 800                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 801                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 802                 break;
 803
 804         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 805                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 806                                          sizeof(struct ipv4_hdr));
 807                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 808                 /*
 809                  * The source and destination fields in the transmitted packet
 810                  * need to be presented in a reversed order with respect
 811                  * to the expected received packets.
 812                  */
 813                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 814                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 815                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 816                 break;
 817
 818         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 819                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 820                                            sizeof(struct ipv4_hdr));
 821                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 822                 /*
 823                  * The source and destination fields in the transmitted packet
 824                  * need to be presented in a reversed order with respect
 825                  * to the expected received packets.
 826                  */
 827                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 828                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 829                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 830                 break;
 831
 832         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 833         case RTE_ETH_FLOW_FRAG_IPV4:
 834                 payload = raw_pkt + sizeof(struct ether_hdr) +
 835                           sizeof(struct ipv4_hdr);
 836                 set_idx = I40E_FLXPLD_L3_IDX;
 837                 break;
 838
 839         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 840                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 841                                          sizeof(struct ipv6_hdr));
 842                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 843                 /*
 844                  * The source and destination fields in the transmitted packet
 845                  * need to be presented in a reversed order with respect
 846                  * to the expected received packets.
 847                  */
 848                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 849                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 850                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 851                 break;
 852
 853         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 854                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 855                                          sizeof(struct ipv6_hdr));
 856                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 857                 /*
 858                  * The source and destination fields in the transmitted packet
 859                  * need to be presented in a reversed order with respect
 860                  * to the expected received packets.
 861                  */
 862                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 863                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 864                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 865                 break;
 866
 867         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 868                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 869                                            sizeof(struct ipv6_hdr));
 870                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 871                 /*
 872                  * The source and destination fields in the transmitted packet
 873                  * need to be presented in a reversed order with respect
 874                  * to the expected received packets.
 875                  */
 876                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 877                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 878                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 879                 break;
 880
 881         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 882         case RTE_ETH_FLOW_FRAG_IPV6:
 883                 payload = raw_pkt + sizeof(struct ether_hdr) +
 884                           sizeof(struct ipv6_hdr);
 885                 set_idx = I40E_FLXPLD_L3_IDX;
 886                 break;
 887         case RTE_ETH_FLOW_L2_PAYLOAD:
 888                 payload = raw_pkt + sizeof(struct ether_hdr);
 889                 /*
 890                  * ARP packet is a special case on which the payload
 891                  * starts after the whole ARP header
 892                  */
 893                 if (fdir_input->flow.l2_flow.ether_type ==
 894                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 895                         payload += sizeof(struct arp_hdr);
 896                 set_idx = I40E_FLXPLD_L2_IDX;
 897                 break;
 898         default:
 899                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 900                 return -EINVAL;
 901         }
 902
 903         /* fill the flexbytes to payload */
 904         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 905                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 906                 size = pf->fdir.flex_set[pit_idx].size;
 907                 if (size == 0)
 908                         continue;
 909                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 910                 ptr = payload +
 911                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 912                 (void)rte_memcpy(ptr,
 913                                  &fdir_input->flow_ext.flexbytes[dst],
 914                                  size * sizeof(uint16_t));
 915         }
 916
 917         return 0;
 918 }
 919
 920 /* Construct the tx flags */
 921 static inline uint64_t
 922 i40e_build_ctob(uint32_t td_cmd,
 923                 uint32_t td_offset,
 924                 unsigned int size,
 925                 uint32_t td_tag)
 926 {
 927         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 928                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 929                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 930                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 931                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 932 }
 933
 934 /*
 935  * check the programming status descriptor in rx queue.
 936  * done after Programming Flow Director is programmed on
 937  * tx queue
 938  */
 939 static inline int
 940 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 941 {
 942         volatile union i40e_rx_desc *rxdp;
 943         uint64_t qword1;
 944         uint32_t rx_status;
 945         uint32_t len, id;
 946         uint32_t error;
 947         int ret = 0;
 948
 949         rxdp = &rxq->rx_ring[rxq->rx_tail];
 950         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 951         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 952                         >> I40E_RXD_QW1_STATUS_SHIFT;
 953
 954         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 955                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 956                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 957                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 958
 959                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 960                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 961                         error = (qword1 &
 962                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 963                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 964                         if (error == (0x1 <<
 965                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 966                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 967                                             " (FD_ID %u): programming status"
 968                                             " reported.",
 969                                             rxdp->wb.qword0.hi_dword.fd_id);
 970                                 ret = -1;
 971                         } else if (error == (0x1 <<
 972                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 973                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
 974                                             " (FD_ID %u): programming status"
 975                                             " reported.",
 976                                             rxdp->wb.qword0.hi_dword.fd_id);
 977                                 ret = -1;
 978                         } else
 979                                 PMD_DRV_LOG(ERR, "invalid programming status"
 980                                             " reported, error = %u.", error);
 981                 } else
 982                         PMD_DRV_LOG(ERR, "unknown programming status"
 983                                     " reported, len = %d, id = %u.", len, id);
 984                 rxdp->wb.qword1.status_error_len = 0;
 985                 rxq->rx_tail++;
 986                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
 987                         rxq->rx_tail = 0;
 988         }
 989         return ret;
 990 }
 991
 992 /*
 993  * i40e_add_del_fdir_filter - add or remove a flow director filter.
 994  * @pf: board private structure
 995  * @filter: fdir filter entry
 996  * @add: 0 - delete, 1 - add
 997  */
 998 static int
 999 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1000                             const struct rte_eth_fdir_filter *filter,
1001                             bool add)
1002 {
1003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1004         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1005         enum i40e_filter_pctype pctype;
1006         int ret = 0;
1007
1008         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1009                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1010                         " check the mode in fdir_conf.");
1011                 return -ENOTSUP;
1012         }
1013
1014         if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1015                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1016                 return -EINVAL;
1017         }
1018         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1019                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1020                 return -EINVAL;
1021         }
1022         if (filter->input.flow_ext.is_vf &&
1023                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1024                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1025                 return -EINVAL;
1026         }
1027
1028         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1029
1030         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1031         if (ret < 0) {
1032                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1033                 return ret;
1034         }
1035         pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1036         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1037         if (ret < 0) {
1038                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1039                             pctype);
1040                 return ret;
1041         }
1042         return ret;
1043 }
1044
1045 /*
1046  * i40e_fdir_filter_programming - Program a flow director filter rule.
1047  * Is done by Flow Director Programming Descriptor followed by packet
1048  * structure that contains the filter fields need to match.
1049  * @pf: board private structure
1050  * @pctype: pctype
1051  * @filter: fdir filter entry
1052  * @add: 0 - delelet, 1 - add
1053  */
1054 static int
1055 i40e_fdir_filter_programming(struct i40e_pf *pf,
1056                         enum i40e_filter_pctype pctype,
1057                         const struct rte_eth_fdir_filter *filter,
1058                         bool add)
1059 {
1060         struct i40e_tx_queue *txq = pf->fdir.txq;
1061         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1062         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1063         volatile struct i40e_tx_desc *txdp;
1064         volatile struct i40e_filter_program_desc *fdirdp;
1065         uint32_t td_cmd;
1066         uint16_t vsi_id, i;
1067         uint8_t dest;
1068
1069         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1070         fdirdp = (volatile struct i40e_filter_program_desc *)
1071                         (&(txq->tx_ring[txq->tx_tail]));
1072
1073         fdirdp->qindex_flex_ptype_vsi =
1074                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1075                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1076                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1077
1078         fdirdp->qindex_flex_ptype_vsi |=
1079                         rte_cpu_to_le_32((fdir_action->flex_off <<
1080                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1081                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1082
1083         fdirdp->qindex_flex_ptype_vsi |=
1084                         rte_cpu_to_le_32((pctype <<
1085                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1086                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1087
1088         if (filter->input.flow_ext.is_vf)
1089                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1090         else
1091                 /* Use LAN VSI Id by default */
1092                 vsi_id = pf->main_vsi->vsi_id;
1093         fdirdp->qindex_flex_ptype_vsi |=
1094                 rte_cpu_to_le_32((vsi_id <<
1095                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1096                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1097
1098         fdirdp->dtype_cmd_cntindex =
1099                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1100
1101         if (add)
1102                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1103                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1104                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1105         else
1106                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1107                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1108                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1109
1110         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1111                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1112         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1113                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1114         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1115                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1116         else {
1117                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1118                             " unsupported fdir behavior.");
1119                 return -EINVAL;
1120         }
1121
1122         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1123                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1124                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1125
1126         fdirdp->dtype_cmd_cntindex |=
1127                 rte_cpu_to_le_32((fdir_action->report_status<<
1128                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1129                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1130
1131         fdirdp->dtype_cmd_cntindex |=
1132                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1133         fdirdp->dtype_cmd_cntindex |=
1134                         rte_cpu_to_le_32((pf->fdir.match_counter_index <<
1135                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1136                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1137
1138         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1139
1140         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1141         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1142         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1143         td_cmd = I40E_TX_DESC_CMD_EOP |
1144                  I40E_TX_DESC_CMD_RS  |
1145                  I40E_TX_DESC_CMD_DUMMY;
1146
1147         txdp->cmd_type_offset_bsz =
1148                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1149
1150         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1151         if (txq->tx_tail >= txq->nb_tx_desc)
1152                 txq->tx_tail = 0;
1153         /* Update the tx tail register */
1154         rte_wmb();
1155         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1156
1157         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1158                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1159                 if ((txdp->cmd_type_offset_bsz &
1160                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1161                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1162                         break;
1163         }
1164         if (i >= I40E_FDIR_WAIT_COUNT) {
1165                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1166                             " time out to get DD on tx queue.");
1167                 return -ETIMEDOUT;
1168         }
1169         /* totally delay 10 ms to check programming status*/
1170         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1171         if (i40e_check_fdir_programming_status(rxq) < 0) {
1172                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1173                             " programming status reported.");
1174                 return -ENOSYS;
1175         }
1176
1177         return 0;
1178 }
1179
1180 /*
1181  * i40e_fdir_flush - clear all filters of Flow Director table
1182  * @pf: board private structure
1183  */
1184 static int
1185 i40e_fdir_flush(struct rte_eth_dev *dev)
1186 {
1187         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1188         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1189         uint32_t reg;
1190         uint16_t guarant_cnt, best_cnt;
1191         uint16_t i;
1192
1193         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1194         I40E_WRITE_FLUSH(hw);
1195
1196         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1197                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1198                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1199                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1200                         break;
1201         }
1202         if (i >= I40E_FDIR_FLUSH_RETRY) {
1203                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1204                 return -ETIMEDOUT;
1205         }
1206         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1207                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1208                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1209         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1210                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1211                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1212         if (guarant_cnt != 0 || best_cnt != 0) {
1213                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1214                 return -ENOSYS;
1215         } else
1216                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1217         return 0;
1218 }
1219
1220 static inline void
1221 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1222                         struct rte_eth_flex_payload_cfg *flex_set,
1223                         uint16_t *num)
1224 {
1225         struct i40e_fdir_flex_pit *flex_pit;
1226         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1227         uint16_t src, dst, size, j, k;
1228         uint8_t i, layer_idx;
1229
1230         for (layer_idx = I40E_FLXPLD_L2_IDX;
1231              layer_idx <= I40E_FLXPLD_L4_IDX;
1232              layer_idx++) {
1233                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1234                         ptr->type = RTE_ETH_L2_PAYLOAD;
1235                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1236                         ptr->type = RTE_ETH_L3_PAYLOAD;
1237                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1238                         ptr->type = RTE_ETH_L4_PAYLOAD;
1239
1240                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1241                         flex_pit = &pf->fdir.flex_set[layer_idx *
1242                                 I40E_MAX_FLXPLD_FIED + i];
1243                         if (flex_pit->size == 0)
1244                                 continue;
1245                         src = flex_pit->src_offset * sizeof(uint16_t);
1246                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1247                         size = flex_pit->size * sizeof(uint16_t);
1248                         for (j = src, k = dst; j < src + size; j++, k++)
1249                                 ptr->src_offset[k] = j;
1250                 }
1251                 (*num)++;
1252                 ptr++;
1253         }
1254 }
1255
1256 static inline void
1257 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1258                         struct rte_eth_fdir_flex_mask *flex_mask,
1259                         uint16_t *num)
1260 {
1261         struct i40e_fdir_flex_mask *mask;
1262         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1263         uint16_t flow_type;
1264         uint8_t i, j;
1265         uint16_t off_bytes, mask_tmp;
1266
1267         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1268              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1269              i++) {
1270                 mask =  &pf->fdir.flex_mask[i];
1271                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1272                         continue;
1273                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1274                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1275                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1276                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1277                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1278                         } else {
1279                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1280                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1281                         }
1282                 }
1283                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1284                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1285                         mask_tmp = ~mask->bitmask[j].mask;
1286                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1287                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1288                 }
1289                 ptr->flow_type = flow_type;
1290                 ptr++;
1291                 (*num)++;
1292         }
1293 }
1294
1295 /*
1296  * i40e_fdir_info_get - get information of Flow Director
1297  * @pf: ethernet device to get info from
1298  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1299  *    the flow director information.
1300  */
1301 static void
1302 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1303 {
1304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1305         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1306         uint16_t num_flex_set = 0;
1307         uint16_t num_flex_mask = 0;
1308
1309         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1310                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1311         else
1312                 fdir->mode = RTE_FDIR_MODE_NONE;
1313
1314         fdir->guarant_spc =
1315                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1316         fdir->best_spc =
1317                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1318         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1319         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1320         fdir->flex_payload_unit = sizeof(uint16_t);
1321         fdir->flex_bitmask_unit = sizeof(uint16_t);
1322         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1323         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1324         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1325
1326         i40e_fdir_info_get_flex_set(pf,
1327                                 fdir->flex_conf.flex_set,
1328                                 &num_flex_set);
1329         i40e_fdir_info_get_flex_mask(pf,
1330                                 fdir->flex_conf.flex_mask,
1331                                 &num_flex_mask);
1332
1333         fdir->flex_conf.nb_payloads = num_flex_set;
1334         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1335 }
1336
1337 /*
1338  * i40e_fdir_stat_get - get statistics of Flow Director
1339  * @pf: ethernet device to get info from
1340  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1341  *    the flow director statistics.
1342  */
1343 static void
1344 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1345 {
1346         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1347         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1348         uint32_t fdstat;
1349
1350         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1351         stat->guarant_cnt =
1352                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1353                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1354         stat->best_cnt =
1355                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1356                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1357 }
1358
1359 static int
1360 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1361                      struct rte_eth_fdir_filter_info *info)
1362 {
1363         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1364         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1365         int ret = 0;
1366
1367         if (!info) {
1368                 PMD_DRV_LOG(ERR, "Invalid pointer");
1369                 return -EFAULT;
1370         }
1371
1372         switch (info->info_type) {
1373         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1374                 ret = i40e_filter_inset_select(hw,
1375                         &(info->info.input_set_conf), RTE_ETH_FILTER_FDIR);
1376                 break;
1377         default:
1378                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1379                             info->info_type);
1380                 return -EINVAL;
1381         }
1382
1383         return ret;
1384 }
1385
1386 /*
1387  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1388  * @pf: board private structure
1389  * @filter_op:operation will be taken.
1390  * @arg: a pointer to specific structure corresponding to the filter_op
1391  */
1392 int
1393 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1394                        enum rte_filter_op filter_op,
1395                        void *arg)
1396 {
1397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1398         int ret = 0;
1399
1400         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1401                 return -ENOTSUP;
1402
1403         if (filter_op == RTE_ETH_FILTER_NOP)
1404                 return 0;
1405
1406         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1407                 return -EINVAL;
1408
1409         switch (filter_op) {
1410         case RTE_ETH_FILTER_ADD:
1411                 ret = i40e_add_del_fdir_filter(dev,
1412                         (struct rte_eth_fdir_filter *)arg,
1413                         TRUE);
1414                 break;
1415         case RTE_ETH_FILTER_DELETE:
1416                 ret = i40e_add_del_fdir_filter(dev,
1417                         (struct rte_eth_fdir_filter *)arg,
1418                         FALSE);
1419                 break;
1420         case RTE_ETH_FILTER_FLUSH:
1421                 ret = i40e_fdir_flush(dev);
1422                 break;
1423         case RTE_ETH_FILTER_INFO:
1424                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1425                 break;
1426         case RTE_ETH_FILTER_SET:
1427                 ret = i40e_fdir_filter_set(dev,
1428                         (struct rte_eth_fdir_filter_info *)arg);
1429                 break;
1430         case RTE_ETH_FILTER_STATS:
1431                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1432                 break;
1433         default:
1434                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1435                 ret = -EINVAL;
1436                 break;
1437         }
1438         return ret;
1439 }