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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
53 #include "i40e_logs.h"
54 #include "base/i40e_type.h"
55 #include "base/i40e_prototype.h"
56 #include "i40e_ethdev.h"
57 #include "i40e_rxtx.h"
59 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
61 #define IPV6_ADDR_LEN 16
64 #define I40E_FDIR_PKT_LEN 512
65 #define I40E_FDIR_IP_DEFAULT_LEN 420
66 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60000000
70 #define I40E_FDIR_IPv6_TC_OFFSET 20
72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
73 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
74 #define I40E_FDIR_UDP_DEFAULT_LEN 400
76 /* Wait count and interval for fdir filter programming */
77 #define I40E_FDIR_WAIT_COUNT 10
78 #define I40E_FDIR_WAIT_INTERVAL_US 1000
80 /* Wait count and interval for fdir filter flush */
81 #define I40E_FDIR_FLUSH_RETRY 50
82 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
84 #define I40E_COUNTER_PF 2
85 /* Statistic counter index for one pf */
86 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
87 #define I40E_MAX_FLX_SOURCE_OFF 480
88 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
90 #define NONUSE_FLX_PIT_DEST_OFF 63
91 #define NONUSE_FLX_PIT_FSIZE 1
92 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
93 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
94 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
95 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
96 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
97 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
98 NONUSE_FLX_PIT_DEST_OFF : \
99 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
100 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
101 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
103 #define I40E_FDIR_FLOWS ( \
104 (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
105 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
106 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
107 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
108 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
109 (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
110 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
111 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
112 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
113 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
114 (1 << RTE_ETH_FLOW_L2_PAYLOAD))
116 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
119 enum i40e_filter_pctype pctype,
120 const struct rte_eth_fdir_filter *filter,
122 static int i40e_fdir_flush(struct rte_eth_dev *dev);
124 static int i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
125 struct i40e_fdir_filter *filter);
126 static struct i40e_fdir_filter *
127 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
128 const struct rte_eth_fdir_input *input);
129 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
130 struct i40e_fdir_filter *filter);
133 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
135 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
136 struct i40e_hmc_obj_rxq rx_ctx;
137 int err = I40E_SUCCESS;
139 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
140 /* Init the RX queue in hardware */
141 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
143 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
144 rx_ctx.qlen = rxq->nb_rx_desc;
145 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
148 rx_ctx.dtype = i40e_header_split_none;
149 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
150 rx_ctx.rxmax = ETHER_MAX_LEN;
151 rx_ctx.tphrdesc_ena = 1;
152 rx_ctx.tphwdesc_ena = 1;
153 rx_ctx.tphdata_ena = 1;
154 rx_ctx.tphhead_ena = 1;
155 rx_ctx.lrxqthresh = 2;
161 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
162 if (err != I40E_SUCCESS) {
163 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
166 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
167 if (err != I40E_SUCCESS) {
168 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
171 rxq->qrx_tail = hw->hw_addr +
172 I40E_QRX_TAIL(rxq->vsi->base_queue);
175 /* Init the RX tail regieter. */
176 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
177 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
183 * i40e_fdir_setup - reserve and initialize the Flow Director resources
184 * @pf: board private structure
187 i40e_fdir_setup(struct i40e_pf *pf)
189 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
190 struct i40e_vsi *vsi;
191 int err = I40E_SUCCESS;
192 char z_name[RTE_MEMZONE_NAMESIZE];
193 const struct rte_memzone *mz = NULL;
194 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
196 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
197 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
198 return I40E_NOT_SUPPORTED;
201 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
202 " num_filters_best_effort = %u.",
203 hw->func_caps.fd_filters_guaranteed,
204 hw->func_caps.fd_filters_best_effort);
206 vsi = pf->fdir.fdir_vsi;
208 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
211 /* make new FDIR VSI */
212 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
214 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
215 return I40E_ERR_NO_AVAILABLE_VSI;
217 pf->fdir.fdir_vsi = vsi;
219 /*Fdir tx queue setup*/
220 err = i40e_fdir_setup_tx_resources(pf);
222 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
226 /*Fdir rx queue setup*/
227 err = i40e_fdir_setup_rx_resources(pf);
229 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
233 err = i40e_tx_queue_init(pf->fdir.txq);
235 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
239 /* need switch on before dev start*/
240 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
242 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
246 /* Init the rx queue in hardware */
247 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
249 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
253 /* switch on rx queue */
254 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
256 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
260 /* reserve memory for the fdir programming packet */
261 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
262 eth_dev->driver->pci_drv.driver.name,
264 eth_dev->data->port_id);
265 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
267 PMD_DRV_LOG(ERR, "Cannot init memzone for "
268 "flow director program packet.");
269 err = I40E_ERR_NO_MEMORY;
272 pf->fdir.prg_pkt = mz->addr;
273 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
275 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
276 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
281 i40e_dev_rx_queue_release(pf->fdir.rxq);
284 i40e_dev_tx_queue_release(pf->fdir.txq);
287 i40e_vsi_release(vsi);
288 pf->fdir.fdir_vsi = NULL;
293 * i40e_fdir_teardown - release the Flow Director resources
294 * @pf: board private structure
297 i40e_fdir_teardown(struct i40e_pf *pf)
299 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
300 struct i40e_vsi *vsi;
302 vsi = pf->fdir.fdir_vsi;
305 i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
306 i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
307 i40e_dev_rx_queue_release(pf->fdir.rxq);
309 i40e_dev_tx_queue_release(pf->fdir.txq);
311 i40e_vsi_release(vsi);
312 pf->fdir.fdir_vsi = NULL;
315 /* check whether the flow director table in empty */
317 i40e_fdir_empty(struct i40e_hw *hw)
319 uint32_t guarant_cnt, best_cnt;
321 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
322 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
323 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
324 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
325 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
326 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
327 if (best_cnt + guarant_cnt > 0)
334 * Initialize the configuration about bytes stream extracted as flexible payload
338 i40e_init_flx_pld(struct i40e_pf *pf)
340 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
345 * Define the bytes stream extracted as flexible payload in
346 * field vector. By default, select 8 words from the beginning
347 * of payload as flexible payload.
349 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
350 index = i * I40E_MAX_FLXPLD_FIED;
351 pf->fdir.flex_set[index].src_offset = 0;
352 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
353 pf->fdir.flex_set[index].dst_offset = 0;
354 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
356 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
358 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
361 /* initialize the masks */
362 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
363 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
364 if (hw->mac.type == I40E_MAC_X722) {
365 if (!I40E_VALID_PCTYPE_X722(
366 (enum i40e_filter_pctype)pctype))
369 if (!I40E_VALID_PCTYPE(
370 (enum i40e_filter_pctype)pctype))
373 pf->fdir.flex_mask[pctype].word_mask = 0;
374 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
375 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
376 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
377 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
378 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
383 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
385 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
386 if ((flex_pit2).src_offset < \
387 (flex_pit1).src_offset + (flex_pit1).size) { \
388 PMD_DRV_LOG(ERR, "src_offset should be not" \
389 " less than than previous offset" \
390 " + previous FSIZE."); \
396 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
397 * and the flex_pit will be sorted by it's src_offset value
399 static inline uint16_t
400 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
401 struct i40e_fdir_flex_pit *flex_pit)
403 uint16_t src_tmp, size, num = 0;
404 uint16_t i, k, j = 0;
406 while (j < I40E_FDIR_MAX_FLEX_LEN) {
408 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
409 if (src_offset[j + 1] == src_offset[j] + 1)
414 src_tmp = src_offset[j] + 1 - size;
415 /* the flex_pit need to be sort by src_offset */
416 for (i = 0; i < num; i++) {
417 if (src_tmp < flex_pit[i].src_offset)
420 /* if insert required, move backward */
421 for (k = num; k > i; k--)
422 flex_pit[k] = flex_pit[k - 1];
424 flex_pit[i].dst_offset = j + 1 - size;
425 flex_pit[i].src_offset = src_tmp;
426 flex_pit[i].size = size;
433 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
435 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
437 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
440 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
441 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
442 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
447 memset(flex_pit, 0, sizeof(flex_pit));
448 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
449 if (num > I40E_MAX_FLXPLD_FIED) {
450 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
453 for (i = 0; i < num; i++) {
454 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
455 flex_pit[i].src_offset & 0x01) {
456 PMD_DRV_LOG(ERR, "flexpayload should be measured"
461 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
467 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
468 * arguments are valid
471 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
473 const struct rte_eth_flex_payload_cfg *flex_cfg;
474 const struct rte_eth_fdir_flex_mask *flex_mask;
481 PMD_DRV_LOG(INFO, "NULL pointer.");
484 /* check flexible payload setting configuration */
485 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
486 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
489 for (i = 0; i < conf->nb_payloads; i++) {
490 flex_cfg = &conf->flex_set[i];
491 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
492 PMD_DRV_LOG(ERR, "invalid payload type.");
495 ret = i40e_check_fdir_flex_payload(flex_cfg);
497 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
502 /* check flex mask setting configuration */
503 if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
504 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
507 for (i = 0; i < conf->nb_flexmasks; i++) {
508 flex_mask = &conf->flex_mask[i];
509 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
510 PMD_DRV_LOG(WARNING, "invalid flow type.");
514 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
515 mask_tmp = I40E_WORD(flex_mask->mask[j],
516 flex_mask->mask[j + 1]);
517 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
519 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
520 PMD_DRV_LOG(ERR, " exceed maximal"
521 " number of bitmasks.");
531 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
532 * @pf: board private structure
533 * @cfg: the rule how bytes stream is extracted as flexible payload
536 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
537 const struct rte_eth_flex_payload_cfg *cfg)
539 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
540 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
542 uint16_t num, min_next_off; /* in words */
543 uint8_t field_idx = 0;
544 uint8_t layer_idx = 0;
547 if (cfg->type == RTE_ETH_L2_PAYLOAD)
548 layer_idx = I40E_FLXPLD_L2_IDX;
549 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
550 layer_idx = I40E_FLXPLD_L3_IDX;
551 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
552 layer_idx = I40E_FLXPLD_L4_IDX;
554 memset(flex_pit, 0, sizeof(flex_pit));
555 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
557 for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
558 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
559 /* record the info in fdir structure */
560 pf->fdir.flex_set[field_idx].src_offset =
561 flex_pit[i].src_offset / sizeof(uint16_t);
562 pf->fdir.flex_set[field_idx].size =
563 flex_pit[i].size / sizeof(uint16_t);
564 pf->fdir.flex_set[field_idx].dst_offset =
565 flex_pit[i].dst_offset / sizeof(uint16_t);
566 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
567 pf->fdir.flex_set[field_idx].size,
568 pf->fdir.flex_set[field_idx].dst_offset);
570 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
572 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
573 pf->fdir.flex_set[field_idx].size;
575 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
576 /* set the non-used register obeying register's constrain */
577 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
578 NONUSE_FLX_PIT_DEST_OFF);
580 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
587 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
588 * @pf: board private structure
589 * @pctype: packet classify type
590 * @flex_masks: mask for flexible payload
593 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
594 enum i40e_filter_pctype pctype,
595 const struct rte_eth_fdir_flex_mask *mask_cfg)
597 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
598 struct i40e_fdir_flex_mask *flex_mask;
599 uint32_t flxinset, fd_mask;
601 uint8_t i, nb_bitmask = 0;
603 flex_mask = &pf->fdir.flex_mask[pctype];
604 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
605 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
606 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
607 if (mask_tmp != 0x0) {
608 flex_mask->word_mask |=
609 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
610 if (mask_tmp != UINT16_MAX) {
612 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
613 flex_mask->bitmask[nb_bitmask].offset =
614 i / sizeof(uint16_t);
619 /* write mask to hw */
620 flxinset = (flex_mask->word_mask <<
621 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
622 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
623 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
625 for (i = 0; i < nb_bitmask; i++) {
626 fd_mask = (flex_mask->bitmask[i].mask <<
627 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
628 I40E_PRTQF_FD_MSK_MASK_MASK;
629 fd_mask |= ((flex_mask->bitmask[i].offset +
630 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
631 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
632 I40E_PRTQF_FD_MSK_OFFSET_MASK;
633 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
638 * Configure flow director related setting
641 i40e_fdir_configure(struct rte_eth_dev *dev)
643 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
645 struct rte_eth_fdir_flex_conf *conf;
646 enum i40e_filter_pctype pctype;
652 * configuration need to be done before
653 * flow director filters are added
654 * If filters exist, flush them.
656 if (i40e_fdir_empty(hw) < 0) {
657 ret = i40e_fdir_flush(dev);
659 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
664 /* enable FDIR filter */
665 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
666 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
667 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
669 i40e_init_flx_pld(pf); /* set flex config to default value */
671 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
672 ret = i40e_check_fdir_flex_conf(conf);
674 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
677 /* configure flex payload */
678 for (i = 0; i < conf->nb_payloads; i++)
679 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
680 /* configure flex mask*/
681 for (i = 0; i < conf->nb_flexmasks; i++) {
682 if (hw->mac.type == I40E_MAC_X722) {
683 /* get translated pctype value in fd pctype register */
684 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
685 hw, I40E_GLQF_FD_PCTYPES(
686 (int)i40e_flowtype_to_pctype(
687 conf->flex_mask[i].flow_type)));
689 pctype = i40e_flowtype_to_pctype(
690 conf->flex_mask[i].flow_type);
692 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
699 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
700 unsigned char *raw_pkt,
703 static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
704 uint16_t *ether_type;
705 uint8_t len = 2 * sizeof(struct ether_addr);
707 struct ipv6_hdr *ip6;
708 static const uint8_t next_proto[] = {
709 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
710 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
711 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
712 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
713 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
714 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
715 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
716 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
717 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
718 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
721 raw_pkt += 2 * sizeof(struct ether_addr);
722 if (vlan && fdir_input->flow_ext.vlan_tci) {
723 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
724 rte_memcpy(raw_pkt + sizeof(uint16_t),
725 &fdir_input->flow_ext.vlan_tci,
727 raw_pkt += sizeof(vlan_frame);
728 len += sizeof(vlan_frame);
730 ether_type = (uint16_t *)raw_pkt;
731 raw_pkt += sizeof(uint16_t);
732 len += sizeof(uint16_t);
734 switch (fdir_input->flow_type) {
735 case RTE_ETH_FLOW_L2_PAYLOAD:
736 *ether_type = fdir_input->flow.l2_flow.ether_type;
738 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
739 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
740 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
741 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
742 case RTE_ETH_FLOW_FRAG_IPV4:
743 ip = (struct ipv4_hdr *)raw_pkt;
745 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
746 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
747 /* set len to by default */
748 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
749 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
750 fdir_input->flow.ip4_flow.proto :
751 next_proto[fdir_input->flow_type];
752 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
753 fdir_input->flow.ip4_flow.ttl :
754 I40E_FDIR_IP_DEFAULT_TTL;
755 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
757 * The source and destination fields in the transmitted packet
758 * need to be presented in a reversed order with respect
759 * to the expected received packets.
761 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
762 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
763 len += sizeof(struct ipv4_hdr);
765 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
766 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
767 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
768 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
769 case RTE_ETH_FLOW_FRAG_IPV6:
770 ip6 = (struct ipv6_hdr *)raw_pkt;
772 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
774 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
775 (fdir_input->flow.ipv6_flow.tc <<
776 I40E_FDIR_IPv6_TC_OFFSET));
778 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
779 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
780 fdir_input->flow.ipv6_flow.proto :
781 next_proto[fdir_input->flow_type];
782 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
783 fdir_input->flow.ipv6_flow.hop_limits :
784 I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
786 * The source and destination fields in the transmitted packet
787 * need to be presented in a reversed order with respect
788 * to the expected received packets.
790 rte_memcpy(&(ip6->src_addr),
791 &(fdir_input->flow.ipv6_flow.dst_ip),
793 rte_memcpy(&(ip6->dst_addr),
794 &(fdir_input->flow.ipv6_flow.src_ip),
796 len += sizeof(struct ipv6_hdr);
799 PMD_DRV_LOG(ERR, "unknown flow type %u.",
800 fdir_input->flow_type);
808 * i40e_fdir_construct_pkt - construct packet based on fields in input
809 * @pf: board private structure
810 * @fdir_input: input set of the flow director entry
811 * @raw_pkt: a packet to be constructed
814 i40e_fdir_construct_pkt(struct i40e_pf *pf,
815 const struct rte_eth_fdir_input *fdir_input,
816 unsigned char *raw_pkt)
818 unsigned char *payload, *ptr;
821 struct sctp_hdr *sctp;
822 uint8_t size, dst = 0;
823 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
826 /* fill the ethernet and IP head */
827 len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
828 !!fdir_input->flow_ext.vlan_tci);
832 /* fill the L4 head */
833 switch (fdir_input->flow_type) {
834 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
835 udp = (struct udp_hdr *)(raw_pkt + len);
836 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
838 * The source and destination fields in the transmitted packet
839 * need to be presented in a reversed order with respect
840 * to the expected received packets.
842 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
843 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
844 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
847 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
848 tcp = (struct tcp_hdr *)(raw_pkt + len);
849 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
851 * The source and destination fields in the transmitted packet
852 * need to be presented in a reversed order with respect
853 * to the expected received packets.
855 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
856 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
857 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
860 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
861 sctp = (struct sctp_hdr *)(raw_pkt + len);
862 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
864 * The source and destination fields in the transmitted packet
865 * need to be presented in a reversed order with respect
866 * to the expected received packets.
868 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
869 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
870 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
873 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
874 case RTE_ETH_FLOW_FRAG_IPV4:
875 payload = raw_pkt + len;
876 set_idx = I40E_FLXPLD_L3_IDX;
879 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
880 udp = (struct udp_hdr *)(raw_pkt + len);
881 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
883 * The source and destination fields in the transmitted packet
884 * need to be presented in a reversed order with respect
885 * to the expected received packets.
887 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
888 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
889 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
892 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
893 tcp = (struct tcp_hdr *)(raw_pkt + len);
894 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
896 * The source and destination fields in the transmitted packet
897 * need to be presented in a reversed order with respect
898 * to the expected received packets.
900 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
901 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
902 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
905 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
906 sctp = (struct sctp_hdr *)(raw_pkt + len);
907 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
909 * The source and destination fields in the transmitted packet
910 * need to be presented in a reversed order with respect
911 * to the expected received packets.
913 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
914 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
915 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
918 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
919 case RTE_ETH_FLOW_FRAG_IPV6:
920 payload = raw_pkt + len;
921 set_idx = I40E_FLXPLD_L3_IDX;
923 case RTE_ETH_FLOW_L2_PAYLOAD:
924 payload = raw_pkt + len;
926 * ARP packet is a special case on which the payload
927 * starts after the whole ARP header
929 if (fdir_input->flow.l2_flow.ether_type ==
930 rte_cpu_to_be_16(ETHER_TYPE_ARP))
931 payload += sizeof(struct arp_hdr);
932 set_idx = I40E_FLXPLD_L2_IDX;
935 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
939 /* fill the flexbytes to payload */
940 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
941 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
942 size = pf->fdir.flex_set[pit_idx].size;
945 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
947 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
948 (void)rte_memcpy(ptr,
949 &fdir_input->flow_ext.flexbytes[dst],
950 size * sizeof(uint16_t));
956 /* Construct the tx flags */
957 static inline uint64_t
958 i40e_build_ctob(uint32_t td_cmd,
963 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
964 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
965 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
966 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
967 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
971 * check the programming status descriptor in rx queue.
972 * done after Programming Flow Director is programmed on
976 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
978 volatile union i40e_rx_desc *rxdp;
985 rxdp = &rxq->rx_ring[rxq->rx_tail];
986 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
987 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
988 >> I40E_RXD_QW1_STATUS_SHIFT;
990 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
991 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
992 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
993 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
995 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
996 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
998 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
999 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1000 if (error == (0x1 <<
1001 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1002 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1003 " (FD_ID %u): programming status"
1005 rxdp->wb.qword0.hi_dword.fd_id);
1007 } else if (error == (0x1 <<
1008 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1009 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1010 " (FD_ID %u): programming status"
1012 rxdp->wb.qword0.hi_dword.fd_id);
1015 PMD_DRV_LOG(ERR, "invalid programming status"
1016 " reported, error = %u.", error);
1018 PMD_DRV_LOG(ERR, "unknown programming status"
1019 " reported, len = %d, id = %u.", len, id);
1020 rxdp->wb.qword1.status_error_len = 0;
1022 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1029 i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
1030 struct i40e_fdir_filter *filter)
1032 rte_memcpy(&filter->fdir, input, sizeof(struct rte_eth_fdir_filter));
1036 /* Check if there exists the flow director filter */
1037 static struct i40e_fdir_filter *
1038 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1039 const struct rte_eth_fdir_input *input)
1043 ret = rte_hash_lookup(fdir_info->hash_table, (const void *)input);
1047 return fdir_info->hash_map[ret];
1050 /* Add a flow director filter into the SW list */
1052 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1054 struct i40e_fdir_info *fdir_info = &pf->fdir;
1057 ret = rte_hash_add_key(fdir_info->hash_table,
1058 &filter->fdir.input);
1061 "Failed to insert fdir filter to hash table %d!",
1065 fdir_info->hash_map[ret] = filter;
1067 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1072 /* Delete a flow director filter from the SW list */
1074 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct rte_eth_fdir_input *input)
1076 struct i40e_fdir_info *fdir_info = &pf->fdir;
1077 struct i40e_fdir_filter *filter;
1080 ret = rte_hash_del_key(fdir_info->hash_table, input);
1083 "Failed to delete fdir filter to hash table %d!",
1087 filter = fdir_info->hash_map[ret];
1088 fdir_info->hash_map[ret] = NULL;
1090 TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1097 * i40e_add_del_fdir_filter - add or remove a flow director filter.
1098 * @pf: board private structure
1099 * @filter: fdir filter entry
1100 * @add: 0 - delete, 1 - add
1103 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1104 const struct rte_eth_fdir_filter *filter,
1107 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1108 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1109 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1110 enum i40e_filter_pctype pctype;
1111 struct i40e_fdir_info *fdir_info = &pf->fdir;
1112 struct i40e_fdir_filter *fdir_filter, *node;
1113 struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1116 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1117 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1118 " check the mode in fdir_conf.");
1122 if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1123 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1126 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1127 PMD_DRV_LOG(ERR, "Invalid queue ID");
1130 if (filter->input.flow_ext.is_vf &&
1131 filter->input.flow_ext.dst_id >= pf->vf_num) {
1132 PMD_DRV_LOG(ERR, "Invalid VF ID");
1136 /* Check if there is the filter in SW list */
1137 memset(&check_filter, 0, sizeof(check_filter));
1138 i40e_fdir_filter_convert(filter, &check_filter);
1139 node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1142 "Conflict with existing flow director rules!");
1146 if (!add && !node) {
1148 "There's no corresponding flow firector filter!");
1152 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1154 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1156 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1160 if (hw->mac.type == I40E_MAC_X722) {
1161 /* get translated pctype value in fd pctype register */
1162 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1163 hw, I40E_GLQF_FD_PCTYPES(
1164 (int)i40e_flowtype_to_pctype(
1165 filter->input.flow_type)));
1167 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1169 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1171 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1177 fdir_filter = rte_zmalloc("fdir_filter",
1178 sizeof(*fdir_filter), 0);
1179 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1180 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1182 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1189 * i40e_fdir_filter_programming - Program a flow director filter rule.
1190 * Is done by Flow Director Programming Descriptor followed by packet
1191 * structure that contains the filter fields need to match.
1192 * @pf: board private structure
1194 * @filter: fdir filter entry
1195 * @add: 0 - delete, 1 - add
1198 i40e_fdir_filter_programming(struct i40e_pf *pf,
1199 enum i40e_filter_pctype pctype,
1200 const struct rte_eth_fdir_filter *filter,
1203 struct i40e_tx_queue *txq = pf->fdir.txq;
1204 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1205 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1206 volatile struct i40e_tx_desc *txdp;
1207 volatile struct i40e_filter_program_desc *fdirdp;
1212 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1213 fdirdp = (volatile struct i40e_filter_program_desc *)
1214 (&(txq->tx_ring[txq->tx_tail]));
1216 fdirdp->qindex_flex_ptype_vsi =
1217 rte_cpu_to_le_32((fdir_action->rx_queue <<
1218 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1219 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1221 fdirdp->qindex_flex_ptype_vsi |=
1222 rte_cpu_to_le_32((fdir_action->flex_off <<
1223 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1224 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1226 fdirdp->qindex_flex_ptype_vsi |=
1227 rte_cpu_to_le_32((pctype <<
1228 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1229 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1231 if (filter->input.flow_ext.is_vf)
1232 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1234 /* Use LAN VSI Id by default */
1235 vsi_id = pf->main_vsi->vsi_id;
1236 fdirdp->qindex_flex_ptype_vsi |=
1237 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1238 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1239 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1241 fdirdp->dtype_cmd_cntindex =
1242 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1245 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1246 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1247 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1249 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1250 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1251 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1253 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1254 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1255 else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1256 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1257 else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1258 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1260 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1261 " unsupported fdir behavior.");
1265 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1266 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1267 I40E_TXD_FLTR_QW1_DEST_MASK);
1269 fdirdp->dtype_cmd_cntindex |=
1270 rte_cpu_to_le_32((fdir_action->report_status<<
1271 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1272 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1274 fdirdp->dtype_cmd_cntindex |=
1275 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1276 fdirdp->dtype_cmd_cntindex |=
1278 ((uint32_t)pf->fdir.match_counter_index <<
1279 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1280 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1282 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1284 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1285 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1286 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1287 td_cmd = I40E_TX_DESC_CMD_EOP |
1288 I40E_TX_DESC_CMD_RS |
1289 I40E_TX_DESC_CMD_DUMMY;
1291 txdp->cmd_type_offset_bsz =
1292 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1294 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1295 if (txq->tx_tail >= txq->nb_tx_desc)
1297 /* Update the tx tail register */
1299 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1301 for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1302 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1303 if ((txdp->cmd_type_offset_bsz &
1304 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1305 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1308 if (i >= I40E_FDIR_WAIT_COUNT) {
1309 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1310 " time out to get DD on tx queue.");
1313 /* totally delay 10 ms to check programming status*/
1314 rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1315 if (i40e_check_fdir_programming_status(rxq) < 0) {
1316 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1317 " programming status reported.");
1325 * i40e_fdir_flush - clear all filters of Flow Director table
1326 * @pf: board private structure
1329 i40e_fdir_flush(struct rte_eth_dev *dev)
1331 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1332 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1334 uint16_t guarant_cnt, best_cnt;
1337 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1338 I40E_WRITE_FLUSH(hw);
1340 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1341 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1342 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1343 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1346 if (i >= I40E_FDIR_FLUSH_RETRY) {
1347 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1350 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1351 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1352 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1353 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1354 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1355 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1356 if (guarant_cnt != 0 || best_cnt != 0) {
1357 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1360 PMD_DRV_LOG(INFO, "FD table Flush success.");
1365 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1366 struct rte_eth_flex_payload_cfg *flex_set,
1369 struct i40e_fdir_flex_pit *flex_pit;
1370 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1371 uint16_t src, dst, size, j, k;
1372 uint8_t i, layer_idx;
1374 for (layer_idx = I40E_FLXPLD_L2_IDX;
1375 layer_idx <= I40E_FLXPLD_L4_IDX;
1377 if (layer_idx == I40E_FLXPLD_L2_IDX)
1378 ptr->type = RTE_ETH_L2_PAYLOAD;
1379 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1380 ptr->type = RTE_ETH_L3_PAYLOAD;
1381 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1382 ptr->type = RTE_ETH_L4_PAYLOAD;
1384 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1385 flex_pit = &pf->fdir.flex_set[layer_idx *
1386 I40E_MAX_FLXPLD_FIED + i];
1387 if (flex_pit->size == 0)
1389 src = flex_pit->src_offset * sizeof(uint16_t);
1390 dst = flex_pit->dst_offset * sizeof(uint16_t);
1391 size = flex_pit->size * sizeof(uint16_t);
1392 for (j = src, k = dst; j < src + size; j++, k++)
1393 ptr->src_offset[k] = j;
1401 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1402 struct rte_eth_fdir_flex_mask *flex_mask,
1405 struct i40e_fdir_flex_mask *mask;
1406 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1407 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1410 uint16_t off_bytes, mask_tmp;
1412 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1413 i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1415 mask = &pf->fdir.flex_mask[i];
1416 if (hw->mac.type == I40E_MAC_X722) {
1417 if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1420 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1423 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1424 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1425 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1426 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1427 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1429 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1430 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1433 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1434 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1435 mask_tmp = ~mask->bitmask[j].mask;
1436 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1437 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1439 ptr->flow_type = flow_type;
1446 * i40e_fdir_info_get - get information of Flow Director
1447 * @pf: ethernet device to get info from
1448 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1449 * the flow director information.
1452 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1454 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1455 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1456 uint16_t num_flex_set = 0;
1457 uint16_t num_flex_mask = 0;
1459 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1460 fdir->mode = RTE_FDIR_MODE_PERFECT;
1462 fdir->mode = RTE_FDIR_MODE_NONE;
1465 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1467 (uint32_t)hw->func_caps.fd_filters_best_effort;
1468 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1469 fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1470 fdir->flex_payload_unit = sizeof(uint16_t);
1471 fdir->flex_bitmask_unit = sizeof(uint16_t);
1472 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1473 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1474 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1476 i40e_fdir_info_get_flex_set(pf,
1477 fdir->flex_conf.flex_set,
1479 i40e_fdir_info_get_flex_mask(pf,
1480 fdir->flex_conf.flex_mask,
1483 fdir->flex_conf.nb_payloads = num_flex_set;
1484 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1488 * i40e_fdir_stat_get - get statistics of Flow Director
1489 * @pf: ethernet device to get info from
1490 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1491 * the flow director statistics.
1494 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1496 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1497 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1500 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1502 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1503 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1505 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1506 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1510 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1511 struct rte_eth_fdir_filter_info *info)
1513 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1517 PMD_DRV_LOG(ERR, "Invalid pointer");
1521 switch (info->info_type) {
1522 case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1523 ret = i40e_fdir_filter_inset_select(pf,
1524 &(info->info.input_set_conf));
1527 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1536 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1537 * @pf: board private structure
1538 * @filter_op:operation will be taken.
1539 * @arg: a pointer to specific structure corresponding to the filter_op
1542 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1543 enum rte_filter_op filter_op,
1546 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1549 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1552 if (filter_op == RTE_ETH_FILTER_NOP)
1555 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1558 switch (filter_op) {
1559 case RTE_ETH_FILTER_ADD:
1560 ret = i40e_add_del_fdir_filter(dev,
1561 (struct rte_eth_fdir_filter *)arg,
1564 case RTE_ETH_FILTER_DELETE:
1565 ret = i40e_add_del_fdir_filter(dev,
1566 (struct rte_eth_fdir_filter *)arg,
1569 case RTE_ETH_FILTER_FLUSH:
1570 ret = i40e_fdir_flush(dev);
1572 case RTE_ETH_FILTER_INFO:
1573 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1575 case RTE_ETH_FILTER_SET:
1576 ret = i40e_fdir_filter_set(dev,
1577 (struct rte_eth_fdir_filter_info *)arg);
1579 case RTE_ETH_FILTER_STATS:
1580 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1583 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1590 /* Restore flow director filter */
1592 i40e_fdir_filter_restore(struct i40e_pf *pf)
1594 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
1595 struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
1596 struct i40e_fdir_filter *f;
1597 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1598 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1600 uint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */
1601 uint32_t best_cnt; /**< Number of filters in best effort spaces. */
1602 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1604 TAILQ_FOREACH(f, fdir_list, rules)
1605 i40e_add_del_fdir_filter(dev, &f->fdir, TRUE);
1607 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
1608 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1610 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1611 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1613 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1614 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1615 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
1617 PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d, Best count: %d\n",
1618 guarant_cnt, best_cnt);