drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_debug.h>
  14 #include <rte_ether.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_log.h>
  17 #include <rte_malloc.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20
  21 #include "i40e_logs.h"
  22 #include "base/i40e_type.h"
  23 #include "base/i40e_prototype.h"
  24 #include "i40e_ethdev.h"
  25
  26 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  27 #define I40E_IPV6_FRAG_HEADER   44
  28 #define I40E_TENANT_ARRAY_NUM   3
  29 #define I40E_TCI_MASK           0xFFFF
  30
  31 static int i40e_flow_validate(struct rte_eth_dev *dev,
  32                               const struct rte_flow_attr *attr,
  33                               const struct rte_flow_item pattern[],
  34                               const struct rte_flow_action actions[],
  35                               struct rte_flow_error *error);
  36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  37                                          const struct rte_flow_attr *attr,
  38                                          const struct rte_flow_item pattern[],
  39                                          const struct rte_flow_action actions[],
  40                                          struct rte_flow_error *error);
  41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  42                              struct rte_flow *flow,
  43                              struct rte_flow_error *error);
  44 static int i40e_flow_flush(struct rte_eth_dev *dev,
  45                            struct rte_flow_error *error);
  46 static int
  47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  48                                   const struct rte_flow_item *pattern,
  49                                   struct rte_flow_error *error,
  50                                   struct rte_eth_ethertype_filter *filter);
  51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  52                                     const struct rte_flow_action *actions,
  53                                     struct rte_flow_error *error,
  54                                     struct rte_eth_ethertype_filter *filter);
  55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  56                                         const struct rte_flow_attr *attr,
  57                                         const struct rte_flow_item *pattern,
  58                                         struct rte_flow_error *error,
  59                                         struct i40e_fdir_filter_conf *filter);
  60 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  61                                        const struct rte_flow_action *actions,
  62                                        struct rte_flow_error *error,
  63                                        struct i40e_fdir_filter_conf *filter);
  64 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  65                                  const struct rte_flow_action *actions,
  66                                  struct rte_flow_error *error,
  67                                  struct i40e_tunnel_filter_conf *filter);
  68 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  69                                 struct rte_flow_error *error);
  70 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  71                                     const struct rte_flow_attr *attr,
  72                                     const struct rte_flow_item pattern[],
  73                                     const struct rte_flow_action actions[],
  74                                     struct rte_flow_error *error,
  75                                     union i40e_filter_t *filter);
  76 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  77                                        const struct rte_flow_attr *attr,
  78                                        const struct rte_flow_item pattern[],
  79                                        const struct rte_flow_action actions[],
  80                                        struct rte_flow_error *error,
  81                                        union i40e_filter_t *filter);
  82 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  83                                         const struct rte_flow_attr *attr,
  84                                         const struct rte_flow_item pattern[],
  85                                         const struct rte_flow_action actions[],
  86                                         struct rte_flow_error *error,
  87                                         union i40e_filter_t *filter);
  88 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  89                                         const struct rte_flow_attr *attr,
  90                                         const struct rte_flow_item pattern[],
  91                                         const struct rte_flow_action actions[],
  92                                         struct rte_flow_error *error,
  93                                         union i40e_filter_t *filter);
  94 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  95                                        const struct rte_flow_attr *attr,
  96                                        const struct rte_flow_item pattern[],
  97                                        const struct rte_flow_action actions[],
  98                                        struct rte_flow_error *error,
  99                                        union i40e_filter_t *filter);
 100 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 101                                       const struct rte_flow_attr *attr,
 102                                       const struct rte_flow_item pattern[],
 103                                       const struct rte_flow_action actions[],
 104                                       struct rte_flow_error *error,
 105                                       union i40e_filter_t *filter);
 106 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 107                                       struct i40e_ethertype_filter *filter);
 108 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 109                                            struct i40e_tunnel_filter *filter);
 110 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 112 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 113 static int
 114 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 115 static int
 116 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 117                               const struct rte_flow_attr *attr,
 118                               const struct rte_flow_item pattern[],
 119                               const struct rte_flow_action actions[],
 120                               struct rte_flow_error *error,
 121                               union i40e_filter_t *filter);
 122 static int
 123 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 124                               const struct rte_flow_item *pattern,
 125                               struct rte_flow_error *error,
 126                               struct i40e_tunnel_filter_conf *filter);
 127
 128 const struct rte_flow_ops i40e_flow_ops = {
 129         .validate = i40e_flow_validate,
 130         .create = i40e_flow_create,
 131         .destroy = i40e_flow_destroy,
 132         .flush = i40e_flow_flush,
 133 };
 134
 135 static union i40e_filter_t cons_filter;
 136 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 137
 138 /* Pattern matched ethertype filter */
 139 static enum rte_flow_item_type pattern_ethertype[] = {
 140         RTE_FLOW_ITEM_TYPE_ETH,
 141         RTE_FLOW_ITEM_TYPE_END,
 142 };
 143
 144 /* Pattern matched flow director filter */
 145 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 146         RTE_FLOW_ITEM_TYPE_ETH,
 147         RTE_FLOW_ITEM_TYPE_IPV4,
 148         RTE_FLOW_ITEM_TYPE_END,
 149 };
 150
 151 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 152         RTE_FLOW_ITEM_TYPE_ETH,
 153         RTE_FLOW_ITEM_TYPE_IPV4,
 154         RTE_FLOW_ITEM_TYPE_UDP,
 155         RTE_FLOW_ITEM_TYPE_END,
 156 };
 157
 158 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 159         RTE_FLOW_ITEM_TYPE_ETH,
 160         RTE_FLOW_ITEM_TYPE_IPV4,
 161         RTE_FLOW_ITEM_TYPE_TCP,
 162         RTE_FLOW_ITEM_TYPE_END,
 163 };
 164
 165 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 166         RTE_FLOW_ITEM_TYPE_ETH,
 167         RTE_FLOW_ITEM_TYPE_IPV4,
 168         RTE_FLOW_ITEM_TYPE_SCTP,
 169         RTE_FLOW_ITEM_TYPE_END,
 170 };
 171
 172 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 173         RTE_FLOW_ITEM_TYPE_ETH,
 174         RTE_FLOW_ITEM_TYPE_IPV4,
 175         RTE_FLOW_ITEM_TYPE_UDP,
 176         RTE_FLOW_ITEM_TYPE_GTPC,
 177         RTE_FLOW_ITEM_TYPE_END,
 178 };
 179
 180 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 181         RTE_FLOW_ITEM_TYPE_ETH,
 182         RTE_FLOW_ITEM_TYPE_IPV4,
 183         RTE_FLOW_ITEM_TYPE_UDP,
 184         RTE_FLOW_ITEM_TYPE_GTPU,
 185         RTE_FLOW_ITEM_TYPE_END,
 186 };
 187
 188 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 189         RTE_FLOW_ITEM_TYPE_ETH,
 190         RTE_FLOW_ITEM_TYPE_IPV4,
 191         RTE_FLOW_ITEM_TYPE_UDP,
 192         RTE_FLOW_ITEM_TYPE_GTPU,
 193         RTE_FLOW_ITEM_TYPE_IPV4,
 194         RTE_FLOW_ITEM_TYPE_END,
 195 };
 196
 197 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 198         RTE_FLOW_ITEM_TYPE_ETH,
 199         RTE_FLOW_ITEM_TYPE_IPV4,
 200         RTE_FLOW_ITEM_TYPE_UDP,
 201         RTE_FLOW_ITEM_TYPE_GTPU,
 202         RTE_FLOW_ITEM_TYPE_IPV6,
 203         RTE_FLOW_ITEM_TYPE_END,
 204 };
 205
 206 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 207         RTE_FLOW_ITEM_TYPE_ETH,
 208         RTE_FLOW_ITEM_TYPE_IPV6,
 209         RTE_FLOW_ITEM_TYPE_END,
 210 };
 211
 212 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 213         RTE_FLOW_ITEM_TYPE_ETH,
 214         RTE_FLOW_ITEM_TYPE_IPV6,
 215         RTE_FLOW_ITEM_TYPE_UDP,
 216         RTE_FLOW_ITEM_TYPE_END,
 217 };
 218
 219 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 220         RTE_FLOW_ITEM_TYPE_ETH,
 221         RTE_FLOW_ITEM_TYPE_IPV6,
 222         RTE_FLOW_ITEM_TYPE_TCP,
 223         RTE_FLOW_ITEM_TYPE_END,
 224 };
 225
 226 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 227         RTE_FLOW_ITEM_TYPE_ETH,
 228         RTE_FLOW_ITEM_TYPE_IPV6,
 229         RTE_FLOW_ITEM_TYPE_SCTP,
 230         RTE_FLOW_ITEM_TYPE_END,
 231 };
 232
 233 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 234         RTE_FLOW_ITEM_TYPE_ETH,
 235         RTE_FLOW_ITEM_TYPE_IPV6,
 236         RTE_FLOW_ITEM_TYPE_UDP,
 237         RTE_FLOW_ITEM_TYPE_GTPC,
 238         RTE_FLOW_ITEM_TYPE_END,
 239 };
 240
 241 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 242         RTE_FLOW_ITEM_TYPE_ETH,
 243         RTE_FLOW_ITEM_TYPE_IPV6,
 244         RTE_FLOW_ITEM_TYPE_UDP,
 245         RTE_FLOW_ITEM_TYPE_GTPU,
 246         RTE_FLOW_ITEM_TYPE_END,
 247 };
 248
 249 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 250         RTE_FLOW_ITEM_TYPE_ETH,
 251         RTE_FLOW_ITEM_TYPE_IPV6,
 252         RTE_FLOW_ITEM_TYPE_UDP,
 253         RTE_FLOW_ITEM_TYPE_GTPU,
 254         RTE_FLOW_ITEM_TYPE_IPV4,
 255         RTE_FLOW_ITEM_TYPE_END,
 256 };
 257
 258 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 259         RTE_FLOW_ITEM_TYPE_ETH,
 260         RTE_FLOW_ITEM_TYPE_IPV6,
 261         RTE_FLOW_ITEM_TYPE_UDP,
 262         RTE_FLOW_ITEM_TYPE_GTPU,
 263         RTE_FLOW_ITEM_TYPE_IPV6,
 264         RTE_FLOW_ITEM_TYPE_END,
 265 };
 266
 267 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 268         RTE_FLOW_ITEM_TYPE_ETH,
 269         RTE_FLOW_ITEM_TYPE_RAW,
 270         RTE_FLOW_ITEM_TYPE_END,
 271 };
 272
 273 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 274         RTE_FLOW_ITEM_TYPE_ETH,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_RAW,
 277         RTE_FLOW_ITEM_TYPE_END,
 278 };
 279
 280 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 281         RTE_FLOW_ITEM_TYPE_ETH,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_RAW,
 285         RTE_FLOW_ITEM_TYPE_END,
 286 };
 287
 288 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 289         RTE_FLOW_ITEM_TYPE_ETH,
 290         RTE_FLOW_ITEM_TYPE_IPV4,
 291         RTE_FLOW_ITEM_TYPE_RAW,
 292         RTE_FLOW_ITEM_TYPE_END,
 293 };
 294
 295 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 296         RTE_FLOW_ITEM_TYPE_ETH,
 297         RTE_FLOW_ITEM_TYPE_IPV4,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_RAW,
 300         RTE_FLOW_ITEM_TYPE_END,
 301 };
 302
 303 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 304         RTE_FLOW_ITEM_TYPE_ETH,
 305         RTE_FLOW_ITEM_TYPE_IPV4,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_RAW,
 309         RTE_FLOW_ITEM_TYPE_END,
 310 };
 311
 312 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 313         RTE_FLOW_ITEM_TYPE_ETH,
 314         RTE_FLOW_ITEM_TYPE_IPV4,
 315         RTE_FLOW_ITEM_TYPE_UDP,
 316         RTE_FLOW_ITEM_TYPE_RAW,
 317         RTE_FLOW_ITEM_TYPE_END,
 318 };
 319
 320 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 321         RTE_FLOW_ITEM_TYPE_ETH,
 322         RTE_FLOW_ITEM_TYPE_IPV4,
 323         RTE_FLOW_ITEM_TYPE_UDP,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_RAW,
 326         RTE_FLOW_ITEM_TYPE_END,
 327 };
 328
 329 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 330         RTE_FLOW_ITEM_TYPE_ETH,
 331         RTE_FLOW_ITEM_TYPE_IPV4,
 332         RTE_FLOW_ITEM_TYPE_UDP,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_RAW,
 336         RTE_FLOW_ITEM_TYPE_END,
 337 };
 338
 339 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 340         RTE_FLOW_ITEM_TYPE_ETH,
 341         RTE_FLOW_ITEM_TYPE_IPV4,
 342         RTE_FLOW_ITEM_TYPE_TCP,
 343         RTE_FLOW_ITEM_TYPE_RAW,
 344         RTE_FLOW_ITEM_TYPE_END,
 345 };
 346
 347 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 348         RTE_FLOW_ITEM_TYPE_ETH,
 349         RTE_FLOW_ITEM_TYPE_IPV4,
 350         RTE_FLOW_ITEM_TYPE_TCP,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_RAW,
 353         RTE_FLOW_ITEM_TYPE_END,
 354 };
 355
 356 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 357         RTE_FLOW_ITEM_TYPE_ETH,
 358         RTE_FLOW_ITEM_TYPE_IPV4,
 359         RTE_FLOW_ITEM_TYPE_TCP,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_RAW,
 363         RTE_FLOW_ITEM_TYPE_END,
 364 };
 365
 366 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 367         RTE_FLOW_ITEM_TYPE_ETH,
 368         RTE_FLOW_ITEM_TYPE_IPV4,
 369         RTE_FLOW_ITEM_TYPE_SCTP,
 370         RTE_FLOW_ITEM_TYPE_RAW,
 371         RTE_FLOW_ITEM_TYPE_END,
 372 };
 373
 374 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 375         RTE_FLOW_ITEM_TYPE_ETH,
 376         RTE_FLOW_ITEM_TYPE_IPV4,
 377         RTE_FLOW_ITEM_TYPE_SCTP,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_RAW,
 380         RTE_FLOW_ITEM_TYPE_END,
 381 };
 382
 383 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 384         RTE_FLOW_ITEM_TYPE_ETH,
 385         RTE_FLOW_ITEM_TYPE_IPV4,
 386         RTE_FLOW_ITEM_TYPE_SCTP,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_RAW,
 390         RTE_FLOW_ITEM_TYPE_END,
 391 };
 392
 393 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 394         RTE_FLOW_ITEM_TYPE_ETH,
 395         RTE_FLOW_ITEM_TYPE_IPV6,
 396         RTE_FLOW_ITEM_TYPE_RAW,
 397         RTE_FLOW_ITEM_TYPE_END,
 398 };
 399
 400 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 401         RTE_FLOW_ITEM_TYPE_ETH,
 402         RTE_FLOW_ITEM_TYPE_IPV6,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_RAW,
 405         RTE_FLOW_ITEM_TYPE_END,
 406 };
 407
 408 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 409         RTE_FLOW_ITEM_TYPE_ETH,
 410         RTE_FLOW_ITEM_TYPE_IPV6,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_RAW,
 414         RTE_FLOW_ITEM_TYPE_END,
 415 };
 416
 417 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 418         RTE_FLOW_ITEM_TYPE_ETH,
 419         RTE_FLOW_ITEM_TYPE_IPV6,
 420         RTE_FLOW_ITEM_TYPE_UDP,
 421         RTE_FLOW_ITEM_TYPE_RAW,
 422         RTE_FLOW_ITEM_TYPE_END,
 423 };
 424
 425 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 426         RTE_FLOW_ITEM_TYPE_ETH,
 427         RTE_FLOW_ITEM_TYPE_IPV6,
 428         RTE_FLOW_ITEM_TYPE_UDP,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_RAW,
 431         RTE_FLOW_ITEM_TYPE_END,
 432 };
 433
 434 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 435         RTE_FLOW_ITEM_TYPE_ETH,
 436         RTE_FLOW_ITEM_TYPE_IPV6,
 437         RTE_FLOW_ITEM_TYPE_UDP,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_RAW,
 441         RTE_FLOW_ITEM_TYPE_END,
 442 };
 443
 444 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 445         RTE_FLOW_ITEM_TYPE_ETH,
 446         RTE_FLOW_ITEM_TYPE_IPV6,
 447         RTE_FLOW_ITEM_TYPE_TCP,
 448         RTE_FLOW_ITEM_TYPE_RAW,
 449         RTE_FLOW_ITEM_TYPE_END,
 450 };
 451
 452 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 453         RTE_FLOW_ITEM_TYPE_ETH,
 454         RTE_FLOW_ITEM_TYPE_IPV6,
 455         RTE_FLOW_ITEM_TYPE_TCP,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_RAW,
 458         RTE_FLOW_ITEM_TYPE_END,
 459 };
 460
 461 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 462         RTE_FLOW_ITEM_TYPE_ETH,
 463         RTE_FLOW_ITEM_TYPE_IPV6,
 464         RTE_FLOW_ITEM_TYPE_TCP,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_RAW,
 468         RTE_FLOW_ITEM_TYPE_END,
 469 };
 470
 471 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 472         RTE_FLOW_ITEM_TYPE_ETH,
 473         RTE_FLOW_ITEM_TYPE_IPV6,
 474         RTE_FLOW_ITEM_TYPE_SCTP,
 475         RTE_FLOW_ITEM_TYPE_RAW,
 476         RTE_FLOW_ITEM_TYPE_END,
 477 };
 478
 479 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 480         RTE_FLOW_ITEM_TYPE_ETH,
 481         RTE_FLOW_ITEM_TYPE_IPV6,
 482         RTE_FLOW_ITEM_TYPE_SCTP,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_RAW,
 485         RTE_FLOW_ITEM_TYPE_END,
 486 };
 487
 488 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 489         RTE_FLOW_ITEM_TYPE_ETH,
 490         RTE_FLOW_ITEM_TYPE_IPV6,
 491         RTE_FLOW_ITEM_TYPE_SCTP,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_RAW,
 495         RTE_FLOW_ITEM_TYPE_END,
 496 };
 497
 498 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 499         RTE_FLOW_ITEM_TYPE_ETH,
 500         RTE_FLOW_ITEM_TYPE_VLAN,
 501         RTE_FLOW_ITEM_TYPE_END,
 502 };
 503
 504 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 505         RTE_FLOW_ITEM_TYPE_ETH,
 506         RTE_FLOW_ITEM_TYPE_VLAN,
 507         RTE_FLOW_ITEM_TYPE_IPV4,
 508         RTE_FLOW_ITEM_TYPE_END,
 509 };
 510
 511 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 512         RTE_FLOW_ITEM_TYPE_ETH,
 513         RTE_FLOW_ITEM_TYPE_VLAN,
 514         RTE_FLOW_ITEM_TYPE_IPV4,
 515         RTE_FLOW_ITEM_TYPE_UDP,
 516         RTE_FLOW_ITEM_TYPE_END,
 517 };
 518
 519 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 520         RTE_FLOW_ITEM_TYPE_ETH,
 521         RTE_FLOW_ITEM_TYPE_VLAN,
 522         RTE_FLOW_ITEM_TYPE_IPV4,
 523         RTE_FLOW_ITEM_TYPE_TCP,
 524         RTE_FLOW_ITEM_TYPE_END,
 525 };
 526
 527 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 528         RTE_FLOW_ITEM_TYPE_ETH,
 529         RTE_FLOW_ITEM_TYPE_VLAN,
 530         RTE_FLOW_ITEM_TYPE_IPV4,
 531         RTE_FLOW_ITEM_TYPE_SCTP,
 532         RTE_FLOW_ITEM_TYPE_END,
 533 };
 534
 535 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 536         RTE_FLOW_ITEM_TYPE_ETH,
 537         RTE_FLOW_ITEM_TYPE_VLAN,
 538         RTE_FLOW_ITEM_TYPE_IPV6,
 539         RTE_FLOW_ITEM_TYPE_END,
 540 };
 541
 542 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 543         RTE_FLOW_ITEM_TYPE_ETH,
 544         RTE_FLOW_ITEM_TYPE_VLAN,
 545         RTE_FLOW_ITEM_TYPE_IPV6,
 546         RTE_FLOW_ITEM_TYPE_UDP,
 547         RTE_FLOW_ITEM_TYPE_END,
 548 };
 549
 550 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 551         RTE_FLOW_ITEM_TYPE_ETH,
 552         RTE_FLOW_ITEM_TYPE_VLAN,
 553         RTE_FLOW_ITEM_TYPE_IPV6,
 554         RTE_FLOW_ITEM_TYPE_TCP,
 555         RTE_FLOW_ITEM_TYPE_END,
 556 };
 557
 558 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 559         RTE_FLOW_ITEM_TYPE_ETH,
 560         RTE_FLOW_ITEM_TYPE_VLAN,
 561         RTE_FLOW_ITEM_TYPE_IPV6,
 562         RTE_FLOW_ITEM_TYPE_SCTP,
 563         RTE_FLOW_ITEM_TYPE_END,
 564 };
 565
 566 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 567         RTE_FLOW_ITEM_TYPE_ETH,
 568         RTE_FLOW_ITEM_TYPE_VLAN,
 569         RTE_FLOW_ITEM_TYPE_RAW,
 570         RTE_FLOW_ITEM_TYPE_END,
 571 };
 572
 573 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 574         RTE_FLOW_ITEM_TYPE_ETH,
 575         RTE_FLOW_ITEM_TYPE_VLAN,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_RAW,
 578         RTE_FLOW_ITEM_TYPE_END,
 579 };
 580
 581 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 582         RTE_FLOW_ITEM_TYPE_ETH,
 583         RTE_FLOW_ITEM_TYPE_VLAN,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_RAW,
 587         RTE_FLOW_ITEM_TYPE_END,
 588 };
 589
 590 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 591         RTE_FLOW_ITEM_TYPE_ETH,
 592         RTE_FLOW_ITEM_TYPE_VLAN,
 593         RTE_FLOW_ITEM_TYPE_IPV4,
 594         RTE_FLOW_ITEM_TYPE_RAW,
 595         RTE_FLOW_ITEM_TYPE_END,
 596 };
 597
 598 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 599         RTE_FLOW_ITEM_TYPE_ETH,
 600         RTE_FLOW_ITEM_TYPE_VLAN,
 601         RTE_FLOW_ITEM_TYPE_IPV4,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_RAW,
 604         RTE_FLOW_ITEM_TYPE_END,
 605 };
 606
 607 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 608         RTE_FLOW_ITEM_TYPE_ETH,
 609         RTE_FLOW_ITEM_TYPE_VLAN,
 610         RTE_FLOW_ITEM_TYPE_IPV4,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_RAW,
 614         RTE_FLOW_ITEM_TYPE_END,
 615 };
 616
 617 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 618         RTE_FLOW_ITEM_TYPE_ETH,
 619         RTE_FLOW_ITEM_TYPE_VLAN,
 620         RTE_FLOW_ITEM_TYPE_IPV4,
 621         RTE_FLOW_ITEM_TYPE_UDP,
 622         RTE_FLOW_ITEM_TYPE_RAW,
 623         RTE_FLOW_ITEM_TYPE_END,
 624 };
 625
 626 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 627         RTE_FLOW_ITEM_TYPE_ETH,
 628         RTE_FLOW_ITEM_TYPE_VLAN,
 629         RTE_FLOW_ITEM_TYPE_IPV4,
 630         RTE_FLOW_ITEM_TYPE_UDP,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_RAW,
 633         RTE_FLOW_ITEM_TYPE_END,
 634 };
 635
 636 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 637         RTE_FLOW_ITEM_TYPE_ETH,
 638         RTE_FLOW_ITEM_TYPE_VLAN,
 639         RTE_FLOW_ITEM_TYPE_IPV4,
 640         RTE_FLOW_ITEM_TYPE_UDP,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_RAW,
 644         RTE_FLOW_ITEM_TYPE_END,
 645 };
 646
 647 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 648         RTE_FLOW_ITEM_TYPE_ETH,
 649         RTE_FLOW_ITEM_TYPE_VLAN,
 650         RTE_FLOW_ITEM_TYPE_IPV4,
 651         RTE_FLOW_ITEM_TYPE_TCP,
 652         RTE_FLOW_ITEM_TYPE_RAW,
 653         RTE_FLOW_ITEM_TYPE_END,
 654 };
 655
 656 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 657         RTE_FLOW_ITEM_TYPE_ETH,
 658         RTE_FLOW_ITEM_TYPE_VLAN,
 659         RTE_FLOW_ITEM_TYPE_IPV4,
 660         RTE_FLOW_ITEM_TYPE_TCP,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_RAW,
 663         RTE_FLOW_ITEM_TYPE_END,
 664 };
 665
 666 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 667         RTE_FLOW_ITEM_TYPE_ETH,
 668         RTE_FLOW_ITEM_TYPE_VLAN,
 669         RTE_FLOW_ITEM_TYPE_IPV4,
 670         RTE_FLOW_ITEM_TYPE_TCP,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_RAW,
 674         RTE_FLOW_ITEM_TYPE_END,
 675 };
 676
 677 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 678         RTE_FLOW_ITEM_TYPE_ETH,
 679         RTE_FLOW_ITEM_TYPE_VLAN,
 680         RTE_FLOW_ITEM_TYPE_IPV4,
 681         RTE_FLOW_ITEM_TYPE_SCTP,
 682         RTE_FLOW_ITEM_TYPE_RAW,
 683         RTE_FLOW_ITEM_TYPE_END,
 684 };
 685
 686 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 687         RTE_FLOW_ITEM_TYPE_ETH,
 688         RTE_FLOW_ITEM_TYPE_VLAN,
 689         RTE_FLOW_ITEM_TYPE_IPV4,
 690         RTE_FLOW_ITEM_TYPE_SCTP,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_RAW,
 693         RTE_FLOW_ITEM_TYPE_END,
 694 };
 695
 696 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 697         RTE_FLOW_ITEM_TYPE_ETH,
 698         RTE_FLOW_ITEM_TYPE_VLAN,
 699         RTE_FLOW_ITEM_TYPE_IPV4,
 700         RTE_FLOW_ITEM_TYPE_SCTP,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_RAW,
 704         RTE_FLOW_ITEM_TYPE_END,
 705 };
 706
 707 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 708         RTE_FLOW_ITEM_TYPE_ETH,
 709         RTE_FLOW_ITEM_TYPE_VLAN,
 710         RTE_FLOW_ITEM_TYPE_IPV6,
 711         RTE_FLOW_ITEM_TYPE_RAW,
 712         RTE_FLOW_ITEM_TYPE_END,
 713 };
 714
 715 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 716         RTE_FLOW_ITEM_TYPE_ETH,
 717         RTE_FLOW_ITEM_TYPE_VLAN,
 718         RTE_FLOW_ITEM_TYPE_IPV6,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_RAW,
 721         RTE_FLOW_ITEM_TYPE_END,
 722 };
 723
 724 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 725         RTE_FLOW_ITEM_TYPE_ETH,
 726         RTE_FLOW_ITEM_TYPE_VLAN,
 727         RTE_FLOW_ITEM_TYPE_IPV6,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_RAW,
 731         RTE_FLOW_ITEM_TYPE_END,
 732 };
 733
 734 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 735         RTE_FLOW_ITEM_TYPE_ETH,
 736         RTE_FLOW_ITEM_TYPE_VLAN,
 737         RTE_FLOW_ITEM_TYPE_IPV6,
 738         RTE_FLOW_ITEM_TYPE_UDP,
 739         RTE_FLOW_ITEM_TYPE_RAW,
 740         RTE_FLOW_ITEM_TYPE_END,
 741 };
 742
 743 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 744         RTE_FLOW_ITEM_TYPE_ETH,
 745         RTE_FLOW_ITEM_TYPE_VLAN,
 746         RTE_FLOW_ITEM_TYPE_IPV6,
 747         RTE_FLOW_ITEM_TYPE_UDP,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_RAW,
 750         RTE_FLOW_ITEM_TYPE_END,
 751 };
 752
 753 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 754         RTE_FLOW_ITEM_TYPE_ETH,
 755         RTE_FLOW_ITEM_TYPE_VLAN,
 756         RTE_FLOW_ITEM_TYPE_IPV6,
 757         RTE_FLOW_ITEM_TYPE_UDP,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_RAW,
 761         RTE_FLOW_ITEM_TYPE_END,
 762 };
 763
 764 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 765         RTE_FLOW_ITEM_TYPE_ETH,
 766         RTE_FLOW_ITEM_TYPE_VLAN,
 767         RTE_FLOW_ITEM_TYPE_IPV6,
 768         RTE_FLOW_ITEM_TYPE_TCP,
 769         RTE_FLOW_ITEM_TYPE_RAW,
 770         RTE_FLOW_ITEM_TYPE_END,
 771 };
 772
 773 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 774         RTE_FLOW_ITEM_TYPE_ETH,
 775         RTE_FLOW_ITEM_TYPE_VLAN,
 776         RTE_FLOW_ITEM_TYPE_IPV6,
 777         RTE_FLOW_ITEM_TYPE_TCP,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_RAW,
 780         RTE_FLOW_ITEM_TYPE_END,
 781 };
 782
 783 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 784         RTE_FLOW_ITEM_TYPE_ETH,
 785         RTE_FLOW_ITEM_TYPE_VLAN,
 786         RTE_FLOW_ITEM_TYPE_IPV6,
 787         RTE_FLOW_ITEM_TYPE_TCP,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_RAW,
 791         RTE_FLOW_ITEM_TYPE_END,
 792 };
 793
 794 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 795         RTE_FLOW_ITEM_TYPE_ETH,
 796         RTE_FLOW_ITEM_TYPE_VLAN,
 797         RTE_FLOW_ITEM_TYPE_IPV6,
 798         RTE_FLOW_ITEM_TYPE_SCTP,
 799         RTE_FLOW_ITEM_TYPE_RAW,
 800         RTE_FLOW_ITEM_TYPE_END,
 801 };
 802
 803 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 804         RTE_FLOW_ITEM_TYPE_ETH,
 805         RTE_FLOW_ITEM_TYPE_VLAN,
 806         RTE_FLOW_ITEM_TYPE_IPV6,
 807         RTE_FLOW_ITEM_TYPE_SCTP,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_RAW,
 810         RTE_FLOW_ITEM_TYPE_END,
 811 };
 812
 813 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 814         RTE_FLOW_ITEM_TYPE_ETH,
 815         RTE_FLOW_ITEM_TYPE_VLAN,
 816         RTE_FLOW_ITEM_TYPE_IPV6,
 817         RTE_FLOW_ITEM_TYPE_SCTP,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_RAW,
 821         RTE_FLOW_ITEM_TYPE_END,
 822 };
 823
 824 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 825         RTE_FLOW_ITEM_TYPE_ETH,
 826         RTE_FLOW_ITEM_TYPE_IPV4,
 827         RTE_FLOW_ITEM_TYPE_VF,
 828         RTE_FLOW_ITEM_TYPE_END,
 829 };
 830
 831 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 832         RTE_FLOW_ITEM_TYPE_ETH,
 833         RTE_FLOW_ITEM_TYPE_IPV4,
 834         RTE_FLOW_ITEM_TYPE_UDP,
 835         RTE_FLOW_ITEM_TYPE_VF,
 836         RTE_FLOW_ITEM_TYPE_END,
 837 };
 838
 839 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 840         RTE_FLOW_ITEM_TYPE_ETH,
 841         RTE_FLOW_ITEM_TYPE_IPV4,
 842         RTE_FLOW_ITEM_TYPE_TCP,
 843         RTE_FLOW_ITEM_TYPE_VF,
 844         RTE_FLOW_ITEM_TYPE_END,
 845 };
 846
 847 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 848         RTE_FLOW_ITEM_TYPE_ETH,
 849         RTE_FLOW_ITEM_TYPE_IPV4,
 850         RTE_FLOW_ITEM_TYPE_SCTP,
 851         RTE_FLOW_ITEM_TYPE_VF,
 852         RTE_FLOW_ITEM_TYPE_END,
 853 };
 854
 855 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 856         RTE_FLOW_ITEM_TYPE_ETH,
 857         RTE_FLOW_ITEM_TYPE_IPV6,
 858         RTE_FLOW_ITEM_TYPE_VF,
 859         RTE_FLOW_ITEM_TYPE_END,
 860 };
 861
 862 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 863         RTE_FLOW_ITEM_TYPE_ETH,
 864         RTE_FLOW_ITEM_TYPE_IPV6,
 865         RTE_FLOW_ITEM_TYPE_UDP,
 866         RTE_FLOW_ITEM_TYPE_VF,
 867         RTE_FLOW_ITEM_TYPE_END,
 868 };
 869
 870 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 871         RTE_FLOW_ITEM_TYPE_ETH,
 872         RTE_FLOW_ITEM_TYPE_IPV6,
 873         RTE_FLOW_ITEM_TYPE_TCP,
 874         RTE_FLOW_ITEM_TYPE_VF,
 875         RTE_FLOW_ITEM_TYPE_END,
 876 };
 877
 878 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 879         RTE_FLOW_ITEM_TYPE_ETH,
 880         RTE_FLOW_ITEM_TYPE_IPV6,
 881         RTE_FLOW_ITEM_TYPE_SCTP,
 882         RTE_FLOW_ITEM_TYPE_VF,
 883         RTE_FLOW_ITEM_TYPE_END,
 884 };
 885
 886 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 887         RTE_FLOW_ITEM_TYPE_ETH,
 888         RTE_FLOW_ITEM_TYPE_RAW,
 889         RTE_FLOW_ITEM_TYPE_VF,
 890         RTE_FLOW_ITEM_TYPE_END,
 891 };
 892
 893 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 894         RTE_FLOW_ITEM_TYPE_ETH,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_RAW,
 897         RTE_FLOW_ITEM_TYPE_VF,
 898         RTE_FLOW_ITEM_TYPE_END,
 899 };
 900
 901 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 902         RTE_FLOW_ITEM_TYPE_ETH,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_RAW,
 906         RTE_FLOW_ITEM_TYPE_VF,
 907         RTE_FLOW_ITEM_TYPE_END,
 908 };
 909
 910 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 911         RTE_FLOW_ITEM_TYPE_ETH,
 912         RTE_FLOW_ITEM_TYPE_IPV4,
 913         RTE_FLOW_ITEM_TYPE_RAW,
 914         RTE_FLOW_ITEM_TYPE_VF,
 915         RTE_FLOW_ITEM_TYPE_END,
 916 };
 917
 918 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 919         RTE_FLOW_ITEM_TYPE_ETH,
 920         RTE_FLOW_ITEM_TYPE_IPV4,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_RAW,
 923         RTE_FLOW_ITEM_TYPE_VF,
 924         RTE_FLOW_ITEM_TYPE_END,
 925 };
 926
 927 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 928         RTE_FLOW_ITEM_TYPE_ETH,
 929         RTE_FLOW_ITEM_TYPE_IPV4,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_RAW,
 933         RTE_FLOW_ITEM_TYPE_VF,
 934         RTE_FLOW_ITEM_TYPE_END,
 935 };
 936
 937 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 938         RTE_FLOW_ITEM_TYPE_ETH,
 939         RTE_FLOW_ITEM_TYPE_IPV4,
 940         RTE_FLOW_ITEM_TYPE_UDP,
 941         RTE_FLOW_ITEM_TYPE_RAW,
 942         RTE_FLOW_ITEM_TYPE_VF,
 943         RTE_FLOW_ITEM_TYPE_END,
 944 };
 945
 946 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 947         RTE_FLOW_ITEM_TYPE_ETH,
 948         RTE_FLOW_ITEM_TYPE_IPV4,
 949         RTE_FLOW_ITEM_TYPE_UDP,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_RAW,
 952         RTE_FLOW_ITEM_TYPE_VF,
 953         RTE_FLOW_ITEM_TYPE_END,
 954 };
 955
 956 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 957         RTE_FLOW_ITEM_TYPE_ETH,
 958         RTE_FLOW_ITEM_TYPE_IPV4,
 959         RTE_FLOW_ITEM_TYPE_UDP,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_RAW,
 963         RTE_FLOW_ITEM_TYPE_VF,
 964         RTE_FLOW_ITEM_TYPE_END,
 965 };
 966
 967 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 968         RTE_FLOW_ITEM_TYPE_ETH,
 969         RTE_FLOW_ITEM_TYPE_IPV4,
 970         RTE_FLOW_ITEM_TYPE_TCP,
 971         RTE_FLOW_ITEM_TYPE_RAW,
 972         RTE_FLOW_ITEM_TYPE_VF,
 973         RTE_FLOW_ITEM_TYPE_END,
 974 };
 975
 976 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 977         RTE_FLOW_ITEM_TYPE_ETH,
 978         RTE_FLOW_ITEM_TYPE_IPV4,
 979         RTE_FLOW_ITEM_TYPE_TCP,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_RAW,
 982         RTE_FLOW_ITEM_TYPE_VF,
 983         RTE_FLOW_ITEM_TYPE_END,
 984 };
 985
 986 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 987         RTE_FLOW_ITEM_TYPE_ETH,
 988         RTE_FLOW_ITEM_TYPE_IPV4,
 989         RTE_FLOW_ITEM_TYPE_TCP,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_RAW,
 993         RTE_FLOW_ITEM_TYPE_VF,
 994         RTE_FLOW_ITEM_TYPE_END,
 995 };
 996
 997 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 998         RTE_FLOW_ITEM_TYPE_ETH,
 999         RTE_FLOW_ITEM_TYPE_IPV4,
1000         RTE_FLOW_ITEM_TYPE_SCTP,
1001         RTE_FLOW_ITEM_TYPE_RAW,
1002         RTE_FLOW_ITEM_TYPE_VF,
1003         RTE_FLOW_ITEM_TYPE_END,
1004 };
1005
1006 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1007         RTE_FLOW_ITEM_TYPE_ETH,
1008         RTE_FLOW_ITEM_TYPE_IPV4,
1009         RTE_FLOW_ITEM_TYPE_SCTP,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_RAW,
1012         RTE_FLOW_ITEM_TYPE_VF,
1013         RTE_FLOW_ITEM_TYPE_END,
1014 };
1015
1016 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1017         RTE_FLOW_ITEM_TYPE_ETH,
1018         RTE_FLOW_ITEM_TYPE_IPV4,
1019         RTE_FLOW_ITEM_TYPE_SCTP,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_RAW,
1023         RTE_FLOW_ITEM_TYPE_VF,
1024         RTE_FLOW_ITEM_TYPE_END,
1025 };
1026
1027 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1028         RTE_FLOW_ITEM_TYPE_ETH,
1029         RTE_FLOW_ITEM_TYPE_IPV6,
1030         RTE_FLOW_ITEM_TYPE_RAW,
1031         RTE_FLOW_ITEM_TYPE_VF,
1032         RTE_FLOW_ITEM_TYPE_END,
1033 };
1034
1035 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1036         RTE_FLOW_ITEM_TYPE_ETH,
1037         RTE_FLOW_ITEM_TYPE_IPV6,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_RAW,
1040         RTE_FLOW_ITEM_TYPE_VF,
1041         RTE_FLOW_ITEM_TYPE_END,
1042 };
1043
1044 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1045         RTE_FLOW_ITEM_TYPE_ETH,
1046         RTE_FLOW_ITEM_TYPE_IPV6,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_RAW,
1050         RTE_FLOW_ITEM_TYPE_VF,
1051         RTE_FLOW_ITEM_TYPE_END,
1052 };
1053
1054 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1055         RTE_FLOW_ITEM_TYPE_ETH,
1056         RTE_FLOW_ITEM_TYPE_IPV6,
1057         RTE_FLOW_ITEM_TYPE_UDP,
1058         RTE_FLOW_ITEM_TYPE_RAW,
1059         RTE_FLOW_ITEM_TYPE_VF,
1060         RTE_FLOW_ITEM_TYPE_END,
1061 };
1062
1063 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1064         RTE_FLOW_ITEM_TYPE_ETH,
1065         RTE_FLOW_ITEM_TYPE_IPV6,
1066         RTE_FLOW_ITEM_TYPE_UDP,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_RAW,
1069         RTE_FLOW_ITEM_TYPE_VF,
1070         RTE_FLOW_ITEM_TYPE_END,
1071 };
1072
1073 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1074         RTE_FLOW_ITEM_TYPE_ETH,
1075         RTE_FLOW_ITEM_TYPE_IPV6,
1076         RTE_FLOW_ITEM_TYPE_UDP,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_RAW,
1080         RTE_FLOW_ITEM_TYPE_VF,
1081         RTE_FLOW_ITEM_TYPE_END,
1082 };
1083
1084 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1085         RTE_FLOW_ITEM_TYPE_ETH,
1086         RTE_FLOW_ITEM_TYPE_IPV6,
1087         RTE_FLOW_ITEM_TYPE_TCP,
1088         RTE_FLOW_ITEM_TYPE_RAW,
1089         RTE_FLOW_ITEM_TYPE_VF,
1090         RTE_FLOW_ITEM_TYPE_END,
1091 };
1092
1093 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1094         RTE_FLOW_ITEM_TYPE_ETH,
1095         RTE_FLOW_ITEM_TYPE_IPV6,
1096         RTE_FLOW_ITEM_TYPE_TCP,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_RAW,
1099         RTE_FLOW_ITEM_TYPE_VF,
1100         RTE_FLOW_ITEM_TYPE_END,
1101 };
1102
1103 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1104         RTE_FLOW_ITEM_TYPE_ETH,
1105         RTE_FLOW_ITEM_TYPE_IPV6,
1106         RTE_FLOW_ITEM_TYPE_TCP,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_RAW,
1110         RTE_FLOW_ITEM_TYPE_VF,
1111         RTE_FLOW_ITEM_TYPE_END,
1112 };
1113
1114 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1115         RTE_FLOW_ITEM_TYPE_ETH,
1116         RTE_FLOW_ITEM_TYPE_IPV6,
1117         RTE_FLOW_ITEM_TYPE_SCTP,
1118         RTE_FLOW_ITEM_TYPE_RAW,
1119         RTE_FLOW_ITEM_TYPE_VF,
1120         RTE_FLOW_ITEM_TYPE_END,
1121 };
1122
1123 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1124         RTE_FLOW_ITEM_TYPE_ETH,
1125         RTE_FLOW_ITEM_TYPE_IPV6,
1126         RTE_FLOW_ITEM_TYPE_SCTP,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_RAW,
1129         RTE_FLOW_ITEM_TYPE_VF,
1130         RTE_FLOW_ITEM_TYPE_END,
1131 };
1132
1133 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1134         RTE_FLOW_ITEM_TYPE_ETH,
1135         RTE_FLOW_ITEM_TYPE_IPV6,
1136         RTE_FLOW_ITEM_TYPE_SCTP,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_RAW,
1140         RTE_FLOW_ITEM_TYPE_VF,
1141         RTE_FLOW_ITEM_TYPE_END,
1142 };
1143
1144 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1145         RTE_FLOW_ITEM_TYPE_ETH,
1146         RTE_FLOW_ITEM_TYPE_VLAN,
1147         RTE_FLOW_ITEM_TYPE_VF,
1148         RTE_FLOW_ITEM_TYPE_END,
1149 };
1150
1151 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1152         RTE_FLOW_ITEM_TYPE_ETH,
1153         RTE_FLOW_ITEM_TYPE_VLAN,
1154         RTE_FLOW_ITEM_TYPE_IPV4,
1155         RTE_FLOW_ITEM_TYPE_VF,
1156         RTE_FLOW_ITEM_TYPE_END,
1157 };
1158
1159 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1160         RTE_FLOW_ITEM_TYPE_ETH,
1161         RTE_FLOW_ITEM_TYPE_VLAN,
1162         RTE_FLOW_ITEM_TYPE_IPV4,
1163         RTE_FLOW_ITEM_TYPE_UDP,
1164         RTE_FLOW_ITEM_TYPE_VF,
1165         RTE_FLOW_ITEM_TYPE_END,
1166 };
1167
1168 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1169         RTE_FLOW_ITEM_TYPE_ETH,
1170         RTE_FLOW_ITEM_TYPE_VLAN,
1171         RTE_FLOW_ITEM_TYPE_IPV4,
1172         RTE_FLOW_ITEM_TYPE_TCP,
1173         RTE_FLOW_ITEM_TYPE_VF,
1174         RTE_FLOW_ITEM_TYPE_END,
1175 };
1176
1177 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1178         RTE_FLOW_ITEM_TYPE_ETH,
1179         RTE_FLOW_ITEM_TYPE_VLAN,
1180         RTE_FLOW_ITEM_TYPE_IPV4,
1181         RTE_FLOW_ITEM_TYPE_SCTP,
1182         RTE_FLOW_ITEM_TYPE_VF,
1183         RTE_FLOW_ITEM_TYPE_END,
1184 };
1185
1186 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1187         RTE_FLOW_ITEM_TYPE_ETH,
1188         RTE_FLOW_ITEM_TYPE_VLAN,
1189         RTE_FLOW_ITEM_TYPE_IPV6,
1190         RTE_FLOW_ITEM_TYPE_VF,
1191         RTE_FLOW_ITEM_TYPE_END,
1192 };
1193
1194 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1195         RTE_FLOW_ITEM_TYPE_ETH,
1196         RTE_FLOW_ITEM_TYPE_VLAN,
1197         RTE_FLOW_ITEM_TYPE_IPV6,
1198         RTE_FLOW_ITEM_TYPE_UDP,
1199         RTE_FLOW_ITEM_TYPE_VF,
1200         RTE_FLOW_ITEM_TYPE_END,
1201 };
1202
1203 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1204         RTE_FLOW_ITEM_TYPE_ETH,
1205         RTE_FLOW_ITEM_TYPE_VLAN,
1206         RTE_FLOW_ITEM_TYPE_IPV6,
1207         RTE_FLOW_ITEM_TYPE_TCP,
1208         RTE_FLOW_ITEM_TYPE_VF,
1209         RTE_FLOW_ITEM_TYPE_END,
1210 };
1211
1212 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1213         RTE_FLOW_ITEM_TYPE_ETH,
1214         RTE_FLOW_ITEM_TYPE_VLAN,
1215         RTE_FLOW_ITEM_TYPE_IPV6,
1216         RTE_FLOW_ITEM_TYPE_SCTP,
1217         RTE_FLOW_ITEM_TYPE_VF,
1218         RTE_FLOW_ITEM_TYPE_END,
1219 };
1220
1221 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1222         RTE_FLOW_ITEM_TYPE_ETH,
1223         RTE_FLOW_ITEM_TYPE_VLAN,
1224         RTE_FLOW_ITEM_TYPE_RAW,
1225         RTE_FLOW_ITEM_TYPE_VF,
1226         RTE_FLOW_ITEM_TYPE_END,
1227 };
1228
1229 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1230         RTE_FLOW_ITEM_TYPE_ETH,
1231         RTE_FLOW_ITEM_TYPE_VLAN,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_RAW,
1234         RTE_FLOW_ITEM_TYPE_VF,
1235         RTE_FLOW_ITEM_TYPE_END,
1236 };
1237
1238 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1239         RTE_FLOW_ITEM_TYPE_ETH,
1240         RTE_FLOW_ITEM_TYPE_VLAN,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_RAW,
1244         RTE_FLOW_ITEM_TYPE_VF,
1245         RTE_FLOW_ITEM_TYPE_END,
1246 };
1247
1248 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1249         RTE_FLOW_ITEM_TYPE_ETH,
1250         RTE_FLOW_ITEM_TYPE_VLAN,
1251         RTE_FLOW_ITEM_TYPE_IPV4,
1252         RTE_FLOW_ITEM_TYPE_RAW,
1253         RTE_FLOW_ITEM_TYPE_VF,
1254         RTE_FLOW_ITEM_TYPE_END,
1255 };
1256
1257 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1258         RTE_FLOW_ITEM_TYPE_ETH,
1259         RTE_FLOW_ITEM_TYPE_VLAN,
1260         RTE_FLOW_ITEM_TYPE_IPV4,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_RAW,
1263         RTE_FLOW_ITEM_TYPE_VF,
1264         RTE_FLOW_ITEM_TYPE_END,
1265 };
1266
1267 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1268         RTE_FLOW_ITEM_TYPE_ETH,
1269         RTE_FLOW_ITEM_TYPE_VLAN,
1270         RTE_FLOW_ITEM_TYPE_IPV4,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_RAW,
1274         RTE_FLOW_ITEM_TYPE_VF,
1275         RTE_FLOW_ITEM_TYPE_END,
1276 };
1277
1278 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1279         RTE_FLOW_ITEM_TYPE_ETH,
1280         RTE_FLOW_ITEM_TYPE_VLAN,
1281         RTE_FLOW_ITEM_TYPE_IPV4,
1282         RTE_FLOW_ITEM_TYPE_UDP,
1283         RTE_FLOW_ITEM_TYPE_RAW,
1284         RTE_FLOW_ITEM_TYPE_VF,
1285         RTE_FLOW_ITEM_TYPE_END,
1286 };
1287
1288 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1289         RTE_FLOW_ITEM_TYPE_ETH,
1290         RTE_FLOW_ITEM_TYPE_VLAN,
1291         RTE_FLOW_ITEM_TYPE_IPV4,
1292         RTE_FLOW_ITEM_TYPE_UDP,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_RAW,
1295         RTE_FLOW_ITEM_TYPE_VF,
1296         RTE_FLOW_ITEM_TYPE_END,
1297 };
1298
1299 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1300         RTE_FLOW_ITEM_TYPE_ETH,
1301         RTE_FLOW_ITEM_TYPE_VLAN,
1302         RTE_FLOW_ITEM_TYPE_IPV4,
1303         RTE_FLOW_ITEM_TYPE_UDP,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_RAW,
1307         RTE_FLOW_ITEM_TYPE_VF,
1308         RTE_FLOW_ITEM_TYPE_END,
1309 };
1310
1311 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1312         RTE_FLOW_ITEM_TYPE_ETH,
1313         RTE_FLOW_ITEM_TYPE_VLAN,
1314         RTE_FLOW_ITEM_TYPE_IPV4,
1315         RTE_FLOW_ITEM_TYPE_TCP,
1316         RTE_FLOW_ITEM_TYPE_RAW,
1317         RTE_FLOW_ITEM_TYPE_VF,
1318         RTE_FLOW_ITEM_TYPE_END,
1319 };
1320
1321 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1322         RTE_FLOW_ITEM_TYPE_ETH,
1323         RTE_FLOW_ITEM_TYPE_VLAN,
1324         RTE_FLOW_ITEM_TYPE_IPV4,
1325         RTE_FLOW_ITEM_TYPE_TCP,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_RAW,
1328         RTE_FLOW_ITEM_TYPE_VF,
1329         RTE_FLOW_ITEM_TYPE_END,
1330 };
1331
1332 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1333         RTE_FLOW_ITEM_TYPE_ETH,
1334         RTE_FLOW_ITEM_TYPE_VLAN,
1335         RTE_FLOW_ITEM_TYPE_IPV4,
1336         RTE_FLOW_ITEM_TYPE_TCP,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_RAW,
1340         RTE_FLOW_ITEM_TYPE_VF,
1341         RTE_FLOW_ITEM_TYPE_END,
1342 };
1343
1344 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1345         RTE_FLOW_ITEM_TYPE_ETH,
1346         RTE_FLOW_ITEM_TYPE_VLAN,
1347         RTE_FLOW_ITEM_TYPE_IPV4,
1348         RTE_FLOW_ITEM_TYPE_SCTP,
1349         RTE_FLOW_ITEM_TYPE_RAW,
1350         RTE_FLOW_ITEM_TYPE_VF,
1351         RTE_FLOW_ITEM_TYPE_END,
1352 };
1353
1354 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1355         RTE_FLOW_ITEM_TYPE_ETH,
1356         RTE_FLOW_ITEM_TYPE_VLAN,
1357         RTE_FLOW_ITEM_TYPE_IPV4,
1358         RTE_FLOW_ITEM_TYPE_SCTP,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_RAW,
1361         RTE_FLOW_ITEM_TYPE_VF,
1362         RTE_FLOW_ITEM_TYPE_END,
1363 };
1364
1365 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1366         RTE_FLOW_ITEM_TYPE_ETH,
1367         RTE_FLOW_ITEM_TYPE_VLAN,
1368         RTE_FLOW_ITEM_TYPE_IPV4,
1369         RTE_FLOW_ITEM_TYPE_SCTP,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_RAW,
1373         RTE_FLOW_ITEM_TYPE_VF,
1374         RTE_FLOW_ITEM_TYPE_END,
1375 };
1376
1377 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1378         RTE_FLOW_ITEM_TYPE_ETH,
1379         RTE_FLOW_ITEM_TYPE_VLAN,
1380         RTE_FLOW_ITEM_TYPE_IPV6,
1381         RTE_FLOW_ITEM_TYPE_RAW,
1382         RTE_FLOW_ITEM_TYPE_VF,
1383         RTE_FLOW_ITEM_TYPE_END,
1384 };
1385
1386 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1387         RTE_FLOW_ITEM_TYPE_ETH,
1388         RTE_FLOW_ITEM_TYPE_VLAN,
1389         RTE_FLOW_ITEM_TYPE_IPV6,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_RAW,
1392         RTE_FLOW_ITEM_TYPE_VF,
1393         RTE_FLOW_ITEM_TYPE_END,
1394 };
1395
1396 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1397         RTE_FLOW_ITEM_TYPE_ETH,
1398         RTE_FLOW_ITEM_TYPE_VLAN,
1399         RTE_FLOW_ITEM_TYPE_IPV6,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_RAW,
1403         RTE_FLOW_ITEM_TYPE_VF,
1404         RTE_FLOW_ITEM_TYPE_END,
1405 };
1406
1407 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1408         RTE_FLOW_ITEM_TYPE_ETH,
1409         RTE_FLOW_ITEM_TYPE_VLAN,
1410         RTE_FLOW_ITEM_TYPE_IPV6,
1411         RTE_FLOW_ITEM_TYPE_UDP,
1412         RTE_FLOW_ITEM_TYPE_RAW,
1413         RTE_FLOW_ITEM_TYPE_VF,
1414         RTE_FLOW_ITEM_TYPE_END,
1415 };
1416
1417 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1418         RTE_FLOW_ITEM_TYPE_ETH,
1419         RTE_FLOW_ITEM_TYPE_VLAN,
1420         RTE_FLOW_ITEM_TYPE_IPV6,
1421         RTE_FLOW_ITEM_TYPE_UDP,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_RAW,
1424         RTE_FLOW_ITEM_TYPE_VF,
1425         RTE_FLOW_ITEM_TYPE_END,
1426 };
1427
1428 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1429         RTE_FLOW_ITEM_TYPE_ETH,
1430         RTE_FLOW_ITEM_TYPE_VLAN,
1431         RTE_FLOW_ITEM_TYPE_IPV6,
1432         RTE_FLOW_ITEM_TYPE_UDP,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_RAW,
1436         RTE_FLOW_ITEM_TYPE_VF,
1437         RTE_FLOW_ITEM_TYPE_END,
1438 };
1439
1440 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1441         RTE_FLOW_ITEM_TYPE_ETH,
1442         RTE_FLOW_ITEM_TYPE_VLAN,
1443         RTE_FLOW_ITEM_TYPE_IPV6,
1444         RTE_FLOW_ITEM_TYPE_TCP,
1445         RTE_FLOW_ITEM_TYPE_RAW,
1446         RTE_FLOW_ITEM_TYPE_VF,
1447         RTE_FLOW_ITEM_TYPE_END,
1448 };
1449
1450 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1451         RTE_FLOW_ITEM_TYPE_ETH,
1452         RTE_FLOW_ITEM_TYPE_VLAN,
1453         RTE_FLOW_ITEM_TYPE_IPV6,
1454         RTE_FLOW_ITEM_TYPE_TCP,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_RAW,
1457         RTE_FLOW_ITEM_TYPE_VF,
1458         RTE_FLOW_ITEM_TYPE_END,
1459 };
1460
1461 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1462         RTE_FLOW_ITEM_TYPE_ETH,
1463         RTE_FLOW_ITEM_TYPE_VLAN,
1464         RTE_FLOW_ITEM_TYPE_IPV6,
1465         RTE_FLOW_ITEM_TYPE_TCP,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_RAW,
1469         RTE_FLOW_ITEM_TYPE_VF,
1470         RTE_FLOW_ITEM_TYPE_END,
1471 };
1472
1473 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1474         RTE_FLOW_ITEM_TYPE_ETH,
1475         RTE_FLOW_ITEM_TYPE_VLAN,
1476         RTE_FLOW_ITEM_TYPE_IPV6,
1477         RTE_FLOW_ITEM_TYPE_SCTP,
1478         RTE_FLOW_ITEM_TYPE_RAW,
1479         RTE_FLOW_ITEM_TYPE_VF,
1480         RTE_FLOW_ITEM_TYPE_END,
1481 };
1482
1483 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1484         RTE_FLOW_ITEM_TYPE_ETH,
1485         RTE_FLOW_ITEM_TYPE_VLAN,
1486         RTE_FLOW_ITEM_TYPE_IPV6,
1487         RTE_FLOW_ITEM_TYPE_SCTP,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_RAW,
1490         RTE_FLOW_ITEM_TYPE_VF,
1491         RTE_FLOW_ITEM_TYPE_END,
1492 };
1493
1494 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1495         RTE_FLOW_ITEM_TYPE_ETH,
1496         RTE_FLOW_ITEM_TYPE_VLAN,
1497         RTE_FLOW_ITEM_TYPE_IPV6,
1498         RTE_FLOW_ITEM_TYPE_SCTP,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_RAW,
1502         RTE_FLOW_ITEM_TYPE_VF,
1503         RTE_FLOW_ITEM_TYPE_END,
1504 };
1505
1506 /* Pattern matched tunnel filter */
1507 static enum rte_flow_item_type pattern_vxlan_1[] = {
1508         RTE_FLOW_ITEM_TYPE_ETH,
1509         RTE_FLOW_ITEM_TYPE_IPV4,
1510         RTE_FLOW_ITEM_TYPE_UDP,
1511         RTE_FLOW_ITEM_TYPE_VXLAN,
1512         RTE_FLOW_ITEM_TYPE_ETH,
1513         RTE_FLOW_ITEM_TYPE_END,
1514 };
1515
1516 static enum rte_flow_item_type pattern_vxlan_2[] = {
1517         RTE_FLOW_ITEM_TYPE_ETH,
1518         RTE_FLOW_ITEM_TYPE_IPV6,
1519         RTE_FLOW_ITEM_TYPE_UDP,
1520         RTE_FLOW_ITEM_TYPE_VXLAN,
1521         RTE_FLOW_ITEM_TYPE_ETH,
1522         RTE_FLOW_ITEM_TYPE_END,
1523 };
1524
1525 static enum rte_flow_item_type pattern_vxlan_3[] = {
1526         RTE_FLOW_ITEM_TYPE_ETH,
1527         RTE_FLOW_ITEM_TYPE_IPV4,
1528         RTE_FLOW_ITEM_TYPE_UDP,
1529         RTE_FLOW_ITEM_TYPE_VXLAN,
1530         RTE_FLOW_ITEM_TYPE_ETH,
1531         RTE_FLOW_ITEM_TYPE_VLAN,
1532         RTE_FLOW_ITEM_TYPE_END,
1533 };
1534
1535 static enum rte_flow_item_type pattern_vxlan_4[] = {
1536         RTE_FLOW_ITEM_TYPE_ETH,
1537         RTE_FLOW_ITEM_TYPE_IPV6,
1538         RTE_FLOW_ITEM_TYPE_UDP,
1539         RTE_FLOW_ITEM_TYPE_VXLAN,
1540         RTE_FLOW_ITEM_TYPE_ETH,
1541         RTE_FLOW_ITEM_TYPE_VLAN,
1542         RTE_FLOW_ITEM_TYPE_END,
1543 };
1544
1545 static enum rte_flow_item_type pattern_nvgre_1[] = {
1546         RTE_FLOW_ITEM_TYPE_ETH,
1547         RTE_FLOW_ITEM_TYPE_IPV4,
1548         RTE_FLOW_ITEM_TYPE_NVGRE,
1549         RTE_FLOW_ITEM_TYPE_ETH,
1550         RTE_FLOW_ITEM_TYPE_END,
1551 };
1552
1553 static enum rte_flow_item_type pattern_nvgre_2[] = {
1554         RTE_FLOW_ITEM_TYPE_ETH,
1555         RTE_FLOW_ITEM_TYPE_IPV6,
1556         RTE_FLOW_ITEM_TYPE_NVGRE,
1557         RTE_FLOW_ITEM_TYPE_ETH,
1558         RTE_FLOW_ITEM_TYPE_END,
1559 };
1560
1561 static enum rte_flow_item_type pattern_nvgre_3[] = {
1562         RTE_FLOW_ITEM_TYPE_ETH,
1563         RTE_FLOW_ITEM_TYPE_IPV4,
1564         RTE_FLOW_ITEM_TYPE_NVGRE,
1565         RTE_FLOW_ITEM_TYPE_ETH,
1566         RTE_FLOW_ITEM_TYPE_VLAN,
1567         RTE_FLOW_ITEM_TYPE_END,
1568 };
1569
1570 static enum rte_flow_item_type pattern_nvgre_4[] = {
1571         RTE_FLOW_ITEM_TYPE_ETH,
1572         RTE_FLOW_ITEM_TYPE_IPV6,
1573         RTE_FLOW_ITEM_TYPE_NVGRE,
1574         RTE_FLOW_ITEM_TYPE_ETH,
1575         RTE_FLOW_ITEM_TYPE_VLAN,
1576         RTE_FLOW_ITEM_TYPE_END,
1577 };
1578
1579 static enum rte_flow_item_type pattern_mpls_1[] = {
1580         RTE_FLOW_ITEM_TYPE_ETH,
1581         RTE_FLOW_ITEM_TYPE_IPV4,
1582         RTE_FLOW_ITEM_TYPE_UDP,
1583         RTE_FLOW_ITEM_TYPE_MPLS,
1584         RTE_FLOW_ITEM_TYPE_END,
1585 };
1586
1587 static enum rte_flow_item_type pattern_mpls_2[] = {
1588         RTE_FLOW_ITEM_TYPE_ETH,
1589         RTE_FLOW_ITEM_TYPE_IPV6,
1590         RTE_FLOW_ITEM_TYPE_UDP,
1591         RTE_FLOW_ITEM_TYPE_MPLS,
1592         RTE_FLOW_ITEM_TYPE_END,
1593 };
1594
1595 static enum rte_flow_item_type pattern_mpls_3[] = {
1596         RTE_FLOW_ITEM_TYPE_ETH,
1597         RTE_FLOW_ITEM_TYPE_IPV4,
1598         RTE_FLOW_ITEM_TYPE_GRE,
1599         RTE_FLOW_ITEM_TYPE_MPLS,
1600         RTE_FLOW_ITEM_TYPE_END,
1601 };
1602
1603 static enum rte_flow_item_type pattern_mpls_4[] = {
1604         RTE_FLOW_ITEM_TYPE_ETH,
1605         RTE_FLOW_ITEM_TYPE_IPV6,
1606         RTE_FLOW_ITEM_TYPE_GRE,
1607         RTE_FLOW_ITEM_TYPE_MPLS,
1608         RTE_FLOW_ITEM_TYPE_END,
1609 };
1610
1611 static enum rte_flow_item_type pattern_qinq_1[] = {
1612         RTE_FLOW_ITEM_TYPE_ETH,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_VLAN,
1615         RTE_FLOW_ITEM_TYPE_END,
1616 };
1617
1618 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1619         /* Ethertype */
1620         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1621         /* FDIR - support default flow type without flexible payload*/
1622         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1623         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1636         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1637         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1638         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1639         /* FDIR - support default flow type with flexible payload */
1640         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1641         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1665         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1666         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1667         /* FDIR - support single vlan input set */
1668         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1704         /* FDIR - support VF item */
1705         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1776         /* VXLAN */
1777         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1778         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1779         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1780         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1781         /* NVGRE */
1782         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1783         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1784         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1785         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1786         /* MPLSoUDP & MPLSoGRE */
1787         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1788         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1789         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1790         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1791         /* GTP-C & GTP-U */
1792         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1793         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1794         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1795         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1796         /* QINQ */
1797         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1798 };
1799
1800 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1801         do {                                                            \
1802                 act = actions + index;                                  \
1803                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1804                         index++;                                        \
1805                         act = actions + index;                          \
1806                 }                                                       \
1807         } while (0)
1808
1809 /* Find the first VOID or non-VOID item pointer */
1810 static const struct rte_flow_item *
1811 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1812 {
1813         bool is_find;
1814
1815         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1816                 if (is_void)
1817                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1818                 else
1819                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1820                 if (is_find)
1821                         break;
1822                 item++;
1823         }
1824         return item;
1825 }
1826
1827 /* Skip all VOID items of the pattern */
1828 static void
1829 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1830                             const struct rte_flow_item *pattern)
1831 {
1832         uint32_t cpy_count = 0;
1833         const struct rte_flow_item *pb = pattern, *pe = pattern;
1834
1835         for (;;) {
1836                 /* Find a non-void item first */
1837                 pb = i40e_find_first_item(pb, false);
1838                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1839                         pe = pb;
1840                         break;
1841                 }
1842
1843                 /* Find a void item */
1844                 pe = i40e_find_first_item(pb + 1, true);
1845
1846                 cpy_count = pe - pb;
1847                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1848
1849                 items += cpy_count;
1850
1851                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1852                         pb = pe;
1853                         break;
1854                 }
1855
1856                 pb = pe + 1;
1857         }
1858         /* Copy the END item. */
1859         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1860 }
1861
1862 /* Check if the pattern matches a supported item type array */
1863 static bool
1864 i40e_match_pattern(enum rte_flow_item_type *item_array,
1865                    struct rte_flow_item *pattern)
1866 {
1867         struct rte_flow_item *item = pattern;
1868
1869         while ((*item_array == item->type) &&
1870                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1871                 item_array++;
1872                 item++;
1873         }
1874
1875         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1876                 item->type == RTE_FLOW_ITEM_TYPE_END);
1877 }
1878
1879 /* Find if there's parse filter function matched */
1880 static parse_filter_t
1881 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1882 {
1883         parse_filter_t parse_filter = NULL;
1884         uint8_t i = *idx;
1885
1886         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1887                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1888                                         pattern)) {
1889                         parse_filter = i40e_supported_patterns[i].parse_filter;
1890                         break;
1891                 }
1892         }
1893
1894         *idx = ++i;
1895
1896         return parse_filter;
1897 }
1898
1899 /* Parse attributes */
1900 static int
1901 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1902                      struct rte_flow_error *error)
1903 {
1904         /* Must be input direction */
1905         if (!attr->ingress) {
1906                 rte_flow_error_set(error, EINVAL,
1907                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1908                                    attr, "Only support ingress.");
1909                 return -rte_errno;
1910         }
1911
1912         /* Not supported */
1913         if (attr->egress) {
1914                 rte_flow_error_set(error, EINVAL,
1915                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1916                                    attr, "Not support egress.");
1917                 return -rte_errno;
1918         }
1919
1920         /* Not supported */
1921         if (attr->priority) {
1922                 rte_flow_error_set(error, EINVAL,
1923                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1924                                    attr, "Not support priority.");
1925                 return -rte_errno;
1926         }
1927
1928         /* Not supported */
1929         if (attr->group) {
1930                 rte_flow_error_set(error, EINVAL,
1931                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1932                                    attr, "Not support group.");
1933                 return -rte_errno;
1934         }
1935
1936         return 0;
1937 }
1938
1939 static uint16_t
1940 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1941 {
1942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         int qinq = dev->data->dev_conf.rxmode.offloads &
1944                 DEV_RX_OFFLOAD_VLAN_EXTEND;
1945         uint64_t reg_r = 0;
1946         uint16_t reg_id;
1947         uint16_t tpid;
1948
1949         if (qinq)
1950                 reg_id = 2;
1951         else
1952                 reg_id = 3;
1953
1954         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1955                                     &reg_r, NULL);
1956
1957         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1958
1959         return tpid;
1960 }
1961
1962 /* 1. Last in item should be NULL as range is not supported.
1963  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1964  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1965  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1966  *    FF:FF:FF:FF:FF:FF
1967  * 5. Ether_type mask should be 0xFFFF.
1968  */
1969 static int
1970 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1971                                   const struct rte_flow_item *pattern,
1972                                   struct rte_flow_error *error,
1973                                   struct rte_eth_ethertype_filter *filter)
1974 {
1975         const struct rte_flow_item *item = pattern;
1976         const struct rte_flow_item_eth *eth_spec;
1977         const struct rte_flow_item_eth *eth_mask;
1978         enum rte_flow_item_type item_type;
1979         uint16_t outer_tpid;
1980
1981         outer_tpid = i40e_get_outer_vlan(dev);
1982
1983         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1984                 if (item->last) {
1985                         rte_flow_error_set(error, EINVAL,
1986                                            RTE_FLOW_ERROR_TYPE_ITEM,
1987                                            item,
1988                                            "Not support range");
1989                         return -rte_errno;
1990                 }
1991                 item_type = item->type;
1992                 switch (item_type) {
1993                 case RTE_FLOW_ITEM_TYPE_ETH:
1994                         eth_spec = item->spec;
1995                         eth_mask = item->mask;
1996                         /* Get the MAC info. */
1997                         if (!eth_spec || !eth_mask) {
1998                                 rte_flow_error_set(error, EINVAL,
1999                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2000                                                    item,
2001                                                    "NULL ETH spec/mask");
2002                                 return -rte_errno;
2003                         }
2004
2005                         /* Mask bits of source MAC address must be full of 0.
2006                          * Mask bits of destination MAC address must be full
2007                          * of 1 or full of 0.
2008                          */
2009                         if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2010                             (!rte_is_zero_ether_addr(&eth_mask->dst) &&
2011                              !rte_is_broadcast_ether_addr(&eth_mask->dst))) {
2012                                 rte_flow_error_set(error, EINVAL,
2013                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2014                                                    item,
2015                                                    "Invalid MAC_addr mask");
2016                                 return -rte_errno;
2017                         }
2018
2019                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2020                                 rte_flow_error_set(error, EINVAL,
2021                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2022                                                    item,
2023                                                    "Invalid ethertype mask");
2024                                 return -rte_errno;
2025                         }
2026
2027                         /* If mask bits of destination MAC address
2028                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2029                          */
2030                         if (rte_is_broadcast_ether_addr(&eth_mask->dst)) {
2031                                 filter->mac_addr = eth_spec->dst;
2032                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2033                         } else {
2034                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2035                         }
2036                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2037
2038                         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2039                             filter->ether_type == RTE_ETHER_TYPE_IPV6 ||
2040                             filter->ether_type == RTE_ETHER_TYPE_LLDP ||
2041                             filter->ether_type == outer_tpid) {
2042                                 rte_flow_error_set(error, EINVAL,
2043                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2044                                                    item,
2045                                                    "Unsupported ether_type in"
2046                                                    " control packet filter.");
2047                                 return -rte_errno;
2048                         }
2049                         break;
2050                 default:
2051                         break;
2052                 }
2053         }
2054
2055         return 0;
2056 }
2057
2058 /* Ethertype action only supports QUEUE or DROP. */
2059 static int
2060 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2061                                  const struct rte_flow_action *actions,
2062                                  struct rte_flow_error *error,
2063                                  struct rte_eth_ethertype_filter *filter)
2064 {
2065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066         const struct rte_flow_action *act;
2067         const struct rte_flow_action_queue *act_q;
2068         uint32_t index = 0;
2069
2070         /* Check if the first non-void action is QUEUE or DROP. */
2071         NEXT_ITEM_OF_ACTION(act, actions, index);
2072         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2073             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2074                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2075                                    act, "Not supported action.");
2076                 return -rte_errno;
2077         }
2078
2079         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2080                 act_q = act->conf;
2081                 filter->queue = act_q->index;
2082                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2083                         rte_flow_error_set(error, EINVAL,
2084                                            RTE_FLOW_ERROR_TYPE_ACTION,
2085                                            act, "Invalid queue ID for"
2086                                            " ethertype_filter.");
2087                         return -rte_errno;
2088                 }
2089         } else {
2090                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2091         }
2092
2093         /* Check if the next non-void item is END */
2094         index++;
2095         NEXT_ITEM_OF_ACTION(act, actions, index);
2096         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2097                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2098                                    act, "Not supported action.");
2099                 return -rte_errno;
2100         }
2101
2102         return 0;
2103 }
2104
2105 static int
2106 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2107                                  const struct rte_flow_attr *attr,
2108                                  const struct rte_flow_item pattern[],
2109                                  const struct rte_flow_action actions[],
2110                                  struct rte_flow_error *error,
2111                                  union i40e_filter_t *filter)
2112 {
2113         struct rte_eth_ethertype_filter *ethertype_filter =
2114                 &filter->ethertype_filter;
2115         int ret;
2116
2117         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2118                                                 ethertype_filter);
2119         if (ret)
2120                 return ret;
2121
2122         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2123                                                ethertype_filter);
2124         if (ret)
2125                 return ret;
2126
2127         ret = i40e_flow_parse_attr(attr, error);
2128         if (ret)
2129                 return ret;
2130
2131         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2132
2133         return ret;
2134 }
2135
2136 static int
2137 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2138                          const struct rte_flow_item_raw *raw_spec,
2139                          struct rte_flow_error *error)
2140 {
2141         if (!raw_spec->relative) {
2142                 rte_flow_error_set(error, EINVAL,
2143                                    RTE_FLOW_ERROR_TYPE_ITEM,
2144                                    item,
2145                                    "Relative should be 1.");
2146                 return -rte_errno;
2147         }
2148
2149         if (raw_spec->offset % sizeof(uint16_t)) {
2150                 rte_flow_error_set(error, EINVAL,
2151                                    RTE_FLOW_ERROR_TYPE_ITEM,
2152                                    item,
2153                                    "Offset should be even.");
2154                 return -rte_errno;
2155         }
2156
2157         if (raw_spec->search || raw_spec->limit) {
2158                 rte_flow_error_set(error, EINVAL,
2159                                    RTE_FLOW_ERROR_TYPE_ITEM,
2160                                    item,
2161                                    "search or limit is not supported.");
2162                 return -rte_errno;
2163         }
2164
2165         if (raw_spec->offset < 0) {
2166                 rte_flow_error_set(error, EINVAL,
2167                                    RTE_FLOW_ERROR_TYPE_ITEM,
2168                                    item,
2169                                    "Offset should be non-negative.");
2170                 return -rte_errno;
2171         }
2172         return 0;
2173 }
2174
2175 static int
2176 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2177                          struct i40e_fdir_flex_pit *flex_pit,
2178                          enum i40e_flxpld_layer_idx layer_idx,
2179                          uint8_t raw_id)
2180 {
2181         uint8_t field_idx;
2182
2183         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2184         /* Check if the configuration is conflicted */
2185         if (pf->fdir.flex_pit_flag[layer_idx] &&
2186             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2187              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2188              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2189                 return -1;
2190
2191         /* Check if the configuration exists. */
2192         if (pf->fdir.flex_pit_flag[layer_idx] &&
2193             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2194              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2195              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2196                 return 1;
2197
2198         pf->fdir.flex_set[field_idx].src_offset =
2199                 flex_pit->src_offset;
2200         pf->fdir.flex_set[field_idx].size =
2201                 flex_pit->size;
2202         pf->fdir.flex_set[field_idx].dst_offset =
2203                 flex_pit->dst_offset;
2204
2205         return 0;
2206 }
2207
2208 static int
2209 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2210                           enum i40e_filter_pctype pctype,
2211                           uint8_t *mask)
2212 {
2213         struct i40e_fdir_flex_mask flex_mask;
2214         uint16_t mask_tmp;
2215         uint8_t i, nb_bitmask = 0;
2216
2217         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2218         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2219                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2220                 if (mask_tmp) {
2221                         flex_mask.word_mask |=
2222                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2223                         if (mask_tmp != UINT16_MAX) {
2224                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2225                                 flex_mask.bitmask[nb_bitmask].offset =
2226                                         i / sizeof(uint16_t);
2227                                 nb_bitmask++;
2228                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2229                                         return -1;
2230                         }
2231                 }
2232         }
2233         flex_mask.nb_bitmask = nb_bitmask;
2234
2235         if (pf->fdir.flex_mask_flag[pctype] &&
2236             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2237                     sizeof(struct i40e_fdir_flex_mask))))
2238                 return -2;
2239         else if (pf->fdir.flex_mask_flag[pctype] &&
2240                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2241                           sizeof(struct i40e_fdir_flex_mask))))
2242                 return 1;
2243
2244         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2245                sizeof(struct i40e_fdir_flex_mask));
2246         return 0;
2247 }
2248
2249 static void
2250 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2251                             enum i40e_flxpld_layer_idx layer_idx,
2252                             uint8_t raw_id)
2253 {
2254         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2255         uint32_t flx_pit, flx_ort;
2256         uint8_t field_idx;
2257         uint16_t min_next_off = 0;  /* in words */
2258         uint8_t i;
2259
2260         if (raw_id) {
2261                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2262                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2263                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2264                 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2265         }
2266
2267         /* Set flex pit */
2268         for (i = 0; i < raw_id; i++) {
2269                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2270                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2271                                      pf->fdir.flex_set[field_idx].size,
2272                                      pf->fdir.flex_set[field_idx].dst_offset);
2273
2274                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2275                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2276                         pf->fdir.flex_set[field_idx].size;
2277         }
2278
2279         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2280                 /* set the non-used register obeying register's constrain */
2281                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2282                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2283                                      NONUSE_FLX_PIT_DEST_OFF);
2284                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2285                 min_next_off++;
2286         }
2287
2288         pf->fdir.flex_pit_flag[layer_idx] = 1;
2289 }
2290
2291 static void
2292 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2293                             enum i40e_filter_pctype pctype)
2294 {
2295         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2296         struct i40e_fdir_flex_mask *flex_mask;
2297         uint32_t flxinset, fd_mask;
2298         uint8_t i;
2299
2300         /* Set flex mask */
2301         flex_mask = &pf->fdir.flex_mask[pctype];
2302         flxinset = (flex_mask->word_mask <<
2303                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2304                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2305         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2306
2307         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2308                 fd_mask = (flex_mask->bitmask[i].mask <<
2309                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2310                         I40E_PRTQF_FD_MSK_MASK_MASK;
2311                 fd_mask |= ((flex_mask->bitmask[i].offset +
2312                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2313                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2314                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2315                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2316         }
2317
2318         pf->fdir.flex_mask_flag[pctype] = 1;
2319 }
2320
2321 static int
2322 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2323                          enum i40e_filter_pctype pctype,
2324                          uint64_t input_set)
2325 {
2326         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2327         uint64_t inset_reg = 0;
2328         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2329         int i, num;
2330
2331         /* Check if the input set is valid */
2332         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2333                                     input_set) != 0) {
2334                 PMD_DRV_LOG(ERR, "Invalid input set");
2335                 return -EINVAL;
2336         }
2337
2338         /* Check if the configuration is conflicted */
2339         if (pf->fdir.inset_flag[pctype] &&
2340             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2341                 return -1;
2342
2343         if (pf->fdir.inset_flag[pctype] &&
2344             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2345                 return 0;
2346
2347         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2348                                            I40E_INSET_MASK_NUM_REG);
2349         if (num < 0)
2350                 return -EINVAL;
2351
2352         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2353
2354         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2355                              (uint32_t)(inset_reg & UINT32_MAX));
2356         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2357                              (uint32_t)((inset_reg >>
2358                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2359
2360         for (i = 0; i < num; i++)
2361                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2362                                      mask_reg[i]);
2363
2364         /*clear unused mask registers of the pctype */
2365         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2366                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2367         I40E_WRITE_FLUSH(hw);
2368
2369         pf->fdir.input_set[pctype] = input_set;
2370         pf->fdir.inset_flag[pctype] = 1;
2371         return 0;
2372 }
2373
2374 static uint8_t
2375 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2376                                 enum rte_flow_item_type item_type,
2377                                 struct i40e_fdir_filter_conf *filter)
2378 {
2379         struct i40e_customized_pctype *cus_pctype = NULL;
2380
2381         switch (item_type) {
2382         case RTE_FLOW_ITEM_TYPE_GTPC:
2383                 cus_pctype = i40e_find_customized_pctype(pf,
2384                                                          I40E_CUSTOMIZED_GTPC);
2385                 break;
2386         case RTE_FLOW_ITEM_TYPE_GTPU:
2387                 if (!filter->input.flow_ext.inner_ip)
2388                         cus_pctype = i40e_find_customized_pctype(pf,
2389                                                          I40E_CUSTOMIZED_GTPU);
2390                 else if (filter->input.flow_ext.iip_type ==
2391                          I40E_FDIR_IPTYPE_IPV4)
2392                         cus_pctype = i40e_find_customized_pctype(pf,
2393                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2394                 else if (filter->input.flow_ext.iip_type ==
2395                          I40E_FDIR_IPTYPE_IPV6)
2396                         cus_pctype = i40e_find_customized_pctype(pf,
2397                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2398                 break;
2399         default:
2400                 PMD_DRV_LOG(ERR, "Unsupported item type");
2401                 break;
2402         }
2403
2404         if (cus_pctype && cus_pctype->valid)
2405                 return cus_pctype->pctype;
2406
2407         return I40E_FILTER_PCTYPE_INVALID;
2408 }
2409
2410 /* 1. Last in item should be NULL as range is not supported.
2411  * 2. Supported patterns: refer to array i40e_supported_patterns.
2412  * 3. Default supported flow type and input set: refer to array
2413  *    valid_fdir_inset_table in i40e_ethdev.c.
2414  * 4. Mask of fields which need to be matched should be
2415  *    filled with 1.
2416  * 5. Mask of fields which needn't to be matched should be
2417  *    filled with 0.
2418  * 6. GTP profile supports GTPv1 only.
2419  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2420  */
2421 static int
2422 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2423                              const struct rte_flow_attr *attr,
2424                              const struct rte_flow_item *pattern,
2425                              struct rte_flow_error *error,
2426                              struct i40e_fdir_filter_conf *filter)
2427 {
2428         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2429         const struct rte_flow_item *item = pattern;
2430         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2431         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2432         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2433         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2434         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2435         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2436         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2437         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2438         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2439         const struct rte_flow_item_vf *vf_spec;
2440
2441         uint8_t pctype = 0;
2442         uint64_t input_set = I40E_INSET_NONE;
2443         uint16_t frag_off;
2444         enum rte_flow_item_type item_type;
2445         enum rte_flow_item_type next_type;
2446         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2447         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2448         uint32_t i, j;
2449         uint8_t  ipv6_addr_mask[16] = {
2450                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2451                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2452         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2453         uint8_t raw_id = 0;
2454         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2455         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2456         struct i40e_fdir_flex_pit flex_pit;
2457         uint8_t next_dst_off = 0;
2458         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2459         uint16_t flex_size;
2460         bool cfg_flex_pit = true;
2461         bool cfg_flex_msk = true;
2462         uint16_t outer_tpid;
2463         uint16_t ether_type;
2464         uint32_t vtc_flow_cpu;
2465         bool outer_ip = true;
2466         int ret;
2467
2468         memset(off_arr, 0, sizeof(off_arr));
2469         memset(len_arr, 0, sizeof(len_arr));
2470         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2471         outer_tpid = i40e_get_outer_vlan(dev);
2472         filter->input.flow_ext.customized_pctype = false;
2473         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2474                 if (item->last) {
2475                         rte_flow_error_set(error, EINVAL,
2476                                            RTE_FLOW_ERROR_TYPE_ITEM,
2477                                            item,
2478                                            "Not support range");
2479                         return -rte_errno;
2480                 }
2481                 item_type = item->type;
2482                 switch (item_type) {
2483                 case RTE_FLOW_ITEM_TYPE_ETH:
2484                         eth_spec = item->spec;
2485                         eth_mask = item->mask;
2486                         next_type = (item + 1)->type;
2487
2488                         if (next_type == RTE_FLOW_ITEM_TYPE_END &&
2489                                                 (!eth_spec || !eth_mask)) {
2490                                 rte_flow_error_set(error, EINVAL,
2491                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2492                                                    item,
2493                                                    "NULL eth spec/mask.");
2494                                 return -rte_errno;
2495                         }
2496
2497                         if (eth_spec && eth_mask) {
2498                                 if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2499                                     !rte_is_zero_ether_addr(&eth_mask->dst)) {
2500                                         rte_flow_error_set(error, EINVAL,
2501                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2502                                                       item,
2503                                                       "Invalid MAC_addr mask.");
2504                                         return -rte_errno;
2505                                 }
2506                         }
2507                         if (eth_spec && eth_mask && eth_mask->type) {
2508                                 if (eth_mask->type != RTE_BE16(0xffff)) {
2509                                         rte_flow_error_set(error, EINVAL,
2510                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2511                                                       item,
2512                                                       "Invalid type mask.");
2513                                         return -rte_errno;
2514                                 }
2515
2516                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2517
2518                                 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN ||
2519                                     ether_type == RTE_ETHER_TYPE_IPV4 ||
2520                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2521                                     ether_type == RTE_ETHER_TYPE_ARP ||
2522                                     ether_type == outer_tpid) {
2523                                         rte_flow_error_set(error, EINVAL,
2524                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2525                                                      item,
2526                                                      "Unsupported ether_type.");
2527                                         return -rte_errno;
2528                                 }
2529                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2530                                 filter->input.flow.l2_flow.ether_type =
2531                                         eth_spec->type;
2532                         }
2533
2534                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2535                         layer_idx = I40E_FLXPLD_L2_IDX;
2536
2537                         break;
2538                 case RTE_FLOW_ITEM_TYPE_VLAN:
2539                         vlan_spec = item->spec;
2540                         vlan_mask = item->mask;
2541
2542                         RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2543                         if (vlan_spec && vlan_mask) {
2544                                 if (vlan_mask->tci ==
2545                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2546                                         input_set |= I40E_INSET_VLAN_INNER;
2547                                         filter->input.flow_ext.vlan_tci =
2548                                                 vlan_spec->tci;
2549                                 }
2550                         }
2551                         if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2552                                 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2553                                         rte_flow_error_set(error, EINVAL,
2554                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2555                                                       item,
2556                                                       "Invalid inner_type"
2557                                                       " mask.");
2558                                         return -rte_errno;
2559                                 }
2560
2561                                 ether_type =
2562                                         rte_be_to_cpu_16(vlan_spec->inner_type);
2563
2564                                 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
2565                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2566                                     ether_type == RTE_ETHER_TYPE_ARP ||
2567                                     ether_type == outer_tpid) {
2568                                         rte_flow_error_set(error, EINVAL,
2569                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2570                                                      item,
2571                                                      "Unsupported inner_type.");
2572                                         return -rte_errno;
2573                                 }
2574                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2575                                 filter->input.flow.l2_flow.ether_type =
2576                                         vlan_spec->inner_type;
2577                         }
2578
2579                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2580                         layer_idx = I40E_FLXPLD_L2_IDX;
2581
2582                         break;
2583                 case RTE_FLOW_ITEM_TYPE_IPV4:
2584                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2585                         ipv4_spec = item->spec;
2586                         ipv4_mask = item->mask;
2587                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2588                         layer_idx = I40E_FLXPLD_L3_IDX;
2589
2590                         if (ipv4_spec && ipv4_mask && outer_ip) {
2591                                 /* Check IPv4 mask and update input set */
2592                                 if (ipv4_mask->hdr.version_ihl ||
2593                                     ipv4_mask->hdr.total_length ||
2594                                     ipv4_mask->hdr.packet_id ||
2595                                     ipv4_mask->hdr.fragment_offset ||
2596                                     ipv4_mask->hdr.hdr_checksum) {
2597                                         rte_flow_error_set(error, EINVAL,
2598                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2599                                                    item,
2600                                                    "Invalid IPv4 mask.");
2601                                         return -rte_errno;
2602                                 }
2603
2604                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2605                                         input_set |= I40E_INSET_IPV4_SRC;
2606                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2607                                         input_set |= I40E_INSET_IPV4_DST;
2608                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2609                                         input_set |= I40E_INSET_IPV4_TOS;
2610                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2611                                         input_set |= I40E_INSET_IPV4_TTL;
2612                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2613                                         input_set |= I40E_INSET_IPV4_PROTO;
2614
2615                                 /* Check if it is fragment. */
2616                                 frag_off = ipv4_spec->hdr.fragment_offset;
2617                                 frag_off = rte_be_to_cpu_16(frag_off);
2618                                 if (frag_off & RTE_IPV4_HDR_OFFSET_MASK ||
2619                                     frag_off & RTE_IPV4_HDR_MF_FLAG)
2620                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2621
2622                                 /* Get the filter info */
2623                                 filter->input.flow.ip4_flow.proto =
2624                                         ipv4_spec->hdr.next_proto_id;
2625                                 filter->input.flow.ip4_flow.tos =
2626                                         ipv4_spec->hdr.type_of_service;
2627                                 filter->input.flow.ip4_flow.ttl =
2628                                         ipv4_spec->hdr.time_to_live;
2629                                 filter->input.flow.ip4_flow.src_ip =
2630                                         ipv4_spec->hdr.src_addr;
2631                                 filter->input.flow.ip4_flow.dst_ip =
2632                                         ipv4_spec->hdr.dst_addr;
2633                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2634                                 filter->input.flow_ext.inner_ip = true;
2635                                 filter->input.flow_ext.iip_type =
2636                                         I40E_FDIR_IPTYPE_IPV4;
2637                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2638                                 rte_flow_error_set(error, EINVAL,
2639                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2640                                                    item,
2641                                                    "Invalid inner IPv4 mask.");
2642                                 return -rte_errno;
2643                         }
2644
2645                         if (outer_ip)
2646                                 outer_ip = false;
2647
2648                         break;
2649                 case RTE_FLOW_ITEM_TYPE_IPV6:
2650                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2651                         ipv6_spec = item->spec;
2652                         ipv6_mask = item->mask;
2653                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2654                         layer_idx = I40E_FLXPLD_L3_IDX;
2655
2656                         if (ipv6_spec && ipv6_mask && outer_ip) {
2657                                 /* Check IPv6 mask and update input set */
2658                                 if (ipv6_mask->hdr.payload_len) {
2659                                         rte_flow_error_set(error, EINVAL,
2660                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2661                                                    item,
2662                                                    "Invalid IPv6 mask");
2663                                         return -rte_errno;
2664                                 }
2665
2666                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2667                                             ipv6_addr_mask,
2668                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2669                                         input_set |= I40E_INSET_IPV6_SRC;
2670                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2671                                             ipv6_addr_mask,
2672                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2673                                         input_set |= I40E_INSET_IPV6_DST;
2674
2675                                 if ((ipv6_mask->hdr.vtc_flow &
2676                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2677                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2678                                         input_set |= I40E_INSET_IPV6_TC;
2679                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2680                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2681                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2682                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2683
2684                                 /* Get filter info */
2685                                 vtc_flow_cpu =
2686                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2687                                 filter->input.flow.ipv6_flow.tc =
2688                                         (uint8_t)(vtc_flow_cpu >>
2689                                                   I40E_FDIR_IPv6_TC_OFFSET);
2690                                 filter->input.flow.ipv6_flow.proto =
2691                                         ipv6_spec->hdr.proto;
2692                                 filter->input.flow.ipv6_flow.hop_limits =
2693                                         ipv6_spec->hdr.hop_limits;
2694
2695                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2696                                            ipv6_spec->hdr.src_addr, 16);
2697                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2698                                            ipv6_spec->hdr.dst_addr, 16);
2699
2700                                 /* Check if it is fragment. */
2701                                 if (ipv6_spec->hdr.proto ==
2702                                     I40E_IPV6_FRAG_HEADER)
2703                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2704                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2705                                 filter->input.flow_ext.inner_ip = true;
2706                                 filter->input.flow_ext.iip_type =
2707                                         I40E_FDIR_IPTYPE_IPV6;
2708                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2709                                 rte_flow_error_set(error, EINVAL,
2710                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2711                                                    item,
2712                                                    "Invalid inner IPv6 mask");
2713                                 return -rte_errno;
2714                         }
2715
2716                         if (outer_ip)
2717                                 outer_ip = false;
2718                         break;
2719                 case RTE_FLOW_ITEM_TYPE_TCP:
2720                         tcp_spec = item->spec;
2721                         tcp_mask = item->mask;
2722
2723                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2724                                 pctype =
2725                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2726                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2727                                 pctype =
2728                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2729                         if (tcp_spec && tcp_mask) {
2730                                 /* Check TCP mask and update input set */
2731                                 if (tcp_mask->hdr.sent_seq ||
2732                                     tcp_mask->hdr.recv_ack ||
2733                                     tcp_mask->hdr.data_off ||
2734                                     tcp_mask->hdr.tcp_flags ||
2735                                     tcp_mask->hdr.rx_win ||
2736                                     tcp_mask->hdr.cksum ||
2737                                     tcp_mask->hdr.tcp_urp) {
2738                                         rte_flow_error_set(error, EINVAL,
2739                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2740                                                    item,
2741                                                    "Invalid TCP mask");
2742                                         return -rte_errno;
2743                                 }
2744
2745                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2746                                         input_set |= I40E_INSET_SRC_PORT;
2747                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2748                                         input_set |= I40E_INSET_DST_PORT;
2749
2750                                 /* Get filter info */
2751                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2752                                         filter->input.flow.tcp4_flow.src_port =
2753                                                 tcp_spec->hdr.src_port;
2754                                         filter->input.flow.tcp4_flow.dst_port =
2755                                                 tcp_spec->hdr.dst_port;
2756                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2757                                         filter->input.flow.tcp6_flow.src_port =
2758                                                 tcp_spec->hdr.src_port;
2759                                         filter->input.flow.tcp6_flow.dst_port =
2760                                                 tcp_spec->hdr.dst_port;
2761                                 }
2762                         }
2763
2764                         layer_idx = I40E_FLXPLD_L4_IDX;
2765
2766                         break;
2767                 case RTE_FLOW_ITEM_TYPE_UDP:
2768                         udp_spec = item->spec;
2769                         udp_mask = item->mask;
2770
2771                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2772                                 pctype =
2773                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2774                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2775                                 pctype =
2776                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2777
2778                         if (udp_spec && udp_mask) {
2779                                 /* Check UDP mask and update input set*/
2780                                 if (udp_mask->hdr.dgram_len ||
2781                                     udp_mask->hdr.dgram_cksum) {
2782                                         rte_flow_error_set(error, EINVAL,
2783                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2784                                                    item,
2785                                                    "Invalid UDP mask");
2786                                         return -rte_errno;
2787                                 }
2788
2789                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2790                                         input_set |= I40E_INSET_SRC_PORT;
2791                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2792                                         input_set |= I40E_INSET_DST_PORT;
2793
2794                                 /* Get filter info */
2795                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2796                                         filter->input.flow.udp4_flow.src_port =
2797                                                 udp_spec->hdr.src_port;
2798                                         filter->input.flow.udp4_flow.dst_port =
2799                                                 udp_spec->hdr.dst_port;
2800                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2801                                         filter->input.flow.udp6_flow.src_port =
2802                                                 udp_spec->hdr.src_port;
2803                                         filter->input.flow.udp6_flow.dst_port =
2804                                                 udp_spec->hdr.dst_port;
2805                                 }
2806                         }
2807
2808                         layer_idx = I40E_FLXPLD_L4_IDX;
2809
2810                         break;
2811                 case RTE_FLOW_ITEM_TYPE_GTPC:
2812                 case RTE_FLOW_ITEM_TYPE_GTPU:
2813                         if (!pf->gtp_support) {
2814                                 rte_flow_error_set(error, EINVAL,
2815                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2816                                                    item,
2817                                                    "Unsupported protocol");
2818                                 return -rte_errno;
2819                         }
2820
2821                         gtp_spec = item->spec;
2822                         gtp_mask = item->mask;
2823
2824                         if (gtp_spec && gtp_mask) {
2825                                 if (gtp_mask->v_pt_rsv_flags ||
2826                                     gtp_mask->msg_type ||
2827                                     gtp_mask->msg_len ||
2828                                     gtp_mask->teid != UINT32_MAX) {
2829                                         rte_flow_error_set(error, EINVAL,
2830                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2831                                                    item,
2832                                                    "Invalid GTP mask");
2833                                         return -rte_errno;
2834                                 }
2835
2836                                 filter->input.flow.gtp_flow.teid =
2837                                         gtp_spec->teid;
2838                                 filter->input.flow_ext.customized_pctype = true;
2839                                 cus_proto = item_type;
2840                         }
2841                         break;
2842                 case RTE_FLOW_ITEM_TYPE_SCTP:
2843                         sctp_spec = item->spec;
2844                         sctp_mask = item->mask;
2845
2846                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2847                                 pctype =
2848                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2849                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2850                                 pctype =
2851                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2852
2853                         if (sctp_spec && sctp_mask) {
2854                                 /* Check SCTP mask and update input set */
2855                                 if (sctp_mask->hdr.cksum) {
2856                                         rte_flow_error_set(error, EINVAL,
2857                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2858                                                    item,
2859                                                    "Invalid UDP mask");
2860                                         return -rte_errno;
2861                                 }
2862
2863                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2864                                         input_set |= I40E_INSET_SRC_PORT;
2865                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2866                                         input_set |= I40E_INSET_DST_PORT;
2867                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2868                                         input_set |= I40E_INSET_SCTP_VT;
2869
2870                                 /* Get filter info */
2871                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2872                                         filter->input.flow.sctp4_flow.src_port =
2873                                                 sctp_spec->hdr.src_port;
2874                                         filter->input.flow.sctp4_flow.dst_port =
2875                                                 sctp_spec->hdr.dst_port;
2876                                         filter->input.flow.sctp4_flow.verify_tag
2877                                                 = sctp_spec->hdr.tag;
2878                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2879                                         filter->input.flow.sctp6_flow.src_port =
2880                                                 sctp_spec->hdr.src_port;
2881                                         filter->input.flow.sctp6_flow.dst_port =
2882                                                 sctp_spec->hdr.dst_port;
2883                                         filter->input.flow.sctp6_flow.verify_tag
2884                                                 = sctp_spec->hdr.tag;
2885                                 }
2886                         }
2887
2888                         layer_idx = I40E_FLXPLD_L4_IDX;
2889
2890                         break;
2891                 case RTE_FLOW_ITEM_TYPE_RAW:
2892                         raw_spec = item->spec;
2893                         raw_mask = item->mask;
2894
2895                         if (!raw_spec || !raw_mask) {
2896                                 rte_flow_error_set(error, EINVAL,
2897                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2898                                                    item,
2899                                                    "NULL RAW spec/mask");
2900                                 return -rte_errno;
2901                         }
2902
2903                         if (pf->support_multi_driver) {
2904                                 rte_flow_error_set(error, ENOTSUP,
2905                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2906                                                    item,
2907                                                    "Unsupported flexible payload.");
2908                                 return -rte_errno;
2909                         }
2910
2911                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2912                         if (ret < 0)
2913                                 return ret;
2914
2915                         off_arr[raw_id] = raw_spec->offset;
2916                         len_arr[raw_id] = raw_spec->length;
2917
2918                         flex_size = 0;
2919                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2920                         flex_pit.size =
2921                                 raw_spec->length / sizeof(uint16_t);
2922                         flex_pit.dst_offset =
2923                                 next_dst_off / sizeof(uint16_t);
2924
2925                         for (i = 0; i <= raw_id; i++) {
2926                                 if (i == raw_id)
2927                                         flex_pit.src_offset +=
2928                                                 raw_spec->offset /
2929                                                 sizeof(uint16_t);
2930                                 else
2931                                         flex_pit.src_offset +=
2932                                                 (off_arr[i] + len_arr[i]) /
2933                                                 sizeof(uint16_t);
2934                                 flex_size += len_arr[i];
2935                         }
2936                         if (((flex_pit.src_offset + flex_pit.size) >=
2937                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2938                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2939                                 rte_flow_error_set(error, EINVAL,
2940                                            RTE_FLOW_ERROR_TYPE_ITEM,
2941                                            item,
2942                                            "Exceeds maxmial payload limit.");
2943                                 return -rte_errno;
2944                         }
2945
2946                         /* Store flex pit to SW */
2947                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2948                                                        layer_idx, raw_id);
2949                         if (ret < 0) {
2950                                 rte_flow_error_set(error, EINVAL,
2951                                    RTE_FLOW_ERROR_TYPE_ITEM,
2952                                    item,
2953                                    "Conflict with the first flexible rule.");
2954                                 return -rte_errno;
2955                         } else if (ret > 0)
2956                                 cfg_flex_pit = false;
2957
2958                         for (i = 0; i < raw_spec->length; i++) {
2959                                 j = i + next_dst_off;
2960                                 filter->input.flow_ext.flexbytes[j] =
2961                                         raw_spec->pattern[i];
2962                                 flex_mask[j] = raw_mask->pattern[i];
2963                         }
2964
2965                         next_dst_off += raw_spec->length;
2966                         raw_id++;
2967                         break;
2968                 case RTE_FLOW_ITEM_TYPE_VF:
2969                         vf_spec = item->spec;
2970                         if (!attr->transfer) {
2971                                 rte_flow_error_set(error, ENOTSUP,
2972                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2973                                                    item,
2974                                                    "Matching VF traffic"
2975                                                    " without affecting it"
2976                                                    " (transfer attribute)"
2977                                                    " is unsupported");
2978                                 return -rte_errno;
2979                         }
2980                         filter->input.flow_ext.is_vf = 1;
2981                         filter->input.flow_ext.dst_id = vf_spec->id;
2982                         if (filter->input.flow_ext.is_vf &&
2983                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2984                                 rte_flow_error_set(error, EINVAL,
2985                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2986                                                    item,
2987                                                    "Invalid VF ID for FDIR.");
2988                                 return -rte_errno;
2989                         }
2990                         break;
2991                 default:
2992                         break;
2993                 }
2994         }
2995
2996         /* Get customized pctype value */
2997         if (filter->input.flow_ext.customized_pctype) {
2998                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2999                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
3000                         rte_flow_error_set(error, EINVAL,
3001                                            RTE_FLOW_ERROR_TYPE_ITEM,
3002                                            item,
3003                                            "Unsupported pctype");
3004                         return -rte_errno;
3005                 }
3006         }
3007
3008         /* If customized pctype is not used, set fdir configuration.*/
3009         if (!filter->input.flow_ext.customized_pctype) {
3010                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3011                 if (ret == -1) {
3012                         rte_flow_error_set(error, EINVAL,
3013                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3014                                            "Conflict with the first rule's input set.");
3015                         return -rte_errno;
3016                 } else if (ret == -EINVAL) {
3017                         rte_flow_error_set(error, EINVAL,
3018                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3019                                            "Invalid pattern mask.");
3020                         return -rte_errno;
3021                 }
3022
3023                 /* Store flex mask to SW */
3024                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3025                 if (ret == -1) {
3026                         rte_flow_error_set(error, EINVAL,
3027                                            RTE_FLOW_ERROR_TYPE_ITEM,
3028                                            item,
3029                                            "Exceed maximal number of bitmasks");
3030                         return -rte_errno;
3031                 } else if (ret == -2) {
3032                         rte_flow_error_set(error, EINVAL,
3033                                            RTE_FLOW_ERROR_TYPE_ITEM,
3034                                            item,
3035                                            "Conflict with the first flexible rule");
3036                         return -rte_errno;
3037                 } else if (ret > 0)
3038                         cfg_flex_msk = false;
3039
3040                 if (cfg_flex_pit)
3041                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3042
3043                 if (cfg_flex_msk)
3044                         i40e_flow_set_fdir_flex_msk(pf, pctype);
3045         }
3046
3047         filter->input.pctype = pctype;
3048
3049         return 0;
3050 }
3051
3052 /* Parse to get the action info of a FDIR filter.
3053  * FDIR action supports QUEUE or (QUEUE + MARK).
3054  */
3055 static int
3056 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3057                             const struct rte_flow_action *actions,
3058                             struct rte_flow_error *error,
3059                             struct i40e_fdir_filter_conf *filter)
3060 {
3061         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3062         const struct rte_flow_action *act;
3063         const struct rte_flow_action_queue *act_q;
3064         const struct rte_flow_action_mark *mark_spec = NULL;
3065         uint32_t index = 0;
3066
3067         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3068         NEXT_ITEM_OF_ACTION(act, actions, index);
3069         switch (act->type) {
3070         case RTE_FLOW_ACTION_TYPE_QUEUE:
3071                 act_q = act->conf;
3072                 filter->action.rx_queue = act_q->index;
3073                 if ((!filter->input.flow_ext.is_vf &&
3074                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3075                     (filter->input.flow_ext.is_vf &&
3076                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3077                         rte_flow_error_set(error, EINVAL,
3078                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3079                                            "Invalid queue ID for FDIR.");
3080                         return -rte_errno;
3081                 }
3082                 filter->action.behavior = I40E_FDIR_ACCEPT;
3083                 break;
3084         case RTE_FLOW_ACTION_TYPE_DROP:
3085                 filter->action.behavior = I40E_FDIR_REJECT;
3086                 break;
3087         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3088                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3089                 break;
3090         case RTE_FLOW_ACTION_TYPE_MARK:
3091                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3092                 mark_spec = act->conf;
3093                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3094                 filter->soft_id = mark_spec->id;
3095         break;
3096         default:
3097                 rte_flow_error_set(error, EINVAL,
3098                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3099                                    "Invalid action.");
3100                 return -rte_errno;
3101         }
3102
3103         /* Check if the next non-void item is MARK or FLAG or END. */
3104         index++;
3105         NEXT_ITEM_OF_ACTION(act, actions, index);
3106         switch (act->type) {
3107         case RTE_FLOW_ACTION_TYPE_MARK:
3108                 if (!mark_spec) {
3109                         /* Double MARK actions requested */
3110                         rte_flow_error_set(error, EINVAL,
3111                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3112                            "Invalid action.");
3113                         return -rte_errno;
3114                 }
3115                 mark_spec = act->conf;
3116                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3117                 filter->soft_id = mark_spec->id;
3118                 break;
3119         case RTE_FLOW_ACTION_TYPE_FLAG:
3120                 if (!mark_spec) {
3121                         /* MARK + FLAG not supported */
3122                         rte_flow_error_set(error, EINVAL,
3123                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3124                                            "Invalid action.");
3125                         return -rte_errno;
3126                 }
3127                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3128                 break;
3129         case RTE_FLOW_ACTION_TYPE_RSS:
3130                 if (filter->action.behavior != I40E_FDIR_PASSTHRU) {
3131                         /* RSS filter won't be next if FDIR did not pass thru */
3132                         rte_flow_error_set(error, EINVAL,
3133                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3134                                            "Invalid action.");
3135                         return -rte_errno;
3136                 }
3137                 break;
3138         case RTE_FLOW_ACTION_TYPE_END:
3139                 return 0;
3140         default:
3141                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3142                                    act, "Invalid action.");
3143                 return -rte_errno;
3144         }
3145
3146         /* Check if the next non-void item is END */
3147         index++;
3148         NEXT_ITEM_OF_ACTION(act, actions, index);
3149         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3150                 rte_flow_error_set(error, EINVAL,
3151                                    RTE_FLOW_ERROR_TYPE_ACTION,
3152                                    act, "Invalid action.");
3153                 return -rte_errno;
3154         }
3155
3156         return 0;
3157 }
3158
3159 static int
3160 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3161                             const struct rte_flow_attr *attr,
3162                             const struct rte_flow_item pattern[],
3163                             const struct rte_flow_action actions[],
3164                             struct rte_flow_error *error,
3165                             union i40e_filter_t *filter)
3166 {
3167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3168         struct i40e_fdir_filter_conf *fdir_filter =
3169                 &filter->fdir_filter;
3170         int ret;
3171
3172         ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3173                                            fdir_filter);
3174         if (ret)
3175                 return ret;
3176
3177         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3178         if (ret)
3179                 return ret;
3180
3181         ret = i40e_flow_parse_attr(attr, error);
3182         if (ret)
3183                 return ret;
3184
3185         cons_filter_type = RTE_ETH_FILTER_FDIR;
3186
3187         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT ||
3188                 pf->fdir.fdir_vsi == NULL) {
3189                 /* Enable fdir when fdir flow is added at first time. */
3190                 ret = i40e_fdir_setup(pf);
3191                 if (ret != I40E_SUCCESS) {
3192                         rte_flow_error_set(error, ENOTSUP,
3193                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3194                                            NULL, "Failed to setup fdir.");
3195                         return -rte_errno;
3196                 }
3197                 ret = i40e_fdir_configure(dev);
3198                 if (ret < 0) {
3199                         rte_flow_error_set(error, ENOTSUP,
3200                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3201                                            NULL, "Failed to configure fdir.");
3202                         goto err;
3203                 }
3204
3205                 dev->data->dev_conf.fdir_conf.mode = RTE_FDIR_MODE_PERFECT;
3206         }
3207
3208         return 0;
3209 err:
3210         i40e_fdir_teardown(pf);
3211         return -rte_errno;
3212 }
3213
3214 /* Parse to get the action info of a tunnel filter
3215  * Tunnel action only supports PF, VF and QUEUE.
3216  */
3217 static int
3218 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3219                               const struct rte_flow_action *actions,
3220                               struct rte_flow_error *error,
3221                               struct i40e_tunnel_filter_conf *filter)
3222 {
3223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3224         const struct rte_flow_action *act;
3225         const struct rte_flow_action_queue *act_q;
3226         const struct rte_flow_action_vf *act_vf;
3227         uint32_t index = 0;
3228
3229         /* Check if the first non-void action is PF or VF. */
3230         NEXT_ITEM_OF_ACTION(act, actions, index);
3231         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3232             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3233                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3234                                    act, "Not supported action.");
3235                 return -rte_errno;
3236         }
3237
3238         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3239                 act_vf = act->conf;
3240                 filter->vf_id = act_vf->id;
3241                 filter->is_to_vf = 1;
3242                 if (filter->vf_id >= pf->vf_num) {
3243                         rte_flow_error_set(error, EINVAL,
3244                                    RTE_FLOW_ERROR_TYPE_ACTION,
3245                                    act, "Invalid VF ID for tunnel filter");
3246                         return -rte_errno;
3247                 }
3248         }
3249
3250         /* Check if the next non-void item is QUEUE */
3251         index++;
3252         NEXT_ITEM_OF_ACTION(act, actions, index);
3253         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3254                 act_q = act->conf;
3255                 filter->queue_id = act_q->index;
3256                 if ((!filter->is_to_vf) &&
3257                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3258                         rte_flow_error_set(error, EINVAL,
3259                                    RTE_FLOW_ERROR_TYPE_ACTION,
3260                                    act, "Invalid queue ID for tunnel filter");
3261                         return -rte_errno;
3262                 } else if (filter->is_to_vf &&
3263                            (filter->queue_id >= pf->vf_nb_qps)) {
3264                         rte_flow_error_set(error, EINVAL,
3265                                    RTE_FLOW_ERROR_TYPE_ACTION,
3266                                    act, "Invalid queue ID for tunnel filter");
3267                         return -rte_errno;
3268                 }
3269         }
3270
3271         /* Check if the next non-void item is END */
3272         index++;
3273         NEXT_ITEM_OF_ACTION(act, actions, index);
3274         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3275                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3276                                    act, "Not supported action.");
3277                 return -rte_errno;
3278         }
3279
3280         return 0;
3281 }
3282
3283 static uint16_t i40e_supported_tunnel_filter_types[] = {
3284         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3285         ETH_TUNNEL_FILTER_IVLAN,
3286         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3287         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3288         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3289         ETH_TUNNEL_FILTER_IMAC,
3290         ETH_TUNNEL_FILTER_IMAC,
3291 };
3292
3293 static int
3294 i40e_check_tunnel_filter_type(uint8_t filter_type)
3295 {
3296         uint8_t i;
3297
3298         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3299                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3300                         return 0;
3301         }
3302
3303         return -1;
3304 }
3305
3306 /* 1. Last in item should be NULL as range is not supported.
3307  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3308  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3309  * 3. Mask of fields which need to be matched should be
3310  *    filled with 1.
3311  * 4. Mask of fields which needn't to be matched should be
3312  *    filled with 0.
3313  */
3314 static int
3315 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3316                               const struct rte_flow_item *pattern,
3317                               struct rte_flow_error *error,
3318                               struct i40e_tunnel_filter_conf *filter)
3319 {
3320         const struct rte_flow_item *item = pattern;
3321         const struct rte_flow_item_eth *eth_spec;
3322         const struct rte_flow_item_eth *eth_mask;
3323         const struct rte_flow_item_vxlan *vxlan_spec;
3324         const struct rte_flow_item_vxlan *vxlan_mask;
3325         const struct rte_flow_item_vlan *vlan_spec;
3326         const struct rte_flow_item_vlan *vlan_mask;
3327         uint8_t filter_type = 0;
3328         bool is_vni_masked = 0;
3329         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3330         enum rte_flow_item_type item_type;
3331         bool vxlan_flag = 0;
3332         uint32_t tenant_id_be = 0;
3333         int ret;
3334
3335         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3336                 if (item->last) {
3337                         rte_flow_error_set(error, EINVAL,
3338                                            RTE_FLOW_ERROR_TYPE_ITEM,
3339                                            item,
3340                                            "Not support range");
3341                         return -rte_errno;
3342                 }
3343                 item_type = item->type;
3344                 switch (item_type) {
3345                 case RTE_FLOW_ITEM_TYPE_ETH:
3346                         eth_spec = item->spec;
3347                         eth_mask = item->mask;
3348
3349                         /* Check if ETH item is used for place holder.
3350                          * If yes, both spec and mask should be NULL.
3351                          * If no, both spec and mask shouldn't be NULL.
3352                          */
3353                         if ((!eth_spec && eth_mask) ||
3354                             (eth_spec && !eth_mask)) {
3355                                 rte_flow_error_set(error, EINVAL,
3356                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3357                                                    item,
3358                                                    "Invalid ether spec/mask");
3359                                 return -rte_errno;
3360                         }
3361
3362                         if (eth_spec && eth_mask) {
3363                                 /* DST address of inner MAC shouldn't be masked.
3364                                  * SRC address of Inner MAC should be masked.
3365                                  */
3366                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3367                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3368                                     eth_mask->type) {
3369                                         rte_flow_error_set(error, EINVAL,
3370                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3371                                                    item,
3372                                                    "Invalid ether spec/mask");
3373                                         return -rte_errno;
3374                                 }
3375
3376                                 if (!vxlan_flag) {
3377                                         rte_memcpy(&filter->outer_mac,
3378                                                    &eth_spec->dst,
3379                                                    RTE_ETHER_ADDR_LEN);
3380                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3381                                 } else {
3382                                         rte_memcpy(&filter->inner_mac,
3383                                                    &eth_spec->dst,
3384                                                    RTE_ETHER_ADDR_LEN);
3385                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3386                                 }
3387                         }
3388                         break;
3389                 case RTE_FLOW_ITEM_TYPE_VLAN:
3390                         vlan_spec = item->spec;
3391                         vlan_mask = item->mask;
3392                         if (!(vlan_spec && vlan_mask) ||
3393                             vlan_mask->inner_type) {
3394                                 rte_flow_error_set(error, EINVAL,
3395                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3396                                                    item,
3397                                                    "Invalid vlan item");
3398                                 return -rte_errno;
3399                         }
3400
3401                         if (vlan_spec && vlan_mask) {
3402                                 if (vlan_mask->tci ==
3403                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3404                                         filter->inner_vlan =
3405                                               rte_be_to_cpu_16(vlan_spec->tci) &
3406                                               I40E_TCI_MASK;
3407                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3408                         }
3409                         break;
3410                 case RTE_FLOW_ITEM_TYPE_IPV4:
3411                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3412                         /* IPv4 is used to describe protocol,
3413                          * spec and mask should be NULL.
3414                          */
3415                         if (item->spec || item->mask) {
3416                                 rte_flow_error_set(error, EINVAL,
3417                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3418                                                    item,
3419                                                    "Invalid IPv4 item");
3420                                 return -rte_errno;
3421                         }
3422                         break;
3423                 case RTE_FLOW_ITEM_TYPE_IPV6:
3424                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3425                         /* IPv6 is used to describe protocol,
3426                          * spec and mask should be NULL.
3427                          */
3428                         if (item->spec || item->mask) {
3429                                 rte_flow_error_set(error, EINVAL,
3430                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3431                                                    item,
3432                                                    "Invalid IPv6 item");
3433                                 return -rte_errno;
3434                         }
3435                         break;
3436                 case RTE_FLOW_ITEM_TYPE_UDP:
3437                         /* UDP is used to describe protocol,
3438                          * spec and mask should be NULL.
3439                          */
3440                         if (item->spec || item->mask) {
3441                                 rte_flow_error_set(error, EINVAL,
3442                                            RTE_FLOW_ERROR_TYPE_ITEM,
3443                                            item,
3444                                            "Invalid UDP item");
3445                                 return -rte_errno;
3446                         }
3447                         break;
3448                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3449                         vxlan_spec = item->spec;
3450                         vxlan_mask = item->mask;
3451                         /* Check if VXLAN item is used to describe protocol.
3452                          * If yes, both spec and mask should be NULL.
3453                          * If no, both spec and mask shouldn't be NULL.
3454                          */
3455                         if ((!vxlan_spec && vxlan_mask) ||
3456                             (vxlan_spec && !vxlan_mask)) {
3457                                 rte_flow_error_set(error, EINVAL,
3458                                            RTE_FLOW_ERROR_TYPE_ITEM,
3459                                            item,
3460                                            "Invalid VXLAN item");
3461                                 return -rte_errno;
3462                         }
3463
3464                         /* Check if VNI is masked. */
3465                         if (vxlan_spec && vxlan_mask) {
3466                                 is_vni_masked =
3467                                         !!memcmp(vxlan_mask->vni, vni_mask,
3468                                                  RTE_DIM(vni_mask));
3469                                 if (is_vni_masked) {
3470                                         rte_flow_error_set(error, EINVAL,
3471                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3472                                                    item,
3473                                                    "Invalid VNI mask");
3474                                         return -rte_errno;
3475                                 }
3476
3477                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3478                                            vxlan_spec->vni, 3);
3479                                 filter->tenant_id =
3480                                         rte_be_to_cpu_32(tenant_id_be);
3481                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3482                         }
3483
3484                         vxlan_flag = 1;
3485                         break;
3486                 default:
3487                         break;
3488                 }
3489         }
3490
3491         ret = i40e_check_tunnel_filter_type(filter_type);
3492         if (ret < 0) {
3493                 rte_flow_error_set(error, EINVAL,
3494                                    RTE_FLOW_ERROR_TYPE_ITEM,
3495                                    NULL,
3496                                    "Invalid filter type");
3497                 return -rte_errno;
3498         }
3499         filter->filter_type = filter_type;
3500
3501         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3502
3503         return 0;
3504 }
3505
3506 static int
3507 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3508                              const struct rte_flow_attr *attr,
3509                              const struct rte_flow_item pattern[],
3510                              const struct rte_flow_action actions[],
3511                              struct rte_flow_error *error,
3512                              union i40e_filter_t *filter)
3513 {
3514         struct i40e_tunnel_filter_conf *tunnel_filter =
3515                 &filter->consistent_tunnel_filter;
3516         int ret;
3517
3518         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3519                                             error, tunnel_filter);
3520         if (ret)
3521                 return ret;
3522
3523         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3524         if (ret)
3525                 return ret;
3526
3527         ret = i40e_flow_parse_attr(attr, error);
3528         if (ret)
3529                 return ret;
3530
3531         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3532
3533         return ret;
3534 }
3535
3536 /* 1. Last in item should be NULL as range is not supported.
3537  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3538  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3539  * 3. Mask of fields which need to be matched should be
3540  *    filled with 1.
3541  * 4. Mask of fields which needn't to be matched should be
3542  *    filled with 0.
3543  */
3544 static int
3545 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3546                               const struct rte_flow_item *pattern,
3547                               struct rte_flow_error *error,
3548                               struct i40e_tunnel_filter_conf *filter)
3549 {
3550         const struct rte_flow_item *item = pattern;
3551         const struct rte_flow_item_eth *eth_spec;
3552         const struct rte_flow_item_eth *eth_mask;
3553         const struct rte_flow_item_nvgre *nvgre_spec;
3554         const struct rte_flow_item_nvgre *nvgre_mask;
3555         const struct rte_flow_item_vlan *vlan_spec;
3556         const struct rte_flow_item_vlan *vlan_mask;
3557         enum rte_flow_item_type item_type;
3558         uint8_t filter_type = 0;
3559         bool is_tni_masked = 0;
3560         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3561         bool nvgre_flag = 0;
3562         uint32_t tenant_id_be = 0;
3563         int ret;
3564
3565         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3566                 if (item->last) {
3567                         rte_flow_error_set(error, EINVAL,
3568                                            RTE_FLOW_ERROR_TYPE_ITEM,
3569                                            item,
3570                                            "Not support range");
3571                         return -rte_errno;
3572                 }
3573                 item_type = item->type;
3574                 switch (item_type) {
3575                 case RTE_FLOW_ITEM_TYPE_ETH:
3576                         eth_spec = item->spec;
3577                         eth_mask = item->mask;
3578
3579                         /* Check if ETH item is used for place holder.
3580                          * If yes, both spec and mask should be NULL.
3581                          * If no, both spec and mask shouldn't be NULL.
3582                          */
3583                         if ((!eth_spec && eth_mask) ||
3584                             (eth_spec && !eth_mask)) {
3585                                 rte_flow_error_set(error, EINVAL,
3586                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3587                                                    item,
3588                                                    "Invalid ether spec/mask");
3589                                 return -rte_errno;
3590                         }
3591
3592                         if (eth_spec && eth_mask) {
3593                                 /* DST address of inner MAC shouldn't be masked.
3594                                  * SRC address of Inner MAC should be masked.
3595                                  */
3596                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3597                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3598                                     eth_mask->type) {
3599                                         rte_flow_error_set(error, EINVAL,
3600                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3601                                                    item,
3602                                                    "Invalid ether spec/mask");
3603                                         return -rte_errno;
3604                                 }
3605
3606                                 if (!nvgre_flag) {
3607                                         rte_memcpy(&filter->outer_mac,
3608                                                    &eth_spec->dst,
3609                                                    RTE_ETHER_ADDR_LEN);
3610                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3611                                 } else {
3612                                         rte_memcpy(&filter->inner_mac,
3613                                                    &eth_spec->dst,
3614                                                    RTE_ETHER_ADDR_LEN);
3615                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3616                                 }
3617                         }
3618
3619                         break;
3620                 case RTE_FLOW_ITEM_TYPE_VLAN:
3621                         vlan_spec = item->spec;
3622                         vlan_mask = item->mask;
3623                         if (!(vlan_spec && vlan_mask) ||
3624                             vlan_mask->inner_type) {
3625                                 rte_flow_error_set(error, EINVAL,
3626                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3627                                                    item,
3628                                                    "Invalid vlan item");
3629                                 return -rte_errno;
3630                         }
3631
3632                         if (vlan_spec && vlan_mask) {
3633                                 if (vlan_mask->tci ==
3634                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3635                                         filter->inner_vlan =
3636                                               rte_be_to_cpu_16(vlan_spec->tci) &
3637                                               I40E_TCI_MASK;
3638                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3639                         }
3640                         break;
3641                 case RTE_FLOW_ITEM_TYPE_IPV4:
3642                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3643                         /* IPv4 is used to describe protocol,
3644                          * spec and mask should be NULL.
3645                          */
3646                         if (item->spec || item->mask) {
3647                                 rte_flow_error_set(error, EINVAL,
3648                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3649                                                    item,
3650                                                    "Invalid IPv4 item");
3651                                 return -rte_errno;
3652                         }
3653                         break;
3654                 case RTE_FLOW_ITEM_TYPE_IPV6:
3655                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3656                         /* IPv6 is used to describe protocol,
3657                          * spec and mask should be NULL.
3658                          */
3659                         if (item->spec || item->mask) {
3660                                 rte_flow_error_set(error, EINVAL,
3661                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3662                                                    item,
3663                                                    "Invalid IPv6 item");
3664                                 return -rte_errno;
3665                         }
3666                         break;
3667                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3668                         nvgre_spec = item->spec;
3669                         nvgre_mask = item->mask;
3670                         /* Check if NVGRE item is used to describe protocol.
3671                          * If yes, both spec and mask should be NULL.
3672                          * If no, both spec and mask shouldn't be NULL.
3673                          */
3674                         if ((!nvgre_spec && nvgre_mask) ||
3675                             (nvgre_spec && !nvgre_mask)) {
3676                                 rte_flow_error_set(error, EINVAL,
3677                                            RTE_FLOW_ERROR_TYPE_ITEM,
3678                                            item,
3679                                            "Invalid NVGRE item");
3680                                 return -rte_errno;
3681                         }
3682
3683                         if (nvgre_spec && nvgre_mask) {
3684                                 is_tni_masked =
3685                                         !!memcmp(nvgre_mask->tni, tni_mask,
3686                                                  RTE_DIM(tni_mask));
3687                                 if (is_tni_masked) {
3688                                         rte_flow_error_set(error, EINVAL,
3689                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3690                                                        item,
3691                                                        "Invalid TNI mask");
3692                                         return -rte_errno;
3693                                 }
3694                                 if (nvgre_mask->protocol &&
3695                                         nvgre_mask->protocol != 0xFFFF) {
3696                                         rte_flow_error_set(error, EINVAL,
3697                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3698                                                 item,
3699                                                 "Invalid NVGRE item");
3700                                         return -rte_errno;
3701                                 }
3702                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3703                                         nvgre_mask->c_k_s_rsvd0_ver !=
3704                                         rte_cpu_to_be_16(0xFFFF)) {
3705                                         rte_flow_error_set(error, EINVAL,
3706                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3707                                                    item,
3708                                                    "Invalid NVGRE item");
3709                                         return -rte_errno;
3710                                 }
3711                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3712                                         rte_cpu_to_be_16(0x2000) &&
3713                                         nvgre_mask->c_k_s_rsvd0_ver) {
3714                                         rte_flow_error_set(error, EINVAL,
3715                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3716                                                    item,
3717                                                    "Invalid NVGRE item");
3718                                         return -rte_errno;
3719                                 }
3720                                 if (nvgre_mask->protocol &&
3721                                         nvgre_spec->protocol !=
3722                                         rte_cpu_to_be_16(0x6558)) {
3723                                         rte_flow_error_set(error, EINVAL,
3724                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3725                                                    item,
3726                                                    "Invalid NVGRE item");
3727                                         return -rte_errno;
3728                                 }
3729                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3730                                            nvgre_spec->tni, 3);
3731                                 filter->tenant_id =
3732                                         rte_be_to_cpu_32(tenant_id_be);
3733                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3734                         }
3735
3736                         nvgre_flag = 1;
3737                         break;
3738                 default:
3739                         break;
3740                 }
3741         }
3742
3743         ret = i40e_check_tunnel_filter_type(filter_type);
3744         if (ret < 0) {
3745                 rte_flow_error_set(error, EINVAL,
3746                                    RTE_FLOW_ERROR_TYPE_ITEM,
3747                                    NULL,
3748                                    "Invalid filter type");
3749                 return -rte_errno;
3750         }
3751         filter->filter_type = filter_type;
3752
3753         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3754
3755         return 0;
3756 }
3757
3758 static int
3759 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3760                              const struct rte_flow_attr *attr,
3761                              const struct rte_flow_item pattern[],
3762                              const struct rte_flow_action actions[],
3763                              struct rte_flow_error *error,
3764                              union i40e_filter_t *filter)
3765 {
3766         struct i40e_tunnel_filter_conf *tunnel_filter =
3767                 &filter->consistent_tunnel_filter;
3768         int ret;
3769
3770         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3771                                             error, tunnel_filter);
3772         if (ret)
3773                 return ret;
3774
3775         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3776         if (ret)
3777                 return ret;
3778
3779         ret = i40e_flow_parse_attr(attr, error);
3780         if (ret)
3781                 return ret;
3782
3783         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3784
3785         return ret;
3786 }
3787
3788 /* 1. Last in item should be NULL as range is not supported.
3789  * 2. Supported filter types: MPLS label.
3790  * 3. Mask of fields which need to be matched should be
3791  *    filled with 1.
3792  * 4. Mask of fields which needn't to be matched should be
3793  *    filled with 0.
3794  */
3795 static int
3796 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3797                              const struct rte_flow_item *pattern,
3798                              struct rte_flow_error *error,
3799                              struct i40e_tunnel_filter_conf *filter)
3800 {
3801         const struct rte_flow_item *item = pattern;
3802         const struct rte_flow_item_mpls *mpls_spec;
3803         const struct rte_flow_item_mpls *mpls_mask;
3804         enum rte_flow_item_type item_type;
3805         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3806         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3807         uint32_t label_be = 0;
3808
3809         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3810                 if (item->last) {
3811                         rte_flow_error_set(error, EINVAL,
3812                                            RTE_FLOW_ERROR_TYPE_ITEM,
3813                                            item,
3814                                            "Not support range");
3815                         return -rte_errno;
3816                 }
3817                 item_type = item->type;
3818                 switch (item_type) {
3819                 case RTE_FLOW_ITEM_TYPE_ETH:
3820                         if (item->spec || item->mask) {
3821                                 rte_flow_error_set(error, EINVAL,
3822                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3823                                                    item,
3824                                                    "Invalid ETH item");
3825                                 return -rte_errno;
3826                         }
3827                         break;
3828                 case RTE_FLOW_ITEM_TYPE_IPV4:
3829                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3830                         /* IPv4 is used to describe protocol,
3831                          * spec and mask should be NULL.
3832                          */
3833                         if (item->spec || item->mask) {
3834                                 rte_flow_error_set(error, EINVAL,
3835                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3836                                                    item,
3837                                                    "Invalid IPv4 item");
3838                                 return -rte_errno;
3839                         }
3840                         break;
3841                 case RTE_FLOW_ITEM_TYPE_IPV6:
3842                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3843                         /* IPv6 is used to describe protocol,
3844                          * spec and mask should be NULL.
3845                          */
3846                         if (item->spec || item->mask) {
3847                                 rte_flow_error_set(error, EINVAL,
3848                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3849                                                    item,
3850                                                    "Invalid IPv6 item");
3851                                 return -rte_errno;
3852                         }
3853                         break;
3854                 case RTE_FLOW_ITEM_TYPE_UDP:
3855                         /* UDP is used to describe protocol,
3856                          * spec and mask should be NULL.
3857                          */
3858                         if (item->spec || item->mask) {
3859                                 rte_flow_error_set(error, EINVAL,
3860                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3861                                                    item,
3862                                                    "Invalid UDP item");
3863                                 return -rte_errno;
3864                         }
3865                         is_mplsoudp = 1;
3866                         break;
3867                 case RTE_FLOW_ITEM_TYPE_GRE:
3868                         /* GRE is used to describe protocol,
3869                          * spec and mask should be NULL.
3870                          */
3871                         if (item->spec || item->mask) {
3872                                 rte_flow_error_set(error, EINVAL,
3873                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3874                                                    item,
3875                                                    "Invalid GRE item");
3876                                 return -rte_errno;
3877                         }
3878                         break;
3879                 case RTE_FLOW_ITEM_TYPE_MPLS:
3880                         mpls_spec = item->spec;
3881                         mpls_mask = item->mask;
3882
3883                         if (!mpls_spec || !mpls_mask) {
3884                                 rte_flow_error_set(error, EINVAL,
3885                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3886                                                    item,
3887                                                    "Invalid MPLS item");
3888                                 return -rte_errno;
3889                         }
3890
3891                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3892                                 rte_flow_error_set(error, EINVAL,
3893                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3894                                                    item,
3895                                                    "Invalid MPLS label mask");
3896                                 return -rte_errno;
3897                         }
3898                         rte_memcpy(((uint8_t *)&label_be + 1),
3899                                    mpls_spec->label_tc_s, 3);
3900                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3901                         break;
3902                 default:
3903                         break;
3904                 }
3905         }
3906
3907         if (is_mplsoudp)
3908                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3909         else
3910                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3911
3912         return 0;
3913 }
3914
3915 static int
3916 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3917                             const struct rte_flow_attr *attr,
3918                             const struct rte_flow_item pattern[],
3919                             const struct rte_flow_action actions[],
3920                             struct rte_flow_error *error,
3921                             union i40e_filter_t *filter)
3922 {
3923         struct i40e_tunnel_filter_conf *tunnel_filter =
3924                 &filter->consistent_tunnel_filter;
3925         int ret;
3926
3927         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3928                                            error, tunnel_filter);
3929         if (ret)
3930                 return ret;
3931
3932         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3933         if (ret)
3934                 return ret;
3935
3936         ret = i40e_flow_parse_attr(attr, error);
3937         if (ret)
3938                 return ret;
3939
3940         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3941
3942         return ret;
3943 }
3944
3945 /* 1. Last in item should be NULL as range is not supported.
3946  * 2. Supported filter types: GTP TEID.
3947  * 3. Mask of fields which need to be matched should be
3948  *    filled with 1.
3949  * 4. Mask of fields which needn't to be matched should be
3950  *    filled with 0.
3951  * 5. GTP profile supports GTPv1 only.
3952  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3953  */
3954 static int
3955 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3956                             const struct rte_flow_item *pattern,
3957                             struct rte_flow_error *error,
3958                             struct i40e_tunnel_filter_conf *filter)
3959 {
3960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3961         const struct rte_flow_item *item = pattern;
3962         const struct rte_flow_item_gtp *gtp_spec;
3963         const struct rte_flow_item_gtp *gtp_mask;
3964         enum rte_flow_item_type item_type;
3965
3966         if (!pf->gtp_support) {
3967                 rte_flow_error_set(error, EINVAL,
3968                                    RTE_FLOW_ERROR_TYPE_ITEM,
3969                                    item,
3970                                    "GTP is not supported by default.");
3971                 return -rte_errno;
3972         }
3973
3974         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3975                 if (item->last) {
3976                         rte_flow_error_set(error, EINVAL,
3977                                            RTE_FLOW_ERROR_TYPE_ITEM,
3978                                            item,
3979                                            "Not support range");
3980                         return -rte_errno;
3981                 }
3982                 item_type = item->type;
3983                 switch (item_type) {
3984                 case RTE_FLOW_ITEM_TYPE_ETH:
3985                         if (item->spec || item->mask) {
3986                                 rte_flow_error_set(error, EINVAL,
3987                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3988                                                    item,
3989                                                    "Invalid ETH item");
3990                                 return -rte_errno;
3991                         }
3992                         break;
3993                 case RTE_FLOW_ITEM_TYPE_IPV4:
3994                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3995                         /* IPv4 is used to describe protocol,
3996                          * spec and mask should be NULL.
3997                          */
3998                         if (item->spec || item->mask) {
3999                                 rte_flow_error_set(error, EINVAL,
4000                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4001                                                    item,
4002                                                    "Invalid IPv4 item");
4003                                 return -rte_errno;
4004                         }
4005                         break;
4006                 case RTE_FLOW_ITEM_TYPE_UDP:
4007                         if (item->spec || item->mask) {
4008                                 rte_flow_error_set(error, EINVAL,
4009                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4010                                                    item,
4011                                                    "Invalid UDP item");
4012                                 return -rte_errno;
4013                         }
4014                         break;
4015                 case RTE_FLOW_ITEM_TYPE_GTPC:
4016                 case RTE_FLOW_ITEM_TYPE_GTPU:
4017                         gtp_spec = item->spec;
4018                         gtp_mask = item->mask;
4019
4020                         if (!gtp_spec || !gtp_mask) {
4021                                 rte_flow_error_set(error, EINVAL,
4022                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4023                                                    item,
4024                                                    "Invalid GTP item");
4025                                 return -rte_errno;
4026                         }
4027
4028                         if (gtp_mask->v_pt_rsv_flags ||
4029                             gtp_mask->msg_type ||
4030                             gtp_mask->msg_len ||
4031                             gtp_mask->teid != UINT32_MAX) {
4032                                 rte_flow_error_set(error, EINVAL,
4033                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4034                                                    item,
4035                                                    "Invalid GTP mask");
4036                                 return -rte_errno;
4037                         }
4038
4039                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
4040                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
4041                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
4042                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
4043
4044                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4045
4046                         break;
4047                 default:
4048                         break;
4049                 }
4050         }
4051
4052         return 0;
4053 }
4054
4055 static int
4056 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4057                            const struct rte_flow_attr *attr,
4058                            const struct rte_flow_item pattern[],
4059                            const struct rte_flow_action actions[],
4060                            struct rte_flow_error *error,
4061                            union i40e_filter_t *filter)
4062 {
4063         struct i40e_tunnel_filter_conf *tunnel_filter =
4064                 &filter->consistent_tunnel_filter;
4065         int ret;
4066
4067         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4068                                           error, tunnel_filter);
4069         if (ret)
4070                 return ret;
4071
4072         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4073         if (ret)
4074                 return ret;
4075
4076         ret = i40e_flow_parse_attr(attr, error);
4077         if (ret)
4078                 return ret;
4079
4080         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4081
4082         return ret;
4083 }
4084
4085 /* 1. Last in item should be NULL as range is not supported.
4086  * 2. Supported filter types: QINQ.
4087  * 3. Mask of fields which need to be matched should be
4088  *    filled with 1.
4089  * 4. Mask of fields which needn't to be matched should be
4090  *    filled with 0.
4091  */
4092 static int
4093 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4094                               const struct rte_flow_item *pattern,
4095                               struct rte_flow_error *error,
4096                               struct i40e_tunnel_filter_conf *filter)
4097 {
4098         const struct rte_flow_item *item = pattern;
4099         const struct rte_flow_item_vlan *vlan_spec = NULL;
4100         const struct rte_flow_item_vlan *vlan_mask = NULL;
4101         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4102         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4103         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4104         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4105
4106         enum rte_flow_item_type item_type;
4107         bool vlan_flag = 0;
4108
4109         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4110                 if (item->last) {
4111                         rte_flow_error_set(error, EINVAL,
4112                                            RTE_FLOW_ERROR_TYPE_ITEM,
4113                                            item,
4114                                            "Not support range");
4115                         return -rte_errno;
4116                 }
4117                 item_type = item->type;
4118                 switch (item_type) {
4119                 case RTE_FLOW_ITEM_TYPE_ETH:
4120                         if (item->spec || item->mask) {
4121                                 rte_flow_error_set(error, EINVAL,
4122                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4123                                                    item,
4124                                                    "Invalid ETH item");
4125                                 return -rte_errno;
4126                         }
4127                         break;
4128                 case RTE_FLOW_ITEM_TYPE_VLAN:
4129                         vlan_spec = item->spec;
4130                         vlan_mask = item->mask;
4131
4132                         if (!(vlan_spec && vlan_mask) ||
4133                             vlan_mask->inner_type) {
4134                                 rte_flow_error_set(error, EINVAL,
4135                                            RTE_FLOW_ERROR_TYPE_ITEM,
4136                                            item,
4137                                            "Invalid vlan item");
4138                                 return -rte_errno;
4139                         }
4140
4141                         if (!vlan_flag) {
4142                                 o_vlan_spec = vlan_spec;
4143                                 o_vlan_mask = vlan_mask;
4144                                 vlan_flag = 1;
4145                         } else {
4146                                 i_vlan_spec = vlan_spec;
4147                                 i_vlan_mask = vlan_mask;
4148                                 vlan_flag = 0;
4149                         }
4150                         break;
4151
4152                 default:
4153                         break;
4154                 }
4155         }
4156
4157         /* Get filter specification */
4158         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4159                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4160                         (i_vlan_mask != NULL) &&
4161                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4162                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4163                         & I40E_TCI_MASK;
4164                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4165                         & I40E_TCI_MASK;
4166         } else {
4167                         rte_flow_error_set(error, EINVAL,
4168                                            RTE_FLOW_ERROR_TYPE_ITEM,
4169                                            NULL,
4170                                            "Invalid filter type");
4171                         return -rte_errno;
4172         }
4173
4174         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4175         return 0;
4176 }
4177
4178 static int
4179 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4180                               const struct rte_flow_attr *attr,
4181                               const struct rte_flow_item pattern[],
4182                               const struct rte_flow_action actions[],
4183                               struct rte_flow_error *error,
4184                               union i40e_filter_t *filter)
4185 {
4186         struct i40e_tunnel_filter_conf *tunnel_filter =
4187                 &filter->consistent_tunnel_filter;
4188         int ret;
4189
4190         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4191                                              error, tunnel_filter);
4192         if (ret)
4193                 return ret;
4194
4195         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4196         if (ret)
4197                 return ret;
4198
4199         ret = i40e_flow_parse_attr(attr, error);
4200         if (ret)
4201                 return ret;
4202
4203         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4204
4205         return ret;
4206 }
4207
4208 /**
4209  * This function is used to do configuration i40e existing RSS with rte_flow.
4210  * It also enable queue region configuration using flow API for i40e.
4211  * pattern can be used indicate what parameters will be include in flow,
4212  * like user_priority or flowtype for queue region or HASH function for RSS.
4213  * Action is used to transmit parameter like queue index and HASH
4214  * function for RSS, or flowtype for queue region configuration.
4215  * For example:
4216  * pattern:
4217  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4218  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4219  * Case 3: none, indicate RSS related will be parsed in action.
4220  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4221  * So, pattern choice is depened on the purpose of configuration of
4222  * that flow.
4223  * action:
4224  * action RSS will be uaed to transmit valid parameter with
4225  * struct rte_flow_action_rss for all the 3 case.
4226  */
4227 static int
4228 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4229                              const struct rte_flow_item *pattern,
4230                              struct rte_flow_error *error,
4231                              uint8_t *action_flag,
4232                              struct i40e_queue_regions *info)
4233 {
4234         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4235         const struct rte_flow_item *item = pattern;
4236         enum rte_flow_item_type item_type;
4237
4238         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4239                 return 0;
4240
4241         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4242                 if (item->last) {
4243                         rte_flow_error_set(error, EINVAL,
4244                                            RTE_FLOW_ERROR_TYPE_ITEM,
4245                                            item,
4246                                            "Not support range");
4247                         return -rte_errno;
4248                 }
4249                 item_type = item->type;
4250                 switch (item_type) {
4251                 case RTE_FLOW_ITEM_TYPE_ETH:
4252                         *action_flag = 1;
4253                         break;
4254                 case RTE_FLOW_ITEM_TYPE_VLAN:
4255                         vlan_spec = item->spec;
4256                         vlan_mask = item->mask;
4257                         if (vlan_spec && vlan_mask) {
4258                                 if (vlan_mask->tci ==
4259                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4260                                         info->region[0].user_priority[0] =
4261                                                 (rte_be_to_cpu_16(
4262                                                 vlan_spec->tci) >> 13) & 0x7;
4263                                         info->region[0].user_priority_num = 1;
4264                                         info->queue_region_number = 1;
4265                                         *action_flag = 0;
4266                                 }
4267                         }
4268                         break;
4269                 default:
4270                         rte_flow_error_set(error, EINVAL,
4271                                         RTE_FLOW_ERROR_TYPE_ITEM,
4272                                         item,
4273                                         "Not support range");
4274                         return -rte_errno;
4275                 }
4276         }
4277
4278         return 0;
4279 }
4280
4281 /**
4282  * This function is used to parse rss queue index, total queue number and
4283  * hash functions, If the purpose of this configuration is for queue region
4284  * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4285  * In queue region configuration, it also need to parse hardware flowtype
4286  * and user_priority from configuration, it will also cheeck the validity
4287  * of these parameters. For example, The queue region sizes should
4288  * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4289  * hw_flowtype or PCTYPE max index should be 63, the user priority
4290  * max index should be 7, and so on. And also, queue index should be
4291  * continuous sequence and queue region index should be part of rss
4292  * queue index for this port.
4293  */
4294 static int
4295 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4296                             const struct rte_flow_action *actions,
4297                             struct rte_flow_error *error,
4298                             uint8_t action_flag,
4299                             struct i40e_queue_regions *conf_info,
4300                             union i40e_filter_t *filter)
4301 {
4302         const struct rte_flow_action *act;
4303         const struct rte_flow_action_rss *rss;
4304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4305         struct i40e_queue_regions *info = &pf->queue_region;
4306         struct i40e_rte_flow_rss_conf *rss_config =
4307                         &filter->rss_conf;
4308         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4309         uint16_t i, j, n, tmp;
4310         uint32_t index = 0;
4311         uint64_t hf_bit = 1;
4312
4313         NEXT_ITEM_OF_ACTION(act, actions, index);
4314         rss = act->conf;
4315
4316         /**
4317          * rss only supports forwarding,
4318          * check if the first not void action is RSS.
4319          */
4320         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4321                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4322                 rte_flow_error_set(error, EINVAL,
4323                         RTE_FLOW_ERROR_TYPE_ACTION,
4324                         act, "Not supported action.");
4325                 return -rte_errno;
4326         }
4327
4328         if (action_flag) {
4329                 for (n = 0; n < 64; n++) {
4330                         if (rss->types & (hf_bit << n)) {
4331                                 conf_info->region[0].hw_flowtype[0] = n;
4332                                 conf_info->region[0].flowtype_num = 1;
4333                                 conf_info->queue_region_number = 1;
4334                                 break;
4335                         }
4336                 }
4337         }
4338
4339         /**
4340          * Do some queue region related parameters check
4341          * in order to keep queue index for queue region to be
4342          * continuous sequence and also to be part of RSS
4343          * queue index for this port.
4344          */
4345         if (conf_info->queue_region_number) {
4346                 for (i = 0; i < rss->queue_num; i++) {
4347                         for (j = 0; j < rss_info->conf.queue_num; j++) {
4348                                 if (rss->queue[i] == rss_info->conf.queue[j])
4349                                         break;
4350                         }
4351                         if (j == rss_info->conf.queue_num) {
4352                                 rte_flow_error_set(error, EINVAL,
4353                                         RTE_FLOW_ERROR_TYPE_ACTION,
4354                                         act,
4355                                         "no valid queues");
4356                                 return -rte_errno;
4357                         }
4358                 }
4359
4360                 for (i = 0; i < rss->queue_num - 1; i++) {
4361                         if (rss->queue[i + 1] != rss->queue[i] + 1) {
4362                                 rte_flow_error_set(error, EINVAL,
4363                                         RTE_FLOW_ERROR_TYPE_ACTION,
4364                                         act,
4365                                         "no valid queues");
4366                                 return -rte_errno;
4367                         }
4368                 }
4369         }
4370
4371         /* Parse queue region related parameters from configuration */
4372         for (n = 0; n < conf_info->queue_region_number; n++) {
4373                 if (conf_info->region[n].user_priority_num ||
4374                                 conf_info->region[n].flowtype_num) {
4375                         if (!((rte_is_power_of_2(rss->queue_num)) &&
4376                                         rss->queue_num <= 64)) {
4377                                 rte_flow_error_set(error, EINVAL,
4378                                         RTE_FLOW_ERROR_TYPE_ACTION,
4379                                         act,
4380                                         "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4381                                         "total number of queues do not exceed the VSI allocation");
4382                                 return -rte_errno;
4383                         }
4384
4385                         if (conf_info->region[n].user_priority[n] >=
4386                                         I40E_MAX_USER_PRIORITY) {
4387                                 rte_flow_error_set(error, EINVAL,
4388                                         RTE_FLOW_ERROR_TYPE_ACTION,
4389                                         act,
4390                                         "the user priority max index is 7");
4391                                 return -rte_errno;
4392                         }
4393
4394                         if (conf_info->region[n].hw_flowtype[n] >=
4395                                         I40E_FILTER_PCTYPE_MAX) {
4396                                 rte_flow_error_set(error, EINVAL,
4397                                         RTE_FLOW_ERROR_TYPE_ACTION,
4398                                         act,
4399                                         "the hw_flowtype or PCTYPE max index is 63");
4400                                 return -rte_errno;
4401                         }
4402
4403                         for (i = 0; i < info->queue_region_number; i++) {
4404                                 if (info->region[i].queue_num ==
4405                                     rss->queue_num &&
4406                                         info->region[i].queue_start_index ==
4407                                                 rss->queue[0])
4408                                         break;
4409                         }
4410
4411                         if (i == info->queue_region_number) {
4412                                 if (i > I40E_REGION_MAX_INDEX) {
4413                                         rte_flow_error_set(error, EINVAL,
4414                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4415                                                 act,
4416                                                 "the queue region max index is 7");
4417                                         return -rte_errno;
4418                                 }
4419
4420                                 info->region[i].queue_num =
4421                                         rss->queue_num;
4422                                 info->region[i].queue_start_index =
4423                                         rss->queue[0];
4424                                 info->region[i].region_id =
4425                                         info->queue_region_number;
4426
4427                                 j = info->region[i].user_priority_num;
4428                                 tmp = conf_info->region[n].user_priority[0];
4429                                 if (conf_info->region[n].user_priority_num) {
4430                                         info->region[i].user_priority[j] = tmp;
4431                                         info->region[i].user_priority_num++;
4432                                 }
4433
4434                                 j = info->region[i].flowtype_num;
4435                                 tmp = conf_info->region[n].hw_flowtype[0];
4436                                 if (conf_info->region[n].flowtype_num) {
4437                                         info->region[i].hw_flowtype[j] = tmp;
4438                                         info->region[i].flowtype_num++;
4439                                 }
4440                                 info->queue_region_number++;
4441                         } else {
4442                                 j = info->region[i].user_priority_num;
4443                                 tmp = conf_info->region[n].user_priority[0];
4444                                 if (conf_info->region[n].user_priority_num) {
4445                                         info->region[i].user_priority[j] = tmp;
4446                                         info->region[i].user_priority_num++;
4447                                 }
4448
4449                                 j = info->region[i].flowtype_num;
4450                                 tmp = conf_info->region[n].hw_flowtype[0];
4451                                 if (conf_info->region[n].flowtype_num) {
4452                                         info->region[i].hw_flowtype[j] = tmp;
4453                                         info->region[i].flowtype_num++;
4454                                 }
4455                         }
4456                 }
4457
4458                 rss_config->queue_region_conf = TRUE;
4459         }
4460
4461         /**
4462          * Return function if this flow is used for queue region configuration
4463          */
4464         if (rss_config->queue_region_conf)
4465                 return 0;
4466
4467         if (!rss || !rss->queue_num) {
4468                 rte_flow_error_set(error, EINVAL,
4469                                 RTE_FLOW_ERROR_TYPE_ACTION,
4470                                 act,
4471                                 "no valid queues");
4472                 return -rte_errno;
4473         }
4474
4475         for (n = 0; n < rss->queue_num; n++) {
4476                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4477                         rte_flow_error_set(error, EINVAL,
4478                                    RTE_FLOW_ERROR_TYPE_ACTION,
4479                                    act,
4480                                    "queue id > max number of queues");
4481                         return -rte_errno;
4482                 }
4483         }
4484
4485         if (rss_info->conf.queue_num) {
4486                 rte_flow_error_set(error, EINVAL,
4487                                 RTE_FLOW_ERROR_TYPE_ACTION,
4488                                 act,
4489                                 "rss only allow one valid rule");
4490                 return -rte_errno;
4491         }
4492
4493         /* Parse RSS related parameters from configuration */
4494         if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4495                 return rte_flow_error_set
4496                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4497                          "non-default RSS hash functions are not supported");
4498         if (rss->level)
4499                 return rte_flow_error_set
4500                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4501                          "a nonzero RSS encapsulation level is not supported");
4502         if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4503                 return rte_flow_error_set
4504                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4505                          "RSS hash key too large");
4506         if (rss->queue_num > RTE_DIM(rss_config->queue))
4507                 return rte_flow_error_set
4508                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4509                          "too many queues for RSS context");
4510         if (i40e_rss_conf_init(rss_config, rss))
4511                 return rte_flow_error_set
4512                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4513                          "RSS context initialization failure");
4514
4515         index++;
4516
4517         /* check if the next not void action is END */
4518         NEXT_ITEM_OF_ACTION(act, actions, index);
4519         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4520                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4521                 rte_flow_error_set(error, EINVAL,
4522                         RTE_FLOW_ERROR_TYPE_ACTION,
4523                         act, "Not supported action.");
4524                 return -rte_errno;
4525         }
4526         rss_config->queue_region_conf = FALSE;
4527
4528         return 0;
4529 }
4530
4531 static int
4532 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4533                         const struct rte_flow_attr *attr,
4534                         const struct rte_flow_item pattern[],
4535                         const struct rte_flow_action actions[],
4536                         union i40e_filter_t *filter,
4537                         struct rte_flow_error *error)
4538 {
4539         int ret;
4540         struct i40e_queue_regions info;
4541         uint8_t action_flag = 0;
4542
4543         memset(&info, 0, sizeof(struct i40e_queue_regions));
4544
4545         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4546                                         error, &action_flag, &info);
4547         if (ret)
4548                 return ret;
4549
4550         ret = i40e_flow_parse_rss_action(dev, actions, error,
4551                                         action_flag, &info, filter);
4552         if (ret)
4553                 return ret;
4554
4555         ret = i40e_flow_parse_attr(attr, error);
4556         if (ret)
4557                 return ret;
4558
4559         cons_filter_type = RTE_ETH_FILTER_HASH;
4560
4561         return 0;
4562 }
4563
4564 static int
4565 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4566                 struct i40e_rte_flow_rss_conf *conf)
4567 {
4568         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4570         int ret;
4571
4572         if (conf->queue_region_conf) {
4573                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4574                 conf->queue_region_conf = 0;
4575         } else {
4576                 ret = i40e_config_rss_filter(pf, conf, 1);
4577         }
4578         return ret;
4579 }
4580
4581 static int
4582 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4583                 struct i40e_rte_flow_rss_conf *conf)
4584 {
4585         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4586         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4587
4588         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4589
4590         i40e_config_rss_filter(pf, conf, 0);
4591         return 0;
4592 }
4593
4594 static int
4595 i40e_flow_validate(struct rte_eth_dev *dev,
4596                    const struct rte_flow_attr *attr,
4597                    const struct rte_flow_item pattern[],
4598                    const struct rte_flow_action actions[],
4599                    struct rte_flow_error *error)
4600 {
4601         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4602         parse_filter_t parse_filter;
4603         uint32_t item_num = 0; /* non-void item number of pattern*/
4604         uint32_t i = 0;
4605         bool flag = false;
4606         int ret = I40E_NOT_SUPPORTED;
4607
4608         if (!pattern) {
4609                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4610                                    NULL, "NULL pattern.");
4611                 return -rte_errno;
4612         }
4613
4614         if (!actions) {
4615                 rte_flow_error_set(error, EINVAL,
4616                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4617                                    NULL, "NULL action.");
4618                 return -rte_errno;
4619         }
4620
4621         if (!attr) {
4622                 rte_flow_error_set(error, EINVAL,
4623                                    RTE_FLOW_ERROR_TYPE_ATTR,
4624                                    NULL, "NULL attribute.");
4625                 return -rte_errno;
4626         }
4627
4628         memset(&cons_filter, 0, sizeof(cons_filter));
4629
4630         /* Get the non-void item of action */
4631         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4632                 i++;
4633
4634         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4635                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4636                                         actions, &cons_filter, error);
4637                 return ret;
4638         }
4639
4640         i = 0;
4641         /* Get the non-void item number of pattern */
4642         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4643                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4644                         item_num++;
4645                 i++;
4646         }
4647         item_num++;
4648
4649         items = rte_zmalloc("i40e_pattern",
4650                             item_num * sizeof(struct rte_flow_item), 0);
4651         if (!items) {
4652                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4653                                    NULL, "No memory for PMD internal items.");
4654                 return -ENOMEM;
4655         }
4656
4657         i40e_pattern_skip_void_item(items, pattern);
4658
4659         i = 0;
4660         do {
4661                 parse_filter = i40e_find_parse_filter_func(items, &i);
4662                 if (!parse_filter && !flag) {
4663                         rte_flow_error_set(error, EINVAL,
4664                                            RTE_FLOW_ERROR_TYPE_ITEM,
4665                                            pattern, "Unsupported pattern");
4666                         rte_free(items);
4667                         return -rte_errno;
4668                 }
4669                 if (parse_filter)
4670                         ret = parse_filter(dev, attr, items, actions,
4671                                            error, &cons_filter);
4672                 flag = true;
4673         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4674
4675         rte_free(items);
4676
4677         return ret;
4678 }
4679
4680 static struct rte_flow *
4681 i40e_flow_create(struct rte_eth_dev *dev,
4682                  const struct rte_flow_attr *attr,
4683                  const struct rte_flow_item pattern[],
4684                  const struct rte_flow_action actions[],
4685                  struct rte_flow_error *error)
4686 {
4687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4688         struct rte_flow *flow;
4689         int ret;
4690
4691         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4692         if (!flow) {
4693                 rte_flow_error_set(error, ENOMEM,
4694                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4695                                    "Failed to allocate memory");
4696                 return flow;
4697         }
4698
4699         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4700         if (ret < 0)
4701                 return NULL;
4702
4703         switch (cons_filter_type) {
4704         case RTE_ETH_FILTER_ETHERTYPE:
4705                 ret = i40e_ethertype_filter_set(pf,
4706                                         &cons_filter.ethertype_filter, 1);
4707                 if (ret)
4708                         goto free_flow;
4709                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4710                                         i40e_ethertype_filter_list);
4711                 break;
4712         case RTE_ETH_FILTER_FDIR:
4713                 ret = i40e_flow_add_del_fdir_filter(dev,
4714                                        &cons_filter.fdir_filter, 1);
4715                 if (ret)
4716                         goto free_flow;
4717                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4718                                         i40e_fdir_filter_list);
4719                 break;
4720         case RTE_ETH_FILTER_TUNNEL:
4721                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4722                             &cons_filter.consistent_tunnel_filter, 1);
4723                 if (ret)
4724                         goto free_flow;
4725                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4726                                         i40e_tunnel_filter_list);
4727                 break;
4728         case RTE_ETH_FILTER_HASH:
4729                 ret = i40e_config_rss_filter_set(dev,
4730                             &cons_filter.rss_conf);
4731                 if (ret)
4732                         goto free_flow;
4733                 flow->rule = &pf->rss_info;
4734                 break;
4735         default:
4736                 goto free_flow;
4737         }
4738
4739         flow->filter_type = cons_filter_type;
4740         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4741         return flow;
4742
4743 free_flow:
4744         rte_flow_error_set(error, -ret,
4745                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4746                            "Failed to create flow.");
4747         rte_free(flow);
4748         return NULL;
4749 }
4750
4751 static int
4752 i40e_flow_destroy(struct rte_eth_dev *dev,
4753                   struct rte_flow *flow,
4754                   struct rte_flow_error *error)
4755 {
4756         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4757         enum rte_filter_type filter_type = flow->filter_type;
4758         int ret = 0;
4759
4760         switch (filter_type) {
4761         case RTE_ETH_FILTER_ETHERTYPE:
4762                 ret = i40e_flow_destroy_ethertype_filter(pf,
4763                          (struct i40e_ethertype_filter *)flow->rule);
4764                 break;
4765         case RTE_ETH_FILTER_TUNNEL:
4766                 ret = i40e_flow_destroy_tunnel_filter(pf,
4767                               (struct i40e_tunnel_filter *)flow->rule);
4768                 break;
4769         case RTE_ETH_FILTER_FDIR:
4770                 ret = i40e_flow_add_del_fdir_filter(dev,
4771                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4772
4773                 /* If the last flow is destroyed, disable fdir. */
4774                 if (!ret && !TAILQ_EMPTY(&pf->fdir.fdir_list)) {
4775                         i40e_fdir_teardown(pf);
4776                         dev->data->dev_conf.fdir_conf.mode =
4777                                    RTE_FDIR_MODE_NONE;
4778                 }
4779                 break;
4780         case RTE_ETH_FILTER_HASH:
4781                 ret = i40e_config_rss_filter_del(dev,
4782                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4783                 break;
4784         default:
4785                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4786                             filter_type);
4787                 ret = -EINVAL;
4788                 break;
4789         }
4790
4791         if (!ret) {
4792                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4793                 rte_free(flow);
4794         } else
4795                 rte_flow_error_set(error, -ret,
4796                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4797                                    "Failed to destroy flow.");
4798
4799         return ret;
4800 }
4801
4802 static int
4803 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4804                                    struct i40e_ethertype_filter *filter)
4805 {
4806         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4807         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4808         struct i40e_ethertype_filter *node;
4809         struct i40e_control_filter_stats stats;
4810         uint16_t flags = 0;
4811         int ret = 0;
4812
4813         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4814                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4815         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4816                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4817         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4818
4819         memset(&stats, 0, sizeof(stats));
4820         ret = i40e_aq_add_rem_control_packet_filter(hw,
4821                                     filter->input.mac_addr.addr_bytes,
4822                                     filter->input.ether_type,
4823                                     flags, pf->main_vsi->seid,
4824                                     filter->queue, 0, &stats, NULL);
4825         if (ret < 0)
4826                 return ret;
4827
4828         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4829         if (!node)
4830                 return -EINVAL;
4831
4832         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4833
4834         return ret;
4835 }
4836
4837 static int
4838 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4839                                 struct i40e_tunnel_filter *filter)
4840 {
4841         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4842         struct i40e_vsi *vsi;
4843         struct i40e_pf_vf *vf;
4844         struct i40e_aqc_cloud_filters_element_bb cld_filter;
4845         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4846         struct i40e_tunnel_filter *node;
4847         bool big_buffer = 0;
4848         int ret = 0;
4849
4850         memset(&cld_filter, 0, sizeof(cld_filter));
4851         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac,
4852                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
4853         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac,
4854                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
4855         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4856         cld_filter.element.flags = filter->input.flags;
4857         cld_filter.element.tenant_id = filter->input.tenant_id;
4858         cld_filter.element.queue_number = filter->queue;
4859         rte_memcpy(cld_filter.general_fields,
4860                    filter->input.general_fields,
4861                    sizeof(cld_filter.general_fields));
4862
4863         if (!filter->is_to_vf)
4864                 vsi = pf->main_vsi;
4865         else {
4866                 vf = &pf->vfs[filter->vf_id];
4867                 vsi = vf->vsi;
4868         }
4869
4870         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4871             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4872             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4873             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4874             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4875             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4876                 big_buffer = 1;
4877
4878         if (big_buffer)
4879                 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid,
4880                                                 &cld_filter, 1);
4881         else
4882                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
4883                                                 &cld_filter.element, 1);
4884         if (ret < 0)
4885                 return -ENOTSUP;
4886
4887         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4888         if (!node)
4889                 return -EINVAL;
4890
4891         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4892
4893         return ret;
4894 }
4895
4896 static int
4897 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4898 {
4899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4900         int ret;
4901
4902         ret = i40e_flow_flush_fdir_filter(pf);
4903         if (ret) {
4904                 rte_flow_error_set(error, -ret,
4905                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4906                                    "Failed to flush FDIR flows.");
4907                 return -rte_errno;
4908         }
4909
4910         ret = i40e_flow_flush_ethertype_filter(pf);
4911         if (ret) {
4912                 rte_flow_error_set(error, -ret,
4913                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4914                                    "Failed to ethertype flush flows.");
4915                 return -rte_errno;
4916         }
4917
4918         ret = i40e_flow_flush_tunnel_filter(pf);
4919         if (ret) {
4920                 rte_flow_error_set(error, -ret,
4921                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4922                                    "Failed to flush tunnel flows.");
4923                 return -rte_errno;
4924         }
4925
4926         ret = i40e_flow_flush_rss_filter(dev);
4927         if (ret) {
4928                 rte_flow_error_set(error, -ret,
4929                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4930                                    "Failed to flush rss flows.");
4931                 return -rte_errno;
4932         }
4933
4934         return ret;
4935 }
4936
4937 static int
4938 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4939 {
4940         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4941         struct i40e_fdir_info *fdir_info = &pf->fdir;
4942         struct i40e_fdir_filter *fdir_filter;
4943         enum i40e_filter_pctype pctype;
4944         struct rte_flow *flow;
4945         void *temp;
4946         int ret;
4947
4948         ret = i40e_fdir_flush(dev);
4949         if (!ret) {
4950                 /* Delete FDIR filters in FDIR list. */
4951                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4952                         ret = i40e_sw_fdir_filter_del(pf,
4953                                                       &fdir_filter->fdir.input);
4954                         if (ret < 0)
4955                                 return ret;
4956                 }
4957
4958                 /* Delete FDIR flows in flow list. */
4959                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4960                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4961                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4962                                 rte_free(flow);
4963                         }
4964                 }
4965
4966                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4967                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4968                         pf->fdir.inset_flag[pctype] = 0;
4969         }
4970
4971         i40e_fdir_teardown(pf);
4972
4973         return ret;
4974 }
4975
4976 /* Flush all ethertype filters */
4977 static int
4978 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4979 {
4980         struct i40e_ethertype_filter_list
4981                 *ethertype_list = &pf->ethertype.ethertype_list;
4982         struct i40e_ethertype_filter *filter;
4983         struct rte_flow *flow;
4984         void *temp;
4985         int ret = 0;
4986
4987         while ((filter = TAILQ_FIRST(ethertype_list))) {
4988                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4989                 if (ret)
4990                         return ret;
4991         }
4992
4993         /* Delete ethertype flows in flow list. */
4994         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4995                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4996                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4997                         rte_free(flow);
4998                 }
4999         }
5000
5001         return ret;
5002 }
5003
5004 /* Flush all tunnel filters */
5005 static int
5006 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
5007 {
5008         struct i40e_tunnel_filter_list
5009                 *tunnel_list = &pf->tunnel.tunnel_list;
5010         struct i40e_tunnel_filter *filter;
5011         struct rte_flow *flow;
5012         void *temp;
5013         int ret = 0;
5014
5015         while ((filter = TAILQ_FIRST(tunnel_list))) {
5016                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
5017                 if (ret)
5018                         return ret;
5019         }
5020
5021         /* Delete tunnel flows in flow list. */
5022         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5023                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
5024                         TAILQ_REMOVE(&pf->flow_list, flow, node);
5025                         rte_free(flow);
5026                 }
5027         }
5028
5029         return ret;
5030 }
5031
5032 /* remove the rss filter */
5033 static int
5034 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
5035 {
5036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5037         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
5038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039         int32_t ret = -EINVAL;
5040
5041         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5042
5043         if (rss_info->conf.queue_num)
5044                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
5045         return ret;
5046 }