drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_debug.h>
  14 #include <rte_ether.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_log.h>
  17 #include <rte_malloc.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20
  21 #include "i40e_logs.h"
  22 #include "base/i40e_type.h"
  23 #include "base/i40e_prototype.h"
  24 #include "i40e_ethdev.h"
  25
  26 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  27 #define I40E_IPV6_FRAG_HEADER   44
  28 #define I40E_TENANT_ARRAY_NUM   3
  29 #define I40E_TCI_MASK           0xFFFF
  30
  31 static int i40e_flow_validate(struct rte_eth_dev *dev,
  32                               const struct rte_flow_attr *attr,
  33                               const struct rte_flow_item pattern[],
  34                               const struct rte_flow_action actions[],
  35                               struct rte_flow_error *error);
  36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  37                                          const struct rte_flow_attr *attr,
  38                                          const struct rte_flow_item pattern[],
  39                                          const struct rte_flow_action actions[],
  40                                          struct rte_flow_error *error);
  41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  42                              struct rte_flow *flow,
  43                              struct rte_flow_error *error);
  44 static int i40e_flow_flush(struct rte_eth_dev *dev,
  45                            struct rte_flow_error *error);
  46 static int
  47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  48                                   const struct rte_flow_item *pattern,
  49                                   struct rte_flow_error *error,
  50                                   struct rte_eth_ethertype_filter *filter);
  51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  52                                     const struct rte_flow_action *actions,
  53                                     struct rte_flow_error *error,
  54                                     struct rte_eth_ethertype_filter *filter);
  55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  56                                         const struct rte_flow_attr *attr,
  57                                         const struct rte_flow_item *pattern,
  58                                         struct rte_flow_error *error,
  59                                         struct i40e_fdir_filter_conf *filter);
  60 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  61                                        const struct rte_flow_action *actions,
  62                                        struct rte_flow_error *error,
  63                                        struct i40e_fdir_filter_conf *filter);
  64 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  65                                  const struct rte_flow_action *actions,
  66                                  struct rte_flow_error *error,
  67                                  struct i40e_tunnel_filter_conf *filter);
  68 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  69                                 struct rte_flow_error *error);
  70 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  71                                     const struct rte_flow_attr *attr,
  72                                     const struct rte_flow_item pattern[],
  73                                     const struct rte_flow_action actions[],
  74                                     struct rte_flow_error *error,
  75                                     union i40e_filter_t *filter);
  76 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  77                                        const struct rte_flow_attr *attr,
  78                                        const struct rte_flow_item pattern[],
  79                                        const struct rte_flow_action actions[],
  80                                        struct rte_flow_error *error,
  81                                        union i40e_filter_t *filter);
  82 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  83                                         const struct rte_flow_attr *attr,
  84                                         const struct rte_flow_item pattern[],
  85                                         const struct rte_flow_action actions[],
  86                                         struct rte_flow_error *error,
  87                                         union i40e_filter_t *filter);
  88 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  89                                         const struct rte_flow_attr *attr,
  90                                         const struct rte_flow_item pattern[],
  91                                         const struct rte_flow_action actions[],
  92                                         struct rte_flow_error *error,
  93                                         union i40e_filter_t *filter);
  94 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  95                                        const struct rte_flow_attr *attr,
  96                                        const struct rte_flow_item pattern[],
  97                                        const struct rte_flow_action actions[],
  98                                        struct rte_flow_error *error,
  99                                        union i40e_filter_t *filter);
 100 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 101                                       const struct rte_flow_attr *attr,
 102                                       const struct rte_flow_item pattern[],
 103                                       const struct rte_flow_action actions[],
 104                                       struct rte_flow_error *error,
 105                                       union i40e_filter_t *filter);
 106 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 107                                       struct i40e_ethertype_filter *filter);
 108 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 109                                            struct i40e_tunnel_filter *filter);
 110 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 112 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 113 static int
 114 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 115 static int
 116 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 117                               const struct rte_flow_attr *attr,
 118                               const struct rte_flow_item pattern[],
 119                               const struct rte_flow_action actions[],
 120                               struct rte_flow_error *error,
 121                               union i40e_filter_t *filter);
 122 static int
 123 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 124                               const struct rte_flow_item *pattern,
 125                               struct rte_flow_error *error,
 126                               struct i40e_tunnel_filter_conf *filter);
 127
 128 const struct rte_flow_ops i40e_flow_ops = {
 129         .validate = i40e_flow_validate,
 130         .create = i40e_flow_create,
 131         .destroy = i40e_flow_destroy,
 132         .flush = i40e_flow_flush,
 133 };
 134
 135 static union i40e_filter_t cons_filter;
 136 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 137
 138 /* Pattern matched ethertype filter */
 139 static enum rte_flow_item_type pattern_ethertype[] = {
 140         RTE_FLOW_ITEM_TYPE_ETH,
 141         RTE_FLOW_ITEM_TYPE_END,
 142 };
 143
 144 /* Pattern matched flow director filter */
 145 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 146         RTE_FLOW_ITEM_TYPE_ETH,
 147         RTE_FLOW_ITEM_TYPE_IPV4,
 148         RTE_FLOW_ITEM_TYPE_END,
 149 };
 150
 151 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 152         RTE_FLOW_ITEM_TYPE_ETH,
 153         RTE_FLOW_ITEM_TYPE_IPV4,
 154         RTE_FLOW_ITEM_TYPE_UDP,
 155         RTE_FLOW_ITEM_TYPE_END,
 156 };
 157
 158 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 159         RTE_FLOW_ITEM_TYPE_ETH,
 160         RTE_FLOW_ITEM_TYPE_IPV4,
 161         RTE_FLOW_ITEM_TYPE_TCP,
 162         RTE_FLOW_ITEM_TYPE_END,
 163 };
 164
 165 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 166         RTE_FLOW_ITEM_TYPE_ETH,
 167         RTE_FLOW_ITEM_TYPE_IPV4,
 168         RTE_FLOW_ITEM_TYPE_SCTP,
 169         RTE_FLOW_ITEM_TYPE_END,
 170 };
 171
 172 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 173         RTE_FLOW_ITEM_TYPE_ETH,
 174         RTE_FLOW_ITEM_TYPE_IPV4,
 175         RTE_FLOW_ITEM_TYPE_UDP,
 176         RTE_FLOW_ITEM_TYPE_GTPC,
 177         RTE_FLOW_ITEM_TYPE_END,
 178 };
 179
 180 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 181         RTE_FLOW_ITEM_TYPE_ETH,
 182         RTE_FLOW_ITEM_TYPE_IPV4,
 183         RTE_FLOW_ITEM_TYPE_UDP,
 184         RTE_FLOW_ITEM_TYPE_GTPU,
 185         RTE_FLOW_ITEM_TYPE_END,
 186 };
 187
 188 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 189         RTE_FLOW_ITEM_TYPE_ETH,
 190         RTE_FLOW_ITEM_TYPE_IPV4,
 191         RTE_FLOW_ITEM_TYPE_UDP,
 192         RTE_FLOW_ITEM_TYPE_GTPU,
 193         RTE_FLOW_ITEM_TYPE_IPV4,
 194         RTE_FLOW_ITEM_TYPE_END,
 195 };
 196
 197 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 198         RTE_FLOW_ITEM_TYPE_ETH,
 199         RTE_FLOW_ITEM_TYPE_IPV4,
 200         RTE_FLOW_ITEM_TYPE_UDP,
 201         RTE_FLOW_ITEM_TYPE_GTPU,
 202         RTE_FLOW_ITEM_TYPE_IPV6,
 203         RTE_FLOW_ITEM_TYPE_END,
 204 };
 205
 206 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 207         RTE_FLOW_ITEM_TYPE_ETH,
 208         RTE_FLOW_ITEM_TYPE_IPV6,
 209         RTE_FLOW_ITEM_TYPE_END,
 210 };
 211
 212 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 213         RTE_FLOW_ITEM_TYPE_ETH,
 214         RTE_FLOW_ITEM_TYPE_IPV6,
 215         RTE_FLOW_ITEM_TYPE_UDP,
 216         RTE_FLOW_ITEM_TYPE_END,
 217 };
 218
 219 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 220         RTE_FLOW_ITEM_TYPE_ETH,
 221         RTE_FLOW_ITEM_TYPE_IPV6,
 222         RTE_FLOW_ITEM_TYPE_TCP,
 223         RTE_FLOW_ITEM_TYPE_END,
 224 };
 225
 226 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 227         RTE_FLOW_ITEM_TYPE_ETH,
 228         RTE_FLOW_ITEM_TYPE_IPV6,
 229         RTE_FLOW_ITEM_TYPE_SCTP,
 230         RTE_FLOW_ITEM_TYPE_END,
 231 };
 232
 233 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 234         RTE_FLOW_ITEM_TYPE_ETH,
 235         RTE_FLOW_ITEM_TYPE_IPV6,
 236         RTE_FLOW_ITEM_TYPE_UDP,
 237         RTE_FLOW_ITEM_TYPE_GTPC,
 238         RTE_FLOW_ITEM_TYPE_END,
 239 };
 240
 241 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 242         RTE_FLOW_ITEM_TYPE_ETH,
 243         RTE_FLOW_ITEM_TYPE_IPV6,
 244         RTE_FLOW_ITEM_TYPE_UDP,
 245         RTE_FLOW_ITEM_TYPE_GTPU,
 246         RTE_FLOW_ITEM_TYPE_END,
 247 };
 248
 249 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 250         RTE_FLOW_ITEM_TYPE_ETH,
 251         RTE_FLOW_ITEM_TYPE_IPV6,
 252         RTE_FLOW_ITEM_TYPE_UDP,
 253         RTE_FLOW_ITEM_TYPE_GTPU,
 254         RTE_FLOW_ITEM_TYPE_IPV4,
 255         RTE_FLOW_ITEM_TYPE_END,
 256 };
 257
 258 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 259         RTE_FLOW_ITEM_TYPE_ETH,
 260         RTE_FLOW_ITEM_TYPE_IPV6,
 261         RTE_FLOW_ITEM_TYPE_UDP,
 262         RTE_FLOW_ITEM_TYPE_GTPU,
 263         RTE_FLOW_ITEM_TYPE_IPV6,
 264         RTE_FLOW_ITEM_TYPE_END,
 265 };
 266
 267 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 268         RTE_FLOW_ITEM_TYPE_ETH,
 269         RTE_FLOW_ITEM_TYPE_RAW,
 270         RTE_FLOW_ITEM_TYPE_END,
 271 };
 272
 273 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 274         RTE_FLOW_ITEM_TYPE_ETH,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_RAW,
 277         RTE_FLOW_ITEM_TYPE_END,
 278 };
 279
 280 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 281         RTE_FLOW_ITEM_TYPE_ETH,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_RAW,
 285         RTE_FLOW_ITEM_TYPE_END,
 286 };
 287
 288 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 289         RTE_FLOW_ITEM_TYPE_ETH,
 290         RTE_FLOW_ITEM_TYPE_IPV4,
 291         RTE_FLOW_ITEM_TYPE_RAW,
 292         RTE_FLOW_ITEM_TYPE_END,
 293 };
 294
 295 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 296         RTE_FLOW_ITEM_TYPE_ETH,
 297         RTE_FLOW_ITEM_TYPE_IPV4,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_RAW,
 300         RTE_FLOW_ITEM_TYPE_END,
 301 };
 302
 303 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 304         RTE_FLOW_ITEM_TYPE_ETH,
 305         RTE_FLOW_ITEM_TYPE_IPV4,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_RAW,
 309         RTE_FLOW_ITEM_TYPE_END,
 310 };
 311
 312 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 313         RTE_FLOW_ITEM_TYPE_ETH,
 314         RTE_FLOW_ITEM_TYPE_IPV4,
 315         RTE_FLOW_ITEM_TYPE_UDP,
 316         RTE_FLOW_ITEM_TYPE_RAW,
 317         RTE_FLOW_ITEM_TYPE_END,
 318 };
 319
 320 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 321         RTE_FLOW_ITEM_TYPE_ETH,
 322         RTE_FLOW_ITEM_TYPE_IPV4,
 323         RTE_FLOW_ITEM_TYPE_UDP,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_RAW,
 326         RTE_FLOW_ITEM_TYPE_END,
 327 };
 328
 329 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 330         RTE_FLOW_ITEM_TYPE_ETH,
 331         RTE_FLOW_ITEM_TYPE_IPV4,
 332         RTE_FLOW_ITEM_TYPE_UDP,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_RAW,
 336         RTE_FLOW_ITEM_TYPE_END,
 337 };
 338
 339 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 340         RTE_FLOW_ITEM_TYPE_ETH,
 341         RTE_FLOW_ITEM_TYPE_IPV4,
 342         RTE_FLOW_ITEM_TYPE_TCP,
 343         RTE_FLOW_ITEM_TYPE_RAW,
 344         RTE_FLOW_ITEM_TYPE_END,
 345 };
 346
 347 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 348         RTE_FLOW_ITEM_TYPE_ETH,
 349         RTE_FLOW_ITEM_TYPE_IPV4,
 350         RTE_FLOW_ITEM_TYPE_TCP,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_RAW,
 353         RTE_FLOW_ITEM_TYPE_END,
 354 };
 355
 356 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 357         RTE_FLOW_ITEM_TYPE_ETH,
 358         RTE_FLOW_ITEM_TYPE_IPV4,
 359         RTE_FLOW_ITEM_TYPE_TCP,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_RAW,
 363         RTE_FLOW_ITEM_TYPE_END,
 364 };
 365
 366 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 367         RTE_FLOW_ITEM_TYPE_ETH,
 368         RTE_FLOW_ITEM_TYPE_IPV4,
 369         RTE_FLOW_ITEM_TYPE_SCTP,
 370         RTE_FLOW_ITEM_TYPE_RAW,
 371         RTE_FLOW_ITEM_TYPE_END,
 372 };
 373
 374 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 375         RTE_FLOW_ITEM_TYPE_ETH,
 376         RTE_FLOW_ITEM_TYPE_IPV4,
 377         RTE_FLOW_ITEM_TYPE_SCTP,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_RAW,
 380         RTE_FLOW_ITEM_TYPE_END,
 381 };
 382
 383 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 384         RTE_FLOW_ITEM_TYPE_ETH,
 385         RTE_FLOW_ITEM_TYPE_IPV4,
 386         RTE_FLOW_ITEM_TYPE_SCTP,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_RAW,
 390         RTE_FLOW_ITEM_TYPE_END,
 391 };
 392
 393 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 394         RTE_FLOW_ITEM_TYPE_ETH,
 395         RTE_FLOW_ITEM_TYPE_IPV6,
 396         RTE_FLOW_ITEM_TYPE_RAW,
 397         RTE_FLOW_ITEM_TYPE_END,
 398 };
 399
 400 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 401         RTE_FLOW_ITEM_TYPE_ETH,
 402         RTE_FLOW_ITEM_TYPE_IPV6,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_RAW,
 405         RTE_FLOW_ITEM_TYPE_END,
 406 };
 407
 408 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 409         RTE_FLOW_ITEM_TYPE_ETH,
 410         RTE_FLOW_ITEM_TYPE_IPV6,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_RAW,
 414         RTE_FLOW_ITEM_TYPE_END,
 415 };
 416
 417 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 418         RTE_FLOW_ITEM_TYPE_ETH,
 419         RTE_FLOW_ITEM_TYPE_IPV6,
 420         RTE_FLOW_ITEM_TYPE_UDP,
 421         RTE_FLOW_ITEM_TYPE_RAW,
 422         RTE_FLOW_ITEM_TYPE_END,
 423 };
 424
 425 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 426         RTE_FLOW_ITEM_TYPE_ETH,
 427         RTE_FLOW_ITEM_TYPE_IPV6,
 428         RTE_FLOW_ITEM_TYPE_UDP,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_RAW,
 431         RTE_FLOW_ITEM_TYPE_END,
 432 };
 433
 434 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 435         RTE_FLOW_ITEM_TYPE_ETH,
 436         RTE_FLOW_ITEM_TYPE_IPV6,
 437         RTE_FLOW_ITEM_TYPE_UDP,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_RAW,
 441         RTE_FLOW_ITEM_TYPE_END,
 442 };
 443
 444 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 445         RTE_FLOW_ITEM_TYPE_ETH,
 446         RTE_FLOW_ITEM_TYPE_IPV6,
 447         RTE_FLOW_ITEM_TYPE_TCP,
 448         RTE_FLOW_ITEM_TYPE_RAW,
 449         RTE_FLOW_ITEM_TYPE_END,
 450 };
 451
 452 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 453         RTE_FLOW_ITEM_TYPE_ETH,
 454         RTE_FLOW_ITEM_TYPE_IPV6,
 455         RTE_FLOW_ITEM_TYPE_TCP,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_RAW,
 458         RTE_FLOW_ITEM_TYPE_END,
 459 };
 460
 461 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 462         RTE_FLOW_ITEM_TYPE_ETH,
 463         RTE_FLOW_ITEM_TYPE_IPV6,
 464         RTE_FLOW_ITEM_TYPE_TCP,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_RAW,
 468         RTE_FLOW_ITEM_TYPE_END,
 469 };
 470
 471 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 472         RTE_FLOW_ITEM_TYPE_ETH,
 473         RTE_FLOW_ITEM_TYPE_IPV6,
 474         RTE_FLOW_ITEM_TYPE_SCTP,
 475         RTE_FLOW_ITEM_TYPE_RAW,
 476         RTE_FLOW_ITEM_TYPE_END,
 477 };
 478
 479 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 480         RTE_FLOW_ITEM_TYPE_ETH,
 481         RTE_FLOW_ITEM_TYPE_IPV6,
 482         RTE_FLOW_ITEM_TYPE_SCTP,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_RAW,
 485         RTE_FLOW_ITEM_TYPE_END,
 486 };
 487
 488 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 489         RTE_FLOW_ITEM_TYPE_ETH,
 490         RTE_FLOW_ITEM_TYPE_IPV6,
 491         RTE_FLOW_ITEM_TYPE_SCTP,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_RAW,
 495         RTE_FLOW_ITEM_TYPE_END,
 496 };
 497
 498 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 499         RTE_FLOW_ITEM_TYPE_ETH,
 500         RTE_FLOW_ITEM_TYPE_VLAN,
 501         RTE_FLOW_ITEM_TYPE_END,
 502 };
 503
 504 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 505         RTE_FLOW_ITEM_TYPE_ETH,
 506         RTE_FLOW_ITEM_TYPE_VLAN,
 507         RTE_FLOW_ITEM_TYPE_IPV4,
 508         RTE_FLOW_ITEM_TYPE_END,
 509 };
 510
 511 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 512         RTE_FLOW_ITEM_TYPE_ETH,
 513         RTE_FLOW_ITEM_TYPE_VLAN,
 514         RTE_FLOW_ITEM_TYPE_IPV4,
 515         RTE_FLOW_ITEM_TYPE_UDP,
 516         RTE_FLOW_ITEM_TYPE_END,
 517 };
 518
 519 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 520         RTE_FLOW_ITEM_TYPE_ETH,
 521         RTE_FLOW_ITEM_TYPE_VLAN,
 522         RTE_FLOW_ITEM_TYPE_IPV4,
 523         RTE_FLOW_ITEM_TYPE_TCP,
 524         RTE_FLOW_ITEM_TYPE_END,
 525 };
 526
 527 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 528         RTE_FLOW_ITEM_TYPE_ETH,
 529         RTE_FLOW_ITEM_TYPE_VLAN,
 530         RTE_FLOW_ITEM_TYPE_IPV4,
 531         RTE_FLOW_ITEM_TYPE_SCTP,
 532         RTE_FLOW_ITEM_TYPE_END,
 533 };
 534
 535 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 536         RTE_FLOW_ITEM_TYPE_ETH,
 537         RTE_FLOW_ITEM_TYPE_VLAN,
 538         RTE_FLOW_ITEM_TYPE_IPV6,
 539         RTE_FLOW_ITEM_TYPE_END,
 540 };
 541
 542 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 543         RTE_FLOW_ITEM_TYPE_ETH,
 544         RTE_FLOW_ITEM_TYPE_VLAN,
 545         RTE_FLOW_ITEM_TYPE_IPV6,
 546         RTE_FLOW_ITEM_TYPE_UDP,
 547         RTE_FLOW_ITEM_TYPE_END,
 548 };
 549
 550 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 551         RTE_FLOW_ITEM_TYPE_ETH,
 552         RTE_FLOW_ITEM_TYPE_VLAN,
 553         RTE_FLOW_ITEM_TYPE_IPV6,
 554         RTE_FLOW_ITEM_TYPE_TCP,
 555         RTE_FLOW_ITEM_TYPE_END,
 556 };
 557
 558 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 559         RTE_FLOW_ITEM_TYPE_ETH,
 560         RTE_FLOW_ITEM_TYPE_VLAN,
 561         RTE_FLOW_ITEM_TYPE_IPV6,
 562         RTE_FLOW_ITEM_TYPE_SCTP,
 563         RTE_FLOW_ITEM_TYPE_END,
 564 };
 565
 566 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 567         RTE_FLOW_ITEM_TYPE_ETH,
 568         RTE_FLOW_ITEM_TYPE_VLAN,
 569         RTE_FLOW_ITEM_TYPE_RAW,
 570         RTE_FLOW_ITEM_TYPE_END,
 571 };
 572
 573 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 574         RTE_FLOW_ITEM_TYPE_ETH,
 575         RTE_FLOW_ITEM_TYPE_VLAN,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_RAW,
 578         RTE_FLOW_ITEM_TYPE_END,
 579 };
 580
 581 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 582         RTE_FLOW_ITEM_TYPE_ETH,
 583         RTE_FLOW_ITEM_TYPE_VLAN,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_RAW,
 587         RTE_FLOW_ITEM_TYPE_END,
 588 };
 589
 590 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 591         RTE_FLOW_ITEM_TYPE_ETH,
 592         RTE_FLOW_ITEM_TYPE_VLAN,
 593         RTE_FLOW_ITEM_TYPE_IPV4,
 594         RTE_FLOW_ITEM_TYPE_RAW,
 595         RTE_FLOW_ITEM_TYPE_END,
 596 };
 597
 598 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 599         RTE_FLOW_ITEM_TYPE_ETH,
 600         RTE_FLOW_ITEM_TYPE_VLAN,
 601         RTE_FLOW_ITEM_TYPE_IPV4,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_RAW,
 604         RTE_FLOW_ITEM_TYPE_END,
 605 };
 606
 607 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 608         RTE_FLOW_ITEM_TYPE_ETH,
 609         RTE_FLOW_ITEM_TYPE_VLAN,
 610         RTE_FLOW_ITEM_TYPE_IPV4,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_RAW,
 614         RTE_FLOW_ITEM_TYPE_END,
 615 };
 616
 617 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 618         RTE_FLOW_ITEM_TYPE_ETH,
 619         RTE_FLOW_ITEM_TYPE_VLAN,
 620         RTE_FLOW_ITEM_TYPE_IPV4,
 621         RTE_FLOW_ITEM_TYPE_UDP,
 622         RTE_FLOW_ITEM_TYPE_RAW,
 623         RTE_FLOW_ITEM_TYPE_END,
 624 };
 625
 626 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 627         RTE_FLOW_ITEM_TYPE_ETH,
 628         RTE_FLOW_ITEM_TYPE_VLAN,
 629         RTE_FLOW_ITEM_TYPE_IPV4,
 630         RTE_FLOW_ITEM_TYPE_UDP,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_RAW,
 633         RTE_FLOW_ITEM_TYPE_END,
 634 };
 635
 636 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 637         RTE_FLOW_ITEM_TYPE_ETH,
 638         RTE_FLOW_ITEM_TYPE_VLAN,
 639         RTE_FLOW_ITEM_TYPE_IPV4,
 640         RTE_FLOW_ITEM_TYPE_UDP,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_RAW,
 644         RTE_FLOW_ITEM_TYPE_END,
 645 };
 646
 647 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 648         RTE_FLOW_ITEM_TYPE_ETH,
 649         RTE_FLOW_ITEM_TYPE_VLAN,
 650         RTE_FLOW_ITEM_TYPE_IPV4,
 651         RTE_FLOW_ITEM_TYPE_TCP,
 652         RTE_FLOW_ITEM_TYPE_RAW,
 653         RTE_FLOW_ITEM_TYPE_END,
 654 };
 655
 656 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 657         RTE_FLOW_ITEM_TYPE_ETH,
 658         RTE_FLOW_ITEM_TYPE_VLAN,
 659         RTE_FLOW_ITEM_TYPE_IPV4,
 660         RTE_FLOW_ITEM_TYPE_TCP,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_RAW,
 663         RTE_FLOW_ITEM_TYPE_END,
 664 };
 665
 666 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 667         RTE_FLOW_ITEM_TYPE_ETH,
 668         RTE_FLOW_ITEM_TYPE_VLAN,
 669         RTE_FLOW_ITEM_TYPE_IPV4,
 670         RTE_FLOW_ITEM_TYPE_TCP,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_RAW,
 674         RTE_FLOW_ITEM_TYPE_END,
 675 };
 676
 677 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 678         RTE_FLOW_ITEM_TYPE_ETH,
 679         RTE_FLOW_ITEM_TYPE_VLAN,
 680         RTE_FLOW_ITEM_TYPE_IPV4,
 681         RTE_FLOW_ITEM_TYPE_SCTP,
 682         RTE_FLOW_ITEM_TYPE_RAW,
 683         RTE_FLOW_ITEM_TYPE_END,
 684 };
 685
 686 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 687         RTE_FLOW_ITEM_TYPE_ETH,
 688         RTE_FLOW_ITEM_TYPE_VLAN,
 689         RTE_FLOW_ITEM_TYPE_IPV4,
 690         RTE_FLOW_ITEM_TYPE_SCTP,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_RAW,
 693         RTE_FLOW_ITEM_TYPE_END,
 694 };
 695
 696 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 697         RTE_FLOW_ITEM_TYPE_ETH,
 698         RTE_FLOW_ITEM_TYPE_VLAN,
 699         RTE_FLOW_ITEM_TYPE_IPV4,
 700         RTE_FLOW_ITEM_TYPE_SCTP,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_RAW,
 704         RTE_FLOW_ITEM_TYPE_END,
 705 };
 706
 707 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 708         RTE_FLOW_ITEM_TYPE_ETH,
 709         RTE_FLOW_ITEM_TYPE_VLAN,
 710         RTE_FLOW_ITEM_TYPE_IPV6,
 711         RTE_FLOW_ITEM_TYPE_RAW,
 712         RTE_FLOW_ITEM_TYPE_END,
 713 };
 714
 715 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 716         RTE_FLOW_ITEM_TYPE_ETH,
 717         RTE_FLOW_ITEM_TYPE_VLAN,
 718         RTE_FLOW_ITEM_TYPE_IPV6,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_RAW,
 721         RTE_FLOW_ITEM_TYPE_END,
 722 };
 723
 724 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 725         RTE_FLOW_ITEM_TYPE_ETH,
 726         RTE_FLOW_ITEM_TYPE_VLAN,
 727         RTE_FLOW_ITEM_TYPE_IPV6,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_RAW,
 731         RTE_FLOW_ITEM_TYPE_END,
 732 };
 733
 734 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 735         RTE_FLOW_ITEM_TYPE_ETH,
 736         RTE_FLOW_ITEM_TYPE_VLAN,
 737         RTE_FLOW_ITEM_TYPE_IPV6,
 738         RTE_FLOW_ITEM_TYPE_UDP,
 739         RTE_FLOW_ITEM_TYPE_RAW,
 740         RTE_FLOW_ITEM_TYPE_END,
 741 };
 742
 743 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 744         RTE_FLOW_ITEM_TYPE_ETH,
 745         RTE_FLOW_ITEM_TYPE_VLAN,
 746         RTE_FLOW_ITEM_TYPE_IPV6,
 747         RTE_FLOW_ITEM_TYPE_UDP,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_RAW,
 750         RTE_FLOW_ITEM_TYPE_END,
 751 };
 752
 753 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 754         RTE_FLOW_ITEM_TYPE_ETH,
 755         RTE_FLOW_ITEM_TYPE_VLAN,
 756         RTE_FLOW_ITEM_TYPE_IPV6,
 757         RTE_FLOW_ITEM_TYPE_UDP,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_RAW,
 761         RTE_FLOW_ITEM_TYPE_END,
 762 };
 763
 764 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 765         RTE_FLOW_ITEM_TYPE_ETH,
 766         RTE_FLOW_ITEM_TYPE_VLAN,
 767         RTE_FLOW_ITEM_TYPE_IPV6,
 768         RTE_FLOW_ITEM_TYPE_TCP,
 769         RTE_FLOW_ITEM_TYPE_RAW,
 770         RTE_FLOW_ITEM_TYPE_END,
 771 };
 772
 773 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 774         RTE_FLOW_ITEM_TYPE_ETH,
 775         RTE_FLOW_ITEM_TYPE_VLAN,
 776         RTE_FLOW_ITEM_TYPE_IPV6,
 777         RTE_FLOW_ITEM_TYPE_TCP,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_RAW,
 780         RTE_FLOW_ITEM_TYPE_END,
 781 };
 782
 783 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 784         RTE_FLOW_ITEM_TYPE_ETH,
 785         RTE_FLOW_ITEM_TYPE_VLAN,
 786         RTE_FLOW_ITEM_TYPE_IPV6,
 787         RTE_FLOW_ITEM_TYPE_TCP,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_RAW,
 791         RTE_FLOW_ITEM_TYPE_END,
 792 };
 793
 794 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 795         RTE_FLOW_ITEM_TYPE_ETH,
 796         RTE_FLOW_ITEM_TYPE_VLAN,
 797         RTE_FLOW_ITEM_TYPE_IPV6,
 798         RTE_FLOW_ITEM_TYPE_SCTP,
 799         RTE_FLOW_ITEM_TYPE_RAW,
 800         RTE_FLOW_ITEM_TYPE_END,
 801 };
 802
 803 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 804         RTE_FLOW_ITEM_TYPE_ETH,
 805         RTE_FLOW_ITEM_TYPE_VLAN,
 806         RTE_FLOW_ITEM_TYPE_IPV6,
 807         RTE_FLOW_ITEM_TYPE_SCTP,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_RAW,
 810         RTE_FLOW_ITEM_TYPE_END,
 811 };
 812
 813 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 814         RTE_FLOW_ITEM_TYPE_ETH,
 815         RTE_FLOW_ITEM_TYPE_VLAN,
 816         RTE_FLOW_ITEM_TYPE_IPV6,
 817         RTE_FLOW_ITEM_TYPE_SCTP,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_RAW,
 821         RTE_FLOW_ITEM_TYPE_END,
 822 };
 823
 824 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 825         RTE_FLOW_ITEM_TYPE_ETH,
 826         RTE_FLOW_ITEM_TYPE_IPV4,
 827         RTE_FLOW_ITEM_TYPE_VF,
 828         RTE_FLOW_ITEM_TYPE_END,
 829 };
 830
 831 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 832         RTE_FLOW_ITEM_TYPE_ETH,
 833         RTE_FLOW_ITEM_TYPE_IPV4,
 834         RTE_FLOW_ITEM_TYPE_UDP,
 835         RTE_FLOW_ITEM_TYPE_VF,
 836         RTE_FLOW_ITEM_TYPE_END,
 837 };
 838
 839 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 840         RTE_FLOW_ITEM_TYPE_ETH,
 841         RTE_FLOW_ITEM_TYPE_IPV4,
 842         RTE_FLOW_ITEM_TYPE_TCP,
 843         RTE_FLOW_ITEM_TYPE_VF,
 844         RTE_FLOW_ITEM_TYPE_END,
 845 };
 846
 847 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 848         RTE_FLOW_ITEM_TYPE_ETH,
 849         RTE_FLOW_ITEM_TYPE_IPV4,
 850         RTE_FLOW_ITEM_TYPE_SCTP,
 851         RTE_FLOW_ITEM_TYPE_VF,
 852         RTE_FLOW_ITEM_TYPE_END,
 853 };
 854
 855 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 856         RTE_FLOW_ITEM_TYPE_ETH,
 857         RTE_FLOW_ITEM_TYPE_IPV6,
 858         RTE_FLOW_ITEM_TYPE_VF,
 859         RTE_FLOW_ITEM_TYPE_END,
 860 };
 861
 862 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 863         RTE_FLOW_ITEM_TYPE_ETH,
 864         RTE_FLOW_ITEM_TYPE_IPV6,
 865         RTE_FLOW_ITEM_TYPE_UDP,
 866         RTE_FLOW_ITEM_TYPE_VF,
 867         RTE_FLOW_ITEM_TYPE_END,
 868 };
 869
 870 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 871         RTE_FLOW_ITEM_TYPE_ETH,
 872         RTE_FLOW_ITEM_TYPE_IPV6,
 873         RTE_FLOW_ITEM_TYPE_TCP,
 874         RTE_FLOW_ITEM_TYPE_VF,
 875         RTE_FLOW_ITEM_TYPE_END,
 876 };
 877
 878 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 879         RTE_FLOW_ITEM_TYPE_ETH,
 880         RTE_FLOW_ITEM_TYPE_IPV6,
 881         RTE_FLOW_ITEM_TYPE_SCTP,
 882         RTE_FLOW_ITEM_TYPE_VF,
 883         RTE_FLOW_ITEM_TYPE_END,
 884 };
 885
 886 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 887         RTE_FLOW_ITEM_TYPE_ETH,
 888         RTE_FLOW_ITEM_TYPE_RAW,
 889         RTE_FLOW_ITEM_TYPE_VF,
 890         RTE_FLOW_ITEM_TYPE_END,
 891 };
 892
 893 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 894         RTE_FLOW_ITEM_TYPE_ETH,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_RAW,
 897         RTE_FLOW_ITEM_TYPE_VF,
 898         RTE_FLOW_ITEM_TYPE_END,
 899 };
 900
 901 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 902         RTE_FLOW_ITEM_TYPE_ETH,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_RAW,
 906         RTE_FLOW_ITEM_TYPE_VF,
 907         RTE_FLOW_ITEM_TYPE_END,
 908 };
 909
 910 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 911         RTE_FLOW_ITEM_TYPE_ETH,
 912         RTE_FLOW_ITEM_TYPE_IPV4,
 913         RTE_FLOW_ITEM_TYPE_RAW,
 914         RTE_FLOW_ITEM_TYPE_VF,
 915         RTE_FLOW_ITEM_TYPE_END,
 916 };
 917
 918 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 919         RTE_FLOW_ITEM_TYPE_ETH,
 920         RTE_FLOW_ITEM_TYPE_IPV4,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_RAW,
 923         RTE_FLOW_ITEM_TYPE_VF,
 924         RTE_FLOW_ITEM_TYPE_END,
 925 };
 926
 927 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 928         RTE_FLOW_ITEM_TYPE_ETH,
 929         RTE_FLOW_ITEM_TYPE_IPV4,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_RAW,
 933         RTE_FLOW_ITEM_TYPE_VF,
 934         RTE_FLOW_ITEM_TYPE_END,
 935 };
 936
 937 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 938         RTE_FLOW_ITEM_TYPE_ETH,
 939         RTE_FLOW_ITEM_TYPE_IPV4,
 940         RTE_FLOW_ITEM_TYPE_UDP,
 941         RTE_FLOW_ITEM_TYPE_RAW,
 942         RTE_FLOW_ITEM_TYPE_VF,
 943         RTE_FLOW_ITEM_TYPE_END,
 944 };
 945
 946 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 947         RTE_FLOW_ITEM_TYPE_ETH,
 948         RTE_FLOW_ITEM_TYPE_IPV4,
 949         RTE_FLOW_ITEM_TYPE_UDP,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_RAW,
 952         RTE_FLOW_ITEM_TYPE_VF,
 953         RTE_FLOW_ITEM_TYPE_END,
 954 };
 955
 956 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 957         RTE_FLOW_ITEM_TYPE_ETH,
 958         RTE_FLOW_ITEM_TYPE_IPV4,
 959         RTE_FLOW_ITEM_TYPE_UDP,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_RAW,
 963         RTE_FLOW_ITEM_TYPE_VF,
 964         RTE_FLOW_ITEM_TYPE_END,
 965 };
 966
 967 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 968         RTE_FLOW_ITEM_TYPE_ETH,
 969         RTE_FLOW_ITEM_TYPE_IPV4,
 970         RTE_FLOW_ITEM_TYPE_TCP,
 971         RTE_FLOW_ITEM_TYPE_RAW,
 972         RTE_FLOW_ITEM_TYPE_VF,
 973         RTE_FLOW_ITEM_TYPE_END,
 974 };
 975
 976 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 977         RTE_FLOW_ITEM_TYPE_ETH,
 978         RTE_FLOW_ITEM_TYPE_IPV4,
 979         RTE_FLOW_ITEM_TYPE_TCP,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_RAW,
 982         RTE_FLOW_ITEM_TYPE_VF,
 983         RTE_FLOW_ITEM_TYPE_END,
 984 };
 985
 986 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 987         RTE_FLOW_ITEM_TYPE_ETH,
 988         RTE_FLOW_ITEM_TYPE_IPV4,
 989         RTE_FLOW_ITEM_TYPE_TCP,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_RAW,
 993         RTE_FLOW_ITEM_TYPE_VF,
 994         RTE_FLOW_ITEM_TYPE_END,
 995 };
 996
 997 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 998         RTE_FLOW_ITEM_TYPE_ETH,
 999         RTE_FLOW_ITEM_TYPE_IPV4,
1000         RTE_FLOW_ITEM_TYPE_SCTP,
1001         RTE_FLOW_ITEM_TYPE_RAW,
1002         RTE_FLOW_ITEM_TYPE_VF,
1003         RTE_FLOW_ITEM_TYPE_END,
1004 };
1005
1006 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1007         RTE_FLOW_ITEM_TYPE_ETH,
1008         RTE_FLOW_ITEM_TYPE_IPV4,
1009         RTE_FLOW_ITEM_TYPE_SCTP,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_RAW,
1012         RTE_FLOW_ITEM_TYPE_VF,
1013         RTE_FLOW_ITEM_TYPE_END,
1014 };
1015
1016 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1017         RTE_FLOW_ITEM_TYPE_ETH,
1018         RTE_FLOW_ITEM_TYPE_IPV4,
1019         RTE_FLOW_ITEM_TYPE_SCTP,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_RAW,
1023         RTE_FLOW_ITEM_TYPE_VF,
1024         RTE_FLOW_ITEM_TYPE_END,
1025 };
1026
1027 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1028         RTE_FLOW_ITEM_TYPE_ETH,
1029         RTE_FLOW_ITEM_TYPE_IPV6,
1030         RTE_FLOW_ITEM_TYPE_RAW,
1031         RTE_FLOW_ITEM_TYPE_VF,
1032         RTE_FLOW_ITEM_TYPE_END,
1033 };
1034
1035 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1036         RTE_FLOW_ITEM_TYPE_ETH,
1037         RTE_FLOW_ITEM_TYPE_IPV6,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_RAW,
1040         RTE_FLOW_ITEM_TYPE_VF,
1041         RTE_FLOW_ITEM_TYPE_END,
1042 };
1043
1044 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1045         RTE_FLOW_ITEM_TYPE_ETH,
1046         RTE_FLOW_ITEM_TYPE_IPV6,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_RAW,
1050         RTE_FLOW_ITEM_TYPE_VF,
1051         RTE_FLOW_ITEM_TYPE_END,
1052 };
1053
1054 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1055         RTE_FLOW_ITEM_TYPE_ETH,
1056         RTE_FLOW_ITEM_TYPE_IPV6,
1057         RTE_FLOW_ITEM_TYPE_UDP,
1058         RTE_FLOW_ITEM_TYPE_RAW,
1059         RTE_FLOW_ITEM_TYPE_VF,
1060         RTE_FLOW_ITEM_TYPE_END,
1061 };
1062
1063 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1064         RTE_FLOW_ITEM_TYPE_ETH,
1065         RTE_FLOW_ITEM_TYPE_IPV6,
1066         RTE_FLOW_ITEM_TYPE_UDP,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_RAW,
1069         RTE_FLOW_ITEM_TYPE_VF,
1070         RTE_FLOW_ITEM_TYPE_END,
1071 };
1072
1073 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1074         RTE_FLOW_ITEM_TYPE_ETH,
1075         RTE_FLOW_ITEM_TYPE_IPV6,
1076         RTE_FLOW_ITEM_TYPE_UDP,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_RAW,
1080         RTE_FLOW_ITEM_TYPE_VF,
1081         RTE_FLOW_ITEM_TYPE_END,
1082 };
1083
1084 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1085         RTE_FLOW_ITEM_TYPE_ETH,
1086         RTE_FLOW_ITEM_TYPE_IPV6,
1087         RTE_FLOW_ITEM_TYPE_TCP,
1088         RTE_FLOW_ITEM_TYPE_RAW,
1089         RTE_FLOW_ITEM_TYPE_VF,
1090         RTE_FLOW_ITEM_TYPE_END,
1091 };
1092
1093 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1094         RTE_FLOW_ITEM_TYPE_ETH,
1095         RTE_FLOW_ITEM_TYPE_IPV6,
1096         RTE_FLOW_ITEM_TYPE_TCP,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_RAW,
1099         RTE_FLOW_ITEM_TYPE_VF,
1100         RTE_FLOW_ITEM_TYPE_END,
1101 };
1102
1103 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1104         RTE_FLOW_ITEM_TYPE_ETH,
1105         RTE_FLOW_ITEM_TYPE_IPV6,
1106         RTE_FLOW_ITEM_TYPE_TCP,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_RAW,
1110         RTE_FLOW_ITEM_TYPE_VF,
1111         RTE_FLOW_ITEM_TYPE_END,
1112 };
1113
1114 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1115         RTE_FLOW_ITEM_TYPE_ETH,
1116         RTE_FLOW_ITEM_TYPE_IPV6,
1117         RTE_FLOW_ITEM_TYPE_SCTP,
1118         RTE_FLOW_ITEM_TYPE_RAW,
1119         RTE_FLOW_ITEM_TYPE_VF,
1120         RTE_FLOW_ITEM_TYPE_END,
1121 };
1122
1123 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1124         RTE_FLOW_ITEM_TYPE_ETH,
1125         RTE_FLOW_ITEM_TYPE_IPV6,
1126         RTE_FLOW_ITEM_TYPE_SCTP,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_RAW,
1129         RTE_FLOW_ITEM_TYPE_VF,
1130         RTE_FLOW_ITEM_TYPE_END,
1131 };
1132
1133 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1134         RTE_FLOW_ITEM_TYPE_ETH,
1135         RTE_FLOW_ITEM_TYPE_IPV6,
1136         RTE_FLOW_ITEM_TYPE_SCTP,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_RAW,
1140         RTE_FLOW_ITEM_TYPE_VF,
1141         RTE_FLOW_ITEM_TYPE_END,
1142 };
1143
1144 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1145         RTE_FLOW_ITEM_TYPE_ETH,
1146         RTE_FLOW_ITEM_TYPE_VLAN,
1147         RTE_FLOW_ITEM_TYPE_VF,
1148         RTE_FLOW_ITEM_TYPE_END,
1149 };
1150
1151 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1152         RTE_FLOW_ITEM_TYPE_ETH,
1153         RTE_FLOW_ITEM_TYPE_VLAN,
1154         RTE_FLOW_ITEM_TYPE_IPV4,
1155         RTE_FLOW_ITEM_TYPE_VF,
1156         RTE_FLOW_ITEM_TYPE_END,
1157 };
1158
1159 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1160         RTE_FLOW_ITEM_TYPE_ETH,
1161         RTE_FLOW_ITEM_TYPE_VLAN,
1162         RTE_FLOW_ITEM_TYPE_IPV4,
1163         RTE_FLOW_ITEM_TYPE_UDP,
1164         RTE_FLOW_ITEM_TYPE_VF,
1165         RTE_FLOW_ITEM_TYPE_END,
1166 };
1167
1168 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1169         RTE_FLOW_ITEM_TYPE_ETH,
1170         RTE_FLOW_ITEM_TYPE_VLAN,
1171         RTE_FLOW_ITEM_TYPE_IPV4,
1172         RTE_FLOW_ITEM_TYPE_TCP,
1173         RTE_FLOW_ITEM_TYPE_VF,
1174         RTE_FLOW_ITEM_TYPE_END,
1175 };
1176
1177 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1178         RTE_FLOW_ITEM_TYPE_ETH,
1179         RTE_FLOW_ITEM_TYPE_VLAN,
1180         RTE_FLOW_ITEM_TYPE_IPV4,
1181         RTE_FLOW_ITEM_TYPE_SCTP,
1182         RTE_FLOW_ITEM_TYPE_VF,
1183         RTE_FLOW_ITEM_TYPE_END,
1184 };
1185
1186 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1187         RTE_FLOW_ITEM_TYPE_ETH,
1188         RTE_FLOW_ITEM_TYPE_VLAN,
1189         RTE_FLOW_ITEM_TYPE_IPV6,
1190         RTE_FLOW_ITEM_TYPE_VF,
1191         RTE_FLOW_ITEM_TYPE_END,
1192 };
1193
1194 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1195         RTE_FLOW_ITEM_TYPE_ETH,
1196         RTE_FLOW_ITEM_TYPE_VLAN,
1197         RTE_FLOW_ITEM_TYPE_IPV6,
1198         RTE_FLOW_ITEM_TYPE_UDP,
1199         RTE_FLOW_ITEM_TYPE_VF,
1200         RTE_FLOW_ITEM_TYPE_END,
1201 };
1202
1203 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1204         RTE_FLOW_ITEM_TYPE_ETH,
1205         RTE_FLOW_ITEM_TYPE_VLAN,
1206         RTE_FLOW_ITEM_TYPE_IPV6,
1207         RTE_FLOW_ITEM_TYPE_TCP,
1208         RTE_FLOW_ITEM_TYPE_VF,
1209         RTE_FLOW_ITEM_TYPE_END,
1210 };
1211
1212 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1213         RTE_FLOW_ITEM_TYPE_ETH,
1214         RTE_FLOW_ITEM_TYPE_VLAN,
1215         RTE_FLOW_ITEM_TYPE_IPV6,
1216         RTE_FLOW_ITEM_TYPE_SCTP,
1217         RTE_FLOW_ITEM_TYPE_VF,
1218         RTE_FLOW_ITEM_TYPE_END,
1219 };
1220
1221 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1222         RTE_FLOW_ITEM_TYPE_ETH,
1223         RTE_FLOW_ITEM_TYPE_VLAN,
1224         RTE_FLOW_ITEM_TYPE_RAW,
1225         RTE_FLOW_ITEM_TYPE_VF,
1226         RTE_FLOW_ITEM_TYPE_END,
1227 };
1228
1229 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1230         RTE_FLOW_ITEM_TYPE_ETH,
1231         RTE_FLOW_ITEM_TYPE_VLAN,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_RAW,
1234         RTE_FLOW_ITEM_TYPE_VF,
1235         RTE_FLOW_ITEM_TYPE_END,
1236 };
1237
1238 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1239         RTE_FLOW_ITEM_TYPE_ETH,
1240         RTE_FLOW_ITEM_TYPE_VLAN,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_RAW,
1244         RTE_FLOW_ITEM_TYPE_VF,
1245         RTE_FLOW_ITEM_TYPE_END,
1246 };
1247
1248 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1249         RTE_FLOW_ITEM_TYPE_ETH,
1250         RTE_FLOW_ITEM_TYPE_VLAN,
1251         RTE_FLOW_ITEM_TYPE_IPV4,
1252         RTE_FLOW_ITEM_TYPE_RAW,
1253         RTE_FLOW_ITEM_TYPE_VF,
1254         RTE_FLOW_ITEM_TYPE_END,
1255 };
1256
1257 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1258         RTE_FLOW_ITEM_TYPE_ETH,
1259         RTE_FLOW_ITEM_TYPE_VLAN,
1260         RTE_FLOW_ITEM_TYPE_IPV4,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_RAW,
1263         RTE_FLOW_ITEM_TYPE_VF,
1264         RTE_FLOW_ITEM_TYPE_END,
1265 };
1266
1267 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1268         RTE_FLOW_ITEM_TYPE_ETH,
1269         RTE_FLOW_ITEM_TYPE_VLAN,
1270         RTE_FLOW_ITEM_TYPE_IPV4,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_RAW,
1274         RTE_FLOW_ITEM_TYPE_VF,
1275         RTE_FLOW_ITEM_TYPE_END,
1276 };
1277
1278 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1279         RTE_FLOW_ITEM_TYPE_ETH,
1280         RTE_FLOW_ITEM_TYPE_VLAN,
1281         RTE_FLOW_ITEM_TYPE_IPV4,
1282         RTE_FLOW_ITEM_TYPE_UDP,
1283         RTE_FLOW_ITEM_TYPE_RAW,
1284         RTE_FLOW_ITEM_TYPE_VF,
1285         RTE_FLOW_ITEM_TYPE_END,
1286 };
1287
1288 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1289         RTE_FLOW_ITEM_TYPE_ETH,
1290         RTE_FLOW_ITEM_TYPE_VLAN,
1291         RTE_FLOW_ITEM_TYPE_IPV4,
1292         RTE_FLOW_ITEM_TYPE_UDP,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_RAW,
1295         RTE_FLOW_ITEM_TYPE_VF,
1296         RTE_FLOW_ITEM_TYPE_END,
1297 };
1298
1299 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1300         RTE_FLOW_ITEM_TYPE_ETH,
1301         RTE_FLOW_ITEM_TYPE_VLAN,
1302         RTE_FLOW_ITEM_TYPE_IPV4,
1303         RTE_FLOW_ITEM_TYPE_UDP,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_RAW,
1307         RTE_FLOW_ITEM_TYPE_VF,
1308         RTE_FLOW_ITEM_TYPE_END,
1309 };
1310
1311 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1312         RTE_FLOW_ITEM_TYPE_ETH,
1313         RTE_FLOW_ITEM_TYPE_VLAN,
1314         RTE_FLOW_ITEM_TYPE_IPV4,
1315         RTE_FLOW_ITEM_TYPE_TCP,
1316         RTE_FLOW_ITEM_TYPE_RAW,
1317         RTE_FLOW_ITEM_TYPE_VF,
1318         RTE_FLOW_ITEM_TYPE_END,
1319 };
1320
1321 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1322         RTE_FLOW_ITEM_TYPE_ETH,
1323         RTE_FLOW_ITEM_TYPE_VLAN,
1324         RTE_FLOW_ITEM_TYPE_IPV4,
1325         RTE_FLOW_ITEM_TYPE_TCP,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_RAW,
1328         RTE_FLOW_ITEM_TYPE_VF,
1329         RTE_FLOW_ITEM_TYPE_END,
1330 };
1331
1332 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1333         RTE_FLOW_ITEM_TYPE_ETH,
1334         RTE_FLOW_ITEM_TYPE_VLAN,
1335         RTE_FLOW_ITEM_TYPE_IPV4,
1336         RTE_FLOW_ITEM_TYPE_TCP,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_RAW,
1340         RTE_FLOW_ITEM_TYPE_VF,
1341         RTE_FLOW_ITEM_TYPE_END,
1342 };
1343
1344 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1345         RTE_FLOW_ITEM_TYPE_ETH,
1346         RTE_FLOW_ITEM_TYPE_VLAN,
1347         RTE_FLOW_ITEM_TYPE_IPV4,
1348         RTE_FLOW_ITEM_TYPE_SCTP,
1349         RTE_FLOW_ITEM_TYPE_RAW,
1350         RTE_FLOW_ITEM_TYPE_VF,
1351         RTE_FLOW_ITEM_TYPE_END,
1352 };
1353
1354 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1355         RTE_FLOW_ITEM_TYPE_ETH,
1356         RTE_FLOW_ITEM_TYPE_VLAN,
1357         RTE_FLOW_ITEM_TYPE_IPV4,
1358         RTE_FLOW_ITEM_TYPE_SCTP,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_RAW,
1361         RTE_FLOW_ITEM_TYPE_VF,
1362         RTE_FLOW_ITEM_TYPE_END,
1363 };
1364
1365 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1366         RTE_FLOW_ITEM_TYPE_ETH,
1367         RTE_FLOW_ITEM_TYPE_VLAN,
1368         RTE_FLOW_ITEM_TYPE_IPV4,
1369         RTE_FLOW_ITEM_TYPE_SCTP,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_RAW,
1373         RTE_FLOW_ITEM_TYPE_VF,
1374         RTE_FLOW_ITEM_TYPE_END,
1375 };
1376
1377 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1378         RTE_FLOW_ITEM_TYPE_ETH,
1379         RTE_FLOW_ITEM_TYPE_VLAN,
1380         RTE_FLOW_ITEM_TYPE_IPV6,
1381         RTE_FLOW_ITEM_TYPE_RAW,
1382         RTE_FLOW_ITEM_TYPE_VF,
1383         RTE_FLOW_ITEM_TYPE_END,
1384 };
1385
1386 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1387         RTE_FLOW_ITEM_TYPE_ETH,
1388         RTE_FLOW_ITEM_TYPE_VLAN,
1389         RTE_FLOW_ITEM_TYPE_IPV6,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_RAW,
1392         RTE_FLOW_ITEM_TYPE_VF,
1393         RTE_FLOW_ITEM_TYPE_END,
1394 };
1395
1396 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1397         RTE_FLOW_ITEM_TYPE_ETH,
1398         RTE_FLOW_ITEM_TYPE_VLAN,
1399         RTE_FLOW_ITEM_TYPE_IPV6,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_RAW,
1403         RTE_FLOW_ITEM_TYPE_VF,
1404         RTE_FLOW_ITEM_TYPE_END,
1405 };
1406
1407 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1408         RTE_FLOW_ITEM_TYPE_ETH,
1409         RTE_FLOW_ITEM_TYPE_VLAN,
1410         RTE_FLOW_ITEM_TYPE_IPV6,
1411         RTE_FLOW_ITEM_TYPE_UDP,
1412         RTE_FLOW_ITEM_TYPE_RAW,
1413         RTE_FLOW_ITEM_TYPE_VF,
1414         RTE_FLOW_ITEM_TYPE_END,
1415 };
1416
1417 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1418         RTE_FLOW_ITEM_TYPE_ETH,
1419         RTE_FLOW_ITEM_TYPE_VLAN,
1420         RTE_FLOW_ITEM_TYPE_IPV6,
1421         RTE_FLOW_ITEM_TYPE_UDP,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_RAW,
1424         RTE_FLOW_ITEM_TYPE_VF,
1425         RTE_FLOW_ITEM_TYPE_END,
1426 };
1427
1428 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1429         RTE_FLOW_ITEM_TYPE_ETH,
1430         RTE_FLOW_ITEM_TYPE_VLAN,
1431         RTE_FLOW_ITEM_TYPE_IPV6,
1432         RTE_FLOW_ITEM_TYPE_UDP,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_RAW,
1436         RTE_FLOW_ITEM_TYPE_VF,
1437         RTE_FLOW_ITEM_TYPE_END,
1438 };
1439
1440 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1441         RTE_FLOW_ITEM_TYPE_ETH,
1442         RTE_FLOW_ITEM_TYPE_VLAN,
1443         RTE_FLOW_ITEM_TYPE_IPV6,
1444         RTE_FLOW_ITEM_TYPE_TCP,
1445         RTE_FLOW_ITEM_TYPE_RAW,
1446         RTE_FLOW_ITEM_TYPE_VF,
1447         RTE_FLOW_ITEM_TYPE_END,
1448 };
1449
1450 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1451         RTE_FLOW_ITEM_TYPE_ETH,
1452         RTE_FLOW_ITEM_TYPE_VLAN,
1453         RTE_FLOW_ITEM_TYPE_IPV6,
1454         RTE_FLOW_ITEM_TYPE_TCP,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_RAW,
1457         RTE_FLOW_ITEM_TYPE_VF,
1458         RTE_FLOW_ITEM_TYPE_END,
1459 };
1460
1461 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1462         RTE_FLOW_ITEM_TYPE_ETH,
1463         RTE_FLOW_ITEM_TYPE_VLAN,
1464         RTE_FLOW_ITEM_TYPE_IPV6,
1465         RTE_FLOW_ITEM_TYPE_TCP,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_RAW,
1469         RTE_FLOW_ITEM_TYPE_VF,
1470         RTE_FLOW_ITEM_TYPE_END,
1471 };
1472
1473 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1474         RTE_FLOW_ITEM_TYPE_ETH,
1475         RTE_FLOW_ITEM_TYPE_VLAN,
1476         RTE_FLOW_ITEM_TYPE_IPV6,
1477         RTE_FLOW_ITEM_TYPE_SCTP,
1478         RTE_FLOW_ITEM_TYPE_RAW,
1479         RTE_FLOW_ITEM_TYPE_VF,
1480         RTE_FLOW_ITEM_TYPE_END,
1481 };
1482
1483 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1484         RTE_FLOW_ITEM_TYPE_ETH,
1485         RTE_FLOW_ITEM_TYPE_VLAN,
1486         RTE_FLOW_ITEM_TYPE_IPV6,
1487         RTE_FLOW_ITEM_TYPE_SCTP,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_RAW,
1490         RTE_FLOW_ITEM_TYPE_VF,
1491         RTE_FLOW_ITEM_TYPE_END,
1492 };
1493
1494 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1495         RTE_FLOW_ITEM_TYPE_ETH,
1496         RTE_FLOW_ITEM_TYPE_VLAN,
1497         RTE_FLOW_ITEM_TYPE_IPV6,
1498         RTE_FLOW_ITEM_TYPE_SCTP,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_RAW,
1502         RTE_FLOW_ITEM_TYPE_VF,
1503         RTE_FLOW_ITEM_TYPE_END,
1504 };
1505
1506 /* Pattern matched tunnel filter */
1507 static enum rte_flow_item_type pattern_vxlan_1[] = {
1508         RTE_FLOW_ITEM_TYPE_ETH,
1509         RTE_FLOW_ITEM_TYPE_IPV4,
1510         RTE_FLOW_ITEM_TYPE_UDP,
1511         RTE_FLOW_ITEM_TYPE_VXLAN,
1512         RTE_FLOW_ITEM_TYPE_ETH,
1513         RTE_FLOW_ITEM_TYPE_END,
1514 };
1515
1516 static enum rte_flow_item_type pattern_vxlan_2[] = {
1517         RTE_FLOW_ITEM_TYPE_ETH,
1518         RTE_FLOW_ITEM_TYPE_IPV6,
1519         RTE_FLOW_ITEM_TYPE_UDP,
1520         RTE_FLOW_ITEM_TYPE_VXLAN,
1521         RTE_FLOW_ITEM_TYPE_ETH,
1522         RTE_FLOW_ITEM_TYPE_END,
1523 };
1524
1525 static enum rte_flow_item_type pattern_vxlan_3[] = {
1526         RTE_FLOW_ITEM_TYPE_ETH,
1527         RTE_FLOW_ITEM_TYPE_IPV4,
1528         RTE_FLOW_ITEM_TYPE_UDP,
1529         RTE_FLOW_ITEM_TYPE_VXLAN,
1530         RTE_FLOW_ITEM_TYPE_ETH,
1531         RTE_FLOW_ITEM_TYPE_VLAN,
1532         RTE_FLOW_ITEM_TYPE_END,
1533 };
1534
1535 static enum rte_flow_item_type pattern_vxlan_4[] = {
1536         RTE_FLOW_ITEM_TYPE_ETH,
1537         RTE_FLOW_ITEM_TYPE_IPV6,
1538         RTE_FLOW_ITEM_TYPE_UDP,
1539         RTE_FLOW_ITEM_TYPE_VXLAN,
1540         RTE_FLOW_ITEM_TYPE_ETH,
1541         RTE_FLOW_ITEM_TYPE_VLAN,
1542         RTE_FLOW_ITEM_TYPE_END,
1543 };
1544
1545 static enum rte_flow_item_type pattern_nvgre_1[] = {
1546         RTE_FLOW_ITEM_TYPE_ETH,
1547         RTE_FLOW_ITEM_TYPE_IPV4,
1548         RTE_FLOW_ITEM_TYPE_NVGRE,
1549         RTE_FLOW_ITEM_TYPE_ETH,
1550         RTE_FLOW_ITEM_TYPE_END,
1551 };
1552
1553 static enum rte_flow_item_type pattern_nvgre_2[] = {
1554         RTE_FLOW_ITEM_TYPE_ETH,
1555         RTE_FLOW_ITEM_TYPE_IPV6,
1556         RTE_FLOW_ITEM_TYPE_NVGRE,
1557         RTE_FLOW_ITEM_TYPE_ETH,
1558         RTE_FLOW_ITEM_TYPE_END,
1559 };
1560
1561 static enum rte_flow_item_type pattern_nvgre_3[] = {
1562         RTE_FLOW_ITEM_TYPE_ETH,
1563         RTE_FLOW_ITEM_TYPE_IPV4,
1564         RTE_FLOW_ITEM_TYPE_NVGRE,
1565         RTE_FLOW_ITEM_TYPE_ETH,
1566         RTE_FLOW_ITEM_TYPE_VLAN,
1567         RTE_FLOW_ITEM_TYPE_END,
1568 };
1569
1570 static enum rte_flow_item_type pattern_nvgre_4[] = {
1571         RTE_FLOW_ITEM_TYPE_ETH,
1572         RTE_FLOW_ITEM_TYPE_IPV6,
1573         RTE_FLOW_ITEM_TYPE_NVGRE,
1574         RTE_FLOW_ITEM_TYPE_ETH,
1575         RTE_FLOW_ITEM_TYPE_VLAN,
1576         RTE_FLOW_ITEM_TYPE_END,
1577 };
1578
1579 static enum rte_flow_item_type pattern_mpls_1[] = {
1580         RTE_FLOW_ITEM_TYPE_ETH,
1581         RTE_FLOW_ITEM_TYPE_IPV4,
1582         RTE_FLOW_ITEM_TYPE_UDP,
1583         RTE_FLOW_ITEM_TYPE_MPLS,
1584         RTE_FLOW_ITEM_TYPE_END,
1585 };
1586
1587 static enum rte_flow_item_type pattern_mpls_2[] = {
1588         RTE_FLOW_ITEM_TYPE_ETH,
1589         RTE_FLOW_ITEM_TYPE_IPV6,
1590         RTE_FLOW_ITEM_TYPE_UDP,
1591         RTE_FLOW_ITEM_TYPE_MPLS,
1592         RTE_FLOW_ITEM_TYPE_END,
1593 };
1594
1595 static enum rte_flow_item_type pattern_mpls_3[] = {
1596         RTE_FLOW_ITEM_TYPE_ETH,
1597         RTE_FLOW_ITEM_TYPE_IPV4,
1598         RTE_FLOW_ITEM_TYPE_GRE,
1599         RTE_FLOW_ITEM_TYPE_MPLS,
1600         RTE_FLOW_ITEM_TYPE_END,
1601 };
1602
1603 static enum rte_flow_item_type pattern_mpls_4[] = {
1604         RTE_FLOW_ITEM_TYPE_ETH,
1605         RTE_FLOW_ITEM_TYPE_IPV6,
1606         RTE_FLOW_ITEM_TYPE_GRE,
1607         RTE_FLOW_ITEM_TYPE_MPLS,
1608         RTE_FLOW_ITEM_TYPE_END,
1609 };
1610
1611 static enum rte_flow_item_type pattern_qinq_1[] = {
1612         RTE_FLOW_ITEM_TYPE_ETH,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_VLAN,
1615         RTE_FLOW_ITEM_TYPE_END,
1616 };
1617
1618 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1619         /* Ethertype */
1620         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1621         /* FDIR - support default flow type without flexible payload*/
1622         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1623         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1636         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1637         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1638         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1639         /* FDIR - support default flow type with flexible payload */
1640         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1641         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1665         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1666         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1667         /* FDIR - support single vlan input set */
1668         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1704         /* FDIR - support VF item */
1705         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1776         /* VXLAN */
1777         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1778         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1779         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1780         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1781         /* NVGRE */
1782         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1783         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1784         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1785         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1786         /* MPLSoUDP & MPLSoGRE */
1787         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1788         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1789         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1790         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1791         /* GTP-C & GTP-U */
1792         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1793         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1794         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1795         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1796         /* QINQ */
1797         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1798 };
1799
1800 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1801         do {                                                            \
1802                 act = actions + index;                                  \
1803                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1804                         index++;                                        \
1805                         act = actions + index;                          \
1806                 }                                                       \
1807         } while (0)
1808
1809 /* Find the first VOID or non-VOID item pointer */
1810 static const struct rte_flow_item *
1811 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1812 {
1813         bool is_find;
1814
1815         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1816                 if (is_void)
1817                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1818                 else
1819                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1820                 if (is_find)
1821                         break;
1822                 item++;
1823         }
1824         return item;
1825 }
1826
1827 /* Skip all VOID items of the pattern */
1828 static void
1829 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1830                             const struct rte_flow_item *pattern)
1831 {
1832         uint32_t cpy_count = 0;
1833         const struct rte_flow_item *pb = pattern, *pe = pattern;
1834
1835         for (;;) {
1836                 /* Find a non-void item first */
1837                 pb = i40e_find_first_item(pb, false);
1838                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1839                         pe = pb;
1840                         break;
1841                 }
1842
1843                 /* Find a void item */
1844                 pe = i40e_find_first_item(pb + 1, true);
1845
1846                 cpy_count = pe - pb;
1847                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1848
1849                 items += cpy_count;
1850
1851                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1852                         pb = pe;
1853                         break;
1854                 }
1855
1856                 pb = pe + 1;
1857         }
1858         /* Copy the END item. */
1859         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1860 }
1861
1862 /* Check if the pattern matches a supported item type array */
1863 static bool
1864 i40e_match_pattern(enum rte_flow_item_type *item_array,
1865                    struct rte_flow_item *pattern)
1866 {
1867         struct rte_flow_item *item = pattern;
1868
1869         while ((*item_array == item->type) &&
1870                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1871                 item_array++;
1872                 item++;
1873         }
1874
1875         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1876                 item->type == RTE_FLOW_ITEM_TYPE_END);
1877 }
1878
1879 /* Find if there's parse filter function matched */
1880 static parse_filter_t
1881 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1882 {
1883         parse_filter_t parse_filter = NULL;
1884         uint8_t i = *idx;
1885
1886         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1887                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1888                                         pattern)) {
1889                         parse_filter = i40e_supported_patterns[i].parse_filter;
1890                         break;
1891                 }
1892         }
1893
1894         *idx = ++i;
1895
1896         return parse_filter;
1897 }
1898
1899 /* Parse attributes */
1900 static int
1901 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1902                      struct rte_flow_error *error)
1903 {
1904         /* Must be input direction */
1905         if (!attr->ingress) {
1906                 rte_flow_error_set(error, EINVAL,
1907                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1908                                    attr, "Only support ingress.");
1909                 return -rte_errno;
1910         }
1911
1912         /* Not supported */
1913         if (attr->egress) {
1914                 rte_flow_error_set(error, EINVAL,
1915                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1916                                    attr, "Not support egress.");
1917                 return -rte_errno;
1918         }
1919
1920         /* Not supported */
1921         if (attr->priority) {
1922                 rte_flow_error_set(error, EINVAL,
1923                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1924                                    attr, "Not support priority.");
1925                 return -rte_errno;
1926         }
1927
1928         /* Not supported */
1929         if (attr->group) {
1930                 rte_flow_error_set(error, EINVAL,
1931                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1932                                    attr, "Not support group.");
1933                 return -rte_errno;
1934         }
1935
1936         return 0;
1937 }
1938
1939 static uint16_t
1940 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1941 {
1942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         int qinq = dev->data->dev_conf.rxmode.offloads &
1944                 DEV_RX_OFFLOAD_VLAN_EXTEND;
1945         uint64_t reg_r = 0;
1946         uint16_t reg_id;
1947         uint16_t tpid;
1948
1949         if (qinq)
1950                 reg_id = 2;
1951         else
1952                 reg_id = 3;
1953
1954         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1955                                     &reg_r, NULL);
1956
1957         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1958
1959         return tpid;
1960 }
1961
1962 /* 1. Last in item should be NULL as range is not supported.
1963  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1964  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1965  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1966  *    FF:FF:FF:FF:FF:FF
1967  * 5. Ether_type mask should be 0xFFFF.
1968  */
1969 static int
1970 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1971                                   const struct rte_flow_item *pattern,
1972                                   struct rte_flow_error *error,
1973                                   struct rte_eth_ethertype_filter *filter)
1974 {
1975         const struct rte_flow_item *item = pattern;
1976         const struct rte_flow_item_eth *eth_spec;
1977         const struct rte_flow_item_eth *eth_mask;
1978         enum rte_flow_item_type item_type;
1979         uint16_t outer_tpid;
1980
1981         outer_tpid = i40e_get_outer_vlan(dev);
1982
1983         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1984                 if (item->last) {
1985                         rte_flow_error_set(error, EINVAL,
1986                                            RTE_FLOW_ERROR_TYPE_ITEM,
1987                                            item,
1988                                            "Not support range");
1989                         return -rte_errno;
1990                 }
1991                 item_type = item->type;
1992                 switch (item_type) {
1993                 case RTE_FLOW_ITEM_TYPE_ETH:
1994                         eth_spec = item->spec;
1995                         eth_mask = item->mask;
1996                         /* Get the MAC info. */
1997                         if (!eth_spec || !eth_mask) {
1998                                 rte_flow_error_set(error, EINVAL,
1999                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2000                                                    item,
2001                                                    "NULL ETH spec/mask");
2002                                 return -rte_errno;
2003                         }
2004
2005                         /* Mask bits of source MAC address must be full of 0.
2006                          * Mask bits of destination MAC address must be full
2007                          * of 1 or full of 0.
2008                          */
2009                         if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2010                             (!rte_is_zero_ether_addr(&eth_mask->dst) &&
2011                              !rte_is_broadcast_ether_addr(&eth_mask->dst))) {
2012                                 rte_flow_error_set(error, EINVAL,
2013                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2014                                                    item,
2015                                                    "Invalid MAC_addr mask");
2016                                 return -rte_errno;
2017                         }
2018
2019                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2020                                 rte_flow_error_set(error, EINVAL,
2021                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2022                                                    item,
2023                                                    "Invalid ethertype mask");
2024                                 return -rte_errno;
2025                         }
2026
2027                         /* If mask bits of destination MAC address
2028                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2029                          */
2030                         if (rte_is_broadcast_ether_addr(&eth_mask->dst)) {
2031                                 filter->mac_addr = eth_spec->dst;
2032                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2033                         } else {
2034                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2035                         }
2036                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2037
2038                         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2039                             filter->ether_type == RTE_ETHER_TYPE_IPV6 ||
2040                             filter->ether_type == RTE_ETHER_TYPE_LLDP ||
2041                             filter->ether_type == outer_tpid) {
2042                                 rte_flow_error_set(error, EINVAL,
2043                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2044                                                    item,
2045                                                    "Unsupported ether_type in"
2046                                                    " control packet filter.");
2047                                 return -rte_errno;
2048                         }
2049                         break;
2050                 default:
2051                         break;
2052                 }
2053         }
2054
2055         return 0;
2056 }
2057
2058 /* Ethertype action only supports QUEUE or DROP. */
2059 static int
2060 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2061                                  const struct rte_flow_action *actions,
2062                                  struct rte_flow_error *error,
2063                                  struct rte_eth_ethertype_filter *filter)
2064 {
2065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066         const struct rte_flow_action *act;
2067         const struct rte_flow_action_queue *act_q;
2068         uint32_t index = 0;
2069
2070         /* Check if the first non-void action is QUEUE or DROP. */
2071         NEXT_ITEM_OF_ACTION(act, actions, index);
2072         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2073             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2074                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2075                                    act, "Not supported action.");
2076                 return -rte_errno;
2077         }
2078
2079         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2080                 act_q = act->conf;
2081                 filter->queue = act_q->index;
2082                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2083                         rte_flow_error_set(error, EINVAL,
2084                                            RTE_FLOW_ERROR_TYPE_ACTION,
2085                                            act, "Invalid queue ID for"
2086                                            " ethertype_filter.");
2087                         return -rte_errno;
2088                 }
2089         } else {
2090                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2091         }
2092
2093         /* Check if the next non-void item is END */
2094         index++;
2095         NEXT_ITEM_OF_ACTION(act, actions, index);
2096         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2097                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2098                                    act, "Not supported action.");
2099                 return -rte_errno;
2100         }
2101
2102         return 0;
2103 }
2104
2105 static int
2106 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2107                                  const struct rte_flow_attr *attr,
2108                                  const struct rte_flow_item pattern[],
2109                                  const struct rte_flow_action actions[],
2110                                  struct rte_flow_error *error,
2111                                  union i40e_filter_t *filter)
2112 {
2113         struct rte_eth_ethertype_filter *ethertype_filter =
2114                 &filter->ethertype_filter;
2115         int ret;
2116
2117         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2118                                                 ethertype_filter);
2119         if (ret)
2120                 return ret;
2121
2122         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2123                                                ethertype_filter);
2124         if (ret)
2125                 return ret;
2126
2127         ret = i40e_flow_parse_attr(attr, error);
2128         if (ret)
2129                 return ret;
2130
2131         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2132
2133         return ret;
2134 }
2135
2136 static int
2137 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2138                          const struct rte_flow_item_raw *raw_spec,
2139                          struct rte_flow_error *error)
2140 {
2141         if (!raw_spec->relative) {
2142                 rte_flow_error_set(error, EINVAL,
2143                                    RTE_FLOW_ERROR_TYPE_ITEM,
2144                                    item,
2145                                    "Relative should be 1.");
2146                 return -rte_errno;
2147         }
2148
2149         if (raw_spec->offset % sizeof(uint16_t)) {
2150                 rte_flow_error_set(error, EINVAL,
2151                                    RTE_FLOW_ERROR_TYPE_ITEM,
2152                                    item,
2153                                    "Offset should be even.");
2154                 return -rte_errno;
2155         }
2156
2157         if (raw_spec->search || raw_spec->limit) {
2158                 rte_flow_error_set(error, EINVAL,
2159                                    RTE_FLOW_ERROR_TYPE_ITEM,
2160                                    item,
2161                                    "search or limit is not supported.");
2162                 return -rte_errno;
2163         }
2164
2165         if (raw_spec->offset < 0) {
2166                 rte_flow_error_set(error, EINVAL,
2167                                    RTE_FLOW_ERROR_TYPE_ITEM,
2168                                    item,
2169                                    "Offset should be non-negative.");
2170                 return -rte_errno;
2171         }
2172         return 0;
2173 }
2174
2175 static int
2176 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2177                          struct i40e_fdir_flex_pit *flex_pit,
2178                          enum i40e_flxpld_layer_idx layer_idx,
2179                          uint8_t raw_id)
2180 {
2181         uint8_t field_idx;
2182
2183         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2184         /* Check if the configuration is conflicted */
2185         if (pf->fdir.flex_pit_flag[layer_idx] &&
2186             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2187              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2188              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2189                 return -1;
2190
2191         /* Check if the configuration exists. */
2192         if (pf->fdir.flex_pit_flag[layer_idx] &&
2193             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2194              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2195              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2196                 return 1;
2197
2198         pf->fdir.flex_set[field_idx].src_offset =
2199                 flex_pit->src_offset;
2200         pf->fdir.flex_set[field_idx].size =
2201                 flex_pit->size;
2202         pf->fdir.flex_set[field_idx].dst_offset =
2203                 flex_pit->dst_offset;
2204
2205         return 0;
2206 }
2207
2208 static int
2209 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2210                           enum i40e_filter_pctype pctype,
2211                           uint8_t *mask)
2212 {
2213         struct i40e_fdir_flex_mask flex_mask;
2214         uint16_t mask_tmp;
2215         uint8_t i, nb_bitmask = 0;
2216
2217         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2218         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2219                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2220                 if (mask_tmp) {
2221                         flex_mask.word_mask |=
2222                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2223                         if (mask_tmp != UINT16_MAX) {
2224                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2225                                 flex_mask.bitmask[nb_bitmask].offset =
2226                                         i / sizeof(uint16_t);
2227                                 nb_bitmask++;
2228                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2229                                         return -1;
2230                         }
2231                 }
2232         }
2233         flex_mask.nb_bitmask = nb_bitmask;
2234
2235         if (pf->fdir.flex_mask_flag[pctype] &&
2236             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2237                     sizeof(struct i40e_fdir_flex_mask))))
2238                 return -2;
2239         else if (pf->fdir.flex_mask_flag[pctype] &&
2240                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2241                           sizeof(struct i40e_fdir_flex_mask))))
2242                 return 1;
2243
2244         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2245                sizeof(struct i40e_fdir_flex_mask));
2246         return 0;
2247 }
2248
2249 static void
2250 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2251                             enum i40e_flxpld_layer_idx layer_idx,
2252                             uint8_t raw_id)
2253 {
2254         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2255         uint32_t flx_pit, flx_ort;
2256         uint8_t field_idx;
2257         uint16_t min_next_off = 0;  /* in words */
2258         uint8_t i;
2259
2260         if (raw_id) {
2261                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2262                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2263                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2264                 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2265         }
2266
2267         /* Set flex pit */
2268         for (i = 0; i < raw_id; i++) {
2269                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2270                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2271                                      pf->fdir.flex_set[field_idx].size,
2272                                      pf->fdir.flex_set[field_idx].dst_offset);
2273
2274                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2275                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2276                         pf->fdir.flex_set[field_idx].size;
2277         }
2278
2279         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2280                 /* set the non-used register obeying register's constrain */
2281                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2282                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2283                                      NONUSE_FLX_PIT_DEST_OFF);
2284                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2285                 min_next_off++;
2286         }
2287
2288         pf->fdir.flex_pit_flag[layer_idx] = 1;
2289 }
2290
2291 static void
2292 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2293                             enum i40e_filter_pctype pctype)
2294 {
2295         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2296         struct i40e_fdir_flex_mask *flex_mask;
2297         uint32_t flxinset, fd_mask;
2298         uint8_t i;
2299
2300         /* Set flex mask */
2301         flex_mask = &pf->fdir.flex_mask[pctype];
2302         flxinset = (flex_mask->word_mask <<
2303                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2304                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2305         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2306
2307         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2308                 fd_mask = (flex_mask->bitmask[i].mask <<
2309                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2310                         I40E_PRTQF_FD_MSK_MASK_MASK;
2311                 fd_mask |= ((flex_mask->bitmask[i].offset +
2312                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2313                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2314                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2315                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2316         }
2317
2318         pf->fdir.flex_mask_flag[pctype] = 1;
2319 }
2320
2321 static int
2322 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2323                          enum i40e_filter_pctype pctype,
2324                          uint64_t input_set)
2325 {
2326         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2327         uint64_t inset_reg = 0;
2328         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2329         int i, num;
2330
2331         /* Check if the input set is valid */
2332         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2333                                     input_set) != 0) {
2334                 PMD_DRV_LOG(ERR, "Invalid input set");
2335                 return -EINVAL;
2336         }
2337
2338         /* Check if the configuration is conflicted */
2339         if (pf->fdir.inset_flag[pctype] &&
2340             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2341                 return -1;
2342
2343         if (pf->fdir.inset_flag[pctype] &&
2344             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2345                 return 0;
2346
2347         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2348                                            I40E_INSET_MASK_NUM_REG);
2349         if (num < 0)
2350                 return -EINVAL;
2351
2352         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2353
2354         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2355                              (uint32_t)(inset_reg & UINT32_MAX));
2356         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2357                              (uint32_t)((inset_reg >>
2358                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2359
2360         for (i = 0; i < num; i++)
2361                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2362                                      mask_reg[i]);
2363
2364         /*clear unused mask registers of the pctype */
2365         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2366                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2367         I40E_WRITE_FLUSH(hw);
2368
2369         pf->fdir.input_set[pctype] = input_set;
2370         pf->fdir.inset_flag[pctype] = 1;
2371         return 0;
2372 }
2373
2374 static uint8_t
2375 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2376                                 enum rte_flow_item_type item_type,
2377                                 struct i40e_fdir_filter_conf *filter)
2378 {
2379         struct i40e_customized_pctype *cus_pctype = NULL;
2380
2381         switch (item_type) {
2382         case RTE_FLOW_ITEM_TYPE_GTPC:
2383                 cus_pctype = i40e_find_customized_pctype(pf,
2384                                                          I40E_CUSTOMIZED_GTPC);
2385                 break;
2386         case RTE_FLOW_ITEM_TYPE_GTPU:
2387                 if (!filter->input.flow_ext.inner_ip)
2388                         cus_pctype = i40e_find_customized_pctype(pf,
2389                                                          I40E_CUSTOMIZED_GTPU);
2390                 else if (filter->input.flow_ext.iip_type ==
2391                          I40E_FDIR_IPTYPE_IPV4)
2392                         cus_pctype = i40e_find_customized_pctype(pf,
2393                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2394                 else if (filter->input.flow_ext.iip_type ==
2395                          I40E_FDIR_IPTYPE_IPV6)
2396                         cus_pctype = i40e_find_customized_pctype(pf,
2397                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2398                 break;
2399         default:
2400                 PMD_DRV_LOG(ERR, "Unsupported item type");
2401                 break;
2402         }
2403
2404         if (cus_pctype && cus_pctype->valid)
2405                 return cus_pctype->pctype;
2406
2407         return I40E_FILTER_PCTYPE_INVALID;
2408 }
2409
2410 /* 1. Last in item should be NULL as range is not supported.
2411  * 2. Supported patterns: refer to array i40e_supported_patterns.
2412  * 3. Default supported flow type and input set: refer to array
2413  *    valid_fdir_inset_table in i40e_ethdev.c.
2414  * 4. Mask of fields which need to be matched should be
2415  *    filled with 1.
2416  * 5. Mask of fields which needn't to be matched should be
2417  *    filled with 0.
2418  * 6. GTP profile supports GTPv1 only.
2419  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2420  */
2421 static int
2422 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2423                              const struct rte_flow_attr *attr,
2424                              const struct rte_flow_item *pattern,
2425                              struct rte_flow_error *error,
2426                              struct i40e_fdir_filter_conf *filter)
2427 {
2428         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2429         const struct rte_flow_item *item = pattern;
2430         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2431         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2432         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2433         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2434         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2435         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2436         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2437         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2438         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2439         const struct rte_flow_item_vf *vf_spec;
2440
2441         uint8_t pctype = 0;
2442         uint64_t input_set = I40E_INSET_NONE;
2443         uint16_t frag_off;
2444         enum rte_flow_item_type item_type;
2445         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2446         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2447         uint32_t i, j;
2448         uint8_t  ipv6_addr_mask[16] = {
2449                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2450                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2451         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2452         uint8_t raw_id = 0;
2453         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2454         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2455         struct i40e_fdir_flex_pit flex_pit;
2456         uint8_t next_dst_off = 0;
2457         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2458         uint16_t flex_size;
2459         bool cfg_flex_pit = true;
2460         bool cfg_flex_msk = true;
2461         uint16_t outer_tpid;
2462         uint16_t ether_type;
2463         uint32_t vtc_flow_cpu;
2464         bool outer_ip = true;
2465         int ret;
2466
2467         memset(off_arr, 0, sizeof(off_arr));
2468         memset(len_arr, 0, sizeof(len_arr));
2469         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2470         outer_tpid = i40e_get_outer_vlan(dev);
2471         filter->input.flow_ext.customized_pctype = false;
2472         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2473                 if (item->last) {
2474                         rte_flow_error_set(error, EINVAL,
2475                                            RTE_FLOW_ERROR_TYPE_ITEM,
2476                                            item,
2477                                            "Not support range");
2478                         return -rte_errno;
2479                 }
2480                 item_type = item->type;
2481                 switch (item_type) {
2482                 case RTE_FLOW_ITEM_TYPE_ETH:
2483                         eth_spec = item->spec;
2484                         eth_mask = item->mask;
2485
2486                         if (eth_spec && eth_mask) {
2487                                 if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2488                                     !rte_is_zero_ether_addr(&eth_mask->dst)) {
2489                                         rte_flow_error_set(error, EINVAL,
2490                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2491                                                       item,
2492                                                       "Invalid MAC_addr mask.");
2493                                         return -rte_errno;
2494                                 }
2495                         }
2496                         if (eth_spec && eth_mask && eth_mask->type) {
2497                                 enum rte_flow_item_type next = (item + 1)->type;
2498
2499                                 if (eth_mask->type != RTE_BE16(0xffff)) {
2500                                         rte_flow_error_set(error, EINVAL,
2501                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2502                                                       item,
2503                                                       "Invalid type mask.");
2504                                         return -rte_errno;
2505                                 }
2506
2507                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2508
2509                                 if (next == RTE_FLOW_ITEM_TYPE_VLAN ||
2510                                     ether_type == RTE_ETHER_TYPE_IPV4 ||
2511                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2512                                     ether_type == RTE_ETHER_TYPE_ARP ||
2513                                     ether_type == outer_tpid) {
2514                                         rte_flow_error_set(error, EINVAL,
2515                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2516                                                      item,
2517                                                      "Unsupported ether_type.");
2518                                         return -rte_errno;
2519                                 }
2520                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2521                                 filter->input.flow.l2_flow.ether_type =
2522                                         eth_spec->type;
2523                         }
2524
2525                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2526                         layer_idx = I40E_FLXPLD_L2_IDX;
2527
2528                         break;
2529                 case RTE_FLOW_ITEM_TYPE_VLAN:
2530                         vlan_spec = item->spec;
2531                         vlan_mask = item->mask;
2532
2533                         RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2534                         if (vlan_spec && vlan_mask) {
2535                                 if (vlan_mask->tci ==
2536                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2537                                         input_set |= I40E_INSET_VLAN_INNER;
2538                                         filter->input.flow_ext.vlan_tci =
2539                                                 vlan_spec->tci;
2540                                 }
2541                         }
2542                         if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2543                                 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2544                                         rte_flow_error_set(error, EINVAL,
2545                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2546                                                       item,
2547                                                       "Invalid inner_type"
2548                                                       " mask.");
2549                                         return -rte_errno;
2550                                 }
2551
2552                                 ether_type =
2553                                         rte_be_to_cpu_16(vlan_spec->inner_type);
2554
2555                                 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
2556                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2557                                     ether_type == RTE_ETHER_TYPE_ARP ||
2558                                     ether_type == outer_tpid) {
2559                                         rte_flow_error_set(error, EINVAL,
2560                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2561                                                      item,
2562                                                      "Unsupported inner_type.");
2563                                         return -rte_errno;
2564                                 }
2565                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2566                                 filter->input.flow.l2_flow.ether_type =
2567                                         vlan_spec->inner_type;
2568                         }
2569
2570                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2571                         layer_idx = I40E_FLXPLD_L2_IDX;
2572
2573                         break;
2574                 case RTE_FLOW_ITEM_TYPE_IPV4:
2575                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2576                         ipv4_spec = item->spec;
2577                         ipv4_mask = item->mask;
2578                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2579                         layer_idx = I40E_FLXPLD_L3_IDX;
2580
2581                         if (ipv4_spec && ipv4_mask && outer_ip) {
2582                                 /* Check IPv4 mask and update input set */
2583                                 if (ipv4_mask->hdr.version_ihl ||
2584                                     ipv4_mask->hdr.total_length ||
2585                                     ipv4_mask->hdr.packet_id ||
2586                                     ipv4_mask->hdr.fragment_offset ||
2587                                     ipv4_mask->hdr.hdr_checksum) {
2588                                         rte_flow_error_set(error, EINVAL,
2589                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2590                                                    item,
2591                                                    "Invalid IPv4 mask.");
2592                                         return -rte_errno;
2593                                 }
2594
2595                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2596                                         input_set |= I40E_INSET_IPV4_SRC;
2597                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2598                                         input_set |= I40E_INSET_IPV4_DST;
2599                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2600                                         input_set |= I40E_INSET_IPV4_TOS;
2601                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2602                                         input_set |= I40E_INSET_IPV4_TTL;
2603                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2604                                         input_set |= I40E_INSET_IPV4_PROTO;
2605
2606                                 /* Check if it is fragment. */
2607                                 frag_off = ipv4_spec->hdr.fragment_offset;
2608                                 frag_off = rte_be_to_cpu_16(frag_off);
2609                                 if (frag_off & RTE_IPV4_HDR_OFFSET_MASK ||
2610                                     frag_off & RTE_IPV4_HDR_MF_FLAG)
2611                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2612
2613                                 /* Get the filter info */
2614                                 filter->input.flow.ip4_flow.proto =
2615                                         ipv4_spec->hdr.next_proto_id;
2616                                 filter->input.flow.ip4_flow.tos =
2617                                         ipv4_spec->hdr.type_of_service;
2618                                 filter->input.flow.ip4_flow.ttl =
2619                                         ipv4_spec->hdr.time_to_live;
2620                                 filter->input.flow.ip4_flow.src_ip =
2621                                         ipv4_spec->hdr.src_addr;
2622                                 filter->input.flow.ip4_flow.dst_ip =
2623                                         ipv4_spec->hdr.dst_addr;
2624                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2625                                 filter->input.flow_ext.inner_ip = true;
2626                                 filter->input.flow_ext.iip_type =
2627                                         I40E_FDIR_IPTYPE_IPV4;
2628                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2629                                 rte_flow_error_set(error, EINVAL,
2630                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2631                                                    item,
2632                                                    "Invalid inner IPv4 mask.");
2633                                 return -rte_errno;
2634                         }
2635
2636                         if (outer_ip)
2637                                 outer_ip = false;
2638
2639                         break;
2640                 case RTE_FLOW_ITEM_TYPE_IPV6:
2641                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2642                         ipv6_spec = item->spec;
2643                         ipv6_mask = item->mask;
2644                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2645                         layer_idx = I40E_FLXPLD_L3_IDX;
2646
2647                         if (ipv6_spec && ipv6_mask && outer_ip) {
2648                                 /* Check IPv6 mask and update input set */
2649                                 if (ipv6_mask->hdr.payload_len) {
2650                                         rte_flow_error_set(error, EINVAL,
2651                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2652                                                    item,
2653                                                    "Invalid IPv6 mask");
2654                                         return -rte_errno;
2655                                 }
2656
2657                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2658                                             ipv6_addr_mask,
2659                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2660                                         input_set |= I40E_INSET_IPV6_SRC;
2661                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2662                                             ipv6_addr_mask,
2663                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2664                                         input_set |= I40E_INSET_IPV6_DST;
2665
2666                                 if ((ipv6_mask->hdr.vtc_flow &
2667                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2668                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2669                                         input_set |= I40E_INSET_IPV6_TC;
2670                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2671                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2672                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2673                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2674
2675                                 /* Get filter info */
2676                                 vtc_flow_cpu =
2677                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2678                                 filter->input.flow.ipv6_flow.tc =
2679                                         (uint8_t)(vtc_flow_cpu >>
2680                                                   I40E_FDIR_IPv6_TC_OFFSET);
2681                                 filter->input.flow.ipv6_flow.proto =
2682                                         ipv6_spec->hdr.proto;
2683                                 filter->input.flow.ipv6_flow.hop_limits =
2684                                         ipv6_spec->hdr.hop_limits;
2685
2686                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2687                                            ipv6_spec->hdr.src_addr, 16);
2688                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2689                                            ipv6_spec->hdr.dst_addr, 16);
2690
2691                                 /* Check if it is fragment. */
2692                                 if (ipv6_spec->hdr.proto ==
2693                                     I40E_IPV6_FRAG_HEADER)
2694                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2695                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2696                                 filter->input.flow_ext.inner_ip = true;
2697                                 filter->input.flow_ext.iip_type =
2698                                         I40E_FDIR_IPTYPE_IPV6;
2699                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2700                                 rte_flow_error_set(error, EINVAL,
2701                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2702                                                    item,
2703                                                    "Invalid inner IPv6 mask");
2704                                 return -rte_errno;
2705                         }
2706
2707                         if (outer_ip)
2708                                 outer_ip = false;
2709                         break;
2710                 case RTE_FLOW_ITEM_TYPE_TCP:
2711                         tcp_spec = item->spec;
2712                         tcp_mask = item->mask;
2713
2714                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2715                                 pctype =
2716                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2717                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2718                                 pctype =
2719                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2720                         if (tcp_spec && tcp_mask) {
2721                                 /* Check TCP mask and update input set */
2722                                 if (tcp_mask->hdr.sent_seq ||
2723                                     tcp_mask->hdr.recv_ack ||
2724                                     tcp_mask->hdr.data_off ||
2725                                     tcp_mask->hdr.tcp_flags ||
2726                                     tcp_mask->hdr.rx_win ||
2727                                     tcp_mask->hdr.cksum ||
2728                                     tcp_mask->hdr.tcp_urp) {
2729                                         rte_flow_error_set(error, EINVAL,
2730                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2731                                                    item,
2732                                                    "Invalid TCP mask");
2733                                         return -rte_errno;
2734                                 }
2735
2736                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2737                                         input_set |= I40E_INSET_SRC_PORT;
2738                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2739                                         input_set |= I40E_INSET_DST_PORT;
2740
2741                                 /* Get filter info */
2742                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2743                                         filter->input.flow.tcp4_flow.src_port =
2744                                                 tcp_spec->hdr.src_port;
2745                                         filter->input.flow.tcp4_flow.dst_port =
2746                                                 tcp_spec->hdr.dst_port;
2747                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2748                                         filter->input.flow.tcp6_flow.src_port =
2749                                                 tcp_spec->hdr.src_port;
2750                                         filter->input.flow.tcp6_flow.dst_port =
2751                                                 tcp_spec->hdr.dst_port;
2752                                 }
2753                         }
2754
2755                         layer_idx = I40E_FLXPLD_L4_IDX;
2756
2757                         break;
2758                 case RTE_FLOW_ITEM_TYPE_UDP:
2759                         udp_spec = item->spec;
2760                         udp_mask = item->mask;
2761
2762                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2763                                 pctype =
2764                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2765                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2766                                 pctype =
2767                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2768
2769                         if (udp_spec && udp_mask) {
2770                                 /* Check UDP mask and update input set*/
2771                                 if (udp_mask->hdr.dgram_len ||
2772                                     udp_mask->hdr.dgram_cksum) {
2773                                         rte_flow_error_set(error, EINVAL,
2774                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2775                                                    item,
2776                                                    "Invalid UDP mask");
2777                                         return -rte_errno;
2778                                 }
2779
2780                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2781                                         input_set |= I40E_INSET_SRC_PORT;
2782                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2783                                         input_set |= I40E_INSET_DST_PORT;
2784
2785                                 /* Get filter info */
2786                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2787                                         filter->input.flow.udp4_flow.src_port =
2788                                                 udp_spec->hdr.src_port;
2789                                         filter->input.flow.udp4_flow.dst_port =
2790                                                 udp_spec->hdr.dst_port;
2791                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2792                                         filter->input.flow.udp6_flow.src_port =
2793                                                 udp_spec->hdr.src_port;
2794                                         filter->input.flow.udp6_flow.dst_port =
2795                                                 udp_spec->hdr.dst_port;
2796                                 }
2797                         }
2798
2799                         layer_idx = I40E_FLXPLD_L4_IDX;
2800
2801                         break;
2802                 case RTE_FLOW_ITEM_TYPE_GTPC:
2803                 case RTE_FLOW_ITEM_TYPE_GTPU:
2804                         if (!pf->gtp_support) {
2805                                 rte_flow_error_set(error, EINVAL,
2806                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2807                                                    item,
2808                                                    "Unsupported protocol");
2809                                 return -rte_errno;
2810                         }
2811
2812                         gtp_spec = item->spec;
2813                         gtp_mask = item->mask;
2814
2815                         if (gtp_spec && gtp_mask) {
2816                                 if (gtp_mask->v_pt_rsv_flags ||
2817                                     gtp_mask->msg_type ||
2818                                     gtp_mask->msg_len ||
2819                                     gtp_mask->teid != UINT32_MAX) {
2820                                         rte_flow_error_set(error, EINVAL,
2821                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2822                                                    item,
2823                                                    "Invalid GTP mask");
2824                                         return -rte_errno;
2825                                 }
2826
2827                                 filter->input.flow.gtp_flow.teid =
2828                                         gtp_spec->teid;
2829                                 filter->input.flow_ext.customized_pctype = true;
2830                                 cus_proto = item_type;
2831                         }
2832                         break;
2833                 case RTE_FLOW_ITEM_TYPE_SCTP:
2834                         sctp_spec = item->spec;
2835                         sctp_mask = item->mask;
2836
2837                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2838                                 pctype =
2839                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2840                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2841                                 pctype =
2842                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2843
2844                         if (sctp_spec && sctp_mask) {
2845                                 /* Check SCTP mask and update input set */
2846                                 if (sctp_mask->hdr.cksum) {
2847                                         rte_flow_error_set(error, EINVAL,
2848                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2849                                                    item,
2850                                                    "Invalid UDP mask");
2851                                         return -rte_errno;
2852                                 }
2853
2854                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2855                                         input_set |= I40E_INSET_SRC_PORT;
2856                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2857                                         input_set |= I40E_INSET_DST_PORT;
2858                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2859                                         input_set |= I40E_INSET_SCTP_VT;
2860
2861                                 /* Get filter info */
2862                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2863                                         filter->input.flow.sctp4_flow.src_port =
2864                                                 sctp_spec->hdr.src_port;
2865                                         filter->input.flow.sctp4_flow.dst_port =
2866                                                 sctp_spec->hdr.dst_port;
2867                                         filter->input.flow.sctp4_flow.verify_tag
2868                                                 = sctp_spec->hdr.tag;
2869                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2870                                         filter->input.flow.sctp6_flow.src_port =
2871                                                 sctp_spec->hdr.src_port;
2872                                         filter->input.flow.sctp6_flow.dst_port =
2873                                                 sctp_spec->hdr.dst_port;
2874                                         filter->input.flow.sctp6_flow.verify_tag
2875                                                 = sctp_spec->hdr.tag;
2876                                 }
2877                         }
2878
2879                         layer_idx = I40E_FLXPLD_L4_IDX;
2880
2881                         break;
2882                 case RTE_FLOW_ITEM_TYPE_RAW:
2883                         raw_spec = item->spec;
2884                         raw_mask = item->mask;
2885
2886                         if (!raw_spec || !raw_mask) {
2887                                 rte_flow_error_set(error, EINVAL,
2888                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2889                                                    item,
2890                                                    "NULL RAW spec/mask");
2891                                 return -rte_errno;
2892                         }
2893
2894                         if (pf->support_multi_driver) {
2895                                 rte_flow_error_set(error, ENOTSUP,
2896                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2897                                                    item,
2898                                                    "Unsupported flexible payload.");
2899                                 return -rte_errno;
2900                         }
2901
2902                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2903                         if (ret < 0)
2904                                 return ret;
2905
2906                         off_arr[raw_id] = raw_spec->offset;
2907                         len_arr[raw_id] = raw_spec->length;
2908
2909                         flex_size = 0;
2910                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2911                         flex_pit.size =
2912                                 raw_spec->length / sizeof(uint16_t);
2913                         flex_pit.dst_offset =
2914                                 next_dst_off / sizeof(uint16_t);
2915
2916                         for (i = 0; i <= raw_id; i++) {
2917                                 if (i == raw_id)
2918                                         flex_pit.src_offset +=
2919                                                 raw_spec->offset /
2920                                                 sizeof(uint16_t);
2921                                 else
2922                                         flex_pit.src_offset +=
2923                                                 (off_arr[i] + len_arr[i]) /
2924                                                 sizeof(uint16_t);
2925                                 flex_size += len_arr[i];
2926                         }
2927                         if (((flex_pit.src_offset + flex_pit.size) >=
2928                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2929                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2930                                 rte_flow_error_set(error, EINVAL,
2931                                            RTE_FLOW_ERROR_TYPE_ITEM,
2932                                            item,
2933                                            "Exceeds maxmial payload limit.");
2934                                 return -rte_errno;
2935                         }
2936
2937                         /* Store flex pit to SW */
2938                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2939                                                        layer_idx, raw_id);
2940                         if (ret < 0) {
2941                                 rte_flow_error_set(error, EINVAL,
2942                                    RTE_FLOW_ERROR_TYPE_ITEM,
2943                                    item,
2944                                    "Conflict with the first flexible rule.");
2945                                 return -rte_errno;
2946                         } else if (ret > 0)
2947                                 cfg_flex_pit = false;
2948
2949                         for (i = 0; i < raw_spec->length; i++) {
2950                                 j = i + next_dst_off;
2951                                 filter->input.flow_ext.flexbytes[j] =
2952                                         raw_spec->pattern[i];
2953                                 flex_mask[j] = raw_mask->pattern[i];
2954                         }
2955
2956                         next_dst_off += raw_spec->length;
2957                         raw_id++;
2958                         break;
2959                 case RTE_FLOW_ITEM_TYPE_VF:
2960                         vf_spec = item->spec;
2961                         if (!attr->transfer) {
2962                                 rte_flow_error_set(error, ENOTSUP,
2963                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2964                                                    item,
2965                                                    "Matching VF traffic"
2966                                                    " without affecting it"
2967                                                    " (transfer attribute)"
2968                                                    " is unsupported");
2969                                 return -rte_errno;
2970                         }
2971                         filter->input.flow_ext.is_vf = 1;
2972                         filter->input.flow_ext.dst_id = vf_spec->id;
2973                         if (filter->input.flow_ext.is_vf &&
2974                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2975                                 rte_flow_error_set(error, EINVAL,
2976                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2977                                                    item,
2978                                                    "Invalid VF ID for FDIR.");
2979                                 return -rte_errno;
2980                         }
2981                         break;
2982                 default:
2983                         break;
2984                 }
2985         }
2986
2987         /* Get customized pctype value */
2988         if (filter->input.flow_ext.customized_pctype) {
2989                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2990                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2991                         rte_flow_error_set(error, EINVAL,
2992                                            RTE_FLOW_ERROR_TYPE_ITEM,
2993                                            item,
2994                                            "Unsupported pctype");
2995                         return -rte_errno;
2996                 }
2997         }
2998
2999         /* If customized pctype is not used, set fdir configuration.*/
3000         if (!filter->input.flow_ext.customized_pctype) {
3001                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3002                 if (ret == -1) {
3003                         rte_flow_error_set(error, EINVAL,
3004                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3005                                            "Conflict with the first rule's input set.");
3006                         return -rte_errno;
3007                 } else if (ret == -EINVAL) {
3008                         rte_flow_error_set(error, EINVAL,
3009                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3010                                            "Invalid pattern mask.");
3011                         return -rte_errno;
3012                 }
3013
3014                 /* Store flex mask to SW */
3015                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3016                 if (ret == -1) {
3017                         rte_flow_error_set(error, EINVAL,
3018                                            RTE_FLOW_ERROR_TYPE_ITEM,
3019                                            item,
3020                                            "Exceed maximal number of bitmasks");
3021                         return -rte_errno;
3022                 } else if (ret == -2) {
3023                         rte_flow_error_set(error, EINVAL,
3024                                            RTE_FLOW_ERROR_TYPE_ITEM,
3025                                            item,
3026                                            "Conflict with the first flexible rule");
3027                         return -rte_errno;
3028                 } else if (ret > 0)
3029                         cfg_flex_msk = false;
3030
3031                 if (cfg_flex_pit)
3032                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3033
3034                 if (cfg_flex_msk)
3035                         i40e_flow_set_fdir_flex_msk(pf, pctype);
3036         }
3037
3038         filter->input.pctype = pctype;
3039
3040         return 0;
3041 }
3042
3043 /* Parse to get the action info of a FDIR filter.
3044  * FDIR action supports QUEUE or (QUEUE + MARK).
3045  */
3046 static int
3047 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3048                             const struct rte_flow_action *actions,
3049                             struct rte_flow_error *error,
3050                             struct i40e_fdir_filter_conf *filter)
3051 {
3052         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3053         const struct rte_flow_action *act;
3054         const struct rte_flow_action_queue *act_q;
3055         const struct rte_flow_action_mark *mark_spec = NULL;
3056         uint32_t index = 0;
3057
3058         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3059         NEXT_ITEM_OF_ACTION(act, actions, index);
3060         switch (act->type) {
3061         case RTE_FLOW_ACTION_TYPE_QUEUE:
3062                 act_q = act->conf;
3063                 filter->action.rx_queue = act_q->index;
3064                 if ((!filter->input.flow_ext.is_vf &&
3065                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3066                     (filter->input.flow_ext.is_vf &&
3067                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3068                         rte_flow_error_set(error, EINVAL,
3069                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3070                                            "Invalid queue ID for FDIR.");
3071                         return -rte_errno;
3072                 }
3073                 filter->action.behavior = I40E_FDIR_ACCEPT;
3074                 break;
3075         case RTE_FLOW_ACTION_TYPE_DROP:
3076                 filter->action.behavior = I40E_FDIR_REJECT;
3077                 break;
3078         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3079                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3080                 break;
3081         case RTE_FLOW_ACTION_TYPE_MARK:
3082                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3083                 mark_spec = act->conf;
3084                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3085                 filter->soft_id = mark_spec->id;
3086         break;
3087         default:
3088                 rte_flow_error_set(error, EINVAL,
3089                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3090                                    "Invalid action.");
3091                 return -rte_errno;
3092         }
3093
3094         /* Check if the next non-void item is MARK or FLAG or END. */
3095         index++;
3096         NEXT_ITEM_OF_ACTION(act, actions, index);
3097         switch (act->type) {
3098         case RTE_FLOW_ACTION_TYPE_MARK:
3099                 if (!mark_spec) {
3100                         /* Double MARK actions requested */
3101                         rte_flow_error_set(error, EINVAL,
3102                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3103                            "Invalid action.");
3104                         return -rte_errno;
3105                 }
3106                 mark_spec = act->conf;
3107                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3108                 filter->soft_id = mark_spec->id;
3109                 break;
3110         case RTE_FLOW_ACTION_TYPE_FLAG:
3111                 if (!mark_spec) {
3112                         /* MARK + FLAG not supported */
3113                         rte_flow_error_set(error, EINVAL,
3114                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3115                                            "Invalid action.");
3116                         return -rte_errno;
3117                 }
3118                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3119                 break;
3120         case RTE_FLOW_ACTION_TYPE_RSS:
3121                 if (filter->action.behavior != I40E_FDIR_PASSTHRU) {
3122                         /* RSS filter won't be next if FDIR did not pass thru */
3123                         rte_flow_error_set(error, EINVAL,
3124                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3125                                            "Invalid action.");
3126                         return -rte_errno;
3127                 }
3128                 break;
3129         case RTE_FLOW_ACTION_TYPE_END:
3130                 return 0;
3131         default:
3132                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3133                                    act, "Invalid action.");
3134                 return -rte_errno;
3135         }
3136
3137         /* Check if the next non-void item is END */
3138         index++;
3139         NEXT_ITEM_OF_ACTION(act, actions, index);
3140         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3141                 rte_flow_error_set(error, EINVAL,
3142                                    RTE_FLOW_ERROR_TYPE_ACTION,
3143                                    act, "Invalid action.");
3144                 return -rte_errno;
3145         }
3146
3147         return 0;
3148 }
3149
3150 static int
3151 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3152                             const struct rte_flow_attr *attr,
3153                             const struct rte_flow_item pattern[],
3154                             const struct rte_flow_action actions[],
3155                             struct rte_flow_error *error,
3156                             union i40e_filter_t *filter)
3157 {
3158         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3159         struct i40e_fdir_filter_conf *fdir_filter =
3160                 &filter->fdir_filter;
3161         int ret;
3162
3163         ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3164                                            fdir_filter);
3165         if (ret)
3166                 return ret;
3167
3168         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3169         if (ret)
3170                 return ret;
3171
3172         ret = i40e_flow_parse_attr(attr, error);
3173         if (ret)
3174                 return ret;
3175
3176         cons_filter_type = RTE_ETH_FILTER_FDIR;
3177
3178         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT ||
3179                 pf->fdir.fdir_vsi == NULL) {
3180                 /* Enable fdir when fdir flow is added at first time. */
3181                 ret = i40e_fdir_setup(pf);
3182                 if (ret != I40E_SUCCESS) {
3183                         rte_flow_error_set(error, ENOTSUP,
3184                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3185                                            NULL, "Failed to setup fdir.");
3186                         return -rte_errno;
3187                 }
3188                 ret = i40e_fdir_configure(dev);
3189                 if (ret < 0) {
3190                         rte_flow_error_set(error, ENOTSUP,
3191                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3192                                            NULL, "Failed to configure fdir.");
3193                         goto err;
3194                 }
3195
3196                 dev->data->dev_conf.fdir_conf.mode = RTE_FDIR_MODE_PERFECT;
3197         }
3198
3199         return 0;
3200 err:
3201         i40e_fdir_teardown(pf);
3202         return -rte_errno;
3203 }
3204
3205 /* Parse to get the action info of a tunnel filter
3206  * Tunnel action only supports PF, VF and QUEUE.
3207  */
3208 static int
3209 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3210                               const struct rte_flow_action *actions,
3211                               struct rte_flow_error *error,
3212                               struct i40e_tunnel_filter_conf *filter)
3213 {
3214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3215         const struct rte_flow_action *act;
3216         const struct rte_flow_action_queue *act_q;
3217         const struct rte_flow_action_vf *act_vf;
3218         uint32_t index = 0;
3219
3220         /* Check if the first non-void action is PF or VF. */
3221         NEXT_ITEM_OF_ACTION(act, actions, index);
3222         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3223             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3224                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3225                                    act, "Not supported action.");
3226                 return -rte_errno;
3227         }
3228
3229         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3230                 act_vf = act->conf;
3231                 filter->vf_id = act_vf->id;
3232                 filter->is_to_vf = 1;
3233                 if (filter->vf_id >= pf->vf_num) {
3234                         rte_flow_error_set(error, EINVAL,
3235                                    RTE_FLOW_ERROR_TYPE_ACTION,
3236                                    act, "Invalid VF ID for tunnel filter");
3237                         return -rte_errno;
3238                 }
3239         }
3240
3241         /* Check if the next non-void item is QUEUE */
3242         index++;
3243         NEXT_ITEM_OF_ACTION(act, actions, index);
3244         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3245                 act_q = act->conf;
3246                 filter->queue_id = act_q->index;
3247                 if ((!filter->is_to_vf) &&
3248                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3249                         rte_flow_error_set(error, EINVAL,
3250                                    RTE_FLOW_ERROR_TYPE_ACTION,
3251                                    act, "Invalid queue ID for tunnel filter");
3252                         return -rte_errno;
3253                 } else if (filter->is_to_vf &&
3254                            (filter->queue_id >= pf->vf_nb_qps)) {
3255                         rte_flow_error_set(error, EINVAL,
3256                                    RTE_FLOW_ERROR_TYPE_ACTION,
3257                                    act, "Invalid queue ID for tunnel filter");
3258                         return -rte_errno;
3259                 }
3260         }
3261
3262         /* Check if the next non-void item is END */
3263         index++;
3264         NEXT_ITEM_OF_ACTION(act, actions, index);
3265         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3266                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3267                                    act, "Not supported action.");
3268                 return -rte_errno;
3269         }
3270
3271         return 0;
3272 }
3273
3274 static uint16_t i40e_supported_tunnel_filter_types[] = {
3275         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3276         ETH_TUNNEL_FILTER_IVLAN,
3277         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3278         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3279         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3280         ETH_TUNNEL_FILTER_IMAC,
3281         ETH_TUNNEL_FILTER_IMAC,
3282 };
3283
3284 static int
3285 i40e_check_tunnel_filter_type(uint8_t filter_type)
3286 {
3287         uint8_t i;
3288
3289         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3290                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3291                         return 0;
3292         }
3293
3294         return -1;
3295 }
3296
3297 /* 1. Last in item should be NULL as range is not supported.
3298  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3299  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3300  * 3. Mask of fields which need to be matched should be
3301  *    filled with 1.
3302  * 4. Mask of fields which needn't to be matched should be
3303  *    filled with 0.
3304  */
3305 static int
3306 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3307                               const struct rte_flow_item *pattern,
3308                               struct rte_flow_error *error,
3309                               struct i40e_tunnel_filter_conf *filter)
3310 {
3311         const struct rte_flow_item *item = pattern;
3312         const struct rte_flow_item_eth *eth_spec;
3313         const struct rte_flow_item_eth *eth_mask;
3314         const struct rte_flow_item_vxlan *vxlan_spec;
3315         const struct rte_flow_item_vxlan *vxlan_mask;
3316         const struct rte_flow_item_vlan *vlan_spec;
3317         const struct rte_flow_item_vlan *vlan_mask;
3318         uint8_t filter_type = 0;
3319         bool is_vni_masked = 0;
3320         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3321         enum rte_flow_item_type item_type;
3322         bool vxlan_flag = 0;
3323         uint32_t tenant_id_be = 0;
3324         int ret;
3325
3326         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3327                 if (item->last) {
3328                         rte_flow_error_set(error, EINVAL,
3329                                            RTE_FLOW_ERROR_TYPE_ITEM,
3330                                            item,
3331                                            "Not support range");
3332                         return -rte_errno;
3333                 }
3334                 item_type = item->type;
3335                 switch (item_type) {
3336                 case RTE_FLOW_ITEM_TYPE_ETH:
3337                         eth_spec = item->spec;
3338                         eth_mask = item->mask;
3339
3340                         /* Check if ETH item is used for place holder.
3341                          * If yes, both spec and mask should be NULL.
3342                          * If no, both spec and mask shouldn't be NULL.
3343                          */
3344                         if ((!eth_spec && eth_mask) ||
3345                             (eth_spec && !eth_mask)) {
3346                                 rte_flow_error_set(error, EINVAL,
3347                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3348                                                    item,
3349                                                    "Invalid ether spec/mask");
3350                                 return -rte_errno;
3351                         }
3352
3353                         if (eth_spec && eth_mask) {
3354                                 /* DST address of inner MAC shouldn't be masked.
3355                                  * SRC address of Inner MAC should be masked.
3356                                  */
3357                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3358                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3359                                     eth_mask->type) {
3360                                         rte_flow_error_set(error, EINVAL,
3361                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3362                                                    item,
3363                                                    "Invalid ether spec/mask");
3364                                         return -rte_errno;
3365                                 }
3366
3367                                 if (!vxlan_flag) {
3368                                         rte_memcpy(&filter->outer_mac,
3369                                                    &eth_spec->dst,
3370                                                    RTE_ETHER_ADDR_LEN);
3371                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3372                                 } else {
3373                                         rte_memcpy(&filter->inner_mac,
3374                                                    &eth_spec->dst,
3375                                                    RTE_ETHER_ADDR_LEN);
3376                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3377                                 }
3378                         }
3379                         break;
3380                 case RTE_FLOW_ITEM_TYPE_VLAN:
3381                         vlan_spec = item->spec;
3382                         vlan_mask = item->mask;
3383                         if (!(vlan_spec && vlan_mask) ||
3384                             vlan_mask->inner_type) {
3385                                 rte_flow_error_set(error, EINVAL,
3386                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3387                                                    item,
3388                                                    "Invalid vlan item");
3389                                 return -rte_errno;
3390                         }
3391
3392                         if (vlan_spec && vlan_mask) {
3393                                 if (vlan_mask->tci ==
3394                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3395                                         filter->inner_vlan =
3396                                               rte_be_to_cpu_16(vlan_spec->tci) &
3397                                               I40E_TCI_MASK;
3398                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3399                         }
3400                         break;
3401                 case RTE_FLOW_ITEM_TYPE_IPV4:
3402                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3403                         /* IPv4 is used to describe protocol,
3404                          * spec and mask should be NULL.
3405                          */
3406                         if (item->spec || item->mask) {
3407                                 rte_flow_error_set(error, EINVAL,
3408                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3409                                                    item,
3410                                                    "Invalid IPv4 item");
3411                                 return -rte_errno;
3412                         }
3413                         break;
3414                 case RTE_FLOW_ITEM_TYPE_IPV6:
3415                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3416                         /* IPv6 is used to describe protocol,
3417                          * spec and mask should be NULL.
3418                          */
3419                         if (item->spec || item->mask) {
3420                                 rte_flow_error_set(error, EINVAL,
3421                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3422                                                    item,
3423                                                    "Invalid IPv6 item");
3424                                 return -rte_errno;
3425                         }
3426                         break;
3427                 case RTE_FLOW_ITEM_TYPE_UDP:
3428                         /* UDP is used to describe protocol,
3429                          * spec and mask should be NULL.
3430                          */
3431                         if (item->spec || item->mask) {
3432                                 rte_flow_error_set(error, EINVAL,
3433                                            RTE_FLOW_ERROR_TYPE_ITEM,
3434                                            item,
3435                                            "Invalid UDP item");
3436                                 return -rte_errno;
3437                         }
3438                         break;
3439                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3440                         vxlan_spec = item->spec;
3441                         vxlan_mask = item->mask;
3442                         /* Check if VXLAN item is used to describe protocol.
3443                          * If yes, both spec and mask should be NULL.
3444                          * If no, both spec and mask shouldn't be NULL.
3445                          */
3446                         if ((!vxlan_spec && vxlan_mask) ||
3447                             (vxlan_spec && !vxlan_mask)) {
3448                                 rte_flow_error_set(error, EINVAL,
3449                                            RTE_FLOW_ERROR_TYPE_ITEM,
3450                                            item,
3451                                            "Invalid VXLAN item");
3452                                 return -rte_errno;
3453                         }
3454
3455                         /* Check if VNI is masked. */
3456                         if (vxlan_spec && vxlan_mask) {
3457                                 is_vni_masked =
3458                                         !!memcmp(vxlan_mask->vni, vni_mask,
3459                                                  RTE_DIM(vni_mask));
3460                                 if (is_vni_masked) {
3461                                         rte_flow_error_set(error, EINVAL,
3462                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3463                                                    item,
3464                                                    "Invalid VNI mask");
3465                                         return -rte_errno;
3466                                 }
3467
3468                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3469                                            vxlan_spec->vni, 3);
3470                                 filter->tenant_id =
3471                                         rte_be_to_cpu_32(tenant_id_be);
3472                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3473                         }
3474
3475                         vxlan_flag = 1;
3476                         break;
3477                 default:
3478                         break;
3479                 }
3480         }
3481
3482         ret = i40e_check_tunnel_filter_type(filter_type);
3483         if (ret < 0) {
3484                 rte_flow_error_set(error, EINVAL,
3485                                    RTE_FLOW_ERROR_TYPE_ITEM,
3486                                    NULL,
3487                                    "Invalid filter type");
3488                 return -rte_errno;
3489         }
3490         filter->filter_type = filter_type;
3491
3492         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3493
3494         return 0;
3495 }
3496
3497 static int
3498 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3499                              const struct rte_flow_attr *attr,
3500                              const struct rte_flow_item pattern[],
3501                              const struct rte_flow_action actions[],
3502                              struct rte_flow_error *error,
3503                              union i40e_filter_t *filter)
3504 {
3505         struct i40e_tunnel_filter_conf *tunnel_filter =
3506                 &filter->consistent_tunnel_filter;
3507         int ret;
3508
3509         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3510                                             error, tunnel_filter);
3511         if (ret)
3512                 return ret;
3513
3514         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3515         if (ret)
3516                 return ret;
3517
3518         ret = i40e_flow_parse_attr(attr, error);
3519         if (ret)
3520                 return ret;
3521
3522         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3523
3524         return ret;
3525 }
3526
3527 /* 1. Last in item should be NULL as range is not supported.
3528  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3529  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3530  * 3. Mask of fields which need to be matched should be
3531  *    filled with 1.
3532  * 4. Mask of fields which needn't to be matched should be
3533  *    filled with 0.
3534  */
3535 static int
3536 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3537                               const struct rte_flow_item *pattern,
3538                               struct rte_flow_error *error,
3539                               struct i40e_tunnel_filter_conf *filter)
3540 {
3541         const struct rte_flow_item *item = pattern;
3542         const struct rte_flow_item_eth *eth_spec;
3543         const struct rte_flow_item_eth *eth_mask;
3544         const struct rte_flow_item_nvgre *nvgre_spec;
3545         const struct rte_flow_item_nvgre *nvgre_mask;
3546         const struct rte_flow_item_vlan *vlan_spec;
3547         const struct rte_flow_item_vlan *vlan_mask;
3548         enum rte_flow_item_type item_type;
3549         uint8_t filter_type = 0;
3550         bool is_tni_masked = 0;
3551         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3552         bool nvgre_flag = 0;
3553         uint32_t tenant_id_be = 0;
3554         int ret;
3555
3556         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3557                 if (item->last) {
3558                         rte_flow_error_set(error, EINVAL,
3559                                            RTE_FLOW_ERROR_TYPE_ITEM,
3560                                            item,
3561                                            "Not support range");
3562                         return -rte_errno;
3563                 }
3564                 item_type = item->type;
3565                 switch (item_type) {
3566                 case RTE_FLOW_ITEM_TYPE_ETH:
3567                         eth_spec = item->spec;
3568                         eth_mask = item->mask;
3569
3570                         /* Check if ETH item is used for place holder.
3571                          * If yes, both spec and mask should be NULL.
3572                          * If no, both spec and mask shouldn't be NULL.
3573                          */
3574                         if ((!eth_spec && eth_mask) ||
3575                             (eth_spec && !eth_mask)) {
3576                                 rte_flow_error_set(error, EINVAL,
3577                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3578                                                    item,
3579                                                    "Invalid ether spec/mask");
3580                                 return -rte_errno;
3581                         }
3582
3583                         if (eth_spec && eth_mask) {
3584                                 /* DST address of inner MAC shouldn't be masked.
3585                                  * SRC address of Inner MAC should be masked.
3586                                  */
3587                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3588                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3589                                     eth_mask->type) {
3590                                         rte_flow_error_set(error, EINVAL,
3591                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3592                                                    item,
3593                                                    "Invalid ether spec/mask");
3594                                         return -rte_errno;
3595                                 }
3596
3597                                 if (!nvgre_flag) {
3598                                         rte_memcpy(&filter->outer_mac,
3599                                                    &eth_spec->dst,
3600                                                    RTE_ETHER_ADDR_LEN);
3601                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3602                                 } else {
3603                                         rte_memcpy(&filter->inner_mac,
3604                                                    &eth_spec->dst,
3605                                                    RTE_ETHER_ADDR_LEN);
3606                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3607                                 }
3608                         }
3609
3610                         break;
3611                 case RTE_FLOW_ITEM_TYPE_VLAN:
3612                         vlan_spec = item->spec;
3613                         vlan_mask = item->mask;
3614                         if (!(vlan_spec && vlan_mask) ||
3615                             vlan_mask->inner_type) {
3616                                 rte_flow_error_set(error, EINVAL,
3617                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3618                                                    item,
3619                                                    "Invalid vlan item");
3620                                 return -rte_errno;
3621                         }
3622
3623                         if (vlan_spec && vlan_mask) {
3624                                 if (vlan_mask->tci ==
3625                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3626                                         filter->inner_vlan =
3627                                               rte_be_to_cpu_16(vlan_spec->tci) &
3628                                               I40E_TCI_MASK;
3629                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3630                         }
3631                         break;
3632                 case RTE_FLOW_ITEM_TYPE_IPV4:
3633                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3634                         /* IPv4 is used to describe protocol,
3635                          * spec and mask should be NULL.
3636                          */
3637                         if (item->spec || item->mask) {
3638                                 rte_flow_error_set(error, EINVAL,
3639                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3640                                                    item,
3641                                                    "Invalid IPv4 item");
3642                                 return -rte_errno;
3643                         }
3644                         break;
3645                 case RTE_FLOW_ITEM_TYPE_IPV6:
3646                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3647                         /* IPv6 is used to describe protocol,
3648                          * spec and mask should be NULL.
3649                          */
3650                         if (item->spec || item->mask) {
3651                                 rte_flow_error_set(error, EINVAL,
3652                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3653                                                    item,
3654                                                    "Invalid IPv6 item");
3655                                 return -rte_errno;
3656                         }
3657                         break;
3658                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3659                         nvgre_spec = item->spec;
3660                         nvgre_mask = item->mask;
3661                         /* Check if NVGRE item is used to describe protocol.
3662                          * If yes, both spec and mask should be NULL.
3663                          * If no, both spec and mask shouldn't be NULL.
3664                          */
3665                         if ((!nvgre_spec && nvgre_mask) ||
3666                             (nvgre_spec && !nvgre_mask)) {
3667                                 rte_flow_error_set(error, EINVAL,
3668                                            RTE_FLOW_ERROR_TYPE_ITEM,
3669                                            item,
3670                                            "Invalid NVGRE item");
3671                                 return -rte_errno;
3672                         }
3673
3674                         if (nvgre_spec && nvgre_mask) {
3675                                 is_tni_masked =
3676                                         !!memcmp(nvgre_mask->tni, tni_mask,
3677                                                  RTE_DIM(tni_mask));
3678                                 if (is_tni_masked) {
3679                                         rte_flow_error_set(error, EINVAL,
3680                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3681                                                        item,
3682                                                        "Invalid TNI mask");
3683                                         return -rte_errno;
3684                                 }
3685                                 if (nvgre_mask->protocol &&
3686                                         nvgre_mask->protocol != 0xFFFF) {
3687                                         rte_flow_error_set(error, EINVAL,
3688                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3689                                                 item,
3690                                                 "Invalid NVGRE item");
3691                                         return -rte_errno;
3692                                 }
3693                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3694                                         nvgre_mask->c_k_s_rsvd0_ver !=
3695                                         rte_cpu_to_be_16(0xFFFF)) {
3696                                         rte_flow_error_set(error, EINVAL,
3697                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3698                                                    item,
3699                                                    "Invalid NVGRE item");
3700                                         return -rte_errno;
3701                                 }
3702                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3703                                         rte_cpu_to_be_16(0x2000) &&
3704                                         nvgre_mask->c_k_s_rsvd0_ver) {
3705                                         rte_flow_error_set(error, EINVAL,
3706                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3707                                                    item,
3708                                                    "Invalid NVGRE item");
3709                                         return -rte_errno;
3710                                 }
3711                                 if (nvgre_mask->protocol &&
3712                                         nvgre_spec->protocol !=
3713                                         rte_cpu_to_be_16(0x6558)) {
3714                                         rte_flow_error_set(error, EINVAL,
3715                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3716                                                    item,
3717                                                    "Invalid NVGRE item");
3718                                         return -rte_errno;
3719                                 }
3720                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3721                                            nvgre_spec->tni, 3);
3722                                 filter->tenant_id =
3723                                         rte_be_to_cpu_32(tenant_id_be);
3724                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3725                         }
3726
3727                         nvgre_flag = 1;
3728                         break;
3729                 default:
3730                         break;
3731                 }
3732         }
3733
3734         ret = i40e_check_tunnel_filter_type(filter_type);
3735         if (ret < 0) {
3736                 rte_flow_error_set(error, EINVAL,
3737                                    RTE_FLOW_ERROR_TYPE_ITEM,
3738                                    NULL,
3739                                    "Invalid filter type");
3740                 return -rte_errno;
3741         }
3742         filter->filter_type = filter_type;
3743
3744         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3745
3746         return 0;
3747 }
3748
3749 static int
3750 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3751                              const struct rte_flow_attr *attr,
3752                              const struct rte_flow_item pattern[],
3753                              const struct rte_flow_action actions[],
3754                              struct rte_flow_error *error,
3755                              union i40e_filter_t *filter)
3756 {
3757         struct i40e_tunnel_filter_conf *tunnel_filter =
3758                 &filter->consistent_tunnel_filter;
3759         int ret;
3760
3761         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3762                                             error, tunnel_filter);
3763         if (ret)
3764                 return ret;
3765
3766         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3767         if (ret)
3768                 return ret;
3769
3770         ret = i40e_flow_parse_attr(attr, error);
3771         if (ret)
3772                 return ret;
3773
3774         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3775
3776         return ret;
3777 }
3778
3779 /* 1. Last in item should be NULL as range is not supported.
3780  * 2. Supported filter types: MPLS label.
3781  * 3. Mask of fields which need to be matched should be
3782  *    filled with 1.
3783  * 4. Mask of fields which needn't to be matched should be
3784  *    filled with 0.
3785  */
3786 static int
3787 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3788                              const struct rte_flow_item *pattern,
3789                              struct rte_flow_error *error,
3790                              struct i40e_tunnel_filter_conf *filter)
3791 {
3792         const struct rte_flow_item *item = pattern;
3793         const struct rte_flow_item_mpls *mpls_spec;
3794         const struct rte_flow_item_mpls *mpls_mask;
3795         enum rte_flow_item_type item_type;
3796         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3797         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3798         uint32_t label_be = 0;
3799
3800         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3801                 if (item->last) {
3802                         rte_flow_error_set(error, EINVAL,
3803                                            RTE_FLOW_ERROR_TYPE_ITEM,
3804                                            item,
3805                                            "Not support range");
3806                         return -rte_errno;
3807                 }
3808                 item_type = item->type;
3809                 switch (item_type) {
3810                 case RTE_FLOW_ITEM_TYPE_ETH:
3811                         if (item->spec || item->mask) {
3812                                 rte_flow_error_set(error, EINVAL,
3813                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3814                                                    item,
3815                                                    "Invalid ETH item");
3816                                 return -rte_errno;
3817                         }
3818                         break;
3819                 case RTE_FLOW_ITEM_TYPE_IPV4:
3820                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3821                         /* IPv4 is used to describe protocol,
3822                          * spec and mask should be NULL.
3823                          */
3824                         if (item->spec || item->mask) {
3825                                 rte_flow_error_set(error, EINVAL,
3826                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3827                                                    item,
3828                                                    "Invalid IPv4 item");
3829                                 return -rte_errno;
3830                         }
3831                         break;
3832                 case RTE_FLOW_ITEM_TYPE_IPV6:
3833                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3834                         /* IPv6 is used to describe protocol,
3835                          * spec and mask should be NULL.
3836                          */
3837                         if (item->spec || item->mask) {
3838                                 rte_flow_error_set(error, EINVAL,
3839                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3840                                                    item,
3841                                                    "Invalid IPv6 item");
3842                                 return -rte_errno;
3843                         }
3844                         break;
3845                 case RTE_FLOW_ITEM_TYPE_UDP:
3846                         /* UDP is used to describe protocol,
3847                          * spec and mask should be NULL.
3848                          */
3849                         if (item->spec || item->mask) {
3850                                 rte_flow_error_set(error, EINVAL,
3851                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3852                                                    item,
3853                                                    "Invalid UDP item");
3854                                 return -rte_errno;
3855                         }
3856                         is_mplsoudp = 1;
3857                         break;
3858                 case RTE_FLOW_ITEM_TYPE_GRE:
3859                         /* GRE is used to describe protocol,
3860                          * spec and mask should be NULL.
3861                          */
3862                         if (item->spec || item->mask) {
3863                                 rte_flow_error_set(error, EINVAL,
3864                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3865                                                    item,
3866                                                    "Invalid GRE item");
3867                                 return -rte_errno;
3868                         }
3869                         break;
3870                 case RTE_FLOW_ITEM_TYPE_MPLS:
3871                         mpls_spec = item->spec;
3872                         mpls_mask = item->mask;
3873
3874                         if (!mpls_spec || !mpls_mask) {
3875                                 rte_flow_error_set(error, EINVAL,
3876                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3877                                                    item,
3878                                                    "Invalid MPLS item");
3879                                 return -rte_errno;
3880                         }
3881
3882                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3883                                 rte_flow_error_set(error, EINVAL,
3884                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3885                                                    item,
3886                                                    "Invalid MPLS label mask");
3887                                 return -rte_errno;
3888                         }
3889                         rte_memcpy(((uint8_t *)&label_be + 1),
3890                                    mpls_spec->label_tc_s, 3);
3891                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3892                         break;
3893                 default:
3894                         break;
3895                 }
3896         }
3897
3898         if (is_mplsoudp)
3899                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3900         else
3901                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3902
3903         return 0;
3904 }
3905
3906 static int
3907 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3908                             const struct rte_flow_attr *attr,
3909                             const struct rte_flow_item pattern[],
3910                             const struct rte_flow_action actions[],
3911                             struct rte_flow_error *error,
3912                             union i40e_filter_t *filter)
3913 {
3914         struct i40e_tunnel_filter_conf *tunnel_filter =
3915                 &filter->consistent_tunnel_filter;
3916         int ret;
3917
3918         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3919                                            error, tunnel_filter);
3920         if (ret)
3921                 return ret;
3922
3923         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3924         if (ret)
3925                 return ret;
3926
3927         ret = i40e_flow_parse_attr(attr, error);
3928         if (ret)
3929                 return ret;
3930
3931         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3932
3933         return ret;
3934 }
3935
3936 /* 1. Last in item should be NULL as range is not supported.
3937  * 2. Supported filter types: GTP TEID.
3938  * 3. Mask of fields which need to be matched should be
3939  *    filled with 1.
3940  * 4. Mask of fields which needn't to be matched should be
3941  *    filled with 0.
3942  * 5. GTP profile supports GTPv1 only.
3943  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3944  */
3945 static int
3946 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3947                             const struct rte_flow_item *pattern,
3948                             struct rte_flow_error *error,
3949                             struct i40e_tunnel_filter_conf *filter)
3950 {
3951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3952         const struct rte_flow_item *item = pattern;
3953         const struct rte_flow_item_gtp *gtp_spec;
3954         const struct rte_flow_item_gtp *gtp_mask;
3955         enum rte_flow_item_type item_type;
3956
3957         if (!pf->gtp_support) {
3958                 rte_flow_error_set(error, EINVAL,
3959                                    RTE_FLOW_ERROR_TYPE_ITEM,
3960                                    item,
3961                                    "GTP is not supported by default.");
3962                 return -rte_errno;
3963         }
3964
3965         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3966                 if (item->last) {
3967                         rte_flow_error_set(error, EINVAL,
3968                                            RTE_FLOW_ERROR_TYPE_ITEM,
3969                                            item,
3970                                            "Not support range");
3971                         return -rte_errno;
3972                 }
3973                 item_type = item->type;
3974                 switch (item_type) {
3975                 case RTE_FLOW_ITEM_TYPE_ETH:
3976                         if (item->spec || item->mask) {
3977                                 rte_flow_error_set(error, EINVAL,
3978                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3979                                                    item,
3980                                                    "Invalid ETH item");
3981                                 return -rte_errno;
3982                         }
3983                         break;
3984                 case RTE_FLOW_ITEM_TYPE_IPV4:
3985                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3986                         /* IPv4 is used to describe protocol,
3987                          * spec and mask should be NULL.
3988                          */
3989                         if (item->spec || item->mask) {
3990                                 rte_flow_error_set(error, EINVAL,
3991                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3992                                                    item,
3993                                                    "Invalid IPv4 item");
3994                                 return -rte_errno;
3995                         }
3996                         break;
3997                 case RTE_FLOW_ITEM_TYPE_UDP:
3998                         if (item->spec || item->mask) {
3999                                 rte_flow_error_set(error, EINVAL,
4000                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4001                                                    item,
4002                                                    "Invalid UDP item");
4003                                 return -rte_errno;
4004                         }
4005                         break;
4006                 case RTE_FLOW_ITEM_TYPE_GTPC:
4007                 case RTE_FLOW_ITEM_TYPE_GTPU:
4008                         gtp_spec = item->spec;
4009                         gtp_mask = item->mask;
4010
4011                         if (!gtp_spec || !gtp_mask) {
4012                                 rte_flow_error_set(error, EINVAL,
4013                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4014                                                    item,
4015                                                    "Invalid GTP item");
4016                                 return -rte_errno;
4017                         }
4018
4019                         if (gtp_mask->v_pt_rsv_flags ||
4020                             gtp_mask->msg_type ||
4021                             gtp_mask->msg_len ||
4022                             gtp_mask->teid != UINT32_MAX) {
4023                                 rte_flow_error_set(error, EINVAL,
4024                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4025                                                    item,
4026                                                    "Invalid GTP mask");
4027                                 return -rte_errno;
4028                         }
4029
4030                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
4031                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
4032                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
4033                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
4034
4035                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4036
4037                         break;
4038                 default:
4039                         break;
4040                 }
4041         }
4042
4043         return 0;
4044 }
4045
4046 static int
4047 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4048                            const struct rte_flow_attr *attr,
4049                            const struct rte_flow_item pattern[],
4050                            const struct rte_flow_action actions[],
4051                            struct rte_flow_error *error,
4052                            union i40e_filter_t *filter)
4053 {
4054         struct i40e_tunnel_filter_conf *tunnel_filter =
4055                 &filter->consistent_tunnel_filter;
4056         int ret;
4057
4058         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4059                                           error, tunnel_filter);
4060         if (ret)
4061                 return ret;
4062
4063         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4064         if (ret)
4065                 return ret;
4066
4067         ret = i40e_flow_parse_attr(attr, error);
4068         if (ret)
4069                 return ret;
4070
4071         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4072
4073         return ret;
4074 }
4075
4076 /* 1. Last in item should be NULL as range is not supported.
4077  * 2. Supported filter types: QINQ.
4078  * 3. Mask of fields which need to be matched should be
4079  *    filled with 1.
4080  * 4. Mask of fields which needn't to be matched should be
4081  *    filled with 0.
4082  */
4083 static int
4084 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4085                               const struct rte_flow_item *pattern,
4086                               struct rte_flow_error *error,
4087                               struct i40e_tunnel_filter_conf *filter)
4088 {
4089         const struct rte_flow_item *item = pattern;
4090         const struct rte_flow_item_vlan *vlan_spec = NULL;
4091         const struct rte_flow_item_vlan *vlan_mask = NULL;
4092         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4093         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4094         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4095         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4096
4097         enum rte_flow_item_type item_type;
4098         bool vlan_flag = 0;
4099
4100         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4101                 if (item->last) {
4102                         rte_flow_error_set(error, EINVAL,
4103                                            RTE_FLOW_ERROR_TYPE_ITEM,
4104                                            item,
4105                                            "Not support range");
4106                         return -rte_errno;
4107                 }
4108                 item_type = item->type;
4109                 switch (item_type) {
4110                 case RTE_FLOW_ITEM_TYPE_ETH:
4111                         if (item->spec || item->mask) {
4112                                 rte_flow_error_set(error, EINVAL,
4113                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4114                                                    item,
4115                                                    "Invalid ETH item");
4116                                 return -rte_errno;
4117                         }
4118                         break;
4119                 case RTE_FLOW_ITEM_TYPE_VLAN:
4120                         vlan_spec = item->spec;
4121                         vlan_mask = item->mask;
4122
4123                         if (!(vlan_spec && vlan_mask) ||
4124                             vlan_mask->inner_type) {
4125                                 rte_flow_error_set(error, EINVAL,
4126                                            RTE_FLOW_ERROR_TYPE_ITEM,
4127                                            item,
4128                                            "Invalid vlan item");
4129                                 return -rte_errno;
4130                         }
4131
4132                         if (!vlan_flag) {
4133                                 o_vlan_spec = vlan_spec;
4134                                 o_vlan_mask = vlan_mask;
4135                                 vlan_flag = 1;
4136                         } else {
4137                                 i_vlan_spec = vlan_spec;
4138                                 i_vlan_mask = vlan_mask;
4139                                 vlan_flag = 0;
4140                         }
4141                         break;
4142
4143                 default:
4144                         break;
4145                 }
4146         }
4147
4148         /* Get filter specification */
4149         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4150                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4151                         (i_vlan_mask != NULL) &&
4152                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4153                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4154                         & I40E_TCI_MASK;
4155                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4156                         & I40E_TCI_MASK;
4157         } else {
4158                         rte_flow_error_set(error, EINVAL,
4159                                            RTE_FLOW_ERROR_TYPE_ITEM,
4160                                            NULL,
4161                                            "Invalid filter type");
4162                         return -rte_errno;
4163         }
4164
4165         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4166         return 0;
4167 }
4168
4169 static int
4170 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4171                               const struct rte_flow_attr *attr,
4172                               const struct rte_flow_item pattern[],
4173                               const struct rte_flow_action actions[],
4174                               struct rte_flow_error *error,
4175                               union i40e_filter_t *filter)
4176 {
4177         struct i40e_tunnel_filter_conf *tunnel_filter =
4178                 &filter->consistent_tunnel_filter;
4179         int ret;
4180
4181         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4182                                              error, tunnel_filter);
4183         if (ret)
4184                 return ret;
4185
4186         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4187         if (ret)
4188                 return ret;
4189
4190         ret = i40e_flow_parse_attr(attr, error);
4191         if (ret)
4192                 return ret;
4193
4194         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4195
4196         return ret;
4197 }
4198
4199 /**
4200  * This function is used to do configuration i40e existing RSS with rte_flow.
4201  * It also enable queue region configuration using flow API for i40e.
4202  * pattern can be used indicate what parameters will be include in flow,
4203  * like user_priority or flowtype for queue region or HASH function for RSS.
4204  * Action is used to transmit parameter like queue index and HASH
4205  * function for RSS, or flowtype for queue region configuration.
4206  * For example:
4207  * pattern:
4208  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4209  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4210  * Case 3: none, indicate RSS related will be parsed in action.
4211  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4212  * So, pattern choice is depened on the purpose of configuration of
4213  * that flow.
4214  * action:
4215  * action RSS will be uaed to transmit valid parameter with
4216  * struct rte_flow_action_rss for all the 3 case.
4217  */
4218 static int
4219 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4220                              const struct rte_flow_item *pattern,
4221                              struct rte_flow_error *error,
4222                              uint8_t *action_flag,
4223                              struct i40e_queue_regions *info)
4224 {
4225         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4226         const struct rte_flow_item *item = pattern;
4227         enum rte_flow_item_type item_type;
4228
4229         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4230                 return 0;
4231
4232         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4233                 if (item->last) {
4234                         rte_flow_error_set(error, EINVAL,
4235                                            RTE_FLOW_ERROR_TYPE_ITEM,
4236                                            item,
4237                                            "Not support range");
4238                         return -rte_errno;
4239                 }
4240                 item_type = item->type;
4241                 switch (item_type) {
4242                 case RTE_FLOW_ITEM_TYPE_ETH:
4243                         *action_flag = 1;
4244                         break;
4245                 case RTE_FLOW_ITEM_TYPE_VLAN:
4246                         vlan_spec = item->spec;
4247                         vlan_mask = item->mask;
4248                         if (vlan_spec && vlan_mask) {
4249                                 if (vlan_mask->tci ==
4250                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4251                                         info->region[0].user_priority[0] =
4252                                                 (rte_be_to_cpu_16(
4253                                                 vlan_spec->tci) >> 13) & 0x7;
4254                                         info->region[0].user_priority_num = 1;
4255                                         info->queue_region_number = 1;
4256                                         *action_flag = 0;
4257                                 }
4258                         }
4259                         break;
4260                 default:
4261                         rte_flow_error_set(error, EINVAL,
4262                                         RTE_FLOW_ERROR_TYPE_ITEM,
4263                                         item,
4264                                         "Not support range");
4265                         return -rte_errno;
4266                 }
4267         }
4268
4269         return 0;
4270 }
4271
4272 /**
4273  * This function is used to parse rss queue index, total queue number and
4274  * hash functions, If the purpose of this configuration is for queue region
4275  * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4276  * In queue region configuration, it also need to parse hardware flowtype
4277  * and user_priority from configuration, it will also cheeck the validity
4278  * of these parameters. For example, The queue region sizes should
4279  * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4280  * hw_flowtype or PCTYPE max index should be 63, the user priority
4281  * max index should be 7, and so on. And also, queue index should be
4282  * continuous sequence and queue region index should be part of rss
4283  * queue index for this port.
4284  */
4285 static int
4286 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4287                             const struct rte_flow_action *actions,
4288                             struct rte_flow_error *error,
4289                             uint8_t action_flag,
4290                             struct i40e_queue_regions *conf_info,
4291                             union i40e_filter_t *filter)
4292 {
4293         const struct rte_flow_action *act;
4294         const struct rte_flow_action_rss *rss;
4295         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4296         struct i40e_queue_regions *info = &pf->queue_region;
4297         struct i40e_rte_flow_rss_conf *rss_config =
4298                         &filter->rss_conf;
4299         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4300         uint16_t i, j, n, tmp;
4301         uint32_t index = 0;
4302         uint64_t hf_bit = 1;
4303
4304         NEXT_ITEM_OF_ACTION(act, actions, index);
4305         rss = act->conf;
4306
4307         /**
4308          * rss only supports forwarding,
4309          * check if the first not void action is RSS.
4310          */
4311         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4312                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4313                 rte_flow_error_set(error, EINVAL,
4314                         RTE_FLOW_ERROR_TYPE_ACTION,
4315                         act, "Not supported action.");
4316                 return -rte_errno;
4317         }
4318
4319         if (action_flag) {
4320                 for (n = 0; n < 64; n++) {
4321                         if (rss->types & (hf_bit << n)) {
4322                                 conf_info->region[0].hw_flowtype[0] = n;
4323                                 conf_info->region[0].flowtype_num = 1;
4324                                 conf_info->queue_region_number = 1;
4325                                 break;
4326                         }
4327                 }
4328         }
4329
4330         /**
4331          * Do some queue region related parameters check
4332          * in order to keep queue index for queue region to be
4333          * continuous sequence and also to be part of RSS
4334          * queue index for this port.
4335          */
4336         if (conf_info->queue_region_number) {
4337                 for (i = 0; i < rss->queue_num; i++) {
4338                         for (j = 0; j < rss_info->conf.queue_num; j++) {
4339                                 if (rss->queue[i] == rss_info->conf.queue[j])
4340                                         break;
4341                         }
4342                         if (j == rss_info->conf.queue_num) {
4343                                 rte_flow_error_set(error, EINVAL,
4344                                         RTE_FLOW_ERROR_TYPE_ACTION,
4345                                         act,
4346                                         "no valid queues");
4347                                 return -rte_errno;
4348                         }
4349                 }
4350
4351                 for (i = 0; i < rss->queue_num - 1; i++) {
4352                         if (rss->queue[i + 1] != rss->queue[i] + 1) {
4353                                 rte_flow_error_set(error, EINVAL,
4354                                         RTE_FLOW_ERROR_TYPE_ACTION,
4355                                         act,
4356                                         "no valid queues");
4357                                 return -rte_errno;
4358                         }
4359                 }
4360         }
4361
4362         /* Parse queue region related parameters from configuration */
4363         for (n = 0; n < conf_info->queue_region_number; n++) {
4364                 if (conf_info->region[n].user_priority_num ||
4365                                 conf_info->region[n].flowtype_num) {
4366                         if (!((rte_is_power_of_2(rss->queue_num)) &&
4367                                         rss->queue_num <= 64)) {
4368                                 rte_flow_error_set(error, EINVAL,
4369                                         RTE_FLOW_ERROR_TYPE_ACTION,
4370                                         act,
4371                                         "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4372                                         "total number of queues do not exceed the VSI allocation");
4373                                 return -rte_errno;
4374                         }
4375
4376                         if (conf_info->region[n].user_priority[n] >=
4377                                         I40E_MAX_USER_PRIORITY) {
4378                                 rte_flow_error_set(error, EINVAL,
4379                                         RTE_FLOW_ERROR_TYPE_ACTION,
4380                                         act,
4381                                         "the user priority max index is 7");
4382                                 return -rte_errno;
4383                         }
4384
4385                         if (conf_info->region[n].hw_flowtype[n] >=
4386                                         I40E_FILTER_PCTYPE_MAX) {
4387                                 rte_flow_error_set(error, EINVAL,
4388                                         RTE_FLOW_ERROR_TYPE_ACTION,
4389                                         act,
4390                                         "the hw_flowtype or PCTYPE max index is 63");
4391                                 return -rte_errno;
4392                         }
4393
4394                         for (i = 0; i < info->queue_region_number; i++) {
4395                                 if (info->region[i].queue_num ==
4396                                     rss->queue_num &&
4397                                         info->region[i].queue_start_index ==
4398                                                 rss->queue[0])
4399                                         break;
4400                         }
4401
4402                         if (i == info->queue_region_number) {
4403                                 if (i > I40E_REGION_MAX_INDEX) {
4404                                         rte_flow_error_set(error, EINVAL,
4405                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4406                                                 act,
4407                                                 "the queue region max index is 7");
4408                                         return -rte_errno;
4409                                 }
4410
4411                                 info->region[i].queue_num =
4412                                         rss->queue_num;
4413                                 info->region[i].queue_start_index =
4414                                         rss->queue[0];
4415                                 info->region[i].region_id =
4416                                         info->queue_region_number;
4417
4418                                 j = info->region[i].user_priority_num;
4419                                 tmp = conf_info->region[n].user_priority[0];
4420                                 if (conf_info->region[n].user_priority_num) {
4421                                         info->region[i].user_priority[j] = tmp;
4422                                         info->region[i].user_priority_num++;
4423                                 }
4424
4425                                 j = info->region[i].flowtype_num;
4426                                 tmp = conf_info->region[n].hw_flowtype[0];
4427                                 if (conf_info->region[n].flowtype_num) {
4428                                         info->region[i].hw_flowtype[j] = tmp;
4429                                         info->region[i].flowtype_num++;
4430                                 }
4431                                 info->queue_region_number++;
4432                         } else {
4433                                 j = info->region[i].user_priority_num;
4434                                 tmp = conf_info->region[n].user_priority[0];
4435                                 if (conf_info->region[n].user_priority_num) {
4436                                         info->region[i].user_priority[j] = tmp;
4437                                         info->region[i].user_priority_num++;
4438                                 }
4439
4440                                 j = info->region[i].flowtype_num;
4441                                 tmp = conf_info->region[n].hw_flowtype[0];
4442                                 if (conf_info->region[n].flowtype_num) {
4443                                         info->region[i].hw_flowtype[j] = tmp;
4444                                         info->region[i].flowtype_num++;
4445                                 }
4446                         }
4447                 }
4448
4449                 rss_config->queue_region_conf = TRUE;
4450         }
4451
4452         /**
4453          * Return function if this flow is used for queue region configuration
4454          */
4455         if (rss_config->queue_region_conf)
4456                 return 0;
4457
4458         if (!rss || !rss->queue_num) {
4459                 rte_flow_error_set(error, EINVAL,
4460                                 RTE_FLOW_ERROR_TYPE_ACTION,
4461                                 act,
4462                                 "no valid queues");
4463                 return -rte_errno;
4464         }
4465
4466         for (n = 0; n < rss->queue_num; n++) {
4467                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4468                         rte_flow_error_set(error, EINVAL,
4469                                    RTE_FLOW_ERROR_TYPE_ACTION,
4470                                    act,
4471                                    "queue id > max number of queues");
4472                         return -rte_errno;
4473                 }
4474         }
4475
4476         if (rss_info->conf.queue_num) {
4477                 rte_flow_error_set(error, EINVAL,
4478                                 RTE_FLOW_ERROR_TYPE_ACTION,
4479                                 act,
4480                                 "rss only allow one valid rule");
4481                 return -rte_errno;
4482         }
4483
4484         /* Parse RSS related parameters from configuration */
4485         if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4486                 return rte_flow_error_set
4487                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4488                          "non-default RSS hash functions are not supported");
4489         if (rss->level)
4490                 return rte_flow_error_set
4491                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4492                          "a nonzero RSS encapsulation level is not supported");
4493         if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4494                 return rte_flow_error_set
4495                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4496                          "RSS hash key too large");
4497         if (rss->queue_num > RTE_DIM(rss_config->queue))
4498                 return rte_flow_error_set
4499                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4500                          "too many queues for RSS context");
4501         if (i40e_rss_conf_init(rss_config, rss))
4502                 return rte_flow_error_set
4503                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4504                          "RSS context initialization failure");
4505
4506         index++;
4507
4508         /* check if the next not void action is END */
4509         NEXT_ITEM_OF_ACTION(act, actions, index);
4510         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4511                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4512                 rte_flow_error_set(error, EINVAL,
4513                         RTE_FLOW_ERROR_TYPE_ACTION,
4514                         act, "Not supported action.");
4515                 return -rte_errno;
4516         }
4517         rss_config->queue_region_conf = FALSE;
4518
4519         return 0;
4520 }
4521
4522 static int
4523 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4524                         const struct rte_flow_attr *attr,
4525                         const struct rte_flow_item pattern[],
4526                         const struct rte_flow_action actions[],
4527                         union i40e_filter_t *filter,
4528                         struct rte_flow_error *error)
4529 {
4530         int ret;
4531         struct i40e_queue_regions info;
4532         uint8_t action_flag = 0;
4533
4534         memset(&info, 0, sizeof(struct i40e_queue_regions));
4535
4536         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4537                                         error, &action_flag, &info);
4538         if (ret)
4539                 return ret;
4540
4541         ret = i40e_flow_parse_rss_action(dev, actions, error,
4542                                         action_flag, &info, filter);
4543         if (ret)
4544                 return ret;
4545
4546         ret = i40e_flow_parse_attr(attr, error);
4547         if (ret)
4548                 return ret;
4549
4550         cons_filter_type = RTE_ETH_FILTER_HASH;
4551
4552         return 0;
4553 }
4554
4555 static int
4556 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4557                 struct i40e_rte_flow_rss_conf *conf)
4558 {
4559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4560         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4561         int ret;
4562
4563         if (conf->queue_region_conf) {
4564                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4565                 conf->queue_region_conf = 0;
4566         } else {
4567                 ret = i40e_config_rss_filter(pf, conf, 1);
4568         }
4569         return ret;
4570 }
4571
4572 static int
4573 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4574                 struct i40e_rte_flow_rss_conf *conf)
4575 {
4576         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4578
4579         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4580
4581         i40e_config_rss_filter(pf, conf, 0);
4582         return 0;
4583 }
4584
4585 static int
4586 i40e_flow_validate(struct rte_eth_dev *dev,
4587                    const struct rte_flow_attr *attr,
4588                    const struct rte_flow_item pattern[],
4589                    const struct rte_flow_action actions[],
4590                    struct rte_flow_error *error)
4591 {
4592         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4593         parse_filter_t parse_filter;
4594         uint32_t item_num = 0; /* non-void item number of pattern*/
4595         uint32_t i = 0;
4596         bool flag = false;
4597         int ret = I40E_NOT_SUPPORTED;
4598
4599         if (!pattern) {
4600                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4601                                    NULL, "NULL pattern.");
4602                 return -rte_errno;
4603         }
4604
4605         if (!actions) {
4606                 rte_flow_error_set(error, EINVAL,
4607                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4608                                    NULL, "NULL action.");
4609                 return -rte_errno;
4610         }
4611
4612         if (!attr) {
4613                 rte_flow_error_set(error, EINVAL,
4614                                    RTE_FLOW_ERROR_TYPE_ATTR,
4615                                    NULL, "NULL attribute.");
4616                 return -rte_errno;
4617         }
4618
4619         memset(&cons_filter, 0, sizeof(cons_filter));
4620
4621         /* Get the non-void item of action */
4622         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4623                 i++;
4624
4625         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4626                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4627                                         actions, &cons_filter, error);
4628                 return ret;
4629         }
4630
4631         i = 0;
4632         /* Get the non-void item number of pattern */
4633         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4634                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4635                         item_num++;
4636                 i++;
4637         }
4638         item_num++;
4639
4640         items = rte_zmalloc("i40e_pattern",
4641                             item_num * sizeof(struct rte_flow_item), 0);
4642         if (!items) {
4643                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4644                                    NULL, "No memory for PMD internal items.");
4645                 return -ENOMEM;
4646         }
4647
4648         i40e_pattern_skip_void_item(items, pattern);
4649
4650         i = 0;
4651         do {
4652                 parse_filter = i40e_find_parse_filter_func(items, &i);
4653                 if (!parse_filter && !flag) {
4654                         rte_flow_error_set(error, EINVAL,
4655                                            RTE_FLOW_ERROR_TYPE_ITEM,
4656                                            pattern, "Unsupported pattern");
4657                         rte_free(items);
4658                         return -rte_errno;
4659                 }
4660                 if (parse_filter)
4661                         ret = parse_filter(dev, attr, items, actions,
4662                                            error, &cons_filter);
4663                 flag = true;
4664         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4665
4666         rte_free(items);
4667
4668         return ret;
4669 }
4670
4671 static struct rte_flow *
4672 i40e_flow_create(struct rte_eth_dev *dev,
4673                  const struct rte_flow_attr *attr,
4674                  const struct rte_flow_item pattern[],
4675                  const struct rte_flow_action actions[],
4676                  struct rte_flow_error *error)
4677 {
4678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4679         struct rte_flow *flow;
4680         int ret;
4681
4682         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4683         if (!flow) {
4684                 rte_flow_error_set(error, ENOMEM,
4685                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4686                                    "Failed to allocate memory");
4687                 return flow;
4688         }
4689
4690         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4691         if (ret < 0)
4692                 return NULL;
4693
4694         switch (cons_filter_type) {
4695         case RTE_ETH_FILTER_ETHERTYPE:
4696                 ret = i40e_ethertype_filter_set(pf,
4697                                         &cons_filter.ethertype_filter, 1);
4698                 if (ret)
4699                         goto free_flow;
4700                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4701                                         i40e_ethertype_filter_list);
4702                 break;
4703         case RTE_ETH_FILTER_FDIR:
4704                 ret = i40e_flow_add_del_fdir_filter(dev,
4705                                        &cons_filter.fdir_filter, 1);
4706                 if (ret)
4707                         goto free_flow;
4708                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4709                                         i40e_fdir_filter_list);
4710                 break;
4711         case RTE_ETH_FILTER_TUNNEL:
4712                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4713                             &cons_filter.consistent_tunnel_filter, 1);
4714                 if (ret)
4715                         goto free_flow;
4716                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4717                                         i40e_tunnel_filter_list);
4718                 break;
4719         case RTE_ETH_FILTER_HASH:
4720                 ret = i40e_config_rss_filter_set(dev,
4721                             &cons_filter.rss_conf);
4722                 if (ret)
4723                         goto free_flow;
4724                 flow->rule = &pf->rss_info;
4725                 break;
4726         default:
4727                 goto free_flow;
4728         }
4729
4730         flow->filter_type = cons_filter_type;
4731         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4732         return flow;
4733
4734 free_flow:
4735         rte_flow_error_set(error, -ret,
4736                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4737                            "Failed to create flow.");
4738         rte_free(flow);
4739         return NULL;
4740 }
4741
4742 static int
4743 i40e_flow_destroy(struct rte_eth_dev *dev,
4744                   struct rte_flow *flow,
4745                   struct rte_flow_error *error)
4746 {
4747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4748         enum rte_filter_type filter_type = flow->filter_type;
4749         int ret = 0;
4750
4751         switch (filter_type) {
4752         case RTE_ETH_FILTER_ETHERTYPE:
4753                 ret = i40e_flow_destroy_ethertype_filter(pf,
4754                          (struct i40e_ethertype_filter *)flow->rule);
4755                 break;
4756         case RTE_ETH_FILTER_TUNNEL:
4757                 ret = i40e_flow_destroy_tunnel_filter(pf,
4758                               (struct i40e_tunnel_filter *)flow->rule);
4759                 break;
4760         case RTE_ETH_FILTER_FDIR:
4761                 ret = i40e_flow_add_del_fdir_filter(dev,
4762                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4763
4764                 /* If the last flow is destroyed, disable fdir. */
4765                 if (!ret && !TAILQ_EMPTY(&pf->fdir.fdir_list)) {
4766                         i40e_fdir_teardown(pf);
4767                         dev->data->dev_conf.fdir_conf.mode =
4768                                    RTE_FDIR_MODE_NONE;
4769                 }
4770                 break;
4771         case RTE_ETH_FILTER_HASH:
4772                 ret = i40e_config_rss_filter_del(dev,
4773                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4774                 break;
4775         default:
4776                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4777                             filter_type);
4778                 ret = -EINVAL;
4779                 break;
4780         }
4781
4782         if (!ret) {
4783                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4784                 rte_free(flow);
4785         } else
4786                 rte_flow_error_set(error, -ret,
4787                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4788                                    "Failed to destroy flow.");
4789
4790         return ret;
4791 }
4792
4793 static int
4794 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4795                                    struct i40e_ethertype_filter *filter)
4796 {
4797         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4798         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4799         struct i40e_ethertype_filter *node;
4800         struct i40e_control_filter_stats stats;
4801         uint16_t flags = 0;
4802         int ret = 0;
4803
4804         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4805                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4806         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4807                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4808         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4809
4810         memset(&stats, 0, sizeof(stats));
4811         ret = i40e_aq_add_rem_control_packet_filter(hw,
4812                                     filter->input.mac_addr.addr_bytes,
4813                                     filter->input.ether_type,
4814                                     flags, pf->main_vsi->seid,
4815                                     filter->queue, 0, &stats, NULL);
4816         if (ret < 0)
4817                 return ret;
4818
4819         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4820         if (!node)
4821                 return -EINVAL;
4822
4823         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4824
4825         return ret;
4826 }
4827
4828 static int
4829 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4830                                 struct i40e_tunnel_filter *filter)
4831 {
4832         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4833         struct i40e_vsi *vsi;
4834         struct i40e_pf_vf *vf;
4835         struct i40e_aqc_cloud_filters_element_bb cld_filter;
4836         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4837         struct i40e_tunnel_filter *node;
4838         bool big_buffer = 0;
4839         int ret = 0;
4840
4841         memset(&cld_filter, 0, sizeof(cld_filter));
4842         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac,
4843                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
4844         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac,
4845                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
4846         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4847         cld_filter.element.flags = filter->input.flags;
4848         cld_filter.element.tenant_id = filter->input.tenant_id;
4849         cld_filter.element.queue_number = filter->queue;
4850         rte_memcpy(cld_filter.general_fields,
4851                    filter->input.general_fields,
4852                    sizeof(cld_filter.general_fields));
4853
4854         if (!filter->is_to_vf)
4855                 vsi = pf->main_vsi;
4856         else {
4857                 vf = &pf->vfs[filter->vf_id];
4858                 vsi = vf->vsi;
4859         }
4860
4861         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4862             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4863             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4864             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4865             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4866             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4867                 big_buffer = 1;
4868
4869         if (big_buffer)
4870                 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid,
4871                                                 &cld_filter, 1);
4872         else
4873                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
4874                                                 &cld_filter.element, 1);
4875         if (ret < 0)
4876                 return -ENOTSUP;
4877
4878         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4879         if (!node)
4880                 return -EINVAL;
4881
4882         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4883
4884         return ret;
4885 }
4886
4887 static int
4888 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4889 {
4890         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4891         int ret;
4892
4893         ret = i40e_flow_flush_fdir_filter(pf);
4894         if (ret) {
4895                 rte_flow_error_set(error, -ret,
4896                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4897                                    "Failed to flush FDIR flows.");
4898                 return -rte_errno;
4899         }
4900
4901         ret = i40e_flow_flush_ethertype_filter(pf);
4902         if (ret) {
4903                 rte_flow_error_set(error, -ret,
4904                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4905                                    "Failed to ethertype flush flows.");
4906                 return -rte_errno;
4907         }
4908
4909         ret = i40e_flow_flush_tunnel_filter(pf);
4910         if (ret) {
4911                 rte_flow_error_set(error, -ret,
4912                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4913                                    "Failed to flush tunnel flows.");
4914                 return -rte_errno;
4915         }
4916
4917         ret = i40e_flow_flush_rss_filter(dev);
4918         if (ret) {
4919                 rte_flow_error_set(error, -ret,
4920                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4921                                    "Failed to flush rss flows.");
4922                 return -rte_errno;
4923         }
4924
4925         return ret;
4926 }
4927
4928 static int
4929 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4930 {
4931         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4932         struct i40e_fdir_info *fdir_info = &pf->fdir;
4933         struct i40e_fdir_filter *fdir_filter;
4934         enum i40e_filter_pctype pctype;
4935         struct rte_flow *flow;
4936         void *temp;
4937         int ret;
4938
4939         ret = i40e_fdir_flush(dev);
4940         if (!ret) {
4941                 /* Delete FDIR filters in FDIR list. */
4942                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4943                         ret = i40e_sw_fdir_filter_del(pf,
4944                                                       &fdir_filter->fdir.input);
4945                         if (ret < 0)
4946                                 return ret;
4947                 }
4948
4949                 /* Delete FDIR flows in flow list. */
4950                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4951                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4952                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4953                                 rte_free(flow);
4954                         }
4955                 }
4956
4957                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4958                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4959                         pf->fdir.inset_flag[pctype] = 0;
4960         }
4961
4962         i40e_fdir_teardown(pf);
4963
4964         return ret;
4965 }
4966
4967 /* Flush all ethertype filters */
4968 static int
4969 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4970 {
4971         struct i40e_ethertype_filter_list
4972                 *ethertype_list = &pf->ethertype.ethertype_list;
4973         struct i40e_ethertype_filter *filter;
4974         struct rte_flow *flow;
4975         void *temp;
4976         int ret = 0;
4977
4978         while ((filter = TAILQ_FIRST(ethertype_list))) {
4979                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4980                 if (ret)
4981                         return ret;
4982         }
4983
4984         /* Delete ethertype flows in flow list. */
4985         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4986                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4987                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4988                         rte_free(flow);
4989                 }
4990         }
4991
4992         return ret;
4993 }
4994
4995 /* Flush all tunnel filters */
4996 static int
4997 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4998 {
4999         struct i40e_tunnel_filter_list
5000                 *tunnel_list = &pf->tunnel.tunnel_list;
5001         struct i40e_tunnel_filter *filter;
5002         struct rte_flow *flow;
5003         void *temp;
5004         int ret = 0;
5005
5006         while ((filter = TAILQ_FIRST(tunnel_list))) {
5007                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
5008                 if (ret)
5009                         return ret;
5010         }
5011
5012         /* Delete tunnel flows in flow list. */
5013         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5014                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
5015                         TAILQ_REMOVE(&pf->flow_list, flow, node);
5016                         rte_free(flow);
5017                 }
5018         }
5019
5020         return ret;
5021 }
5022
5023 /* remove the rss filter */
5024 static int
5025 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
5026 {
5027         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5028         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
5029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030         int32_t ret = -EINVAL;
5031
5032         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5033
5034         if (rss_info->conf.queue_num)
5035                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
5036         return ret;
5037 }