drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_debug.h>
  14 #include <rte_ether.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_log.h>
  17 #include <rte_malloc.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20
  21 #include "i40e_logs.h"
  22 #include "base/i40e_type.h"
  23 #include "base/i40e_prototype.h"
  24 #include "i40e_ethdev.h"
  25
  26 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  27 #define I40E_IPV6_FRAG_HEADER   44
  28 #define I40E_TENANT_ARRAY_NUM   3
  29 #define I40E_TCI_MASK           0xFFFF
  30
  31 static int i40e_flow_validate(struct rte_eth_dev *dev,
  32                               const struct rte_flow_attr *attr,
  33                               const struct rte_flow_item pattern[],
  34                               const struct rte_flow_action actions[],
  35                               struct rte_flow_error *error);
  36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  37                                          const struct rte_flow_attr *attr,
  38                                          const struct rte_flow_item pattern[],
  39                                          const struct rte_flow_action actions[],
  40                                          struct rte_flow_error *error);
  41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  42                              struct rte_flow *flow,
  43                              struct rte_flow_error *error);
  44 static int i40e_flow_flush(struct rte_eth_dev *dev,
  45                            struct rte_flow_error *error);
  46 static int
  47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  48                                   const struct rte_flow_item *pattern,
  49                                   struct rte_flow_error *error,
  50                                   struct rte_eth_ethertype_filter *filter);
  51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  52                                     const struct rte_flow_action *actions,
  53                                     struct rte_flow_error *error,
  54                                     struct rte_eth_ethertype_filter *filter);
  55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  56                                         const struct rte_flow_attr *attr,
  57                                         const struct rte_flow_item *pattern,
  58                                         struct rte_flow_error *error,
  59                                         struct i40e_fdir_filter_conf *filter);
  60 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  61                                        const struct rte_flow_action *actions,
  62                                        struct rte_flow_error *error,
  63                                        struct i40e_fdir_filter_conf *filter);
  64 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  65                                  const struct rte_flow_action *actions,
  66                                  struct rte_flow_error *error,
  67                                  struct i40e_tunnel_filter_conf *filter);
  68 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  69                                 struct rte_flow_error *error);
  70 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  71                                     const struct rte_flow_attr *attr,
  72                                     const struct rte_flow_item pattern[],
  73                                     const struct rte_flow_action actions[],
  74                                     struct rte_flow_error *error,
  75                                     union i40e_filter_t *filter);
  76 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  77                                        const struct rte_flow_attr *attr,
  78                                        const struct rte_flow_item pattern[],
  79                                        const struct rte_flow_action actions[],
  80                                        struct rte_flow_error *error,
  81                                        union i40e_filter_t *filter);
  82 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  83                                         const struct rte_flow_attr *attr,
  84                                         const struct rte_flow_item pattern[],
  85                                         const struct rte_flow_action actions[],
  86                                         struct rte_flow_error *error,
  87                                         union i40e_filter_t *filter);
  88 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  89                                         const struct rte_flow_attr *attr,
  90                                         const struct rte_flow_item pattern[],
  91                                         const struct rte_flow_action actions[],
  92                                         struct rte_flow_error *error,
  93                                         union i40e_filter_t *filter);
  94 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  95                                        const struct rte_flow_attr *attr,
  96                                        const struct rte_flow_item pattern[],
  97                                        const struct rte_flow_action actions[],
  98                                        struct rte_flow_error *error,
  99                                        union i40e_filter_t *filter);
 100 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 101                                       const struct rte_flow_attr *attr,
 102                                       const struct rte_flow_item pattern[],
 103                                       const struct rte_flow_action actions[],
 104                                       struct rte_flow_error *error,
 105                                       union i40e_filter_t *filter);
 106 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 107                                       struct i40e_ethertype_filter *filter);
 108 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 109                                            struct i40e_tunnel_filter *filter);
 110 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 112 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 113 static int i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 114 static int
 115 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 116                               const struct rte_flow_attr *attr,
 117                               const struct rte_flow_item pattern[],
 118                               const struct rte_flow_action actions[],
 119                               struct rte_flow_error *error,
 120                               union i40e_filter_t *filter);
 121 static int
 122 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 123                               const struct rte_flow_item *pattern,
 124                               struct rte_flow_error *error,
 125                               struct i40e_tunnel_filter_conf *filter);
 126
 127 const struct rte_flow_ops i40e_flow_ops = {
 128         .validate = i40e_flow_validate,
 129         .create = i40e_flow_create,
 130         .destroy = i40e_flow_destroy,
 131         .flush = i40e_flow_flush,
 132 };
 133
 134 static union i40e_filter_t cons_filter;
 135 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 136
 137 /* Pattern matched ethertype filter */
 138 static enum rte_flow_item_type pattern_ethertype[] = {
 139         RTE_FLOW_ITEM_TYPE_ETH,
 140         RTE_FLOW_ITEM_TYPE_END,
 141 };
 142
 143 /* Pattern matched flow director filter */
 144 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 145         RTE_FLOW_ITEM_TYPE_ETH,
 146         RTE_FLOW_ITEM_TYPE_IPV4,
 147         RTE_FLOW_ITEM_TYPE_END,
 148 };
 149
 150 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 151         RTE_FLOW_ITEM_TYPE_ETH,
 152         RTE_FLOW_ITEM_TYPE_IPV4,
 153         RTE_FLOW_ITEM_TYPE_UDP,
 154         RTE_FLOW_ITEM_TYPE_END,
 155 };
 156
 157 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 158         RTE_FLOW_ITEM_TYPE_ETH,
 159         RTE_FLOW_ITEM_TYPE_IPV4,
 160         RTE_FLOW_ITEM_TYPE_TCP,
 161         RTE_FLOW_ITEM_TYPE_END,
 162 };
 163
 164 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 165         RTE_FLOW_ITEM_TYPE_ETH,
 166         RTE_FLOW_ITEM_TYPE_IPV4,
 167         RTE_FLOW_ITEM_TYPE_SCTP,
 168         RTE_FLOW_ITEM_TYPE_END,
 169 };
 170
 171 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 172         RTE_FLOW_ITEM_TYPE_ETH,
 173         RTE_FLOW_ITEM_TYPE_IPV4,
 174         RTE_FLOW_ITEM_TYPE_UDP,
 175         RTE_FLOW_ITEM_TYPE_GTPC,
 176         RTE_FLOW_ITEM_TYPE_END,
 177 };
 178
 179 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 180         RTE_FLOW_ITEM_TYPE_ETH,
 181         RTE_FLOW_ITEM_TYPE_IPV4,
 182         RTE_FLOW_ITEM_TYPE_UDP,
 183         RTE_FLOW_ITEM_TYPE_GTPU,
 184         RTE_FLOW_ITEM_TYPE_END,
 185 };
 186
 187 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 188         RTE_FLOW_ITEM_TYPE_ETH,
 189         RTE_FLOW_ITEM_TYPE_IPV4,
 190         RTE_FLOW_ITEM_TYPE_UDP,
 191         RTE_FLOW_ITEM_TYPE_GTPU,
 192         RTE_FLOW_ITEM_TYPE_IPV4,
 193         RTE_FLOW_ITEM_TYPE_END,
 194 };
 195
 196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 197         RTE_FLOW_ITEM_TYPE_ETH,
 198         RTE_FLOW_ITEM_TYPE_IPV4,
 199         RTE_FLOW_ITEM_TYPE_UDP,
 200         RTE_FLOW_ITEM_TYPE_GTPU,
 201         RTE_FLOW_ITEM_TYPE_IPV6,
 202         RTE_FLOW_ITEM_TYPE_END,
 203 };
 204
 205 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 206         RTE_FLOW_ITEM_TYPE_ETH,
 207         RTE_FLOW_ITEM_TYPE_IPV6,
 208         RTE_FLOW_ITEM_TYPE_END,
 209 };
 210
 211 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 212         RTE_FLOW_ITEM_TYPE_ETH,
 213         RTE_FLOW_ITEM_TYPE_IPV6,
 214         RTE_FLOW_ITEM_TYPE_UDP,
 215         RTE_FLOW_ITEM_TYPE_END,
 216 };
 217
 218 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 219         RTE_FLOW_ITEM_TYPE_ETH,
 220         RTE_FLOW_ITEM_TYPE_IPV6,
 221         RTE_FLOW_ITEM_TYPE_TCP,
 222         RTE_FLOW_ITEM_TYPE_END,
 223 };
 224
 225 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 226         RTE_FLOW_ITEM_TYPE_ETH,
 227         RTE_FLOW_ITEM_TYPE_IPV6,
 228         RTE_FLOW_ITEM_TYPE_SCTP,
 229         RTE_FLOW_ITEM_TYPE_END,
 230 };
 231
 232 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 233         RTE_FLOW_ITEM_TYPE_ETH,
 234         RTE_FLOW_ITEM_TYPE_IPV6,
 235         RTE_FLOW_ITEM_TYPE_UDP,
 236         RTE_FLOW_ITEM_TYPE_GTPC,
 237         RTE_FLOW_ITEM_TYPE_END,
 238 };
 239
 240 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 241         RTE_FLOW_ITEM_TYPE_ETH,
 242         RTE_FLOW_ITEM_TYPE_IPV6,
 243         RTE_FLOW_ITEM_TYPE_UDP,
 244         RTE_FLOW_ITEM_TYPE_GTPU,
 245         RTE_FLOW_ITEM_TYPE_END,
 246 };
 247
 248 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 249         RTE_FLOW_ITEM_TYPE_ETH,
 250         RTE_FLOW_ITEM_TYPE_IPV6,
 251         RTE_FLOW_ITEM_TYPE_UDP,
 252         RTE_FLOW_ITEM_TYPE_GTPU,
 253         RTE_FLOW_ITEM_TYPE_IPV4,
 254         RTE_FLOW_ITEM_TYPE_END,
 255 };
 256
 257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 258         RTE_FLOW_ITEM_TYPE_ETH,
 259         RTE_FLOW_ITEM_TYPE_IPV6,
 260         RTE_FLOW_ITEM_TYPE_UDP,
 261         RTE_FLOW_ITEM_TYPE_GTPU,
 262         RTE_FLOW_ITEM_TYPE_IPV6,
 263         RTE_FLOW_ITEM_TYPE_END,
 264 };
 265
 266 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 267         RTE_FLOW_ITEM_TYPE_ETH,
 268         RTE_FLOW_ITEM_TYPE_RAW,
 269         RTE_FLOW_ITEM_TYPE_END,
 270 };
 271
 272 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 273         RTE_FLOW_ITEM_TYPE_ETH,
 274         RTE_FLOW_ITEM_TYPE_RAW,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_END,
 277 };
 278
 279 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 280         RTE_FLOW_ITEM_TYPE_ETH,
 281         RTE_FLOW_ITEM_TYPE_RAW,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_END,
 285 };
 286
 287 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 288         RTE_FLOW_ITEM_TYPE_ETH,
 289         RTE_FLOW_ITEM_TYPE_IPV4,
 290         RTE_FLOW_ITEM_TYPE_RAW,
 291         RTE_FLOW_ITEM_TYPE_END,
 292 };
 293
 294 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 295         RTE_FLOW_ITEM_TYPE_ETH,
 296         RTE_FLOW_ITEM_TYPE_IPV4,
 297         RTE_FLOW_ITEM_TYPE_RAW,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_END,
 300 };
 301
 302 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 303         RTE_FLOW_ITEM_TYPE_ETH,
 304         RTE_FLOW_ITEM_TYPE_IPV4,
 305         RTE_FLOW_ITEM_TYPE_RAW,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_END,
 309 };
 310
 311 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 312         RTE_FLOW_ITEM_TYPE_ETH,
 313         RTE_FLOW_ITEM_TYPE_IPV4,
 314         RTE_FLOW_ITEM_TYPE_UDP,
 315         RTE_FLOW_ITEM_TYPE_RAW,
 316         RTE_FLOW_ITEM_TYPE_END,
 317 };
 318
 319 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 320         RTE_FLOW_ITEM_TYPE_ETH,
 321         RTE_FLOW_ITEM_TYPE_IPV4,
 322         RTE_FLOW_ITEM_TYPE_UDP,
 323         RTE_FLOW_ITEM_TYPE_RAW,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_END,
 326 };
 327
 328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 329         RTE_FLOW_ITEM_TYPE_ETH,
 330         RTE_FLOW_ITEM_TYPE_IPV4,
 331         RTE_FLOW_ITEM_TYPE_UDP,
 332         RTE_FLOW_ITEM_TYPE_RAW,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_END,
 336 };
 337
 338 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 339         RTE_FLOW_ITEM_TYPE_ETH,
 340         RTE_FLOW_ITEM_TYPE_IPV4,
 341         RTE_FLOW_ITEM_TYPE_TCP,
 342         RTE_FLOW_ITEM_TYPE_RAW,
 343         RTE_FLOW_ITEM_TYPE_END,
 344 };
 345
 346 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 347         RTE_FLOW_ITEM_TYPE_ETH,
 348         RTE_FLOW_ITEM_TYPE_IPV4,
 349         RTE_FLOW_ITEM_TYPE_TCP,
 350         RTE_FLOW_ITEM_TYPE_RAW,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_END,
 353 };
 354
 355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 356         RTE_FLOW_ITEM_TYPE_ETH,
 357         RTE_FLOW_ITEM_TYPE_IPV4,
 358         RTE_FLOW_ITEM_TYPE_TCP,
 359         RTE_FLOW_ITEM_TYPE_RAW,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_END,
 363 };
 364
 365 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 366         RTE_FLOW_ITEM_TYPE_ETH,
 367         RTE_FLOW_ITEM_TYPE_IPV4,
 368         RTE_FLOW_ITEM_TYPE_SCTP,
 369         RTE_FLOW_ITEM_TYPE_RAW,
 370         RTE_FLOW_ITEM_TYPE_END,
 371 };
 372
 373 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 374         RTE_FLOW_ITEM_TYPE_ETH,
 375         RTE_FLOW_ITEM_TYPE_IPV4,
 376         RTE_FLOW_ITEM_TYPE_SCTP,
 377         RTE_FLOW_ITEM_TYPE_RAW,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_END,
 380 };
 381
 382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 383         RTE_FLOW_ITEM_TYPE_ETH,
 384         RTE_FLOW_ITEM_TYPE_IPV4,
 385         RTE_FLOW_ITEM_TYPE_SCTP,
 386         RTE_FLOW_ITEM_TYPE_RAW,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_END,
 390 };
 391
 392 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 393         RTE_FLOW_ITEM_TYPE_ETH,
 394         RTE_FLOW_ITEM_TYPE_IPV6,
 395         RTE_FLOW_ITEM_TYPE_RAW,
 396         RTE_FLOW_ITEM_TYPE_END,
 397 };
 398
 399 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 400         RTE_FLOW_ITEM_TYPE_ETH,
 401         RTE_FLOW_ITEM_TYPE_IPV6,
 402         RTE_FLOW_ITEM_TYPE_RAW,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_END,
 405 };
 406
 407 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 408         RTE_FLOW_ITEM_TYPE_ETH,
 409         RTE_FLOW_ITEM_TYPE_IPV6,
 410         RTE_FLOW_ITEM_TYPE_RAW,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_END,
 414 };
 415
 416 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 417         RTE_FLOW_ITEM_TYPE_ETH,
 418         RTE_FLOW_ITEM_TYPE_IPV6,
 419         RTE_FLOW_ITEM_TYPE_UDP,
 420         RTE_FLOW_ITEM_TYPE_RAW,
 421         RTE_FLOW_ITEM_TYPE_END,
 422 };
 423
 424 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 425         RTE_FLOW_ITEM_TYPE_ETH,
 426         RTE_FLOW_ITEM_TYPE_IPV6,
 427         RTE_FLOW_ITEM_TYPE_UDP,
 428         RTE_FLOW_ITEM_TYPE_RAW,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_END,
 431 };
 432
 433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 434         RTE_FLOW_ITEM_TYPE_ETH,
 435         RTE_FLOW_ITEM_TYPE_IPV6,
 436         RTE_FLOW_ITEM_TYPE_UDP,
 437         RTE_FLOW_ITEM_TYPE_RAW,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_END,
 441 };
 442
 443 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 444         RTE_FLOW_ITEM_TYPE_ETH,
 445         RTE_FLOW_ITEM_TYPE_IPV6,
 446         RTE_FLOW_ITEM_TYPE_TCP,
 447         RTE_FLOW_ITEM_TYPE_RAW,
 448         RTE_FLOW_ITEM_TYPE_END,
 449 };
 450
 451 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 452         RTE_FLOW_ITEM_TYPE_ETH,
 453         RTE_FLOW_ITEM_TYPE_IPV6,
 454         RTE_FLOW_ITEM_TYPE_TCP,
 455         RTE_FLOW_ITEM_TYPE_RAW,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_END,
 458 };
 459
 460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 461         RTE_FLOW_ITEM_TYPE_ETH,
 462         RTE_FLOW_ITEM_TYPE_IPV6,
 463         RTE_FLOW_ITEM_TYPE_TCP,
 464         RTE_FLOW_ITEM_TYPE_RAW,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_END,
 468 };
 469
 470 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 471         RTE_FLOW_ITEM_TYPE_ETH,
 472         RTE_FLOW_ITEM_TYPE_IPV6,
 473         RTE_FLOW_ITEM_TYPE_SCTP,
 474         RTE_FLOW_ITEM_TYPE_RAW,
 475         RTE_FLOW_ITEM_TYPE_END,
 476 };
 477
 478 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 479         RTE_FLOW_ITEM_TYPE_ETH,
 480         RTE_FLOW_ITEM_TYPE_IPV6,
 481         RTE_FLOW_ITEM_TYPE_SCTP,
 482         RTE_FLOW_ITEM_TYPE_RAW,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_END,
 485 };
 486
 487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 488         RTE_FLOW_ITEM_TYPE_ETH,
 489         RTE_FLOW_ITEM_TYPE_IPV6,
 490         RTE_FLOW_ITEM_TYPE_SCTP,
 491         RTE_FLOW_ITEM_TYPE_RAW,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_END,
 495 };
 496
 497 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 498         RTE_FLOW_ITEM_TYPE_ETH,
 499         RTE_FLOW_ITEM_TYPE_VLAN,
 500         RTE_FLOW_ITEM_TYPE_END,
 501 };
 502
 503 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 504         RTE_FLOW_ITEM_TYPE_ETH,
 505         RTE_FLOW_ITEM_TYPE_VLAN,
 506         RTE_FLOW_ITEM_TYPE_IPV4,
 507         RTE_FLOW_ITEM_TYPE_END,
 508 };
 509
 510 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 511         RTE_FLOW_ITEM_TYPE_ETH,
 512         RTE_FLOW_ITEM_TYPE_VLAN,
 513         RTE_FLOW_ITEM_TYPE_IPV4,
 514         RTE_FLOW_ITEM_TYPE_UDP,
 515         RTE_FLOW_ITEM_TYPE_END,
 516 };
 517
 518 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 519         RTE_FLOW_ITEM_TYPE_ETH,
 520         RTE_FLOW_ITEM_TYPE_VLAN,
 521         RTE_FLOW_ITEM_TYPE_IPV4,
 522         RTE_FLOW_ITEM_TYPE_TCP,
 523         RTE_FLOW_ITEM_TYPE_END,
 524 };
 525
 526 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 527         RTE_FLOW_ITEM_TYPE_ETH,
 528         RTE_FLOW_ITEM_TYPE_VLAN,
 529         RTE_FLOW_ITEM_TYPE_IPV4,
 530         RTE_FLOW_ITEM_TYPE_SCTP,
 531         RTE_FLOW_ITEM_TYPE_END,
 532 };
 533
 534 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 535         RTE_FLOW_ITEM_TYPE_ETH,
 536         RTE_FLOW_ITEM_TYPE_VLAN,
 537         RTE_FLOW_ITEM_TYPE_IPV6,
 538         RTE_FLOW_ITEM_TYPE_END,
 539 };
 540
 541 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 542         RTE_FLOW_ITEM_TYPE_ETH,
 543         RTE_FLOW_ITEM_TYPE_VLAN,
 544         RTE_FLOW_ITEM_TYPE_IPV6,
 545         RTE_FLOW_ITEM_TYPE_UDP,
 546         RTE_FLOW_ITEM_TYPE_END,
 547 };
 548
 549 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 550         RTE_FLOW_ITEM_TYPE_ETH,
 551         RTE_FLOW_ITEM_TYPE_VLAN,
 552         RTE_FLOW_ITEM_TYPE_IPV6,
 553         RTE_FLOW_ITEM_TYPE_TCP,
 554         RTE_FLOW_ITEM_TYPE_END,
 555 };
 556
 557 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 558         RTE_FLOW_ITEM_TYPE_ETH,
 559         RTE_FLOW_ITEM_TYPE_VLAN,
 560         RTE_FLOW_ITEM_TYPE_IPV6,
 561         RTE_FLOW_ITEM_TYPE_SCTP,
 562         RTE_FLOW_ITEM_TYPE_END,
 563 };
 564
 565 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 566         RTE_FLOW_ITEM_TYPE_ETH,
 567         RTE_FLOW_ITEM_TYPE_VLAN,
 568         RTE_FLOW_ITEM_TYPE_RAW,
 569         RTE_FLOW_ITEM_TYPE_END,
 570 };
 571
 572 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 573         RTE_FLOW_ITEM_TYPE_ETH,
 574         RTE_FLOW_ITEM_TYPE_VLAN,
 575         RTE_FLOW_ITEM_TYPE_RAW,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_END,
 578 };
 579
 580 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 581         RTE_FLOW_ITEM_TYPE_ETH,
 582         RTE_FLOW_ITEM_TYPE_VLAN,
 583         RTE_FLOW_ITEM_TYPE_RAW,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_END,
 587 };
 588
 589 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 590         RTE_FLOW_ITEM_TYPE_ETH,
 591         RTE_FLOW_ITEM_TYPE_VLAN,
 592         RTE_FLOW_ITEM_TYPE_IPV4,
 593         RTE_FLOW_ITEM_TYPE_RAW,
 594         RTE_FLOW_ITEM_TYPE_END,
 595 };
 596
 597 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 598         RTE_FLOW_ITEM_TYPE_ETH,
 599         RTE_FLOW_ITEM_TYPE_VLAN,
 600         RTE_FLOW_ITEM_TYPE_IPV4,
 601         RTE_FLOW_ITEM_TYPE_RAW,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_END,
 604 };
 605
 606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 607         RTE_FLOW_ITEM_TYPE_ETH,
 608         RTE_FLOW_ITEM_TYPE_VLAN,
 609         RTE_FLOW_ITEM_TYPE_IPV4,
 610         RTE_FLOW_ITEM_TYPE_RAW,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_END,
 614 };
 615
 616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 617         RTE_FLOW_ITEM_TYPE_ETH,
 618         RTE_FLOW_ITEM_TYPE_VLAN,
 619         RTE_FLOW_ITEM_TYPE_IPV4,
 620         RTE_FLOW_ITEM_TYPE_UDP,
 621         RTE_FLOW_ITEM_TYPE_RAW,
 622         RTE_FLOW_ITEM_TYPE_END,
 623 };
 624
 625 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 626         RTE_FLOW_ITEM_TYPE_ETH,
 627         RTE_FLOW_ITEM_TYPE_VLAN,
 628         RTE_FLOW_ITEM_TYPE_IPV4,
 629         RTE_FLOW_ITEM_TYPE_UDP,
 630         RTE_FLOW_ITEM_TYPE_RAW,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_END,
 633 };
 634
 635 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 636         RTE_FLOW_ITEM_TYPE_ETH,
 637         RTE_FLOW_ITEM_TYPE_VLAN,
 638         RTE_FLOW_ITEM_TYPE_IPV4,
 639         RTE_FLOW_ITEM_TYPE_UDP,
 640         RTE_FLOW_ITEM_TYPE_RAW,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_END,
 644 };
 645
 646 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 647         RTE_FLOW_ITEM_TYPE_ETH,
 648         RTE_FLOW_ITEM_TYPE_VLAN,
 649         RTE_FLOW_ITEM_TYPE_IPV4,
 650         RTE_FLOW_ITEM_TYPE_TCP,
 651         RTE_FLOW_ITEM_TYPE_RAW,
 652         RTE_FLOW_ITEM_TYPE_END,
 653 };
 654
 655 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 656         RTE_FLOW_ITEM_TYPE_ETH,
 657         RTE_FLOW_ITEM_TYPE_VLAN,
 658         RTE_FLOW_ITEM_TYPE_IPV4,
 659         RTE_FLOW_ITEM_TYPE_TCP,
 660         RTE_FLOW_ITEM_TYPE_RAW,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_END,
 663 };
 664
 665 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 666         RTE_FLOW_ITEM_TYPE_ETH,
 667         RTE_FLOW_ITEM_TYPE_VLAN,
 668         RTE_FLOW_ITEM_TYPE_IPV4,
 669         RTE_FLOW_ITEM_TYPE_TCP,
 670         RTE_FLOW_ITEM_TYPE_RAW,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_END,
 674 };
 675
 676 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 677         RTE_FLOW_ITEM_TYPE_ETH,
 678         RTE_FLOW_ITEM_TYPE_VLAN,
 679         RTE_FLOW_ITEM_TYPE_IPV4,
 680         RTE_FLOW_ITEM_TYPE_SCTP,
 681         RTE_FLOW_ITEM_TYPE_RAW,
 682         RTE_FLOW_ITEM_TYPE_END,
 683 };
 684
 685 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 686         RTE_FLOW_ITEM_TYPE_ETH,
 687         RTE_FLOW_ITEM_TYPE_VLAN,
 688         RTE_FLOW_ITEM_TYPE_IPV4,
 689         RTE_FLOW_ITEM_TYPE_SCTP,
 690         RTE_FLOW_ITEM_TYPE_RAW,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_END,
 693 };
 694
 695 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 696         RTE_FLOW_ITEM_TYPE_ETH,
 697         RTE_FLOW_ITEM_TYPE_VLAN,
 698         RTE_FLOW_ITEM_TYPE_IPV4,
 699         RTE_FLOW_ITEM_TYPE_SCTP,
 700         RTE_FLOW_ITEM_TYPE_RAW,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_END,
 704 };
 705
 706 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 707         RTE_FLOW_ITEM_TYPE_ETH,
 708         RTE_FLOW_ITEM_TYPE_VLAN,
 709         RTE_FLOW_ITEM_TYPE_IPV6,
 710         RTE_FLOW_ITEM_TYPE_RAW,
 711         RTE_FLOW_ITEM_TYPE_END,
 712 };
 713
 714 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 715         RTE_FLOW_ITEM_TYPE_ETH,
 716         RTE_FLOW_ITEM_TYPE_VLAN,
 717         RTE_FLOW_ITEM_TYPE_IPV6,
 718         RTE_FLOW_ITEM_TYPE_RAW,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_END,
 721 };
 722
 723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 724         RTE_FLOW_ITEM_TYPE_ETH,
 725         RTE_FLOW_ITEM_TYPE_VLAN,
 726         RTE_FLOW_ITEM_TYPE_IPV6,
 727         RTE_FLOW_ITEM_TYPE_RAW,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_END,
 731 };
 732
 733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 734         RTE_FLOW_ITEM_TYPE_ETH,
 735         RTE_FLOW_ITEM_TYPE_VLAN,
 736         RTE_FLOW_ITEM_TYPE_IPV6,
 737         RTE_FLOW_ITEM_TYPE_UDP,
 738         RTE_FLOW_ITEM_TYPE_RAW,
 739         RTE_FLOW_ITEM_TYPE_END,
 740 };
 741
 742 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 743         RTE_FLOW_ITEM_TYPE_ETH,
 744         RTE_FLOW_ITEM_TYPE_VLAN,
 745         RTE_FLOW_ITEM_TYPE_IPV6,
 746         RTE_FLOW_ITEM_TYPE_UDP,
 747         RTE_FLOW_ITEM_TYPE_RAW,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_END,
 750 };
 751
 752 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 753         RTE_FLOW_ITEM_TYPE_ETH,
 754         RTE_FLOW_ITEM_TYPE_VLAN,
 755         RTE_FLOW_ITEM_TYPE_IPV6,
 756         RTE_FLOW_ITEM_TYPE_UDP,
 757         RTE_FLOW_ITEM_TYPE_RAW,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_END,
 761 };
 762
 763 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 764         RTE_FLOW_ITEM_TYPE_ETH,
 765         RTE_FLOW_ITEM_TYPE_VLAN,
 766         RTE_FLOW_ITEM_TYPE_IPV6,
 767         RTE_FLOW_ITEM_TYPE_TCP,
 768         RTE_FLOW_ITEM_TYPE_RAW,
 769         RTE_FLOW_ITEM_TYPE_END,
 770 };
 771
 772 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 773         RTE_FLOW_ITEM_TYPE_ETH,
 774         RTE_FLOW_ITEM_TYPE_VLAN,
 775         RTE_FLOW_ITEM_TYPE_IPV6,
 776         RTE_FLOW_ITEM_TYPE_TCP,
 777         RTE_FLOW_ITEM_TYPE_RAW,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_END,
 780 };
 781
 782 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 783         RTE_FLOW_ITEM_TYPE_ETH,
 784         RTE_FLOW_ITEM_TYPE_VLAN,
 785         RTE_FLOW_ITEM_TYPE_IPV6,
 786         RTE_FLOW_ITEM_TYPE_TCP,
 787         RTE_FLOW_ITEM_TYPE_RAW,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_END,
 791 };
 792
 793 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 794         RTE_FLOW_ITEM_TYPE_ETH,
 795         RTE_FLOW_ITEM_TYPE_VLAN,
 796         RTE_FLOW_ITEM_TYPE_IPV6,
 797         RTE_FLOW_ITEM_TYPE_SCTP,
 798         RTE_FLOW_ITEM_TYPE_RAW,
 799         RTE_FLOW_ITEM_TYPE_END,
 800 };
 801
 802 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 803         RTE_FLOW_ITEM_TYPE_ETH,
 804         RTE_FLOW_ITEM_TYPE_VLAN,
 805         RTE_FLOW_ITEM_TYPE_IPV6,
 806         RTE_FLOW_ITEM_TYPE_SCTP,
 807         RTE_FLOW_ITEM_TYPE_RAW,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_END,
 810 };
 811
 812 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 813         RTE_FLOW_ITEM_TYPE_ETH,
 814         RTE_FLOW_ITEM_TYPE_VLAN,
 815         RTE_FLOW_ITEM_TYPE_IPV6,
 816         RTE_FLOW_ITEM_TYPE_SCTP,
 817         RTE_FLOW_ITEM_TYPE_RAW,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_END,
 821 };
 822
 823 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 824         RTE_FLOW_ITEM_TYPE_ETH,
 825         RTE_FLOW_ITEM_TYPE_IPV4,
 826         RTE_FLOW_ITEM_TYPE_VF,
 827         RTE_FLOW_ITEM_TYPE_END,
 828 };
 829
 830 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 831         RTE_FLOW_ITEM_TYPE_ETH,
 832         RTE_FLOW_ITEM_TYPE_IPV4,
 833         RTE_FLOW_ITEM_TYPE_UDP,
 834         RTE_FLOW_ITEM_TYPE_VF,
 835         RTE_FLOW_ITEM_TYPE_END,
 836 };
 837
 838 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 839         RTE_FLOW_ITEM_TYPE_ETH,
 840         RTE_FLOW_ITEM_TYPE_IPV4,
 841         RTE_FLOW_ITEM_TYPE_TCP,
 842         RTE_FLOW_ITEM_TYPE_VF,
 843         RTE_FLOW_ITEM_TYPE_END,
 844 };
 845
 846 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 847         RTE_FLOW_ITEM_TYPE_ETH,
 848         RTE_FLOW_ITEM_TYPE_IPV4,
 849         RTE_FLOW_ITEM_TYPE_SCTP,
 850         RTE_FLOW_ITEM_TYPE_VF,
 851         RTE_FLOW_ITEM_TYPE_END,
 852 };
 853
 854 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 855         RTE_FLOW_ITEM_TYPE_ETH,
 856         RTE_FLOW_ITEM_TYPE_IPV6,
 857         RTE_FLOW_ITEM_TYPE_VF,
 858         RTE_FLOW_ITEM_TYPE_END,
 859 };
 860
 861 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 862         RTE_FLOW_ITEM_TYPE_ETH,
 863         RTE_FLOW_ITEM_TYPE_IPV6,
 864         RTE_FLOW_ITEM_TYPE_UDP,
 865         RTE_FLOW_ITEM_TYPE_VF,
 866         RTE_FLOW_ITEM_TYPE_END,
 867 };
 868
 869 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 870         RTE_FLOW_ITEM_TYPE_ETH,
 871         RTE_FLOW_ITEM_TYPE_IPV6,
 872         RTE_FLOW_ITEM_TYPE_TCP,
 873         RTE_FLOW_ITEM_TYPE_VF,
 874         RTE_FLOW_ITEM_TYPE_END,
 875 };
 876
 877 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 878         RTE_FLOW_ITEM_TYPE_ETH,
 879         RTE_FLOW_ITEM_TYPE_IPV6,
 880         RTE_FLOW_ITEM_TYPE_SCTP,
 881         RTE_FLOW_ITEM_TYPE_VF,
 882         RTE_FLOW_ITEM_TYPE_END,
 883 };
 884
 885 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 886         RTE_FLOW_ITEM_TYPE_ETH,
 887         RTE_FLOW_ITEM_TYPE_RAW,
 888         RTE_FLOW_ITEM_TYPE_VF,
 889         RTE_FLOW_ITEM_TYPE_END,
 890 };
 891
 892 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 893         RTE_FLOW_ITEM_TYPE_ETH,
 894         RTE_FLOW_ITEM_TYPE_RAW,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_VF,
 897         RTE_FLOW_ITEM_TYPE_END,
 898 };
 899
 900 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 901         RTE_FLOW_ITEM_TYPE_ETH,
 902         RTE_FLOW_ITEM_TYPE_RAW,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_VF,
 906         RTE_FLOW_ITEM_TYPE_END,
 907 };
 908
 909 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 910         RTE_FLOW_ITEM_TYPE_ETH,
 911         RTE_FLOW_ITEM_TYPE_IPV4,
 912         RTE_FLOW_ITEM_TYPE_RAW,
 913         RTE_FLOW_ITEM_TYPE_VF,
 914         RTE_FLOW_ITEM_TYPE_END,
 915 };
 916
 917 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 918         RTE_FLOW_ITEM_TYPE_ETH,
 919         RTE_FLOW_ITEM_TYPE_IPV4,
 920         RTE_FLOW_ITEM_TYPE_RAW,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_VF,
 923         RTE_FLOW_ITEM_TYPE_END,
 924 };
 925
 926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 927         RTE_FLOW_ITEM_TYPE_ETH,
 928         RTE_FLOW_ITEM_TYPE_IPV4,
 929         RTE_FLOW_ITEM_TYPE_RAW,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_VF,
 933         RTE_FLOW_ITEM_TYPE_END,
 934 };
 935
 936 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 937         RTE_FLOW_ITEM_TYPE_ETH,
 938         RTE_FLOW_ITEM_TYPE_IPV4,
 939         RTE_FLOW_ITEM_TYPE_UDP,
 940         RTE_FLOW_ITEM_TYPE_RAW,
 941         RTE_FLOW_ITEM_TYPE_VF,
 942         RTE_FLOW_ITEM_TYPE_END,
 943 };
 944
 945 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 946         RTE_FLOW_ITEM_TYPE_ETH,
 947         RTE_FLOW_ITEM_TYPE_IPV4,
 948         RTE_FLOW_ITEM_TYPE_UDP,
 949         RTE_FLOW_ITEM_TYPE_RAW,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_VF,
 952         RTE_FLOW_ITEM_TYPE_END,
 953 };
 954
 955 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 956         RTE_FLOW_ITEM_TYPE_ETH,
 957         RTE_FLOW_ITEM_TYPE_IPV4,
 958         RTE_FLOW_ITEM_TYPE_UDP,
 959         RTE_FLOW_ITEM_TYPE_RAW,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_VF,
 963         RTE_FLOW_ITEM_TYPE_END,
 964 };
 965
 966 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 967         RTE_FLOW_ITEM_TYPE_ETH,
 968         RTE_FLOW_ITEM_TYPE_IPV4,
 969         RTE_FLOW_ITEM_TYPE_TCP,
 970         RTE_FLOW_ITEM_TYPE_RAW,
 971         RTE_FLOW_ITEM_TYPE_VF,
 972         RTE_FLOW_ITEM_TYPE_END,
 973 };
 974
 975 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 976         RTE_FLOW_ITEM_TYPE_ETH,
 977         RTE_FLOW_ITEM_TYPE_IPV4,
 978         RTE_FLOW_ITEM_TYPE_TCP,
 979         RTE_FLOW_ITEM_TYPE_RAW,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_VF,
 982         RTE_FLOW_ITEM_TYPE_END,
 983 };
 984
 985 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 986         RTE_FLOW_ITEM_TYPE_ETH,
 987         RTE_FLOW_ITEM_TYPE_IPV4,
 988         RTE_FLOW_ITEM_TYPE_TCP,
 989         RTE_FLOW_ITEM_TYPE_RAW,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_VF,
 993         RTE_FLOW_ITEM_TYPE_END,
 994 };
 995
 996 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 997         RTE_FLOW_ITEM_TYPE_ETH,
 998         RTE_FLOW_ITEM_TYPE_IPV4,
 999         RTE_FLOW_ITEM_TYPE_SCTP,
1000         RTE_FLOW_ITEM_TYPE_RAW,
1001         RTE_FLOW_ITEM_TYPE_VF,
1002         RTE_FLOW_ITEM_TYPE_END,
1003 };
1004
1005 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1006         RTE_FLOW_ITEM_TYPE_ETH,
1007         RTE_FLOW_ITEM_TYPE_IPV4,
1008         RTE_FLOW_ITEM_TYPE_SCTP,
1009         RTE_FLOW_ITEM_TYPE_RAW,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_VF,
1012         RTE_FLOW_ITEM_TYPE_END,
1013 };
1014
1015 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1016         RTE_FLOW_ITEM_TYPE_ETH,
1017         RTE_FLOW_ITEM_TYPE_IPV4,
1018         RTE_FLOW_ITEM_TYPE_SCTP,
1019         RTE_FLOW_ITEM_TYPE_RAW,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_VF,
1023         RTE_FLOW_ITEM_TYPE_END,
1024 };
1025
1026 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1027         RTE_FLOW_ITEM_TYPE_ETH,
1028         RTE_FLOW_ITEM_TYPE_IPV6,
1029         RTE_FLOW_ITEM_TYPE_RAW,
1030         RTE_FLOW_ITEM_TYPE_VF,
1031         RTE_FLOW_ITEM_TYPE_END,
1032 };
1033
1034 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1035         RTE_FLOW_ITEM_TYPE_ETH,
1036         RTE_FLOW_ITEM_TYPE_IPV6,
1037         RTE_FLOW_ITEM_TYPE_RAW,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_VF,
1040         RTE_FLOW_ITEM_TYPE_END,
1041 };
1042
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1044         RTE_FLOW_ITEM_TYPE_ETH,
1045         RTE_FLOW_ITEM_TYPE_IPV6,
1046         RTE_FLOW_ITEM_TYPE_RAW,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_VF,
1050         RTE_FLOW_ITEM_TYPE_END,
1051 };
1052
1053 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1054         RTE_FLOW_ITEM_TYPE_ETH,
1055         RTE_FLOW_ITEM_TYPE_IPV6,
1056         RTE_FLOW_ITEM_TYPE_UDP,
1057         RTE_FLOW_ITEM_TYPE_RAW,
1058         RTE_FLOW_ITEM_TYPE_VF,
1059         RTE_FLOW_ITEM_TYPE_END,
1060 };
1061
1062 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1063         RTE_FLOW_ITEM_TYPE_ETH,
1064         RTE_FLOW_ITEM_TYPE_IPV6,
1065         RTE_FLOW_ITEM_TYPE_UDP,
1066         RTE_FLOW_ITEM_TYPE_RAW,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_VF,
1069         RTE_FLOW_ITEM_TYPE_END,
1070 };
1071
1072 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1073         RTE_FLOW_ITEM_TYPE_ETH,
1074         RTE_FLOW_ITEM_TYPE_IPV6,
1075         RTE_FLOW_ITEM_TYPE_UDP,
1076         RTE_FLOW_ITEM_TYPE_RAW,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_VF,
1080         RTE_FLOW_ITEM_TYPE_END,
1081 };
1082
1083 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1084         RTE_FLOW_ITEM_TYPE_ETH,
1085         RTE_FLOW_ITEM_TYPE_IPV6,
1086         RTE_FLOW_ITEM_TYPE_TCP,
1087         RTE_FLOW_ITEM_TYPE_RAW,
1088         RTE_FLOW_ITEM_TYPE_VF,
1089         RTE_FLOW_ITEM_TYPE_END,
1090 };
1091
1092 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1093         RTE_FLOW_ITEM_TYPE_ETH,
1094         RTE_FLOW_ITEM_TYPE_IPV6,
1095         RTE_FLOW_ITEM_TYPE_TCP,
1096         RTE_FLOW_ITEM_TYPE_RAW,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_VF,
1099         RTE_FLOW_ITEM_TYPE_END,
1100 };
1101
1102 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1103         RTE_FLOW_ITEM_TYPE_ETH,
1104         RTE_FLOW_ITEM_TYPE_IPV6,
1105         RTE_FLOW_ITEM_TYPE_TCP,
1106         RTE_FLOW_ITEM_TYPE_RAW,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_VF,
1110         RTE_FLOW_ITEM_TYPE_END,
1111 };
1112
1113 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1114         RTE_FLOW_ITEM_TYPE_ETH,
1115         RTE_FLOW_ITEM_TYPE_IPV6,
1116         RTE_FLOW_ITEM_TYPE_SCTP,
1117         RTE_FLOW_ITEM_TYPE_RAW,
1118         RTE_FLOW_ITEM_TYPE_VF,
1119         RTE_FLOW_ITEM_TYPE_END,
1120 };
1121
1122 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1123         RTE_FLOW_ITEM_TYPE_ETH,
1124         RTE_FLOW_ITEM_TYPE_IPV6,
1125         RTE_FLOW_ITEM_TYPE_SCTP,
1126         RTE_FLOW_ITEM_TYPE_RAW,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_VF,
1129         RTE_FLOW_ITEM_TYPE_END,
1130 };
1131
1132 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1133         RTE_FLOW_ITEM_TYPE_ETH,
1134         RTE_FLOW_ITEM_TYPE_IPV6,
1135         RTE_FLOW_ITEM_TYPE_SCTP,
1136         RTE_FLOW_ITEM_TYPE_RAW,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_VF,
1140         RTE_FLOW_ITEM_TYPE_END,
1141 };
1142
1143 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1144         RTE_FLOW_ITEM_TYPE_ETH,
1145         RTE_FLOW_ITEM_TYPE_VLAN,
1146         RTE_FLOW_ITEM_TYPE_VF,
1147         RTE_FLOW_ITEM_TYPE_END,
1148 };
1149
1150 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1151         RTE_FLOW_ITEM_TYPE_ETH,
1152         RTE_FLOW_ITEM_TYPE_VLAN,
1153         RTE_FLOW_ITEM_TYPE_IPV4,
1154         RTE_FLOW_ITEM_TYPE_VF,
1155         RTE_FLOW_ITEM_TYPE_END,
1156 };
1157
1158 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1159         RTE_FLOW_ITEM_TYPE_ETH,
1160         RTE_FLOW_ITEM_TYPE_VLAN,
1161         RTE_FLOW_ITEM_TYPE_IPV4,
1162         RTE_FLOW_ITEM_TYPE_UDP,
1163         RTE_FLOW_ITEM_TYPE_VF,
1164         RTE_FLOW_ITEM_TYPE_END,
1165 };
1166
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1168         RTE_FLOW_ITEM_TYPE_ETH,
1169         RTE_FLOW_ITEM_TYPE_VLAN,
1170         RTE_FLOW_ITEM_TYPE_IPV4,
1171         RTE_FLOW_ITEM_TYPE_TCP,
1172         RTE_FLOW_ITEM_TYPE_VF,
1173         RTE_FLOW_ITEM_TYPE_END,
1174 };
1175
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1177         RTE_FLOW_ITEM_TYPE_ETH,
1178         RTE_FLOW_ITEM_TYPE_VLAN,
1179         RTE_FLOW_ITEM_TYPE_IPV4,
1180         RTE_FLOW_ITEM_TYPE_SCTP,
1181         RTE_FLOW_ITEM_TYPE_VF,
1182         RTE_FLOW_ITEM_TYPE_END,
1183 };
1184
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1186         RTE_FLOW_ITEM_TYPE_ETH,
1187         RTE_FLOW_ITEM_TYPE_VLAN,
1188         RTE_FLOW_ITEM_TYPE_IPV6,
1189         RTE_FLOW_ITEM_TYPE_VF,
1190         RTE_FLOW_ITEM_TYPE_END,
1191 };
1192
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1194         RTE_FLOW_ITEM_TYPE_ETH,
1195         RTE_FLOW_ITEM_TYPE_VLAN,
1196         RTE_FLOW_ITEM_TYPE_IPV6,
1197         RTE_FLOW_ITEM_TYPE_UDP,
1198         RTE_FLOW_ITEM_TYPE_VF,
1199         RTE_FLOW_ITEM_TYPE_END,
1200 };
1201
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1203         RTE_FLOW_ITEM_TYPE_ETH,
1204         RTE_FLOW_ITEM_TYPE_VLAN,
1205         RTE_FLOW_ITEM_TYPE_IPV6,
1206         RTE_FLOW_ITEM_TYPE_TCP,
1207         RTE_FLOW_ITEM_TYPE_VF,
1208         RTE_FLOW_ITEM_TYPE_END,
1209 };
1210
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1212         RTE_FLOW_ITEM_TYPE_ETH,
1213         RTE_FLOW_ITEM_TYPE_VLAN,
1214         RTE_FLOW_ITEM_TYPE_IPV6,
1215         RTE_FLOW_ITEM_TYPE_SCTP,
1216         RTE_FLOW_ITEM_TYPE_VF,
1217         RTE_FLOW_ITEM_TYPE_END,
1218 };
1219
1220 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1221         RTE_FLOW_ITEM_TYPE_ETH,
1222         RTE_FLOW_ITEM_TYPE_VLAN,
1223         RTE_FLOW_ITEM_TYPE_RAW,
1224         RTE_FLOW_ITEM_TYPE_VF,
1225         RTE_FLOW_ITEM_TYPE_END,
1226 };
1227
1228 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1229         RTE_FLOW_ITEM_TYPE_ETH,
1230         RTE_FLOW_ITEM_TYPE_VLAN,
1231         RTE_FLOW_ITEM_TYPE_RAW,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_VF,
1234         RTE_FLOW_ITEM_TYPE_END,
1235 };
1236
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1238         RTE_FLOW_ITEM_TYPE_ETH,
1239         RTE_FLOW_ITEM_TYPE_VLAN,
1240         RTE_FLOW_ITEM_TYPE_RAW,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_VF,
1244         RTE_FLOW_ITEM_TYPE_END,
1245 };
1246
1247 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1248         RTE_FLOW_ITEM_TYPE_ETH,
1249         RTE_FLOW_ITEM_TYPE_VLAN,
1250         RTE_FLOW_ITEM_TYPE_IPV4,
1251         RTE_FLOW_ITEM_TYPE_RAW,
1252         RTE_FLOW_ITEM_TYPE_VF,
1253         RTE_FLOW_ITEM_TYPE_END,
1254 };
1255
1256 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1257         RTE_FLOW_ITEM_TYPE_ETH,
1258         RTE_FLOW_ITEM_TYPE_VLAN,
1259         RTE_FLOW_ITEM_TYPE_IPV4,
1260         RTE_FLOW_ITEM_TYPE_RAW,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_VF,
1263         RTE_FLOW_ITEM_TYPE_END,
1264 };
1265
1266 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1267         RTE_FLOW_ITEM_TYPE_ETH,
1268         RTE_FLOW_ITEM_TYPE_VLAN,
1269         RTE_FLOW_ITEM_TYPE_IPV4,
1270         RTE_FLOW_ITEM_TYPE_RAW,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_VF,
1274         RTE_FLOW_ITEM_TYPE_END,
1275 };
1276
1277 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1278         RTE_FLOW_ITEM_TYPE_ETH,
1279         RTE_FLOW_ITEM_TYPE_VLAN,
1280         RTE_FLOW_ITEM_TYPE_IPV4,
1281         RTE_FLOW_ITEM_TYPE_UDP,
1282         RTE_FLOW_ITEM_TYPE_RAW,
1283         RTE_FLOW_ITEM_TYPE_VF,
1284         RTE_FLOW_ITEM_TYPE_END,
1285 };
1286
1287 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1288         RTE_FLOW_ITEM_TYPE_ETH,
1289         RTE_FLOW_ITEM_TYPE_VLAN,
1290         RTE_FLOW_ITEM_TYPE_IPV4,
1291         RTE_FLOW_ITEM_TYPE_UDP,
1292         RTE_FLOW_ITEM_TYPE_RAW,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_VF,
1295         RTE_FLOW_ITEM_TYPE_END,
1296 };
1297
1298 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1299         RTE_FLOW_ITEM_TYPE_ETH,
1300         RTE_FLOW_ITEM_TYPE_VLAN,
1301         RTE_FLOW_ITEM_TYPE_IPV4,
1302         RTE_FLOW_ITEM_TYPE_UDP,
1303         RTE_FLOW_ITEM_TYPE_RAW,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_VF,
1307         RTE_FLOW_ITEM_TYPE_END,
1308 };
1309
1310 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1311         RTE_FLOW_ITEM_TYPE_ETH,
1312         RTE_FLOW_ITEM_TYPE_VLAN,
1313         RTE_FLOW_ITEM_TYPE_IPV4,
1314         RTE_FLOW_ITEM_TYPE_TCP,
1315         RTE_FLOW_ITEM_TYPE_RAW,
1316         RTE_FLOW_ITEM_TYPE_VF,
1317         RTE_FLOW_ITEM_TYPE_END,
1318 };
1319
1320 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1321         RTE_FLOW_ITEM_TYPE_ETH,
1322         RTE_FLOW_ITEM_TYPE_VLAN,
1323         RTE_FLOW_ITEM_TYPE_IPV4,
1324         RTE_FLOW_ITEM_TYPE_TCP,
1325         RTE_FLOW_ITEM_TYPE_RAW,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_VF,
1328         RTE_FLOW_ITEM_TYPE_END,
1329 };
1330
1331 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1332         RTE_FLOW_ITEM_TYPE_ETH,
1333         RTE_FLOW_ITEM_TYPE_VLAN,
1334         RTE_FLOW_ITEM_TYPE_IPV4,
1335         RTE_FLOW_ITEM_TYPE_TCP,
1336         RTE_FLOW_ITEM_TYPE_RAW,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_VF,
1340         RTE_FLOW_ITEM_TYPE_END,
1341 };
1342
1343 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1344         RTE_FLOW_ITEM_TYPE_ETH,
1345         RTE_FLOW_ITEM_TYPE_VLAN,
1346         RTE_FLOW_ITEM_TYPE_IPV4,
1347         RTE_FLOW_ITEM_TYPE_SCTP,
1348         RTE_FLOW_ITEM_TYPE_RAW,
1349         RTE_FLOW_ITEM_TYPE_VF,
1350         RTE_FLOW_ITEM_TYPE_END,
1351 };
1352
1353 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1354         RTE_FLOW_ITEM_TYPE_ETH,
1355         RTE_FLOW_ITEM_TYPE_VLAN,
1356         RTE_FLOW_ITEM_TYPE_IPV4,
1357         RTE_FLOW_ITEM_TYPE_SCTP,
1358         RTE_FLOW_ITEM_TYPE_RAW,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_VF,
1361         RTE_FLOW_ITEM_TYPE_END,
1362 };
1363
1364 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1365         RTE_FLOW_ITEM_TYPE_ETH,
1366         RTE_FLOW_ITEM_TYPE_VLAN,
1367         RTE_FLOW_ITEM_TYPE_IPV4,
1368         RTE_FLOW_ITEM_TYPE_SCTP,
1369         RTE_FLOW_ITEM_TYPE_RAW,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_VF,
1373         RTE_FLOW_ITEM_TYPE_END,
1374 };
1375
1376 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1377         RTE_FLOW_ITEM_TYPE_ETH,
1378         RTE_FLOW_ITEM_TYPE_VLAN,
1379         RTE_FLOW_ITEM_TYPE_IPV6,
1380         RTE_FLOW_ITEM_TYPE_RAW,
1381         RTE_FLOW_ITEM_TYPE_VF,
1382         RTE_FLOW_ITEM_TYPE_END,
1383 };
1384
1385 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1386         RTE_FLOW_ITEM_TYPE_ETH,
1387         RTE_FLOW_ITEM_TYPE_VLAN,
1388         RTE_FLOW_ITEM_TYPE_IPV6,
1389         RTE_FLOW_ITEM_TYPE_RAW,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_VF,
1392         RTE_FLOW_ITEM_TYPE_END,
1393 };
1394
1395 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1396         RTE_FLOW_ITEM_TYPE_ETH,
1397         RTE_FLOW_ITEM_TYPE_VLAN,
1398         RTE_FLOW_ITEM_TYPE_IPV6,
1399         RTE_FLOW_ITEM_TYPE_RAW,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_VF,
1403         RTE_FLOW_ITEM_TYPE_END,
1404 };
1405
1406 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1407         RTE_FLOW_ITEM_TYPE_ETH,
1408         RTE_FLOW_ITEM_TYPE_VLAN,
1409         RTE_FLOW_ITEM_TYPE_IPV6,
1410         RTE_FLOW_ITEM_TYPE_UDP,
1411         RTE_FLOW_ITEM_TYPE_RAW,
1412         RTE_FLOW_ITEM_TYPE_VF,
1413         RTE_FLOW_ITEM_TYPE_END,
1414 };
1415
1416 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1417         RTE_FLOW_ITEM_TYPE_ETH,
1418         RTE_FLOW_ITEM_TYPE_VLAN,
1419         RTE_FLOW_ITEM_TYPE_IPV6,
1420         RTE_FLOW_ITEM_TYPE_UDP,
1421         RTE_FLOW_ITEM_TYPE_RAW,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_VF,
1424         RTE_FLOW_ITEM_TYPE_END,
1425 };
1426
1427 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1428         RTE_FLOW_ITEM_TYPE_ETH,
1429         RTE_FLOW_ITEM_TYPE_VLAN,
1430         RTE_FLOW_ITEM_TYPE_IPV6,
1431         RTE_FLOW_ITEM_TYPE_UDP,
1432         RTE_FLOW_ITEM_TYPE_RAW,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_VF,
1436         RTE_FLOW_ITEM_TYPE_END,
1437 };
1438
1439 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1440         RTE_FLOW_ITEM_TYPE_ETH,
1441         RTE_FLOW_ITEM_TYPE_VLAN,
1442         RTE_FLOW_ITEM_TYPE_IPV6,
1443         RTE_FLOW_ITEM_TYPE_TCP,
1444         RTE_FLOW_ITEM_TYPE_RAW,
1445         RTE_FLOW_ITEM_TYPE_VF,
1446         RTE_FLOW_ITEM_TYPE_END,
1447 };
1448
1449 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1450         RTE_FLOW_ITEM_TYPE_ETH,
1451         RTE_FLOW_ITEM_TYPE_VLAN,
1452         RTE_FLOW_ITEM_TYPE_IPV6,
1453         RTE_FLOW_ITEM_TYPE_TCP,
1454         RTE_FLOW_ITEM_TYPE_RAW,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_VF,
1457         RTE_FLOW_ITEM_TYPE_END,
1458 };
1459
1460 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1461         RTE_FLOW_ITEM_TYPE_ETH,
1462         RTE_FLOW_ITEM_TYPE_VLAN,
1463         RTE_FLOW_ITEM_TYPE_IPV6,
1464         RTE_FLOW_ITEM_TYPE_TCP,
1465         RTE_FLOW_ITEM_TYPE_RAW,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_VF,
1469         RTE_FLOW_ITEM_TYPE_END,
1470 };
1471
1472 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1473         RTE_FLOW_ITEM_TYPE_ETH,
1474         RTE_FLOW_ITEM_TYPE_VLAN,
1475         RTE_FLOW_ITEM_TYPE_IPV6,
1476         RTE_FLOW_ITEM_TYPE_SCTP,
1477         RTE_FLOW_ITEM_TYPE_RAW,
1478         RTE_FLOW_ITEM_TYPE_VF,
1479         RTE_FLOW_ITEM_TYPE_END,
1480 };
1481
1482 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1483         RTE_FLOW_ITEM_TYPE_ETH,
1484         RTE_FLOW_ITEM_TYPE_VLAN,
1485         RTE_FLOW_ITEM_TYPE_IPV6,
1486         RTE_FLOW_ITEM_TYPE_SCTP,
1487         RTE_FLOW_ITEM_TYPE_RAW,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_VF,
1490         RTE_FLOW_ITEM_TYPE_END,
1491 };
1492
1493 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1494         RTE_FLOW_ITEM_TYPE_ETH,
1495         RTE_FLOW_ITEM_TYPE_VLAN,
1496         RTE_FLOW_ITEM_TYPE_IPV6,
1497         RTE_FLOW_ITEM_TYPE_SCTP,
1498         RTE_FLOW_ITEM_TYPE_RAW,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_VF,
1502         RTE_FLOW_ITEM_TYPE_END,
1503 };
1504
1505 /* Pattern matched tunnel filter */
1506 static enum rte_flow_item_type pattern_vxlan_1[] = {
1507         RTE_FLOW_ITEM_TYPE_ETH,
1508         RTE_FLOW_ITEM_TYPE_IPV4,
1509         RTE_FLOW_ITEM_TYPE_UDP,
1510         RTE_FLOW_ITEM_TYPE_VXLAN,
1511         RTE_FLOW_ITEM_TYPE_ETH,
1512         RTE_FLOW_ITEM_TYPE_END,
1513 };
1514
1515 static enum rte_flow_item_type pattern_vxlan_2[] = {
1516         RTE_FLOW_ITEM_TYPE_ETH,
1517         RTE_FLOW_ITEM_TYPE_IPV6,
1518         RTE_FLOW_ITEM_TYPE_UDP,
1519         RTE_FLOW_ITEM_TYPE_VXLAN,
1520         RTE_FLOW_ITEM_TYPE_ETH,
1521         RTE_FLOW_ITEM_TYPE_END,
1522 };
1523
1524 static enum rte_flow_item_type pattern_vxlan_3[] = {
1525         RTE_FLOW_ITEM_TYPE_ETH,
1526         RTE_FLOW_ITEM_TYPE_IPV4,
1527         RTE_FLOW_ITEM_TYPE_UDP,
1528         RTE_FLOW_ITEM_TYPE_VXLAN,
1529         RTE_FLOW_ITEM_TYPE_ETH,
1530         RTE_FLOW_ITEM_TYPE_VLAN,
1531         RTE_FLOW_ITEM_TYPE_END,
1532 };
1533
1534 static enum rte_flow_item_type pattern_vxlan_4[] = {
1535         RTE_FLOW_ITEM_TYPE_ETH,
1536         RTE_FLOW_ITEM_TYPE_IPV6,
1537         RTE_FLOW_ITEM_TYPE_UDP,
1538         RTE_FLOW_ITEM_TYPE_VXLAN,
1539         RTE_FLOW_ITEM_TYPE_ETH,
1540         RTE_FLOW_ITEM_TYPE_VLAN,
1541         RTE_FLOW_ITEM_TYPE_END,
1542 };
1543
1544 static enum rte_flow_item_type pattern_nvgre_1[] = {
1545         RTE_FLOW_ITEM_TYPE_ETH,
1546         RTE_FLOW_ITEM_TYPE_IPV4,
1547         RTE_FLOW_ITEM_TYPE_NVGRE,
1548         RTE_FLOW_ITEM_TYPE_ETH,
1549         RTE_FLOW_ITEM_TYPE_END,
1550 };
1551
1552 static enum rte_flow_item_type pattern_nvgre_2[] = {
1553         RTE_FLOW_ITEM_TYPE_ETH,
1554         RTE_FLOW_ITEM_TYPE_IPV6,
1555         RTE_FLOW_ITEM_TYPE_NVGRE,
1556         RTE_FLOW_ITEM_TYPE_ETH,
1557         RTE_FLOW_ITEM_TYPE_END,
1558 };
1559
1560 static enum rte_flow_item_type pattern_nvgre_3[] = {
1561         RTE_FLOW_ITEM_TYPE_ETH,
1562         RTE_FLOW_ITEM_TYPE_IPV4,
1563         RTE_FLOW_ITEM_TYPE_NVGRE,
1564         RTE_FLOW_ITEM_TYPE_ETH,
1565         RTE_FLOW_ITEM_TYPE_VLAN,
1566         RTE_FLOW_ITEM_TYPE_END,
1567 };
1568
1569 static enum rte_flow_item_type pattern_nvgre_4[] = {
1570         RTE_FLOW_ITEM_TYPE_ETH,
1571         RTE_FLOW_ITEM_TYPE_IPV6,
1572         RTE_FLOW_ITEM_TYPE_NVGRE,
1573         RTE_FLOW_ITEM_TYPE_ETH,
1574         RTE_FLOW_ITEM_TYPE_VLAN,
1575         RTE_FLOW_ITEM_TYPE_END,
1576 };
1577
1578 static enum rte_flow_item_type pattern_mpls_1[] = {
1579         RTE_FLOW_ITEM_TYPE_ETH,
1580         RTE_FLOW_ITEM_TYPE_IPV4,
1581         RTE_FLOW_ITEM_TYPE_UDP,
1582         RTE_FLOW_ITEM_TYPE_MPLS,
1583         RTE_FLOW_ITEM_TYPE_END,
1584 };
1585
1586 static enum rte_flow_item_type pattern_mpls_2[] = {
1587         RTE_FLOW_ITEM_TYPE_ETH,
1588         RTE_FLOW_ITEM_TYPE_IPV6,
1589         RTE_FLOW_ITEM_TYPE_UDP,
1590         RTE_FLOW_ITEM_TYPE_MPLS,
1591         RTE_FLOW_ITEM_TYPE_END,
1592 };
1593
1594 static enum rte_flow_item_type pattern_mpls_3[] = {
1595         RTE_FLOW_ITEM_TYPE_ETH,
1596         RTE_FLOW_ITEM_TYPE_IPV4,
1597         RTE_FLOW_ITEM_TYPE_GRE,
1598         RTE_FLOW_ITEM_TYPE_MPLS,
1599         RTE_FLOW_ITEM_TYPE_END,
1600 };
1601
1602 static enum rte_flow_item_type pattern_mpls_4[] = {
1603         RTE_FLOW_ITEM_TYPE_ETH,
1604         RTE_FLOW_ITEM_TYPE_IPV6,
1605         RTE_FLOW_ITEM_TYPE_GRE,
1606         RTE_FLOW_ITEM_TYPE_MPLS,
1607         RTE_FLOW_ITEM_TYPE_END,
1608 };
1609
1610 static enum rte_flow_item_type pattern_qinq_1[] = {
1611         RTE_FLOW_ITEM_TYPE_ETH,
1612         RTE_FLOW_ITEM_TYPE_VLAN,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_END,
1615 };
1616
1617 static enum rte_flow_item_type pattern_fdir_ipv4_l2tpv3oip[] = {
1618         RTE_FLOW_ITEM_TYPE_ETH,
1619         RTE_FLOW_ITEM_TYPE_IPV4,
1620         RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1621         RTE_FLOW_ITEM_TYPE_END,
1622 };
1623
1624 static enum rte_flow_item_type pattern_fdir_ipv6_l2tpv3oip[] = {
1625         RTE_FLOW_ITEM_TYPE_ETH,
1626         RTE_FLOW_ITEM_TYPE_IPV6,
1627         RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1628         RTE_FLOW_ITEM_TYPE_END,
1629 };
1630
1631 static enum rte_flow_item_type pattern_fdir_ipv4_esp[] = {
1632         RTE_FLOW_ITEM_TYPE_ETH,
1633         RTE_FLOW_ITEM_TYPE_IPV4,
1634         RTE_FLOW_ITEM_TYPE_ESP,
1635         RTE_FLOW_ITEM_TYPE_END,
1636 };
1637
1638 static enum rte_flow_item_type pattern_fdir_ipv6_esp[] = {
1639         RTE_FLOW_ITEM_TYPE_ETH,
1640         RTE_FLOW_ITEM_TYPE_IPV6,
1641         RTE_FLOW_ITEM_TYPE_ESP,
1642         RTE_FLOW_ITEM_TYPE_END,
1643 };
1644
1645 static enum rte_flow_item_type pattern_fdir_ipv4_udp_esp[] = {
1646         RTE_FLOW_ITEM_TYPE_ETH,
1647         RTE_FLOW_ITEM_TYPE_IPV4,
1648         RTE_FLOW_ITEM_TYPE_UDP,
1649         RTE_FLOW_ITEM_TYPE_ESP,
1650         RTE_FLOW_ITEM_TYPE_END,
1651 };
1652
1653 static enum rte_flow_item_type pattern_fdir_ipv6_udp_esp[] = {
1654         RTE_FLOW_ITEM_TYPE_ETH,
1655         RTE_FLOW_ITEM_TYPE_IPV6,
1656         RTE_FLOW_ITEM_TYPE_UDP,
1657         RTE_FLOW_ITEM_TYPE_ESP,
1658         RTE_FLOW_ITEM_TYPE_END,
1659 };
1660
1661 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1662         /* Ethertype */
1663         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1664         /* FDIR - support default flow type without flexible payload*/
1665         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1666         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1667         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1668         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_ipv4_esp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_ipv4_udp_esp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_ipv6_esp, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_ipv6_udp_esp, i40e_flow_parse_fdir_filter },
1686         /* FDIR - support default flow type with flexible payload */
1687         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1704         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1705         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1714         /* FDIR - support single vlan input set */
1715         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1751         /* FDIR - support VF item */
1752         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1776         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1777         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1778         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1779         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1780         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1781         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1782         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1783         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1784         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1785         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1786         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1787         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1788         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1789         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1790         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1791         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1792         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1793         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1794         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1795         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1796         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1797         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1798         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1799         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1800         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1801         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1802         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1803         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1804         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1805         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1806         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1807         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1808         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1809         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1810         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1811         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1812         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1813         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1814         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1815         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1816         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1817         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1818         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1819         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1820         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1821         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1822         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1823         /* VXLAN */
1824         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1825         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1826         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1827         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1828         /* NVGRE */
1829         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1830         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1831         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1832         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1833         /* MPLSoUDP & MPLSoGRE */
1834         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1835         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1836         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1837         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1838         /* GTP-C & GTP-U */
1839         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1840         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1841         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1842         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1843         /* QINQ */
1844         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1845         /* L2TPv3 over IP */
1846         { pattern_fdir_ipv4_l2tpv3oip, i40e_flow_parse_fdir_filter },
1847         { pattern_fdir_ipv6_l2tpv3oip, i40e_flow_parse_fdir_filter },
1848 };
1849
1850 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1851         do {                                                            \
1852                 act = actions + index;                                  \
1853                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1854                         index++;                                        \
1855                         act = actions + index;                          \
1856                 }                                                       \
1857         } while (0)
1858
1859 /* Find the first VOID or non-VOID item pointer */
1860 static const struct rte_flow_item *
1861 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1862 {
1863         bool is_find;
1864
1865         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1866                 if (is_void)
1867                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1868                 else
1869                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1870                 if (is_find)
1871                         break;
1872                 item++;
1873         }
1874         return item;
1875 }
1876
1877 /* Skip all VOID items of the pattern */
1878 static void
1879 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1880                             const struct rte_flow_item *pattern)
1881 {
1882         uint32_t cpy_count = 0;
1883         const struct rte_flow_item *pb = pattern, *pe = pattern;
1884
1885         for (;;) {
1886                 /* Find a non-void item first */
1887                 pb = i40e_find_first_item(pb, false);
1888                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1889                         pe = pb;
1890                         break;
1891                 }
1892
1893                 /* Find a void item */
1894                 pe = i40e_find_first_item(pb + 1, true);
1895
1896                 cpy_count = pe - pb;
1897                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1898
1899                 items += cpy_count;
1900
1901                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1902                         pb = pe;
1903                         break;
1904                 }
1905
1906                 pb = pe + 1;
1907         }
1908         /* Copy the END item. */
1909         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1910 }
1911
1912 /* Check if the pattern matches a supported item type array */
1913 static bool
1914 i40e_match_pattern(enum rte_flow_item_type *item_array,
1915                    struct rte_flow_item *pattern)
1916 {
1917         struct rte_flow_item *item = pattern;
1918
1919         while ((*item_array == item->type) &&
1920                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1921                 item_array++;
1922                 item++;
1923         }
1924
1925         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1926                 item->type == RTE_FLOW_ITEM_TYPE_END);
1927 }
1928
1929 /* Find if there's parse filter function matched */
1930 static parse_filter_t
1931 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1932 {
1933         parse_filter_t parse_filter = NULL;
1934         uint8_t i = *idx;
1935
1936         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1937                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1938                                         pattern)) {
1939                         parse_filter = i40e_supported_patterns[i].parse_filter;
1940                         break;
1941                 }
1942         }
1943
1944         *idx = ++i;
1945
1946         return parse_filter;
1947 }
1948
1949 /* Parse attributes */
1950 static int
1951 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1952                      struct rte_flow_error *error)
1953 {
1954         /* Must be input direction */
1955         if (!attr->ingress) {
1956                 rte_flow_error_set(error, EINVAL,
1957                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1958                                    attr, "Only support ingress.");
1959                 return -rte_errno;
1960         }
1961
1962         /* Not supported */
1963         if (attr->egress) {
1964                 rte_flow_error_set(error, EINVAL,
1965                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1966                                    attr, "Not support egress.");
1967                 return -rte_errno;
1968         }
1969
1970         /* Not supported */
1971         if (attr->priority) {
1972                 rte_flow_error_set(error, EINVAL,
1973                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1974                                    attr, "Not support priority.");
1975                 return -rte_errno;
1976         }
1977
1978         /* Not supported */
1979         if (attr->group) {
1980                 rte_flow_error_set(error, EINVAL,
1981                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1982                                    attr, "Not support group.");
1983                 return -rte_errno;
1984         }
1985
1986         return 0;
1987 }
1988
1989 static uint16_t
1990 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1991 {
1992         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993         int qinq = dev->data->dev_conf.rxmode.offloads &
1994                 DEV_RX_OFFLOAD_VLAN_EXTEND;
1995         uint64_t reg_r = 0;
1996         uint16_t reg_id;
1997         uint16_t tpid;
1998
1999         if (qinq)
2000                 reg_id = 2;
2001         else
2002                 reg_id = 3;
2003
2004         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2005                                     &reg_r, NULL);
2006
2007         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
2008
2009         return tpid;
2010 }
2011
2012 /* 1. Last in item should be NULL as range is not supported.
2013  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
2014  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
2015  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
2016  *    FF:FF:FF:FF:FF:FF
2017  * 5. Ether_type mask should be 0xFFFF.
2018  */
2019 static int
2020 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
2021                                   const struct rte_flow_item *pattern,
2022                                   struct rte_flow_error *error,
2023                                   struct rte_eth_ethertype_filter *filter)
2024 {
2025         const struct rte_flow_item *item = pattern;
2026         const struct rte_flow_item_eth *eth_spec;
2027         const struct rte_flow_item_eth *eth_mask;
2028         enum rte_flow_item_type item_type;
2029         uint16_t outer_tpid;
2030
2031         outer_tpid = i40e_get_outer_vlan(dev);
2032
2033         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2034                 if (item->last) {
2035                         rte_flow_error_set(error, EINVAL,
2036                                            RTE_FLOW_ERROR_TYPE_ITEM,
2037                                            item,
2038                                            "Not support range");
2039                         return -rte_errno;
2040                 }
2041                 item_type = item->type;
2042                 switch (item_type) {
2043                 case RTE_FLOW_ITEM_TYPE_ETH:
2044                         eth_spec = item->spec;
2045                         eth_mask = item->mask;
2046                         /* Get the MAC info. */
2047                         if (!eth_spec || !eth_mask) {
2048                                 rte_flow_error_set(error, EINVAL,
2049                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2050                                                    item,
2051                                                    "NULL ETH spec/mask");
2052                                 return -rte_errno;
2053                         }
2054
2055                         /* Mask bits of source MAC address must be full of 0.
2056                          * Mask bits of destination MAC address must be full
2057                          * of 1 or full of 0.
2058                          */
2059                         if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2060                             (!rte_is_zero_ether_addr(&eth_mask->dst) &&
2061                              !rte_is_broadcast_ether_addr(&eth_mask->dst))) {
2062                                 rte_flow_error_set(error, EINVAL,
2063                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2064                                                    item,
2065                                                    "Invalid MAC_addr mask");
2066                                 return -rte_errno;
2067                         }
2068
2069                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2070                                 rte_flow_error_set(error, EINVAL,
2071                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2072                                                    item,
2073                                                    "Invalid ethertype mask");
2074                                 return -rte_errno;
2075                         }
2076
2077                         /* If mask bits of destination MAC address
2078                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2079                          */
2080                         if (rte_is_broadcast_ether_addr(&eth_mask->dst)) {
2081                                 filter->mac_addr = eth_spec->dst;
2082                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2083                         } else {
2084                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2085                         }
2086                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2087
2088                         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2089                             filter->ether_type == RTE_ETHER_TYPE_IPV6 ||
2090                             filter->ether_type == RTE_ETHER_TYPE_LLDP ||
2091                             filter->ether_type == outer_tpid) {
2092                                 rte_flow_error_set(error, EINVAL,
2093                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2094                                                    item,
2095                                                    "Unsupported ether_type in"
2096                                                    " control packet filter.");
2097                                 return -rte_errno;
2098                         }
2099                         break;
2100                 default:
2101                         break;
2102                 }
2103         }
2104
2105         return 0;
2106 }
2107
2108 /* Ethertype action only supports QUEUE or DROP. */
2109 static int
2110 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2111                                  const struct rte_flow_action *actions,
2112                                  struct rte_flow_error *error,
2113                                  struct rte_eth_ethertype_filter *filter)
2114 {
2115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2116         const struct rte_flow_action *act;
2117         const struct rte_flow_action_queue *act_q;
2118         uint32_t index = 0;
2119
2120         /* Check if the first non-void action is QUEUE or DROP. */
2121         NEXT_ITEM_OF_ACTION(act, actions, index);
2122         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2123             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2124                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2125                                    act, "Not supported action.");
2126                 return -rte_errno;
2127         }
2128
2129         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2130                 act_q = act->conf;
2131                 filter->queue = act_q->index;
2132                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2133                         rte_flow_error_set(error, EINVAL,
2134                                            RTE_FLOW_ERROR_TYPE_ACTION,
2135                                            act, "Invalid queue ID for"
2136                                            " ethertype_filter.");
2137                         return -rte_errno;
2138                 }
2139         } else {
2140                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2141         }
2142
2143         /* Check if the next non-void item is END */
2144         index++;
2145         NEXT_ITEM_OF_ACTION(act, actions, index);
2146         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2147                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2148                                    act, "Not supported action.");
2149                 return -rte_errno;
2150         }
2151
2152         return 0;
2153 }
2154
2155 static int
2156 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2157                                  const struct rte_flow_attr *attr,
2158                                  const struct rte_flow_item pattern[],
2159                                  const struct rte_flow_action actions[],
2160                                  struct rte_flow_error *error,
2161                                  union i40e_filter_t *filter)
2162 {
2163         struct rte_eth_ethertype_filter *ethertype_filter =
2164                 &filter->ethertype_filter;
2165         int ret;
2166
2167         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2168                                                 ethertype_filter);
2169         if (ret)
2170                 return ret;
2171
2172         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2173                                                ethertype_filter);
2174         if (ret)
2175                 return ret;
2176
2177         ret = i40e_flow_parse_attr(attr, error);
2178         if (ret)
2179                 return ret;
2180
2181         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2182
2183         return ret;
2184 }
2185
2186 static int
2187 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2188                          const struct rte_flow_item_raw *raw_spec,
2189                          struct rte_flow_error *error)
2190 {
2191         if (!raw_spec->relative) {
2192                 rte_flow_error_set(error, EINVAL,
2193                                    RTE_FLOW_ERROR_TYPE_ITEM,
2194                                    item,
2195                                    "Relative should be 1.");
2196                 return -rte_errno;
2197         }
2198
2199         if (raw_spec->offset % sizeof(uint16_t)) {
2200                 rte_flow_error_set(error, EINVAL,
2201                                    RTE_FLOW_ERROR_TYPE_ITEM,
2202                                    item,
2203                                    "Offset should be even.");
2204                 return -rte_errno;
2205         }
2206
2207         if (raw_spec->search || raw_spec->limit) {
2208                 rte_flow_error_set(error, EINVAL,
2209                                    RTE_FLOW_ERROR_TYPE_ITEM,
2210                                    item,
2211                                    "search or limit is not supported.");
2212                 return -rte_errno;
2213         }
2214
2215         if (raw_spec->offset < 0) {
2216                 rte_flow_error_set(error, EINVAL,
2217                                    RTE_FLOW_ERROR_TYPE_ITEM,
2218                                    item,
2219                                    "Offset should be non-negative.");
2220                 return -rte_errno;
2221         }
2222         return 0;
2223 }
2224
2225 static int
2226 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2227                          struct i40e_fdir_flex_pit *flex_pit,
2228                          enum i40e_flxpld_layer_idx layer_idx,
2229                          uint8_t raw_id)
2230 {
2231         uint8_t field_idx;
2232
2233         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2234         /* Check if the configuration is conflicted */
2235         if (pf->fdir.flex_pit_flag[layer_idx] &&
2236             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2237              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2238              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2239                 return -1;
2240
2241         /* Check if the configuration exists. */
2242         if (pf->fdir.flex_pit_flag[layer_idx] &&
2243             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2244              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2245              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2246                 return 1;
2247
2248         pf->fdir.flex_set[field_idx].src_offset =
2249                 flex_pit->src_offset;
2250         pf->fdir.flex_set[field_idx].size =
2251                 flex_pit->size;
2252         pf->fdir.flex_set[field_idx].dst_offset =
2253                 flex_pit->dst_offset;
2254
2255         return 0;
2256 }
2257
2258 static int
2259 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2260                           enum i40e_filter_pctype pctype,
2261                           uint8_t *mask)
2262 {
2263         struct i40e_fdir_flex_mask flex_mask;
2264         uint16_t mask_tmp;
2265         uint8_t i, nb_bitmask = 0;
2266
2267         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2268         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2269                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2270                 if (mask_tmp) {
2271                         flex_mask.word_mask |=
2272                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2273                         if (mask_tmp != UINT16_MAX) {
2274                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2275                                 flex_mask.bitmask[nb_bitmask].offset =
2276                                         i / sizeof(uint16_t);
2277                                 nb_bitmask++;
2278                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2279                                         return -1;
2280                         }
2281                 }
2282         }
2283         flex_mask.nb_bitmask = nb_bitmask;
2284
2285         if (pf->fdir.flex_mask_flag[pctype] &&
2286             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2287                     sizeof(struct i40e_fdir_flex_mask))))
2288                 return -2;
2289         else if (pf->fdir.flex_mask_flag[pctype] &&
2290                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2291                           sizeof(struct i40e_fdir_flex_mask))))
2292                 return 1;
2293
2294         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2295                sizeof(struct i40e_fdir_flex_mask));
2296         return 0;
2297 }
2298
2299 static void
2300 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2301                             enum i40e_flxpld_layer_idx layer_idx,
2302                             uint8_t raw_id)
2303 {
2304         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2305         uint32_t flx_pit, flx_ort;
2306         uint8_t field_idx;
2307         uint16_t min_next_off = 0;  /* in words */
2308         uint8_t i;
2309
2310         if (raw_id) {
2311                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2312                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2313                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2314                 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2315         }
2316
2317         /* Set flex pit */
2318         for (i = 0; i < raw_id; i++) {
2319                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2320                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2321                                      pf->fdir.flex_set[field_idx].size,
2322                                      pf->fdir.flex_set[field_idx].dst_offset);
2323
2324                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2325                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2326                         pf->fdir.flex_set[field_idx].size;
2327         }
2328
2329         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2330                 /* set the non-used register obeying register's constrain */
2331                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2332                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2333                                      NONUSE_FLX_PIT_DEST_OFF);
2334                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2335                 min_next_off++;
2336         }
2337
2338         pf->fdir.flex_pit_flag[layer_idx] = 1;
2339 }
2340
2341 static void
2342 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2343                             enum i40e_filter_pctype pctype)
2344 {
2345         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2346         struct i40e_fdir_flex_mask *flex_mask;
2347         uint32_t flxinset, fd_mask;
2348         uint8_t i;
2349
2350         /* Set flex mask */
2351         flex_mask = &pf->fdir.flex_mask[pctype];
2352         flxinset = (flex_mask->word_mask <<
2353                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2354                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2355         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2356
2357         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2358                 fd_mask = (flex_mask->bitmask[i].mask <<
2359                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2360                         I40E_PRTQF_FD_MSK_MASK_MASK;
2361                 fd_mask |= ((flex_mask->bitmask[i].offset +
2362                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2363                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2364                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2365                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2366         }
2367
2368         pf->fdir.flex_mask_flag[pctype] = 1;
2369 }
2370
2371 static int
2372 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2373                          enum i40e_filter_pctype pctype,
2374                          uint64_t input_set)
2375 {
2376         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2377         uint64_t inset_reg = 0;
2378         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2379         int i, num;
2380
2381         /* Check if the input set is valid */
2382         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2383                                     input_set) != 0) {
2384                 PMD_DRV_LOG(ERR, "Invalid input set");
2385                 return -EINVAL;
2386         }
2387
2388         /* Check if the configuration is conflicted */
2389         if (pf->fdir.inset_flag[pctype] &&
2390             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2391                 return -1;
2392
2393         if (pf->fdir.inset_flag[pctype] &&
2394             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2395                 return 0;
2396
2397         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2398                                            I40E_INSET_MASK_NUM_REG);
2399         if (num < 0)
2400                 return -EINVAL;
2401
2402         if (pf->support_multi_driver) {
2403                 for (i = 0; i < num; i++)
2404                         if (i40e_read_rx_ctl(hw,
2405                                         I40E_GLQF_FD_MSK(i, pctype)) !=
2406                                         mask_reg[i]) {
2407                                 PMD_DRV_LOG(ERR, "Input set setting is not"
2408                                                 " supported with"
2409                                                 " `support-multi-driver`"
2410                                                 " enabled!");
2411                                 return -EPERM;
2412                         }
2413                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2414                         if (i40e_read_rx_ctl(hw,
2415                                         I40E_GLQF_FD_MSK(i, pctype)) != 0) {
2416                                 PMD_DRV_LOG(ERR, "Input set setting is not"
2417                                                 " supported with"
2418                                                 " `support-multi-driver`"
2419                                                 " enabled!");
2420                                 return -EPERM;
2421                         }
2422
2423         } else {
2424                 for (i = 0; i < num; i++)
2425                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2426                                 mask_reg[i]);
2427                 /*clear unused mask registers of the pctype */
2428                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2429                         i40e_check_write_reg(hw,
2430                                         I40E_GLQF_FD_MSK(i, pctype), 0);
2431         }
2432
2433         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2434
2435         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2436                              (uint32_t)(inset_reg & UINT32_MAX));
2437         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2438                              (uint32_t)((inset_reg >>
2439                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2440
2441         I40E_WRITE_FLUSH(hw);
2442
2443         pf->fdir.input_set[pctype] = input_set;
2444         pf->fdir.inset_flag[pctype] = 1;
2445         return 0;
2446 }
2447
2448 static uint8_t
2449 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2450                                 enum rte_flow_item_type item_type,
2451                                 struct i40e_fdir_filter_conf *filter)
2452 {
2453         struct i40e_customized_pctype *cus_pctype = NULL;
2454
2455         switch (item_type) {
2456         case RTE_FLOW_ITEM_TYPE_GTPC:
2457                 cus_pctype = i40e_find_customized_pctype(pf,
2458                                                          I40E_CUSTOMIZED_GTPC);
2459                 break;
2460         case RTE_FLOW_ITEM_TYPE_GTPU:
2461                 if (!filter->input.flow_ext.inner_ip)
2462                         cus_pctype = i40e_find_customized_pctype(pf,
2463                                                          I40E_CUSTOMIZED_GTPU);
2464                 else if (filter->input.flow_ext.iip_type ==
2465                          I40E_FDIR_IPTYPE_IPV4)
2466                         cus_pctype = i40e_find_customized_pctype(pf,
2467                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2468                 else if (filter->input.flow_ext.iip_type ==
2469                          I40E_FDIR_IPTYPE_IPV6)
2470                         cus_pctype = i40e_find_customized_pctype(pf,
2471                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2472                 break;
2473         case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
2474                 if (filter->input.flow_ext.oip_type == I40E_FDIR_IPTYPE_IPV4)
2475                         cus_pctype = i40e_find_customized_pctype(pf,
2476                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
2477                 else if (filter->input.flow_ext.oip_type ==
2478                          I40E_FDIR_IPTYPE_IPV6)
2479                         cus_pctype = i40e_find_customized_pctype(pf,
2480                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
2481                 break;
2482         case RTE_FLOW_ITEM_TYPE_ESP:
2483                 if (!filter->input.flow_ext.is_udp) {
2484                         if (filter->input.flow_ext.oip_type ==
2485                                 I40E_FDIR_IPTYPE_IPV4)
2486                                 cus_pctype = i40e_find_customized_pctype(pf,
2487                                                 I40E_CUSTOMIZED_ESP_IPV4);
2488                         else if (filter->input.flow_ext.oip_type ==
2489                                 I40E_FDIR_IPTYPE_IPV6)
2490                                 cus_pctype = i40e_find_customized_pctype(pf,
2491                                                 I40E_CUSTOMIZED_ESP_IPV6);
2492                 } else {
2493                         if (filter->input.flow_ext.oip_type ==
2494                                 I40E_FDIR_IPTYPE_IPV4)
2495                                 cus_pctype = i40e_find_customized_pctype(pf,
2496                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
2497                         else if (filter->input.flow_ext.oip_type ==
2498                                         I40E_FDIR_IPTYPE_IPV6)
2499                                 cus_pctype = i40e_find_customized_pctype(pf,
2500                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
2501                         filter->input.flow_ext.is_udp = false;
2502                 }
2503                 break;
2504         default:
2505                 PMD_DRV_LOG(ERR, "Unsupported item type");
2506                 break;
2507         }
2508
2509         if (cus_pctype && cus_pctype->valid)
2510                 return cus_pctype->pctype;
2511
2512         return I40E_FILTER_PCTYPE_INVALID;
2513 }
2514
2515 static void
2516 i40e_flow_set_filter_spi(struct i40e_fdir_filter_conf *filter,
2517         const struct rte_flow_item_esp *esp_spec)
2518 {
2519         if (filter->input.flow_ext.oip_type ==
2520                 I40E_FDIR_IPTYPE_IPV4) {
2521                 if (filter->input.flow_ext.is_udp)
2522                         filter->input.flow.esp_ipv4_udp_flow.spi =
2523                                 esp_spec->hdr.spi;
2524                 else
2525                         filter->input.flow.esp_ipv4_flow.spi =
2526                                 esp_spec->hdr.spi;
2527         }
2528         if (filter->input.flow_ext.oip_type ==
2529                 I40E_FDIR_IPTYPE_IPV6) {
2530                 if (filter->input.flow_ext.is_udp)
2531                         filter->input.flow.esp_ipv6_udp_flow.spi =
2532                                 esp_spec->hdr.spi;
2533                 else
2534                         filter->input.flow.esp_ipv6_flow.spi =
2535                                 esp_spec->hdr.spi;
2536         }
2537 }
2538
2539 /* 1. Last in item should be NULL as range is not supported.
2540  * 2. Supported patterns: refer to array i40e_supported_patterns.
2541  * 3. Default supported flow type and input set: refer to array
2542  *    valid_fdir_inset_table in i40e_ethdev.c.
2543  * 4. Mask of fields which need to be matched should be
2544  *    filled with 1.
2545  * 5. Mask of fields which needn't to be matched should be
2546  *    filled with 0.
2547  * 6. GTP profile supports GTPv1 only.
2548  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2549  */
2550 static int
2551 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2552                              const struct rte_flow_attr *attr,
2553                              const struct rte_flow_item *pattern,
2554                              struct rte_flow_error *error,
2555                              struct i40e_fdir_filter_conf *filter)
2556 {
2557         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2558         const struct rte_flow_item *item = pattern;
2559         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2560         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2561         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2562         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2563         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2564         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2565         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2566         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2567         const struct rte_flow_item_esp *esp_spec, *esp_mask;
2568         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2569         const struct rte_flow_item_vf *vf_spec;
2570         const struct rte_flow_item_l2tpv3oip *l2tpv3oip_spec, *l2tpv3oip_mask;
2571
2572         uint8_t pctype = 0;
2573         uint64_t input_set = I40E_INSET_NONE;
2574         uint16_t frag_off;
2575         enum rte_flow_item_type item_type;
2576         enum rte_flow_item_type next_type;
2577         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2578         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2579         uint32_t i, j;
2580         uint8_t  ipv6_addr_mask[16] = {
2581                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2582                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2583         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2584         uint8_t raw_id = 0;
2585         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2586         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2587         struct i40e_fdir_flex_pit flex_pit;
2588         uint8_t next_dst_off = 0;
2589         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2590         uint16_t flex_size;
2591         bool cfg_flex_pit = true;
2592         bool cfg_flex_msk = true;
2593         uint16_t outer_tpid;
2594         uint16_t ether_type;
2595         uint32_t vtc_flow_cpu;
2596         bool outer_ip = true;
2597         int ret;
2598
2599         memset(off_arr, 0, sizeof(off_arr));
2600         memset(len_arr, 0, sizeof(len_arr));
2601         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2602         outer_tpid = i40e_get_outer_vlan(dev);
2603         filter->input.flow_ext.customized_pctype = false;
2604         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2605                 if (item->last) {
2606                         rte_flow_error_set(error, EINVAL,
2607                                            RTE_FLOW_ERROR_TYPE_ITEM,
2608                                            item,
2609                                            "Not support range");
2610                         return -rte_errno;
2611                 }
2612                 item_type = item->type;
2613                 switch (item_type) {
2614                 case RTE_FLOW_ITEM_TYPE_ETH:
2615                         eth_spec = item->spec;
2616                         eth_mask = item->mask;
2617                         next_type = (item + 1)->type;
2618
2619                         if (next_type == RTE_FLOW_ITEM_TYPE_END &&
2620                                                 (!eth_spec || !eth_mask)) {
2621                                 rte_flow_error_set(error, EINVAL,
2622                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2623                                                    item,
2624                                                    "NULL eth spec/mask.");
2625                                 return -rte_errno;
2626                         }
2627
2628                         if (eth_spec && eth_mask) {
2629                                 if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2630                                     !rte_is_zero_ether_addr(&eth_mask->dst)) {
2631                                         rte_flow_error_set(error, EINVAL,
2632                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2633                                                       item,
2634                                                       "Invalid MAC_addr mask.");
2635                                         return -rte_errno;
2636                                 }
2637                         }
2638                         if (eth_spec && eth_mask && eth_mask->type) {
2639                                 if (eth_mask->type != RTE_BE16(0xffff)) {
2640                                         rte_flow_error_set(error, EINVAL,
2641                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2642                                                       item,
2643                                                       "Invalid type mask.");
2644                                         return -rte_errno;
2645                                 }
2646
2647                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2648
2649                                 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN ||
2650                                     ether_type == RTE_ETHER_TYPE_IPV4 ||
2651                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2652                                     ether_type == RTE_ETHER_TYPE_ARP ||
2653                                     ether_type == outer_tpid) {
2654                                         rte_flow_error_set(error, EINVAL,
2655                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2656                                                      item,
2657                                                      "Unsupported ether_type.");
2658                                         return -rte_errno;
2659                                 }
2660                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2661                                 filter->input.flow.l2_flow.ether_type =
2662                                         eth_spec->type;
2663                         }
2664
2665                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2666                         layer_idx = I40E_FLXPLD_L2_IDX;
2667
2668                         break;
2669                 case RTE_FLOW_ITEM_TYPE_VLAN:
2670                         vlan_spec = item->spec;
2671                         vlan_mask = item->mask;
2672
2673                         RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2674                         if (vlan_spec && vlan_mask) {
2675                                 if (vlan_mask->tci ==
2676                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2677                                         input_set |= I40E_INSET_VLAN_INNER;
2678                                         filter->input.flow_ext.vlan_tci =
2679                                                 vlan_spec->tci;
2680                                 }
2681                         }
2682                         if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2683                                 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2684                                         rte_flow_error_set(error, EINVAL,
2685                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2686                                                       item,
2687                                                       "Invalid inner_type"
2688                                                       " mask.");
2689                                         return -rte_errno;
2690                                 }
2691
2692                                 ether_type =
2693                                         rte_be_to_cpu_16(vlan_spec->inner_type);
2694
2695                                 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
2696                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2697                                     ether_type == RTE_ETHER_TYPE_ARP ||
2698                                     ether_type == outer_tpid) {
2699                                         rte_flow_error_set(error, EINVAL,
2700                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2701                                                      item,
2702                                                      "Unsupported inner_type.");
2703                                         return -rte_errno;
2704                                 }
2705                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2706                                 filter->input.flow.l2_flow.ether_type =
2707                                         vlan_spec->inner_type;
2708                         }
2709
2710                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2711                         layer_idx = I40E_FLXPLD_L2_IDX;
2712
2713                         break;
2714                 case RTE_FLOW_ITEM_TYPE_IPV4:
2715                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2716                         ipv4_spec = item->spec;
2717                         ipv4_mask = item->mask;
2718                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2719                         layer_idx = I40E_FLXPLD_L3_IDX;
2720
2721                         if (ipv4_spec && ipv4_mask && outer_ip) {
2722                                 /* Check IPv4 mask and update input set */
2723                                 if (ipv4_mask->hdr.version_ihl ||
2724                                     ipv4_mask->hdr.total_length ||
2725                                     ipv4_mask->hdr.packet_id ||
2726                                     ipv4_mask->hdr.fragment_offset ||
2727                                     ipv4_mask->hdr.hdr_checksum) {
2728                                         rte_flow_error_set(error, EINVAL,
2729                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2730                                                    item,
2731                                                    "Invalid IPv4 mask.");
2732                                         return -rte_errno;
2733                                 }
2734
2735                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2736                                         input_set |= I40E_INSET_IPV4_SRC;
2737                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2738                                         input_set |= I40E_INSET_IPV4_DST;
2739                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2740                                         input_set |= I40E_INSET_IPV4_TOS;
2741                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2742                                         input_set |= I40E_INSET_IPV4_TTL;
2743                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2744                                         input_set |= I40E_INSET_IPV4_PROTO;
2745
2746                                 /* Check if it is fragment. */
2747                                 frag_off = ipv4_spec->hdr.fragment_offset;
2748                                 frag_off = rte_be_to_cpu_16(frag_off);
2749                                 if (frag_off & RTE_IPV4_HDR_OFFSET_MASK ||
2750                                     frag_off & RTE_IPV4_HDR_MF_FLAG)
2751                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2752
2753                                 /* Get the filter info */
2754                                 filter->input.flow.ip4_flow.proto =
2755                                         ipv4_spec->hdr.next_proto_id;
2756                                 filter->input.flow.ip4_flow.tos =
2757                                         ipv4_spec->hdr.type_of_service;
2758                                 filter->input.flow.ip4_flow.ttl =
2759                                         ipv4_spec->hdr.time_to_live;
2760                                 filter->input.flow.ip4_flow.src_ip =
2761                                         ipv4_spec->hdr.src_addr;
2762                                 filter->input.flow.ip4_flow.dst_ip =
2763                                         ipv4_spec->hdr.dst_addr;
2764
2765                                 filter->input.flow_ext.inner_ip = false;
2766                                 filter->input.flow_ext.oip_type =
2767                                         I40E_FDIR_IPTYPE_IPV4;
2768                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2769                                 filter->input.flow_ext.inner_ip = true;
2770                                 filter->input.flow_ext.iip_type =
2771                                         I40E_FDIR_IPTYPE_IPV4;
2772                         } else if (!ipv4_spec && !ipv4_mask && outer_ip) {
2773                                 filter->input.flow_ext.inner_ip = false;
2774                                 filter->input.flow_ext.oip_type =
2775                                         I40E_FDIR_IPTYPE_IPV4;
2776                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2777                                 rte_flow_error_set(error, EINVAL,
2778                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2779                                                    item,
2780                                                    "Invalid inner IPv4 mask.");
2781                                 return -rte_errno;
2782                         }
2783
2784                         if (outer_ip)
2785                                 outer_ip = false;
2786
2787                         break;
2788                 case RTE_FLOW_ITEM_TYPE_IPV6:
2789                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2790                         ipv6_spec = item->spec;
2791                         ipv6_mask = item->mask;
2792                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2793                         layer_idx = I40E_FLXPLD_L3_IDX;
2794
2795                         if (ipv6_spec && ipv6_mask && outer_ip) {
2796                                 /* Check IPv6 mask and update input set */
2797                                 if (ipv6_mask->hdr.payload_len) {
2798                                         rte_flow_error_set(error, EINVAL,
2799                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2800                                                    item,
2801                                                    "Invalid IPv6 mask");
2802                                         return -rte_errno;
2803                                 }
2804
2805                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2806                                             ipv6_addr_mask,
2807                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2808                                         input_set |= I40E_INSET_IPV6_SRC;
2809                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2810                                             ipv6_addr_mask,
2811                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2812                                         input_set |= I40E_INSET_IPV6_DST;
2813
2814                                 if ((ipv6_mask->hdr.vtc_flow &
2815                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2816                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2817                                         input_set |= I40E_INSET_IPV6_TC;
2818                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2819                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2820                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2821                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2822
2823                                 /* Get filter info */
2824                                 vtc_flow_cpu =
2825                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2826                                 filter->input.flow.ipv6_flow.tc =
2827                                         (uint8_t)(vtc_flow_cpu >>
2828                                                   I40E_FDIR_IPv6_TC_OFFSET);
2829                                 filter->input.flow.ipv6_flow.proto =
2830                                         ipv6_spec->hdr.proto;
2831                                 filter->input.flow.ipv6_flow.hop_limits =
2832                                         ipv6_spec->hdr.hop_limits;
2833
2834                                 filter->input.flow_ext.inner_ip = false;
2835                                 filter->input.flow_ext.oip_type =
2836                                         I40E_FDIR_IPTYPE_IPV6;
2837
2838                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2839                                            ipv6_spec->hdr.src_addr, 16);
2840                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2841                                            ipv6_spec->hdr.dst_addr, 16);
2842
2843                                 /* Check if it is fragment. */
2844                                 if (ipv6_spec->hdr.proto ==
2845                                     I40E_IPV6_FRAG_HEADER)
2846                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2847                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2848                                 filter->input.flow_ext.inner_ip = true;
2849                                 filter->input.flow_ext.iip_type =
2850                                         I40E_FDIR_IPTYPE_IPV6;
2851                         } else if (!ipv6_spec && !ipv6_mask && outer_ip) {
2852                                 filter->input.flow_ext.inner_ip = false;
2853                                 filter->input.flow_ext.oip_type =
2854                                         I40E_FDIR_IPTYPE_IPV6;
2855                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2856                                 rte_flow_error_set(error, EINVAL,
2857                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2858                                                    item,
2859                                                    "Invalid inner IPv6 mask");
2860                                 return -rte_errno;
2861                         }
2862
2863                         if (outer_ip)
2864                                 outer_ip = false;
2865                         break;
2866                 case RTE_FLOW_ITEM_TYPE_TCP:
2867                         tcp_spec = item->spec;
2868                         tcp_mask = item->mask;
2869
2870                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2871                                 pctype =
2872                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2873                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2874                                 pctype =
2875                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2876                         if (tcp_spec && tcp_mask) {
2877                                 /* Check TCP mask and update input set */
2878                                 if (tcp_mask->hdr.sent_seq ||
2879                                     tcp_mask->hdr.recv_ack ||
2880                                     tcp_mask->hdr.data_off ||
2881                                     tcp_mask->hdr.tcp_flags ||
2882                                     tcp_mask->hdr.rx_win ||
2883                                     tcp_mask->hdr.cksum ||
2884                                     tcp_mask->hdr.tcp_urp) {
2885                                         rte_flow_error_set(error, EINVAL,
2886                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2887                                                    item,
2888                                                    "Invalid TCP mask");
2889                                         return -rte_errno;
2890                                 }
2891
2892                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2893                                         input_set |= I40E_INSET_SRC_PORT;
2894                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2895                                         input_set |= I40E_INSET_DST_PORT;
2896
2897                                 /* Get filter info */
2898                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2899                                         filter->input.flow.tcp4_flow.src_port =
2900                                                 tcp_spec->hdr.src_port;
2901                                         filter->input.flow.tcp4_flow.dst_port =
2902                                                 tcp_spec->hdr.dst_port;
2903                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2904                                         filter->input.flow.tcp6_flow.src_port =
2905                                                 tcp_spec->hdr.src_port;
2906                                         filter->input.flow.tcp6_flow.dst_port =
2907                                                 tcp_spec->hdr.dst_port;
2908                                 }
2909                         }
2910
2911                         layer_idx = I40E_FLXPLD_L4_IDX;
2912
2913                         break;
2914                 case RTE_FLOW_ITEM_TYPE_UDP:
2915                         udp_spec = item->spec;
2916                         udp_mask = item->mask;
2917
2918                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2919                                 pctype =
2920                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2921                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2922                                 pctype =
2923                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2924
2925                         if (udp_spec && udp_mask) {
2926                                 /* Check UDP mask and update input set*/
2927                                 if (udp_mask->hdr.dgram_len ||
2928                                     udp_mask->hdr.dgram_cksum) {
2929                                         rte_flow_error_set(error, EINVAL,
2930                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2931                                                    item,
2932                                                    "Invalid UDP mask");
2933                                         return -rte_errno;
2934                                 }
2935
2936                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2937                                         input_set |= I40E_INSET_SRC_PORT;
2938                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2939                                         input_set |= I40E_INSET_DST_PORT;
2940
2941                                 /* Get filter info */
2942                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2943                                         filter->input.flow.udp4_flow.src_port =
2944                                                 udp_spec->hdr.src_port;
2945                                         filter->input.flow.udp4_flow.dst_port =
2946                                                 udp_spec->hdr.dst_port;
2947                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2948                                         filter->input.flow.udp6_flow.src_port =
2949                                                 udp_spec->hdr.src_port;
2950                                         filter->input.flow.udp6_flow.dst_port =
2951                                                 udp_spec->hdr.dst_port;
2952                                 }
2953                         }
2954                         filter->input.flow_ext.is_udp = true;
2955                         layer_idx = I40E_FLXPLD_L4_IDX;
2956
2957                         break;
2958                 case RTE_FLOW_ITEM_TYPE_GTPC:
2959                 case RTE_FLOW_ITEM_TYPE_GTPU:
2960                         if (!pf->gtp_support) {
2961                                 rte_flow_error_set(error, EINVAL,
2962                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2963                                                    item,
2964                                                    "Unsupported protocol");
2965                                 return -rte_errno;
2966                         }
2967
2968                         gtp_spec = item->spec;
2969                         gtp_mask = item->mask;
2970
2971                         if (gtp_spec && gtp_mask) {
2972                                 if (gtp_mask->v_pt_rsv_flags ||
2973                                     gtp_mask->msg_type ||
2974                                     gtp_mask->msg_len ||
2975                                     gtp_mask->teid != UINT32_MAX) {
2976                                         rte_flow_error_set(error, EINVAL,
2977                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2978                                                    item,
2979                                                    "Invalid GTP mask");
2980                                         return -rte_errno;
2981                                 }
2982
2983                                 filter->input.flow.gtp_flow.teid =
2984                                         gtp_spec->teid;
2985                                 filter->input.flow_ext.customized_pctype = true;
2986                                 cus_proto = item_type;
2987                         }
2988                         break;
2989                 case RTE_FLOW_ITEM_TYPE_ESP:
2990                         if (!pf->esp_support) {
2991                                 rte_flow_error_set(error, EINVAL,
2992                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2993                                                    item,
2994                                                    "Unsupported ESP protocol");
2995                                 return -rte_errno;
2996                         }
2997
2998                         esp_spec = item->spec;
2999                         esp_mask = item->mask;
3000
3001                         if (!esp_spec || !esp_mask) {
3002                                 rte_flow_error_set(error, EINVAL,
3003                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3004                                                    item,
3005                                                    "Invalid ESP item");
3006                                 return -rte_errno;
3007                         }
3008
3009                         if (esp_spec && esp_mask) {
3010                                 if (esp_mask->hdr.spi != UINT32_MAX) {
3011                                         rte_flow_error_set(error, EINVAL,
3012                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3013                                                    item,
3014                                                    "Invalid ESP mask");
3015                                         return -rte_errno;
3016                                 }
3017                                 i40e_flow_set_filter_spi(filter, esp_spec);
3018                                 filter->input.flow_ext.customized_pctype = true;
3019                                 cus_proto = item_type;
3020                         }
3021                         break;
3022                 case RTE_FLOW_ITEM_TYPE_SCTP:
3023                         sctp_spec = item->spec;
3024                         sctp_mask = item->mask;
3025
3026                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
3027                                 pctype =
3028                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3029                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
3030                                 pctype =
3031                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3032
3033                         if (sctp_spec && sctp_mask) {
3034                                 /* Check SCTP mask and update input set */
3035                                 if (sctp_mask->hdr.cksum) {
3036                                         rte_flow_error_set(error, EINVAL,
3037                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3038                                                    item,
3039                                                    "Invalid UDP mask");
3040                                         return -rte_errno;
3041                                 }
3042
3043                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
3044                                         input_set |= I40E_INSET_SRC_PORT;
3045                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
3046                                         input_set |= I40E_INSET_DST_PORT;
3047                                 if (sctp_mask->hdr.tag == UINT32_MAX)
3048                                         input_set |= I40E_INSET_SCTP_VT;
3049
3050                                 /* Get filter info */
3051                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
3052                                         filter->input.flow.sctp4_flow.src_port =
3053                                                 sctp_spec->hdr.src_port;
3054                                         filter->input.flow.sctp4_flow.dst_port =
3055                                                 sctp_spec->hdr.dst_port;
3056                                         filter->input.flow.sctp4_flow.verify_tag
3057                                                 = sctp_spec->hdr.tag;
3058                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
3059                                         filter->input.flow.sctp6_flow.src_port =
3060                                                 sctp_spec->hdr.src_port;
3061                                         filter->input.flow.sctp6_flow.dst_port =
3062                                                 sctp_spec->hdr.dst_port;
3063                                         filter->input.flow.sctp6_flow.verify_tag
3064                                                 = sctp_spec->hdr.tag;
3065                                 }
3066                         }
3067
3068                         layer_idx = I40E_FLXPLD_L4_IDX;
3069
3070                         break;
3071                 case RTE_FLOW_ITEM_TYPE_RAW:
3072                         raw_spec = item->spec;
3073                         raw_mask = item->mask;
3074
3075                         if (!raw_spec || !raw_mask) {
3076                                 rte_flow_error_set(error, EINVAL,
3077                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3078                                                    item,
3079                                                    "NULL RAW spec/mask");
3080                                 return -rte_errno;
3081                         }
3082
3083                         if (pf->support_multi_driver) {
3084                                 rte_flow_error_set(error, ENOTSUP,
3085                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3086                                                    item,
3087                                                    "Unsupported flexible payload.");
3088                                 return -rte_errno;
3089                         }
3090
3091                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
3092                         if (ret < 0)
3093                                 return ret;
3094
3095                         off_arr[raw_id] = raw_spec->offset;
3096                         len_arr[raw_id] = raw_spec->length;
3097
3098                         flex_size = 0;
3099                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
3100                         flex_pit.size =
3101                                 raw_spec->length / sizeof(uint16_t);
3102                         flex_pit.dst_offset =
3103                                 next_dst_off / sizeof(uint16_t);
3104
3105                         for (i = 0; i <= raw_id; i++) {
3106                                 if (i == raw_id)
3107                                         flex_pit.src_offset +=
3108                                                 raw_spec->offset /
3109                                                 sizeof(uint16_t);
3110                                 else
3111                                         flex_pit.src_offset +=
3112                                                 (off_arr[i] + len_arr[i]) /
3113                                                 sizeof(uint16_t);
3114                                 flex_size += len_arr[i];
3115                         }
3116                         if (((flex_pit.src_offset + flex_pit.size) >=
3117                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
3118                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
3119                                 rte_flow_error_set(error, EINVAL,
3120                                            RTE_FLOW_ERROR_TYPE_ITEM,
3121                                            item,
3122                                            "Exceeds maxmial payload limit.");
3123                                 return -rte_errno;
3124                         }
3125
3126                         /* Store flex pit to SW */
3127                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
3128                                                        layer_idx, raw_id);
3129                         if (ret < 0) {
3130                                 rte_flow_error_set(error, EINVAL,
3131                                    RTE_FLOW_ERROR_TYPE_ITEM,
3132                                    item,
3133                                    "Conflict with the first flexible rule.");
3134                                 return -rte_errno;
3135                         } else if (ret > 0)
3136                                 cfg_flex_pit = false;
3137
3138                         for (i = 0; i < raw_spec->length; i++) {
3139                                 j = i + next_dst_off;
3140                                 filter->input.flow_ext.flexbytes[j] =
3141                                         raw_spec->pattern[i];
3142                                 flex_mask[j] = raw_mask->pattern[i];
3143                         }
3144
3145                         next_dst_off += raw_spec->length;
3146                         raw_id++;
3147                         break;
3148                 case RTE_FLOW_ITEM_TYPE_VF:
3149                         vf_spec = item->spec;
3150                         if (!attr->transfer) {
3151                                 rte_flow_error_set(error, ENOTSUP,
3152                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3153                                                    item,
3154                                                    "Matching VF traffic"
3155                                                    " without affecting it"
3156                                                    " (transfer attribute)"
3157                                                    " is unsupported");
3158                                 return -rte_errno;
3159                         }
3160                         filter->input.flow_ext.is_vf = 1;
3161                         filter->input.flow_ext.dst_id = vf_spec->id;
3162                         if (filter->input.flow_ext.is_vf &&
3163                             filter->input.flow_ext.dst_id >= pf->vf_num) {
3164                                 rte_flow_error_set(error, EINVAL,
3165                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3166                                                    item,
3167                                                    "Invalid VF ID for FDIR.");
3168                                 return -rte_errno;
3169                         }
3170                         break;
3171                 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
3172                         l2tpv3oip_spec = item->spec;
3173                         l2tpv3oip_mask = item->mask;
3174
3175                         if (!l2tpv3oip_spec || !l2tpv3oip_mask)
3176                                 break;
3177
3178                         if (l2tpv3oip_mask->session_id != UINT32_MAX) {
3179                                 rte_flow_error_set(error, EINVAL,
3180                                         RTE_FLOW_ERROR_TYPE_ITEM,
3181                                         item,
3182                                         "Invalid L2TPv3 mask");
3183                                 return -rte_errno;
3184                         }
3185
3186                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
3187                                 filter->input.flow.ip4_l2tpv3oip_flow.session_id =
3188                                         l2tpv3oip_spec->session_id;
3189                                 filter->input.flow_ext.oip_type =
3190                                         I40E_FDIR_IPTYPE_IPV4;
3191                         } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
3192                                 filter->input.flow.ip6_l2tpv3oip_flow.session_id =
3193                                         l2tpv3oip_spec->session_id;
3194                                 filter->input.flow_ext.oip_type =
3195                                         I40E_FDIR_IPTYPE_IPV6;
3196                         }
3197
3198                         filter->input.flow_ext.customized_pctype = true;
3199                         cus_proto = item_type;
3200                         break;
3201                 default:
3202                         break;
3203                 }
3204         }
3205
3206         /* Get customized pctype value */
3207         if (filter->input.flow_ext.customized_pctype) {
3208                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
3209                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
3210                         rte_flow_error_set(error, EINVAL,
3211                                            RTE_FLOW_ERROR_TYPE_ITEM,
3212                                            item,
3213                                            "Unsupported pctype");
3214                         return -rte_errno;
3215                 }
3216         }
3217
3218         /* If customized pctype is not used, set fdir configuration.*/
3219         if (!filter->input.flow_ext.customized_pctype) {
3220                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3221                 if (ret == -1) {
3222                         rte_flow_error_set(error, EINVAL,
3223                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3224                                            "Conflict with the first rule's input set.");
3225                         return -rte_errno;
3226                 } else if (ret == -EINVAL) {
3227                         rte_flow_error_set(error, EINVAL,
3228                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3229                                            "Invalid pattern mask.");
3230                         return -rte_errno;
3231                 }
3232
3233                 /* Store flex mask to SW */
3234                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3235                 if (ret == -1) {
3236                         rte_flow_error_set(error, EINVAL,
3237                                            RTE_FLOW_ERROR_TYPE_ITEM,
3238                                            item,
3239                                            "Exceed maximal number of bitmasks");
3240                         return -rte_errno;
3241                 } else if (ret == -2) {
3242                         rte_flow_error_set(error, EINVAL,
3243                                            RTE_FLOW_ERROR_TYPE_ITEM,
3244                                            item,
3245                                            "Conflict with the first flexible rule");
3246                         return -rte_errno;
3247                 } else if (ret > 0)
3248                         cfg_flex_msk = false;
3249
3250                 if (cfg_flex_pit)
3251                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3252
3253                 if (cfg_flex_msk)
3254                         i40e_flow_set_fdir_flex_msk(pf, pctype);
3255         }
3256
3257         filter->input.pctype = pctype;
3258
3259         return 0;
3260 }
3261
3262 /* Parse to get the action info of a FDIR filter.
3263  * FDIR action supports QUEUE or (QUEUE + MARK).
3264  */
3265 static int
3266 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3267                             const struct rte_flow_action *actions,
3268                             struct rte_flow_error *error,
3269                             struct i40e_fdir_filter_conf *filter)
3270 {
3271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3272         const struct rte_flow_action *act;
3273         const struct rte_flow_action_queue *act_q;
3274         const struct rte_flow_action_mark *mark_spec = NULL;
3275         uint32_t index = 0;
3276
3277         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3278         NEXT_ITEM_OF_ACTION(act, actions, index);
3279         switch (act->type) {
3280         case RTE_FLOW_ACTION_TYPE_QUEUE:
3281                 act_q = act->conf;
3282                 filter->action.rx_queue = act_q->index;
3283                 if ((!filter->input.flow_ext.is_vf &&
3284                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3285                     (filter->input.flow_ext.is_vf &&
3286                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3287                         rte_flow_error_set(error, EINVAL,
3288                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3289                                            "Invalid queue ID for FDIR.");
3290                         return -rte_errno;
3291                 }
3292                 filter->action.behavior = I40E_FDIR_ACCEPT;
3293                 break;
3294         case RTE_FLOW_ACTION_TYPE_DROP:
3295                 filter->action.behavior = I40E_FDIR_REJECT;
3296                 break;
3297         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3298                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3299                 break;
3300         case RTE_FLOW_ACTION_TYPE_MARK:
3301                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3302                 mark_spec = act->conf;
3303                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3304                 filter->soft_id = mark_spec->id;
3305         break;
3306         default:
3307                 rte_flow_error_set(error, EINVAL,
3308                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3309                                    "Invalid action.");
3310                 return -rte_errno;
3311         }
3312
3313         /* Check if the next non-void item is MARK or FLAG or END. */
3314         index++;
3315         NEXT_ITEM_OF_ACTION(act, actions, index);
3316         switch (act->type) {
3317         case RTE_FLOW_ACTION_TYPE_MARK:
3318                 if (mark_spec) {
3319                         /* Double MARK actions requested */
3320                         rte_flow_error_set(error, EINVAL,
3321                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3322                            "Invalid action.");
3323                         return -rte_errno;
3324                 }
3325                 mark_spec = act->conf;
3326                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3327                 filter->soft_id = mark_spec->id;
3328                 break;
3329         case RTE_FLOW_ACTION_TYPE_FLAG:
3330                 if (mark_spec) {
3331                         /* MARK + FLAG not supported */
3332                         rte_flow_error_set(error, EINVAL,
3333                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3334                                            "Invalid action.");
3335                         return -rte_errno;
3336                 }
3337                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3338                 break;
3339         case RTE_FLOW_ACTION_TYPE_RSS:
3340                 if (filter->action.behavior != I40E_FDIR_PASSTHRU) {
3341                         /* RSS filter won't be next if FDIR did not pass thru */
3342                         rte_flow_error_set(error, EINVAL,
3343                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3344                                            "Invalid action.");
3345                         return -rte_errno;
3346                 }
3347                 break;
3348         case RTE_FLOW_ACTION_TYPE_END:
3349                 return 0;
3350         default:
3351                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3352                                    act, "Invalid action.");
3353                 return -rte_errno;
3354         }
3355
3356         /* Check if the next non-void item is END */
3357         index++;
3358         NEXT_ITEM_OF_ACTION(act, actions, index);
3359         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3360                 rte_flow_error_set(error, EINVAL,
3361                                    RTE_FLOW_ERROR_TYPE_ACTION,
3362                                    act, "Invalid action.");
3363                 return -rte_errno;
3364         }
3365
3366         return 0;
3367 }
3368
3369 static int
3370 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3371                             const struct rte_flow_attr *attr,
3372                             const struct rte_flow_item pattern[],
3373                             const struct rte_flow_action actions[],
3374                             struct rte_flow_error *error,
3375                             union i40e_filter_t *filter)
3376 {
3377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3378         struct i40e_fdir_filter_conf *fdir_filter =
3379                 &filter->fdir_filter;
3380         int ret;
3381
3382         ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3383                                            fdir_filter);
3384         if (ret)
3385                 return ret;
3386
3387         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3388         if (ret)
3389                 return ret;
3390
3391         ret = i40e_flow_parse_attr(attr, error);
3392         if (ret)
3393                 return ret;
3394
3395         cons_filter_type = RTE_ETH_FILTER_FDIR;
3396
3397         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT ||
3398                 pf->fdir.fdir_vsi == NULL) {
3399                 /* Enable fdir when fdir flow is added at first time. */
3400                 ret = i40e_fdir_setup(pf);
3401                 if (ret != I40E_SUCCESS) {
3402                         rte_flow_error_set(error, ENOTSUP,
3403                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3404                                            NULL, "Failed to setup fdir.");
3405                         return -rte_errno;
3406                 }
3407                 ret = i40e_fdir_configure(dev);
3408                 if (ret < 0) {
3409                         rte_flow_error_set(error, ENOTSUP,
3410                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3411                                            NULL, "Failed to configure fdir.");
3412                         goto err;
3413                 }
3414
3415                 dev->data->dev_conf.fdir_conf.mode = RTE_FDIR_MODE_PERFECT;
3416         }
3417
3418         return 0;
3419 err:
3420         i40e_fdir_teardown(pf);
3421         return -rte_errno;
3422 }
3423
3424 /* Parse to get the action info of a tunnel filter
3425  * Tunnel action only supports PF, VF and QUEUE.
3426  */
3427 static int
3428 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3429                               const struct rte_flow_action *actions,
3430                               struct rte_flow_error *error,
3431                               struct i40e_tunnel_filter_conf *filter)
3432 {
3433         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3434         const struct rte_flow_action *act;
3435         const struct rte_flow_action_queue *act_q;
3436         const struct rte_flow_action_vf *act_vf;
3437         uint32_t index = 0;
3438
3439         /* Check if the first non-void action is PF or VF. */
3440         NEXT_ITEM_OF_ACTION(act, actions, index);
3441         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3442             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3443                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3444                                    act, "Not supported action.");
3445                 return -rte_errno;
3446         }
3447
3448         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3449                 act_vf = act->conf;
3450                 filter->vf_id = act_vf->id;
3451                 filter->is_to_vf = 1;
3452                 if (filter->vf_id >= pf->vf_num) {
3453                         rte_flow_error_set(error, EINVAL,
3454                                    RTE_FLOW_ERROR_TYPE_ACTION,
3455                                    act, "Invalid VF ID for tunnel filter");
3456                         return -rte_errno;
3457                 }
3458         }
3459
3460         /* Check if the next non-void item is QUEUE */
3461         index++;
3462         NEXT_ITEM_OF_ACTION(act, actions, index);
3463         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3464                 act_q = act->conf;
3465                 filter->queue_id = act_q->index;
3466                 if ((!filter->is_to_vf) &&
3467                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3468                         rte_flow_error_set(error, EINVAL,
3469                                    RTE_FLOW_ERROR_TYPE_ACTION,
3470                                    act, "Invalid queue ID for tunnel filter");
3471                         return -rte_errno;
3472                 } else if (filter->is_to_vf &&
3473                            (filter->queue_id >= pf->vf_nb_qps)) {
3474                         rte_flow_error_set(error, EINVAL,
3475                                    RTE_FLOW_ERROR_TYPE_ACTION,
3476                                    act, "Invalid queue ID for tunnel filter");
3477                         return -rte_errno;
3478                 }
3479         }
3480
3481         /* Check if the next non-void item is END */
3482         index++;
3483         NEXT_ITEM_OF_ACTION(act, actions, index);
3484         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3485                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3486                                    act, "Not supported action.");
3487                 return -rte_errno;
3488         }
3489
3490         return 0;
3491 }
3492
3493 static uint16_t i40e_supported_tunnel_filter_types[] = {
3494         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3495         ETH_TUNNEL_FILTER_IVLAN,
3496         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3497         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3498         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3499         ETH_TUNNEL_FILTER_IMAC,
3500         ETH_TUNNEL_FILTER_IMAC,
3501 };
3502
3503 static int
3504 i40e_check_tunnel_filter_type(uint8_t filter_type)
3505 {
3506         uint8_t i;
3507
3508         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3509                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3510                         return 0;
3511         }
3512
3513         return -1;
3514 }
3515
3516 /* 1. Last in item should be NULL as range is not supported.
3517  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3518  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3519  * 3. Mask of fields which need to be matched should be
3520  *    filled with 1.
3521  * 4. Mask of fields which needn't to be matched should be
3522  *    filled with 0.
3523  */
3524 static int
3525 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3526                               const struct rte_flow_item *pattern,
3527                               struct rte_flow_error *error,
3528                               struct i40e_tunnel_filter_conf *filter)
3529 {
3530         const struct rte_flow_item *item = pattern;
3531         const struct rte_flow_item_eth *eth_spec;
3532         const struct rte_flow_item_eth *eth_mask;
3533         const struct rte_flow_item_vxlan *vxlan_spec;
3534         const struct rte_flow_item_vxlan *vxlan_mask;
3535         const struct rte_flow_item_vlan *vlan_spec;
3536         const struct rte_flow_item_vlan *vlan_mask;
3537         uint8_t filter_type = 0;
3538         bool is_vni_masked = 0;
3539         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3540         enum rte_flow_item_type item_type;
3541         bool vxlan_flag = 0;
3542         uint32_t tenant_id_be = 0;
3543         int ret;
3544
3545         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3546                 if (item->last) {
3547                         rte_flow_error_set(error, EINVAL,
3548                                            RTE_FLOW_ERROR_TYPE_ITEM,
3549                                            item,
3550                                            "Not support range");
3551                         return -rte_errno;
3552                 }
3553                 item_type = item->type;
3554                 switch (item_type) {
3555                 case RTE_FLOW_ITEM_TYPE_ETH:
3556                         eth_spec = item->spec;
3557                         eth_mask = item->mask;
3558
3559                         /* Check if ETH item is used for place holder.
3560                          * If yes, both spec and mask should be NULL.
3561                          * If no, both spec and mask shouldn't be NULL.
3562                          */
3563                         if ((!eth_spec && eth_mask) ||
3564                             (eth_spec && !eth_mask)) {
3565                                 rte_flow_error_set(error, EINVAL,
3566                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3567                                                    item,
3568                                                    "Invalid ether spec/mask");
3569                                 return -rte_errno;
3570                         }
3571
3572                         if (eth_spec && eth_mask) {
3573                                 /* DST address of inner MAC shouldn't be masked.
3574                                  * SRC address of Inner MAC should be masked.
3575                                  */
3576                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3577                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3578                                     eth_mask->type) {
3579                                         rte_flow_error_set(error, EINVAL,
3580                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3581                                                    item,
3582                                                    "Invalid ether spec/mask");
3583                                         return -rte_errno;
3584                                 }
3585
3586                                 if (!vxlan_flag) {
3587                                         rte_memcpy(&filter->outer_mac,
3588                                                    &eth_spec->dst,
3589                                                    RTE_ETHER_ADDR_LEN);
3590                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3591                                 } else {
3592                                         rte_memcpy(&filter->inner_mac,
3593                                                    &eth_spec->dst,
3594                                                    RTE_ETHER_ADDR_LEN);
3595                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3596                                 }
3597                         }
3598                         break;
3599                 case RTE_FLOW_ITEM_TYPE_VLAN:
3600                         vlan_spec = item->spec;
3601                         vlan_mask = item->mask;
3602                         if (!(vlan_spec && vlan_mask) ||
3603                             vlan_mask->inner_type) {
3604                                 rte_flow_error_set(error, EINVAL,
3605                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3606                                                    item,
3607                                                    "Invalid vlan item");
3608                                 return -rte_errno;
3609                         }
3610
3611                         if (vlan_spec && vlan_mask) {
3612                                 if (vlan_mask->tci ==
3613                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3614                                         filter->inner_vlan =
3615                                               rte_be_to_cpu_16(vlan_spec->tci) &
3616                                               I40E_TCI_MASK;
3617                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3618                         }
3619                         break;
3620                 case RTE_FLOW_ITEM_TYPE_IPV4:
3621                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3622                         /* IPv4 is used to describe protocol,
3623                          * spec and mask should be NULL.
3624                          */
3625                         if (item->spec || item->mask) {
3626                                 rte_flow_error_set(error, EINVAL,
3627                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3628                                                    item,
3629                                                    "Invalid IPv4 item");
3630                                 return -rte_errno;
3631                         }
3632                         break;
3633                 case RTE_FLOW_ITEM_TYPE_IPV6:
3634                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3635                         /* IPv6 is used to describe protocol,
3636                          * spec and mask should be NULL.
3637                          */
3638                         if (item->spec || item->mask) {
3639                                 rte_flow_error_set(error, EINVAL,
3640                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3641                                                    item,
3642                                                    "Invalid IPv6 item");
3643                                 return -rte_errno;
3644                         }
3645                         break;
3646                 case RTE_FLOW_ITEM_TYPE_UDP:
3647                         /* UDP is used to describe protocol,
3648                          * spec and mask should be NULL.
3649                          */
3650                         if (item->spec || item->mask) {
3651                                 rte_flow_error_set(error, EINVAL,
3652                                            RTE_FLOW_ERROR_TYPE_ITEM,
3653                                            item,
3654                                            "Invalid UDP item");
3655                                 return -rte_errno;
3656                         }
3657                         break;
3658                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3659                         vxlan_spec = item->spec;
3660                         vxlan_mask = item->mask;
3661                         /* Check if VXLAN item is used to describe protocol.
3662                          * If yes, both spec and mask should be NULL.
3663                          * If no, both spec and mask shouldn't be NULL.
3664                          */
3665                         if ((!vxlan_spec && vxlan_mask) ||
3666                             (vxlan_spec && !vxlan_mask)) {
3667                                 rte_flow_error_set(error, EINVAL,
3668                                            RTE_FLOW_ERROR_TYPE_ITEM,
3669                                            item,
3670                                            "Invalid VXLAN item");
3671                                 return -rte_errno;
3672                         }
3673
3674                         /* Check if VNI is masked. */
3675                         if (vxlan_spec && vxlan_mask) {
3676                                 is_vni_masked =
3677                                         !!memcmp(vxlan_mask->vni, vni_mask,
3678                                                  RTE_DIM(vni_mask));
3679                                 if (is_vni_masked) {
3680                                         rte_flow_error_set(error, EINVAL,
3681                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3682                                                    item,
3683                                                    "Invalid VNI mask");
3684                                         return -rte_errno;
3685                                 }
3686
3687                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3688                                            vxlan_spec->vni, 3);
3689                                 filter->tenant_id =
3690                                         rte_be_to_cpu_32(tenant_id_be);
3691                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3692                         }
3693
3694                         vxlan_flag = 1;
3695                         break;
3696                 default:
3697                         break;
3698                 }
3699         }
3700
3701         ret = i40e_check_tunnel_filter_type(filter_type);
3702         if (ret < 0) {
3703                 rte_flow_error_set(error, EINVAL,
3704                                    RTE_FLOW_ERROR_TYPE_ITEM,
3705                                    NULL,
3706                                    "Invalid filter type");
3707                 return -rte_errno;
3708         }
3709         filter->filter_type = filter_type;
3710
3711         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3712
3713         return 0;
3714 }
3715
3716 static int
3717 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3718                              const struct rte_flow_attr *attr,
3719                              const struct rte_flow_item pattern[],
3720                              const struct rte_flow_action actions[],
3721                              struct rte_flow_error *error,
3722                              union i40e_filter_t *filter)
3723 {
3724         struct i40e_tunnel_filter_conf *tunnel_filter =
3725                 &filter->consistent_tunnel_filter;
3726         int ret;
3727
3728         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3729                                             error, tunnel_filter);
3730         if (ret)
3731                 return ret;
3732
3733         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3734         if (ret)
3735                 return ret;
3736
3737         ret = i40e_flow_parse_attr(attr, error);
3738         if (ret)
3739                 return ret;
3740
3741         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3742
3743         return ret;
3744 }
3745
3746 /* 1. Last in item should be NULL as range is not supported.
3747  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3748  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3749  * 3. Mask of fields which need to be matched should be
3750  *    filled with 1.
3751  * 4. Mask of fields which needn't to be matched should be
3752  *    filled with 0.
3753  */
3754 static int
3755 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3756                               const struct rte_flow_item *pattern,
3757                               struct rte_flow_error *error,
3758                               struct i40e_tunnel_filter_conf *filter)
3759 {
3760         const struct rte_flow_item *item = pattern;
3761         const struct rte_flow_item_eth *eth_spec;
3762         const struct rte_flow_item_eth *eth_mask;
3763         const struct rte_flow_item_nvgre *nvgre_spec;
3764         const struct rte_flow_item_nvgre *nvgre_mask;
3765         const struct rte_flow_item_vlan *vlan_spec;
3766         const struct rte_flow_item_vlan *vlan_mask;
3767         enum rte_flow_item_type item_type;
3768         uint8_t filter_type = 0;
3769         bool is_tni_masked = 0;
3770         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3771         bool nvgre_flag = 0;
3772         uint32_t tenant_id_be = 0;
3773         int ret;
3774
3775         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3776                 if (item->last) {
3777                         rte_flow_error_set(error, EINVAL,
3778                                            RTE_FLOW_ERROR_TYPE_ITEM,
3779                                            item,
3780                                            "Not support range");
3781                         return -rte_errno;
3782                 }
3783                 item_type = item->type;
3784                 switch (item_type) {
3785                 case RTE_FLOW_ITEM_TYPE_ETH:
3786                         eth_spec = item->spec;
3787                         eth_mask = item->mask;
3788
3789                         /* Check if ETH item is used for place holder.
3790                          * If yes, both spec and mask should be NULL.
3791                          * If no, both spec and mask shouldn't be NULL.
3792                          */
3793                         if ((!eth_spec && eth_mask) ||
3794                             (eth_spec && !eth_mask)) {
3795                                 rte_flow_error_set(error, EINVAL,
3796                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3797                                                    item,
3798                                                    "Invalid ether spec/mask");
3799                                 return -rte_errno;
3800                         }
3801
3802                         if (eth_spec && eth_mask) {
3803                                 /* DST address of inner MAC shouldn't be masked.
3804                                  * SRC address of Inner MAC should be masked.
3805                                  */
3806                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3807                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3808                                     eth_mask->type) {
3809                                         rte_flow_error_set(error, EINVAL,
3810                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3811                                                    item,
3812                                                    "Invalid ether spec/mask");
3813                                         return -rte_errno;
3814                                 }
3815
3816                                 if (!nvgre_flag) {
3817                                         rte_memcpy(&filter->outer_mac,
3818                                                    &eth_spec->dst,
3819                                                    RTE_ETHER_ADDR_LEN);
3820                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3821                                 } else {
3822                                         rte_memcpy(&filter->inner_mac,
3823                                                    &eth_spec->dst,
3824                                                    RTE_ETHER_ADDR_LEN);
3825                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3826                                 }
3827                         }
3828
3829                         break;
3830                 case RTE_FLOW_ITEM_TYPE_VLAN:
3831                         vlan_spec = item->spec;
3832                         vlan_mask = item->mask;
3833                         if (!(vlan_spec && vlan_mask) ||
3834                             vlan_mask->inner_type) {
3835                                 rte_flow_error_set(error, EINVAL,
3836                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3837                                                    item,
3838                                                    "Invalid vlan item");
3839                                 return -rte_errno;
3840                         }
3841
3842                         if (vlan_spec && vlan_mask) {
3843                                 if (vlan_mask->tci ==
3844                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3845                                         filter->inner_vlan =
3846                                               rte_be_to_cpu_16(vlan_spec->tci) &
3847                                               I40E_TCI_MASK;
3848                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3849                         }
3850                         break;
3851                 case RTE_FLOW_ITEM_TYPE_IPV4:
3852                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3853                         /* IPv4 is used to describe protocol,
3854                          * spec and mask should be NULL.
3855                          */
3856                         if (item->spec || item->mask) {
3857                                 rte_flow_error_set(error, EINVAL,
3858                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3859                                                    item,
3860                                                    "Invalid IPv4 item");
3861                                 return -rte_errno;
3862                         }
3863                         break;
3864                 case RTE_FLOW_ITEM_TYPE_IPV6:
3865                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3866                         /* IPv6 is used to describe protocol,
3867                          * spec and mask should be NULL.
3868                          */
3869                         if (item->spec || item->mask) {
3870                                 rte_flow_error_set(error, EINVAL,
3871                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3872                                                    item,
3873                                                    "Invalid IPv6 item");
3874                                 return -rte_errno;
3875                         }
3876                         break;
3877                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3878                         nvgre_spec = item->spec;
3879                         nvgre_mask = item->mask;
3880                         /* Check if NVGRE item is used to describe protocol.
3881                          * If yes, both spec and mask should be NULL.
3882                          * If no, both spec and mask shouldn't be NULL.
3883                          */
3884                         if ((!nvgre_spec && nvgre_mask) ||
3885                             (nvgre_spec && !nvgre_mask)) {
3886                                 rte_flow_error_set(error, EINVAL,
3887                                            RTE_FLOW_ERROR_TYPE_ITEM,
3888                                            item,
3889                                            "Invalid NVGRE item");
3890                                 return -rte_errno;
3891                         }
3892
3893                         if (nvgre_spec && nvgre_mask) {
3894                                 is_tni_masked =
3895                                         !!memcmp(nvgre_mask->tni, tni_mask,
3896                                                  RTE_DIM(tni_mask));
3897                                 if (is_tni_masked) {
3898                                         rte_flow_error_set(error, EINVAL,
3899                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3900                                                        item,
3901                                                        "Invalid TNI mask");
3902                                         return -rte_errno;
3903                                 }
3904                                 if (nvgre_mask->protocol &&
3905                                         nvgre_mask->protocol != 0xFFFF) {
3906                                         rte_flow_error_set(error, EINVAL,
3907                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3908                                                 item,
3909                                                 "Invalid NVGRE item");
3910                                         return -rte_errno;
3911                                 }
3912                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3913                                         nvgre_mask->c_k_s_rsvd0_ver !=
3914                                         rte_cpu_to_be_16(0xFFFF)) {
3915                                         rte_flow_error_set(error, EINVAL,
3916                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3917                                                    item,
3918                                                    "Invalid NVGRE item");
3919                                         return -rte_errno;
3920                                 }
3921                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3922                                         rte_cpu_to_be_16(0x2000) &&
3923                                         nvgre_mask->c_k_s_rsvd0_ver) {
3924                                         rte_flow_error_set(error, EINVAL,
3925                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3926                                                    item,
3927                                                    "Invalid NVGRE item");
3928                                         return -rte_errno;
3929                                 }
3930                                 if (nvgre_mask->protocol &&
3931                                         nvgre_spec->protocol !=
3932                                         rte_cpu_to_be_16(0x6558)) {
3933                                         rte_flow_error_set(error, EINVAL,
3934                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3935                                                    item,
3936                                                    "Invalid NVGRE item");
3937                                         return -rte_errno;
3938                                 }
3939                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3940                                            nvgre_spec->tni, 3);
3941                                 filter->tenant_id =
3942                                         rte_be_to_cpu_32(tenant_id_be);
3943                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3944                         }
3945
3946                         nvgre_flag = 1;
3947                         break;
3948                 default:
3949                         break;
3950                 }
3951         }
3952
3953         ret = i40e_check_tunnel_filter_type(filter_type);
3954         if (ret < 0) {
3955                 rte_flow_error_set(error, EINVAL,
3956                                    RTE_FLOW_ERROR_TYPE_ITEM,
3957                                    NULL,
3958                                    "Invalid filter type");
3959                 return -rte_errno;
3960         }
3961         filter->filter_type = filter_type;
3962
3963         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3964
3965         return 0;
3966 }
3967
3968 static int
3969 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3970                              const struct rte_flow_attr *attr,
3971                              const struct rte_flow_item pattern[],
3972                              const struct rte_flow_action actions[],
3973                              struct rte_flow_error *error,
3974                              union i40e_filter_t *filter)
3975 {
3976         struct i40e_tunnel_filter_conf *tunnel_filter =
3977                 &filter->consistent_tunnel_filter;
3978         int ret;
3979
3980         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3981                                             error, tunnel_filter);
3982         if (ret)
3983                 return ret;
3984
3985         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3986         if (ret)
3987                 return ret;
3988
3989         ret = i40e_flow_parse_attr(attr, error);
3990         if (ret)
3991                 return ret;
3992
3993         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3994
3995         return ret;
3996 }
3997
3998 /* 1. Last in item should be NULL as range is not supported.
3999  * 2. Supported filter types: MPLS label.
4000  * 3. Mask of fields which need to be matched should be
4001  *    filled with 1.
4002  * 4. Mask of fields which needn't to be matched should be
4003  *    filled with 0.
4004  */
4005 static int
4006 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
4007                              const struct rte_flow_item *pattern,
4008                              struct rte_flow_error *error,
4009                              struct i40e_tunnel_filter_conf *filter)
4010 {
4011         const struct rte_flow_item *item = pattern;
4012         const struct rte_flow_item_mpls *mpls_spec;
4013         const struct rte_flow_item_mpls *mpls_mask;
4014         enum rte_flow_item_type item_type;
4015         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
4016         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
4017         uint32_t label_be = 0;
4018
4019         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4020                 if (item->last) {
4021                         rte_flow_error_set(error, EINVAL,
4022                                            RTE_FLOW_ERROR_TYPE_ITEM,
4023                                            item,
4024                                            "Not support range");
4025                         return -rte_errno;
4026                 }
4027                 item_type = item->type;
4028                 switch (item_type) {
4029                 case RTE_FLOW_ITEM_TYPE_ETH:
4030                         if (item->spec || item->mask) {
4031                                 rte_flow_error_set(error, EINVAL,
4032                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4033                                                    item,
4034                                                    "Invalid ETH item");
4035                                 return -rte_errno;
4036                         }
4037                         break;
4038                 case RTE_FLOW_ITEM_TYPE_IPV4:
4039                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4040                         /* IPv4 is used to describe protocol,
4041                          * spec and mask should be NULL.
4042                          */
4043                         if (item->spec || item->mask) {
4044                                 rte_flow_error_set(error, EINVAL,
4045                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4046                                                    item,
4047                                                    "Invalid IPv4 item");
4048                                 return -rte_errno;
4049                         }
4050                         break;
4051                 case RTE_FLOW_ITEM_TYPE_IPV6:
4052                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
4053                         /* IPv6 is used to describe protocol,
4054                          * spec and mask should be NULL.
4055                          */
4056                         if (item->spec || item->mask) {
4057                                 rte_flow_error_set(error, EINVAL,
4058                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4059                                                    item,
4060                                                    "Invalid IPv6 item");
4061                                 return -rte_errno;
4062                         }
4063                         break;
4064                 case RTE_FLOW_ITEM_TYPE_UDP:
4065                         /* UDP is used to describe protocol,
4066                          * spec and mask should be NULL.
4067                          */
4068                         if (item->spec || item->mask) {
4069                                 rte_flow_error_set(error, EINVAL,
4070                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4071                                                    item,
4072                                                    "Invalid UDP item");
4073                                 return -rte_errno;
4074                         }
4075                         is_mplsoudp = 1;
4076                         break;
4077                 case RTE_FLOW_ITEM_TYPE_GRE:
4078                         /* GRE is used to describe protocol,
4079                          * spec and mask should be NULL.
4080                          */
4081                         if (item->spec || item->mask) {
4082                                 rte_flow_error_set(error, EINVAL,
4083                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4084                                                    item,
4085                                                    "Invalid GRE item");
4086                                 return -rte_errno;
4087                         }
4088                         break;
4089                 case RTE_FLOW_ITEM_TYPE_MPLS:
4090                         mpls_spec = item->spec;
4091                         mpls_mask = item->mask;
4092
4093                         if (!mpls_spec || !mpls_mask) {
4094                                 rte_flow_error_set(error, EINVAL,
4095                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4096                                                    item,
4097                                                    "Invalid MPLS item");
4098                                 return -rte_errno;
4099                         }
4100
4101                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
4102                                 rte_flow_error_set(error, EINVAL,
4103                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4104                                                    item,
4105                                                    "Invalid MPLS label mask");
4106                                 return -rte_errno;
4107                         }
4108                         rte_memcpy(((uint8_t *)&label_be + 1),
4109                                    mpls_spec->label_tc_s, 3);
4110                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
4111                         break;
4112                 default:
4113                         break;
4114                 }
4115         }
4116
4117         if (is_mplsoudp)
4118                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
4119         else
4120                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
4121
4122         return 0;
4123 }
4124
4125 static int
4126 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
4127                             const struct rte_flow_attr *attr,
4128                             const struct rte_flow_item pattern[],
4129                             const struct rte_flow_action actions[],
4130                             struct rte_flow_error *error,
4131                             union i40e_filter_t *filter)
4132 {
4133         struct i40e_tunnel_filter_conf *tunnel_filter =
4134                 &filter->consistent_tunnel_filter;
4135         int ret;
4136
4137         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
4138                                            error, tunnel_filter);
4139         if (ret)
4140                 return ret;
4141
4142         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4143         if (ret)
4144                 return ret;
4145
4146         ret = i40e_flow_parse_attr(attr, error);
4147         if (ret)
4148                 return ret;
4149
4150         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4151
4152         return ret;
4153 }
4154
4155 /* 1. Last in item should be NULL as range is not supported.
4156  * 2. Supported filter types: GTP TEID.
4157  * 3. Mask of fields which need to be matched should be
4158  *    filled with 1.
4159  * 4. Mask of fields which needn't to be matched should be
4160  *    filled with 0.
4161  * 5. GTP profile supports GTPv1 only.
4162  * 6. GTP-C response message ('source_port' = 2123) is not supported.
4163  */
4164 static int
4165 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
4166                             const struct rte_flow_item *pattern,
4167                             struct rte_flow_error *error,
4168                             struct i40e_tunnel_filter_conf *filter)
4169 {
4170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4171         const struct rte_flow_item *item = pattern;
4172         const struct rte_flow_item_gtp *gtp_spec;
4173         const struct rte_flow_item_gtp *gtp_mask;
4174         enum rte_flow_item_type item_type;
4175
4176         if (!pf->gtp_support) {
4177                 rte_flow_error_set(error, EINVAL,
4178                                    RTE_FLOW_ERROR_TYPE_ITEM,
4179                                    item,
4180                                    "GTP is not supported by default.");
4181                 return -rte_errno;
4182         }
4183
4184         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4185                 if (item->last) {
4186                         rte_flow_error_set(error, EINVAL,
4187                                            RTE_FLOW_ERROR_TYPE_ITEM,
4188                                            item,
4189                                            "Not support range");
4190                         return -rte_errno;
4191                 }
4192                 item_type = item->type;
4193                 switch (item_type) {
4194                 case RTE_FLOW_ITEM_TYPE_ETH:
4195                         if (item->spec || item->mask) {
4196                                 rte_flow_error_set(error, EINVAL,
4197                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4198                                                    item,
4199                                                    "Invalid ETH item");
4200                                 return -rte_errno;
4201                         }
4202                         break;
4203                 case RTE_FLOW_ITEM_TYPE_IPV4:
4204                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4205                         /* IPv4 is used to describe protocol,
4206                          * spec and mask should be NULL.
4207                          */
4208                         if (item->spec || item->mask) {
4209                                 rte_flow_error_set(error, EINVAL,
4210                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4211                                                    item,
4212                                                    "Invalid IPv4 item");
4213                                 return -rte_errno;
4214                         }
4215                         break;
4216                 case RTE_FLOW_ITEM_TYPE_UDP:
4217                         if (item->spec || item->mask) {
4218                                 rte_flow_error_set(error, EINVAL,
4219                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4220                                                    item,
4221                                                    "Invalid UDP item");
4222                                 return -rte_errno;
4223                         }
4224                         break;
4225                 case RTE_FLOW_ITEM_TYPE_GTPC:
4226                 case RTE_FLOW_ITEM_TYPE_GTPU:
4227                         gtp_spec = item->spec;
4228                         gtp_mask = item->mask;
4229
4230                         if (!gtp_spec || !gtp_mask) {
4231                                 rte_flow_error_set(error, EINVAL,
4232                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4233                                                    item,
4234                                                    "Invalid GTP item");
4235                                 return -rte_errno;
4236                         }
4237
4238                         if (gtp_mask->v_pt_rsv_flags ||
4239                             gtp_mask->msg_type ||
4240                             gtp_mask->msg_len ||
4241                             gtp_mask->teid != UINT32_MAX) {
4242                                 rte_flow_error_set(error, EINVAL,
4243                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4244                                                    item,
4245                                                    "Invalid GTP mask");
4246                                 return -rte_errno;
4247                         }
4248
4249                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
4250                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
4251                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
4252                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
4253
4254                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4255
4256                         break;
4257                 default:
4258                         break;
4259                 }
4260         }
4261
4262         return 0;
4263 }
4264
4265 static int
4266 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4267                            const struct rte_flow_attr *attr,
4268                            const struct rte_flow_item pattern[],
4269                            const struct rte_flow_action actions[],
4270                            struct rte_flow_error *error,
4271                            union i40e_filter_t *filter)
4272 {
4273         struct i40e_tunnel_filter_conf *tunnel_filter =
4274                 &filter->consistent_tunnel_filter;
4275         int ret;
4276
4277         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4278                                           error, tunnel_filter);
4279         if (ret)
4280                 return ret;
4281
4282         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4283         if (ret)
4284                 return ret;
4285
4286         ret = i40e_flow_parse_attr(attr, error);
4287         if (ret)
4288                 return ret;
4289
4290         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4291
4292         return ret;
4293 }
4294
4295 /* 1. Last in item should be NULL as range is not supported.
4296  * 2. Supported filter types: QINQ.
4297  * 3. Mask of fields which need to be matched should be
4298  *    filled with 1.
4299  * 4. Mask of fields which needn't to be matched should be
4300  *    filled with 0.
4301  */
4302 static int
4303 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4304                               const struct rte_flow_item *pattern,
4305                               struct rte_flow_error *error,
4306                               struct i40e_tunnel_filter_conf *filter)
4307 {
4308         const struct rte_flow_item *item = pattern;
4309         const struct rte_flow_item_vlan *vlan_spec = NULL;
4310         const struct rte_flow_item_vlan *vlan_mask = NULL;
4311         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4312         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4313         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4314         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4315
4316         enum rte_flow_item_type item_type;
4317         bool vlan_flag = 0;
4318
4319         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4320                 if (item->last) {
4321                         rte_flow_error_set(error, EINVAL,
4322                                            RTE_FLOW_ERROR_TYPE_ITEM,
4323                                            item,
4324                                            "Not support range");
4325                         return -rte_errno;
4326                 }
4327                 item_type = item->type;
4328                 switch (item_type) {
4329                 case RTE_FLOW_ITEM_TYPE_ETH:
4330                         if (item->spec || item->mask) {
4331                                 rte_flow_error_set(error, EINVAL,
4332                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4333                                                    item,
4334                                                    "Invalid ETH item");
4335                                 return -rte_errno;
4336                         }
4337                         break;
4338                 case RTE_FLOW_ITEM_TYPE_VLAN:
4339                         vlan_spec = item->spec;
4340                         vlan_mask = item->mask;
4341
4342                         if (!(vlan_spec && vlan_mask) ||
4343                             vlan_mask->inner_type) {
4344                                 rte_flow_error_set(error, EINVAL,
4345                                            RTE_FLOW_ERROR_TYPE_ITEM,
4346                                            item,
4347                                            "Invalid vlan item");
4348                                 return -rte_errno;
4349                         }
4350
4351                         if (!vlan_flag) {
4352                                 o_vlan_spec = vlan_spec;
4353                                 o_vlan_mask = vlan_mask;
4354                                 vlan_flag = 1;
4355                         } else {
4356                                 i_vlan_spec = vlan_spec;
4357                                 i_vlan_mask = vlan_mask;
4358                                 vlan_flag = 0;
4359                         }
4360                         break;
4361
4362                 default:
4363                         break;
4364                 }
4365         }
4366
4367         /* Get filter specification */
4368         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4369                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4370                         (i_vlan_mask != NULL) &&
4371                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4372                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4373                         & I40E_TCI_MASK;
4374                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4375                         & I40E_TCI_MASK;
4376         } else {
4377                         rte_flow_error_set(error, EINVAL,
4378                                            RTE_FLOW_ERROR_TYPE_ITEM,
4379                                            NULL,
4380                                            "Invalid filter type");
4381                         return -rte_errno;
4382         }
4383
4384         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4385         return 0;
4386 }
4387
4388 static int
4389 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4390                               const struct rte_flow_attr *attr,
4391                               const struct rte_flow_item pattern[],
4392                               const struct rte_flow_action actions[],
4393                               struct rte_flow_error *error,
4394                               union i40e_filter_t *filter)
4395 {
4396         struct i40e_tunnel_filter_conf *tunnel_filter =
4397                 &filter->consistent_tunnel_filter;
4398         int ret;
4399
4400         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4401                                              error, tunnel_filter);
4402         if (ret)
4403                 return ret;
4404
4405         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4406         if (ret)
4407                 return ret;
4408
4409         ret = i40e_flow_parse_attr(attr, error);
4410         if (ret)
4411                 return ret;
4412
4413         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4414
4415         return ret;
4416 }
4417
4418 /**
4419  * This function is used to do configuration i40e existing RSS with rte_flow.
4420  * It also enable queue region configuration using flow API for i40e.
4421  * pattern can be used indicate what parameters will be include in flow,
4422  * like user_priority or flowtype for queue region or HASH function for RSS.
4423  * Action is used to transmit parameter like queue index and HASH
4424  * function for RSS, or flowtype for queue region configuration.
4425  * For example:
4426  * pattern:
4427  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4428  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4429  * Case 3: none, indicate RSS related will be parsed in action.
4430  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4431  * So, pattern choice is depened on the purpose of configuration of
4432  * that flow.
4433  * action:
4434  * action RSS will be uaed to transmit valid parameter with
4435  * struct rte_flow_action_rss for all the 3 case.
4436  */
4437 static int
4438 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4439                              const struct rte_flow_item *pattern,
4440                              struct rte_flow_error *error,
4441                              uint8_t *action_flag,
4442                              struct i40e_queue_regions *info)
4443 {
4444         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4445         const struct rte_flow_item *item = pattern;
4446         enum rte_flow_item_type item_type;
4447
4448         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4449                 return 0;
4450
4451         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4452                 if (item->last) {
4453                         rte_flow_error_set(error, EINVAL,
4454                                            RTE_FLOW_ERROR_TYPE_ITEM,
4455                                            item,
4456                                            "Not support range");
4457                         return -rte_errno;
4458                 }
4459                 item_type = item->type;
4460                 switch (item_type) {
4461                 case RTE_FLOW_ITEM_TYPE_ETH:
4462                         *action_flag = 1;
4463                         break;
4464                 case RTE_FLOW_ITEM_TYPE_VLAN:
4465                         vlan_spec = item->spec;
4466                         vlan_mask = item->mask;
4467                         if (vlan_spec && vlan_mask) {
4468                                 if (vlan_mask->tci ==
4469                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4470                                         info->region[0].user_priority[0] =
4471                                                 (rte_be_to_cpu_16(
4472                                                 vlan_spec->tci) >> 13) & 0x7;
4473                                         info->region[0].user_priority_num = 1;
4474                                         info->queue_region_number = 1;
4475                                         *action_flag = 0;
4476                                 }
4477                         }
4478                         break;
4479                 default:
4480                         rte_flow_error_set(error, EINVAL,
4481                                         RTE_FLOW_ERROR_TYPE_ITEM,
4482                                         item,
4483                                         "Not support range");
4484                         return -rte_errno;
4485                 }
4486         }
4487
4488         return 0;
4489 }
4490
4491 /**
4492  * This function is used to parse rss queue index, total queue number and
4493  * hash functions, If the purpose of this configuration is for queue region
4494  * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4495  * In queue region configuration, it also need to parse hardware flowtype
4496  * and user_priority from configuration, it will also cheeck the validity
4497  * of these parameters. For example, The queue region sizes should
4498  * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4499  * hw_flowtype or PCTYPE max index should be 63, the user priority
4500  * max index should be 7, and so on. And also, queue index should be
4501  * continuous sequence and queue region index should be part of rss
4502  * queue index for this port.
4503  */
4504 static int
4505 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4506                             const struct rte_flow_action *actions,
4507                             struct rte_flow_error *error,
4508                             uint8_t action_flag,
4509                             struct i40e_queue_regions *conf_info,
4510                             union i40e_filter_t *filter)
4511 {
4512         const struct rte_flow_action *act;
4513         const struct rte_flow_action_rss *rss;
4514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4515         struct i40e_queue_regions *info = &pf->queue_region;
4516         struct i40e_rte_flow_rss_conf *rss_config =
4517                         &filter->rss_conf;
4518         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4519         uint16_t i, j, n, tmp;
4520         uint32_t index = 0;
4521         uint64_t hf_bit = 1;
4522
4523         NEXT_ITEM_OF_ACTION(act, actions, index);
4524         rss = act->conf;
4525
4526         /**
4527          * rss only supports forwarding,
4528          * check if the first not void action is RSS.
4529          */
4530         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4531                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4532                 rte_flow_error_set(error, EINVAL,
4533                         RTE_FLOW_ERROR_TYPE_ACTION,
4534                         act, "Not supported action.");
4535                 return -rte_errno;
4536         }
4537
4538         if (action_flag) {
4539                 for (n = 0; n < 64; n++) {
4540                         if (rss->types & (hf_bit << n)) {
4541                                 conf_info->region[0].hw_flowtype[0] = n;
4542                                 conf_info->region[0].flowtype_num = 1;
4543                                 conf_info->queue_region_number = 1;
4544                                 break;
4545                         }
4546                 }
4547         }
4548
4549         /**
4550          * Do some queue region related parameters check
4551          * in order to keep queue index for queue region to be
4552          * continuous sequence and also to be part of RSS
4553          * queue index for this port.
4554          */
4555         if (conf_info->queue_region_number) {
4556                 for (i = 0; i < rss->queue_num; i++) {
4557                         for (j = 0; j < rss_info->conf.queue_num; j++) {
4558                                 if (rss->queue[i] == rss_info->conf.queue[j])
4559                                         break;
4560                         }
4561                         if (j == rss_info->conf.queue_num) {
4562                                 rte_flow_error_set(error, EINVAL,
4563                                         RTE_FLOW_ERROR_TYPE_ACTION,
4564                                         act,
4565                                         "no valid queues");
4566                                 return -rte_errno;
4567                         }
4568                 }
4569
4570                 for (i = 0; i < rss->queue_num - 1; i++) {
4571                         if (rss->queue[i + 1] != rss->queue[i] + 1) {
4572                                 rte_flow_error_set(error, EINVAL,
4573                                         RTE_FLOW_ERROR_TYPE_ACTION,
4574                                         act,
4575                                         "no valid queues");
4576                                 return -rte_errno;
4577                         }
4578                 }
4579         }
4580
4581         /* Parse queue region related parameters from configuration */
4582         for (n = 0; n < conf_info->queue_region_number; n++) {
4583                 if (conf_info->region[n].user_priority_num ||
4584                                 conf_info->region[n].flowtype_num) {
4585                         if (!((rte_is_power_of_2(rss->queue_num)) &&
4586                                         rss->queue_num <= 64)) {
4587                                 rte_flow_error_set(error, EINVAL,
4588                                         RTE_FLOW_ERROR_TYPE_ACTION,
4589                                         act,
4590                                         "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4591                                         "total number of queues do not exceed the VSI allocation");
4592                                 return -rte_errno;
4593                         }
4594
4595                         if (conf_info->region[n].user_priority[n] >=
4596                                         I40E_MAX_USER_PRIORITY) {
4597                                 rte_flow_error_set(error, EINVAL,
4598                                         RTE_FLOW_ERROR_TYPE_ACTION,
4599                                         act,
4600                                         "the user priority max index is 7");
4601                                 return -rte_errno;
4602                         }
4603
4604                         if (conf_info->region[n].hw_flowtype[n] >=
4605                                         I40E_FILTER_PCTYPE_MAX) {
4606                                 rte_flow_error_set(error, EINVAL,
4607                                         RTE_FLOW_ERROR_TYPE_ACTION,
4608                                         act,
4609                                         "the hw_flowtype or PCTYPE max index is 63");
4610                                 return -rte_errno;
4611                         }
4612
4613                         for (i = 0; i < info->queue_region_number; i++) {
4614                                 if (info->region[i].queue_num ==
4615                                     rss->queue_num &&
4616                                         info->region[i].queue_start_index ==
4617                                                 rss->queue[0])
4618                                         break;
4619                         }
4620
4621                         if (i == info->queue_region_number) {
4622                                 if (i > I40E_REGION_MAX_INDEX) {
4623                                         rte_flow_error_set(error, EINVAL,
4624                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4625                                                 act,
4626                                                 "the queue region max index is 7");
4627                                         return -rte_errno;
4628                                 }
4629
4630                                 info->region[i].queue_num =
4631                                         rss->queue_num;
4632                                 info->region[i].queue_start_index =
4633                                         rss->queue[0];
4634                                 info->region[i].region_id =
4635                                         info->queue_region_number;
4636
4637                                 j = info->region[i].user_priority_num;
4638                                 tmp = conf_info->region[n].user_priority[0];
4639                                 if (conf_info->region[n].user_priority_num) {
4640                                         info->region[i].user_priority[j] = tmp;
4641                                         info->region[i].user_priority_num++;
4642                                 }
4643
4644                                 j = info->region[i].flowtype_num;
4645                                 tmp = conf_info->region[n].hw_flowtype[0];
4646                                 if (conf_info->region[n].flowtype_num) {
4647                                         info->region[i].hw_flowtype[j] = tmp;
4648                                         info->region[i].flowtype_num++;
4649                                 }
4650                                 info->queue_region_number++;
4651                         } else {
4652                                 j = info->region[i].user_priority_num;
4653                                 tmp = conf_info->region[n].user_priority[0];
4654                                 if (conf_info->region[n].user_priority_num) {
4655                                         info->region[i].user_priority[j] = tmp;
4656                                         info->region[i].user_priority_num++;
4657                                 }
4658
4659                                 j = info->region[i].flowtype_num;
4660                                 tmp = conf_info->region[n].hw_flowtype[0];
4661                                 if (conf_info->region[n].flowtype_num) {
4662                                         info->region[i].hw_flowtype[j] = tmp;
4663                                         info->region[i].flowtype_num++;
4664                                 }
4665                         }
4666                 }
4667
4668                 rss_config->queue_region_conf = TRUE;
4669         }
4670
4671         /**
4672          * Return function if this flow is used for queue region configuration
4673          */
4674         if (rss_config->queue_region_conf)
4675                 return 0;
4676
4677         if (!rss || !rss->queue_num) {
4678                 rte_flow_error_set(error, EINVAL,
4679                                 RTE_FLOW_ERROR_TYPE_ACTION,
4680                                 act,
4681                                 "no valid queues");
4682                 return -rte_errno;
4683         }
4684
4685         for (n = 0; n < rss->queue_num; n++) {
4686                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4687                         rte_flow_error_set(error, EINVAL,
4688                                    RTE_FLOW_ERROR_TYPE_ACTION,
4689                                    act,
4690                                    "queue id > max number of queues");
4691                         return -rte_errno;
4692                 }
4693         }
4694
4695         if (rss_info->conf.queue_num) {
4696                 rte_flow_error_set(error, EINVAL,
4697                                 RTE_FLOW_ERROR_TYPE_ACTION,
4698                                 act,
4699                                 "rss only allow one valid rule");
4700                 return -rte_errno;
4701         }
4702
4703         /* Parse RSS related parameters from configuration */
4704         if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4705                 return rte_flow_error_set
4706                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4707                          "non-default RSS hash functions are not supported");
4708         if (rss->level)
4709                 return rte_flow_error_set
4710                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4711                          "a nonzero RSS encapsulation level is not supported");
4712         if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4713                 return rte_flow_error_set
4714                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4715                          "RSS hash key too large");
4716         if (rss->queue_num > RTE_DIM(rss_config->queue))
4717                 return rte_flow_error_set
4718                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4719                          "too many queues for RSS context");
4720         if (i40e_rss_conf_init(rss_config, rss))
4721                 return rte_flow_error_set
4722                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4723                          "RSS context initialization failure");
4724
4725         index++;
4726
4727         /* check if the next not void action is END */
4728         NEXT_ITEM_OF_ACTION(act, actions, index);
4729         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4730                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4731                 rte_flow_error_set(error, EINVAL,
4732                         RTE_FLOW_ERROR_TYPE_ACTION,
4733                         act, "Not supported action.");
4734                 return -rte_errno;
4735         }
4736         rss_config->queue_region_conf = FALSE;
4737
4738         return 0;
4739 }
4740
4741 static int
4742 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4743                         const struct rte_flow_attr *attr,
4744                         const struct rte_flow_item pattern[],
4745                         const struct rte_flow_action actions[],
4746                         union i40e_filter_t *filter,
4747                         struct rte_flow_error *error)
4748 {
4749         int ret;
4750         struct i40e_queue_regions info;
4751         uint8_t action_flag = 0;
4752
4753         memset(&info, 0, sizeof(struct i40e_queue_regions));
4754
4755         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4756                                         error, &action_flag, &info);
4757         if (ret)
4758                 return ret;
4759
4760         ret = i40e_flow_parse_rss_action(dev, actions, error,
4761                                         action_flag, &info, filter);
4762         if (ret)
4763                 return ret;
4764
4765         ret = i40e_flow_parse_attr(attr, error);
4766         if (ret)
4767                 return ret;
4768
4769         cons_filter_type = RTE_ETH_FILTER_HASH;
4770
4771         return 0;
4772 }
4773
4774 static int
4775 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4776                 struct i40e_rte_flow_rss_conf *conf)
4777 {
4778         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4780         int ret;
4781
4782         if (conf->queue_region_conf) {
4783                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4784                 conf->queue_region_conf = 0;
4785         } else {
4786                 ret = i40e_config_rss_filter(pf, conf, 1);
4787         }
4788         return ret;
4789 }
4790
4791 static int
4792 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4793                 struct i40e_rte_flow_rss_conf *conf)
4794 {
4795         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797
4798         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4799
4800         i40e_config_rss_filter(pf, conf, 0);
4801         return 0;
4802 }
4803
4804 static int
4805 i40e_flow_validate(struct rte_eth_dev *dev,
4806                    const struct rte_flow_attr *attr,
4807                    const struct rte_flow_item pattern[],
4808                    const struct rte_flow_action actions[],
4809                    struct rte_flow_error *error)
4810 {
4811         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4812         parse_filter_t parse_filter;
4813         uint32_t item_num = 0; /* non-void item number of pattern*/
4814         uint32_t i = 0;
4815         bool flag = false;
4816         int ret = I40E_NOT_SUPPORTED;
4817
4818         if (!pattern) {
4819                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4820                                    NULL, "NULL pattern.");
4821                 return -rte_errno;
4822         }
4823
4824         if (!actions) {
4825                 rte_flow_error_set(error, EINVAL,
4826                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4827                                    NULL, "NULL action.");
4828                 return -rte_errno;
4829         }
4830
4831         if (!attr) {
4832                 rte_flow_error_set(error, EINVAL,
4833                                    RTE_FLOW_ERROR_TYPE_ATTR,
4834                                    NULL, "NULL attribute.");
4835                 return -rte_errno;
4836         }
4837
4838         memset(&cons_filter, 0, sizeof(cons_filter));
4839
4840         /* Get the non-void item of action */
4841         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4842                 i++;
4843
4844         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4845                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4846                                         actions, &cons_filter, error);
4847                 return ret;
4848         }
4849
4850         i = 0;
4851         /* Get the non-void item number of pattern */
4852         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4853                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4854                         item_num++;
4855                 i++;
4856         }
4857         item_num++;
4858
4859         items = rte_zmalloc("i40e_pattern",
4860                             item_num * sizeof(struct rte_flow_item), 0);
4861         if (!items) {
4862                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4863                                    NULL, "No memory for PMD internal items.");
4864                 return -ENOMEM;
4865         }
4866
4867         i40e_pattern_skip_void_item(items, pattern);
4868
4869         i = 0;
4870         do {
4871                 parse_filter = i40e_find_parse_filter_func(items, &i);
4872                 if (!parse_filter && !flag) {
4873                         rte_flow_error_set(error, EINVAL,
4874                                            RTE_FLOW_ERROR_TYPE_ITEM,
4875                                            pattern, "Unsupported pattern");
4876                         rte_free(items);
4877                         return -rte_errno;
4878                 }
4879                 if (parse_filter)
4880                         ret = parse_filter(dev, attr, items, actions,
4881                                            error, &cons_filter);
4882                 flag = true;
4883         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4884
4885         rte_free(items);
4886
4887         return ret;
4888 }
4889
4890 static struct rte_flow *
4891 i40e_flow_create(struct rte_eth_dev *dev,
4892                  const struct rte_flow_attr *attr,
4893                  const struct rte_flow_item pattern[],
4894                  const struct rte_flow_action actions[],
4895                  struct rte_flow_error *error)
4896 {
4897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4898         struct rte_flow *flow;
4899         int ret;
4900
4901         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4902         if (!flow) {
4903                 rte_flow_error_set(error, ENOMEM,
4904                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4905                                    "Failed to allocate memory");
4906                 return flow;
4907         }
4908
4909         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4910         if (ret < 0)
4911                 return NULL;
4912
4913         switch (cons_filter_type) {
4914         case RTE_ETH_FILTER_ETHERTYPE:
4915                 ret = i40e_ethertype_filter_set(pf,
4916                                         &cons_filter.ethertype_filter, 1);
4917                 if (ret)
4918                         goto free_flow;
4919                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4920                                         i40e_ethertype_filter_list);
4921                 break;
4922         case RTE_ETH_FILTER_FDIR:
4923                 ret = i40e_flow_add_del_fdir_filter(dev,
4924                                        &cons_filter.fdir_filter, 1);
4925                 if (ret)
4926                         goto free_flow;
4927                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4928                                         i40e_fdir_filter_list);
4929                 break;
4930         case RTE_ETH_FILTER_TUNNEL:
4931                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4932                             &cons_filter.consistent_tunnel_filter, 1);
4933                 if (ret)
4934                         goto free_flow;
4935                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4936                                         i40e_tunnel_filter_list);
4937                 break;
4938         case RTE_ETH_FILTER_HASH:
4939                 ret = i40e_config_rss_filter_set(dev,
4940                             &cons_filter.rss_conf);
4941                 if (ret)
4942                         goto free_flow;
4943                 flow->rule = &pf->rss_info;
4944                 break;
4945         default:
4946                 goto free_flow;
4947         }
4948
4949         flow->filter_type = cons_filter_type;
4950         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4951         return flow;
4952
4953 free_flow:
4954         rte_flow_error_set(error, -ret,
4955                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4956                            "Failed to create flow.");
4957         rte_free(flow);
4958         return NULL;
4959 }
4960
4961 static int
4962 i40e_flow_destroy(struct rte_eth_dev *dev,
4963                   struct rte_flow *flow,
4964                   struct rte_flow_error *error)
4965 {
4966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4967         enum rte_filter_type filter_type = flow->filter_type;
4968         int ret = 0;
4969
4970         switch (filter_type) {
4971         case RTE_ETH_FILTER_ETHERTYPE:
4972                 ret = i40e_flow_destroy_ethertype_filter(pf,
4973                          (struct i40e_ethertype_filter *)flow->rule);
4974                 break;
4975         case RTE_ETH_FILTER_TUNNEL:
4976                 ret = i40e_flow_destroy_tunnel_filter(pf,
4977                               (struct i40e_tunnel_filter *)flow->rule);
4978                 break;
4979         case RTE_ETH_FILTER_FDIR:
4980                 ret = i40e_flow_add_del_fdir_filter(dev,
4981                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4982
4983                 /* If the last flow is destroyed, disable fdir. */
4984                 if (!ret && TAILQ_EMPTY(&pf->fdir.fdir_list)) {
4985                         i40e_fdir_teardown(pf);
4986                         dev->data->dev_conf.fdir_conf.mode =
4987                                    RTE_FDIR_MODE_NONE;
4988                         i40e_fdir_rx_proc_enable(dev, 0);
4989                 }
4990                 break;
4991         case RTE_ETH_FILTER_HASH:
4992                 ret = i40e_config_rss_filter_del(dev,
4993                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4994                 break;
4995         default:
4996                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4997                             filter_type);
4998                 ret = -EINVAL;
4999                 break;
5000         }
5001
5002         if (!ret) {
5003                 TAILQ_REMOVE(&pf->flow_list, flow, node);
5004                 rte_free(flow);
5005         } else
5006                 rte_flow_error_set(error, -ret,
5007                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5008                                    "Failed to destroy flow.");
5009
5010         return ret;
5011 }
5012
5013 static int
5014 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
5015                                    struct i40e_ethertype_filter *filter)
5016 {
5017         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5018         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
5019         struct i40e_ethertype_filter *node;
5020         struct i40e_control_filter_stats stats;
5021         uint16_t flags = 0;
5022         int ret = 0;
5023
5024         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5025                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5026         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5027                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5028         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5029
5030         memset(&stats, 0, sizeof(stats));
5031         ret = i40e_aq_add_rem_control_packet_filter(hw,
5032                                     filter->input.mac_addr.addr_bytes,
5033                                     filter->input.ether_type,
5034                                     flags, pf->main_vsi->seid,
5035                                     filter->queue, 0, &stats, NULL);
5036         if (ret < 0)
5037                 return ret;
5038
5039         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
5040         if (!node)
5041                 return -EINVAL;
5042
5043         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
5044
5045         return ret;
5046 }
5047
5048 static int
5049 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
5050                                 struct i40e_tunnel_filter *filter)
5051 {
5052         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5053         struct i40e_vsi *vsi;
5054         struct i40e_pf_vf *vf;
5055         struct i40e_aqc_cloud_filters_element_bb cld_filter;
5056         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
5057         struct i40e_tunnel_filter *node;
5058         bool big_buffer = 0;
5059         int ret = 0;
5060
5061         memset(&cld_filter, 0, sizeof(cld_filter));
5062         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac,
5063                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
5064         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac,
5065                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
5066         cld_filter.element.inner_vlan = filter->input.inner_vlan;
5067         cld_filter.element.flags = filter->input.flags;
5068         cld_filter.element.tenant_id = filter->input.tenant_id;
5069         cld_filter.element.queue_number = filter->queue;
5070         rte_memcpy(cld_filter.general_fields,
5071                    filter->input.general_fields,
5072                    sizeof(cld_filter.general_fields));
5073
5074         if (!filter->is_to_vf)
5075                 vsi = pf->main_vsi;
5076         else {
5077                 vf = &pf->vfs[filter->vf_id];
5078                 vsi = vf->vsi;
5079         }
5080
5081         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
5082             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
5083             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
5084             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
5085             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
5086             I40E_AQC_ADD_CLOUD_FILTER_0X10))
5087                 big_buffer = 1;
5088
5089         if (big_buffer)
5090                 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid,
5091                                                 &cld_filter, 1);
5092         else
5093                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
5094                                                 &cld_filter.element, 1);
5095         if (ret < 0)
5096                 return -ENOTSUP;
5097
5098         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
5099         if (!node)
5100                 return -EINVAL;
5101
5102         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
5103
5104         return ret;
5105 }
5106
5107 static int
5108 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
5109 {
5110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5111         int ret;
5112
5113         ret = i40e_flow_flush_fdir_filter(pf);
5114         if (ret) {
5115                 rte_flow_error_set(error, -ret,
5116                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5117                                    "Failed to flush FDIR flows.");
5118                 return -rte_errno;
5119         }
5120
5121         ret = i40e_flow_flush_ethertype_filter(pf);
5122         if (ret) {
5123                 rte_flow_error_set(error, -ret,
5124                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5125                                    "Failed to ethertype flush flows.");
5126                 return -rte_errno;
5127         }
5128
5129         ret = i40e_flow_flush_tunnel_filter(pf);
5130         if (ret) {
5131                 rte_flow_error_set(error, -ret,
5132                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5133                                    "Failed to flush tunnel flows.");
5134                 return -rte_errno;
5135         }
5136
5137         ret = i40e_flow_flush_rss_filter(dev);
5138         if (ret) {
5139                 rte_flow_error_set(error, -ret,
5140                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5141                                    "Failed to flush rss flows.");
5142                 return -rte_errno;
5143         }
5144
5145         /* Disable FDIR processing as all FDIR rules are now flushed */
5146         i40e_fdir_rx_proc_enable(dev, 0);
5147
5148         return ret;
5149 }
5150
5151 static int
5152 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
5153 {
5154         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5155         struct i40e_fdir_info *fdir_info = &pf->fdir;
5156         struct i40e_fdir_filter *fdir_filter;
5157         enum i40e_filter_pctype pctype;
5158         struct rte_flow *flow;
5159         void *temp;
5160         int ret;
5161
5162         ret = i40e_fdir_flush(dev);
5163         if (!ret) {
5164                 /* Delete FDIR filters in FDIR list. */
5165                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
5166                         ret = i40e_sw_fdir_filter_del(pf,
5167                                                       &fdir_filter->fdir.input);
5168                         if (ret < 0)
5169                                 return ret;
5170                 }
5171
5172                 /* Delete FDIR flows in flow list. */
5173                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5174                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
5175                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
5176                                 rte_free(flow);
5177                         }
5178                 }
5179
5180                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5181                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
5182                         pf->fdir.inset_flag[pctype] = 0;
5183         }
5184
5185         i40e_fdir_teardown(pf);
5186
5187         return ret;
5188 }
5189
5190 /* Flush all ethertype filters */
5191 static int
5192 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
5193 {
5194         struct i40e_ethertype_filter_list
5195                 *ethertype_list = &pf->ethertype.ethertype_list;
5196         struct i40e_ethertype_filter *filter;
5197         struct rte_flow *flow;
5198         void *temp;
5199         int ret = 0;
5200
5201         while ((filter = TAILQ_FIRST(ethertype_list))) {
5202                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
5203                 if (ret)
5204                         return ret;
5205         }
5206
5207         /* Delete ethertype flows in flow list. */
5208         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5209                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
5210                         TAILQ_REMOVE(&pf->flow_list, flow, node);
5211                         rte_free(flow);
5212                 }
5213         }
5214
5215         return ret;
5216 }
5217
5218 /* Flush all tunnel filters */
5219 static int
5220 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
5221 {
5222         struct i40e_tunnel_filter_list
5223                 *tunnel_list = &pf->tunnel.tunnel_list;
5224         struct i40e_tunnel_filter *filter;
5225         struct rte_flow *flow;
5226         void *temp;
5227         int ret = 0;
5228
5229         while ((filter = TAILQ_FIRST(tunnel_list))) {
5230                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
5231                 if (ret)
5232                         return ret;
5233         }
5234
5235         /* Delete tunnel flows in flow list. */
5236         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5237                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
5238                         TAILQ_REMOVE(&pf->flow_list, flow, node);
5239                         rte_free(flow);
5240                 }
5241         }
5242
5243         return ret;
5244 }
5245
5246 /* remove the rss filter */
5247 static int
5248 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
5249 {
5250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5251         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
5252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5253         int32_t ret = -EINVAL;
5254
5255         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5256
5257         if (rss_info->conf.queue_num)
5258                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
5259         return ret;
5260 }