drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_debug.h>
  14 #include <rte_ether.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_log.h>
  17 #include <rte_malloc.h>
  18 #include <rte_eth_ctrl.h>
  19 #include <rte_tailq.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "i40e_logs.h"
  23 #include "base/i40e_type.h"
  24 #include "base/i40e_prototype.h"
  25 #include "i40e_ethdev.h"
  26
  27 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  28 #define I40E_IPV6_FRAG_HEADER   44
  29 #define I40E_TENANT_ARRAY_NUM   3
  30 #define I40E_TCI_MASK           0xFFFF
  31
  32 static int i40e_flow_validate(struct rte_eth_dev *dev,
  33                               const struct rte_flow_attr *attr,
  34                               const struct rte_flow_item pattern[],
  35                               const struct rte_flow_action actions[],
  36                               struct rte_flow_error *error);
  37 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  38                                          const struct rte_flow_attr *attr,
  39                                          const struct rte_flow_item pattern[],
  40                                          const struct rte_flow_action actions[],
  41                                          struct rte_flow_error *error);
  42 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  43                              struct rte_flow *flow,
  44                              struct rte_flow_error *error);
  45 static int i40e_flow_flush(struct rte_eth_dev *dev,
  46                            struct rte_flow_error *error);
  47 static int
  48 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  49                                   const struct rte_flow_item *pattern,
  50                                   struct rte_flow_error *error,
  51                                   struct rte_eth_ethertype_filter *filter);
  52 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  53                                     const struct rte_flow_action *actions,
  54                                     struct rte_flow_error *error,
  55                                     struct rte_eth_ethertype_filter *filter);
  56 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  57                                         const struct rte_flow_item *pattern,
  58                                         struct rte_flow_error *error,
  59                                         struct i40e_fdir_filter_conf *filter);
  60 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  61                                        const struct rte_flow_action *actions,
  62                                        struct rte_flow_error *error,
  63                                        struct i40e_fdir_filter_conf *filter);
  64 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  65                                  const struct rte_flow_action *actions,
  66                                  struct rte_flow_error *error,
  67                                  struct i40e_tunnel_filter_conf *filter);
  68 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  69                                 struct rte_flow_error *error);
  70 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  71                                     const struct rte_flow_attr *attr,
  72                                     const struct rte_flow_item pattern[],
  73                                     const struct rte_flow_action actions[],
  74                                     struct rte_flow_error *error,
  75                                     union i40e_filter_t *filter);
  76 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  77                                        const struct rte_flow_attr *attr,
  78                                        const struct rte_flow_item pattern[],
  79                                        const struct rte_flow_action actions[],
  80                                        struct rte_flow_error *error,
  81                                        union i40e_filter_t *filter);
  82 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  83                                         const struct rte_flow_attr *attr,
  84                                         const struct rte_flow_item pattern[],
  85                                         const struct rte_flow_action actions[],
  86                                         struct rte_flow_error *error,
  87                                         union i40e_filter_t *filter);
  88 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  89                                         const struct rte_flow_attr *attr,
  90                                         const struct rte_flow_item pattern[],
  91                                         const struct rte_flow_action actions[],
  92                                         struct rte_flow_error *error,
  93                                         union i40e_filter_t *filter);
  94 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  95                                        const struct rte_flow_attr *attr,
  96                                        const struct rte_flow_item pattern[],
  97                                        const struct rte_flow_action actions[],
  98                                        struct rte_flow_error *error,
  99                                        union i40e_filter_t *filter);
 100 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 101                                       const struct rte_flow_attr *attr,
 102                                       const struct rte_flow_item pattern[],
 103                                       const struct rte_flow_action actions[],
 104                                       struct rte_flow_error *error,
 105                                       union i40e_filter_t *filter);
 106 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 107                                       struct i40e_ethertype_filter *filter);
 108 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 109                                            struct i40e_tunnel_filter *filter);
 110 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 112 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 113 static int
 114 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 115 static int
 116 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 117                               const struct rte_flow_attr *attr,
 118                               const struct rte_flow_item pattern[],
 119                               const struct rte_flow_action actions[],
 120                               struct rte_flow_error *error,
 121                               union i40e_filter_t *filter);
 122 static int
 123 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 124                               const struct rte_flow_item *pattern,
 125                               struct rte_flow_error *error,
 126                               struct i40e_tunnel_filter_conf *filter);
 127
 128 const struct rte_flow_ops i40e_flow_ops = {
 129         .validate = i40e_flow_validate,
 130         .create = i40e_flow_create,
 131         .destroy = i40e_flow_destroy,
 132         .flush = i40e_flow_flush,
 133 };
 134
 135 union i40e_filter_t cons_filter;
 136 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 137
 138 /* Pattern matched ethertype filter */
 139 static enum rte_flow_item_type pattern_ethertype[] = {
 140         RTE_FLOW_ITEM_TYPE_ETH,
 141         RTE_FLOW_ITEM_TYPE_END,
 142 };
 143
 144 /* Pattern matched flow director filter */
 145 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 146         RTE_FLOW_ITEM_TYPE_ETH,
 147         RTE_FLOW_ITEM_TYPE_IPV4,
 148         RTE_FLOW_ITEM_TYPE_END,
 149 };
 150
 151 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 152         RTE_FLOW_ITEM_TYPE_ETH,
 153         RTE_FLOW_ITEM_TYPE_IPV4,
 154         RTE_FLOW_ITEM_TYPE_UDP,
 155         RTE_FLOW_ITEM_TYPE_END,
 156 };
 157
 158 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 159         RTE_FLOW_ITEM_TYPE_ETH,
 160         RTE_FLOW_ITEM_TYPE_IPV4,
 161         RTE_FLOW_ITEM_TYPE_TCP,
 162         RTE_FLOW_ITEM_TYPE_END,
 163 };
 164
 165 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 166         RTE_FLOW_ITEM_TYPE_ETH,
 167         RTE_FLOW_ITEM_TYPE_IPV4,
 168         RTE_FLOW_ITEM_TYPE_SCTP,
 169         RTE_FLOW_ITEM_TYPE_END,
 170 };
 171
 172 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 173         RTE_FLOW_ITEM_TYPE_ETH,
 174         RTE_FLOW_ITEM_TYPE_IPV4,
 175         RTE_FLOW_ITEM_TYPE_UDP,
 176         RTE_FLOW_ITEM_TYPE_GTPC,
 177         RTE_FLOW_ITEM_TYPE_END,
 178 };
 179
 180 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 181         RTE_FLOW_ITEM_TYPE_ETH,
 182         RTE_FLOW_ITEM_TYPE_IPV4,
 183         RTE_FLOW_ITEM_TYPE_UDP,
 184         RTE_FLOW_ITEM_TYPE_GTPU,
 185         RTE_FLOW_ITEM_TYPE_END,
 186 };
 187
 188 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 189         RTE_FLOW_ITEM_TYPE_ETH,
 190         RTE_FLOW_ITEM_TYPE_IPV4,
 191         RTE_FLOW_ITEM_TYPE_UDP,
 192         RTE_FLOW_ITEM_TYPE_GTPU,
 193         RTE_FLOW_ITEM_TYPE_IPV4,
 194         RTE_FLOW_ITEM_TYPE_END,
 195 };
 196
 197 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 198         RTE_FLOW_ITEM_TYPE_ETH,
 199         RTE_FLOW_ITEM_TYPE_IPV4,
 200         RTE_FLOW_ITEM_TYPE_UDP,
 201         RTE_FLOW_ITEM_TYPE_GTPU,
 202         RTE_FLOW_ITEM_TYPE_IPV6,
 203         RTE_FLOW_ITEM_TYPE_END,
 204 };
 205
 206 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 207         RTE_FLOW_ITEM_TYPE_ETH,
 208         RTE_FLOW_ITEM_TYPE_IPV6,
 209         RTE_FLOW_ITEM_TYPE_END,
 210 };
 211
 212 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 213         RTE_FLOW_ITEM_TYPE_ETH,
 214         RTE_FLOW_ITEM_TYPE_IPV6,
 215         RTE_FLOW_ITEM_TYPE_UDP,
 216         RTE_FLOW_ITEM_TYPE_END,
 217 };
 218
 219 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 220         RTE_FLOW_ITEM_TYPE_ETH,
 221         RTE_FLOW_ITEM_TYPE_IPV6,
 222         RTE_FLOW_ITEM_TYPE_TCP,
 223         RTE_FLOW_ITEM_TYPE_END,
 224 };
 225
 226 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 227         RTE_FLOW_ITEM_TYPE_ETH,
 228         RTE_FLOW_ITEM_TYPE_IPV6,
 229         RTE_FLOW_ITEM_TYPE_SCTP,
 230         RTE_FLOW_ITEM_TYPE_END,
 231 };
 232
 233 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 234         RTE_FLOW_ITEM_TYPE_ETH,
 235         RTE_FLOW_ITEM_TYPE_IPV6,
 236         RTE_FLOW_ITEM_TYPE_UDP,
 237         RTE_FLOW_ITEM_TYPE_GTPC,
 238         RTE_FLOW_ITEM_TYPE_END,
 239 };
 240
 241 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 242         RTE_FLOW_ITEM_TYPE_ETH,
 243         RTE_FLOW_ITEM_TYPE_IPV6,
 244         RTE_FLOW_ITEM_TYPE_UDP,
 245         RTE_FLOW_ITEM_TYPE_GTPU,
 246         RTE_FLOW_ITEM_TYPE_END,
 247 };
 248
 249 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 250         RTE_FLOW_ITEM_TYPE_ETH,
 251         RTE_FLOW_ITEM_TYPE_IPV6,
 252         RTE_FLOW_ITEM_TYPE_UDP,
 253         RTE_FLOW_ITEM_TYPE_GTPU,
 254         RTE_FLOW_ITEM_TYPE_IPV4,
 255         RTE_FLOW_ITEM_TYPE_END,
 256 };
 257
 258 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 259         RTE_FLOW_ITEM_TYPE_ETH,
 260         RTE_FLOW_ITEM_TYPE_IPV6,
 261         RTE_FLOW_ITEM_TYPE_UDP,
 262         RTE_FLOW_ITEM_TYPE_GTPU,
 263         RTE_FLOW_ITEM_TYPE_IPV6,
 264         RTE_FLOW_ITEM_TYPE_END,
 265 };
 266
 267 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 268         RTE_FLOW_ITEM_TYPE_ETH,
 269         RTE_FLOW_ITEM_TYPE_RAW,
 270         RTE_FLOW_ITEM_TYPE_END,
 271 };
 272
 273 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 274         RTE_FLOW_ITEM_TYPE_ETH,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_RAW,
 277         RTE_FLOW_ITEM_TYPE_END,
 278 };
 279
 280 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 281         RTE_FLOW_ITEM_TYPE_ETH,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_RAW,
 285         RTE_FLOW_ITEM_TYPE_END,
 286 };
 287
 288 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 289         RTE_FLOW_ITEM_TYPE_ETH,
 290         RTE_FLOW_ITEM_TYPE_IPV4,
 291         RTE_FLOW_ITEM_TYPE_RAW,
 292         RTE_FLOW_ITEM_TYPE_END,
 293 };
 294
 295 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 296         RTE_FLOW_ITEM_TYPE_ETH,
 297         RTE_FLOW_ITEM_TYPE_IPV4,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_RAW,
 300         RTE_FLOW_ITEM_TYPE_END,
 301 };
 302
 303 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 304         RTE_FLOW_ITEM_TYPE_ETH,
 305         RTE_FLOW_ITEM_TYPE_IPV4,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_RAW,
 309         RTE_FLOW_ITEM_TYPE_END,
 310 };
 311
 312 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 313         RTE_FLOW_ITEM_TYPE_ETH,
 314         RTE_FLOW_ITEM_TYPE_IPV4,
 315         RTE_FLOW_ITEM_TYPE_UDP,
 316         RTE_FLOW_ITEM_TYPE_RAW,
 317         RTE_FLOW_ITEM_TYPE_END,
 318 };
 319
 320 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 321         RTE_FLOW_ITEM_TYPE_ETH,
 322         RTE_FLOW_ITEM_TYPE_IPV4,
 323         RTE_FLOW_ITEM_TYPE_UDP,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_RAW,
 326         RTE_FLOW_ITEM_TYPE_END,
 327 };
 328
 329 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 330         RTE_FLOW_ITEM_TYPE_ETH,
 331         RTE_FLOW_ITEM_TYPE_IPV4,
 332         RTE_FLOW_ITEM_TYPE_UDP,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_RAW,
 336         RTE_FLOW_ITEM_TYPE_END,
 337 };
 338
 339 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 340         RTE_FLOW_ITEM_TYPE_ETH,
 341         RTE_FLOW_ITEM_TYPE_IPV4,
 342         RTE_FLOW_ITEM_TYPE_TCP,
 343         RTE_FLOW_ITEM_TYPE_RAW,
 344         RTE_FLOW_ITEM_TYPE_END,
 345 };
 346
 347 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 348         RTE_FLOW_ITEM_TYPE_ETH,
 349         RTE_FLOW_ITEM_TYPE_IPV4,
 350         RTE_FLOW_ITEM_TYPE_TCP,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_RAW,
 353         RTE_FLOW_ITEM_TYPE_END,
 354 };
 355
 356 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 357         RTE_FLOW_ITEM_TYPE_ETH,
 358         RTE_FLOW_ITEM_TYPE_IPV4,
 359         RTE_FLOW_ITEM_TYPE_TCP,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_RAW,
 363         RTE_FLOW_ITEM_TYPE_END,
 364 };
 365
 366 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 367         RTE_FLOW_ITEM_TYPE_ETH,
 368         RTE_FLOW_ITEM_TYPE_IPV4,
 369         RTE_FLOW_ITEM_TYPE_SCTP,
 370         RTE_FLOW_ITEM_TYPE_RAW,
 371         RTE_FLOW_ITEM_TYPE_END,
 372 };
 373
 374 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 375         RTE_FLOW_ITEM_TYPE_ETH,
 376         RTE_FLOW_ITEM_TYPE_IPV4,
 377         RTE_FLOW_ITEM_TYPE_SCTP,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_RAW,
 380         RTE_FLOW_ITEM_TYPE_END,
 381 };
 382
 383 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 384         RTE_FLOW_ITEM_TYPE_ETH,
 385         RTE_FLOW_ITEM_TYPE_IPV4,
 386         RTE_FLOW_ITEM_TYPE_SCTP,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_RAW,
 390         RTE_FLOW_ITEM_TYPE_END,
 391 };
 392
 393 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 394         RTE_FLOW_ITEM_TYPE_ETH,
 395         RTE_FLOW_ITEM_TYPE_IPV6,
 396         RTE_FLOW_ITEM_TYPE_RAW,
 397         RTE_FLOW_ITEM_TYPE_END,
 398 };
 399
 400 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 401         RTE_FLOW_ITEM_TYPE_ETH,
 402         RTE_FLOW_ITEM_TYPE_IPV6,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_RAW,
 405         RTE_FLOW_ITEM_TYPE_END,
 406 };
 407
 408 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 409         RTE_FLOW_ITEM_TYPE_ETH,
 410         RTE_FLOW_ITEM_TYPE_IPV6,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_RAW,
 414         RTE_FLOW_ITEM_TYPE_END,
 415 };
 416
 417 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 418         RTE_FLOW_ITEM_TYPE_ETH,
 419         RTE_FLOW_ITEM_TYPE_IPV6,
 420         RTE_FLOW_ITEM_TYPE_UDP,
 421         RTE_FLOW_ITEM_TYPE_RAW,
 422         RTE_FLOW_ITEM_TYPE_END,
 423 };
 424
 425 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 426         RTE_FLOW_ITEM_TYPE_ETH,
 427         RTE_FLOW_ITEM_TYPE_IPV6,
 428         RTE_FLOW_ITEM_TYPE_UDP,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_RAW,
 431         RTE_FLOW_ITEM_TYPE_END,
 432 };
 433
 434 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 435         RTE_FLOW_ITEM_TYPE_ETH,
 436         RTE_FLOW_ITEM_TYPE_IPV6,
 437         RTE_FLOW_ITEM_TYPE_UDP,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_RAW,
 441         RTE_FLOW_ITEM_TYPE_END,
 442 };
 443
 444 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 445         RTE_FLOW_ITEM_TYPE_ETH,
 446         RTE_FLOW_ITEM_TYPE_IPV6,
 447         RTE_FLOW_ITEM_TYPE_TCP,
 448         RTE_FLOW_ITEM_TYPE_RAW,
 449         RTE_FLOW_ITEM_TYPE_END,
 450 };
 451
 452 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 453         RTE_FLOW_ITEM_TYPE_ETH,
 454         RTE_FLOW_ITEM_TYPE_IPV6,
 455         RTE_FLOW_ITEM_TYPE_TCP,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_RAW,
 458         RTE_FLOW_ITEM_TYPE_END,
 459 };
 460
 461 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 462         RTE_FLOW_ITEM_TYPE_ETH,
 463         RTE_FLOW_ITEM_TYPE_IPV6,
 464         RTE_FLOW_ITEM_TYPE_TCP,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_RAW,
 468         RTE_FLOW_ITEM_TYPE_END,
 469 };
 470
 471 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 472         RTE_FLOW_ITEM_TYPE_ETH,
 473         RTE_FLOW_ITEM_TYPE_IPV6,
 474         RTE_FLOW_ITEM_TYPE_SCTP,
 475         RTE_FLOW_ITEM_TYPE_RAW,
 476         RTE_FLOW_ITEM_TYPE_END,
 477 };
 478
 479 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 480         RTE_FLOW_ITEM_TYPE_ETH,
 481         RTE_FLOW_ITEM_TYPE_IPV6,
 482         RTE_FLOW_ITEM_TYPE_SCTP,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_RAW,
 485         RTE_FLOW_ITEM_TYPE_END,
 486 };
 487
 488 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 489         RTE_FLOW_ITEM_TYPE_ETH,
 490         RTE_FLOW_ITEM_TYPE_IPV6,
 491         RTE_FLOW_ITEM_TYPE_SCTP,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_RAW,
 495         RTE_FLOW_ITEM_TYPE_END,
 496 };
 497
 498 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 499         RTE_FLOW_ITEM_TYPE_ETH,
 500         RTE_FLOW_ITEM_TYPE_VLAN,
 501         RTE_FLOW_ITEM_TYPE_END,
 502 };
 503
 504 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 505         RTE_FLOW_ITEM_TYPE_ETH,
 506         RTE_FLOW_ITEM_TYPE_VLAN,
 507         RTE_FLOW_ITEM_TYPE_IPV4,
 508         RTE_FLOW_ITEM_TYPE_END,
 509 };
 510
 511 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 512         RTE_FLOW_ITEM_TYPE_ETH,
 513         RTE_FLOW_ITEM_TYPE_VLAN,
 514         RTE_FLOW_ITEM_TYPE_IPV4,
 515         RTE_FLOW_ITEM_TYPE_UDP,
 516         RTE_FLOW_ITEM_TYPE_END,
 517 };
 518
 519 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 520         RTE_FLOW_ITEM_TYPE_ETH,
 521         RTE_FLOW_ITEM_TYPE_VLAN,
 522         RTE_FLOW_ITEM_TYPE_IPV4,
 523         RTE_FLOW_ITEM_TYPE_TCP,
 524         RTE_FLOW_ITEM_TYPE_END,
 525 };
 526
 527 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 528         RTE_FLOW_ITEM_TYPE_ETH,
 529         RTE_FLOW_ITEM_TYPE_VLAN,
 530         RTE_FLOW_ITEM_TYPE_IPV4,
 531         RTE_FLOW_ITEM_TYPE_SCTP,
 532         RTE_FLOW_ITEM_TYPE_END,
 533 };
 534
 535 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 536         RTE_FLOW_ITEM_TYPE_ETH,
 537         RTE_FLOW_ITEM_TYPE_VLAN,
 538         RTE_FLOW_ITEM_TYPE_IPV6,
 539         RTE_FLOW_ITEM_TYPE_END,
 540 };
 541
 542 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 543         RTE_FLOW_ITEM_TYPE_ETH,
 544         RTE_FLOW_ITEM_TYPE_VLAN,
 545         RTE_FLOW_ITEM_TYPE_IPV6,
 546         RTE_FLOW_ITEM_TYPE_UDP,
 547         RTE_FLOW_ITEM_TYPE_END,
 548 };
 549
 550 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 551         RTE_FLOW_ITEM_TYPE_ETH,
 552         RTE_FLOW_ITEM_TYPE_VLAN,
 553         RTE_FLOW_ITEM_TYPE_IPV6,
 554         RTE_FLOW_ITEM_TYPE_TCP,
 555         RTE_FLOW_ITEM_TYPE_END,
 556 };
 557
 558 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 559         RTE_FLOW_ITEM_TYPE_ETH,
 560         RTE_FLOW_ITEM_TYPE_VLAN,
 561         RTE_FLOW_ITEM_TYPE_IPV6,
 562         RTE_FLOW_ITEM_TYPE_SCTP,
 563         RTE_FLOW_ITEM_TYPE_END,
 564 };
 565
 566 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 567         RTE_FLOW_ITEM_TYPE_ETH,
 568         RTE_FLOW_ITEM_TYPE_VLAN,
 569         RTE_FLOW_ITEM_TYPE_RAW,
 570         RTE_FLOW_ITEM_TYPE_END,
 571 };
 572
 573 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 574         RTE_FLOW_ITEM_TYPE_ETH,
 575         RTE_FLOW_ITEM_TYPE_VLAN,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_RAW,
 578         RTE_FLOW_ITEM_TYPE_END,
 579 };
 580
 581 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 582         RTE_FLOW_ITEM_TYPE_ETH,
 583         RTE_FLOW_ITEM_TYPE_VLAN,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_RAW,
 587         RTE_FLOW_ITEM_TYPE_END,
 588 };
 589
 590 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 591         RTE_FLOW_ITEM_TYPE_ETH,
 592         RTE_FLOW_ITEM_TYPE_VLAN,
 593         RTE_FLOW_ITEM_TYPE_IPV4,
 594         RTE_FLOW_ITEM_TYPE_RAW,
 595         RTE_FLOW_ITEM_TYPE_END,
 596 };
 597
 598 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 599         RTE_FLOW_ITEM_TYPE_ETH,
 600         RTE_FLOW_ITEM_TYPE_VLAN,
 601         RTE_FLOW_ITEM_TYPE_IPV4,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_RAW,
 604         RTE_FLOW_ITEM_TYPE_END,
 605 };
 606
 607 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 608         RTE_FLOW_ITEM_TYPE_ETH,
 609         RTE_FLOW_ITEM_TYPE_VLAN,
 610         RTE_FLOW_ITEM_TYPE_IPV4,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_RAW,
 614         RTE_FLOW_ITEM_TYPE_END,
 615 };
 616
 617 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 618         RTE_FLOW_ITEM_TYPE_ETH,
 619         RTE_FLOW_ITEM_TYPE_VLAN,
 620         RTE_FLOW_ITEM_TYPE_IPV4,
 621         RTE_FLOW_ITEM_TYPE_UDP,
 622         RTE_FLOW_ITEM_TYPE_RAW,
 623         RTE_FLOW_ITEM_TYPE_END,
 624 };
 625
 626 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 627         RTE_FLOW_ITEM_TYPE_ETH,
 628         RTE_FLOW_ITEM_TYPE_VLAN,
 629         RTE_FLOW_ITEM_TYPE_IPV4,
 630         RTE_FLOW_ITEM_TYPE_UDP,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_RAW,
 633         RTE_FLOW_ITEM_TYPE_END,
 634 };
 635
 636 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 637         RTE_FLOW_ITEM_TYPE_ETH,
 638         RTE_FLOW_ITEM_TYPE_VLAN,
 639         RTE_FLOW_ITEM_TYPE_IPV4,
 640         RTE_FLOW_ITEM_TYPE_UDP,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_RAW,
 644         RTE_FLOW_ITEM_TYPE_END,
 645 };
 646
 647 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 648         RTE_FLOW_ITEM_TYPE_ETH,
 649         RTE_FLOW_ITEM_TYPE_VLAN,
 650         RTE_FLOW_ITEM_TYPE_IPV4,
 651         RTE_FLOW_ITEM_TYPE_TCP,
 652         RTE_FLOW_ITEM_TYPE_RAW,
 653         RTE_FLOW_ITEM_TYPE_END,
 654 };
 655
 656 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 657         RTE_FLOW_ITEM_TYPE_ETH,
 658         RTE_FLOW_ITEM_TYPE_VLAN,
 659         RTE_FLOW_ITEM_TYPE_IPV4,
 660         RTE_FLOW_ITEM_TYPE_TCP,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_RAW,
 663         RTE_FLOW_ITEM_TYPE_END,
 664 };
 665
 666 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 667         RTE_FLOW_ITEM_TYPE_ETH,
 668         RTE_FLOW_ITEM_TYPE_VLAN,
 669         RTE_FLOW_ITEM_TYPE_IPV4,
 670         RTE_FLOW_ITEM_TYPE_TCP,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_RAW,
 674         RTE_FLOW_ITEM_TYPE_END,
 675 };
 676
 677 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 678         RTE_FLOW_ITEM_TYPE_ETH,
 679         RTE_FLOW_ITEM_TYPE_VLAN,
 680         RTE_FLOW_ITEM_TYPE_IPV4,
 681         RTE_FLOW_ITEM_TYPE_SCTP,
 682         RTE_FLOW_ITEM_TYPE_RAW,
 683         RTE_FLOW_ITEM_TYPE_END,
 684 };
 685
 686 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 687         RTE_FLOW_ITEM_TYPE_ETH,
 688         RTE_FLOW_ITEM_TYPE_VLAN,
 689         RTE_FLOW_ITEM_TYPE_IPV4,
 690         RTE_FLOW_ITEM_TYPE_SCTP,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_RAW,
 693         RTE_FLOW_ITEM_TYPE_END,
 694 };
 695
 696 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 697         RTE_FLOW_ITEM_TYPE_ETH,
 698         RTE_FLOW_ITEM_TYPE_VLAN,
 699         RTE_FLOW_ITEM_TYPE_IPV4,
 700         RTE_FLOW_ITEM_TYPE_SCTP,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_RAW,
 704         RTE_FLOW_ITEM_TYPE_END,
 705 };
 706
 707 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 708         RTE_FLOW_ITEM_TYPE_ETH,
 709         RTE_FLOW_ITEM_TYPE_VLAN,
 710         RTE_FLOW_ITEM_TYPE_IPV6,
 711         RTE_FLOW_ITEM_TYPE_RAW,
 712         RTE_FLOW_ITEM_TYPE_END,
 713 };
 714
 715 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 716         RTE_FLOW_ITEM_TYPE_ETH,
 717         RTE_FLOW_ITEM_TYPE_VLAN,
 718         RTE_FLOW_ITEM_TYPE_IPV6,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_RAW,
 721         RTE_FLOW_ITEM_TYPE_END,
 722 };
 723
 724 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 725         RTE_FLOW_ITEM_TYPE_ETH,
 726         RTE_FLOW_ITEM_TYPE_VLAN,
 727         RTE_FLOW_ITEM_TYPE_IPV6,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_RAW,
 731         RTE_FLOW_ITEM_TYPE_END,
 732 };
 733
 734 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 735         RTE_FLOW_ITEM_TYPE_ETH,
 736         RTE_FLOW_ITEM_TYPE_VLAN,
 737         RTE_FLOW_ITEM_TYPE_IPV6,
 738         RTE_FLOW_ITEM_TYPE_UDP,
 739         RTE_FLOW_ITEM_TYPE_RAW,
 740         RTE_FLOW_ITEM_TYPE_END,
 741 };
 742
 743 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 744         RTE_FLOW_ITEM_TYPE_ETH,
 745         RTE_FLOW_ITEM_TYPE_VLAN,
 746         RTE_FLOW_ITEM_TYPE_IPV6,
 747         RTE_FLOW_ITEM_TYPE_UDP,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_RAW,
 750         RTE_FLOW_ITEM_TYPE_END,
 751 };
 752
 753 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 754         RTE_FLOW_ITEM_TYPE_ETH,
 755         RTE_FLOW_ITEM_TYPE_VLAN,
 756         RTE_FLOW_ITEM_TYPE_IPV6,
 757         RTE_FLOW_ITEM_TYPE_UDP,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_RAW,
 761         RTE_FLOW_ITEM_TYPE_END,
 762 };
 763
 764 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 765         RTE_FLOW_ITEM_TYPE_ETH,
 766         RTE_FLOW_ITEM_TYPE_VLAN,
 767         RTE_FLOW_ITEM_TYPE_IPV6,
 768         RTE_FLOW_ITEM_TYPE_TCP,
 769         RTE_FLOW_ITEM_TYPE_RAW,
 770         RTE_FLOW_ITEM_TYPE_END,
 771 };
 772
 773 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 774         RTE_FLOW_ITEM_TYPE_ETH,
 775         RTE_FLOW_ITEM_TYPE_VLAN,
 776         RTE_FLOW_ITEM_TYPE_IPV6,
 777         RTE_FLOW_ITEM_TYPE_TCP,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_RAW,
 780         RTE_FLOW_ITEM_TYPE_END,
 781 };
 782
 783 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 784         RTE_FLOW_ITEM_TYPE_ETH,
 785         RTE_FLOW_ITEM_TYPE_VLAN,
 786         RTE_FLOW_ITEM_TYPE_IPV6,
 787         RTE_FLOW_ITEM_TYPE_TCP,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_RAW,
 791         RTE_FLOW_ITEM_TYPE_END,
 792 };
 793
 794 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 795         RTE_FLOW_ITEM_TYPE_ETH,
 796         RTE_FLOW_ITEM_TYPE_VLAN,
 797         RTE_FLOW_ITEM_TYPE_IPV6,
 798         RTE_FLOW_ITEM_TYPE_SCTP,
 799         RTE_FLOW_ITEM_TYPE_RAW,
 800         RTE_FLOW_ITEM_TYPE_END,
 801 };
 802
 803 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 804         RTE_FLOW_ITEM_TYPE_ETH,
 805         RTE_FLOW_ITEM_TYPE_VLAN,
 806         RTE_FLOW_ITEM_TYPE_IPV6,
 807         RTE_FLOW_ITEM_TYPE_SCTP,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_RAW,
 810         RTE_FLOW_ITEM_TYPE_END,
 811 };
 812
 813 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 814         RTE_FLOW_ITEM_TYPE_ETH,
 815         RTE_FLOW_ITEM_TYPE_VLAN,
 816         RTE_FLOW_ITEM_TYPE_IPV6,
 817         RTE_FLOW_ITEM_TYPE_SCTP,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_RAW,
 821         RTE_FLOW_ITEM_TYPE_END,
 822 };
 823
 824 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 825         RTE_FLOW_ITEM_TYPE_ETH,
 826         RTE_FLOW_ITEM_TYPE_IPV4,
 827         RTE_FLOW_ITEM_TYPE_VF,
 828         RTE_FLOW_ITEM_TYPE_END,
 829 };
 830
 831 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 832         RTE_FLOW_ITEM_TYPE_ETH,
 833         RTE_FLOW_ITEM_TYPE_IPV4,
 834         RTE_FLOW_ITEM_TYPE_UDP,
 835         RTE_FLOW_ITEM_TYPE_VF,
 836         RTE_FLOW_ITEM_TYPE_END,
 837 };
 838
 839 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 840         RTE_FLOW_ITEM_TYPE_ETH,
 841         RTE_FLOW_ITEM_TYPE_IPV4,
 842         RTE_FLOW_ITEM_TYPE_TCP,
 843         RTE_FLOW_ITEM_TYPE_VF,
 844         RTE_FLOW_ITEM_TYPE_END,
 845 };
 846
 847 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 848         RTE_FLOW_ITEM_TYPE_ETH,
 849         RTE_FLOW_ITEM_TYPE_IPV4,
 850         RTE_FLOW_ITEM_TYPE_SCTP,
 851         RTE_FLOW_ITEM_TYPE_VF,
 852         RTE_FLOW_ITEM_TYPE_END,
 853 };
 854
 855 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 856         RTE_FLOW_ITEM_TYPE_ETH,
 857         RTE_FLOW_ITEM_TYPE_IPV6,
 858         RTE_FLOW_ITEM_TYPE_VF,
 859         RTE_FLOW_ITEM_TYPE_END,
 860 };
 861
 862 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 863         RTE_FLOW_ITEM_TYPE_ETH,
 864         RTE_FLOW_ITEM_TYPE_IPV6,
 865         RTE_FLOW_ITEM_TYPE_UDP,
 866         RTE_FLOW_ITEM_TYPE_VF,
 867         RTE_FLOW_ITEM_TYPE_END,
 868 };
 869
 870 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 871         RTE_FLOW_ITEM_TYPE_ETH,
 872         RTE_FLOW_ITEM_TYPE_IPV6,
 873         RTE_FLOW_ITEM_TYPE_TCP,
 874         RTE_FLOW_ITEM_TYPE_VF,
 875         RTE_FLOW_ITEM_TYPE_END,
 876 };
 877
 878 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 879         RTE_FLOW_ITEM_TYPE_ETH,
 880         RTE_FLOW_ITEM_TYPE_IPV6,
 881         RTE_FLOW_ITEM_TYPE_SCTP,
 882         RTE_FLOW_ITEM_TYPE_VF,
 883         RTE_FLOW_ITEM_TYPE_END,
 884 };
 885
 886 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 887         RTE_FLOW_ITEM_TYPE_ETH,
 888         RTE_FLOW_ITEM_TYPE_RAW,
 889         RTE_FLOW_ITEM_TYPE_VF,
 890         RTE_FLOW_ITEM_TYPE_END,
 891 };
 892
 893 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 894         RTE_FLOW_ITEM_TYPE_ETH,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_RAW,
 897         RTE_FLOW_ITEM_TYPE_VF,
 898         RTE_FLOW_ITEM_TYPE_END,
 899 };
 900
 901 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 902         RTE_FLOW_ITEM_TYPE_ETH,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_RAW,
 906         RTE_FLOW_ITEM_TYPE_VF,
 907         RTE_FLOW_ITEM_TYPE_END,
 908 };
 909
 910 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 911         RTE_FLOW_ITEM_TYPE_ETH,
 912         RTE_FLOW_ITEM_TYPE_IPV4,
 913         RTE_FLOW_ITEM_TYPE_RAW,
 914         RTE_FLOW_ITEM_TYPE_VF,
 915         RTE_FLOW_ITEM_TYPE_END,
 916 };
 917
 918 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 919         RTE_FLOW_ITEM_TYPE_ETH,
 920         RTE_FLOW_ITEM_TYPE_IPV4,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_RAW,
 923         RTE_FLOW_ITEM_TYPE_VF,
 924         RTE_FLOW_ITEM_TYPE_END,
 925 };
 926
 927 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 928         RTE_FLOW_ITEM_TYPE_ETH,
 929         RTE_FLOW_ITEM_TYPE_IPV4,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_RAW,
 933         RTE_FLOW_ITEM_TYPE_VF,
 934         RTE_FLOW_ITEM_TYPE_END,
 935 };
 936
 937 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 938         RTE_FLOW_ITEM_TYPE_ETH,
 939         RTE_FLOW_ITEM_TYPE_IPV4,
 940         RTE_FLOW_ITEM_TYPE_UDP,
 941         RTE_FLOW_ITEM_TYPE_RAW,
 942         RTE_FLOW_ITEM_TYPE_VF,
 943         RTE_FLOW_ITEM_TYPE_END,
 944 };
 945
 946 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 947         RTE_FLOW_ITEM_TYPE_ETH,
 948         RTE_FLOW_ITEM_TYPE_IPV4,
 949         RTE_FLOW_ITEM_TYPE_UDP,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_RAW,
 952         RTE_FLOW_ITEM_TYPE_VF,
 953         RTE_FLOW_ITEM_TYPE_END,
 954 };
 955
 956 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 957         RTE_FLOW_ITEM_TYPE_ETH,
 958         RTE_FLOW_ITEM_TYPE_IPV4,
 959         RTE_FLOW_ITEM_TYPE_UDP,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_RAW,
 963         RTE_FLOW_ITEM_TYPE_VF,
 964         RTE_FLOW_ITEM_TYPE_END,
 965 };
 966
 967 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 968         RTE_FLOW_ITEM_TYPE_ETH,
 969         RTE_FLOW_ITEM_TYPE_IPV4,
 970         RTE_FLOW_ITEM_TYPE_TCP,
 971         RTE_FLOW_ITEM_TYPE_RAW,
 972         RTE_FLOW_ITEM_TYPE_VF,
 973         RTE_FLOW_ITEM_TYPE_END,
 974 };
 975
 976 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 977         RTE_FLOW_ITEM_TYPE_ETH,
 978         RTE_FLOW_ITEM_TYPE_IPV4,
 979         RTE_FLOW_ITEM_TYPE_TCP,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_RAW,
 982         RTE_FLOW_ITEM_TYPE_VF,
 983         RTE_FLOW_ITEM_TYPE_END,
 984 };
 985
 986 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 987         RTE_FLOW_ITEM_TYPE_ETH,
 988         RTE_FLOW_ITEM_TYPE_IPV4,
 989         RTE_FLOW_ITEM_TYPE_TCP,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_RAW,
 993         RTE_FLOW_ITEM_TYPE_VF,
 994         RTE_FLOW_ITEM_TYPE_END,
 995 };
 996
 997 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 998         RTE_FLOW_ITEM_TYPE_ETH,
 999         RTE_FLOW_ITEM_TYPE_IPV4,
1000         RTE_FLOW_ITEM_TYPE_SCTP,
1001         RTE_FLOW_ITEM_TYPE_RAW,
1002         RTE_FLOW_ITEM_TYPE_VF,
1003         RTE_FLOW_ITEM_TYPE_END,
1004 };
1005
1006 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1007         RTE_FLOW_ITEM_TYPE_ETH,
1008         RTE_FLOW_ITEM_TYPE_IPV4,
1009         RTE_FLOW_ITEM_TYPE_SCTP,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_RAW,
1012         RTE_FLOW_ITEM_TYPE_VF,
1013         RTE_FLOW_ITEM_TYPE_END,
1014 };
1015
1016 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1017         RTE_FLOW_ITEM_TYPE_ETH,
1018         RTE_FLOW_ITEM_TYPE_IPV4,
1019         RTE_FLOW_ITEM_TYPE_SCTP,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_RAW,
1023         RTE_FLOW_ITEM_TYPE_VF,
1024         RTE_FLOW_ITEM_TYPE_END,
1025 };
1026
1027 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1028         RTE_FLOW_ITEM_TYPE_ETH,
1029         RTE_FLOW_ITEM_TYPE_IPV6,
1030         RTE_FLOW_ITEM_TYPE_RAW,
1031         RTE_FLOW_ITEM_TYPE_VF,
1032         RTE_FLOW_ITEM_TYPE_END,
1033 };
1034
1035 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1036         RTE_FLOW_ITEM_TYPE_ETH,
1037         RTE_FLOW_ITEM_TYPE_IPV6,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_RAW,
1040         RTE_FLOW_ITEM_TYPE_VF,
1041         RTE_FLOW_ITEM_TYPE_END,
1042 };
1043
1044 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1045         RTE_FLOW_ITEM_TYPE_ETH,
1046         RTE_FLOW_ITEM_TYPE_IPV6,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_RAW,
1050         RTE_FLOW_ITEM_TYPE_VF,
1051         RTE_FLOW_ITEM_TYPE_END,
1052 };
1053
1054 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1055         RTE_FLOW_ITEM_TYPE_ETH,
1056         RTE_FLOW_ITEM_TYPE_IPV6,
1057         RTE_FLOW_ITEM_TYPE_UDP,
1058         RTE_FLOW_ITEM_TYPE_RAW,
1059         RTE_FLOW_ITEM_TYPE_VF,
1060         RTE_FLOW_ITEM_TYPE_END,
1061 };
1062
1063 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1064         RTE_FLOW_ITEM_TYPE_ETH,
1065         RTE_FLOW_ITEM_TYPE_IPV6,
1066         RTE_FLOW_ITEM_TYPE_UDP,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_RAW,
1069         RTE_FLOW_ITEM_TYPE_VF,
1070         RTE_FLOW_ITEM_TYPE_END,
1071 };
1072
1073 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1074         RTE_FLOW_ITEM_TYPE_ETH,
1075         RTE_FLOW_ITEM_TYPE_IPV6,
1076         RTE_FLOW_ITEM_TYPE_UDP,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_RAW,
1080         RTE_FLOW_ITEM_TYPE_VF,
1081         RTE_FLOW_ITEM_TYPE_END,
1082 };
1083
1084 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1085         RTE_FLOW_ITEM_TYPE_ETH,
1086         RTE_FLOW_ITEM_TYPE_IPV6,
1087         RTE_FLOW_ITEM_TYPE_TCP,
1088         RTE_FLOW_ITEM_TYPE_RAW,
1089         RTE_FLOW_ITEM_TYPE_VF,
1090         RTE_FLOW_ITEM_TYPE_END,
1091 };
1092
1093 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1094         RTE_FLOW_ITEM_TYPE_ETH,
1095         RTE_FLOW_ITEM_TYPE_IPV6,
1096         RTE_FLOW_ITEM_TYPE_TCP,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_RAW,
1099         RTE_FLOW_ITEM_TYPE_VF,
1100         RTE_FLOW_ITEM_TYPE_END,
1101 };
1102
1103 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1104         RTE_FLOW_ITEM_TYPE_ETH,
1105         RTE_FLOW_ITEM_TYPE_IPV6,
1106         RTE_FLOW_ITEM_TYPE_TCP,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_RAW,
1110         RTE_FLOW_ITEM_TYPE_VF,
1111         RTE_FLOW_ITEM_TYPE_END,
1112 };
1113
1114 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1115         RTE_FLOW_ITEM_TYPE_ETH,
1116         RTE_FLOW_ITEM_TYPE_IPV6,
1117         RTE_FLOW_ITEM_TYPE_SCTP,
1118         RTE_FLOW_ITEM_TYPE_RAW,
1119         RTE_FLOW_ITEM_TYPE_VF,
1120         RTE_FLOW_ITEM_TYPE_END,
1121 };
1122
1123 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1124         RTE_FLOW_ITEM_TYPE_ETH,
1125         RTE_FLOW_ITEM_TYPE_IPV6,
1126         RTE_FLOW_ITEM_TYPE_SCTP,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_RAW,
1129         RTE_FLOW_ITEM_TYPE_VF,
1130         RTE_FLOW_ITEM_TYPE_END,
1131 };
1132
1133 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1134         RTE_FLOW_ITEM_TYPE_ETH,
1135         RTE_FLOW_ITEM_TYPE_IPV6,
1136         RTE_FLOW_ITEM_TYPE_SCTP,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_RAW,
1140         RTE_FLOW_ITEM_TYPE_VF,
1141         RTE_FLOW_ITEM_TYPE_END,
1142 };
1143
1144 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1145         RTE_FLOW_ITEM_TYPE_ETH,
1146         RTE_FLOW_ITEM_TYPE_VLAN,
1147         RTE_FLOW_ITEM_TYPE_VF,
1148         RTE_FLOW_ITEM_TYPE_END,
1149 };
1150
1151 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1152         RTE_FLOW_ITEM_TYPE_ETH,
1153         RTE_FLOW_ITEM_TYPE_VLAN,
1154         RTE_FLOW_ITEM_TYPE_IPV4,
1155         RTE_FLOW_ITEM_TYPE_VF,
1156         RTE_FLOW_ITEM_TYPE_END,
1157 };
1158
1159 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1160         RTE_FLOW_ITEM_TYPE_ETH,
1161         RTE_FLOW_ITEM_TYPE_VLAN,
1162         RTE_FLOW_ITEM_TYPE_IPV4,
1163         RTE_FLOW_ITEM_TYPE_UDP,
1164         RTE_FLOW_ITEM_TYPE_VF,
1165         RTE_FLOW_ITEM_TYPE_END,
1166 };
1167
1168 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1169         RTE_FLOW_ITEM_TYPE_ETH,
1170         RTE_FLOW_ITEM_TYPE_VLAN,
1171         RTE_FLOW_ITEM_TYPE_IPV4,
1172         RTE_FLOW_ITEM_TYPE_TCP,
1173         RTE_FLOW_ITEM_TYPE_VF,
1174         RTE_FLOW_ITEM_TYPE_END,
1175 };
1176
1177 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1178         RTE_FLOW_ITEM_TYPE_ETH,
1179         RTE_FLOW_ITEM_TYPE_VLAN,
1180         RTE_FLOW_ITEM_TYPE_IPV4,
1181         RTE_FLOW_ITEM_TYPE_SCTP,
1182         RTE_FLOW_ITEM_TYPE_VF,
1183         RTE_FLOW_ITEM_TYPE_END,
1184 };
1185
1186 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1187         RTE_FLOW_ITEM_TYPE_ETH,
1188         RTE_FLOW_ITEM_TYPE_VLAN,
1189         RTE_FLOW_ITEM_TYPE_IPV6,
1190         RTE_FLOW_ITEM_TYPE_VF,
1191         RTE_FLOW_ITEM_TYPE_END,
1192 };
1193
1194 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1195         RTE_FLOW_ITEM_TYPE_ETH,
1196         RTE_FLOW_ITEM_TYPE_VLAN,
1197         RTE_FLOW_ITEM_TYPE_IPV6,
1198         RTE_FLOW_ITEM_TYPE_UDP,
1199         RTE_FLOW_ITEM_TYPE_VF,
1200         RTE_FLOW_ITEM_TYPE_END,
1201 };
1202
1203 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1204         RTE_FLOW_ITEM_TYPE_ETH,
1205         RTE_FLOW_ITEM_TYPE_VLAN,
1206         RTE_FLOW_ITEM_TYPE_IPV6,
1207         RTE_FLOW_ITEM_TYPE_TCP,
1208         RTE_FLOW_ITEM_TYPE_VF,
1209         RTE_FLOW_ITEM_TYPE_END,
1210 };
1211
1212 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1213         RTE_FLOW_ITEM_TYPE_ETH,
1214         RTE_FLOW_ITEM_TYPE_VLAN,
1215         RTE_FLOW_ITEM_TYPE_IPV6,
1216         RTE_FLOW_ITEM_TYPE_SCTP,
1217         RTE_FLOW_ITEM_TYPE_VF,
1218         RTE_FLOW_ITEM_TYPE_END,
1219 };
1220
1221 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1222         RTE_FLOW_ITEM_TYPE_ETH,
1223         RTE_FLOW_ITEM_TYPE_VLAN,
1224         RTE_FLOW_ITEM_TYPE_RAW,
1225         RTE_FLOW_ITEM_TYPE_VF,
1226         RTE_FLOW_ITEM_TYPE_END,
1227 };
1228
1229 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1230         RTE_FLOW_ITEM_TYPE_ETH,
1231         RTE_FLOW_ITEM_TYPE_VLAN,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_RAW,
1234         RTE_FLOW_ITEM_TYPE_VF,
1235         RTE_FLOW_ITEM_TYPE_END,
1236 };
1237
1238 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1239         RTE_FLOW_ITEM_TYPE_ETH,
1240         RTE_FLOW_ITEM_TYPE_VLAN,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_RAW,
1244         RTE_FLOW_ITEM_TYPE_VF,
1245         RTE_FLOW_ITEM_TYPE_END,
1246 };
1247
1248 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1249         RTE_FLOW_ITEM_TYPE_ETH,
1250         RTE_FLOW_ITEM_TYPE_VLAN,
1251         RTE_FLOW_ITEM_TYPE_IPV4,
1252         RTE_FLOW_ITEM_TYPE_RAW,
1253         RTE_FLOW_ITEM_TYPE_VF,
1254         RTE_FLOW_ITEM_TYPE_END,
1255 };
1256
1257 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1258         RTE_FLOW_ITEM_TYPE_ETH,
1259         RTE_FLOW_ITEM_TYPE_VLAN,
1260         RTE_FLOW_ITEM_TYPE_IPV4,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_RAW,
1263         RTE_FLOW_ITEM_TYPE_VF,
1264         RTE_FLOW_ITEM_TYPE_END,
1265 };
1266
1267 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1268         RTE_FLOW_ITEM_TYPE_ETH,
1269         RTE_FLOW_ITEM_TYPE_VLAN,
1270         RTE_FLOW_ITEM_TYPE_IPV4,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_RAW,
1274         RTE_FLOW_ITEM_TYPE_VF,
1275         RTE_FLOW_ITEM_TYPE_END,
1276 };
1277
1278 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1279         RTE_FLOW_ITEM_TYPE_ETH,
1280         RTE_FLOW_ITEM_TYPE_VLAN,
1281         RTE_FLOW_ITEM_TYPE_IPV4,
1282         RTE_FLOW_ITEM_TYPE_UDP,
1283         RTE_FLOW_ITEM_TYPE_RAW,
1284         RTE_FLOW_ITEM_TYPE_VF,
1285         RTE_FLOW_ITEM_TYPE_END,
1286 };
1287
1288 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1289         RTE_FLOW_ITEM_TYPE_ETH,
1290         RTE_FLOW_ITEM_TYPE_VLAN,
1291         RTE_FLOW_ITEM_TYPE_IPV4,
1292         RTE_FLOW_ITEM_TYPE_UDP,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_RAW,
1295         RTE_FLOW_ITEM_TYPE_VF,
1296         RTE_FLOW_ITEM_TYPE_END,
1297 };
1298
1299 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1300         RTE_FLOW_ITEM_TYPE_ETH,
1301         RTE_FLOW_ITEM_TYPE_VLAN,
1302         RTE_FLOW_ITEM_TYPE_IPV4,
1303         RTE_FLOW_ITEM_TYPE_UDP,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_RAW,
1307         RTE_FLOW_ITEM_TYPE_VF,
1308         RTE_FLOW_ITEM_TYPE_END,
1309 };
1310
1311 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1312         RTE_FLOW_ITEM_TYPE_ETH,
1313         RTE_FLOW_ITEM_TYPE_VLAN,
1314         RTE_FLOW_ITEM_TYPE_IPV4,
1315         RTE_FLOW_ITEM_TYPE_TCP,
1316         RTE_FLOW_ITEM_TYPE_RAW,
1317         RTE_FLOW_ITEM_TYPE_VF,
1318         RTE_FLOW_ITEM_TYPE_END,
1319 };
1320
1321 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1322         RTE_FLOW_ITEM_TYPE_ETH,
1323         RTE_FLOW_ITEM_TYPE_VLAN,
1324         RTE_FLOW_ITEM_TYPE_IPV4,
1325         RTE_FLOW_ITEM_TYPE_TCP,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_RAW,
1328         RTE_FLOW_ITEM_TYPE_VF,
1329         RTE_FLOW_ITEM_TYPE_END,
1330 };
1331
1332 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1333         RTE_FLOW_ITEM_TYPE_ETH,
1334         RTE_FLOW_ITEM_TYPE_VLAN,
1335         RTE_FLOW_ITEM_TYPE_IPV4,
1336         RTE_FLOW_ITEM_TYPE_TCP,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_RAW,
1340         RTE_FLOW_ITEM_TYPE_VF,
1341         RTE_FLOW_ITEM_TYPE_END,
1342 };
1343
1344 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1345         RTE_FLOW_ITEM_TYPE_ETH,
1346         RTE_FLOW_ITEM_TYPE_VLAN,
1347         RTE_FLOW_ITEM_TYPE_IPV4,
1348         RTE_FLOW_ITEM_TYPE_SCTP,
1349         RTE_FLOW_ITEM_TYPE_RAW,
1350         RTE_FLOW_ITEM_TYPE_VF,
1351         RTE_FLOW_ITEM_TYPE_END,
1352 };
1353
1354 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1355         RTE_FLOW_ITEM_TYPE_ETH,
1356         RTE_FLOW_ITEM_TYPE_VLAN,
1357         RTE_FLOW_ITEM_TYPE_IPV4,
1358         RTE_FLOW_ITEM_TYPE_SCTP,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_RAW,
1361         RTE_FLOW_ITEM_TYPE_VF,
1362         RTE_FLOW_ITEM_TYPE_END,
1363 };
1364
1365 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1366         RTE_FLOW_ITEM_TYPE_ETH,
1367         RTE_FLOW_ITEM_TYPE_VLAN,
1368         RTE_FLOW_ITEM_TYPE_IPV4,
1369         RTE_FLOW_ITEM_TYPE_SCTP,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_RAW,
1373         RTE_FLOW_ITEM_TYPE_VF,
1374         RTE_FLOW_ITEM_TYPE_END,
1375 };
1376
1377 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1378         RTE_FLOW_ITEM_TYPE_ETH,
1379         RTE_FLOW_ITEM_TYPE_VLAN,
1380         RTE_FLOW_ITEM_TYPE_IPV6,
1381         RTE_FLOW_ITEM_TYPE_RAW,
1382         RTE_FLOW_ITEM_TYPE_VF,
1383         RTE_FLOW_ITEM_TYPE_END,
1384 };
1385
1386 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1387         RTE_FLOW_ITEM_TYPE_ETH,
1388         RTE_FLOW_ITEM_TYPE_VLAN,
1389         RTE_FLOW_ITEM_TYPE_IPV6,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_RAW,
1392         RTE_FLOW_ITEM_TYPE_VF,
1393         RTE_FLOW_ITEM_TYPE_END,
1394 };
1395
1396 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1397         RTE_FLOW_ITEM_TYPE_ETH,
1398         RTE_FLOW_ITEM_TYPE_VLAN,
1399         RTE_FLOW_ITEM_TYPE_IPV6,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_RAW,
1403         RTE_FLOW_ITEM_TYPE_VF,
1404         RTE_FLOW_ITEM_TYPE_END,
1405 };
1406
1407 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1408         RTE_FLOW_ITEM_TYPE_ETH,
1409         RTE_FLOW_ITEM_TYPE_VLAN,
1410         RTE_FLOW_ITEM_TYPE_IPV6,
1411         RTE_FLOW_ITEM_TYPE_UDP,
1412         RTE_FLOW_ITEM_TYPE_RAW,
1413         RTE_FLOW_ITEM_TYPE_VF,
1414         RTE_FLOW_ITEM_TYPE_END,
1415 };
1416
1417 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1418         RTE_FLOW_ITEM_TYPE_ETH,
1419         RTE_FLOW_ITEM_TYPE_VLAN,
1420         RTE_FLOW_ITEM_TYPE_IPV6,
1421         RTE_FLOW_ITEM_TYPE_UDP,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_RAW,
1424         RTE_FLOW_ITEM_TYPE_VF,
1425         RTE_FLOW_ITEM_TYPE_END,
1426 };
1427
1428 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1429         RTE_FLOW_ITEM_TYPE_ETH,
1430         RTE_FLOW_ITEM_TYPE_VLAN,
1431         RTE_FLOW_ITEM_TYPE_IPV6,
1432         RTE_FLOW_ITEM_TYPE_UDP,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_RAW,
1436         RTE_FLOW_ITEM_TYPE_VF,
1437         RTE_FLOW_ITEM_TYPE_END,
1438 };
1439
1440 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1441         RTE_FLOW_ITEM_TYPE_ETH,
1442         RTE_FLOW_ITEM_TYPE_VLAN,
1443         RTE_FLOW_ITEM_TYPE_IPV6,
1444         RTE_FLOW_ITEM_TYPE_TCP,
1445         RTE_FLOW_ITEM_TYPE_RAW,
1446         RTE_FLOW_ITEM_TYPE_VF,
1447         RTE_FLOW_ITEM_TYPE_END,
1448 };
1449
1450 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1451         RTE_FLOW_ITEM_TYPE_ETH,
1452         RTE_FLOW_ITEM_TYPE_VLAN,
1453         RTE_FLOW_ITEM_TYPE_IPV6,
1454         RTE_FLOW_ITEM_TYPE_TCP,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_RAW,
1457         RTE_FLOW_ITEM_TYPE_VF,
1458         RTE_FLOW_ITEM_TYPE_END,
1459 };
1460
1461 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1462         RTE_FLOW_ITEM_TYPE_ETH,
1463         RTE_FLOW_ITEM_TYPE_VLAN,
1464         RTE_FLOW_ITEM_TYPE_IPV6,
1465         RTE_FLOW_ITEM_TYPE_TCP,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_RAW,
1469         RTE_FLOW_ITEM_TYPE_VF,
1470         RTE_FLOW_ITEM_TYPE_END,
1471 };
1472
1473 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1474         RTE_FLOW_ITEM_TYPE_ETH,
1475         RTE_FLOW_ITEM_TYPE_VLAN,
1476         RTE_FLOW_ITEM_TYPE_IPV6,
1477         RTE_FLOW_ITEM_TYPE_SCTP,
1478         RTE_FLOW_ITEM_TYPE_RAW,
1479         RTE_FLOW_ITEM_TYPE_VF,
1480         RTE_FLOW_ITEM_TYPE_END,
1481 };
1482
1483 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1484         RTE_FLOW_ITEM_TYPE_ETH,
1485         RTE_FLOW_ITEM_TYPE_VLAN,
1486         RTE_FLOW_ITEM_TYPE_IPV6,
1487         RTE_FLOW_ITEM_TYPE_SCTP,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_RAW,
1490         RTE_FLOW_ITEM_TYPE_VF,
1491         RTE_FLOW_ITEM_TYPE_END,
1492 };
1493
1494 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1495         RTE_FLOW_ITEM_TYPE_ETH,
1496         RTE_FLOW_ITEM_TYPE_VLAN,
1497         RTE_FLOW_ITEM_TYPE_IPV6,
1498         RTE_FLOW_ITEM_TYPE_SCTP,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_RAW,
1502         RTE_FLOW_ITEM_TYPE_VF,
1503         RTE_FLOW_ITEM_TYPE_END,
1504 };
1505
1506 /* Pattern matched tunnel filter */
1507 static enum rte_flow_item_type pattern_vxlan_1[] = {
1508         RTE_FLOW_ITEM_TYPE_ETH,
1509         RTE_FLOW_ITEM_TYPE_IPV4,
1510         RTE_FLOW_ITEM_TYPE_UDP,
1511         RTE_FLOW_ITEM_TYPE_VXLAN,
1512         RTE_FLOW_ITEM_TYPE_ETH,
1513         RTE_FLOW_ITEM_TYPE_END,
1514 };
1515
1516 static enum rte_flow_item_type pattern_vxlan_2[] = {
1517         RTE_FLOW_ITEM_TYPE_ETH,
1518         RTE_FLOW_ITEM_TYPE_IPV6,
1519         RTE_FLOW_ITEM_TYPE_UDP,
1520         RTE_FLOW_ITEM_TYPE_VXLAN,
1521         RTE_FLOW_ITEM_TYPE_ETH,
1522         RTE_FLOW_ITEM_TYPE_END,
1523 };
1524
1525 static enum rte_flow_item_type pattern_vxlan_3[] = {
1526         RTE_FLOW_ITEM_TYPE_ETH,
1527         RTE_FLOW_ITEM_TYPE_IPV4,
1528         RTE_FLOW_ITEM_TYPE_UDP,
1529         RTE_FLOW_ITEM_TYPE_VXLAN,
1530         RTE_FLOW_ITEM_TYPE_ETH,
1531         RTE_FLOW_ITEM_TYPE_VLAN,
1532         RTE_FLOW_ITEM_TYPE_END,
1533 };
1534
1535 static enum rte_flow_item_type pattern_vxlan_4[] = {
1536         RTE_FLOW_ITEM_TYPE_ETH,
1537         RTE_FLOW_ITEM_TYPE_IPV6,
1538         RTE_FLOW_ITEM_TYPE_UDP,
1539         RTE_FLOW_ITEM_TYPE_VXLAN,
1540         RTE_FLOW_ITEM_TYPE_ETH,
1541         RTE_FLOW_ITEM_TYPE_VLAN,
1542         RTE_FLOW_ITEM_TYPE_END,
1543 };
1544
1545 static enum rte_flow_item_type pattern_nvgre_1[] = {
1546         RTE_FLOW_ITEM_TYPE_ETH,
1547         RTE_FLOW_ITEM_TYPE_IPV4,
1548         RTE_FLOW_ITEM_TYPE_NVGRE,
1549         RTE_FLOW_ITEM_TYPE_ETH,
1550         RTE_FLOW_ITEM_TYPE_END,
1551 };
1552
1553 static enum rte_flow_item_type pattern_nvgre_2[] = {
1554         RTE_FLOW_ITEM_TYPE_ETH,
1555         RTE_FLOW_ITEM_TYPE_IPV6,
1556         RTE_FLOW_ITEM_TYPE_NVGRE,
1557         RTE_FLOW_ITEM_TYPE_ETH,
1558         RTE_FLOW_ITEM_TYPE_END,
1559 };
1560
1561 static enum rte_flow_item_type pattern_nvgre_3[] = {
1562         RTE_FLOW_ITEM_TYPE_ETH,
1563         RTE_FLOW_ITEM_TYPE_IPV4,
1564         RTE_FLOW_ITEM_TYPE_NVGRE,
1565         RTE_FLOW_ITEM_TYPE_ETH,
1566         RTE_FLOW_ITEM_TYPE_VLAN,
1567         RTE_FLOW_ITEM_TYPE_END,
1568 };
1569
1570 static enum rte_flow_item_type pattern_nvgre_4[] = {
1571         RTE_FLOW_ITEM_TYPE_ETH,
1572         RTE_FLOW_ITEM_TYPE_IPV6,
1573         RTE_FLOW_ITEM_TYPE_NVGRE,
1574         RTE_FLOW_ITEM_TYPE_ETH,
1575         RTE_FLOW_ITEM_TYPE_VLAN,
1576         RTE_FLOW_ITEM_TYPE_END,
1577 };
1578
1579 static enum rte_flow_item_type pattern_mpls_1[] = {
1580         RTE_FLOW_ITEM_TYPE_ETH,
1581         RTE_FLOW_ITEM_TYPE_IPV4,
1582         RTE_FLOW_ITEM_TYPE_UDP,
1583         RTE_FLOW_ITEM_TYPE_MPLS,
1584         RTE_FLOW_ITEM_TYPE_END,
1585 };
1586
1587 static enum rte_flow_item_type pattern_mpls_2[] = {
1588         RTE_FLOW_ITEM_TYPE_ETH,
1589         RTE_FLOW_ITEM_TYPE_IPV6,
1590         RTE_FLOW_ITEM_TYPE_UDP,
1591         RTE_FLOW_ITEM_TYPE_MPLS,
1592         RTE_FLOW_ITEM_TYPE_END,
1593 };
1594
1595 static enum rte_flow_item_type pattern_mpls_3[] = {
1596         RTE_FLOW_ITEM_TYPE_ETH,
1597         RTE_FLOW_ITEM_TYPE_IPV4,
1598         RTE_FLOW_ITEM_TYPE_GRE,
1599         RTE_FLOW_ITEM_TYPE_MPLS,
1600         RTE_FLOW_ITEM_TYPE_END,
1601 };
1602
1603 static enum rte_flow_item_type pattern_mpls_4[] = {
1604         RTE_FLOW_ITEM_TYPE_ETH,
1605         RTE_FLOW_ITEM_TYPE_IPV6,
1606         RTE_FLOW_ITEM_TYPE_GRE,
1607         RTE_FLOW_ITEM_TYPE_MPLS,
1608         RTE_FLOW_ITEM_TYPE_END,
1609 };
1610
1611 static enum rte_flow_item_type pattern_qinq_1[] = {
1612         RTE_FLOW_ITEM_TYPE_ETH,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_VLAN,
1615         RTE_FLOW_ITEM_TYPE_END,
1616 };
1617
1618 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1619         /* Ethertype */
1620         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1621         /* FDIR - support default flow type without flexible payload*/
1622         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1623         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1636         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1637         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1638         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1639         /* FDIR - support default flow type with flexible payload */
1640         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1641         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1665         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1666         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1667         /* FDIR - support single vlan input set */
1668         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1704         /* FDIR - support VF item */
1705         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1776         /* VXLAN */
1777         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1778         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1779         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1780         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1781         /* NVGRE */
1782         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1783         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1784         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1785         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1786         /* MPLSoUDP & MPLSoGRE */
1787         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1788         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1789         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1790         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1791         /* GTP-C & GTP-U */
1792         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1793         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1794         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1795         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1796         /* QINQ */
1797         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1798 };
1799
1800 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1801         do {                                                            \
1802                 act = actions + index;                                  \
1803                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1804                         index++;                                        \
1805                         act = actions + index;                          \
1806                 }                                                       \
1807         } while (0)
1808
1809 /* Find the first VOID or non-VOID item pointer */
1810 static const struct rte_flow_item *
1811 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1812 {
1813         bool is_find;
1814
1815         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1816                 if (is_void)
1817                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1818                 else
1819                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1820                 if (is_find)
1821                         break;
1822                 item++;
1823         }
1824         return item;
1825 }
1826
1827 /* Skip all VOID items of the pattern */
1828 static void
1829 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1830                             const struct rte_flow_item *pattern)
1831 {
1832         uint32_t cpy_count = 0;
1833         const struct rte_flow_item *pb = pattern, *pe = pattern;
1834
1835         for (;;) {
1836                 /* Find a non-void item first */
1837                 pb = i40e_find_first_item(pb, false);
1838                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1839                         pe = pb;
1840                         break;
1841                 }
1842
1843                 /* Find a void item */
1844                 pe = i40e_find_first_item(pb + 1, true);
1845
1846                 cpy_count = pe - pb;
1847                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1848
1849                 items += cpy_count;
1850
1851                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1852                         pb = pe;
1853                         break;
1854                 }
1855
1856                 pb = pe + 1;
1857         }
1858         /* Copy the END item. */
1859         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1860 }
1861
1862 /* Check if the pattern matches a supported item type array */
1863 static bool
1864 i40e_match_pattern(enum rte_flow_item_type *item_array,
1865                    struct rte_flow_item *pattern)
1866 {
1867         struct rte_flow_item *item = pattern;
1868
1869         while ((*item_array == item->type) &&
1870                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1871                 item_array++;
1872                 item++;
1873         }
1874
1875         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1876                 item->type == RTE_FLOW_ITEM_TYPE_END);
1877 }
1878
1879 /* Find if there's parse filter function matched */
1880 static parse_filter_t
1881 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1882 {
1883         parse_filter_t parse_filter = NULL;
1884         uint8_t i = *idx;
1885
1886         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1887                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1888                                         pattern)) {
1889                         parse_filter = i40e_supported_patterns[i].parse_filter;
1890                         break;
1891                 }
1892         }
1893
1894         *idx = ++i;
1895
1896         return parse_filter;
1897 }
1898
1899 /* Parse attributes */
1900 static int
1901 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1902                      struct rte_flow_error *error)
1903 {
1904         /* Must be input direction */
1905         if (!attr->ingress) {
1906                 rte_flow_error_set(error, EINVAL,
1907                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1908                                    attr, "Only support ingress.");
1909                 return -rte_errno;
1910         }
1911
1912         /* Not supported */
1913         if (attr->egress) {
1914                 rte_flow_error_set(error, EINVAL,
1915                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1916                                    attr, "Not support egress.");
1917                 return -rte_errno;
1918         }
1919
1920         /* Not supported */
1921         if (attr->transfer) {
1922                 rte_flow_error_set(error, EINVAL,
1923                                    RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
1924                                    attr, "No support for transfer.");
1925                 return -rte_errno;
1926         }
1927
1928         /* Not supported */
1929         if (attr->priority) {
1930                 rte_flow_error_set(error, EINVAL,
1931                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1932                                    attr, "Not support priority.");
1933                 return -rte_errno;
1934         }
1935
1936         /* Not supported */
1937         if (attr->group) {
1938                 rte_flow_error_set(error, EINVAL,
1939                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1940                                    attr, "Not support group.");
1941                 return -rte_errno;
1942         }
1943
1944         return 0;
1945 }
1946
1947 static uint16_t
1948 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1949 {
1950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         int qinq = dev->data->dev_conf.rxmode.offloads &
1952                 DEV_RX_OFFLOAD_VLAN_EXTEND;
1953         uint64_t reg_r = 0;
1954         uint16_t reg_id;
1955         uint16_t tpid;
1956
1957         if (qinq)
1958                 reg_id = 2;
1959         else
1960                 reg_id = 3;
1961
1962         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1963                                     &reg_r, NULL);
1964
1965         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1966
1967         return tpid;
1968 }
1969
1970 /* 1. Last in item should be NULL as range is not supported.
1971  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1972  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1973  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1974  *    FF:FF:FF:FF:FF:FF
1975  * 5. Ether_type mask should be 0xFFFF.
1976  */
1977 static int
1978 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1979                                   const struct rte_flow_item *pattern,
1980                                   struct rte_flow_error *error,
1981                                   struct rte_eth_ethertype_filter *filter)
1982 {
1983         const struct rte_flow_item *item = pattern;
1984         const struct rte_flow_item_eth *eth_spec;
1985         const struct rte_flow_item_eth *eth_mask;
1986         enum rte_flow_item_type item_type;
1987         uint16_t outer_tpid;
1988
1989         outer_tpid = i40e_get_outer_vlan(dev);
1990
1991         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1992                 if (item->last) {
1993                         rte_flow_error_set(error, EINVAL,
1994                                            RTE_FLOW_ERROR_TYPE_ITEM,
1995                                            item,
1996                                            "Not support range");
1997                         return -rte_errno;
1998                 }
1999                 item_type = item->type;
2000                 switch (item_type) {
2001                 case RTE_FLOW_ITEM_TYPE_ETH:
2002                         eth_spec = item->spec;
2003                         eth_mask = item->mask;
2004                         /* Get the MAC info. */
2005                         if (!eth_spec || !eth_mask) {
2006                                 rte_flow_error_set(error, EINVAL,
2007                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2008                                                    item,
2009                                                    "NULL ETH spec/mask");
2010                                 return -rte_errno;
2011                         }
2012
2013                         /* Mask bits of source MAC address must be full of 0.
2014                          * Mask bits of destination MAC address must be full
2015                          * of 1 or full of 0.
2016                          */
2017                         if (!is_zero_ether_addr(&eth_mask->src) ||
2018                             (!is_zero_ether_addr(&eth_mask->dst) &&
2019                              !is_broadcast_ether_addr(&eth_mask->dst))) {
2020                                 rte_flow_error_set(error, EINVAL,
2021                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2022                                                    item,
2023                                                    "Invalid MAC_addr mask");
2024                                 return -rte_errno;
2025                         }
2026
2027                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2028                                 rte_flow_error_set(error, EINVAL,
2029                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2030                                                    item,
2031                                                    "Invalid ethertype mask");
2032                                 return -rte_errno;
2033                         }
2034
2035                         /* If mask bits of destination MAC address
2036                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2037                          */
2038                         if (is_broadcast_ether_addr(&eth_mask->dst)) {
2039                                 filter->mac_addr = eth_spec->dst;
2040                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2041                         } else {
2042                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2043                         }
2044                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2045
2046                         if (filter->ether_type == ETHER_TYPE_IPv4 ||
2047                             filter->ether_type == ETHER_TYPE_IPv6 ||
2048                             filter->ether_type == ETHER_TYPE_LLDP ||
2049                             filter->ether_type == outer_tpid) {
2050                                 rte_flow_error_set(error, EINVAL,
2051                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2052                                                    item,
2053                                                    "Unsupported ether_type in"
2054                                                    " control packet filter.");
2055                                 return -rte_errno;
2056                         }
2057                         break;
2058                 default:
2059                         break;
2060                 }
2061         }
2062
2063         return 0;
2064 }
2065
2066 /* Ethertype action only supports QUEUE or DROP. */
2067 static int
2068 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2069                                  const struct rte_flow_action *actions,
2070                                  struct rte_flow_error *error,
2071                                  struct rte_eth_ethertype_filter *filter)
2072 {
2073         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2074         const struct rte_flow_action *act;
2075         const struct rte_flow_action_queue *act_q;
2076         uint32_t index = 0;
2077
2078         /* Check if the first non-void action is QUEUE or DROP. */
2079         NEXT_ITEM_OF_ACTION(act, actions, index);
2080         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2081             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2082                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2083                                    act, "Not supported action.");
2084                 return -rte_errno;
2085         }
2086
2087         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2088                 act_q = act->conf;
2089                 filter->queue = act_q->index;
2090                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2091                         rte_flow_error_set(error, EINVAL,
2092                                            RTE_FLOW_ERROR_TYPE_ACTION,
2093                                            act, "Invalid queue ID for"
2094                                            " ethertype_filter.");
2095                         return -rte_errno;
2096                 }
2097         } else {
2098                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2099         }
2100
2101         /* Check if the next non-void item is END */
2102         index++;
2103         NEXT_ITEM_OF_ACTION(act, actions, index);
2104         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2105                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2106                                    act, "Not supported action.");
2107                 return -rte_errno;
2108         }
2109
2110         return 0;
2111 }
2112
2113 static int
2114 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2115                                  const struct rte_flow_attr *attr,
2116                                  const struct rte_flow_item pattern[],
2117                                  const struct rte_flow_action actions[],
2118                                  struct rte_flow_error *error,
2119                                  union i40e_filter_t *filter)
2120 {
2121         struct rte_eth_ethertype_filter *ethertype_filter =
2122                 &filter->ethertype_filter;
2123         int ret;
2124
2125         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2126                                                 ethertype_filter);
2127         if (ret)
2128                 return ret;
2129
2130         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2131                                                ethertype_filter);
2132         if (ret)
2133                 return ret;
2134
2135         ret = i40e_flow_parse_attr(attr, error);
2136         if (ret)
2137                 return ret;
2138
2139         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2140
2141         return ret;
2142 }
2143
2144 static int
2145 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2146                          const struct rte_flow_item_raw *raw_spec,
2147                          struct rte_flow_error *error)
2148 {
2149         if (!raw_spec->relative) {
2150                 rte_flow_error_set(error, EINVAL,
2151                                    RTE_FLOW_ERROR_TYPE_ITEM,
2152                                    item,
2153                                    "Relative should be 1.");
2154                 return -rte_errno;
2155         }
2156
2157         if (raw_spec->offset % sizeof(uint16_t)) {
2158                 rte_flow_error_set(error, EINVAL,
2159                                    RTE_FLOW_ERROR_TYPE_ITEM,
2160                                    item,
2161                                    "Offset should be even.");
2162                 return -rte_errno;
2163         }
2164
2165         if (raw_spec->search || raw_spec->limit) {
2166                 rte_flow_error_set(error, EINVAL,
2167                                    RTE_FLOW_ERROR_TYPE_ITEM,
2168                                    item,
2169                                    "search or limit is not supported.");
2170                 return -rte_errno;
2171         }
2172
2173         if (raw_spec->offset < 0) {
2174                 rte_flow_error_set(error, EINVAL,
2175                                    RTE_FLOW_ERROR_TYPE_ITEM,
2176                                    item,
2177                                    "Offset should be non-negative.");
2178                 return -rte_errno;
2179         }
2180         return 0;
2181 }
2182
2183 static int
2184 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2185                          struct i40e_fdir_flex_pit *flex_pit,
2186                          enum i40e_flxpld_layer_idx layer_idx,
2187                          uint8_t raw_id)
2188 {
2189         uint8_t field_idx;
2190
2191         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2192         /* Check if the configuration is conflicted */
2193         if (pf->fdir.flex_pit_flag[layer_idx] &&
2194             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2195              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2196              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2197                 return -1;
2198
2199         /* Check if the configuration exists. */
2200         if (pf->fdir.flex_pit_flag[layer_idx] &&
2201             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2202              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2203              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2204                 return 1;
2205
2206         pf->fdir.flex_set[field_idx].src_offset =
2207                 flex_pit->src_offset;
2208         pf->fdir.flex_set[field_idx].size =
2209                 flex_pit->size;
2210         pf->fdir.flex_set[field_idx].dst_offset =
2211                 flex_pit->dst_offset;
2212
2213         return 0;
2214 }
2215
2216 static int
2217 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2218                           enum i40e_filter_pctype pctype,
2219                           uint8_t *mask)
2220 {
2221         struct i40e_fdir_flex_mask flex_mask;
2222         uint16_t mask_tmp;
2223         uint8_t i, nb_bitmask = 0;
2224
2225         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2226         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2227                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2228                 if (mask_tmp) {
2229                         flex_mask.word_mask |=
2230                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2231                         if (mask_tmp != UINT16_MAX) {
2232                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2233                                 flex_mask.bitmask[nb_bitmask].offset =
2234                                         i / sizeof(uint16_t);
2235                                 nb_bitmask++;
2236                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2237                                         return -1;
2238                         }
2239                 }
2240         }
2241         flex_mask.nb_bitmask = nb_bitmask;
2242
2243         if (pf->fdir.flex_mask_flag[pctype] &&
2244             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2245                     sizeof(struct i40e_fdir_flex_mask))))
2246                 return -2;
2247         else if (pf->fdir.flex_mask_flag[pctype] &&
2248                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2249                           sizeof(struct i40e_fdir_flex_mask))))
2250                 return 1;
2251
2252         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2253                sizeof(struct i40e_fdir_flex_mask));
2254         return 0;
2255 }
2256
2257 static void
2258 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2259                             enum i40e_flxpld_layer_idx layer_idx,
2260                             uint8_t raw_id)
2261 {
2262         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2263         uint32_t flx_pit, flx_ort;
2264         uint8_t field_idx;
2265         uint16_t min_next_off = 0;  /* in words */
2266         uint8_t i;
2267
2268         if (raw_id) {
2269                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2270                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2271                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2272                 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2273                 i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
2274         }
2275
2276         /* Set flex pit */
2277         for (i = 0; i < raw_id; i++) {
2278                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2279                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2280                                      pf->fdir.flex_set[field_idx].size,
2281                                      pf->fdir.flex_set[field_idx].dst_offset);
2282
2283                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2284                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2285                         pf->fdir.flex_set[field_idx].size;
2286         }
2287
2288         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2289                 /* set the non-used register obeying register's constrain */
2290                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2291                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2292                                      NONUSE_FLX_PIT_DEST_OFF);
2293                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2294                 min_next_off++;
2295         }
2296
2297         pf->fdir.flex_pit_flag[layer_idx] = 1;
2298 }
2299
2300 static void
2301 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2302                             enum i40e_filter_pctype pctype)
2303 {
2304         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2305         struct i40e_fdir_flex_mask *flex_mask;
2306         uint32_t flxinset, fd_mask;
2307         uint8_t i;
2308
2309         /* Set flex mask */
2310         flex_mask = &pf->fdir.flex_mask[pctype];
2311         flxinset = (flex_mask->word_mask <<
2312                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2313                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2314         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2315
2316         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2317                 fd_mask = (flex_mask->bitmask[i].mask <<
2318                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2319                         I40E_PRTQF_FD_MSK_MASK_MASK;
2320                 fd_mask |= ((flex_mask->bitmask[i].offset +
2321                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2322                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2323                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2324                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2325         }
2326
2327         pf->fdir.flex_mask_flag[pctype] = 1;
2328 }
2329
2330 static int
2331 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2332                          enum i40e_filter_pctype pctype,
2333                          uint64_t input_set)
2334 {
2335         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2336         uint64_t inset_reg = 0;
2337         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2338         int i, num;
2339
2340         /* Check if the input set is valid */
2341         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2342                                     input_set) != 0) {
2343                 PMD_DRV_LOG(ERR, "Invalid input set");
2344                 return -EINVAL;
2345         }
2346
2347         /* Check if the configuration is conflicted */
2348         if (pf->fdir.inset_flag[pctype] &&
2349             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2350                 return -1;
2351
2352         if (pf->fdir.inset_flag[pctype] &&
2353             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2354                 return 0;
2355
2356         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2357                                            I40E_INSET_MASK_NUM_REG);
2358         if (num < 0)
2359                 return -EINVAL;
2360
2361         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2362
2363         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2364                              (uint32_t)(inset_reg & UINT32_MAX));
2365         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2366                              (uint32_t)((inset_reg >>
2367                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2368
2369         for (i = 0; i < num; i++)
2370                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2371                                      mask_reg[i]);
2372
2373         /*clear unused mask registers of the pctype */
2374         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2375                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2376         I40E_WRITE_FLUSH(hw);
2377
2378         pf->fdir.input_set[pctype] = input_set;
2379         pf->fdir.inset_flag[pctype] = 1;
2380         return 0;
2381 }
2382
2383 static uint8_t
2384 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2385                                 enum rte_flow_item_type item_type,
2386                                 struct i40e_fdir_filter_conf *filter)
2387 {
2388         struct i40e_customized_pctype *cus_pctype = NULL;
2389
2390         switch (item_type) {
2391         case RTE_FLOW_ITEM_TYPE_GTPC:
2392                 cus_pctype = i40e_find_customized_pctype(pf,
2393                                                          I40E_CUSTOMIZED_GTPC);
2394                 break;
2395         case RTE_FLOW_ITEM_TYPE_GTPU:
2396                 if (!filter->input.flow_ext.inner_ip)
2397                         cus_pctype = i40e_find_customized_pctype(pf,
2398                                                          I40E_CUSTOMIZED_GTPU);
2399                 else if (filter->input.flow_ext.iip_type ==
2400                          I40E_FDIR_IPTYPE_IPV4)
2401                         cus_pctype = i40e_find_customized_pctype(pf,
2402                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2403                 else if (filter->input.flow_ext.iip_type ==
2404                          I40E_FDIR_IPTYPE_IPV6)
2405                         cus_pctype = i40e_find_customized_pctype(pf,
2406                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2407                 break;
2408         default:
2409                 PMD_DRV_LOG(ERR, "Unsupported item type");
2410                 break;
2411         }
2412
2413         if (cus_pctype && cus_pctype->valid)
2414                 return cus_pctype->pctype;
2415
2416         return I40E_FILTER_PCTYPE_INVALID;
2417 }
2418
2419 /* 1. Last in item should be NULL as range is not supported.
2420  * 2. Supported patterns: refer to array i40e_supported_patterns.
2421  * 3. Default supported flow type and input set: refer to array
2422  *    valid_fdir_inset_table in i40e_ethdev.c.
2423  * 4. Mask of fields which need to be matched should be
2424  *    filled with 1.
2425  * 5. Mask of fields which needn't to be matched should be
2426  *    filled with 0.
2427  * 6. GTP profile supports GTPv1 only.
2428  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2429  */
2430 static int
2431 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2432                              const struct rte_flow_item *pattern,
2433                              struct rte_flow_error *error,
2434                              struct i40e_fdir_filter_conf *filter)
2435 {
2436         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2437         const struct rte_flow_item *item = pattern;
2438         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2439         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2440         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2441         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2442         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2443         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2444         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2445         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2446         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2447         const struct rte_flow_item_vf *vf_spec;
2448
2449         uint8_t pctype = 0;
2450         uint64_t input_set = I40E_INSET_NONE;
2451         uint16_t frag_off;
2452         enum rte_flow_item_type item_type;
2453         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2454         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2455         uint32_t i, j;
2456         uint8_t  ipv6_addr_mask[16] = {
2457                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2458                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2459         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2460         uint8_t raw_id = 0;
2461         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2462         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2463         struct i40e_fdir_flex_pit flex_pit;
2464         uint8_t next_dst_off = 0;
2465         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2466         uint16_t flex_size;
2467         bool cfg_flex_pit = true;
2468         bool cfg_flex_msk = true;
2469         uint16_t outer_tpid;
2470         uint16_t ether_type;
2471         uint32_t vtc_flow_cpu;
2472         bool outer_ip = true;
2473         int ret;
2474
2475         memset(off_arr, 0, sizeof(off_arr));
2476         memset(len_arr, 0, sizeof(len_arr));
2477         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2478         outer_tpid = i40e_get_outer_vlan(dev);
2479         filter->input.flow_ext.customized_pctype = false;
2480         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2481                 if (item->last) {
2482                         rte_flow_error_set(error, EINVAL,
2483                                            RTE_FLOW_ERROR_TYPE_ITEM,
2484                                            item,
2485                                            "Not support range");
2486                         return -rte_errno;
2487                 }
2488                 item_type = item->type;
2489                 switch (item_type) {
2490                 case RTE_FLOW_ITEM_TYPE_ETH:
2491                         eth_spec = item->spec;
2492                         eth_mask = item->mask;
2493
2494                         if (eth_spec && eth_mask) {
2495                                 if (!is_zero_ether_addr(&eth_mask->src) ||
2496                                     !is_zero_ether_addr(&eth_mask->dst)) {
2497                                         rte_flow_error_set(error, EINVAL,
2498                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2499                                                       item,
2500                                                       "Invalid MAC_addr mask.");
2501                                         return -rte_errno;
2502                                 }
2503                         }
2504                         if (eth_spec && eth_mask && eth_mask->type) {
2505                                 enum rte_flow_item_type next = (item + 1)->type;
2506
2507                                 if (eth_mask->type != RTE_BE16(0xffff)) {
2508                                         rte_flow_error_set(error, EINVAL,
2509                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2510                                                       item,
2511                                                       "Invalid type mask.");
2512                                         return -rte_errno;
2513                                 }
2514
2515                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2516
2517                                 if (next == RTE_FLOW_ITEM_TYPE_VLAN ||
2518                                     ether_type == ETHER_TYPE_IPv4 ||
2519                                     ether_type == ETHER_TYPE_IPv6 ||
2520                                     ether_type == ETHER_TYPE_ARP ||
2521                                     ether_type == outer_tpid) {
2522                                         rte_flow_error_set(error, EINVAL,
2523                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2524                                                      item,
2525                                                      "Unsupported ether_type.");
2526                                         return -rte_errno;
2527                                 }
2528                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2529                                 filter->input.flow.l2_flow.ether_type =
2530                                         eth_spec->type;
2531                         }
2532
2533                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2534                         layer_idx = I40E_FLXPLD_L2_IDX;
2535
2536                         break;
2537                 case RTE_FLOW_ITEM_TYPE_VLAN:
2538                         vlan_spec = item->spec;
2539                         vlan_mask = item->mask;
2540
2541                         RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2542                         if (vlan_spec && vlan_mask) {
2543                                 if (vlan_mask->tci ==
2544                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2545                                         input_set |= I40E_INSET_VLAN_INNER;
2546                                         filter->input.flow_ext.vlan_tci =
2547                                                 vlan_spec->tci;
2548                                 }
2549                         }
2550                         if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2551                                 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2552                                         rte_flow_error_set(error, EINVAL,
2553                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2554                                                       item,
2555                                                       "Invalid inner_type"
2556                                                       " mask.");
2557                                         return -rte_errno;
2558                                 }
2559
2560                                 ether_type =
2561                                         rte_be_to_cpu_16(vlan_spec->inner_type);
2562
2563                                 if (ether_type == ETHER_TYPE_IPv4 ||
2564                                     ether_type == ETHER_TYPE_IPv6 ||
2565                                     ether_type == ETHER_TYPE_ARP ||
2566                                     ether_type == outer_tpid) {
2567                                         rte_flow_error_set(error, EINVAL,
2568                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2569                                                      item,
2570                                                      "Unsupported inner_type.");
2571                                         return -rte_errno;
2572                                 }
2573                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2574                                 filter->input.flow.l2_flow.ether_type =
2575                                         vlan_spec->inner_type;
2576                         }
2577
2578                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2579                         layer_idx = I40E_FLXPLD_L2_IDX;
2580
2581                         break;
2582                 case RTE_FLOW_ITEM_TYPE_IPV4:
2583                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2584                         ipv4_spec = item->spec;
2585                         ipv4_mask = item->mask;
2586                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2587                         layer_idx = I40E_FLXPLD_L3_IDX;
2588
2589                         if (ipv4_spec && ipv4_mask && outer_ip) {
2590                                 /* Check IPv4 mask and update input set */
2591                                 if (ipv4_mask->hdr.version_ihl ||
2592                                     ipv4_mask->hdr.total_length ||
2593                                     ipv4_mask->hdr.packet_id ||
2594                                     ipv4_mask->hdr.fragment_offset ||
2595                                     ipv4_mask->hdr.hdr_checksum) {
2596                                         rte_flow_error_set(error, EINVAL,
2597                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2598                                                    item,
2599                                                    "Invalid IPv4 mask.");
2600                                         return -rte_errno;
2601                                 }
2602
2603                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2604                                         input_set |= I40E_INSET_IPV4_SRC;
2605                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2606                                         input_set |= I40E_INSET_IPV4_DST;
2607                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2608                                         input_set |= I40E_INSET_IPV4_TOS;
2609                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2610                                         input_set |= I40E_INSET_IPV4_TTL;
2611                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2612                                         input_set |= I40E_INSET_IPV4_PROTO;
2613
2614                                 /* Check if it is fragment. */
2615                                 frag_off = ipv4_spec->hdr.fragment_offset;
2616                                 frag_off = rte_be_to_cpu_16(frag_off);
2617                                 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2618                                     frag_off & IPV4_HDR_MF_FLAG)
2619                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2620
2621                                 /* Get the filter info */
2622                                 filter->input.flow.ip4_flow.proto =
2623                                         ipv4_spec->hdr.next_proto_id;
2624                                 filter->input.flow.ip4_flow.tos =
2625                                         ipv4_spec->hdr.type_of_service;
2626                                 filter->input.flow.ip4_flow.ttl =
2627                                         ipv4_spec->hdr.time_to_live;
2628                                 filter->input.flow.ip4_flow.src_ip =
2629                                         ipv4_spec->hdr.src_addr;
2630                                 filter->input.flow.ip4_flow.dst_ip =
2631                                         ipv4_spec->hdr.dst_addr;
2632                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2633                                 filter->input.flow_ext.inner_ip = true;
2634                                 filter->input.flow_ext.iip_type =
2635                                         I40E_FDIR_IPTYPE_IPV4;
2636                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2637                                 rte_flow_error_set(error, EINVAL,
2638                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2639                                                    item,
2640                                                    "Invalid inner IPv4 mask.");
2641                                 return -rte_errno;
2642                         }
2643
2644                         if (outer_ip)
2645                                 outer_ip = false;
2646
2647                         break;
2648                 case RTE_FLOW_ITEM_TYPE_IPV6:
2649                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2650                         ipv6_spec = item->spec;
2651                         ipv6_mask = item->mask;
2652                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2653                         layer_idx = I40E_FLXPLD_L3_IDX;
2654
2655                         if (ipv6_spec && ipv6_mask && outer_ip) {
2656                                 /* Check IPv6 mask and update input set */
2657                                 if (ipv6_mask->hdr.payload_len) {
2658                                         rte_flow_error_set(error, EINVAL,
2659                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2660                                                    item,
2661                                                    "Invalid IPv6 mask");
2662                                         return -rte_errno;
2663                                 }
2664
2665                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2666                                             ipv6_addr_mask,
2667                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2668                                         input_set |= I40E_INSET_IPV6_SRC;
2669                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2670                                             ipv6_addr_mask,
2671                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2672                                         input_set |= I40E_INSET_IPV6_DST;
2673
2674                                 if ((ipv6_mask->hdr.vtc_flow &
2675                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2676                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2677                                         input_set |= I40E_INSET_IPV6_TC;
2678                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2679                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2680                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2681                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2682
2683                                 /* Get filter info */
2684                                 vtc_flow_cpu =
2685                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2686                                 filter->input.flow.ipv6_flow.tc =
2687                                         (uint8_t)(vtc_flow_cpu >>
2688                                                   I40E_FDIR_IPv6_TC_OFFSET);
2689                                 filter->input.flow.ipv6_flow.proto =
2690                                         ipv6_spec->hdr.proto;
2691                                 filter->input.flow.ipv6_flow.hop_limits =
2692                                         ipv6_spec->hdr.hop_limits;
2693
2694                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2695                                            ipv6_spec->hdr.src_addr, 16);
2696                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2697                                            ipv6_spec->hdr.dst_addr, 16);
2698
2699                                 /* Check if it is fragment. */
2700                                 if (ipv6_spec->hdr.proto ==
2701                                     I40E_IPV6_FRAG_HEADER)
2702                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2703                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2704                                 filter->input.flow_ext.inner_ip = true;
2705                                 filter->input.flow_ext.iip_type =
2706                                         I40E_FDIR_IPTYPE_IPV6;
2707                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2708                                 rte_flow_error_set(error, EINVAL,
2709                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2710                                                    item,
2711                                                    "Invalid inner IPv6 mask");
2712                                 return -rte_errno;
2713                         }
2714
2715                         if (outer_ip)
2716                                 outer_ip = false;
2717                         break;
2718                 case RTE_FLOW_ITEM_TYPE_TCP:
2719                         tcp_spec = item->spec;
2720                         tcp_mask = item->mask;
2721
2722                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2723                                 pctype =
2724                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2725                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2726                                 pctype =
2727                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2728                         if (tcp_spec && tcp_mask) {
2729                                 /* Check TCP mask and update input set */
2730                                 if (tcp_mask->hdr.sent_seq ||
2731                                     tcp_mask->hdr.recv_ack ||
2732                                     tcp_mask->hdr.data_off ||
2733                                     tcp_mask->hdr.tcp_flags ||
2734                                     tcp_mask->hdr.rx_win ||
2735                                     tcp_mask->hdr.cksum ||
2736                                     tcp_mask->hdr.tcp_urp) {
2737                                         rte_flow_error_set(error, EINVAL,
2738                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2739                                                    item,
2740                                                    "Invalid TCP mask");
2741                                         return -rte_errno;
2742                                 }
2743
2744                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2745                                         input_set |= I40E_INSET_SRC_PORT;
2746                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2747                                         input_set |= I40E_INSET_DST_PORT;
2748
2749                                 /* Get filter info */
2750                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2751                                         filter->input.flow.tcp4_flow.src_port =
2752                                                 tcp_spec->hdr.src_port;
2753                                         filter->input.flow.tcp4_flow.dst_port =
2754                                                 tcp_spec->hdr.dst_port;
2755                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2756                                         filter->input.flow.tcp6_flow.src_port =
2757                                                 tcp_spec->hdr.src_port;
2758                                         filter->input.flow.tcp6_flow.dst_port =
2759                                                 tcp_spec->hdr.dst_port;
2760                                 }
2761                         }
2762
2763                         layer_idx = I40E_FLXPLD_L4_IDX;
2764
2765                         break;
2766                 case RTE_FLOW_ITEM_TYPE_UDP:
2767                         udp_spec = item->spec;
2768                         udp_mask = item->mask;
2769
2770                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2771                                 pctype =
2772                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2773                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2774                                 pctype =
2775                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2776
2777                         if (udp_spec && udp_mask) {
2778                                 /* Check UDP mask and update input set*/
2779                                 if (udp_mask->hdr.dgram_len ||
2780                                     udp_mask->hdr.dgram_cksum) {
2781                                         rte_flow_error_set(error, EINVAL,
2782                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2783                                                    item,
2784                                                    "Invalid UDP mask");
2785                                         return -rte_errno;
2786                                 }
2787
2788                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2789                                         input_set |= I40E_INSET_SRC_PORT;
2790                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2791                                         input_set |= I40E_INSET_DST_PORT;
2792
2793                                 /* Get filter info */
2794                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2795                                         filter->input.flow.udp4_flow.src_port =
2796                                                 udp_spec->hdr.src_port;
2797                                         filter->input.flow.udp4_flow.dst_port =
2798                                                 udp_spec->hdr.dst_port;
2799                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2800                                         filter->input.flow.udp6_flow.src_port =
2801                                                 udp_spec->hdr.src_port;
2802                                         filter->input.flow.udp6_flow.dst_port =
2803                                                 udp_spec->hdr.dst_port;
2804                                 }
2805                         }
2806
2807                         layer_idx = I40E_FLXPLD_L4_IDX;
2808
2809                         break;
2810                 case RTE_FLOW_ITEM_TYPE_GTPC:
2811                 case RTE_FLOW_ITEM_TYPE_GTPU:
2812                         if (!pf->gtp_support) {
2813                                 rte_flow_error_set(error, EINVAL,
2814                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2815                                                    item,
2816                                                    "Unsupported protocol");
2817                                 return -rte_errno;
2818                         }
2819
2820                         gtp_spec = item->spec;
2821                         gtp_mask = item->mask;
2822
2823                         if (gtp_spec && gtp_mask) {
2824                                 if (gtp_mask->v_pt_rsv_flags ||
2825                                     gtp_mask->msg_type ||
2826                                     gtp_mask->msg_len ||
2827                                     gtp_mask->teid != UINT32_MAX) {
2828                                         rte_flow_error_set(error, EINVAL,
2829                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2830                                                    item,
2831                                                    "Invalid GTP mask");
2832                                         return -rte_errno;
2833                                 }
2834
2835                                 filter->input.flow.gtp_flow.teid =
2836                                         gtp_spec->teid;
2837                                 filter->input.flow_ext.customized_pctype = true;
2838                                 cus_proto = item_type;
2839                         }
2840                         break;
2841                 case RTE_FLOW_ITEM_TYPE_SCTP:
2842                         sctp_spec = item->spec;
2843                         sctp_mask = item->mask;
2844
2845                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2846                                 pctype =
2847                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2848                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2849                                 pctype =
2850                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2851
2852                         if (sctp_spec && sctp_mask) {
2853                                 /* Check SCTP mask and update input set */
2854                                 if (sctp_mask->hdr.cksum) {
2855                                         rte_flow_error_set(error, EINVAL,
2856                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2857                                                    item,
2858                                                    "Invalid UDP mask");
2859                                         return -rte_errno;
2860                                 }
2861
2862                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2863                                         input_set |= I40E_INSET_SRC_PORT;
2864                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2865                                         input_set |= I40E_INSET_DST_PORT;
2866                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2867                                         input_set |= I40E_INSET_SCTP_VT;
2868
2869                                 /* Get filter info */
2870                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2871                                         filter->input.flow.sctp4_flow.src_port =
2872                                                 sctp_spec->hdr.src_port;
2873                                         filter->input.flow.sctp4_flow.dst_port =
2874                                                 sctp_spec->hdr.dst_port;
2875                                         filter->input.flow.sctp4_flow.verify_tag
2876                                                 = sctp_spec->hdr.tag;
2877                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2878                                         filter->input.flow.sctp6_flow.src_port =
2879                                                 sctp_spec->hdr.src_port;
2880                                         filter->input.flow.sctp6_flow.dst_port =
2881                                                 sctp_spec->hdr.dst_port;
2882                                         filter->input.flow.sctp6_flow.verify_tag
2883                                                 = sctp_spec->hdr.tag;
2884                                 }
2885                         }
2886
2887                         layer_idx = I40E_FLXPLD_L4_IDX;
2888
2889                         break;
2890                 case RTE_FLOW_ITEM_TYPE_RAW:
2891                         raw_spec = item->spec;
2892                         raw_mask = item->mask;
2893
2894                         if (!raw_spec || !raw_mask) {
2895                                 rte_flow_error_set(error, EINVAL,
2896                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2897                                                    item,
2898                                                    "NULL RAW spec/mask");
2899                                 return -rte_errno;
2900                         }
2901
2902                         if (pf->support_multi_driver) {
2903                                 rte_flow_error_set(error, ENOTSUP,
2904                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2905                                                    item,
2906                                                    "Unsupported flexible payload.");
2907                                 return -rte_errno;
2908                         }
2909
2910                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2911                         if (ret < 0)
2912                                 return ret;
2913
2914                         off_arr[raw_id] = raw_spec->offset;
2915                         len_arr[raw_id] = raw_spec->length;
2916
2917                         flex_size = 0;
2918                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2919                         flex_pit.size =
2920                                 raw_spec->length / sizeof(uint16_t);
2921                         flex_pit.dst_offset =
2922                                 next_dst_off / sizeof(uint16_t);
2923
2924                         for (i = 0; i <= raw_id; i++) {
2925                                 if (i == raw_id)
2926                                         flex_pit.src_offset +=
2927                                                 raw_spec->offset /
2928                                                 sizeof(uint16_t);
2929                                 else
2930                                         flex_pit.src_offset +=
2931                                                 (off_arr[i] + len_arr[i]) /
2932                                                 sizeof(uint16_t);
2933                                 flex_size += len_arr[i];
2934                         }
2935                         if (((flex_pit.src_offset + flex_pit.size) >=
2936                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2937                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2938                                 rte_flow_error_set(error, EINVAL,
2939                                            RTE_FLOW_ERROR_TYPE_ITEM,
2940                                            item,
2941                                            "Exceeds maxmial payload limit.");
2942                                 return -rte_errno;
2943                         }
2944
2945                         /* Store flex pit to SW */
2946                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2947                                                        layer_idx, raw_id);
2948                         if (ret < 0) {
2949                                 rte_flow_error_set(error, EINVAL,
2950                                    RTE_FLOW_ERROR_TYPE_ITEM,
2951                                    item,
2952                                    "Conflict with the first flexible rule.");
2953                                 return -rte_errno;
2954                         } else if (ret > 0)
2955                                 cfg_flex_pit = false;
2956
2957                         for (i = 0; i < raw_spec->length; i++) {
2958                                 j = i + next_dst_off;
2959                                 filter->input.flow_ext.flexbytes[j] =
2960                                         raw_spec->pattern[i];
2961                                 flex_mask[j] = raw_mask->pattern[i];
2962                         }
2963
2964                         next_dst_off += raw_spec->length;
2965                         raw_id++;
2966                         break;
2967                 case RTE_FLOW_ITEM_TYPE_VF:
2968                         vf_spec = item->spec;
2969                         filter->input.flow_ext.is_vf = 1;
2970                         filter->input.flow_ext.dst_id = vf_spec->id;
2971                         if (filter->input.flow_ext.is_vf &&
2972                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2973                                 rte_flow_error_set(error, EINVAL,
2974                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2975                                                    item,
2976                                                    "Invalid VF ID for FDIR.");
2977                                 return -rte_errno;
2978                         }
2979                         break;
2980                 default:
2981                         break;
2982                 }
2983         }
2984
2985         /* Get customized pctype value */
2986         if (filter->input.flow_ext.customized_pctype) {
2987                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2988                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2989                         rte_flow_error_set(error, EINVAL,
2990                                            RTE_FLOW_ERROR_TYPE_ITEM,
2991                                            item,
2992                                            "Unsupported pctype");
2993                         return -rte_errno;
2994                 }
2995         }
2996
2997         /* If customized pctype is not used, set fdir configuration.*/
2998         if (!filter->input.flow_ext.customized_pctype) {
2999                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3000                 if (ret == -1) {
3001                         rte_flow_error_set(error, EINVAL,
3002                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3003                                            "Conflict with the first rule's input set.");
3004                         return -rte_errno;
3005                 } else if (ret == -EINVAL) {
3006                         rte_flow_error_set(error, EINVAL,
3007                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3008                                            "Invalid pattern mask.");
3009                         return -rte_errno;
3010                 }
3011
3012                 /* Store flex mask to SW */
3013                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3014                 if (ret == -1) {
3015                         rte_flow_error_set(error, EINVAL,
3016                                            RTE_FLOW_ERROR_TYPE_ITEM,
3017                                            item,
3018                                            "Exceed maximal number of bitmasks");
3019                         return -rte_errno;
3020                 } else if (ret == -2) {
3021                         rte_flow_error_set(error, EINVAL,
3022                                            RTE_FLOW_ERROR_TYPE_ITEM,
3023                                            item,
3024                                            "Conflict with the first flexible rule");
3025                         return -rte_errno;
3026                 } else if (ret > 0)
3027                         cfg_flex_msk = false;
3028
3029                 if (cfg_flex_pit)
3030                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3031
3032                 if (cfg_flex_msk)
3033                         i40e_flow_set_fdir_flex_msk(pf, pctype);
3034         }
3035
3036         filter->input.pctype = pctype;
3037
3038         return 0;
3039 }
3040
3041 /* Parse to get the action info of a FDIR filter.
3042  * FDIR action supports QUEUE or (QUEUE + MARK).
3043  */
3044 static int
3045 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3046                             const struct rte_flow_action *actions,
3047                             struct rte_flow_error *error,
3048                             struct i40e_fdir_filter_conf *filter)
3049 {
3050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3051         const struct rte_flow_action *act;
3052         const struct rte_flow_action_queue *act_q;
3053         const struct rte_flow_action_mark *mark_spec;
3054         uint32_t index = 0;
3055
3056         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3057         NEXT_ITEM_OF_ACTION(act, actions, index);
3058         switch (act->type) {
3059         case RTE_FLOW_ACTION_TYPE_QUEUE:
3060                 act_q = act->conf;
3061                 filter->action.rx_queue = act_q->index;
3062                 if ((!filter->input.flow_ext.is_vf &&
3063                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3064                     (filter->input.flow_ext.is_vf &&
3065                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3066                         rte_flow_error_set(error, EINVAL,
3067                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3068                                            "Invalid queue ID for FDIR.");
3069                         return -rte_errno;
3070                 }
3071                 filter->action.behavior = I40E_FDIR_ACCEPT;
3072                 break;
3073         case RTE_FLOW_ACTION_TYPE_DROP:
3074                 filter->action.behavior = I40E_FDIR_REJECT;
3075                 break;
3076         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3077                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3078                 break;
3079         default:
3080                 rte_flow_error_set(error, EINVAL,
3081                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3082                                    "Invalid action.");
3083                 return -rte_errno;
3084         }
3085
3086         /* Check if the next non-void item is MARK or FLAG or END. */
3087         index++;
3088         NEXT_ITEM_OF_ACTION(act, actions, index);
3089         switch (act->type) {
3090         case RTE_FLOW_ACTION_TYPE_MARK:
3091                 mark_spec = act->conf;
3092                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3093                 filter->soft_id = mark_spec->id;
3094                 break;
3095         case RTE_FLOW_ACTION_TYPE_FLAG:
3096                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3097                 break;
3098         case RTE_FLOW_ACTION_TYPE_END:
3099                 return 0;
3100         default:
3101                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3102                                    act, "Invalid action.");
3103                 return -rte_errno;
3104         }
3105
3106         /* Check if the next non-void item is END */
3107         index++;
3108         NEXT_ITEM_OF_ACTION(act, actions, index);
3109         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3110                 rte_flow_error_set(error, EINVAL,
3111                                    RTE_FLOW_ERROR_TYPE_ACTION,
3112                                    act, "Invalid action.");
3113                 return -rte_errno;
3114         }
3115
3116         return 0;
3117 }
3118
3119 static int
3120 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3121                             const struct rte_flow_attr *attr,
3122                             const struct rte_flow_item pattern[],
3123                             const struct rte_flow_action actions[],
3124                             struct rte_flow_error *error,
3125                             union i40e_filter_t *filter)
3126 {
3127         struct i40e_fdir_filter_conf *fdir_filter =
3128                 &filter->fdir_filter;
3129         int ret;
3130
3131         ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3132         if (ret)
3133                 return ret;
3134
3135         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3136         if (ret)
3137                 return ret;
3138
3139         ret = i40e_flow_parse_attr(attr, error);
3140         if (ret)
3141                 return ret;
3142
3143         cons_filter_type = RTE_ETH_FILTER_FDIR;
3144
3145         if (dev->data->dev_conf.fdir_conf.mode !=
3146             RTE_FDIR_MODE_PERFECT) {
3147                 rte_flow_error_set(error, ENOTSUP,
3148                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3149                                    NULL,
3150                                    "Check the mode in fdir_conf.");
3151                 return -rte_errno;
3152         }
3153
3154         return 0;
3155 }
3156
3157 /* Parse to get the action info of a tunnel filter
3158  * Tunnel action only supports PF, VF and QUEUE.
3159  */
3160 static int
3161 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3162                               const struct rte_flow_action *actions,
3163                               struct rte_flow_error *error,
3164                               struct i40e_tunnel_filter_conf *filter)
3165 {
3166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3167         const struct rte_flow_action *act;
3168         const struct rte_flow_action_queue *act_q;
3169         const struct rte_flow_action_vf *act_vf;
3170         uint32_t index = 0;
3171
3172         /* Check if the first non-void action is PF or VF. */
3173         NEXT_ITEM_OF_ACTION(act, actions, index);
3174         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3175             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3176                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3177                                    act, "Not supported action.");
3178                 return -rte_errno;
3179         }
3180
3181         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3182                 act_vf = act->conf;
3183                 filter->vf_id = act_vf->id;
3184                 filter->is_to_vf = 1;
3185                 if (filter->vf_id >= pf->vf_num) {
3186                         rte_flow_error_set(error, EINVAL,
3187                                    RTE_FLOW_ERROR_TYPE_ACTION,
3188                                    act, "Invalid VF ID for tunnel filter");
3189                         return -rte_errno;
3190                 }
3191         }
3192
3193         /* Check if the next non-void item is QUEUE */
3194         index++;
3195         NEXT_ITEM_OF_ACTION(act, actions, index);
3196         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3197                 act_q = act->conf;
3198                 filter->queue_id = act_q->index;
3199                 if ((!filter->is_to_vf) &&
3200                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3201                         rte_flow_error_set(error, EINVAL,
3202                                    RTE_FLOW_ERROR_TYPE_ACTION,
3203                                    act, "Invalid queue ID for tunnel filter");
3204                         return -rte_errno;
3205                 } else if (filter->is_to_vf &&
3206                            (filter->queue_id >= pf->vf_nb_qps)) {
3207                         rte_flow_error_set(error, EINVAL,
3208                                    RTE_FLOW_ERROR_TYPE_ACTION,
3209                                    act, "Invalid queue ID for tunnel filter");
3210                         return -rte_errno;
3211                 }
3212         }
3213
3214         /* Check if the next non-void item is END */
3215         index++;
3216         NEXT_ITEM_OF_ACTION(act, actions, index);
3217         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3218                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3219                                    act, "Not supported action.");
3220                 return -rte_errno;
3221         }
3222
3223         return 0;
3224 }
3225
3226 static uint16_t i40e_supported_tunnel_filter_types[] = {
3227         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3228         ETH_TUNNEL_FILTER_IVLAN,
3229         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3230         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3231         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3232         ETH_TUNNEL_FILTER_IMAC,
3233         ETH_TUNNEL_FILTER_IMAC,
3234 };
3235
3236 static int
3237 i40e_check_tunnel_filter_type(uint8_t filter_type)
3238 {
3239         uint8_t i;
3240
3241         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3242                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3243                         return 0;
3244         }
3245
3246         return -1;
3247 }
3248
3249 /* 1. Last in item should be NULL as range is not supported.
3250  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3251  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3252  * 3. Mask of fields which need to be matched should be
3253  *    filled with 1.
3254  * 4. Mask of fields which needn't to be matched should be
3255  *    filled with 0.
3256  */
3257 static int
3258 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3259                               const struct rte_flow_item *pattern,
3260                               struct rte_flow_error *error,
3261                               struct i40e_tunnel_filter_conf *filter)
3262 {
3263         const struct rte_flow_item *item = pattern;
3264         const struct rte_flow_item_eth *eth_spec;
3265         const struct rte_flow_item_eth *eth_mask;
3266         const struct rte_flow_item_vxlan *vxlan_spec;
3267         const struct rte_flow_item_vxlan *vxlan_mask;
3268         const struct rte_flow_item_vlan *vlan_spec;
3269         const struct rte_flow_item_vlan *vlan_mask;
3270         uint8_t filter_type = 0;
3271         bool is_vni_masked = 0;
3272         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3273         enum rte_flow_item_type item_type;
3274         bool vxlan_flag = 0;
3275         uint32_t tenant_id_be = 0;
3276         int ret;
3277
3278         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3279                 if (item->last) {
3280                         rte_flow_error_set(error, EINVAL,
3281                                            RTE_FLOW_ERROR_TYPE_ITEM,
3282                                            item,
3283                                            "Not support range");
3284                         return -rte_errno;
3285                 }
3286                 item_type = item->type;
3287                 switch (item_type) {
3288                 case RTE_FLOW_ITEM_TYPE_ETH:
3289                         eth_spec = item->spec;
3290                         eth_mask = item->mask;
3291
3292                         /* Check if ETH item is used for place holder.
3293                          * If yes, both spec and mask should be NULL.
3294                          * If no, both spec and mask shouldn't be NULL.
3295                          */
3296                         if ((!eth_spec && eth_mask) ||
3297                             (eth_spec && !eth_mask)) {
3298                                 rte_flow_error_set(error, EINVAL,
3299                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3300                                                    item,
3301                                                    "Invalid ether spec/mask");
3302                                 return -rte_errno;
3303                         }
3304
3305                         if (eth_spec && eth_mask) {
3306                                 /* DST address of inner MAC shouldn't be masked.
3307                                  * SRC address of Inner MAC should be masked.
3308                                  */
3309                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3310                                     !is_zero_ether_addr(&eth_mask->src) ||
3311                                     eth_mask->type) {
3312                                         rte_flow_error_set(error, EINVAL,
3313                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3314                                                    item,
3315                                                    "Invalid ether spec/mask");
3316                                         return -rte_errno;
3317                                 }
3318
3319                                 if (!vxlan_flag) {
3320                                         rte_memcpy(&filter->outer_mac,
3321                                                    &eth_spec->dst,
3322                                                    ETHER_ADDR_LEN);
3323                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3324                                 } else {
3325                                         rte_memcpy(&filter->inner_mac,
3326                                                    &eth_spec->dst,
3327                                                    ETHER_ADDR_LEN);
3328                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3329                                 }
3330                         }
3331                         break;
3332                 case RTE_FLOW_ITEM_TYPE_VLAN:
3333                         vlan_spec = item->spec;
3334                         vlan_mask = item->mask;
3335                         if (!(vlan_spec && vlan_mask) ||
3336                             vlan_mask->inner_type) {
3337                                 rte_flow_error_set(error, EINVAL,
3338                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3339                                                    item,
3340                                                    "Invalid vlan item");
3341                                 return -rte_errno;
3342                         }
3343
3344                         if (vlan_spec && vlan_mask) {
3345                                 if (vlan_mask->tci ==
3346                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3347                                         filter->inner_vlan =
3348                                               rte_be_to_cpu_16(vlan_spec->tci) &
3349                                               I40E_TCI_MASK;
3350                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3351                         }
3352                         break;
3353                 case RTE_FLOW_ITEM_TYPE_IPV4:
3354                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3355                         /* IPv4 is used to describe protocol,
3356                          * spec and mask should be NULL.
3357                          */
3358                         if (item->spec || item->mask) {
3359                                 rte_flow_error_set(error, EINVAL,
3360                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3361                                                    item,
3362                                                    "Invalid IPv4 item");
3363                                 return -rte_errno;
3364                         }
3365                         break;
3366                 case RTE_FLOW_ITEM_TYPE_IPV6:
3367                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3368                         /* IPv6 is used to describe protocol,
3369                          * spec and mask should be NULL.
3370                          */
3371                         if (item->spec || item->mask) {
3372                                 rte_flow_error_set(error, EINVAL,
3373                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3374                                                    item,
3375                                                    "Invalid IPv6 item");
3376                                 return -rte_errno;
3377                         }
3378                         break;
3379                 case RTE_FLOW_ITEM_TYPE_UDP:
3380                         /* UDP is used to describe protocol,
3381                          * spec and mask should be NULL.
3382                          */
3383                         if (item->spec || item->mask) {
3384                                 rte_flow_error_set(error, EINVAL,
3385                                            RTE_FLOW_ERROR_TYPE_ITEM,
3386                                            item,
3387                                            "Invalid UDP item");
3388                                 return -rte_errno;
3389                         }
3390                         break;
3391                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3392                         vxlan_spec = item->spec;
3393                         vxlan_mask = item->mask;
3394                         /* Check if VXLAN item is used to describe protocol.
3395                          * If yes, both spec and mask should be NULL.
3396                          * If no, both spec and mask shouldn't be NULL.
3397                          */
3398                         if ((!vxlan_spec && vxlan_mask) ||
3399                             (vxlan_spec && !vxlan_mask)) {
3400                                 rte_flow_error_set(error, EINVAL,
3401                                            RTE_FLOW_ERROR_TYPE_ITEM,
3402                                            item,
3403                                            "Invalid VXLAN item");
3404                                 return -rte_errno;
3405                         }
3406
3407                         /* Check if VNI is masked. */
3408                         if (vxlan_spec && vxlan_mask) {
3409                                 is_vni_masked =
3410                                         !!memcmp(vxlan_mask->vni, vni_mask,
3411                                                  RTE_DIM(vni_mask));
3412                                 if (is_vni_masked) {
3413                                         rte_flow_error_set(error, EINVAL,
3414                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3415                                                    item,
3416                                                    "Invalid VNI mask");
3417                                         return -rte_errno;
3418                                 }
3419
3420                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3421                                            vxlan_spec->vni, 3);
3422                                 filter->tenant_id =
3423                                         rte_be_to_cpu_32(tenant_id_be);
3424                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3425                         }
3426
3427                         vxlan_flag = 1;
3428                         break;
3429                 default:
3430                         break;
3431                 }
3432         }
3433
3434         ret = i40e_check_tunnel_filter_type(filter_type);
3435         if (ret < 0) {
3436                 rte_flow_error_set(error, EINVAL,
3437                                    RTE_FLOW_ERROR_TYPE_ITEM,
3438                                    NULL,
3439                                    "Invalid filter type");
3440                 return -rte_errno;
3441         }
3442         filter->filter_type = filter_type;
3443
3444         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3445
3446         return 0;
3447 }
3448
3449 static int
3450 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3451                              const struct rte_flow_attr *attr,
3452                              const struct rte_flow_item pattern[],
3453                              const struct rte_flow_action actions[],
3454                              struct rte_flow_error *error,
3455                              union i40e_filter_t *filter)
3456 {
3457         struct i40e_tunnel_filter_conf *tunnel_filter =
3458                 &filter->consistent_tunnel_filter;
3459         int ret;
3460
3461         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3462                                             error, tunnel_filter);
3463         if (ret)
3464                 return ret;
3465
3466         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3467         if (ret)
3468                 return ret;
3469
3470         ret = i40e_flow_parse_attr(attr, error);
3471         if (ret)
3472                 return ret;
3473
3474         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3475
3476         return ret;
3477 }
3478
3479 /* 1. Last in item should be NULL as range is not supported.
3480  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3481  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3482  * 3. Mask of fields which need to be matched should be
3483  *    filled with 1.
3484  * 4. Mask of fields which needn't to be matched should be
3485  *    filled with 0.
3486  */
3487 static int
3488 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3489                               const struct rte_flow_item *pattern,
3490                               struct rte_flow_error *error,
3491                               struct i40e_tunnel_filter_conf *filter)
3492 {
3493         const struct rte_flow_item *item = pattern;
3494         const struct rte_flow_item_eth *eth_spec;
3495         const struct rte_flow_item_eth *eth_mask;
3496         const struct rte_flow_item_nvgre *nvgre_spec;
3497         const struct rte_flow_item_nvgre *nvgre_mask;
3498         const struct rte_flow_item_vlan *vlan_spec;
3499         const struct rte_flow_item_vlan *vlan_mask;
3500         enum rte_flow_item_type item_type;
3501         uint8_t filter_type = 0;
3502         bool is_tni_masked = 0;
3503         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3504         bool nvgre_flag = 0;
3505         uint32_t tenant_id_be = 0;
3506         int ret;
3507
3508         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3509                 if (item->last) {
3510                         rte_flow_error_set(error, EINVAL,
3511                                            RTE_FLOW_ERROR_TYPE_ITEM,
3512                                            item,
3513                                            "Not support range");
3514                         return -rte_errno;
3515                 }
3516                 item_type = item->type;
3517                 switch (item_type) {
3518                 case RTE_FLOW_ITEM_TYPE_ETH:
3519                         eth_spec = item->spec;
3520                         eth_mask = item->mask;
3521
3522                         /* Check if ETH item is used for place holder.
3523                          * If yes, both spec and mask should be NULL.
3524                          * If no, both spec and mask shouldn't be NULL.
3525                          */
3526                         if ((!eth_spec && eth_mask) ||
3527                             (eth_spec && !eth_mask)) {
3528                                 rte_flow_error_set(error, EINVAL,
3529                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3530                                                    item,
3531                                                    "Invalid ether spec/mask");
3532                                 return -rte_errno;
3533                         }
3534
3535                         if (eth_spec && eth_mask) {
3536                                 /* DST address of inner MAC shouldn't be masked.
3537                                  * SRC address of Inner MAC should be masked.
3538                                  */
3539                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3540                                     !is_zero_ether_addr(&eth_mask->src) ||
3541                                     eth_mask->type) {
3542                                         rte_flow_error_set(error, EINVAL,
3543                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3544                                                    item,
3545                                                    "Invalid ether spec/mask");
3546                                         return -rte_errno;
3547                                 }
3548
3549                                 if (!nvgre_flag) {
3550                                         rte_memcpy(&filter->outer_mac,
3551                                                    &eth_spec->dst,
3552                                                    ETHER_ADDR_LEN);
3553                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3554                                 } else {
3555                                         rte_memcpy(&filter->inner_mac,
3556                                                    &eth_spec->dst,
3557                                                    ETHER_ADDR_LEN);
3558                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3559                                 }
3560                         }
3561
3562                         break;
3563                 case RTE_FLOW_ITEM_TYPE_VLAN:
3564                         vlan_spec = item->spec;
3565                         vlan_mask = item->mask;
3566                         if (!(vlan_spec && vlan_mask) ||
3567                             vlan_mask->inner_type) {
3568                                 rte_flow_error_set(error, EINVAL,
3569                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3570                                                    item,
3571                                                    "Invalid vlan item");
3572                                 return -rte_errno;
3573                         }
3574
3575                         if (vlan_spec && vlan_mask) {
3576                                 if (vlan_mask->tci ==
3577                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3578                                         filter->inner_vlan =
3579                                               rte_be_to_cpu_16(vlan_spec->tci) &
3580                                               I40E_TCI_MASK;
3581                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3582                         }
3583                         break;
3584                 case RTE_FLOW_ITEM_TYPE_IPV4:
3585                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3586                         /* IPv4 is used to describe protocol,
3587                          * spec and mask should be NULL.
3588                          */
3589                         if (item->spec || item->mask) {
3590                                 rte_flow_error_set(error, EINVAL,
3591                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3592                                                    item,
3593                                                    "Invalid IPv4 item");
3594                                 return -rte_errno;
3595                         }
3596                         break;
3597                 case RTE_FLOW_ITEM_TYPE_IPV6:
3598                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3599                         /* IPv6 is used to describe protocol,
3600                          * spec and mask should be NULL.
3601                          */
3602                         if (item->spec || item->mask) {
3603                                 rte_flow_error_set(error, EINVAL,
3604                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3605                                                    item,
3606                                                    "Invalid IPv6 item");
3607                                 return -rte_errno;
3608                         }
3609                         break;
3610                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3611                         nvgre_spec = item->spec;
3612                         nvgre_mask = item->mask;
3613                         /* Check if NVGRE item is used to describe protocol.
3614                          * If yes, both spec and mask should be NULL.
3615                          * If no, both spec and mask shouldn't be NULL.
3616                          */
3617                         if ((!nvgre_spec && nvgre_mask) ||
3618                             (nvgre_spec && !nvgre_mask)) {
3619                                 rte_flow_error_set(error, EINVAL,
3620                                            RTE_FLOW_ERROR_TYPE_ITEM,
3621                                            item,
3622                                            "Invalid NVGRE item");
3623                                 return -rte_errno;
3624                         }
3625
3626                         if (nvgre_spec && nvgre_mask) {
3627                                 is_tni_masked =
3628                                         !!memcmp(nvgre_mask->tni, tni_mask,
3629                                                  RTE_DIM(tni_mask));
3630                                 if (is_tni_masked) {
3631                                         rte_flow_error_set(error, EINVAL,
3632                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3633                                                        item,
3634                                                        "Invalid TNI mask");
3635                                         return -rte_errno;
3636                                 }
3637                                 if (nvgre_mask->protocol &&
3638                                         nvgre_mask->protocol != 0xFFFF) {
3639                                         rte_flow_error_set(error, EINVAL,
3640                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3641                                                 item,
3642                                                 "Invalid NVGRE item");
3643                                         return -rte_errno;
3644                                 }
3645                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3646                                         nvgre_mask->c_k_s_rsvd0_ver !=
3647                                         rte_cpu_to_be_16(0xFFFF)) {
3648                                         rte_flow_error_set(error, EINVAL,
3649                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3650                                                    item,
3651                                                    "Invalid NVGRE item");
3652                                         return -rte_errno;
3653                                 }
3654                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3655                                         rte_cpu_to_be_16(0x2000) &&
3656                                         nvgre_mask->c_k_s_rsvd0_ver) {
3657                                         rte_flow_error_set(error, EINVAL,
3658                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3659                                                    item,
3660                                                    "Invalid NVGRE item");
3661                                         return -rte_errno;
3662                                 }
3663                                 if (nvgre_mask->protocol &&
3664                                         nvgre_spec->protocol !=
3665                                         rte_cpu_to_be_16(0x6558)) {
3666                                         rte_flow_error_set(error, EINVAL,
3667                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3668                                                    item,
3669                                                    "Invalid NVGRE item");
3670                                         return -rte_errno;
3671                                 }
3672                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3673                                            nvgre_spec->tni, 3);
3674                                 filter->tenant_id =
3675                                         rte_be_to_cpu_32(tenant_id_be);
3676                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3677                         }
3678
3679                         nvgre_flag = 1;
3680                         break;
3681                 default:
3682                         break;
3683                 }
3684         }
3685
3686         ret = i40e_check_tunnel_filter_type(filter_type);
3687         if (ret < 0) {
3688                 rte_flow_error_set(error, EINVAL,
3689                                    RTE_FLOW_ERROR_TYPE_ITEM,
3690                                    NULL,
3691                                    "Invalid filter type");
3692                 return -rte_errno;
3693         }
3694         filter->filter_type = filter_type;
3695
3696         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3697
3698         return 0;
3699 }
3700
3701 static int
3702 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3703                              const struct rte_flow_attr *attr,
3704                              const struct rte_flow_item pattern[],
3705                              const struct rte_flow_action actions[],
3706                              struct rte_flow_error *error,
3707                              union i40e_filter_t *filter)
3708 {
3709         struct i40e_tunnel_filter_conf *tunnel_filter =
3710                 &filter->consistent_tunnel_filter;
3711         int ret;
3712
3713         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3714                                             error, tunnel_filter);
3715         if (ret)
3716                 return ret;
3717
3718         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3719         if (ret)
3720                 return ret;
3721
3722         ret = i40e_flow_parse_attr(attr, error);
3723         if (ret)
3724                 return ret;
3725
3726         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3727
3728         return ret;
3729 }
3730
3731 /* 1. Last in item should be NULL as range is not supported.
3732  * 2. Supported filter types: MPLS label.
3733  * 3. Mask of fields which need to be matched should be
3734  *    filled with 1.
3735  * 4. Mask of fields which needn't to be matched should be
3736  *    filled with 0.
3737  */
3738 static int
3739 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3740                              const struct rte_flow_item *pattern,
3741                              struct rte_flow_error *error,
3742                              struct i40e_tunnel_filter_conf *filter)
3743 {
3744         const struct rte_flow_item *item = pattern;
3745         const struct rte_flow_item_mpls *mpls_spec;
3746         const struct rte_flow_item_mpls *mpls_mask;
3747         enum rte_flow_item_type item_type;
3748         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3749         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3750         uint32_t label_be = 0;
3751
3752         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3753                 if (item->last) {
3754                         rte_flow_error_set(error, EINVAL,
3755                                            RTE_FLOW_ERROR_TYPE_ITEM,
3756                                            item,
3757                                            "Not support range");
3758                         return -rte_errno;
3759                 }
3760                 item_type = item->type;
3761                 switch (item_type) {
3762                 case RTE_FLOW_ITEM_TYPE_ETH:
3763                         if (item->spec || item->mask) {
3764                                 rte_flow_error_set(error, EINVAL,
3765                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3766                                                    item,
3767                                                    "Invalid ETH item");
3768                                 return -rte_errno;
3769                         }
3770                         break;
3771                 case RTE_FLOW_ITEM_TYPE_IPV4:
3772                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3773                         /* IPv4 is used to describe protocol,
3774                          * spec and mask should be NULL.
3775                          */
3776                         if (item->spec || item->mask) {
3777                                 rte_flow_error_set(error, EINVAL,
3778                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3779                                                    item,
3780                                                    "Invalid IPv4 item");
3781                                 return -rte_errno;
3782                         }
3783                         break;
3784                 case RTE_FLOW_ITEM_TYPE_IPV6:
3785                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3786                         /* IPv6 is used to describe protocol,
3787                          * spec and mask should be NULL.
3788                          */
3789                         if (item->spec || item->mask) {
3790                                 rte_flow_error_set(error, EINVAL,
3791                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3792                                                    item,
3793                                                    "Invalid IPv6 item");
3794                                 return -rte_errno;
3795                         }
3796                         break;
3797                 case RTE_FLOW_ITEM_TYPE_UDP:
3798                         /* UDP is used to describe protocol,
3799                          * spec and mask should be NULL.
3800                          */
3801                         if (item->spec || item->mask) {
3802                                 rte_flow_error_set(error, EINVAL,
3803                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3804                                                    item,
3805                                                    "Invalid UDP item");
3806                                 return -rte_errno;
3807                         }
3808                         is_mplsoudp = 1;
3809                         break;
3810                 case RTE_FLOW_ITEM_TYPE_GRE:
3811                         /* GRE is used to describe protocol,
3812                          * spec and mask should be NULL.
3813                          */
3814                         if (item->spec || item->mask) {
3815                                 rte_flow_error_set(error, EINVAL,
3816                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3817                                                    item,
3818                                                    "Invalid GRE item");
3819                                 return -rte_errno;
3820                         }
3821                         break;
3822                 case RTE_FLOW_ITEM_TYPE_MPLS:
3823                         mpls_spec = item->spec;
3824                         mpls_mask = item->mask;
3825
3826                         if (!mpls_spec || !mpls_mask) {
3827                                 rte_flow_error_set(error, EINVAL,
3828                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3829                                                    item,
3830                                                    "Invalid MPLS item");
3831                                 return -rte_errno;
3832                         }
3833
3834                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3835                                 rte_flow_error_set(error, EINVAL,
3836                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3837                                                    item,
3838                                                    "Invalid MPLS label mask");
3839                                 return -rte_errno;
3840                         }
3841                         rte_memcpy(((uint8_t *)&label_be + 1),
3842                                    mpls_spec->label_tc_s, 3);
3843                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3844                         break;
3845                 default:
3846                         break;
3847                 }
3848         }
3849
3850         if (is_mplsoudp)
3851                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3852         else
3853                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3854
3855         return 0;
3856 }
3857
3858 static int
3859 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3860                             const struct rte_flow_attr *attr,
3861                             const struct rte_flow_item pattern[],
3862                             const struct rte_flow_action actions[],
3863                             struct rte_flow_error *error,
3864                             union i40e_filter_t *filter)
3865 {
3866         struct i40e_tunnel_filter_conf *tunnel_filter =
3867                 &filter->consistent_tunnel_filter;
3868         int ret;
3869
3870         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3871                                            error, tunnel_filter);
3872         if (ret)
3873                 return ret;
3874
3875         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3876         if (ret)
3877                 return ret;
3878
3879         ret = i40e_flow_parse_attr(attr, error);
3880         if (ret)
3881                 return ret;
3882
3883         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3884
3885         return ret;
3886 }
3887
3888 /* 1. Last in item should be NULL as range is not supported.
3889  * 2. Supported filter types: GTP TEID.
3890  * 3. Mask of fields which need to be matched should be
3891  *    filled with 1.
3892  * 4. Mask of fields which needn't to be matched should be
3893  *    filled with 0.
3894  * 5. GTP profile supports GTPv1 only.
3895  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3896  */
3897 static int
3898 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3899                             const struct rte_flow_item *pattern,
3900                             struct rte_flow_error *error,
3901                             struct i40e_tunnel_filter_conf *filter)
3902 {
3903         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3904         const struct rte_flow_item *item = pattern;
3905         const struct rte_flow_item_gtp *gtp_spec;
3906         const struct rte_flow_item_gtp *gtp_mask;
3907         enum rte_flow_item_type item_type;
3908
3909         if (!pf->gtp_support) {
3910                 rte_flow_error_set(error, EINVAL,
3911                                    RTE_FLOW_ERROR_TYPE_ITEM,
3912                                    item,
3913                                    "GTP is not supported by default.");
3914                 return -rte_errno;
3915         }
3916
3917         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3918                 if (item->last) {
3919                         rte_flow_error_set(error, EINVAL,
3920                                            RTE_FLOW_ERROR_TYPE_ITEM,
3921                                            item,
3922                                            "Not support range");
3923                         return -rte_errno;
3924                 }
3925                 item_type = item->type;
3926                 switch (item_type) {
3927                 case RTE_FLOW_ITEM_TYPE_ETH:
3928                         if (item->spec || item->mask) {
3929                                 rte_flow_error_set(error, EINVAL,
3930                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3931                                                    item,
3932                                                    "Invalid ETH item");
3933                                 return -rte_errno;
3934                         }
3935                         break;
3936                 case RTE_FLOW_ITEM_TYPE_IPV4:
3937                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3938                         /* IPv4 is used to describe protocol,
3939                          * spec and mask should be NULL.
3940                          */
3941                         if (item->spec || item->mask) {
3942                                 rte_flow_error_set(error, EINVAL,
3943                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3944                                                    item,
3945                                                    "Invalid IPv4 item");
3946                                 return -rte_errno;
3947                         }
3948                         break;
3949                 case RTE_FLOW_ITEM_TYPE_UDP:
3950                         if (item->spec || item->mask) {
3951                                 rte_flow_error_set(error, EINVAL,
3952                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3953                                                    item,
3954                                                    "Invalid UDP item");
3955                                 return -rte_errno;
3956                         }
3957                         break;
3958                 case RTE_FLOW_ITEM_TYPE_GTPC:
3959                 case RTE_FLOW_ITEM_TYPE_GTPU:
3960                         gtp_spec = item->spec;
3961                         gtp_mask = item->mask;
3962
3963                         if (!gtp_spec || !gtp_mask) {
3964                                 rte_flow_error_set(error, EINVAL,
3965                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3966                                                    item,
3967                                                    "Invalid GTP item");
3968                                 return -rte_errno;
3969                         }
3970
3971                         if (gtp_mask->v_pt_rsv_flags ||
3972                             gtp_mask->msg_type ||
3973                             gtp_mask->msg_len ||
3974                             gtp_mask->teid != UINT32_MAX) {
3975                                 rte_flow_error_set(error, EINVAL,
3976                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3977                                                    item,
3978                                                    "Invalid GTP mask");
3979                                 return -rte_errno;
3980                         }
3981
3982                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3983                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3984                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3985                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3986
3987                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3988
3989                         break;
3990                 default:
3991                         break;
3992                 }
3993         }
3994
3995         return 0;
3996 }
3997
3998 static int
3999 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4000                            const struct rte_flow_attr *attr,
4001                            const struct rte_flow_item pattern[],
4002                            const struct rte_flow_action actions[],
4003                            struct rte_flow_error *error,
4004                            union i40e_filter_t *filter)
4005 {
4006         struct i40e_tunnel_filter_conf *tunnel_filter =
4007                 &filter->consistent_tunnel_filter;
4008         int ret;
4009
4010         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4011                                           error, tunnel_filter);
4012         if (ret)
4013                 return ret;
4014
4015         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4016         if (ret)
4017                 return ret;
4018
4019         ret = i40e_flow_parse_attr(attr, error);
4020         if (ret)
4021                 return ret;
4022
4023         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4024
4025         return ret;
4026 }
4027
4028 /* 1. Last in item should be NULL as range is not supported.
4029  * 2. Supported filter types: QINQ.
4030  * 3. Mask of fields which need to be matched should be
4031  *    filled with 1.
4032  * 4. Mask of fields which needn't to be matched should be
4033  *    filled with 0.
4034  */
4035 static int
4036 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4037                               const struct rte_flow_item *pattern,
4038                               struct rte_flow_error *error,
4039                               struct i40e_tunnel_filter_conf *filter)
4040 {
4041         const struct rte_flow_item *item = pattern;
4042         const struct rte_flow_item_vlan *vlan_spec = NULL;
4043         const struct rte_flow_item_vlan *vlan_mask = NULL;
4044         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4045         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4046         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4047         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4048
4049         enum rte_flow_item_type item_type;
4050         bool vlan_flag = 0;
4051
4052         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4053                 if (item->last) {
4054                         rte_flow_error_set(error, EINVAL,
4055                                            RTE_FLOW_ERROR_TYPE_ITEM,
4056                                            item,
4057                                            "Not support range");
4058                         return -rte_errno;
4059                 }
4060                 item_type = item->type;
4061                 switch (item_type) {
4062                 case RTE_FLOW_ITEM_TYPE_ETH:
4063                         if (item->spec || item->mask) {
4064                                 rte_flow_error_set(error, EINVAL,
4065                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4066                                                    item,
4067                                                    "Invalid ETH item");
4068                                 return -rte_errno;
4069                         }
4070                         break;
4071                 case RTE_FLOW_ITEM_TYPE_VLAN:
4072                         vlan_spec = item->spec;
4073                         vlan_mask = item->mask;
4074
4075                         if (!(vlan_spec && vlan_mask) ||
4076                             vlan_mask->inner_type) {
4077                                 rte_flow_error_set(error, EINVAL,
4078                                            RTE_FLOW_ERROR_TYPE_ITEM,
4079                                            item,
4080                                            "Invalid vlan item");
4081                                 return -rte_errno;
4082                         }
4083
4084                         if (!vlan_flag) {
4085                                 o_vlan_spec = vlan_spec;
4086                                 o_vlan_mask = vlan_mask;
4087                                 vlan_flag = 1;
4088                         } else {
4089                                 i_vlan_spec = vlan_spec;
4090                                 i_vlan_mask = vlan_mask;
4091                                 vlan_flag = 0;
4092                         }
4093                         break;
4094
4095                 default:
4096                         break;
4097                 }
4098         }
4099
4100         /* Get filter specification */
4101         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4102                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4103                         (i_vlan_mask != NULL) &&
4104                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4105                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4106                         & I40E_TCI_MASK;
4107                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4108                         & I40E_TCI_MASK;
4109         } else {
4110                         rte_flow_error_set(error, EINVAL,
4111                                            RTE_FLOW_ERROR_TYPE_ITEM,
4112                                            NULL,
4113                                            "Invalid filter type");
4114                         return -rte_errno;
4115         }
4116
4117         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4118         return 0;
4119 }
4120
4121 static int
4122 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4123                               const struct rte_flow_attr *attr,
4124                               const struct rte_flow_item pattern[],
4125                               const struct rte_flow_action actions[],
4126                               struct rte_flow_error *error,
4127                               union i40e_filter_t *filter)
4128 {
4129         struct i40e_tunnel_filter_conf *tunnel_filter =
4130                 &filter->consistent_tunnel_filter;
4131         int ret;
4132
4133         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4134                                              error, tunnel_filter);
4135         if (ret)
4136                 return ret;
4137
4138         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4139         if (ret)
4140                 return ret;
4141
4142         ret = i40e_flow_parse_attr(attr, error);
4143         if (ret)
4144                 return ret;
4145
4146         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4147
4148         return ret;
4149 }
4150
4151 /**
4152  * This function is used to do configuration i40e existing RSS with rte_flow.
4153  * It also enable queue region configuration using flow API for i40e.
4154  * pattern can be used indicate what parameters will be include in flow,
4155  * like user_priority or flowtype for queue region or HASH function for RSS.
4156  * Action is used to transmit parameter like queue index and HASH
4157  * function for RSS, or flowtype for queue region configuration.
4158  * For example:
4159  * pattern:
4160  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4161  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4162  * Case 3: none, indicate RSS related will be parsed in action.
4163  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4164  * So, pattern choice is depened on the purpose of configuration of
4165  * that flow.
4166  * action:
4167  * action RSS will be uaed to transmit valid parameter with
4168  * struct rte_flow_action_rss for all the 3 case.
4169  */
4170 static int
4171 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4172                              const struct rte_flow_item *pattern,
4173                              struct rte_flow_error *error,
4174                              uint8_t *action_flag,
4175                              struct i40e_queue_regions *info)
4176 {
4177         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4178         const struct rte_flow_item *item = pattern;
4179         enum rte_flow_item_type item_type;
4180
4181         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4182                 return 0;
4183
4184         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4185                 if (item->last) {
4186                         rte_flow_error_set(error, EINVAL,
4187                                            RTE_FLOW_ERROR_TYPE_ITEM,
4188                                            item,
4189                                            "Not support range");
4190                         return -rte_errno;
4191                 }
4192                 item_type = item->type;
4193                 switch (item_type) {
4194                 case RTE_FLOW_ITEM_TYPE_ETH:
4195                         *action_flag = 1;
4196                         break;
4197                 case RTE_FLOW_ITEM_TYPE_VLAN:
4198                         vlan_spec = item->spec;
4199                         vlan_mask = item->mask;
4200                         if (vlan_spec && vlan_mask) {
4201                                 if (vlan_mask->tci ==
4202                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4203                                         info->region[0].user_priority[0] =
4204                                                 (rte_be_to_cpu_16(
4205                                                 vlan_spec->tci) >> 13) & 0x7;
4206                                         info->region[0].user_priority_num = 1;
4207                                         info->queue_region_number = 1;
4208                                         *action_flag = 0;
4209                                 }
4210                         }
4211                         break;
4212                 default:
4213                         rte_flow_error_set(error, EINVAL,
4214                                         RTE_FLOW_ERROR_TYPE_ITEM,
4215                                         item,
4216                                         "Not support range");
4217                         return -rte_errno;
4218                 }
4219         }
4220
4221         return 0;
4222 }
4223
4224 /**
4225  * This function is used to parse rss queue index, total queue number and
4226  * hash functions, If the purpose of this configuration is for queue region
4227  * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4228  * In queue region configuration, it also need to parse hardware flowtype
4229  * and user_priority from configuration, it will also cheeck the validity
4230  * of these parameters. For example, The queue region sizes should
4231  * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4232  * hw_flowtype or PCTYPE max index should be 63, the user priority
4233  * max index should be 7, and so on. And also, queue index should be
4234  * continuous sequence and queue region index should be part of rss
4235  * queue index for this port.
4236  */
4237 static int
4238 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4239                             const struct rte_flow_action *actions,
4240                             struct rte_flow_error *error,
4241                             uint8_t action_flag,
4242                             struct i40e_queue_regions *conf_info,
4243                             union i40e_filter_t *filter)
4244 {
4245         const struct rte_flow_action *act;
4246         const struct rte_flow_action_rss *rss;
4247         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4248         struct i40e_queue_regions *info = &pf->queue_region;
4249         struct i40e_rte_flow_rss_conf *rss_config =
4250                         &filter->rss_conf;
4251         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4252         uint16_t i, j, n, tmp;
4253         uint32_t index = 0;
4254         uint64_t hf_bit = 1;
4255
4256         NEXT_ITEM_OF_ACTION(act, actions, index);
4257         rss = act->conf;
4258
4259         /**
4260          * rss only supports forwarding,
4261          * check if the first not void action is RSS.
4262          */
4263         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4264                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4265                 rte_flow_error_set(error, EINVAL,
4266                         RTE_FLOW_ERROR_TYPE_ACTION,
4267                         act, "Not supported action.");
4268                 return -rte_errno;
4269         }
4270
4271         if (action_flag) {
4272                 for (n = 0; n < 64; n++) {
4273                         if (rss->types & (hf_bit << n)) {
4274                                 conf_info->region[0].hw_flowtype[0] = n;
4275                                 conf_info->region[0].flowtype_num = 1;
4276                                 conf_info->queue_region_number = 1;
4277                                 break;
4278                         }
4279                 }
4280         }
4281
4282         /**
4283          * Do some queue region related parameters check
4284          * in order to keep queue index for queue region to be
4285          * continuous sequence and also to be part of RSS
4286          * queue index for this port.
4287          */
4288         if (conf_info->queue_region_number) {
4289                 for (i = 0; i < rss->queue_num; i++) {
4290                         for (j = 0; j < rss_info->conf.queue_num; j++) {
4291                                 if (rss->queue[i] == rss_info->conf.queue[j])
4292                                         break;
4293                         }
4294                         if (j == rss_info->conf.queue_num) {
4295                                 rte_flow_error_set(error, EINVAL,
4296                                         RTE_FLOW_ERROR_TYPE_ACTION,
4297                                         act,
4298                                         "no valid queues");
4299                                 return -rte_errno;
4300                         }
4301                 }
4302
4303                 for (i = 0; i < rss->queue_num - 1; i++) {
4304                         if (rss->queue[i + 1] != rss->queue[i] + 1) {
4305                                 rte_flow_error_set(error, EINVAL,
4306                                         RTE_FLOW_ERROR_TYPE_ACTION,
4307                                         act,
4308                                         "no valid queues");
4309                                 return -rte_errno;
4310                         }
4311                 }
4312         }
4313
4314         /* Parse queue region related parameters from configuration */
4315         for (n = 0; n < conf_info->queue_region_number; n++) {
4316                 if (conf_info->region[n].user_priority_num ||
4317                                 conf_info->region[n].flowtype_num) {
4318                         if (!((rte_is_power_of_2(rss->queue_num)) &&
4319                                         rss->queue_num <= 64)) {
4320                                 rte_flow_error_set(error, EINVAL,
4321                                         RTE_FLOW_ERROR_TYPE_ACTION,
4322                                         act,
4323                                         "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4324                                         "total number of queues do not exceed the VSI allocation");
4325                                 return -rte_errno;
4326                         }
4327
4328                         if (conf_info->region[n].user_priority[n] >=
4329                                         I40E_MAX_USER_PRIORITY) {
4330                                 rte_flow_error_set(error, EINVAL,
4331                                         RTE_FLOW_ERROR_TYPE_ACTION,
4332                                         act,
4333                                         "the user priority max index is 7");
4334                                 return -rte_errno;
4335                         }
4336
4337                         if (conf_info->region[n].hw_flowtype[n] >=
4338                                         I40E_FILTER_PCTYPE_MAX) {
4339                                 rte_flow_error_set(error, EINVAL,
4340                                         RTE_FLOW_ERROR_TYPE_ACTION,
4341                                         act,
4342                                         "the hw_flowtype or PCTYPE max index is 63");
4343                                 return -rte_errno;
4344                         }
4345
4346                         for (i = 0; i < info->queue_region_number; i++) {
4347                                 if (info->region[i].queue_num ==
4348                                     rss->queue_num &&
4349                                         info->region[i].queue_start_index ==
4350                                                 rss->queue[0])
4351                                         break;
4352                         }
4353
4354                         if (i == info->queue_region_number) {
4355                                 if (i > I40E_REGION_MAX_INDEX) {
4356                                         rte_flow_error_set(error, EINVAL,
4357                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4358                                                 act,
4359                                                 "the queue region max index is 7");
4360                                         return -rte_errno;
4361                                 }
4362
4363                                 info->region[i].queue_num =
4364                                         rss->queue_num;
4365                                 info->region[i].queue_start_index =
4366                                         rss->queue[0];
4367                                 info->region[i].region_id =
4368                                         info->queue_region_number;
4369
4370                                 j = info->region[i].user_priority_num;
4371                                 tmp = conf_info->region[n].user_priority[0];
4372                                 if (conf_info->region[n].user_priority_num) {
4373                                         info->region[i].user_priority[j] = tmp;
4374                                         info->region[i].user_priority_num++;
4375                                 }
4376
4377                                 j = info->region[i].flowtype_num;
4378                                 tmp = conf_info->region[n].hw_flowtype[0];
4379                                 if (conf_info->region[n].flowtype_num) {
4380                                         info->region[i].hw_flowtype[j] = tmp;
4381                                         info->region[i].flowtype_num++;
4382                                 }
4383                                 info->queue_region_number++;
4384                         } else {
4385                                 j = info->region[i].user_priority_num;
4386                                 tmp = conf_info->region[n].user_priority[0];
4387                                 if (conf_info->region[n].user_priority_num) {
4388                                         info->region[i].user_priority[j] = tmp;
4389                                         info->region[i].user_priority_num++;
4390                                 }
4391
4392                                 j = info->region[i].flowtype_num;
4393                                 tmp = conf_info->region[n].hw_flowtype[0];
4394                                 if (conf_info->region[n].flowtype_num) {
4395                                         info->region[i].hw_flowtype[j] = tmp;
4396                                         info->region[i].flowtype_num++;
4397                                 }
4398                         }
4399                 }
4400
4401                 rss_config->queue_region_conf = TRUE;
4402         }
4403
4404         /**
4405          * Return function if this flow is used for queue region configuration
4406          */
4407         if (rss_config->queue_region_conf)
4408                 return 0;
4409
4410         if (!rss || !rss->queue_num) {
4411                 rte_flow_error_set(error, EINVAL,
4412                                 RTE_FLOW_ERROR_TYPE_ACTION,
4413                                 act,
4414                                 "no valid queues");
4415                 return -rte_errno;
4416         }
4417
4418         for (n = 0; n < rss->queue_num; n++) {
4419                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4420                         rte_flow_error_set(error, EINVAL,
4421                                    RTE_FLOW_ERROR_TYPE_ACTION,
4422                                    act,
4423                                    "queue id > max number of queues");
4424                         return -rte_errno;
4425                 }
4426         }
4427
4428         /* Parse RSS related parameters from configuration */
4429         if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4430                 return rte_flow_error_set
4431                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4432                          "non-default RSS hash functions are not supported");
4433         if (rss->level)
4434                 return rte_flow_error_set
4435                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4436                          "a nonzero RSS encapsulation level is not supported");
4437         if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4438                 return rte_flow_error_set
4439                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4440                          "RSS hash key too large");
4441         if (rss->queue_num > RTE_DIM(rss_config->queue))
4442                 return rte_flow_error_set
4443                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4444                          "too many queues for RSS context");
4445         if (i40e_rss_conf_init(rss_config, rss))
4446                 return rte_flow_error_set
4447                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4448                          "RSS context initialization failure");
4449
4450         index++;
4451
4452         /* check if the next not void action is END */
4453         NEXT_ITEM_OF_ACTION(act, actions, index);
4454         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4455                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4456                 rte_flow_error_set(error, EINVAL,
4457                         RTE_FLOW_ERROR_TYPE_ACTION,
4458                         act, "Not supported action.");
4459                 return -rte_errno;
4460         }
4461         rss_config->queue_region_conf = FALSE;
4462
4463         return 0;
4464 }
4465
4466 static int
4467 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4468                         const struct rte_flow_attr *attr,
4469                         const struct rte_flow_item pattern[],
4470                         const struct rte_flow_action actions[],
4471                         union i40e_filter_t *filter,
4472                         struct rte_flow_error *error)
4473 {
4474         int ret;
4475         struct i40e_queue_regions info;
4476         uint8_t action_flag = 0;
4477
4478         memset(&info, 0, sizeof(struct i40e_queue_regions));
4479
4480         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4481                                         error, &action_flag, &info);
4482         if (ret)
4483                 return ret;
4484
4485         ret = i40e_flow_parse_rss_action(dev, actions, error,
4486                                         action_flag, &info, filter);
4487         if (ret)
4488                 return ret;
4489
4490         ret = i40e_flow_parse_attr(attr, error);
4491         if (ret)
4492                 return ret;
4493
4494         cons_filter_type = RTE_ETH_FILTER_HASH;
4495
4496         return 0;
4497 }
4498
4499 static int
4500 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4501                 struct i40e_rte_flow_rss_conf *conf)
4502 {
4503         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4504         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         int ret;
4506
4507         if (conf->queue_region_conf) {
4508                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4509                 conf->queue_region_conf = 0;
4510         } else {
4511                 ret = i40e_config_rss_filter(pf, conf, 1);
4512         }
4513         return ret;
4514 }
4515
4516 static int
4517 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4518                 struct i40e_rte_flow_rss_conf *conf)
4519 {
4520         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4521         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4522
4523         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4524
4525         i40e_config_rss_filter(pf, conf, 0);
4526         return 0;
4527 }
4528
4529 static int
4530 i40e_flow_validate(struct rte_eth_dev *dev,
4531                    const struct rte_flow_attr *attr,
4532                    const struct rte_flow_item pattern[],
4533                    const struct rte_flow_action actions[],
4534                    struct rte_flow_error *error)
4535 {
4536         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4537         parse_filter_t parse_filter;
4538         uint32_t item_num = 0; /* non-void item number of pattern*/
4539         uint32_t i = 0;
4540         bool flag = false;
4541         int ret = I40E_NOT_SUPPORTED;
4542
4543         if (!pattern) {
4544                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4545                                    NULL, "NULL pattern.");
4546                 return -rte_errno;
4547         }
4548
4549         if (!actions) {
4550                 rte_flow_error_set(error, EINVAL,
4551                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4552                                    NULL, "NULL action.");
4553                 return -rte_errno;
4554         }
4555
4556         if (!attr) {
4557                 rte_flow_error_set(error, EINVAL,
4558                                    RTE_FLOW_ERROR_TYPE_ATTR,
4559                                    NULL, "NULL attribute.");
4560                 return -rte_errno;
4561         }
4562
4563         memset(&cons_filter, 0, sizeof(cons_filter));
4564
4565         /* Get the non-void item of action */
4566         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4567                 i++;
4568
4569         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4570                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4571                                         actions, &cons_filter, error);
4572                 return ret;
4573         }
4574
4575         i = 0;
4576         /* Get the non-void item number of pattern */
4577         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4578                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4579                         item_num++;
4580                 i++;
4581         }
4582         item_num++;
4583
4584         items = rte_zmalloc("i40e_pattern",
4585                             item_num * sizeof(struct rte_flow_item), 0);
4586         if (!items) {
4587                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4588                                    NULL, "No memory for PMD internal items.");
4589                 return -ENOMEM;
4590         }
4591
4592         i40e_pattern_skip_void_item(items, pattern);
4593
4594         i = 0;
4595         do {
4596                 parse_filter = i40e_find_parse_filter_func(items, &i);
4597                 if (!parse_filter && !flag) {
4598                         rte_flow_error_set(error, EINVAL,
4599                                            RTE_FLOW_ERROR_TYPE_ITEM,
4600                                            pattern, "Unsupported pattern");
4601                         rte_free(items);
4602                         return -rte_errno;
4603                 }
4604                 if (parse_filter)
4605                         ret = parse_filter(dev, attr, items, actions,
4606                                            error, &cons_filter);
4607                 flag = true;
4608         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4609
4610         rte_free(items);
4611
4612         return ret;
4613 }
4614
4615 static struct rte_flow *
4616 i40e_flow_create(struct rte_eth_dev *dev,
4617                  const struct rte_flow_attr *attr,
4618                  const struct rte_flow_item pattern[],
4619                  const struct rte_flow_action actions[],
4620                  struct rte_flow_error *error)
4621 {
4622         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4623         struct rte_flow *flow;
4624         int ret;
4625
4626         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4627         if (!flow) {
4628                 rte_flow_error_set(error, ENOMEM,
4629                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4630                                    "Failed to allocate memory");
4631                 return flow;
4632         }
4633
4634         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4635         if (ret < 0)
4636                 return NULL;
4637
4638         switch (cons_filter_type) {
4639         case RTE_ETH_FILTER_ETHERTYPE:
4640                 ret = i40e_ethertype_filter_set(pf,
4641                                         &cons_filter.ethertype_filter, 1);
4642                 if (ret)
4643                         goto free_flow;
4644                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4645                                         i40e_ethertype_filter_list);
4646                 break;
4647         case RTE_ETH_FILTER_FDIR:
4648                 ret = i40e_flow_add_del_fdir_filter(dev,
4649                                        &cons_filter.fdir_filter, 1);
4650                 if (ret)
4651                         goto free_flow;
4652                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4653                                         i40e_fdir_filter_list);
4654                 break;
4655         case RTE_ETH_FILTER_TUNNEL:
4656                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4657                             &cons_filter.consistent_tunnel_filter, 1);
4658                 if (ret)
4659                         goto free_flow;
4660                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4661                                         i40e_tunnel_filter_list);
4662                 break;
4663         case RTE_ETH_FILTER_HASH:
4664                 ret = i40e_config_rss_filter_set(dev,
4665                             &cons_filter.rss_conf);
4666                 if (ret)
4667                         goto free_flow;
4668                 flow->rule = &pf->rss_info;
4669                 break;
4670         default:
4671                 goto free_flow;
4672         }
4673
4674         flow->filter_type = cons_filter_type;
4675         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4676         return flow;
4677
4678 free_flow:
4679         rte_flow_error_set(error, -ret,
4680                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4681                            "Failed to create flow.");
4682         rte_free(flow);
4683         return NULL;
4684 }
4685
4686 static int
4687 i40e_flow_destroy(struct rte_eth_dev *dev,
4688                   struct rte_flow *flow,
4689                   struct rte_flow_error *error)
4690 {
4691         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4692         enum rte_filter_type filter_type = flow->filter_type;
4693         int ret = 0;
4694
4695         switch (filter_type) {
4696         case RTE_ETH_FILTER_ETHERTYPE:
4697                 ret = i40e_flow_destroy_ethertype_filter(pf,
4698                          (struct i40e_ethertype_filter *)flow->rule);
4699                 break;
4700         case RTE_ETH_FILTER_TUNNEL:
4701                 ret = i40e_flow_destroy_tunnel_filter(pf,
4702                               (struct i40e_tunnel_filter *)flow->rule);
4703                 break;
4704         case RTE_ETH_FILTER_FDIR:
4705                 ret = i40e_flow_add_del_fdir_filter(dev,
4706                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4707                 break;
4708         case RTE_ETH_FILTER_HASH:
4709                 ret = i40e_config_rss_filter_del(dev,
4710                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4711                 break;
4712         default:
4713                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4714                             filter_type);
4715                 ret = -EINVAL;
4716                 break;
4717         }
4718
4719         if (!ret) {
4720                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4721                 rte_free(flow);
4722         } else
4723                 rte_flow_error_set(error, -ret,
4724                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4725                                    "Failed to destroy flow.");
4726
4727         return ret;
4728 }
4729
4730 static int
4731 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4732                                    struct i40e_ethertype_filter *filter)
4733 {
4734         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4735         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4736         struct i40e_ethertype_filter *node;
4737         struct i40e_control_filter_stats stats;
4738         uint16_t flags = 0;
4739         int ret = 0;
4740
4741         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4742                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4743         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4744                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4745         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4746
4747         memset(&stats, 0, sizeof(stats));
4748         ret = i40e_aq_add_rem_control_packet_filter(hw,
4749                                     filter->input.mac_addr.addr_bytes,
4750                                     filter->input.ether_type,
4751                                     flags, pf->main_vsi->seid,
4752                                     filter->queue, 0, &stats, NULL);
4753         if (ret < 0)
4754                 return ret;
4755
4756         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4757         if (!node)
4758                 return -EINVAL;
4759
4760         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4761
4762         return ret;
4763 }
4764
4765 static int
4766 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4767                                 struct i40e_tunnel_filter *filter)
4768 {
4769         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4770         struct i40e_vsi *vsi;
4771         struct i40e_pf_vf *vf;
4772         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4773         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4774         struct i40e_tunnel_filter *node;
4775         bool big_buffer = 0;
4776         int ret = 0;
4777
4778         memset(&cld_filter, 0, sizeof(cld_filter));
4779         ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4780                         (struct ether_addr *)&cld_filter.element.outer_mac);
4781         ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4782                         (struct ether_addr *)&cld_filter.element.inner_mac);
4783         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4784         cld_filter.element.flags = filter->input.flags;
4785         cld_filter.element.tenant_id = filter->input.tenant_id;
4786         cld_filter.element.queue_number = filter->queue;
4787         rte_memcpy(cld_filter.general_fields,
4788                    filter->input.general_fields,
4789                    sizeof(cld_filter.general_fields));
4790
4791         if (!filter->is_to_vf)
4792                 vsi = pf->main_vsi;
4793         else {
4794                 vf = &pf->vfs[filter->vf_id];
4795                 vsi = vf->vsi;
4796         }
4797
4798         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4799             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4800             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4801             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4802             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4803             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4804                 big_buffer = 1;
4805
4806         if (big_buffer)
4807                 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4808                                                               &cld_filter, 1);
4809         else
4810                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4811                                                    &cld_filter.element, 1);
4812         if (ret < 0)
4813                 return -ENOTSUP;
4814
4815         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4816         if (!node)
4817                 return -EINVAL;
4818
4819         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4820
4821         return ret;
4822 }
4823
4824 static int
4825 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4826 {
4827         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4828         int ret;
4829
4830         ret = i40e_flow_flush_fdir_filter(pf);
4831         if (ret) {
4832                 rte_flow_error_set(error, -ret,
4833                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4834                                    "Failed to flush FDIR flows.");
4835                 return -rte_errno;
4836         }
4837
4838         ret = i40e_flow_flush_ethertype_filter(pf);
4839         if (ret) {
4840                 rte_flow_error_set(error, -ret,
4841                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4842                                    "Failed to ethertype flush flows.");
4843                 return -rte_errno;
4844         }
4845
4846         ret = i40e_flow_flush_tunnel_filter(pf);
4847         if (ret) {
4848                 rte_flow_error_set(error, -ret,
4849                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4850                                    "Failed to flush tunnel flows.");
4851                 return -rte_errno;
4852         }
4853
4854         ret = i40e_flow_flush_rss_filter(dev);
4855         if (ret) {
4856                 rte_flow_error_set(error, -ret,
4857                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4858                                    "Failed to flush rss flows.");
4859                 return -rte_errno;
4860         }
4861
4862         return ret;
4863 }
4864
4865 static int
4866 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4867 {
4868         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4869         struct i40e_fdir_info *fdir_info = &pf->fdir;
4870         struct i40e_fdir_filter *fdir_filter;
4871         enum i40e_filter_pctype pctype;
4872         struct rte_flow *flow;
4873         void *temp;
4874         int ret;
4875
4876         ret = i40e_fdir_flush(dev);
4877         if (!ret) {
4878                 /* Delete FDIR filters in FDIR list. */
4879                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4880                         ret = i40e_sw_fdir_filter_del(pf,
4881                                                       &fdir_filter->fdir.input);
4882                         if (ret < 0)
4883                                 return ret;
4884                 }
4885
4886                 /* Delete FDIR flows in flow list. */
4887                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4888                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4889                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4890                                 rte_free(flow);
4891                         }
4892                 }
4893
4894                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4895                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4896                         pf->fdir.inset_flag[pctype] = 0;
4897         }
4898
4899         return ret;
4900 }
4901
4902 /* Flush all ethertype filters */
4903 static int
4904 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4905 {
4906         struct i40e_ethertype_filter_list
4907                 *ethertype_list = &pf->ethertype.ethertype_list;
4908         struct i40e_ethertype_filter *filter;
4909         struct rte_flow *flow;
4910         void *temp;
4911         int ret = 0;
4912
4913         while ((filter = TAILQ_FIRST(ethertype_list))) {
4914                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4915                 if (ret)
4916                         return ret;
4917         }
4918
4919         /* Delete ethertype flows in flow list. */
4920         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4921                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4922                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4923                         rte_free(flow);
4924                 }
4925         }
4926
4927         return ret;
4928 }
4929
4930 /* Flush all tunnel filters */
4931 static int
4932 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4933 {
4934         struct i40e_tunnel_filter_list
4935                 *tunnel_list = &pf->tunnel.tunnel_list;
4936         struct i40e_tunnel_filter *filter;
4937         struct rte_flow *flow;
4938         void *temp;
4939         int ret = 0;
4940
4941         while ((filter = TAILQ_FIRST(tunnel_list))) {
4942                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4943                 if (ret)
4944                         return ret;
4945         }
4946
4947         /* Delete tunnel flows in flow list. */
4948         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4949                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4950                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4951                         rte_free(flow);
4952                 }
4953         }
4954
4955         return ret;
4956 }
4957
4958 /* remove the rss filter */
4959 static int
4960 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4961 {
4962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4963         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4964         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965         int32_t ret = -EINVAL;
4966
4967         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4968
4969         if (rss_info->conf.queue_num)
4970                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
4971         return ret;
4972 }