drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_debug.h>
  14 #include <rte_ether.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_log.h>
  17 #include <rte_malloc.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20 #include <rte_bitmap.h>
  21
  22 #include "i40e_logs.h"
  23 #include "base/i40e_type.h"
  24 #include "base/i40e_prototype.h"
  25 #include "i40e_ethdev.h"
  26
  27 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  28 #define I40E_IPV6_FRAG_HEADER   44
  29 #define I40E_TENANT_ARRAY_NUM   3
  30 #define I40E_VLAN_TCI_MASK      0xFFFF
  31 #define I40E_VLAN_PRI_MASK      0xE000
  32 #define I40E_VLAN_CFI_MASK      0x1000
  33 #define I40E_VLAN_VID_MASK      0x0FFF
  34
  35 static int i40e_flow_validate(struct rte_eth_dev *dev,
  36                               const struct rte_flow_attr *attr,
  37                               const struct rte_flow_item pattern[],
  38                               const struct rte_flow_action actions[],
  39                               struct rte_flow_error *error);
  40 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  41                                          const struct rte_flow_attr *attr,
  42                                          const struct rte_flow_item pattern[],
  43                                          const struct rte_flow_action actions[],
  44                                          struct rte_flow_error *error);
  45 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  46                              struct rte_flow *flow,
  47                              struct rte_flow_error *error);
  48 static int i40e_flow_flush(struct rte_eth_dev *dev,
  49                            struct rte_flow_error *error);
  50 static int i40e_flow_query(struct rte_eth_dev *dev,
  51                            struct rte_flow *flow,
  52                            const struct rte_flow_action *actions,
  53                            void *data, struct rte_flow_error *error);
  54 static int
  55 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  56                                   const struct rte_flow_item *pattern,
  57                                   struct rte_flow_error *error,
  58                                   struct rte_eth_ethertype_filter *filter);
  59 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  60                                     const struct rte_flow_action *actions,
  61                                     struct rte_flow_error *error,
  62                                     struct rte_eth_ethertype_filter *filter);
  63 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  64                                         const struct rte_flow_attr *attr,
  65                                         const struct rte_flow_item *pattern,
  66                                         struct rte_flow_error *error,
  67                                         struct i40e_fdir_filter_conf *filter);
  68 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  69                                        const struct rte_flow_action *actions,
  70                                        struct rte_flow_error *error,
  71                                        struct i40e_fdir_filter_conf *filter);
  72 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  73                                  const struct rte_flow_action *actions,
  74                                  struct rte_flow_error *error,
  75                                  struct i40e_tunnel_filter_conf *filter);
  76 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  77                                 struct rte_flow_error *error);
  78 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  79                                     const struct rte_flow_attr *attr,
  80                                     const struct rte_flow_item pattern[],
  81                                     const struct rte_flow_action actions[],
  82                                     struct rte_flow_error *error,
  83                                     union i40e_filter_t *filter);
  84 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  85                                        const struct rte_flow_attr *attr,
  86                                        const struct rte_flow_item pattern[],
  87                                        const struct rte_flow_action actions[],
  88                                        struct rte_flow_error *error,
  89                                        union i40e_filter_t *filter);
  90 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  91                                         const struct rte_flow_attr *attr,
  92                                         const struct rte_flow_item pattern[],
  93                                         const struct rte_flow_action actions[],
  94                                         struct rte_flow_error *error,
  95                                         union i40e_filter_t *filter);
  96 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  97                                         const struct rte_flow_attr *attr,
  98                                         const struct rte_flow_item pattern[],
  99                                         const struct rte_flow_action actions[],
 100                                         struct rte_flow_error *error,
 101                                         union i40e_filter_t *filter);
 102 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
 103                                        const struct rte_flow_attr *attr,
 104                                        const struct rte_flow_item pattern[],
 105                                        const struct rte_flow_action actions[],
 106                                        struct rte_flow_error *error,
 107                                        union i40e_filter_t *filter);
 108 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 109                                       const struct rte_flow_attr *attr,
 110                                       const struct rte_flow_item pattern[],
 111                                       const struct rte_flow_action actions[],
 112                                       struct rte_flow_error *error,
 113                                       union i40e_filter_t *filter);
 114 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 115                                       struct i40e_ethertype_filter *filter);
 116 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 117                                            struct i40e_tunnel_filter *filter);
 118 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 119 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 120 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 121 static int i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 122 static int
 123 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 124                               const struct rte_flow_attr *attr,
 125                               const struct rte_flow_item pattern[],
 126                               const struct rte_flow_action actions[],
 127                               struct rte_flow_error *error,
 128                               union i40e_filter_t *filter);
 129 static int
 130 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 131                               const struct rte_flow_item *pattern,
 132                               struct rte_flow_error *error,
 133                               struct i40e_tunnel_filter_conf *filter);
 134
 135 static int i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
 136                                            const struct rte_flow_attr *attr,
 137                                            const struct rte_flow_item pattern[],
 138                                            const struct rte_flow_action actions[],
 139                                            struct rte_flow_error *error,
 140                                            union i40e_filter_t *filter);
 141 const struct rte_flow_ops i40e_flow_ops = {
 142         .validate = i40e_flow_validate,
 143         .create = i40e_flow_create,
 144         .destroy = i40e_flow_destroy,
 145         .flush = i40e_flow_flush,
 146         .query = i40e_flow_query,
 147 };
 148
 149 static union i40e_filter_t cons_filter;
 150 static enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 151 /* internal pattern w/o VOID items */
 152 struct rte_flow_item g_items[32];
 153
 154 /* Pattern matched ethertype filter */
 155 static enum rte_flow_item_type pattern_ethertype[] = {
 156         RTE_FLOW_ITEM_TYPE_ETH,
 157         RTE_FLOW_ITEM_TYPE_END,
 158 };
 159
 160 /* Pattern matched flow director filter */
 161 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 162         RTE_FLOW_ITEM_TYPE_ETH,
 163         RTE_FLOW_ITEM_TYPE_IPV4,
 164         RTE_FLOW_ITEM_TYPE_END,
 165 };
 166
 167 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 168         RTE_FLOW_ITEM_TYPE_ETH,
 169         RTE_FLOW_ITEM_TYPE_IPV4,
 170         RTE_FLOW_ITEM_TYPE_UDP,
 171         RTE_FLOW_ITEM_TYPE_END,
 172 };
 173
 174 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 175         RTE_FLOW_ITEM_TYPE_ETH,
 176         RTE_FLOW_ITEM_TYPE_IPV4,
 177         RTE_FLOW_ITEM_TYPE_TCP,
 178         RTE_FLOW_ITEM_TYPE_END,
 179 };
 180
 181 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 182         RTE_FLOW_ITEM_TYPE_ETH,
 183         RTE_FLOW_ITEM_TYPE_IPV4,
 184         RTE_FLOW_ITEM_TYPE_SCTP,
 185         RTE_FLOW_ITEM_TYPE_END,
 186 };
 187
 188 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 189         RTE_FLOW_ITEM_TYPE_ETH,
 190         RTE_FLOW_ITEM_TYPE_IPV4,
 191         RTE_FLOW_ITEM_TYPE_UDP,
 192         RTE_FLOW_ITEM_TYPE_GTPC,
 193         RTE_FLOW_ITEM_TYPE_END,
 194 };
 195
 196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 197         RTE_FLOW_ITEM_TYPE_ETH,
 198         RTE_FLOW_ITEM_TYPE_IPV4,
 199         RTE_FLOW_ITEM_TYPE_UDP,
 200         RTE_FLOW_ITEM_TYPE_GTPU,
 201         RTE_FLOW_ITEM_TYPE_END,
 202 };
 203
 204 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 205         RTE_FLOW_ITEM_TYPE_ETH,
 206         RTE_FLOW_ITEM_TYPE_IPV4,
 207         RTE_FLOW_ITEM_TYPE_UDP,
 208         RTE_FLOW_ITEM_TYPE_GTPU,
 209         RTE_FLOW_ITEM_TYPE_IPV4,
 210         RTE_FLOW_ITEM_TYPE_END,
 211 };
 212
 213 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 214         RTE_FLOW_ITEM_TYPE_ETH,
 215         RTE_FLOW_ITEM_TYPE_IPV4,
 216         RTE_FLOW_ITEM_TYPE_UDP,
 217         RTE_FLOW_ITEM_TYPE_GTPU,
 218         RTE_FLOW_ITEM_TYPE_IPV6,
 219         RTE_FLOW_ITEM_TYPE_END,
 220 };
 221
 222 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 223         RTE_FLOW_ITEM_TYPE_ETH,
 224         RTE_FLOW_ITEM_TYPE_IPV6,
 225         RTE_FLOW_ITEM_TYPE_END,
 226 };
 227
 228 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 229         RTE_FLOW_ITEM_TYPE_ETH,
 230         RTE_FLOW_ITEM_TYPE_IPV6,
 231         RTE_FLOW_ITEM_TYPE_UDP,
 232         RTE_FLOW_ITEM_TYPE_END,
 233 };
 234
 235 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 236         RTE_FLOW_ITEM_TYPE_ETH,
 237         RTE_FLOW_ITEM_TYPE_IPV6,
 238         RTE_FLOW_ITEM_TYPE_TCP,
 239         RTE_FLOW_ITEM_TYPE_END,
 240 };
 241
 242 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 243         RTE_FLOW_ITEM_TYPE_ETH,
 244         RTE_FLOW_ITEM_TYPE_IPV6,
 245         RTE_FLOW_ITEM_TYPE_SCTP,
 246         RTE_FLOW_ITEM_TYPE_END,
 247 };
 248
 249 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 250         RTE_FLOW_ITEM_TYPE_ETH,
 251         RTE_FLOW_ITEM_TYPE_IPV6,
 252         RTE_FLOW_ITEM_TYPE_UDP,
 253         RTE_FLOW_ITEM_TYPE_GTPC,
 254         RTE_FLOW_ITEM_TYPE_END,
 255 };
 256
 257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 258         RTE_FLOW_ITEM_TYPE_ETH,
 259         RTE_FLOW_ITEM_TYPE_IPV6,
 260         RTE_FLOW_ITEM_TYPE_UDP,
 261         RTE_FLOW_ITEM_TYPE_GTPU,
 262         RTE_FLOW_ITEM_TYPE_END,
 263 };
 264
 265 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 266         RTE_FLOW_ITEM_TYPE_ETH,
 267         RTE_FLOW_ITEM_TYPE_IPV6,
 268         RTE_FLOW_ITEM_TYPE_UDP,
 269         RTE_FLOW_ITEM_TYPE_GTPU,
 270         RTE_FLOW_ITEM_TYPE_IPV4,
 271         RTE_FLOW_ITEM_TYPE_END,
 272 };
 273
 274 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 275         RTE_FLOW_ITEM_TYPE_ETH,
 276         RTE_FLOW_ITEM_TYPE_IPV6,
 277         RTE_FLOW_ITEM_TYPE_UDP,
 278         RTE_FLOW_ITEM_TYPE_GTPU,
 279         RTE_FLOW_ITEM_TYPE_IPV6,
 280         RTE_FLOW_ITEM_TYPE_END,
 281 };
 282
 283 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 284         RTE_FLOW_ITEM_TYPE_ETH,
 285         RTE_FLOW_ITEM_TYPE_RAW,
 286         RTE_FLOW_ITEM_TYPE_END,
 287 };
 288
 289 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 290         RTE_FLOW_ITEM_TYPE_ETH,
 291         RTE_FLOW_ITEM_TYPE_RAW,
 292         RTE_FLOW_ITEM_TYPE_RAW,
 293         RTE_FLOW_ITEM_TYPE_END,
 294 };
 295
 296 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 297         RTE_FLOW_ITEM_TYPE_ETH,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_RAW,
 300         RTE_FLOW_ITEM_TYPE_RAW,
 301         RTE_FLOW_ITEM_TYPE_END,
 302 };
 303
 304 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 305         RTE_FLOW_ITEM_TYPE_ETH,
 306         RTE_FLOW_ITEM_TYPE_IPV4,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_END,
 309 };
 310
 311 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 312         RTE_FLOW_ITEM_TYPE_ETH,
 313         RTE_FLOW_ITEM_TYPE_IPV4,
 314         RTE_FLOW_ITEM_TYPE_RAW,
 315         RTE_FLOW_ITEM_TYPE_RAW,
 316         RTE_FLOW_ITEM_TYPE_END,
 317 };
 318
 319 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 320         RTE_FLOW_ITEM_TYPE_ETH,
 321         RTE_FLOW_ITEM_TYPE_IPV4,
 322         RTE_FLOW_ITEM_TYPE_RAW,
 323         RTE_FLOW_ITEM_TYPE_RAW,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_END,
 326 };
 327
 328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 329         RTE_FLOW_ITEM_TYPE_ETH,
 330         RTE_FLOW_ITEM_TYPE_IPV4,
 331         RTE_FLOW_ITEM_TYPE_UDP,
 332         RTE_FLOW_ITEM_TYPE_RAW,
 333         RTE_FLOW_ITEM_TYPE_END,
 334 };
 335
 336 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 337         RTE_FLOW_ITEM_TYPE_ETH,
 338         RTE_FLOW_ITEM_TYPE_IPV4,
 339         RTE_FLOW_ITEM_TYPE_UDP,
 340         RTE_FLOW_ITEM_TYPE_RAW,
 341         RTE_FLOW_ITEM_TYPE_RAW,
 342         RTE_FLOW_ITEM_TYPE_END,
 343 };
 344
 345 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 346         RTE_FLOW_ITEM_TYPE_ETH,
 347         RTE_FLOW_ITEM_TYPE_IPV4,
 348         RTE_FLOW_ITEM_TYPE_UDP,
 349         RTE_FLOW_ITEM_TYPE_RAW,
 350         RTE_FLOW_ITEM_TYPE_RAW,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_END,
 353 };
 354
 355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 356         RTE_FLOW_ITEM_TYPE_ETH,
 357         RTE_FLOW_ITEM_TYPE_IPV4,
 358         RTE_FLOW_ITEM_TYPE_TCP,
 359         RTE_FLOW_ITEM_TYPE_RAW,
 360         RTE_FLOW_ITEM_TYPE_END,
 361 };
 362
 363 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 364         RTE_FLOW_ITEM_TYPE_ETH,
 365         RTE_FLOW_ITEM_TYPE_IPV4,
 366         RTE_FLOW_ITEM_TYPE_TCP,
 367         RTE_FLOW_ITEM_TYPE_RAW,
 368         RTE_FLOW_ITEM_TYPE_RAW,
 369         RTE_FLOW_ITEM_TYPE_END,
 370 };
 371
 372 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 373         RTE_FLOW_ITEM_TYPE_ETH,
 374         RTE_FLOW_ITEM_TYPE_IPV4,
 375         RTE_FLOW_ITEM_TYPE_TCP,
 376         RTE_FLOW_ITEM_TYPE_RAW,
 377         RTE_FLOW_ITEM_TYPE_RAW,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_END,
 380 };
 381
 382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 383         RTE_FLOW_ITEM_TYPE_ETH,
 384         RTE_FLOW_ITEM_TYPE_IPV4,
 385         RTE_FLOW_ITEM_TYPE_SCTP,
 386         RTE_FLOW_ITEM_TYPE_RAW,
 387         RTE_FLOW_ITEM_TYPE_END,
 388 };
 389
 390 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 391         RTE_FLOW_ITEM_TYPE_ETH,
 392         RTE_FLOW_ITEM_TYPE_IPV4,
 393         RTE_FLOW_ITEM_TYPE_SCTP,
 394         RTE_FLOW_ITEM_TYPE_RAW,
 395         RTE_FLOW_ITEM_TYPE_RAW,
 396         RTE_FLOW_ITEM_TYPE_END,
 397 };
 398
 399 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 400         RTE_FLOW_ITEM_TYPE_ETH,
 401         RTE_FLOW_ITEM_TYPE_IPV4,
 402         RTE_FLOW_ITEM_TYPE_SCTP,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_RAW,
 405         RTE_FLOW_ITEM_TYPE_RAW,
 406         RTE_FLOW_ITEM_TYPE_END,
 407 };
 408
 409 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 410         RTE_FLOW_ITEM_TYPE_ETH,
 411         RTE_FLOW_ITEM_TYPE_IPV6,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_END,
 414 };
 415
 416 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 417         RTE_FLOW_ITEM_TYPE_ETH,
 418         RTE_FLOW_ITEM_TYPE_IPV6,
 419         RTE_FLOW_ITEM_TYPE_RAW,
 420         RTE_FLOW_ITEM_TYPE_RAW,
 421         RTE_FLOW_ITEM_TYPE_END,
 422 };
 423
 424 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 425         RTE_FLOW_ITEM_TYPE_ETH,
 426         RTE_FLOW_ITEM_TYPE_IPV6,
 427         RTE_FLOW_ITEM_TYPE_RAW,
 428         RTE_FLOW_ITEM_TYPE_RAW,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_END,
 431 };
 432
 433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 434         RTE_FLOW_ITEM_TYPE_ETH,
 435         RTE_FLOW_ITEM_TYPE_IPV6,
 436         RTE_FLOW_ITEM_TYPE_UDP,
 437         RTE_FLOW_ITEM_TYPE_RAW,
 438         RTE_FLOW_ITEM_TYPE_END,
 439 };
 440
 441 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 442         RTE_FLOW_ITEM_TYPE_ETH,
 443         RTE_FLOW_ITEM_TYPE_IPV6,
 444         RTE_FLOW_ITEM_TYPE_UDP,
 445         RTE_FLOW_ITEM_TYPE_RAW,
 446         RTE_FLOW_ITEM_TYPE_RAW,
 447         RTE_FLOW_ITEM_TYPE_END,
 448 };
 449
 450 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 451         RTE_FLOW_ITEM_TYPE_ETH,
 452         RTE_FLOW_ITEM_TYPE_IPV6,
 453         RTE_FLOW_ITEM_TYPE_UDP,
 454         RTE_FLOW_ITEM_TYPE_RAW,
 455         RTE_FLOW_ITEM_TYPE_RAW,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_END,
 458 };
 459
 460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 461         RTE_FLOW_ITEM_TYPE_ETH,
 462         RTE_FLOW_ITEM_TYPE_IPV6,
 463         RTE_FLOW_ITEM_TYPE_TCP,
 464         RTE_FLOW_ITEM_TYPE_RAW,
 465         RTE_FLOW_ITEM_TYPE_END,
 466 };
 467
 468 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 469         RTE_FLOW_ITEM_TYPE_ETH,
 470         RTE_FLOW_ITEM_TYPE_IPV6,
 471         RTE_FLOW_ITEM_TYPE_TCP,
 472         RTE_FLOW_ITEM_TYPE_RAW,
 473         RTE_FLOW_ITEM_TYPE_RAW,
 474         RTE_FLOW_ITEM_TYPE_END,
 475 };
 476
 477 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 478         RTE_FLOW_ITEM_TYPE_ETH,
 479         RTE_FLOW_ITEM_TYPE_IPV6,
 480         RTE_FLOW_ITEM_TYPE_TCP,
 481         RTE_FLOW_ITEM_TYPE_RAW,
 482         RTE_FLOW_ITEM_TYPE_RAW,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_END,
 485 };
 486
 487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 488         RTE_FLOW_ITEM_TYPE_ETH,
 489         RTE_FLOW_ITEM_TYPE_IPV6,
 490         RTE_FLOW_ITEM_TYPE_SCTP,
 491         RTE_FLOW_ITEM_TYPE_RAW,
 492         RTE_FLOW_ITEM_TYPE_END,
 493 };
 494
 495 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 496         RTE_FLOW_ITEM_TYPE_ETH,
 497         RTE_FLOW_ITEM_TYPE_IPV6,
 498         RTE_FLOW_ITEM_TYPE_SCTP,
 499         RTE_FLOW_ITEM_TYPE_RAW,
 500         RTE_FLOW_ITEM_TYPE_RAW,
 501         RTE_FLOW_ITEM_TYPE_END,
 502 };
 503
 504 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 505         RTE_FLOW_ITEM_TYPE_ETH,
 506         RTE_FLOW_ITEM_TYPE_IPV6,
 507         RTE_FLOW_ITEM_TYPE_SCTP,
 508         RTE_FLOW_ITEM_TYPE_RAW,
 509         RTE_FLOW_ITEM_TYPE_RAW,
 510         RTE_FLOW_ITEM_TYPE_RAW,
 511         RTE_FLOW_ITEM_TYPE_END,
 512 };
 513
 514 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 515         RTE_FLOW_ITEM_TYPE_ETH,
 516         RTE_FLOW_ITEM_TYPE_VLAN,
 517         RTE_FLOW_ITEM_TYPE_END,
 518 };
 519
 520 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 521         RTE_FLOW_ITEM_TYPE_ETH,
 522         RTE_FLOW_ITEM_TYPE_VLAN,
 523         RTE_FLOW_ITEM_TYPE_IPV4,
 524         RTE_FLOW_ITEM_TYPE_END,
 525 };
 526
 527 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 528         RTE_FLOW_ITEM_TYPE_ETH,
 529         RTE_FLOW_ITEM_TYPE_VLAN,
 530         RTE_FLOW_ITEM_TYPE_IPV4,
 531         RTE_FLOW_ITEM_TYPE_UDP,
 532         RTE_FLOW_ITEM_TYPE_END,
 533 };
 534
 535 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 536         RTE_FLOW_ITEM_TYPE_ETH,
 537         RTE_FLOW_ITEM_TYPE_VLAN,
 538         RTE_FLOW_ITEM_TYPE_IPV4,
 539         RTE_FLOW_ITEM_TYPE_TCP,
 540         RTE_FLOW_ITEM_TYPE_END,
 541 };
 542
 543 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 544         RTE_FLOW_ITEM_TYPE_ETH,
 545         RTE_FLOW_ITEM_TYPE_VLAN,
 546         RTE_FLOW_ITEM_TYPE_IPV4,
 547         RTE_FLOW_ITEM_TYPE_SCTP,
 548         RTE_FLOW_ITEM_TYPE_END,
 549 };
 550
 551 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 552         RTE_FLOW_ITEM_TYPE_ETH,
 553         RTE_FLOW_ITEM_TYPE_VLAN,
 554         RTE_FLOW_ITEM_TYPE_IPV6,
 555         RTE_FLOW_ITEM_TYPE_END,
 556 };
 557
 558 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 559         RTE_FLOW_ITEM_TYPE_ETH,
 560         RTE_FLOW_ITEM_TYPE_VLAN,
 561         RTE_FLOW_ITEM_TYPE_IPV6,
 562         RTE_FLOW_ITEM_TYPE_UDP,
 563         RTE_FLOW_ITEM_TYPE_END,
 564 };
 565
 566 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 567         RTE_FLOW_ITEM_TYPE_ETH,
 568         RTE_FLOW_ITEM_TYPE_VLAN,
 569         RTE_FLOW_ITEM_TYPE_IPV6,
 570         RTE_FLOW_ITEM_TYPE_TCP,
 571         RTE_FLOW_ITEM_TYPE_END,
 572 };
 573
 574 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 575         RTE_FLOW_ITEM_TYPE_ETH,
 576         RTE_FLOW_ITEM_TYPE_VLAN,
 577         RTE_FLOW_ITEM_TYPE_IPV6,
 578         RTE_FLOW_ITEM_TYPE_SCTP,
 579         RTE_FLOW_ITEM_TYPE_END,
 580 };
 581
 582 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 583         RTE_FLOW_ITEM_TYPE_ETH,
 584         RTE_FLOW_ITEM_TYPE_VLAN,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_END,
 587 };
 588
 589 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 590         RTE_FLOW_ITEM_TYPE_ETH,
 591         RTE_FLOW_ITEM_TYPE_VLAN,
 592         RTE_FLOW_ITEM_TYPE_RAW,
 593         RTE_FLOW_ITEM_TYPE_RAW,
 594         RTE_FLOW_ITEM_TYPE_END,
 595 };
 596
 597 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 598         RTE_FLOW_ITEM_TYPE_ETH,
 599         RTE_FLOW_ITEM_TYPE_VLAN,
 600         RTE_FLOW_ITEM_TYPE_RAW,
 601         RTE_FLOW_ITEM_TYPE_RAW,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_END,
 604 };
 605
 606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 607         RTE_FLOW_ITEM_TYPE_ETH,
 608         RTE_FLOW_ITEM_TYPE_VLAN,
 609         RTE_FLOW_ITEM_TYPE_IPV4,
 610         RTE_FLOW_ITEM_TYPE_RAW,
 611         RTE_FLOW_ITEM_TYPE_END,
 612 };
 613
 614 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 615         RTE_FLOW_ITEM_TYPE_ETH,
 616         RTE_FLOW_ITEM_TYPE_VLAN,
 617         RTE_FLOW_ITEM_TYPE_IPV4,
 618         RTE_FLOW_ITEM_TYPE_RAW,
 619         RTE_FLOW_ITEM_TYPE_RAW,
 620         RTE_FLOW_ITEM_TYPE_END,
 621 };
 622
 623 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 624         RTE_FLOW_ITEM_TYPE_ETH,
 625         RTE_FLOW_ITEM_TYPE_VLAN,
 626         RTE_FLOW_ITEM_TYPE_IPV4,
 627         RTE_FLOW_ITEM_TYPE_RAW,
 628         RTE_FLOW_ITEM_TYPE_RAW,
 629         RTE_FLOW_ITEM_TYPE_RAW,
 630         RTE_FLOW_ITEM_TYPE_END,
 631 };
 632
 633 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 634         RTE_FLOW_ITEM_TYPE_ETH,
 635         RTE_FLOW_ITEM_TYPE_VLAN,
 636         RTE_FLOW_ITEM_TYPE_IPV4,
 637         RTE_FLOW_ITEM_TYPE_UDP,
 638         RTE_FLOW_ITEM_TYPE_RAW,
 639         RTE_FLOW_ITEM_TYPE_END,
 640 };
 641
 642 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 643         RTE_FLOW_ITEM_TYPE_ETH,
 644         RTE_FLOW_ITEM_TYPE_VLAN,
 645         RTE_FLOW_ITEM_TYPE_IPV4,
 646         RTE_FLOW_ITEM_TYPE_UDP,
 647         RTE_FLOW_ITEM_TYPE_RAW,
 648         RTE_FLOW_ITEM_TYPE_RAW,
 649         RTE_FLOW_ITEM_TYPE_END,
 650 };
 651
 652 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 653         RTE_FLOW_ITEM_TYPE_ETH,
 654         RTE_FLOW_ITEM_TYPE_VLAN,
 655         RTE_FLOW_ITEM_TYPE_IPV4,
 656         RTE_FLOW_ITEM_TYPE_UDP,
 657         RTE_FLOW_ITEM_TYPE_RAW,
 658         RTE_FLOW_ITEM_TYPE_RAW,
 659         RTE_FLOW_ITEM_TYPE_RAW,
 660         RTE_FLOW_ITEM_TYPE_END,
 661 };
 662
 663 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 664         RTE_FLOW_ITEM_TYPE_ETH,
 665         RTE_FLOW_ITEM_TYPE_VLAN,
 666         RTE_FLOW_ITEM_TYPE_IPV4,
 667         RTE_FLOW_ITEM_TYPE_TCP,
 668         RTE_FLOW_ITEM_TYPE_RAW,
 669         RTE_FLOW_ITEM_TYPE_END,
 670 };
 671
 672 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 673         RTE_FLOW_ITEM_TYPE_ETH,
 674         RTE_FLOW_ITEM_TYPE_VLAN,
 675         RTE_FLOW_ITEM_TYPE_IPV4,
 676         RTE_FLOW_ITEM_TYPE_TCP,
 677         RTE_FLOW_ITEM_TYPE_RAW,
 678         RTE_FLOW_ITEM_TYPE_RAW,
 679         RTE_FLOW_ITEM_TYPE_END,
 680 };
 681
 682 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 683         RTE_FLOW_ITEM_TYPE_ETH,
 684         RTE_FLOW_ITEM_TYPE_VLAN,
 685         RTE_FLOW_ITEM_TYPE_IPV4,
 686         RTE_FLOW_ITEM_TYPE_TCP,
 687         RTE_FLOW_ITEM_TYPE_RAW,
 688         RTE_FLOW_ITEM_TYPE_RAW,
 689         RTE_FLOW_ITEM_TYPE_RAW,
 690         RTE_FLOW_ITEM_TYPE_END,
 691 };
 692
 693 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 694         RTE_FLOW_ITEM_TYPE_ETH,
 695         RTE_FLOW_ITEM_TYPE_VLAN,
 696         RTE_FLOW_ITEM_TYPE_IPV4,
 697         RTE_FLOW_ITEM_TYPE_SCTP,
 698         RTE_FLOW_ITEM_TYPE_RAW,
 699         RTE_FLOW_ITEM_TYPE_END,
 700 };
 701
 702 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 703         RTE_FLOW_ITEM_TYPE_ETH,
 704         RTE_FLOW_ITEM_TYPE_VLAN,
 705         RTE_FLOW_ITEM_TYPE_IPV4,
 706         RTE_FLOW_ITEM_TYPE_SCTP,
 707         RTE_FLOW_ITEM_TYPE_RAW,
 708         RTE_FLOW_ITEM_TYPE_RAW,
 709         RTE_FLOW_ITEM_TYPE_END,
 710 };
 711
 712 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 713         RTE_FLOW_ITEM_TYPE_ETH,
 714         RTE_FLOW_ITEM_TYPE_VLAN,
 715         RTE_FLOW_ITEM_TYPE_IPV4,
 716         RTE_FLOW_ITEM_TYPE_SCTP,
 717         RTE_FLOW_ITEM_TYPE_RAW,
 718         RTE_FLOW_ITEM_TYPE_RAW,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_END,
 721 };
 722
 723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 724         RTE_FLOW_ITEM_TYPE_ETH,
 725         RTE_FLOW_ITEM_TYPE_VLAN,
 726         RTE_FLOW_ITEM_TYPE_IPV6,
 727         RTE_FLOW_ITEM_TYPE_RAW,
 728         RTE_FLOW_ITEM_TYPE_END,
 729 };
 730
 731 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 732         RTE_FLOW_ITEM_TYPE_ETH,
 733         RTE_FLOW_ITEM_TYPE_VLAN,
 734         RTE_FLOW_ITEM_TYPE_IPV6,
 735         RTE_FLOW_ITEM_TYPE_RAW,
 736         RTE_FLOW_ITEM_TYPE_RAW,
 737         RTE_FLOW_ITEM_TYPE_END,
 738 };
 739
 740 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 741         RTE_FLOW_ITEM_TYPE_ETH,
 742         RTE_FLOW_ITEM_TYPE_VLAN,
 743         RTE_FLOW_ITEM_TYPE_IPV6,
 744         RTE_FLOW_ITEM_TYPE_RAW,
 745         RTE_FLOW_ITEM_TYPE_RAW,
 746         RTE_FLOW_ITEM_TYPE_RAW,
 747         RTE_FLOW_ITEM_TYPE_END,
 748 };
 749
 750 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 751         RTE_FLOW_ITEM_TYPE_ETH,
 752         RTE_FLOW_ITEM_TYPE_VLAN,
 753         RTE_FLOW_ITEM_TYPE_IPV6,
 754         RTE_FLOW_ITEM_TYPE_UDP,
 755         RTE_FLOW_ITEM_TYPE_RAW,
 756         RTE_FLOW_ITEM_TYPE_END,
 757 };
 758
 759 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 760         RTE_FLOW_ITEM_TYPE_ETH,
 761         RTE_FLOW_ITEM_TYPE_VLAN,
 762         RTE_FLOW_ITEM_TYPE_IPV6,
 763         RTE_FLOW_ITEM_TYPE_UDP,
 764         RTE_FLOW_ITEM_TYPE_RAW,
 765         RTE_FLOW_ITEM_TYPE_RAW,
 766         RTE_FLOW_ITEM_TYPE_END,
 767 };
 768
 769 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 770         RTE_FLOW_ITEM_TYPE_ETH,
 771         RTE_FLOW_ITEM_TYPE_VLAN,
 772         RTE_FLOW_ITEM_TYPE_IPV6,
 773         RTE_FLOW_ITEM_TYPE_UDP,
 774         RTE_FLOW_ITEM_TYPE_RAW,
 775         RTE_FLOW_ITEM_TYPE_RAW,
 776         RTE_FLOW_ITEM_TYPE_RAW,
 777         RTE_FLOW_ITEM_TYPE_END,
 778 };
 779
 780 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 781         RTE_FLOW_ITEM_TYPE_ETH,
 782         RTE_FLOW_ITEM_TYPE_VLAN,
 783         RTE_FLOW_ITEM_TYPE_IPV6,
 784         RTE_FLOW_ITEM_TYPE_TCP,
 785         RTE_FLOW_ITEM_TYPE_RAW,
 786         RTE_FLOW_ITEM_TYPE_END,
 787 };
 788
 789 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 790         RTE_FLOW_ITEM_TYPE_ETH,
 791         RTE_FLOW_ITEM_TYPE_VLAN,
 792         RTE_FLOW_ITEM_TYPE_IPV6,
 793         RTE_FLOW_ITEM_TYPE_TCP,
 794         RTE_FLOW_ITEM_TYPE_RAW,
 795         RTE_FLOW_ITEM_TYPE_RAW,
 796         RTE_FLOW_ITEM_TYPE_END,
 797 };
 798
 799 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 800         RTE_FLOW_ITEM_TYPE_ETH,
 801         RTE_FLOW_ITEM_TYPE_VLAN,
 802         RTE_FLOW_ITEM_TYPE_IPV6,
 803         RTE_FLOW_ITEM_TYPE_TCP,
 804         RTE_FLOW_ITEM_TYPE_RAW,
 805         RTE_FLOW_ITEM_TYPE_RAW,
 806         RTE_FLOW_ITEM_TYPE_RAW,
 807         RTE_FLOW_ITEM_TYPE_END,
 808 };
 809
 810 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 811         RTE_FLOW_ITEM_TYPE_ETH,
 812         RTE_FLOW_ITEM_TYPE_VLAN,
 813         RTE_FLOW_ITEM_TYPE_IPV6,
 814         RTE_FLOW_ITEM_TYPE_SCTP,
 815         RTE_FLOW_ITEM_TYPE_RAW,
 816         RTE_FLOW_ITEM_TYPE_END,
 817 };
 818
 819 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 820         RTE_FLOW_ITEM_TYPE_ETH,
 821         RTE_FLOW_ITEM_TYPE_VLAN,
 822         RTE_FLOW_ITEM_TYPE_IPV6,
 823         RTE_FLOW_ITEM_TYPE_SCTP,
 824         RTE_FLOW_ITEM_TYPE_RAW,
 825         RTE_FLOW_ITEM_TYPE_RAW,
 826         RTE_FLOW_ITEM_TYPE_END,
 827 };
 828
 829 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 830         RTE_FLOW_ITEM_TYPE_ETH,
 831         RTE_FLOW_ITEM_TYPE_VLAN,
 832         RTE_FLOW_ITEM_TYPE_IPV6,
 833         RTE_FLOW_ITEM_TYPE_SCTP,
 834         RTE_FLOW_ITEM_TYPE_RAW,
 835         RTE_FLOW_ITEM_TYPE_RAW,
 836         RTE_FLOW_ITEM_TYPE_RAW,
 837         RTE_FLOW_ITEM_TYPE_END,
 838 };
 839
 840 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 841         RTE_FLOW_ITEM_TYPE_ETH,
 842         RTE_FLOW_ITEM_TYPE_IPV4,
 843         RTE_FLOW_ITEM_TYPE_VF,
 844         RTE_FLOW_ITEM_TYPE_END,
 845 };
 846
 847 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 848         RTE_FLOW_ITEM_TYPE_ETH,
 849         RTE_FLOW_ITEM_TYPE_IPV4,
 850         RTE_FLOW_ITEM_TYPE_UDP,
 851         RTE_FLOW_ITEM_TYPE_VF,
 852         RTE_FLOW_ITEM_TYPE_END,
 853 };
 854
 855 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 856         RTE_FLOW_ITEM_TYPE_ETH,
 857         RTE_FLOW_ITEM_TYPE_IPV4,
 858         RTE_FLOW_ITEM_TYPE_TCP,
 859         RTE_FLOW_ITEM_TYPE_VF,
 860         RTE_FLOW_ITEM_TYPE_END,
 861 };
 862
 863 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 864         RTE_FLOW_ITEM_TYPE_ETH,
 865         RTE_FLOW_ITEM_TYPE_IPV4,
 866         RTE_FLOW_ITEM_TYPE_SCTP,
 867         RTE_FLOW_ITEM_TYPE_VF,
 868         RTE_FLOW_ITEM_TYPE_END,
 869 };
 870
 871 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 872         RTE_FLOW_ITEM_TYPE_ETH,
 873         RTE_FLOW_ITEM_TYPE_IPV6,
 874         RTE_FLOW_ITEM_TYPE_VF,
 875         RTE_FLOW_ITEM_TYPE_END,
 876 };
 877
 878 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 879         RTE_FLOW_ITEM_TYPE_ETH,
 880         RTE_FLOW_ITEM_TYPE_IPV6,
 881         RTE_FLOW_ITEM_TYPE_UDP,
 882         RTE_FLOW_ITEM_TYPE_VF,
 883         RTE_FLOW_ITEM_TYPE_END,
 884 };
 885
 886 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 887         RTE_FLOW_ITEM_TYPE_ETH,
 888         RTE_FLOW_ITEM_TYPE_IPV6,
 889         RTE_FLOW_ITEM_TYPE_TCP,
 890         RTE_FLOW_ITEM_TYPE_VF,
 891         RTE_FLOW_ITEM_TYPE_END,
 892 };
 893
 894 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 895         RTE_FLOW_ITEM_TYPE_ETH,
 896         RTE_FLOW_ITEM_TYPE_IPV6,
 897         RTE_FLOW_ITEM_TYPE_SCTP,
 898         RTE_FLOW_ITEM_TYPE_VF,
 899         RTE_FLOW_ITEM_TYPE_END,
 900 };
 901
 902 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 903         RTE_FLOW_ITEM_TYPE_ETH,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_VF,
 906         RTE_FLOW_ITEM_TYPE_END,
 907 };
 908
 909 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 910         RTE_FLOW_ITEM_TYPE_ETH,
 911         RTE_FLOW_ITEM_TYPE_RAW,
 912         RTE_FLOW_ITEM_TYPE_RAW,
 913         RTE_FLOW_ITEM_TYPE_VF,
 914         RTE_FLOW_ITEM_TYPE_END,
 915 };
 916
 917 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 918         RTE_FLOW_ITEM_TYPE_ETH,
 919         RTE_FLOW_ITEM_TYPE_RAW,
 920         RTE_FLOW_ITEM_TYPE_RAW,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_VF,
 923         RTE_FLOW_ITEM_TYPE_END,
 924 };
 925
 926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 927         RTE_FLOW_ITEM_TYPE_ETH,
 928         RTE_FLOW_ITEM_TYPE_IPV4,
 929         RTE_FLOW_ITEM_TYPE_RAW,
 930         RTE_FLOW_ITEM_TYPE_VF,
 931         RTE_FLOW_ITEM_TYPE_END,
 932 };
 933
 934 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 935         RTE_FLOW_ITEM_TYPE_ETH,
 936         RTE_FLOW_ITEM_TYPE_IPV4,
 937         RTE_FLOW_ITEM_TYPE_RAW,
 938         RTE_FLOW_ITEM_TYPE_RAW,
 939         RTE_FLOW_ITEM_TYPE_VF,
 940         RTE_FLOW_ITEM_TYPE_END,
 941 };
 942
 943 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 944         RTE_FLOW_ITEM_TYPE_ETH,
 945         RTE_FLOW_ITEM_TYPE_IPV4,
 946         RTE_FLOW_ITEM_TYPE_RAW,
 947         RTE_FLOW_ITEM_TYPE_RAW,
 948         RTE_FLOW_ITEM_TYPE_RAW,
 949         RTE_FLOW_ITEM_TYPE_VF,
 950         RTE_FLOW_ITEM_TYPE_END,
 951 };
 952
 953 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 954         RTE_FLOW_ITEM_TYPE_ETH,
 955         RTE_FLOW_ITEM_TYPE_IPV4,
 956         RTE_FLOW_ITEM_TYPE_UDP,
 957         RTE_FLOW_ITEM_TYPE_RAW,
 958         RTE_FLOW_ITEM_TYPE_VF,
 959         RTE_FLOW_ITEM_TYPE_END,
 960 };
 961
 962 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 963         RTE_FLOW_ITEM_TYPE_ETH,
 964         RTE_FLOW_ITEM_TYPE_IPV4,
 965         RTE_FLOW_ITEM_TYPE_UDP,
 966         RTE_FLOW_ITEM_TYPE_RAW,
 967         RTE_FLOW_ITEM_TYPE_RAW,
 968         RTE_FLOW_ITEM_TYPE_VF,
 969         RTE_FLOW_ITEM_TYPE_END,
 970 };
 971
 972 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 973         RTE_FLOW_ITEM_TYPE_ETH,
 974         RTE_FLOW_ITEM_TYPE_IPV4,
 975         RTE_FLOW_ITEM_TYPE_UDP,
 976         RTE_FLOW_ITEM_TYPE_RAW,
 977         RTE_FLOW_ITEM_TYPE_RAW,
 978         RTE_FLOW_ITEM_TYPE_RAW,
 979         RTE_FLOW_ITEM_TYPE_VF,
 980         RTE_FLOW_ITEM_TYPE_END,
 981 };
 982
 983 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 984         RTE_FLOW_ITEM_TYPE_ETH,
 985         RTE_FLOW_ITEM_TYPE_IPV4,
 986         RTE_FLOW_ITEM_TYPE_TCP,
 987         RTE_FLOW_ITEM_TYPE_RAW,
 988         RTE_FLOW_ITEM_TYPE_VF,
 989         RTE_FLOW_ITEM_TYPE_END,
 990 };
 991
 992 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 993         RTE_FLOW_ITEM_TYPE_ETH,
 994         RTE_FLOW_ITEM_TYPE_IPV4,
 995         RTE_FLOW_ITEM_TYPE_TCP,
 996         RTE_FLOW_ITEM_TYPE_RAW,
 997         RTE_FLOW_ITEM_TYPE_RAW,
 998         RTE_FLOW_ITEM_TYPE_VF,
 999         RTE_FLOW_ITEM_TYPE_END,
1000 };
1001
1002 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
1003         RTE_FLOW_ITEM_TYPE_ETH,
1004         RTE_FLOW_ITEM_TYPE_IPV4,
1005         RTE_FLOW_ITEM_TYPE_TCP,
1006         RTE_FLOW_ITEM_TYPE_RAW,
1007         RTE_FLOW_ITEM_TYPE_RAW,
1008         RTE_FLOW_ITEM_TYPE_RAW,
1009         RTE_FLOW_ITEM_TYPE_VF,
1010         RTE_FLOW_ITEM_TYPE_END,
1011 };
1012
1013 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
1014         RTE_FLOW_ITEM_TYPE_ETH,
1015         RTE_FLOW_ITEM_TYPE_IPV4,
1016         RTE_FLOW_ITEM_TYPE_SCTP,
1017         RTE_FLOW_ITEM_TYPE_RAW,
1018         RTE_FLOW_ITEM_TYPE_VF,
1019         RTE_FLOW_ITEM_TYPE_END,
1020 };
1021
1022 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1023         RTE_FLOW_ITEM_TYPE_ETH,
1024         RTE_FLOW_ITEM_TYPE_IPV4,
1025         RTE_FLOW_ITEM_TYPE_SCTP,
1026         RTE_FLOW_ITEM_TYPE_RAW,
1027         RTE_FLOW_ITEM_TYPE_RAW,
1028         RTE_FLOW_ITEM_TYPE_VF,
1029         RTE_FLOW_ITEM_TYPE_END,
1030 };
1031
1032 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1033         RTE_FLOW_ITEM_TYPE_ETH,
1034         RTE_FLOW_ITEM_TYPE_IPV4,
1035         RTE_FLOW_ITEM_TYPE_SCTP,
1036         RTE_FLOW_ITEM_TYPE_RAW,
1037         RTE_FLOW_ITEM_TYPE_RAW,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_VF,
1040         RTE_FLOW_ITEM_TYPE_END,
1041 };
1042
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1044         RTE_FLOW_ITEM_TYPE_ETH,
1045         RTE_FLOW_ITEM_TYPE_IPV6,
1046         RTE_FLOW_ITEM_TYPE_RAW,
1047         RTE_FLOW_ITEM_TYPE_VF,
1048         RTE_FLOW_ITEM_TYPE_END,
1049 };
1050
1051 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1052         RTE_FLOW_ITEM_TYPE_ETH,
1053         RTE_FLOW_ITEM_TYPE_IPV6,
1054         RTE_FLOW_ITEM_TYPE_RAW,
1055         RTE_FLOW_ITEM_TYPE_RAW,
1056         RTE_FLOW_ITEM_TYPE_VF,
1057         RTE_FLOW_ITEM_TYPE_END,
1058 };
1059
1060 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1061         RTE_FLOW_ITEM_TYPE_ETH,
1062         RTE_FLOW_ITEM_TYPE_IPV6,
1063         RTE_FLOW_ITEM_TYPE_RAW,
1064         RTE_FLOW_ITEM_TYPE_RAW,
1065         RTE_FLOW_ITEM_TYPE_RAW,
1066         RTE_FLOW_ITEM_TYPE_VF,
1067         RTE_FLOW_ITEM_TYPE_END,
1068 };
1069
1070 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1071         RTE_FLOW_ITEM_TYPE_ETH,
1072         RTE_FLOW_ITEM_TYPE_IPV6,
1073         RTE_FLOW_ITEM_TYPE_UDP,
1074         RTE_FLOW_ITEM_TYPE_RAW,
1075         RTE_FLOW_ITEM_TYPE_VF,
1076         RTE_FLOW_ITEM_TYPE_END,
1077 };
1078
1079 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1080         RTE_FLOW_ITEM_TYPE_ETH,
1081         RTE_FLOW_ITEM_TYPE_IPV6,
1082         RTE_FLOW_ITEM_TYPE_UDP,
1083         RTE_FLOW_ITEM_TYPE_RAW,
1084         RTE_FLOW_ITEM_TYPE_RAW,
1085         RTE_FLOW_ITEM_TYPE_VF,
1086         RTE_FLOW_ITEM_TYPE_END,
1087 };
1088
1089 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1090         RTE_FLOW_ITEM_TYPE_ETH,
1091         RTE_FLOW_ITEM_TYPE_IPV6,
1092         RTE_FLOW_ITEM_TYPE_UDP,
1093         RTE_FLOW_ITEM_TYPE_RAW,
1094         RTE_FLOW_ITEM_TYPE_RAW,
1095         RTE_FLOW_ITEM_TYPE_RAW,
1096         RTE_FLOW_ITEM_TYPE_VF,
1097         RTE_FLOW_ITEM_TYPE_END,
1098 };
1099
1100 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1101         RTE_FLOW_ITEM_TYPE_ETH,
1102         RTE_FLOW_ITEM_TYPE_IPV6,
1103         RTE_FLOW_ITEM_TYPE_TCP,
1104         RTE_FLOW_ITEM_TYPE_RAW,
1105         RTE_FLOW_ITEM_TYPE_VF,
1106         RTE_FLOW_ITEM_TYPE_END,
1107 };
1108
1109 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1110         RTE_FLOW_ITEM_TYPE_ETH,
1111         RTE_FLOW_ITEM_TYPE_IPV6,
1112         RTE_FLOW_ITEM_TYPE_TCP,
1113         RTE_FLOW_ITEM_TYPE_RAW,
1114         RTE_FLOW_ITEM_TYPE_RAW,
1115         RTE_FLOW_ITEM_TYPE_VF,
1116         RTE_FLOW_ITEM_TYPE_END,
1117 };
1118
1119 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1120         RTE_FLOW_ITEM_TYPE_ETH,
1121         RTE_FLOW_ITEM_TYPE_IPV6,
1122         RTE_FLOW_ITEM_TYPE_TCP,
1123         RTE_FLOW_ITEM_TYPE_RAW,
1124         RTE_FLOW_ITEM_TYPE_RAW,
1125         RTE_FLOW_ITEM_TYPE_RAW,
1126         RTE_FLOW_ITEM_TYPE_VF,
1127         RTE_FLOW_ITEM_TYPE_END,
1128 };
1129
1130 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1131         RTE_FLOW_ITEM_TYPE_ETH,
1132         RTE_FLOW_ITEM_TYPE_IPV6,
1133         RTE_FLOW_ITEM_TYPE_SCTP,
1134         RTE_FLOW_ITEM_TYPE_RAW,
1135         RTE_FLOW_ITEM_TYPE_VF,
1136         RTE_FLOW_ITEM_TYPE_END,
1137 };
1138
1139 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1140         RTE_FLOW_ITEM_TYPE_ETH,
1141         RTE_FLOW_ITEM_TYPE_IPV6,
1142         RTE_FLOW_ITEM_TYPE_SCTP,
1143         RTE_FLOW_ITEM_TYPE_RAW,
1144         RTE_FLOW_ITEM_TYPE_RAW,
1145         RTE_FLOW_ITEM_TYPE_VF,
1146         RTE_FLOW_ITEM_TYPE_END,
1147 };
1148
1149 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1150         RTE_FLOW_ITEM_TYPE_ETH,
1151         RTE_FLOW_ITEM_TYPE_IPV6,
1152         RTE_FLOW_ITEM_TYPE_SCTP,
1153         RTE_FLOW_ITEM_TYPE_RAW,
1154         RTE_FLOW_ITEM_TYPE_RAW,
1155         RTE_FLOW_ITEM_TYPE_RAW,
1156         RTE_FLOW_ITEM_TYPE_VF,
1157         RTE_FLOW_ITEM_TYPE_END,
1158 };
1159
1160 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1161         RTE_FLOW_ITEM_TYPE_ETH,
1162         RTE_FLOW_ITEM_TYPE_VLAN,
1163         RTE_FLOW_ITEM_TYPE_VF,
1164         RTE_FLOW_ITEM_TYPE_END,
1165 };
1166
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1168         RTE_FLOW_ITEM_TYPE_ETH,
1169         RTE_FLOW_ITEM_TYPE_VLAN,
1170         RTE_FLOW_ITEM_TYPE_IPV4,
1171         RTE_FLOW_ITEM_TYPE_VF,
1172         RTE_FLOW_ITEM_TYPE_END,
1173 };
1174
1175 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1176         RTE_FLOW_ITEM_TYPE_ETH,
1177         RTE_FLOW_ITEM_TYPE_VLAN,
1178         RTE_FLOW_ITEM_TYPE_IPV4,
1179         RTE_FLOW_ITEM_TYPE_UDP,
1180         RTE_FLOW_ITEM_TYPE_VF,
1181         RTE_FLOW_ITEM_TYPE_END,
1182 };
1183
1184 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1185         RTE_FLOW_ITEM_TYPE_ETH,
1186         RTE_FLOW_ITEM_TYPE_VLAN,
1187         RTE_FLOW_ITEM_TYPE_IPV4,
1188         RTE_FLOW_ITEM_TYPE_TCP,
1189         RTE_FLOW_ITEM_TYPE_VF,
1190         RTE_FLOW_ITEM_TYPE_END,
1191 };
1192
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1194         RTE_FLOW_ITEM_TYPE_ETH,
1195         RTE_FLOW_ITEM_TYPE_VLAN,
1196         RTE_FLOW_ITEM_TYPE_IPV4,
1197         RTE_FLOW_ITEM_TYPE_SCTP,
1198         RTE_FLOW_ITEM_TYPE_VF,
1199         RTE_FLOW_ITEM_TYPE_END,
1200 };
1201
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1203         RTE_FLOW_ITEM_TYPE_ETH,
1204         RTE_FLOW_ITEM_TYPE_VLAN,
1205         RTE_FLOW_ITEM_TYPE_IPV6,
1206         RTE_FLOW_ITEM_TYPE_VF,
1207         RTE_FLOW_ITEM_TYPE_END,
1208 };
1209
1210 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1211         RTE_FLOW_ITEM_TYPE_ETH,
1212         RTE_FLOW_ITEM_TYPE_VLAN,
1213         RTE_FLOW_ITEM_TYPE_IPV6,
1214         RTE_FLOW_ITEM_TYPE_UDP,
1215         RTE_FLOW_ITEM_TYPE_VF,
1216         RTE_FLOW_ITEM_TYPE_END,
1217 };
1218
1219 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1220         RTE_FLOW_ITEM_TYPE_ETH,
1221         RTE_FLOW_ITEM_TYPE_VLAN,
1222         RTE_FLOW_ITEM_TYPE_IPV6,
1223         RTE_FLOW_ITEM_TYPE_TCP,
1224         RTE_FLOW_ITEM_TYPE_VF,
1225         RTE_FLOW_ITEM_TYPE_END,
1226 };
1227
1228 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1229         RTE_FLOW_ITEM_TYPE_ETH,
1230         RTE_FLOW_ITEM_TYPE_VLAN,
1231         RTE_FLOW_ITEM_TYPE_IPV6,
1232         RTE_FLOW_ITEM_TYPE_SCTP,
1233         RTE_FLOW_ITEM_TYPE_VF,
1234         RTE_FLOW_ITEM_TYPE_END,
1235 };
1236
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1238         RTE_FLOW_ITEM_TYPE_ETH,
1239         RTE_FLOW_ITEM_TYPE_VLAN,
1240         RTE_FLOW_ITEM_TYPE_RAW,
1241         RTE_FLOW_ITEM_TYPE_VF,
1242         RTE_FLOW_ITEM_TYPE_END,
1243 };
1244
1245 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1246         RTE_FLOW_ITEM_TYPE_ETH,
1247         RTE_FLOW_ITEM_TYPE_VLAN,
1248         RTE_FLOW_ITEM_TYPE_RAW,
1249         RTE_FLOW_ITEM_TYPE_RAW,
1250         RTE_FLOW_ITEM_TYPE_VF,
1251         RTE_FLOW_ITEM_TYPE_END,
1252 };
1253
1254 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1255         RTE_FLOW_ITEM_TYPE_ETH,
1256         RTE_FLOW_ITEM_TYPE_VLAN,
1257         RTE_FLOW_ITEM_TYPE_RAW,
1258         RTE_FLOW_ITEM_TYPE_RAW,
1259         RTE_FLOW_ITEM_TYPE_RAW,
1260         RTE_FLOW_ITEM_TYPE_VF,
1261         RTE_FLOW_ITEM_TYPE_END,
1262 };
1263
1264 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1265         RTE_FLOW_ITEM_TYPE_ETH,
1266         RTE_FLOW_ITEM_TYPE_VLAN,
1267         RTE_FLOW_ITEM_TYPE_IPV4,
1268         RTE_FLOW_ITEM_TYPE_RAW,
1269         RTE_FLOW_ITEM_TYPE_VF,
1270         RTE_FLOW_ITEM_TYPE_END,
1271 };
1272
1273 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1274         RTE_FLOW_ITEM_TYPE_ETH,
1275         RTE_FLOW_ITEM_TYPE_VLAN,
1276         RTE_FLOW_ITEM_TYPE_IPV4,
1277         RTE_FLOW_ITEM_TYPE_RAW,
1278         RTE_FLOW_ITEM_TYPE_RAW,
1279         RTE_FLOW_ITEM_TYPE_VF,
1280         RTE_FLOW_ITEM_TYPE_END,
1281 };
1282
1283 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1284         RTE_FLOW_ITEM_TYPE_ETH,
1285         RTE_FLOW_ITEM_TYPE_VLAN,
1286         RTE_FLOW_ITEM_TYPE_IPV4,
1287         RTE_FLOW_ITEM_TYPE_RAW,
1288         RTE_FLOW_ITEM_TYPE_RAW,
1289         RTE_FLOW_ITEM_TYPE_RAW,
1290         RTE_FLOW_ITEM_TYPE_VF,
1291         RTE_FLOW_ITEM_TYPE_END,
1292 };
1293
1294 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1295         RTE_FLOW_ITEM_TYPE_ETH,
1296         RTE_FLOW_ITEM_TYPE_VLAN,
1297         RTE_FLOW_ITEM_TYPE_IPV4,
1298         RTE_FLOW_ITEM_TYPE_UDP,
1299         RTE_FLOW_ITEM_TYPE_RAW,
1300         RTE_FLOW_ITEM_TYPE_VF,
1301         RTE_FLOW_ITEM_TYPE_END,
1302 };
1303
1304 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1305         RTE_FLOW_ITEM_TYPE_ETH,
1306         RTE_FLOW_ITEM_TYPE_VLAN,
1307         RTE_FLOW_ITEM_TYPE_IPV4,
1308         RTE_FLOW_ITEM_TYPE_UDP,
1309         RTE_FLOW_ITEM_TYPE_RAW,
1310         RTE_FLOW_ITEM_TYPE_RAW,
1311         RTE_FLOW_ITEM_TYPE_VF,
1312         RTE_FLOW_ITEM_TYPE_END,
1313 };
1314
1315 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1316         RTE_FLOW_ITEM_TYPE_ETH,
1317         RTE_FLOW_ITEM_TYPE_VLAN,
1318         RTE_FLOW_ITEM_TYPE_IPV4,
1319         RTE_FLOW_ITEM_TYPE_UDP,
1320         RTE_FLOW_ITEM_TYPE_RAW,
1321         RTE_FLOW_ITEM_TYPE_RAW,
1322         RTE_FLOW_ITEM_TYPE_RAW,
1323         RTE_FLOW_ITEM_TYPE_VF,
1324         RTE_FLOW_ITEM_TYPE_END,
1325 };
1326
1327 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1328         RTE_FLOW_ITEM_TYPE_ETH,
1329         RTE_FLOW_ITEM_TYPE_VLAN,
1330         RTE_FLOW_ITEM_TYPE_IPV4,
1331         RTE_FLOW_ITEM_TYPE_TCP,
1332         RTE_FLOW_ITEM_TYPE_RAW,
1333         RTE_FLOW_ITEM_TYPE_VF,
1334         RTE_FLOW_ITEM_TYPE_END,
1335 };
1336
1337 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1338         RTE_FLOW_ITEM_TYPE_ETH,
1339         RTE_FLOW_ITEM_TYPE_VLAN,
1340         RTE_FLOW_ITEM_TYPE_IPV4,
1341         RTE_FLOW_ITEM_TYPE_TCP,
1342         RTE_FLOW_ITEM_TYPE_RAW,
1343         RTE_FLOW_ITEM_TYPE_RAW,
1344         RTE_FLOW_ITEM_TYPE_VF,
1345         RTE_FLOW_ITEM_TYPE_END,
1346 };
1347
1348 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1349         RTE_FLOW_ITEM_TYPE_ETH,
1350         RTE_FLOW_ITEM_TYPE_VLAN,
1351         RTE_FLOW_ITEM_TYPE_IPV4,
1352         RTE_FLOW_ITEM_TYPE_TCP,
1353         RTE_FLOW_ITEM_TYPE_RAW,
1354         RTE_FLOW_ITEM_TYPE_RAW,
1355         RTE_FLOW_ITEM_TYPE_RAW,
1356         RTE_FLOW_ITEM_TYPE_VF,
1357         RTE_FLOW_ITEM_TYPE_END,
1358 };
1359
1360 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1361         RTE_FLOW_ITEM_TYPE_ETH,
1362         RTE_FLOW_ITEM_TYPE_VLAN,
1363         RTE_FLOW_ITEM_TYPE_IPV4,
1364         RTE_FLOW_ITEM_TYPE_SCTP,
1365         RTE_FLOW_ITEM_TYPE_RAW,
1366         RTE_FLOW_ITEM_TYPE_VF,
1367         RTE_FLOW_ITEM_TYPE_END,
1368 };
1369
1370 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1371         RTE_FLOW_ITEM_TYPE_ETH,
1372         RTE_FLOW_ITEM_TYPE_VLAN,
1373         RTE_FLOW_ITEM_TYPE_IPV4,
1374         RTE_FLOW_ITEM_TYPE_SCTP,
1375         RTE_FLOW_ITEM_TYPE_RAW,
1376         RTE_FLOW_ITEM_TYPE_RAW,
1377         RTE_FLOW_ITEM_TYPE_VF,
1378         RTE_FLOW_ITEM_TYPE_END,
1379 };
1380
1381 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1382         RTE_FLOW_ITEM_TYPE_ETH,
1383         RTE_FLOW_ITEM_TYPE_VLAN,
1384         RTE_FLOW_ITEM_TYPE_IPV4,
1385         RTE_FLOW_ITEM_TYPE_SCTP,
1386         RTE_FLOW_ITEM_TYPE_RAW,
1387         RTE_FLOW_ITEM_TYPE_RAW,
1388         RTE_FLOW_ITEM_TYPE_RAW,
1389         RTE_FLOW_ITEM_TYPE_VF,
1390         RTE_FLOW_ITEM_TYPE_END,
1391 };
1392
1393 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1394         RTE_FLOW_ITEM_TYPE_ETH,
1395         RTE_FLOW_ITEM_TYPE_VLAN,
1396         RTE_FLOW_ITEM_TYPE_IPV6,
1397         RTE_FLOW_ITEM_TYPE_RAW,
1398         RTE_FLOW_ITEM_TYPE_VF,
1399         RTE_FLOW_ITEM_TYPE_END,
1400 };
1401
1402 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1403         RTE_FLOW_ITEM_TYPE_ETH,
1404         RTE_FLOW_ITEM_TYPE_VLAN,
1405         RTE_FLOW_ITEM_TYPE_IPV6,
1406         RTE_FLOW_ITEM_TYPE_RAW,
1407         RTE_FLOW_ITEM_TYPE_RAW,
1408         RTE_FLOW_ITEM_TYPE_VF,
1409         RTE_FLOW_ITEM_TYPE_END,
1410 };
1411
1412 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1413         RTE_FLOW_ITEM_TYPE_ETH,
1414         RTE_FLOW_ITEM_TYPE_VLAN,
1415         RTE_FLOW_ITEM_TYPE_IPV6,
1416         RTE_FLOW_ITEM_TYPE_RAW,
1417         RTE_FLOW_ITEM_TYPE_RAW,
1418         RTE_FLOW_ITEM_TYPE_RAW,
1419         RTE_FLOW_ITEM_TYPE_VF,
1420         RTE_FLOW_ITEM_TYPE_END,
1421 };
1422
1423 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1424         RTE_FLOW_ITEM_TYPE_ETH,
1425         RTE_FLOW_ITEM_TYPE_VLAN,
1426         RTE_FLOW_ITEM_TYPE_IPV6,
1427         RTE_FLOW_ITEM_TYPE_UDP,
1428         RTE_FLOW_ITEM_TYPE_RAW,
1429         RTE_FLOW_ITEM_TYPE_VF,
1430         RTE_FLOW_ITEM_TYPE_END,
1431 };
1432
1433 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1434         RTE_FLOW_ITEM_TYPE_ETH,
1435         RTE_FLOW_ITEM_TYPE_VLAN,
1436         RTE_FLOW_ITEM_TYPE_IPV6,
1437         RTE_FLOW_ITEM_TYPE_UDP,
1438         RTE_FLOW_ITEM_TYPE_RAW,
1439         RTE_FLOW_ITEM_TYPE_RAW,
1440         RTE_FLOW_ITEM_TYPE_VF,
1441         RTE_FLOW_ITEM_TYPE_END,
1442 };
1443
1444 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1445         RTE_FLOW_ITEM_TYPE_ETH,
1446         RTE_FLOW_ITEM_TYPE_VLAN,
1447         RTE_FLOW_ITEM_TYPE_IPV6,
1448         RTE_FLOW_ITEM_TYPE_UDP,
1449         RTE_FLOW_ITEM_TYPE_RAW,
1450         RTE_FLOW_ITEM_TYPE_RAW,
1451         RTE_FLOW_ITEM_TYPE_RAW,
1452         RTE_FLOW_ITEM_TYPE_VF,
1453         RTE_FLOW_ITEM_TYPE_END,
1454 };
1455
1456 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1457         RTE_FLOW_ITEM_TYPE_ETH,
1458         RTE_FLOW_ITEM_TYPE_VLAN,
1459         RTE_FLOW_ITEM_TYPE_IPV6,
1460         RTE_FLOW_ITEM_TYPE_TCP,
1461         RTE_FLOW_ITEM_TYPE_RAW,
1462         RTE_FLOW_ITEM_TYPE_VF,
1463         RTE_FLOW_ITEM_TYPE_END,
1464 };
1465
1466 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1467         RTE_FLOW_ITEM_TYPE_ETH,
1468         RTE_FLOW_ITEM_TYPE_VLAN,
1469         RTE_FLOW_ITEM_TYPE_IPV6,
1470         RTE_FLOW_ITEM_TYPE_TCP,
1471         RTE_FLOW_ITEM_TYPE_RAW,
1472         RTE_FLOW_ITEM_TYPE_RAW,
1473         RTE_FLOW_ITEM_TYPE_VF,
1474         RTE_FLOW_ITEM_TYPE_END,
1475 };
1476
1477 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1478         RTE_FLOW_ITEM_TYPE_ETH,
1479         RTE_FLOW_ITEM_TYPE_VLAN,
1480         RTE_FLOW_ITEM_TYPE_IPV6,
1481         RTE_FLOW_ITEM_TYPE_TCP,
1482         RTE_FLOW_ITEM_TYPE_RAW,
1483         RTE_FLOW_ITEM_TYPE_RAW,
1484         RTE_FLOW_ITEM_TYPE_RAW,
1485         RTE_FLOW_ITEM_TYPE_VF,
1486         RTE_FLOW_ITEM_TYPE_END,
1487 };
1488
1489 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1490         RTE_FLOW_ITEM_TYPE_ETH,
1491         RTE_FLOW_ITEM_TYPE_VLAN,
1492         RTE_FLOW_ITEM_TYPE_IPV6,
1493         RTE_FLOW_ITEM_TYPE_SCTP,
1494         RTE_FLOW_ITEM_TYPE_RAW,
1495         RTE_FLOW_ITEM_TYPE_VF,
1496         RTE_FLOW_ITEM_TYPE_END,
1497 };
1498
1499 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1500         RTE_FLOW_ITEM_TYPE_ETH,
1501         RTE_FLOW_ITEM_TYPE_VLAN,
1502         RTE_FLOW_ITEM_TYPE_IPV6,
1503         RTE_FLOW_ITEM_TYPE_SCTP,
1504         RTE_FLOW_ITEM_TYPE_RAW,
1505         RTE_FLOW_ITEM_TYPE_RAW,
1506         RTE_FLOW_ITEM_TYPE_VF,
1507         RTE_FLOW_ITEM_TYPE_END,
1508 };
1509
1510 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1511         RTE_FLOW_ITEM_TYPE_ETH,
1512         RTE_FLOW_ITEM_TYPE_VLAN,
1513         RTE_FLOW_ITEM_TYPE_IPV6,
1514         RTE_FLOW_ITEM_TYPE_SCTP,
1515         RTE_FLOW_ITEM_TYPE_RAW,
1516         RTE_FLOW_ITEM_TYPE_RAW,
1517         RTE_FLOW_ITEM_TYPE_RAW,
1518         RTE_FLOW_ITEM_TYPE_VF,
1519         RTE_FLOW_ITEM_TYPE_END,
1520 };
1521
1522 /* Pattern matched tunnel filter */
1523 static enum rte_flow_item_type pattern_vxlan_1[] = {
1524         RTE_FLOW_ITEM_TYPE_ETH,
1525         RTE_FLOW_ITEM_TYPE_IPV4,
1526         RTE_FLOW_ITEM_TYPE_UDP,
1527         RTE_FLOW_ITEM_TYPE_VXLAN,
1528         RTE_FLOW_ITEM_TYPE_ETH,
1529         RTE_FLOW_ITEM_TYPE_END,
1530 };
1531
1532 static enum rte_flow_item_type pattern_vxlan_2[] = {
1533         RTE_FLOW_ITEM_TYPE_ETH,
1534         RTE_FLOW_ITEM_TYPE_IPV6,
1535         RTE_FLOW_ITEM_TYPE_UDP,
1536         RTE_FLOW_ITEM_TYPE_VXLAN,
1537         RTE_FLOW_ITEM_TYPE_ETH,
1538         RTE_FLOW_ITEM_TYPE_END,
1539 };
1540
1541 static enum rte_flow_item_type pattern_vxlan_3[] = {
1542         RTE_FLOW_ITEM_TYPE_ETH,
1543         RTE_FLOW_ITEM_TYPE_IPV4,
1544         RTE_FLOW_ITEM_TYPE_UDP,
1545         RTE_FLOW_ITEM_TYPE_VXLAN,
1546         RTE_FLOW_ITEM_TYPE_ETH,
1547         RTE_FLOW_ITEM_TYPE_VLAN,
1548         RTE_FLOW_ITEM_TYPE_END,
1549 };
1550
1551 static enum rte_flow_item_type pattern_vxlan_4[] = {
1552         RTE_FLOW_ITEM_TYPE_ETH,
1553         RTE_FLOW_ITEM_TYPE_IPV6,
1554         RTE_FLOW_ITEM_TYPE_UDP,
1555         RTE_FLOW_ITEM_TYPE_VXLAN,
1556         RTE_FLOW_ITEM_TYPE_ETH,
1557         RTE_FLOW_ITEM_TYPE_VLAN,
1558         RTE_FLOW_ITEM_TYPE_END,
1559 };
1560
1561 static enum rte_flow_item_type pattern_nvgre_1[] = {
1562         RTE_FLOW_ITEM_TYPE_ETH,
1563         RTE_FLOW_ITEM_TYPE_IPV4,
1564         RTE_FLOW_ITEM_TYPE_NVGRE,
1565         RTE_FLOW_ITEM_TYPE_ETH,
1566         RTE_FLOW_ITEM_TYPE_END,
1567 };
1568
1569 static enum rte_flow_item_type pattern_nvgre_2[] = {
1570         RTE_FLOW_ITEM_TYPE_ETH,
1571         RTE_FLOW_ITEM_TYPE_IPV6,
1572         RTE_FLOW_ITEM_TYPE_NVGRE,
1573         RTE_FLOW_ITEM_TYPE_ETH,
1574         RTE_FLOW_ITEM_TYPE_END,
1575 };
1576
1577 static enum rte_flow_item_type pattern_nvgre_3[] = {
1578         RTE_FLOW_ITEM_TYPE_ETH,
1579         RTE_FLOW_ITEM_TYPE_IPV4,
1580         RTE_FLOW_ITEM_TYPE_NVGRE,
1581         RTE_FLOW_ITEM_TYPE_ETH,
1582         RTE_FLOW_ITEM_TYPE_VLAN,
1583         RTE_FLOW_ITEM_TYPE_END,
1584 };
1585
1586 static enum rte_flow_item_type pattern_nvgre_4[] = {
1587         RTE_FLOW_ITEM_TYPE_ETH,
1588         RTE_FLOW_ITEM_TYPE_IPV6,
1589         RTE_FLOW_ITEM_TYPE_NVGRE,
1590         RTE_FLOW_ITEM_TYPE_ETH,
1591         RTE_FLOW_ITEM_TYPE_VLAN,
1592         RTE_FLOW_ITEM_TYPE_END,
1593 };
1594
1595 static enum rte_flow_item_type pattern_mpls_1[] = {
1596         RTE_FLOW_ITEM_TYPE_ETH,
1597         RTE_FLOW_ITEM_TYPE_IPV4,
1598         RTE_FLOW_ITEM_TYPE_UDP,
1599         RTE_FLOW_ITEM_TYPE_MPLS,
1600         RTE_FLOW_ITEM_TYPE_END,
1601 };
1602
1603 static enum rte_flow_item_type pattern_mpls_2[] = {
1604         RTE_FLOW_ITEM_TYPE_ETH,
1605         RTE_FLOW_ITEM_TYPE_IPV6,
1606         RTE_FLOW_ITEM_TYPE_UDP,
1607         RTE_FLOW_ITEM_TYPE_MPLS,
1608         RTE_FLOW_ITEM_TYPE_END,
1609 };
1610
1611 static enum rte_flow_item_type pattern_mpls_3[] = {
1612         RTE_FLOW_ITEM_TYPE_ETH,
1613         RTE_FLOW_ITEM_TYPE_IPV4,
1614         RTE_FLOW_ITEM_TYPE_GRE,
1615         RTE_FLOW_ITEM_TYPE_MPLS,
1616         RTE_FLOW_ITEM_TYPE_END,
1617 };
1618
1619 static enum rte_flow_item_type pattern_mpls_4[] = {
1620         RTE_FLOW_ITEM_TYPE_ETH,
1621         RTE_FLOW_ITEM_TYPE_IPV6,
1622         RTE_FLOW_ITEM_TYPE_GRE,
1623         RTE_FLOW_ITEM_TYPE_MPLS,
1624         RTE_FLOW_ITEM_TYPE_END,
1625 };
1626
1627 static enum rte_flow_item_type pattern_qinq_1[] = {
1628         RTE_FLOW_ITEM_TYPE_ETH,
1629         RTE_FLOW_ITEM_TYPE_VLAN,
1630         RTE_FLOW_ITEM_TYPE_VLAN,
1631         RTE_FLOW_ITEM_TYPE_END,
1632 };
1633
1634 static enum rte_flow_item_type pattern_fdir_ipv4_l2tpv3oip[] = {
1635         RTE_FLOW_ITEM_TYPE_ETH,
1636         RTE_FLOW_ITEM_TYPE_IPV4,
1637         RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1638         RTE_FLOW_ITEM_TYPE_END,
1639 };
1640
1641 static enum rte_flow_item_type pattern_fdir_ipv6_l2tpv3oip[] = {
1642         RTE_FLOW_ITEM_TYPE_ETH,
1643         RTE_FLOW_ITEM_TYPE_IPV6,
1644         RTE_FLOW_ITEM_TYPE_L2TPV3OIP,
1645         RTE_FLOW_ITEM_TYPE_END,
1646 };
1647
1648 static enum rte_flow_item_type pattern_fdir_ipv4_esp[] = {
1649         RTE_FLOW_ITEM_TYPE_ETH,
1650         RTE_FLOW_ITEM_TYPE_IPV4,
1651         RTE_FLOW_ITEM_TYPE_ESP,
1652         RTE_FLOW_ITEM_TYPE_END,
1653 };
1654
1655 static enum rte_flow_item_type pattern_fdir_ipv6_esp[] = {
1656         RTE_FLOW_ITEM_TYPE_ETH,
1657         RTE_FLOW_ITEM_TYPE_IPV6,
1658         RTE_FLOW_ITEM_TYPE_ESP,
1659         RTE_FLOW_ITEM_TYPE_END,
1660 };
1661
1662 static enum rte_flow_item_type pattern_fdir_ipv4_udp_esp[] = {
1663         RTE_FLOW_ITEM_TYPE_ETH,
1664         RTE_FLOW_ITEM_TYPE_IPV4,
1665         RTE_FLOW_ITEM_TYPE_UDP,
1666         RTE_FLOW_ITEM_TYPE_ESP,
1667         RTE_FLOW_ITEM_TYPE_END,
1668 };
1669
1670 static enum rte_flow_item_type pattern_fdir_ipv6_udp_esp[] = {
1671         RTE_FLOW_ITEM_TYPE_ETH,
1672         RTE_FLOW_ITEM_TYPE_IPV6,
1673         RTE_FLOW_ITEM_TYPE_UDP,
1674         RTE_FLOW_ITEM_TYPE_ESP,
1675         RTE_FLOW_ITEM_TYPE_END,
1676 };
1677
1678 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1679         /* Ethertype */
1680         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1681         /* FDIR - support default flow type without flexible payload*/
1682         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_ipv4_esp, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_ipv4_udp_esp, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_ipv6_esp, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_ipv6_udp_esp, i40e_flow_parse_fdir_filter },
1703         /* FDIR - support default flow type with flexible payload */
1704         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1705         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1731         /* FDIR - support single vlan input set */
1732         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1768         /* FDIR - support VF item */
1769         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1776         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1777         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1778         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1779         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1780         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1781         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1782         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1783         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1784         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1785         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1786         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1787         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1788         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1789         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1790         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1791         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1792         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1793         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1794         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1795         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1796         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1797         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1798         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1799         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1800         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1801         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1802         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1803         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1804         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1805         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1806         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1807         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1808         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1809         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1810         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1811         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1812         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1813         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1814         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1815         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1816         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1817         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1818         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1819         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1820         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1821         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1822         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1823         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1824         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1825         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1826         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1827         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1828         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1829         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1830         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1831         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1832         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1833         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1834         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1835         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1836         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1837         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1838         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1839         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1840         /* VXLAN */
1841         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1842         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1843         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1844         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1845         /* NVGRE */
1846         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1847         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1848         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1849         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1850         /* MPLSoUDP & MPLSoGRE */
1851         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1852         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1853         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1854         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1855         /* GTP-C & GTP-U */
1856         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1857         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1858         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1859         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1860         /* QINQ */
1861         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1862         /* L2TPv3 over IP */
1863         { pattern_fdir_ipv4_l2tpv3oip, i40e_flow_parse_fdir_filter },
1864         { pattern_fdir_ipv6_l2tpv3oip, i40e_flow_parse_fdir_filter },
1865         /* L4 over port */
1866         { pattern_fdir_ipv4_udp, i40e_flow_parse_l4_cloud_filter },
1867         { pattern_fdir_ipv4_tcp, i40e_flow_parse_l4_cloud_filter },
1868         { pattern_fdir_ipv4_sctp, i40e_flow_parse_l4_cloud_filter },
1869         { pattern_fdir_ipv6_udp, i40e_flow_parse_l4_cloud_filter },
1870         { pattern_fdir_ipv6_tcp, i40e_flow_parse_l4_cloud_filter },
1871         { pattern_fdir_ipv6_sctp, i40e_flow_parse_l4_cloud_filter },
1872 };
1873
1874 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1875         do {                                                            \
1876                 act = actions + index;                                  \
1877                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1878                         index++;                                        \
1879                         act = actions + index;                          \
1880                 }                                                       \
1881         } while (0)
1882
1883 /* Find the first VOID or non-VOID item pointer */
1884 static const struct rte_flow_item *
1885 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1886 {
1887         bool is_find;
1888
1889         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1890                 if (is_void)
1891                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1892                 else
1893                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1894                 if (is_find)
1895                         break;
1896                 item++;
1897         }
1898         return item;
1899 }
1900
1901 /* Skip all VOID items of the pattern */
1902 static void
1903 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1904                             const struct rte_flow_item *pattern)
1905 {
1906         uint32_t cpy_count = 0;
1907         const struct rte_flow_item *pb = pattern, *pe = pattern;
1908
1909         for (;;) {
1910                 /* Find a non-void item first */
1911                 pb = i40e_find_first_item(pb, false);
1912                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1913                         pe = pb;
1914                         break;
1915                 }
1916
1917                 /* Find a void item */
1918                 pe = i40e_find_first_item(pb + 1, true);
1919
1920                 cpy_count = pe - pb;
1921                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1922
1923                 items += cpy_count;
1924
1925                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1926                         pb = pe;
1927                         break;
1928                 }
1929
1930                 pb = pe + 1;
1931         }
1932         /* Copy the END item. */
1933         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1934 }
1935
1936 /* Check if the pattern matches a supported item type array */
1937 static bool
1938 i40e_match_pattern(enum rte_flow_item_type *item_array,
1939                    struct rte_flow_item *pattern)
1940 {
1941         struct rte_flow_item *item = pattern;
1942
1943         while ((*item_array == item->type) &&
1944                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1945                 item_array++;
1946                 item++;
1947         }
1948
1949         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1950                 item->type == RTE_FLOW_ITEM_TYPE_END);
1951 }
1952
1953 /* Find if there's parse filter function matched */
1954 static parse_filter_t
1955 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1956 {
1957         parse_filter_t parse_filter = NULL;
1958         uint8_t i = *idx;
1959
1960         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1961                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1962                                         pattern)) {
1963                         parse_filter = i40e_supported_patterns[i].parse_filter;
1964                         break;
1965                 }
1966         }
1967
1968         *idx = ++i;
1969
1970         return parse_filter;
1971 }
1972
1973 /* Parse attributes */
1974 static int
1975 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1976                      struct rte_flow_error *error)
1977 {
1978         /* Must be input direction */
1979         if (!attr->ingress) {
1980                 rte_flow_error_set(error, EINVAL,
1981                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1982                                    attr, "Only support ingress.");
1983                 return -rte_errno;
1984         }
1985
1986         /* Not supported */
1987         if (attr->egress) {
1988                 rte_flow_error_set(error, EINVAL,
1989                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1990                                    attr, "Not support egress.");
1991                 return -rte_errno;
1992         }
1993
1994         /* Not supported */
1995         if (attr->priority) {
1996                 rte_flow_error_set(error, EINVAL,
1997                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1998                                    attr, "Not support priority.");
1999                 return -rte_errno;
2000         }
2001
2002         /* Not supported */
2003         if (attr->group) {
2004                 rte_flow_error_set(error, EINVAL,
2005                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
2006                                    attr, "Not support group.");
2007                 return -rte_errno;
2008         }
2009
2010         return 0;
2011 }
2012
2013 static uint16_t
2014 i40e_get_outer_vlan(struct rte_eth_dev *dev)
2015 {
2016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         int qinq = dev->data->dev_conf.rxmode.offloads &
2018                 DEV_RX_OFFLOAD_VLAN_EXTEND;
2019         uint64_t reg_r = 0;
2020         uint16_t reg_id;
2021         uint16_t tpid;
2022
2023         if (qinq)
2024                 reg_id = 2;
2025         else
2026                 reg_id = 3;
2027
2028         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2029                                     &reg_r, NULL);
2030
2031         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
2032
2033         return tpid;
2034 }
2035
2036 /* 1. Last in item should be NULL as range is not supported.
2037  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
2038  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
2039  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
2040  *    FF:FF:FF:FF:FF:FF
2041  * 5. Ether_type mask should be 0xFFFF.
2042  */
2043 static int
2044 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
2045                                   const struct rte_flow_item *pattern,
2046                                   struct rte_flow_error *error,
2047                                   struct rte_eth_ethertype_filter *filter)
2048 {
2049         const struct rte_flow_item *item = pattern;
2050         const struct rte_flow_item_eth *eth_spec;
2051         const struct rte_flow_item_eth *eth_mask;
2052         enum rte_flow_item_type item_type;
2053
2054         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2055                 if (item->last) {
2056                         rte_flow_error_set(error, EINVAL,
2057                                            RTE_FLOW_ERROR_TYPE_ITEM,
2058                                            item,
2059                                            "Not support range");
2060                         return -rte_errno;
2061                 }
2062                 item_type = item->type;
2063                 switch (item_type) {
2064                 case RTE_FLOW_ITEM_TYPE_ETH:
2065                         eth_spec = item->spec;
2066                         eth_mask = item->mask;
2067                         /* Get the MAC info. */
2068                         if (!eth_spec || !eth_mask) {
2069                                 rte_flow_error_set(error, EINVAL,
2070                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2071                                                    item,
2072                                                    "NULL ETH spec/mask");
2073                                 return -rte_errno;
2074                         }
2075
2076                         /* Mask bits of source MAC address must be full of 0.
2077                          * Mask bits of destination MAC address must be full
2078                          * of 1 or full of 0.
2079                          */
2080                         if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2081                             (!rte_is_zero_ether_addr(&eth_mask->dst) &&
2082                              !rte_is_broadcast_ether_addr(&eth_mask->dst))) {
2083                                 rte_flow_error_set(error, EINVAL,
2084                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2085                                                    item,
2086                                                    "Invalid MAC_addr mask");
2087                                 return -rte_errno;
2088                         }
2089
2090                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2091                                 rte_flow_error_set(error, EINVAL,
2092                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2093                                                    item,
2094                                                    "Invalid ethertype mask");
2095                                 return -rte_errno;
2096                         }
2097
2098                         /* If mask bits of destination MAC address
2099                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2100                          */
2101                         if (rte_is_broadcast_ether_addr(&eth_mask->dst)) {
2102                                 filter->mac_addr = eth_spec->dst;
2103                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2104                         } else {
2105                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2106                         }
2107                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2108
2109                         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2110                             filter->ether_type == RTE_ETHER_TYPE_IPV6 ||
2111                             filter->ether_type == RTE_ETHER_TYPE_LLDP ||
2112                             filter->ether_type == i40e_get_outer_vlan(dev)) {
2113                                 rte_flow_error_set(error, EINVAL,
2114                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2115                                                    item,
2116                                                    "Unsupported ether_type in"
2117                                                    " control packet filter.");
2118                                 return -rte_errno;
2119                         }
2120                         break;
2121                 default:
2122                         break;
2123                 }
2124         }
2125
2126         return 0;
2127 }
2128
2129 /* Ethertype action only supports QUEUE or DROP. */
2130 static int
2131 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2132                                  const struct rte_flow_action *actions,
2133                                  struct rte_flow_error *error,
2134                                  struct rte_eth_ethertype_filter *filter)
2135 {
2136         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2137         const struct rte_flow_action *act;
2138         const struct rte_flow_action_queue *act_q;
2139         uint32_t index = 0;
2140
2141         /* Check if the first non-void action is QUEUE or DROP. */
2142         NEXT_ITEM_OF_ACTION(act, actions, index);
2143         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2144             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2145                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2146                                    act, "Not supported action.");
2147                 return -rte_errno;
2148         }
2149
2150         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2151                 act_q = act->conf;
2152                 filter->queue = act_q->index;
2153                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2154                         rte_flow_error_set(error, EINVAL,
2155                                            RTE_FLOW_ERROR_TYPE_ACTION,
2156                                            act, "Invalid queue ID for"
2157                                            " ethertype_filter.");
2158                         return -rte_errno;
2159                 }
2160         } else {
2161                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2162         }
2163
2164         /* Check if the next non-void item is END */
2165         index++;
2166         NEXT_ITEM_OF_ACTION(act, actions, index);
2167         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2168                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2169                                    act, "Not supported action.");
2170                 return -rte_errno;
2171         }
2172
2173         return 0;
2174 }
2175
2176 static int
2177 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2178                                  const struct rte_flow_attr *attr,
2179                                  const struct rte_flow_item pattern[],
2180                                  const struct rte_flow_action actions[],
2181                                  struct rte_flow_error *error,
2182                                  union i40e_filter_t *filter)
2183 {
2184         struct rte_eth_ethertype_filter *ethertype_filter =
2185                 &filter->ethertype_filter;
2186         int ret;
2187
2188         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2189                                                 ethertype_filter);
2190         if (ret)
2191                 return ret;
2192
2193         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2194                                                ethertype_filter);
2195         if (ret)
2196                 return ret;
2197
2198         ret = i40e_flow_parse_attr(attr, error);
2199         if (ret)
2200                 return ret;
2201
2202         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2203
2204         return ret;
2205 }
2206
2207 static int
2208 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2209                          const struct rte_flow_item_raw *raw_spec,
2210                          struct rte_flow_error *error)
2211 {
2212         if (!raw_spec->relative) {
2213                 rte_flow_error_set(error, EINVAL,
2214                                    RTE_FLOW_ERROR_TYPE_ITEM,
2215                                    item,
2216                                    "Relative should be 1.");
2217                 return -rte_errno;
2218         }
2219
2220         if (raw_spec->offset % sizeof(uint16_t)) {
2221                 rte_flow_error_set(error, EINVAL,
2222                                    RTE_FLOW_ERROR_TYPE_ITEM,
2223                                    item,
2224                                    "Offset should be even.");
2225                 return -rte_errno;
2226         }
2227
2228         if (raw_spec->search || raw_spec->limit) {
2229                 rte_flow_error_set(error, EINVAL,
2230                                    RTE_FLOW_ERROR_TYPE_ITEM,
2231                                    item,
2232                                    "search or limit is not supported.");
2233                 return -rte_errno;
2234         }
2235
2236         if (raw_spec->offset < 0) {
2237                 rte_flow_error_set(error, EINVAL,
2238                                    RTE_FLOW_ERROR_TYPE_ITEM,
2239                                    item,
2240                                    "Offset should be non-negative.");
2241                 return -rte_errno;
2242         }
2243         return 0;
2244 }
2245
2246 static int
2247 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2248                          enum i40e_filter_pctype pctype,
2249                          uint64_t input_set)
2250 {
2251         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2252         uint64_t inset_reg = 0;
2253         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2254         int i, num;
2255
2256         /* Check if the input set is valid */
2257         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2258                                     input_set) != 0) {
2259                 PMD_DRV_LOG(ERR, "Invalid input set");
2260                 return -EINVAL;
2261         }
2262
2263         /* Check if the configuration is conflicted */
2264         if (pf->fdir.inset_flag[pctype] &&
2265             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2266                 return -1;
2267
2268         if (pf->fdir.inset_flag[pctype] &&
2269             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2270                 return 0;
2271
2272         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2273                                            I40E_INSET_MASK_NUM_REG);
2274         if (num < 0)
2275                 return -EINVAL;
2276
2277         if (pf->support_multi_driver) {
2278                 for (i = 0; i < num; i++)
2279                         if (i40e_read_rx_ctl(hw,
2280                                         I40E_GLQF_FD_MSK(i, pctype)) !=
2281                                         mask_reg[i]) {
2282                                 PMD_DRV_LOG(ERR, "Input set setting is not"
2283                                                 " supported with"
2284                                                 " `support-multi-driver`"
2285                                                 " enabled!");
2286                                 return -EPERM;
2287                         }
2288                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2289                         if (i40e_read_rx_ctl(hw,
2290                                         I40E_GLQF_FD_MSK(i, pctype)) != 0) {
2291                                 PMD_DRV_LOG(ERR, "Input set setting is not"
2292                                                 " supported with"
2293                                                 " `support-multi-driver`"
2294                                                 " enabled!");
2295                                 return -EPERM;
2296                         }
2297
2298         } else {
2299                 for (i = 0; i < num; i++)
2300                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2301                                 mask_reg[i]);
2302                 /*clear unused mask registers of the pctype */
2303                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2304                         i40e_check_write_reg(hw,
2305                                         I40E_GLQF_FD_MSK(i, pctype), 0);
2306         }
2307
2308         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2309
2310         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2311                              (uint32_t)(inset_reg & UINT32_MAX));
2312         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2313                              (uint32_t)((inset_reg >>
2314                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2315
2316         I40E_WRITE_FLUSH(hw);
2317
2318         pf->fdir.input_set[pctype] = input_set;
2319         pf->fdir.inset_flag[pctype] = 1;
2320         return 0;
2321 }
2322
2323 static uint8_t
2324 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2325                                 enum rte_flow_item_type item_type,
2326                                 struct i40e_fdir_filter_conf *filter)
2327 {
2328         struct i40e_customized_pctype *cus_pctype = NULL;
2329
2330         switch (item_type) {
2331         case RTE_FLOW_ITEM_TYPE_GTPC:
2332                 cus_pctype = i40e_find_customized_pctype(pf,
2333                                                          I40E_CUSTOMIZED_GTPC);
2334                 break;
2335         case RTE_FLOW_ITEM_TYPE_GTPU:
2336                 if (!filter->input.flow_ext.inner_ip)
2337                         cus_pctype = i40e_find_customized_pctype(pf,
2338                                                          I40E_CUSTOMIZED_GTPU);
2339                 else if (filter->input.flow_ext.iip_type ==
2340                          I40E_FDIR_IPTYPE_IPV4)
2341                         cus_pctype = i40e_find_customized_pctype(pf,
2342                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2343                 else if (filter->input.flow_ext.iip_type ==
2344                          I40E_FDIR_IPTYPE_IPV6)
2345                         cus_pctype = i40e_find_customized_pctype(pf,
2346                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2347                 break;
2348         case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
2349                 if (filter->input.flow_ext.oip_type == I40E_FDIR_IPTYPE_IPV4)
2350                         cus_pctype = i40e_find_customized_pctype(pf,
2351                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
2352                 else if (filter->input.flow_ext.oip_type ==
2353                          I40E_FDIR_IPTYPE_IPV6)
2354                         cus_pctype = i40e_find_customized_pctype(pf,
2355                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
2356                 break;
2357         case RTE_FLOW_ITEM_TYPE_ESP:
2358                 if (!filter->input.flow_ext.is_udp) {
2359                         if (filter->input.flow_ext.oip_type ==
2360                                 I40E_FDIR_IPTYPE_IPV4)
2361                                 cus_pctype = i40e_find_customized_pctype(pf,
2362                                                 I40E_CUSTOMIZED_ESP_IPV4);
2363                         else if (filter->input.flow_ext.oip_type ==
2364                                 I40E_FDIR_IPTYPE_IPV6)
2365                                 cus_pctype = i40e_find_customized_pctype(pf,
2366                                                 I40E_CUSTOMIZED_ESP_IPV6);
2367                 } else {
2368                         if (filter->input.flow_ext.oip_type ==
2369                                 I40E_FDIR_IPTYPE_IPV4)
2370                                 cus_pctype = i40e_find_customized_pctype(pf,
2371                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
2372                         else if (filter->input.flow_ext.oip_type ==
2373                                         I40E_FDIR_IPTYPE_IPV6)
2374                                 cus_pctype = i40e_find_customized_pctype(pf,
2375                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
2376                         filter->input.flow_ext.is_udp = false;
2377                 }
2378                 break;
2379         default:
2380                 PMD_DRV_LOG(ERR, "Unsupported item type");
2381                 break;
2382         }
2383
2384         if (cus_pctype && cus_pctype->valid)
2385                 return cus_pctype->pctype;
2386
2387         return I40E_FILTER_PCTYPE_INVALID;
2388 }
2389
2390 static void
2391 i40e_flow_set_filter_spi(struct i40e_fdir_filter_conf *filter,
2392         const struct rte_flow_item_esp *esp_spec)
2393 {
2394         if (filter->input.flow_ext.oip_type ==
2395                 I40E_FDIR_IPTYPE_IPV4) {
2396                 if (filter->input.flow_ext.is_udp)
2397                         filter->input.flow.esp_ipv4_udp_flow.spi =
2398                                 esp_spec->hdr.spi;
2399                 else
2400                         filter->input.flow.esp_ipv4_flow.spi =
2401                                 esp_spec->hdr.spi;
2402         }
2403         if (filter->input.flow_ext.oip_type ==
2404                 I40E_FDIR_IPTYPE_IPV6) {
2405                 if (filter->input.flow_ext.is_udp)
2406                         filter->input.flow.esp_ipv6_udp_flow.spi =
2407                                 esp_spec->hdr.spi;
2408                 else
2409                         filter->input.flow.esp_ipv6_flow.spi =
2410                                 esp_spec->hdr.spi;
2411         }
2412 }
2413
2414 /* 1. Last in item should be NULL as range is not supported.
2415  * 2. Supported patterns: refer to array i40e_supported_patterns.
2416  * 3. Default supported flow type and input set: refer to array
2417  *    valid_fdir_inset_table in i40e_ethdev.c.
2418  * 4. Mask of fields which need to be matched should be
2419  *    filled with 1.
2420  * 5. Mask of fields which needn't to be matched should be
2421  *    filled with 0.
2422  * 6. GTP profile supports GTPv1 only.
2423  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2424  */
2425 static int
2426 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2427                              const struct rte_flow_attr *attr,
2428                              const struct rte_flow_item *pattern,
2429                              struct rte_flow_error *error,
2430                              struct i40e_fdir_filter_conf *filter)
2431 {
2432         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2433         const struct rte_flow_item *item = pattern;
2434         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2435         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2436         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2437         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2438         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2439         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2440         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2441         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2442         const struct rte_flow_item_esp *esp_spec, *esp_mask;
2443         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2444         const struct rte_flow_item_vf *vf_spec;
2445         const struct rte_flow_item_l2tpv3oip *l2tpv3oip_spec, *l2tpv3oip_mask;
2446
2447         uint8_t pctype = 0;
2448         uint64_t input_set = I40E_INSET_NONE;
2449         uint16_t frag_off;
2450         enum rte_flow_item_type item_type;
2451         enum rte_flow_item_type next_type;
2452         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2453         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2454         uint32_t i, j;
2455         uint8_t  ipv6_addr_mask[16] = {
2456                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2457                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2458         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2459         uint8_t raw_id = 0;
2460         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2461         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2462         struct i40e_fdir_flex_pit flex_pit;
2463         uint8_t next_dst_off = 0;
2464         uint16_t flex_size;
2465         uint16_t ether_type;
2466         uint32_t vtc_flow_cpu;
2467         bool outer_ip = true;
2468         uint8_t field_idx;
2469         int ret;
2470
2471         memset(off_arr, 0, sizeof(off_arr));
2472         memset(len_arr, 0, sizeof(len_arr));
2473         filter->input.flow_ext.customized_pctype = false;
2474         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2475                 if (item->last) {
2476                         rte_flow_error_set(error, EINVAL,
2477                                            RTE_FLOW_ERROR_TYPE_ITEM,
2478                                            item,
2479                                            "Not support range");
2480                         return -rte_errno;
2481                 }
2482                 item_type = item->type;
2483                 switch (item_type) {
2484                 case RTE_FLOW_ITEM_TYPE_ETH:
2485                         eth_spec = item->spec;
2486                         eth_mask = item->mask;
2487                         next_type = (item + 1)->type;
2488
2489                         if (next_type == RTE_FLOW_ITEM_TYPE_END &&
2490                                                 (!eth_spec || !eth_mask)) {
2491                                 rte_flow_error_set(error, EINVAL,
2492                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2493                                                    item,
2494                                                    "NULL eth spec/mask.");
2495                                 return -rte_errno;
2496                         }
2497
2498                         if (eth_spec && eth_mask) {
2499                                 if (rte_is_broadcast_ether_addr(&eth_mask->dst) &&
2500                                         rte_is_zero_ether_addr(&eth_mask->src)) {
2501                                         filter->input.flow.l2_flow.dst =
2502                                                 eth_spec->dst;
2503                                         input_set |= I40E_INSET_DMAC;
2504                                 } else if (rte_is_zero_ether_addr(&eth_mask->dst) &&
2505                                         rte_is_broadcast_ether_addr(&eth_mask->src)) {
2506                                         filter->input.flow.l2_flow.src =
2507                                                 eth_spec->src;
2508                                         input_set |= I40E_INSET_SMAC;
2509                                 } else if (rte_is_broadcast_ether_addr(&eth_mask->dst) &&
2510                                         rte_is_broadcast_ether_addr(&eth_mask->src)) {
2511                                         filter->input.flow.l2_flow.dst =
2512                                                 eth_spec->dst;
2513                                         filter->input.flow.l2_flow.src =
2514                                                 eth_spec->src;
2515                                         input_set |= (I40E_INSET_DMAC | I40E_INSET_SMAC);
2516                                 } else if (!rte_is_zero_ether_addr(&eth_mask->src) ||
2517                                            !rte_is_zero_ether_addr(&eth_mask->dst)) {
2518                                         rte_flow_error_set(error, EINVAL,
2519                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2520                                                       item,
2521                                                       "Invalid MAC_addr mask.");
2522                                         return -rte_errno;
2523                                 }
2524                         }
2525                         if (eth_spec && eth_mask &&
2526                         next_type == RTE_FLOW_ITEM_TYPE_END) {
2527                                 if (eth_mask->type != RTE_BE16(0xffff)) {
2528                                         rte_flow_error_set(error, EINVAL,
2529                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2530                                                       item,
2531                                                       "Invalid type mask.");
2532                                         return -rte_errno;
2533                                 }
2534
2535                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2536
2537                                 if (next_type == RTE_FLOW_ITEM_TYPE_VLAN ||
2538                                     ether_type == RTE_ETHER_TYPE_IPV4 ||
2539                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2540                                     ether_type == i40e_get_outer_vlan(dev)) {
2541                                         rte_flow_error_set(error, EINVAL,
2542                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2543                                                      item,
2544                                                      "Unsupported ether_type.");
2545                                         return -rte_errno;
2546                                 }
2547                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2548                                 filter->input.flow.l2_flow.ether_type =
2549                                         eth_spec->type;
2550                         }
2551
2552                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2553                         layer_idx = I40E_FLXPLD_L2_IDX;
2554
2555                         break;
2556                 case RTE_FLOW_ITEM_TYPE_VLAN:
2557                         vlan_spec = item->spec;
2558                         vlan_mask = item->mask;
2559
2560                         RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2561                         if (vlan_spec && vlan_mask) {
2562                                 if (vlan_mask->tci !=
2563                                     rte_cpu_to_be_16(I40E_VLAN_TCI_MASK) &&
2564                                     vlan_mask->tci !=
2565                                     rte_cpu_to_be_16(I40E_VLAN_PRI_MASK) &&
2566                                     vlan_mask->tci !=
2567                                     rte_cpu_to_be_16(I40E_VLAN_CFI_MASK) &&
2568                                     vlan_mask->tci !=
2569                                     rte_cpu_to_be_16(I40E_VLAN_VID_MASK)) {
2570                                         rte_flow_error_set(error, EINVAL,
2571                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2572                                                    item,
2573                                                    "Unsupported TCI mask.");
2574                                 }
2575                                 input_set |= I40E_INSET_VLAN_INNER;
2576                                 filter->input.flow_ext.vlan_tci =
2577                                         vlan_spec->tci;
2578                         }
2579                         if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2580                                 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2581                                         rte_flow_error_set(error, EINVAL,
2582                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2583                                                       item,
2584                                                       "Invalid inner_type"
2585                                                       " mask.");
2586                                         return -rte_errno;
2587                                 }
2588
2589                                 ether_type =
2590                                         rte_be_to_cpu_16(vlan_spec->inner_type);
2591
2592                                 if (ether_type == RTE_ETHER_TYPE_IPV4 ||
2593                                     ether_type == RTE_ETHER_TYPE_IPV6 ||
2594                                     ether_type == i40e_get_outer_vlan(dev)) {
2595                                         rte_flow_error_set(error, EINVAL,
2596                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2597                                                      item,
2598                                                      "Unsupported inner_type.");
2599                                         return -rte_errno;
2600                                 }
2601                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2602                                 filter->input.flow.l2_flow.ether_type =
2603                                         vlan_spec->inner_type;
2604                         }
2605
2606                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2607                         layer_idx = I40E_FLXPLD_L2_IDX;
2608
2609                         break;
2610                 case RTE_FLOW_ITEM_TYPE_IPV4:
2611                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2612                         ipv4_spec = item->spec;
2613                         ipv4_mask = item->mask;
2614                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2615                         layer_idx = I40E_FLXPLD_L3_IDX;
2616
2617                         if (ipv4_spec && ipv4_mask && outer_ip) {
2618                                 /* Check IPv4 mask and update input set */
2619                                 if (ipv4_mask->hdr.version_ihl ||
2620                                     ipv4_mask->hdr.total_length ||
2621                                     ipv4_mask->hdr.packet_id ||
2622                                     ipv4_mask->hdr.fragment_offset ||
2623                                     ipv4_mask->hdr.hdr_checksum) {
2624                                         rte_flow_error_set(error, EINVAL,
2625                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2626                                                    item,
2627                                                    "Invalid IPv4 mask.");
2628                                         return -rte_errno;
2629                                 }
2630
2631                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2632                                         input_set |= I40E_INSET_IPV4_SRC;
2633                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2634                                         input_set |= I40E_INSET_IPV4_DST;
2635                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2636                                         input_set |= I40E_INSET_IPV4_TOS;
2637                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2638                                         input_set |= I40E_INSET_IPV4_TTL;
2639                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2640                                         input_set |= I40E_INSET_IPV4_PROTO;
2641
2642                                 /* Check if it is fragment. */
2643                                 frag_off = ipv4_spec->hdr.fragment_offset;
2644                                 frag_off = rte_be_to_cpu_16(frag_off);
2645                                 if (frag_off & RTE_IPV4_HDR_OFFSET_MASK ||
2646                                     frag_off & RTE_IPV4_HDR_MF_FLAG)
2647                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2648
2649                                 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2650                                         if (input_set & (I40E_INSET_IPV4_SRC |
2651                                                 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
2652                                                 I40E_INSET_IPV4_TTL | I40E_INSET_IPV4_PROTO)) {
2653                                                 rte_flow_error_set(error, EINVAL,
2654                                                         RTE_FLOW_ERROR_TYPE_ITEM,
2655                                                         item,
2656                                                         "L2 and L3 input set are exclusive.");
2657                                                 return -rte_errno;
2658                                         }
2659                                 } else {
2660                                         /* Get the filter info */
2661                                         filter->input.flow.ip4_flow.proto =
2662                                                 ipv4_spec->hdr.next_proto_id;
2663                                         filter->input.flow.ip4_flow.tos =
2664                                                 ipv4_spec->hdr.type_of_service;
2665                                         filter->input.flow.ip4_flow.ttl =
2666                                                 ipv4_spec->hdr.time_to_live;
2667                                         filter->input.flow.ip4_flow.src_ip =
2668                                                 ipv4_spec->hdr.src_addr;
2669                                         filter->input.flow.ip4_flow.dst_ip =
2670                                                 ipv4_spec->hdr.dst_addr;
2671
2672                                         filter->input.flow_ext.inner_ip = false;
2673                                         filter->input.flow_ext.oip_type =
2674                                                 I40E_FDIR_IPTYPE_IPV4;
2675                                 }
2676                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2677                                 filter->input.flow_ext.inner_ip = true;
2678                                 filter->input.flow_ext.iip_type =
2679                                         I40E_FDIR_IPTYPE_IPV4;
2680                         } else if (!ipv4_spec && !ipv4_mask && outer_ip) {
2681                                 filter->input.flow_ext.inner_ip = false;
2682                                 filter->input.flow_ext.oip_type =
2683                                         I40E_FDIR_IPTYPE_IPV4;
2684                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2685                                 rte_flow_error_set(error, EINVAL,
2686                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2687                                                    item,
2688                                                    "Invalid inner IPv4 mask.");
2689                                 return -rte_errno;
2690                         }
2691
2692                         if (outer_ip)
2693                                 outer_ip = false;
2694
2695                         break;
2696                 case RTE_FLOW_ITEM_TYPE_IPV6:
2697                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2698                         ipv6_spec = item->spec;
2699                         ipv6_mask = item->mask;
2700                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2701                         layer_idx = I40E_FLXPLD_L3_IDX;
2702
2703                         if (ipv6_spec && ipv6_mask && outer_ip) {
2704                                 /* Check IPv6 mask and update input set */
2705                                 if (ipv6_mask->hdr.payload_len) {
2706                                         rte_flow_error_set(error, EINVAL,
2707                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2708                                                    item,
2709                                                    "Invalid IPv6 mask");
2710                                         return -rte_errno;
2711                                 }
2712
2713                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2714                                             ipv6_addr_mask,
2715                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2716                                         input_set |= I40E_INSET_IPV6_SRC;
2717                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2718                                             ipv6_addr_mask,
2719                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2720                                         input_set |= I40E_INSET_IPV6_DST;
2721
2722                                 if ((ipv6_mask->hdr.vtc_flow &
2723                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2724                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2725                                         input_set |= I40E_INSET_IPV6_TC;
2726                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2727                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2728                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2729                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2730
2731                                 /* Get filter info */
2732                                 vtc_flow_cpu =
2733                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2734                                 filter->input.flow.ipv6_flow.tc =
2735                                         (uint8_t)(vtc_flow_cpu >>
2736                                                   I40E_FDIR_IPv6_TC_OFFSET);
2737                                 filter->input.flow.ipv6_flow.proto =
2738                                         ipv6_spec->hdr.proto;
2739                                 filter->input.flow.ipv6_flow.hop_limits =
2740                                         ipv6_spec->hdr.hop_limits;
2741
2742                                 filter->input.flow_ext.inner_ip = false;
2743                                 filter->input.flow_ext.oip_type =
2744                                         I40E_FDIR_IPTYPE_IPV6;
2745
2746                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2747                                            ipv6_spec->hdr.src_addr, 16);
2748                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2749                                            ipv6_spec->hdr.dst_addr, 16);
2750
2751                                 /* Check if it is fragment. */
2752                                 if (ipv6_spec->hdr.proto ==
2753                                     I40E_IPV6_FRAG_HEADER)
2754                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2755                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2756                                 filter->input.flow_ext.inner_ip = true;
2757                                 filter->input.flow_ext.iip_type =
2758                                         I40E_FDIR_IPTYPE_IPV6;
2759                         } else if (!ipv6_spec && !ipv6_mask && outer_ip) {
2760                                 filter->input.flow_ext.inner_ip = false;
2761                                 filter->input.flow_ext.oip_type =
2762                                         I40E_FDIR_IPTYPE_IPV6;
2763                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2764                                 rte_flow_error_set(error, EINVAL,
2765                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2766                                                    item,
2767                                                    "Invalid inner IPv6 mask");
2768                                 return -rte_errno;
2769                         }
2770
2771                         if (outer_ip)
2772                                 outer_ip = false;
2773                         break;
2774                 case RTE_FLOW_ITEM_TYPE_TCP:
2775                         tcp_spec = item->spec;
2776                         tcp_mask = item->mask;
2777
2778                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2779                                 pctype =
2780                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2781                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2782                                 pctype =
2783                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2784                         if (tcp_spec && tcp_mask) {
2785                                 /* Check TCP mask and update input set */
2786                                 if (tcp_mask->hdr.sent_seq ||
2787                                     tcp_mask->hdr.recv_ack ||
2788                                     tcp_mask->hdr.data_off ||
2789                                     tcp_mask->hdr.tcp_flags ||
2790                                     tcp_mask->hdr.rx_win ||
2791                                     tcp_mask->hdr.cksum ||
2792                                     tcp_mask->hdr.tcp_urp) {
2793                                         rte_flow_error_set(error, EINVAL,
2794                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2795                                                    item,
2796                                                    "Invalid TCP mask");
2797                                         return -rte_errno;
2798                                 }
2799
2800                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2801                                         input_set |= I40E_INSET_SRC_PORT;
2802                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2803                                         input_set |= I40E_INSET_DST_PORT;
2804
2805                                 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2806                                         if (input_set &
2807                                                 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) {
2808                                                 rte_flow_error_set(error, EINVAL,
2809                                                         RTE_FLOW_ERROR_TYPE_ITEM,
2810                                                         item,
2811                                                         "L2 and L4 input set are exclusive.");
2812                                                 return -rte_errno;
2813                                         }
2814                                 } else {
2815                                         /* Get filter info */
2816                                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2817                                                 filter->input.flow.tcp4_flow.src_port =
2818                                                         tcp_spec->hdr.src_port;
2819                                                 filter->input.flow.tcp4_flow.dst_port =
2820                                                         tcp_spec->hdr.dst_port;
2821                                         } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2822                                                 filter->input.flow.tcp6_flow.src_port =
2823                                                         tcp_spec->hdr.src_port;
2824                                                 filter->input.flow.tcp6_flow.dst_port =
2825                                                         tcp_spec->hdr.dst_port;
2826                                         }
2827                                 }
2828                         }
2829
2830                         layer_idx = I40E_FLXPLD_L4_IDX;
2831
2832                         break;
2833                 case RTE_FLOW_ITEM_TYPE_UDP:
2834                         udp_spec = item->spec;
2835                         udp_mask = item->mask;
2836
2837                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2838                                 pctype =
2839                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2840                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2841                                 pctype =
2842                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2843
2844                         if (udp_spec && udp_mask) {
2845                                 /* Check UDP mask and update input set*/
2846                                 if (udp_mask->hdr.dgram_len ||
2847                                     udp_mask->hdr.dgram_cksum) {
2848                                         rte_flow_error_set(error, EINVAL,
2849                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2850                                                    item,
2851                                                    "Invalid UDP mask");
2852                                         return -rte_errno;
2853                                 }
2854
2855                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2856                                         input_set |= I40E_INSET_SRC_PORT;
2857                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2858                                         input_set |= I40E_INSET_DST_PORT;
2859
2860                                 if (input_set & (I40E_INSET_DMAC | I40E_INSET_SMAC)) {
2861                                         if (input_set &
2862                                                 (I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT)) {
2863                                                 rte_flow_error_set(error, EINVAL,
2864                                                         RTE_FLOW_ERROR_TYPE_ITEM,
2865                                                         item,
2866                                                         "L2 and L4 input set are exclusive.");
2867                                                 return -rte_errno;
2868                                         }
2869                                 } else {
2870                                         /* Get filter info */
2871                                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2872                                                 filter->input.flow.udp4_flow.src_port =
2873                                                         udp_spec->hdr.src_port;
2874                                                 filter->input.flow.udp4_flow.dst_port =
2875                                                         udp_spec->hdr.dst_port;
2876                                         } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2877                                                 filter->input.flow.udp6_flow.src_port =
2878                                                         udp_spec->hdr.src_port;
2879                                                 filter->input.flow.udp6_flow.dst_port =
2880                                                         udp_spec->hdr.dst_port;
2881                                         }
2882                                 }
2883                         }
2884                         filter->input.flow_ext.is_udp = true;
2885                         layer_idx = I40E_FLXPLD_L4_IDX;
2886
2887                         break;
2888                 case RTE_FLOW_ITEM_TYPE_GTPC:
2889                 case RTE_FLOW_ITEM_TYPE_GTPU:
2890                         if (!pf->gtp_support) {
2891                                 rte_flow_error_set(error, EINVAL,
2892                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2893                                                    item,
2894                                                    "Unsupported protocol");
2895                                 return -rte_errno;
2896                         }
2897
2898                         gtp_spec = item->spec;
2899                         gtp_mask = item->mask;
2900
2901                         if (gtp_spec && gtp_mask) {
2902                                 if (gtp_mask->v_pt_rsv_flags ||
2903                                     gtp_mask->msg_type ||
2904                                     gtp_mask->msg_len ||
2905                                     gtp_mask->teid != UINT32_MAX) {
2906                                         rte_flow_error_set(error, EINVAL,
2907                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2908                                                    item,
2909                                                    "Invalid GTP mask");
2910                                         return -rte_errno;
2911                                 }
2912
2913                                 filter->input.flow.gtp_flow.teid =
2914                                         gtp_spec->teid;
2915                                 filter->input.flow_ext.customized_pctype = true;
2916                                 cus_proto = item_type;
2917                         }
2918                         break;
2919                 case RTE_FLOW_ITEM_TYPE_ESP:
2920                         if (!pf->esp_support) {
2921                                 rte_flow_error_set(error, EINVAL,
2922                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2923                                                    item,
2924                                                    "Unsupported ESP protocol");
2925                                 return -rte_errno;
2926                         }
2927
2928                         esp_spec = item->spec;
2929                         esp_mask = item->mask;
2930
2931                         if (!esp_spec || !esp_mask) {
2932                                 rte_flow_error_set(error, EINVAL,
2933                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2934                                                    item,
2935                                                    "Invalid ESP item");
2936                                 return -rte_errno;
2937                         }
2938
2939                         if (esp_spec && esp_mask) {
2940                                 if (esp_mask->hdr.spi != UINT32_MAX) {
2941                                         rte_flow_error_set(error, EINVAL,
2942                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2943                                                    item,
2944                                                    "Invalid ESP mask");
2945                                         return -rte_errno;
2946                                 }
2947                                 i40e_flow_set_filter_spi(filter, esp_spec);
2948                                 filter->input.flow_ext.customized_pctype = true;
2949                                 cus_proto = item_type;
2950                         }
2951                         break;
2952                 case RTE_FLOW_ITEM_TYPE_SCTP:
2953                         sctp_spec = item->spec;
2954                         sctp_mask = item->mask;
2955
2956                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2957                                 pctype =
2958                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2959                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2960                                 pctype =
2961                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2962
2963                         if (sctp_spec && sctp_mask) {
2964                                 /* Check SCTP mask and update input set */
2965                                 if (sctp_mask->hdr.cksum) {
2966                                         rte_flow_error_set(error, EINVAL,
2967                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2968                                                    item,
2969                                                    "Invalid UDP mask");
2970                                         return -rte_errno;
2971                                 }
2972
2973                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2974                                         input_set |= I40E_INSET_SRC_PORT;
2975                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2976                                         input_set |= I40E_INSET_DST_PORT;
2977                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2978                                         input_set |= I40E_INSET_SCTP_VT;
2979
2980                                 /* Get filter info */
2981                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2982                                         filter->input.flow.sctp4_flow.src_port =
2983                                                 sctp_spec->hdr.src_port;
2984                                         filter->input.flow.sctp4_flow.dst_port =
2985                                                 sctp_spec->hdr.dst_port;
2986                                         filter->input.flow.sctp4_flow.verify_tag
2987                                                 = sctp_spec->hdr.tag;
2988                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2989                                         filter->input.flow.sctp6_flow.src_port =
2990                                                 sctp_spec->hdr.src_port;
2991                                         filter->input.flow.sctp6_flow.dst_port =
2992                                                 sctp_spec->hdr.dst_port;
2993                                         filter->input.flow.sctp6_flow.verify_tag
2994                                                 = sctp_spec->hdr.tag;
2995                                 }
2996                         }
2997
2998                         layer_idx = I40E_FLXPLD_L4_IDX;
2999
3000                         break;
3001                 case RTE_FLOW_ITEM_TYPE_RAW:
3002                         raw_spec = item->spec;
3003                         raw_mask = item->mask;
3004
3005                         if (!raw_spec || !raw_mask) {
3006                                 rte_flow_error_set(error, EINVAL,
3007                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3008                                                    item,
3009                                                    "NULL RAW spec/mask");
3010                                 return -rte_errno;
3011                         }
3012
3013                         if (pf->support_multi_driver) {
3014                                 rte_flow_error_set(error, ENOTSUP,
3015                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3016                                                    item,
3017                                                    "Unsupported flexible payload.");
3018                                 return -rte_errno;
3019                         }
3020
3021                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
3022                         if (ret < 0)
3023                                 return ret;
3024
3025                         off_arr[raw_id] = raw_spec->offset;
3026                         len_arr[raw_id] = raw_spec->length;
3027
3028                         flex_size = 0;
3029                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
3030                         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
3031                         flex_pit.size =
3032                                 raw_spec->length / sizeof(uint16_t);
3033                         flex_pit.dst_offset =
3034                                 next_dst_off / sizeof(uint16_t);
3035
3036                         for (i = 0; i <= raw_id; i++) {
3037                                 if (i == raw_id)
3038                                         flex_pit.src_offset +=
3039                                                 raw_spec->offset /
3040                                                 sizeof(uint16_t);
3041                                 else
3042                                         flex_pit.src_offset +=
3043                                                 (off_arr[i] + len_arr[i]) /
3044                                                 sizeof(uint16_t);
3045                                 flex_size += len_arr[i];
3046                         }
3047                         if (((flex_pit.src_offset + flex_pit.size) >=
3048                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
3049                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
3050                                 rte_flow_error_set(error, EINVAL,
3051                                            RTE_FLOW_ERROR_TYPE_ITEM,
3052                                            item,
3053                                            "Exceeds maxmial payload limit.");
3054                                 return -rte_errno;
3055                         }
3056
3057                         for (i = 0; i < raw_spec->length; i++) {
3058                                 j = i + next_dst_off;
3059                                 filter->input.flow_ext.flexbytes[j] =
3060                                         raw_spec->pattern[i];
3061                                 filter->input.flow_ext.flex_mask[j] =
3062                                         raw_mask->pattern[i];
3063                         }
3064
3065                         next_dst_off += raw_spec->length;
3066                         raw_id++;
3067
3068                         memcpy(&filter->input.flow_ext.flex_pit[field_idx],
3069                                &flex_pit, sizeof(struct i40e_fdir_flex_pit));
3070                         filter->input.flow_ext.layer_idx = layer_idx;
3071                         filter->input.flow_ext.raw_id = raw_id;
3072                         break;
3073                 case RTE_FLOW_ITEM_TYPE_VF:
3074                         vf_spec = item->spec;
3075                         if (!attr->transfer) {
3076                                 rte_flow_error_set(error, ENOTSUP,
3077                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3078                                                    item,
3079                                                    "Matching VF traffic"
3080                                                    " without affecting it"
3081                                                    " (transfer attribute)"
3082                                                    " is unsupported");
3083                                 return -rte_errno;
3084                         }
3085                         filter->input.flow_ext.is_vf = 1;
3086                         filter->input.flow_ext.dst_id = vf_spec->id;
3087                         if (filter->input.flow_ext.is_vf &&
3088                             filter->input.flow_ext.dst_id >= pf->vf_num) {
3089                                 rte_flow_error_set(error, EINVAL,
3090                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3091                                                    item,
3092                                                    "Invalid VF ID for FDIR.");
3093                                 return -rte_errno;
3094                         }
3095                         break;
3096                 case RTE_FLOW_ITEM_TYPE_L2TPV3OIP:
3097                         l2tpv3oip_spec = item->spec;
3098                         l2tpv3oip_mask = item->mask;
3099
3100                         if (!l2tpv3oip_spec || !l2tpv3oip_mask)
3101                                 break;
3102
3103                         if (l2tpv3oip_mask->session_id != UINT32_MAX) {
3104                                 rte_flow_error_set(error, EINVAL,
3105                                         RTE_FLOW_ERROR_TYPE_ITEM,
3106                                         item,
3107                                         "Invalid L2TPv3 mask");
3108                                 return -rte_errno;
3109                         }
3110
3111                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
3112                                 filter->input.flow.ip4_l2tpv3oip_flow.session_id =
3113                                         l2tpv3oip_spec->session_id;
3114                                 filter->input.flow_ext.oip_type =
3115                                         I40E_FDIR_IPTYPE_IPV4;
3116                         } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
3117                                 filter->input.flow.ip6_l2tpv3oip_flow.session_id =
3118                                         l2tpv3oip_spec->session_id;
3119                                 filter->input.flow_ext.oip_type =
3120                                         I40E_FDIR_IPTYPE_IPV6;
3121                         }
3122
3123                         filter->input.flow_ext.customized_pctype = true;
3124                         cus_proto = item_type;
3125                         break;
3126                 default:
3127                         break;
3128                 }
3129         }
3130
3131         /* Get customized pctype value */
3132         if (filter->input.flow_ext.customized_pctype) {
3133                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
3134                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
3135                         rte_flow_error_set(error, EINVAL,
3136                                            RTE_FLOW_ERROR_TYPE_ITEM,
3137                                            item,
3138                                            "Unsupported pctype");
3139                         return -rte_errno;
3140                 }
3141         }
3142
3143         /* If customized pctype is not used, set fdir configuration.*/
3144         if (!filter->input.flow_ext.customized_pctype) {
3145                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3146                 if (ret == -1) {
3147                         rte_flow_error_set(error, EINVAL,
3148                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3149                                            "Conflict with the first rule's input set.");
3150                         return -rte_errno;
3151                 } else if (ret == -EINVAL) {
3152                         rte_flow_error_set(error, EINVAL,
3153                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3154                                            "Invalid pattern mask.");
3155                         return -rte_errno;
3156                 }
3157         }
3158
3159         filter->input.pctype = pctype;
3160
3161         return 0;
3162 }
3163
3164 /* Parse to get the action info of a FDIR filter.
3165  * FDIR action supports QUEUE or (QUEUE + MARK).
3166  */
3167 static int
3168 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3169                             const struct rte_flow_action *actions,
3170                             struct rte_flow_error *error,
3171                             struct i40e_fdir_filter_conf *filter)
3172 {
3173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3174         const struct rte_flow_action *act;
3175         const struct rte_flow_action_queue *act_q;
3176         const struct rte_flow_action_mark *mark_spec = NULL;
3177         uint32_t index = 0;
3178
3179         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3180         NEXT_ITEM_OF_ACTION(act, actions, index);
3181         switch (act->type) {
3182         case RTE_FLOW_ACTION_TYPE_QUEUE:
3183                 act_q = act->conf;
3184                 filter->action.rx_queue = act_q->index;
3185                 if ((!filter->input.flow_ext.is_vf &&
3186                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3187                     (filter->input.flow_ext.is_vf &&
3188                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3189                         rte_flow_error_set(error, EINVAL,
3190                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3191                                            "Invalid queue ID for FDIR.");
3192                         return -rte_errno;
3193                 }
3194                 filter->action.behavior = I40E_FDIR_ACCEPT;
3195                 break;
3196         case RTE_FLOW_ACTION_TYPE_DROP:
3197                 filter->action.behavior = I40E_FDIR_REJECT;
3198                 break;
3199         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3200                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3201                 break;
3202         case RTE_FLOW_ACTION_TYPE_MARK:
3203                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3204                 mark_spec = act->conf;
3205                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3206                 filter->soft_id = mark_spec->id;
3207         break;
3208         default:
3209                 rte_flow_error_set(error, EINVAL,
3210                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3211                                    "Invalid action.");
3212                 return -rte_errno;
3213         }
3214
3215         /* Check if the next non-void item is MARK or FLAG or END. */
3216         index++;
3217         NEXT_ITEM_OF_ACTION(act, actions, index);
3218         switch (act->type) {
3219         case RTE_FLOW_ACTION_TYPE_MARK:
3220                 if (mark_spec) {
3221                         /* Double MARK actions requested */
3222                         rte_flow_error_set(error, EINVAL,
3223                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3224                            "Invalid action.");
3225                         return -rte_errno;
3226                 }
3227                 mark_spec = act->conf;
3228                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3229                 filter->soft_id = mark_spec->id;
3230                 break;
3231         case RTE_FLOW_ACTION_TYPE_FLAG:
3232                 if (mark_spec) {
3233                         /* MARK + FLAG not supported */
3234                         rte_flow_error_set(error, EINVAL,
3235                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3236                                            "Invalid action.");
3237                         return -rte_errno;
3238                 }
3239                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3240                 break;
3241         case RTE_FLOW_ACTION_TYPE_RSS:
3242                 if (filter->action.behavior != I40E_FDIR_PASSTHRU) {
3243                         /* RSS filter won't be next if FDIR did not pass thru */
3244                         rte_flow_error_set(error, EINVAL,
3245                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3246                                            "Invalid action.");
3247                         return -rte_errno;
3248                 }
3249                 break;
3250         case RTE_FLOW_ACTION_TYPE_END:
3251                 return 0;
3252         default:
3253                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3254                                    act, "Invalid action.");
3255                 return -rte_errno;
3256         }
3257
3258         /* Check if the next non-void item is END */
3259         index++;
3260         NEXT_ITEM_OF_ACTION(act, actions, index);
3261         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3262                 rte_flow_error_set(error, EINVAL,
3263                                    RTE_FLOW_ERROR_TYPE_ACTION,
3264                                    act, "Invalid action.");
3265                 return -rte_errno;
3266         }
3267
3268         return 0;
3269 }
3270
3271 static int
3272 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3273                             const struct rte_flow_attr *attr,
3274                             const struct rte_flow_item pattern[],
3275                             const struct rte_flow_action actions[],
3276                             struct rte_flow_error *error,
3277                             union i40e_filter_t *filter)
3278 {
3279         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3280         struct i40e_fdir_filter_conf *fdir_filter =
3281                 &filter->fdir_filter;
3282         int ret;
3283
3284         ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3285                                            fdir_filter);
3286         if (ret)
3287                 return ret;
3288
3289         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3290         if (ret)
3291                 return ret;
3292
3293         ret = i40e_flow_parse_attr(attr, error);
3294         if (ret)
3295                 return ret;
3296
3297         cons_filter_type = RTE_ETH_FILTER_FDIR;
3298
3299         if (pf->fdir.fdir_vsi == NULL) {
3300                 /* Enable fdir when fdir flow is added at first time. */
3301                 ret = i40e_fdir_setup(pf);
3302                 if (ret != I40E_SUCCESS) {
3303                         rte_flow_error_set(error, ENOTSUP,
3304                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3305                                            NULL, "Failed to setup fdir.");
3306                         return -rte_errno;
3307                 }
3308                 ret = i40e_fdir_configure(dev);
3309                 if (ret < 0) {
3310                         rte_flow_error_set(error, ENOTSUP,
3311                                            RTE_FLOW_ERROR_TYPE_HANDLE,
3312                                            NULL, "Failed to configure fdir.");
3313                         goto err;
3314                 }
3315         }
3316
3317         /* If create the first fdir rule, enable fdir check for rx queues */
3318         if (TAILQ_EMPTY(&pf->fdir.fdir_list))
3319                 i40e_fdir_rx_proc_enable(dev, 1);
3320
3321         return 0;
3322 err:
3323         i40e_fdir_teardown(pf);
3324         return -rte_errno;
3325 }
3326
3327 /* Parse to get the action info of a tunnel filter
3328  * Tunnel action only supports PF, VF and QUEUE.
3329  */
3330 static int
3331 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3332                               const struct rte_flow_action *actions,
3333                               struct rte_flow_error *error,
3334                               struct i40e_tunnel_filter_conf *filter)
3335 {
3336         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3337         const struct rte_flow_action *act;
3338         const struct rte_flow_action_queue *act_q;
3339         const struct rte_flow_action_vf *act_vf;
3340         uint32_t index = 0;
3341
3342         /* Check if the first non-void action is PF or VF. */
3343         NEXT_ITEM_OF_ACTION(act, actions, index);
3344         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3345             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3346                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3347                                    act, "Not supported action.");
3348                 return -rte_errno;
3349         }
3350
3351         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3352                 act_vf = act->conf;
3353                 filter->vf_id = act_vf->id;
3354                 filter->is_to_vf = 1;
3355                 if (filter->vf_id >= pf->vf_num) {
3356                         rte_flow_error_set(error, EINVAL,
3357                                    RTE_FLOW_ERROR_TYPE_ACTION,
3358                                    act, "Invalid VF ID for tunnel filter");
3359                         return -rte_errno;
3360                 }
3361         }
3362
3363         /* Check if the next non-void item is QUEUE */
3364         index++;
3365         NEXT_ITEM_OF_ACTION(act, actions, index);
3366         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3367                 act_q = act->conf;
3368                 filter->queue_id = act_q->index;
3369                 if ((!filter->is_to_vf) &&
3370                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3371                         rte_flow_error_set(error, EINVAL,
3372                                    RTE_FLOW_ERROR_TYPE_ACTION,
3373                                    act, "Invalid queue ID for tunnel filter");
3374                         return -rte_errno;
3375                 } else if (filter->is_to_vf &&
3376                            (filter->queue_id >= pf->vf_nb_qps)) {
3377                         rte_flow_error_set(error, EINVAL,
3378                                    RTE_FLOW_ERROR_TYPE_ACTION,
3379                                    act, "Invalid queue ID for tunnel filter");
3380                         return -rte_errno;
3381                 }
3382         }
3383
3384         /* Check if the next non-void item is END */
3385         index++;
3386         NEXT_ITEM_OF_ACTION(act, actions, index);
3387         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3388                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3389                                    act, "Not supported action.");
3390                 return -rte_errno;
3391         }
3392
3393         return 0;
3394 }
3395
3396 /* 1. Last in item should be NULL as range is not supported.
3397  * 2. Supported filter types: Source port only and Destination port only.
3398  * 3. Mask of fields which need to be matched should be
3399  *    filled with 1.
3400  * 4. Mask of fields which needn't to be matched should be
3401  *    filled with 0.
3402  */
3403 static int
3404 i40e_flow_parse_l4_pattern(const struct rte_flow_item *pattern,
3405                            struct rte_flow_error *error,
3406                            struct i40e_tunnel_filter_conf *filter)
3407 {
3408         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
3409         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
3410         const struct rte_flow_item_udp *udp_spec, *udp_mask;
3411         const struct rte_flow_item *item = pattern;
3412         enum rte_flow_item_type item_type;
3413
3414         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3415                 if (item->last) {
3416                         rte_flow_error_set(error, EINVAL,
3417                                            RTE_FLOW_ERROR_TYPE_ITEM,
3418                                            item,
3419                                            "Not support range");
3420                         return -rte_errno;
3421                 }
3422                 item_type = item->type;
3423                 switch (item_type) {
3424                 case RTE_FLOW_ITEM_TYPE_ETH:
3425                         if (item->spec || item->mask) {
3426                                 rte_flow_error_set(error, EINVAL,
3427                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3428                                                    item,
3429                                                    "Invalid ETH item");
3430                                 return -rte_errno;
3431                         }
3432
3433                         break;
3434                 case RTE_FLOW_ITEM_TYPE_IPV4:
3435                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3436                         /* IPv4 is used to describe protocol,
3437                          * spec and mask should be NULL.
3438                          */
3439                         if (item->spec || item->mask) {
3440                                 rte_flow_error_set(error, EINVAL,
3441                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3442                                                    item,
3443                                                    "Invalid IPv4 item");
3444                                 return -rte_errno;
3445                         }
3446
3447                         break;
3448                 case RTE_FLOW_ITEM_TYPE_IPV6:
3449                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3450                         /* IPv6 is used to describe protocol,
3451                          * spec and mask should be NULL.
3452                          */
3453                         if (item->spec || item->mask) {
3454                                 rte_flow_error_set(error, EINVAL,
3455                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3456                                                    item,
3457                                                    "Invalid IPv6 item");
3458                                 return -rte_errno;
3459                         }
3460
3461                         break;
3462                 case RTE_FLOW_ITEM_TYPE_UDP:
3463                         udp_spec = item->spec;
3464                         udp_mask = item->mask;
3465
3466                         if (!udp_spec || !udp_mask) {
3467                                 rte_flow_error_set(error, EINVAL,
3468                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3469                                                    item,
3470                                                    "Invalid udp item");
3471                                 return -rte_errno;
3472                         }
3473
3474                         if (udp_spec->hdr.src_port != 0 &&
3475                             udp_spec->hdr.dst_port != 0) {
3476                                 rte_flow_error_set(error, EINVAL,
3477                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3478                                                    item,
3479                                                    "Invalid udp spec");
3480                                 return -rte_errno;
3481                         }
3482
3483                         if (udp_spec->hdr.src_port != 0) {
3484                                 filter->l4_port_type =
3485                                         I40E_L4_PORT_TYPE_SRC;
3486                                 filter->tenant_id =
3487                                 rte_be_to_cpu_32(udp_spec->hdr.src_port);
3488                         }
3489
3490                         if (udp_spec->hdr.dst_port != 0) {
3491                                 filter->l4_port_type =
3492                                         I40E_L4_PORT_TYPE_DST;
3493                                 filter->tenant_id =
3494                                 rte_be_to_cpu_32(udp_spec->hdr.dst_port);
3495                         }
3496
3497                         filter->tunnel_type = I40E_CLOUD_TYPE_UDP;
3498
3499                         break;
3500                 case RTE_FLOW_ITEM_TYPE_TCP:
3501                         tcp_spec = item->spec;
3502                         tcp_mask = item->mask;
3503
3504                         if (!tcp_spec || !tcp_mask) {
3505                                 rte_flow_error_set(error, EINVAL,
3506                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3507                                                    item,
3508                                                    "Invalid tcp item");
3509                                 return -rte_errno;
3510                         }
3511
3512                         if (tcp_spec->hdr.src_port != 0 &&
3513                             tcp_spec->hdr.dst_port != 0) {
3514                                 rte_flow_error_set(error, EINVAL,
3515                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3516                                                    item,
3517                                                    "Invalid tcp spec");
3518                                 return -rte_errno;
3519                         }
3520
3521                         if (tcp_spec->hdr.src_port != 0) {
3522                                 filter->l4_port_type =
3523                                         I40E_L4_PORT_TYPE_SRC;
3524                                 filter->tenant_id =
3525                                 rte_be_to_cpu_32(tcp_spec->hdr.src_port);
3526                         }
3527
3528                         if (tcp_spec->hdr.dst_port != 0) {
3529                                 filter->l4_port_type =
3530                                         I40E_L4_PORT_TYPE_DST;
3531                                 filter->tenant_id =
3532                                 rte_be_to_cpu_32(tcp_spec->hdr.dst_port);
3533                         }
3534
3535                         filter->tunnel_type = I40E_CLOUD_TYPE_TCP;
3536
3537                         break;
3538                 case RTE_FLOW_ITEM_TYPE_SCTP:
3539                         sctp_spec = item->spec;
3540                         sctp_mask = item->mask;
3541
3542                         if (!sctp_spec || !sctp_mask) {
3543                                 rte_flow_error_set(error, EINVAL,
3544                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3545                                                    item,
3546                                                    "Invalid sctp item");
3547                                 return -rte_errno;
3548                         }
3549
3550                         if (sctp_spec->hdr.src_port != 0 &&
3551                             sctp_spec->hdr.dst_port != 0) {
3552                                 rte_flow_error_set(error, EINVAL,
3553                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3554                                                    item,
3555                                                    "Invalid sctp spec");
3556                                 return -rte_errno;
3557                         }
3558
3559                         if (sctp_spec->hdr.src_port != 0) {
3560                                 filter->l4_port_type =
3561                                         I40E_L4_PORT_TYPE_SRC;
3562                                 filter->tenant_id =
3563                                         rte_be_to_cpu_32(sctp_spec->hdr.src_port);
3564                         }
3565
3566                         if (sctp_spec->hdr.dst_port != 0) {
3567                                 filter->l4_port_type =
3568                                         I40E_L4_PORT_TYPE_DST;
3569                                 filter->tenant_id =
3570                                         rte_be_to_cpu_32(sctp_spec->hdr.dst_port);
3571                         }
3572
3573                         filter->tunnel_type = I40E_CLOUD_TYPE_SCTP;
3574
3575                         break;
3576                 default:
3577                         break;
3578                 }
3579         }
3580
3581         return 0;
3582 }
3583
3584 static int
3585 i40e_flow_parse_l4_cloud_filter(struct rte_eth_dev *dev,
3586                                 const struct rte_flow_attr *attr,
3587                                 const struct rte_flow_item pattern[],
3588                                 const struct rte_flow_action actions[],
3589                                 struct rte_flow_error *error,
3590                                 union i40e_filter_t *filter)
3591 {
3592         struct i40e_tunnel_filter_conf *tunnel_filter =
3593                 &filter->consistent_tunnel_filter;
3594         int ret;
3595
3596         ret = i40e_flow_parse_l4_pattern(pattern, error, tunnel_filter);
3597         if (ret)
3598                 return ret;
3599
3600         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3601         if (ret)
3602                 return ret;
3603
3604         ret = i40e_flow_parse_attr(attr, error);
3605         if (ret)
3606                 return ret;
3607
3608         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3609
3610         return ret;
3611 }
3612
3613 static uint16_t i40e_supported_tunnel_filter_types[] = {
3614         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3615         ETH_TUNNEL_FILTER_IVLAN,
3616         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3617         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3618         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3619         ETH_TUNNEL_FILTER_IMAC,
3620         ETH_TUNNEL_FILTER_IMAC,
3621 };
3622
3623 static int
3624 i40e_check_tunnel_filter_type(uint8_t filter_type)
3625 {
3626         uint8_t i;
3627
3628         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3629                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3630                         return 0;
3631         }
3632
3633         return -1;
3634 }
3635
3636 /* 1. Last in item should be NULL as range is not supported.
3637  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3638  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3639  * 3. Mask of fields which need to be matched should be
3640  *    filled with 1.
3641  * 4. Mask of fields which needn't to be matched should be
3642  *    filled with 0.
3643  */
3644 static int
3645 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3646                               const struct rte_flow_item *pattern,
3647                               struct rte_flow_error *error,
3648                               struct i40e_tunnel_filter_conf *filter)
3649 {
3650         const struct rte_flow_item *item = pattern;
3651         const struct rte_flow_item_eth *eth_spec;
3652         const struct rte_flow_item_eth *eth_mask;
3653         const struct rte_flow_item_vxlan *vxlan_spec;
3654         const struct rte_flow_item_vxlan *vxlan_mask;
3655         const struct rte_flow_item_vlan *vlan_spec;
3656         const struct rte_flow_item_vlan *vlan_mask;
3657         uint8_t filter_type = 0;
3658         bool is_vni_masked = 0;
3659         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3660         enum rte_flow_item_type item_type;
3661         bool vxlan_flag = 0;
3662         uint32_t tenant_id_be = 0;
3663         int ret;
3664
3665         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3666                 if (item->last) {
3667                         rte_flow_error_set(error, EINVAL,
3668                                            RTE_FLOW_ERROR_TYPE_ITEM,
3669                                            item,
3670                                            "Not support range");
3671                         return -rte_errno;
3672                 }
3673                 item_type = item->type;
3674                 switch (item_type) {
3675                 case RTE_FLOW_ITEM_TYPE_ETH:
3676                         eth_spec = item->spec;
3677                         eth_mask = item->mask;
3678
3679                         /* Check if ETH item is used for place holder.
3680                          * If yes, both spec and mask should be NULL.
3681                          * If no, both spec and mask shouldn't be NULL.
3682                          */
3683                         if ((!eth_spec && eth_mask) ||
3684                             (eth_spec && !eth_mask)) {
3685                                 rte_flow_error_set(error, EINVAL,
3686                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3687                                                    item,
3688                                                    "Invalid ether spec/mask");
3689                                 return -rte_errno;
3690                         }
3691
3692                         if (eth_spec && eth_mask) {
3693                                 /* DST address of inner MAC shouldn't be masked.
3694                                  * SRC address of Inner MAC should be masked.
3695                                  */
3696                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3697                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3698                                     eth_mask->type) {
3699                                         rte_flow_error_set(error, EINVAL,
3700                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3701                                                    item,
3702                                                    "Invalid ether spec/mask");
3703                                         return -rte_errno;
3704                                 }
3705
3706                                 if (!vxlan_flag) {
3707                                         rte_memcpy(&filter->outer_mac,
3708                                                    &eth_spec->dst,
3709                                                    RTE_ETHER_ADDR_LEN);
3710                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3711                                 } else {
3712                                         rte_memcpy(&filter->inner_mac,
3713                                                    &eth_spec->dst,
3714                                                    RTE_ETHER_ADDR_LEN);
3715                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3716                                 }
3717                         }
3718                         break;
3719                 case RTE_FLOW_ITEM_TYPE_VLAN:
3720                         vlan_spec = item->spec;
3721                         vlan_mask = item->mask;
3722                         if (!(vlan_spec && vlan_mask) ||
3723                             vlan_mask->inner_type) {
3724                                 rte_flow_error_set(error, EINVAL,
3725                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3726                                                    item,
3727                                                    "Invalid vlan item");
3728                                 return -rte_errno;
3729                         }
3730
3731                         if (vlan_spec && vlan_mask) {
3732                                 if (vlan_mask->tci ==
3733                                     rte_cpu_to_be_16(I40E_VLAN_TCI_MASK))
3734                                         filter->inner_vlan =
3735                                               rte_be_to_cpu_16(vlan_spec->tci) &
3736                                               I40E_VLAN_TCI_MASK;
3737                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3738                         }
3739                         break;
3740                 case RTE_FLOW_ITEM_TYPE_IPV4:
3741                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3742                         /* IPv4 is used to describe protocol,
3743                          * spec and mask should be NULL.
3744                          */
3745                         if (item->spec || item->mask) {
3746                                 rte_flow_error_set(error, EINVAL,
3747                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3748                                                    item,
3749                                                    "Invalid IPv4 item");
3750                                 return -rte_errno;
3751                         }
3752                         break;
3753                 case RTE_FLOW_ITEM_TYPE_IPV6:
3754                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3755                         /* IPv6 is used to describe protocol,
3756                          * spec and mask should be NULL.
3757                          */
3758                         if (item->spec || item->mask) {
3759                                 rte_flow_error_set(error, EINVAL,
3760                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3761                                                    item,
3762                                                    "Invalid IPv6 item");
3763                                 return -rte_errno;
3764                         }
3765                         break;
3766                 case RTE_FLOW_ITEM_TYPE_UDP:
3767                         /* UDP is used to describe protocol,
3768                          * spec and mask should be NULL.
3769                          */
3770                         if (item->spec || item->mask) {
3771                                 rte_flow_error_set(error, EINVAL,
3772                                            RTE_FLOW_ERROR_TYPE_ITEM,
3773                                            item,
3774                                            "Invalid UDP item");
3775                                 return -rte_errno;
3776                         }
3777                         break;
3778                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3779                         vxlan_spec = item->spec;
3780                         vxlan_mask = item->mask;
3781                         /* Check if VXLAN item is used to describe protocol.
3782                          * If yes, both spec and mask should be NULL.
3783                          * If no, both spec and mask shouldn't be NULL.
3784                          */
3785                         if ((!vxlan_spec && vxlan_mask) ||
3786                             (vxlan_spec && !vxlan_mask)) {
3787                                 rte_flow_error_set(error, EINVAL,
3788                                            RTE_FLOW_ERROR_TYPE_ITEM,
3789                                            item,
3790                                            "Invalid VXLAN item");
3791                                 return -rte_errno;
3792                         }
3793
3794                         /* Check if VNI is masked. */
3795                         if (vxlan_spec && vxlan_mask) {
3796                                 is_vni_masked =
3797                                         !!memcmp(vxlan_mask->vni, vni_mask,
3798                                                  RTE_DIM(vni_mask));
3799                                 if (is_vni_masked) {
3800                                         rte_flow_error_set(error, EINVAL,
3801                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3802                                                    item,
3803                                                    "Invalid VNI mask");
3804                                         return -rte_errno;
3805                                 }
3806
3807                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3808                                            vxlan_spec->vni, 3);
3809                                 filter->tenant_id =
3810                                         rte_be_to_cpu_32(tenant_id_be);
3811                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3812                         }
3813
3814                         vxlan_flag = 1;
3815                         break;
3816                 default:
3817                         break;
3818                 }
3819         }
3820
3821         ret = i40e_check_tunnel_filter_type(filter_type);
3822         if (ret < 0) {
3823                 rte_flow_error_set(error, EINVAL,
3824                                    RTE_FLOW_ERROR_TYPE_ITEM,
3825                                    NULL,
3826                                    "Invalid filter type");
3827                 return -rte_errno;
3828         }
3829         filter->filter_type = filter_type;
3830
3831         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3832
3833         return 0;
3834 }
3835
3836 static int
3837 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3838                              const struct rte_flow_attr *attr,
3839                              const struct rte_flow_item pattern[],
3840                              const struct rte_flow_action actions[],
3841                              struct rte_flow_error *error,
3842                              union i40e_filter_t *filter)
3843 {
3844         struct i40e_tunnel_filter_conf *tunnel_filter =
3845                 &filter->consistent_tunnel_filter;
3846         int ret;
3847
3848         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3849                                             error, tunnel_filter);
3850         if (ret)
3851                 return ret;
3852
3853         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3854         if (ret)
3855                 return ret;
3856
3857         ret = i40e_flow_parse_attr(attr, error);
3858         if (ret)
3859                 return ret;
3860
3861         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3862
3863         return ret;
3864 }
3865
3866 /* 1. Last in item should be NULL as range is not supported.
3867  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3868  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3869  * 3. Mask of fields which need to be matched should be
3870  *    filled with 1.
3871  * 4. Mask of fields which needn't to be matched should be
3872  *    filled with 0.
3873  */
3874 static int
3875 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3876                               const struct rte_flow_item *pattern,
3877                               struct rte_flow_error *error,
3878                               struct i40e_tunnel_filter_conf *filter)
3879 {
3880         const struct rte_flow_item *item = pattern;
3881         const struct rte_flow_item_eth *eth_spec;
3882         const struct rte_flow_item_eth *eth_mask;
3883         const struct rte_flow_item_nvgre *nvgre_spec;
3884         const struct rte_flow_item_nvgre *nvgre_mask;
3885         const struct rte_flow_item_vlan *vlan_spec;
3886         const struct rte_flow_item_vlan *vlan_mask;
3887         enum rte_flow_item_type item_type;
3888         uint8_t filter_type = 0;
3889         bool is_tni_masked = 0;
3890         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3891         bool nvgre_flag = 0;
3892         uint32_t tenant_id_be = 0;
3893         int ret;
3894
3895         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3896                 if (item->last) {
3897                         rte_flow_error_set(error, EINVAL,
3898                                            RTE_FLOW_ERROR_TYPE_ITEM,
3899                                            item,
3900                                            "Not support range");
3901                         return -rte_errno;
3902                 }
3903                 item_type = item->type;
3904                 switch (item_type) {
3905                 case RTE_FLOW_ITEM_TYPE_ETH:
3906                         eth_spec = item->spec;
3907                         eth_mask = item->mask;
3908
3909                         /* Check if ETH item is used for place holder.
3910                          * If yes, both spec and mask should be NULL.
3911                          * If no, both spec and mask shouldn't be NULL.
3912                          */
3913                         if ((!eth_spec && eth_mask) ||
3914                             (eth_spec && !eth_mask)) {
3915                                 rte_flow_error_set(error, EINVAL,
3916                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3917                                                    item,
3918                                                    "Invalid ether spec/mask");
3919                                 return -rte_errno;
3920                         }
3921
3922                         if (eth_spec && eth_mask) {
3923                                 /* DST address of inner MAC shouldn't be masked.
3924                                  * SRC address of Inner MAC should be masked.
3925                                  */
3926                                 if (!rte_is_broadcast_ether_addr(&eth_mask->dst) ||
3927                                     !rte_is_zero_ether_addr(&eth_mask->src) ||
3928                                     eth_mask->type) {
3929                                         rte_flow_error_set(error, EINVAL,
3930                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3931                                                    item,
3932                                                    "Invalid ether spec/mask");
3933                                         return -rte_errno;
3934                                 }
3935
3936                                 if (!nvgre_flag) {
3937                                         rte_memcpy(&filter->outer_mac,
3938                                                    &eth_spec->dst,
3939                                                    RTE_ETHER_ADDR_LEN);
3940                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3941                                 } else {
3942                                         rte_memcpy(&filter->inner_mac,
3943                                                    &eth_spec->dst,
3944                                                    RTE_ETHER_ADDR_LEN);
3945                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3946                                 }
3947                         }
3948
3949                         break;
3950                 case RTE_FLOW_ITEM_TYPE_VLAN:
3951                         vlan_spec = item->spec;
3952                         vlan_mask = item->mask;
3953                         if (!(vlan_spec && vlan_mask) ||
3954                             vlan_mask->inner_type) {
3955                                 rte_flow_error_set(error, EINVAL,
3956                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3957                                                    item,
3958                                                    "Invalid vlan item");
3959                                 return -rte_errno;
3960                         }
3961
3962                         if (vlan_spec && vlan_mask) {
3963                                 if (vlan_mask->tci ==
3964                                     rte_cpu_to_be_16(I40E_VLAN_TCI_MASK))
3965                                         filter->inner_vlan =
3966                                               rte_be_to_cpu_16(vlan_spec->tci) &
3967                                               I40E_VLAN_TCI_MASK;
3968                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3969                         }
3970                         break;
3971                 case RTE_FLOW_ITEM_TYPE_IPV4:
3972                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3973                         /* IPv4 is used to describe protocol,
3974                          * spec and mask should be NULL.
3975                          */
3976                         if (item->spec || item->mask) {
3977                                 rte_flow_error_set(error, EINVAL,
3978                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3979                                                    item,
3980                                                    "Invalid IPv4 item");
3981                                 return -rte_errno;
3982                         }
3983                         break;
3984                 case RTE_FLOW_ITEM_TYPE_IPV6:
3985                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3986                         /* IPv6 is used to describe protocol,
3987                          * spec and mask should be NULL.
3988                          */
3989                         if (item->spec || item->mask) {
3990                                 rte_flow_error_set(error, EINVAL,
3991                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3992                                                    item,
3993                                                    "Invalid IPv6 item");
3994                                 return -rte_errno;
3995                         }
3996                         break;
3997                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3998                         nvgre_spec = item->spec;
3999                         nvgre_mask = item->mask;
4000                         /* Check if NVGRE item is used to describe protocol.
4001                          * If yes, both spec and mask should be NULL.
4002                          * If no, both spec and mask shouldn't be NULL.
4003                          */
4004                         if ((!nvgre_spec && nvgre_mask) ||
4005                             (nvgre_spec && !nvgre_mask)) {
4006                                 rte_flow_error_set(error, EINVAL,
4007                                            RTE_FLOW_ERROR_TYPE_ITEM,
4008                                            item,
4009                                            "Invalid NVGRE item");
4010                                 return -rte_errno;
4011                         }
4012
4013                         if (nvgre_spec && nvgre_mask) {
4014                                 is_tni_masked =
4015                                         !!memcmp(nvgre_mask->tni, tni_mask,
4016                                                  RTE_DIM(tni_mask));
4017                                 if (is_tni_masked) {
4018                                         rte_flow_error_set(error, EINVAL,
4019                                                        RTE_FLOW_ERROR_TYPE_ITEM,
4020                                                        item,
4021                                                        "Invalid TNI mask");
4022                                         return -rte_errno;
4023                                 }
4024                                 if (nvgre_mask->protocol &&
4025                                         nvgre_mask->protocol != 0xFFFF) {
4026                                         rte_flow_error_set(error, EINVAL,
4027                                                 RTE_FLOW_ERROR_TYPE_ITEM,
4028                                                 item,
4029                                                 "Invalid NVGRE item");
4030                                         return -rte_errno;
4031                                 }
4032                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
4033                                         nvgre_mask->c_k_s_rsvd0_ver !=
4034                                         rte_cpu_to_be_16(0xFFFF)) {
4035                                         rte_flow_error_set(error, EINVAL,
4036                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4037                                                    item,
4038                                                    "Invalid NVGRE item");
4039                                         return -rte_errno;
4040                                 }
4041                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
4042                                         rte_cpu_to_be_16(0x2000) &&
4043                                         nvgre_mask->c_k_s_rsvd0_ver) {
4044                                         rte_flow_error_set(error, EINVAL,
4045                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4046                                                    item,
4047                                                    "Invalid NVGRE item");
4048                                         return -rte_errno;
4049                                 }
4050                                 if (nvgre_mask->protocol &&
4051                                         nvgre_spec->protocol !=
4052                                         rte_cpu_to_be_16(0x6558)) {
4053                                         rte_flow_error_set(error, EINVAL,
4054                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4055                                                    item,
4056                                                    "Invalid NVGRE item");
4057                                         return -rte_errno;
4058                                 }
4059                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
4060                                            nvgre_spec->tni, 3);
4061                                 filter->tenant_id =
4062                                         rte_be_to_cpu_32(tenant_id_be);
4063                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
4064                         }
4065
4066                         nvgre_flag = 1;
4067                         break;
4068                 default:
4069                         break;
4070                 }
4071         }
4072
4073         ret = i40e_check_tunnel_filter_type(filter_type);
4074         if (ret < 0) {
4075                 rte_flow_error_set(error, EINVAL,
4076                                    RTE_FLOW_ERROR_TYPE_ITEM,
4077                                    NULL,
4078                                    "Invalid filter type");
4079                 return -rte_errno;
4080         }
4081         filter->filter_type = filter_type;
4082
4083         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
4084
4085         return 0;
4086 }
4087
4088 static int
4089 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
4090                              const struct rte_flow_attr *attr,
4091                              const struct rte_flow_item pattern[],
4092                              const struct rte_flow_action actions[],
4093                              struct rte_flow_error *error,
4094                              union i40e_filter_t *filter)
4095 {
4096         struct i40e_tunnel_filter_conf *tunnel_filter =
4097                 &filter->consistent_tunnel_filter;
4098         int ret;
4099
4100         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
4101                                             error, tunnel_filter);
4102         if (ret)
4103                 return ret;
4104
4105         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4106         if (ret)
4107                 return ret;
4108
4109         ret = i40e_flow_parse_attr(attr, error);
4110         if (ret)
4111                 return ret;
4112
4113         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4114
4115         return ret;
4116 }
4117
4118 /* 1. Last in item should be NULL as range is not supported.
4119  * 2. Supported filter types: MPLS label.
4120  * 3. Mask of fields which need to be matched should be
4121  *    filled with 1.
4122  * 4. Mask of fields which needn't to be matched should be
4123  *    filled with 0.
4124  */
4125 static int
4126 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
4127                              const struct rte_flow_item *pattern,
4128                              struct rte_flow_error *error,
4129                              struct i40e_tunnel_filter_conf *filter)
4130 {
4131         const struct rte_flow_item *item = pattern;
4132         const struct rte_flow_item_mpls *mpls_spec;
4133         const struct rte_flow_item_mpls *mpls_mask;
4134         enum rte_flow_item_type item_type;
4135         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
4136         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
4137         uint32_t label_be = 0;
4138
4139         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4140                 if (item->last) {
4141                         rte_flow_error_set(error, EINVAL,
4142                                            RTE_FLOW_ERROR_TYPE_ITEM,
4143                                            item,
4144                                            "Not support range");
4145                         return -rte_errno;
4146                 }
4147                 item_type = item->type;
4148                 switch (item_type) {
4149                 case RTE_FLOW_ITEM_TYPE_ETH:
4150                         if (item->spec || item->mask) {
4151                                 rte_flow_error_set(error, EINVAL,
4152                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4153                                                    item,
4154                                                    "Invalid ETH item");
4155                                 return -rte_errno;
4156                         }
4157                         break;
4158                 case RTE_FLOW_ITEM_TYPE_IPV4:
4159                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4160                         /* IPv4 is used to describe protocol,
4161                          * spec and mask should be NULL.
4162                          */
4163                         if (item->spec || item->mask) {
4164                                 rte_flow_error_set(error, EINVAL,
4165                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4166                                                    item,
4167                                                    "Invalid IPv4 item");
4168                                 return -rte_errno;
4169                         }
4170                         break;
4171                 case RTE_FLOW_ITEM_TYPE_IPV6:
4172                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
4173                         /* IPv6 is used to describe protocol,
4174                          * spec and mask should be NULL.
4175                          */
4176                         if (item->spec || item->mask) {
4177                                 rte_flow_error_set(error, EINVAL,
4178                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4179                                                    item,
4180                                                    "Invalid IPv6 item");
4181                                 return -rte_errno;
4182                         }
4183                         break;
4184                 case RTE_FLOW_ITEM_TYPE_UDP:
4185                         /* UDP is used to describe protocol,
4186                          * spec and mask should be NULL.
4187                          */
4188                         if (item->spec || item->mask) {
4189                                 rte_flow_error_set(error, EINVAL,
4190                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4191                                                    item,
4192                                                    "Invalid UDP item");
4193                                 return -rte_errno;
4194                         }
4195                         is_mplsoudp = 1;
4196                         break;
4197                 case RTE_FLOW_ITEM_TYPE_GRE:
4198                         /* GRE is used to describe protocol,
4199                          * spec and mask should be NULL.
4200                          */
4201                         if (item->spec || item->mask) {
4202                                 rte_flow_error_set(error, EINVAL,
4203                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4204                                                    item,
4205                                                    "Invalid GRE item");
4206                                 return -rte_errno;
4207                         }
4208                         break;
4209                 case RTE_FLOW_ITEM_TYPE_MPLS:
4210                         mpls_spec = item->spec;
4211                         mpls_mask = item->mask;
4212
4213                         if (!mpls_spec || !mpls_mask) {
4214                                 rte_flow_error_set(error, EINVAL,
4215                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4216                                                    item,
4217                                                    "Invalid MPLS item");
4218                                 return -rte_errno;
4219                         }
4220
4221                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
4222                                 rte_flow_error_set(error, EINVAL,
4223                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4224                                                    item,
4225                                                    "Invalid MPLS label mask");
4226                                 return -rte_errno;
4227                         }
4228                         rte_memcpy(((uint8_t *)&label_be + 1),
4229                                    mpls_spec->label_tc_s, 3);
4230                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
4231                         break;
4232                 default:
4233                         break;
4234                 }
4235         }
4236
4237         if (is_mplsoudp)
4238                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
4239         else
4240                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
4241
4242         return 0;
4243 }
4244
4245 static int
4246 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
4247                             const struct rte_flow_attr *attr,
4248                             const struct rte_flow_item pattern[],
4249                             const struct rte_flow_action actions[],
4250                             struct rte_flow_error *error,
4251                             union i40e_filter_t *filter)
4252 {
4253         struct i40e_tunnel_filter_conf *tunnel_filter =
4254                 &filter->consistent_tunnel_filter;
4255         int ret;
4256
4257         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
4258                                            error, tunnel_filter);
4259         if (ret)
4260                 return ret;
4261
4262         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4263         if (ret)
4264                 return ret;
4265
4266         ret = i40e_flow_parse_attr(attr, error);
4267         if (ret)
4268                 return ret;
4269
4270         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4271
4272         return ret;
4273 }
4274
4275 /* 1. Last in item should be NULL as range is not supported.
4276  * 2. Supported filter types: GTP TEID.
4277  * 3. Mask of fields which need to be matched should be
4278  *    filled with 1.
4279  * 4. Mask of fields which needn't to be matched should be
4280  *    filled with 0.
4281  * 5. GTP profile supports GTPv1 only.
4282  * 6. GTP-C response message ('source_port' = 2123) is not supported.
4283  */
4284 static int
4285 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
4286                             const struct rte_flow_item *pattern,
4287                             struct rte_flow_error *error,
4288                             struct i40e_tunnel_filter_conf *filter)
4289 {
4290         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4291         const struct rte_flow_item *item = pattern;
4292         const struct rte_flow_item_gtp *gtp_spec;
4293         const struct rte_flow_item_gtp *gtp_mask;
4294         enum rte_flow_item_type item_type;
4295
4296         if (!pf->gtp_support) {
4297                 rte_flow_error_set(error, EINVAL,
4298                                    RTE_FLOW_ERROR_TYPE_ITEM,
4299                                    item,
4300                                    "GTP is not supported by default.");
4301                 return -rte_errno;
4302         }
4303
4304         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4305                 if (item->last) {
4306                         rte_flow_error_set(error, EINVAL,
4307                                            RTE_FLOW_ERROR_TYPE_ITEM,
4308                                            item,
4309                                            "Not support range");
4310                         return -rte_errno;
4311                 }
4312                 item_type = item->type;
4313                 switch (item_type) {
4314                 case RTE_FLOW_ITEM_TYPE_ETH:
4315                         if (item->spec || item->mask) {
4316                                 rte_flow_error_set(error, EINVAL,
4317                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4318                                                    item,
4319                                                    "Invalid ETH item");
4320                                 return -rte_errno;
4321                         }
4322                         break;
4323                 case RTE_FLOW_ITEM_TYPE_IPV4:
4324                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
4325                         /* IPv4 is used to describe protocol,
4326                          * spec and mask should be NULL.
4327                          */
4328                         if (item->spec || item->mask) {
4329                                 rte_flow_error_set(error, EINVAL,
4330                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4331                                                    item,
4332                                                    "Invalid IPv4 item");
4333                                 return -rte_errno;
4334                         }
4335                         break;
4336                 case RTE_FLOW_ITEM_TYPE_UDP:
4337                         if (item->spec || item->mask) {
4338                                 rte_flow_error_set(error, EINVAL,
4339                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4340                                                    item,
4341                                                    "Invalid UDP item");
4342                                 return -rte_errno;
4343                         }
4344                         break;
4345                 case RTE_FLOW_ITEM_TYPE_GTPC:
4346                 case RTE_FLOW_ITEM_TYPE_GTPU:
4347                         gtp_spec = item->spec;
4348                         gtp_mask = item->mask;
4349
4350                         if (!gtp_spec || !gtp_mask) {
4351                                 rte_flow_error_set(error, EINVAL,
4352                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4353                                                    item,
4354                                                    "Invalid GTP item");
4355                                 return -rte_errno;
4356                         }
4357
4358                         if (gtp_mask->v_pt_rsv_flags ||
4359                             gtp_mask->msg_type ||
4360                             gtp_mask->msg_len ||
4361                             gtp_mask->teid != UINT32_MAX) {
4362                                 rte_flow_error_set(error, EINVAL,
4363                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4364                                                    item,
4365                                                    "Invalid GTP mask");
4366                                 return -rte_errno;
4367                         }
4368
4369                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
4370                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
4371                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
4372                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
4373
4374                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
4375
4376                         break;
4377                 default:
4378                         break;
4379                 }
4380         }
4381
4382         return 0;
4383 }
4384
4385 static int
4386 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4387                            const struct rte_flow_attr *attr,
4388                            const struct rte_flow_item pattern[],
4389                            const struct rte_flow_action actions[],
4390                            struct rte_flow_error *error,
4391                            union i40e_filter_t *filter)
4392 {
4393         struct i40e_tunnel_filter_conf *tunnel_filter =
4394                 &filter->consistent_tunnel_filter;
4395         int ret;
4396
4397         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4398                                           error, tunnel_filter);
4399         if (ret)
4400                 return ret;
4401
4402         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4403         if (ret)
4404                 return ret;
4405
4406         ret = i40e_flow_parse_attr(attr, error);
4407         if (ret)
4408                 return ret;
4409
4410         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4411
4412         return ret;
4413 }
4414
4415 /* 1. Last in item should be NULL as range is not supported.
4416  * 2. Supported filter types: QINQ.
4417  * 3. Mask of fields which need to be matched should be
4418  *    filled with 1.
4419  * 4. Mask of fields which needn't to be matched should be
4420  *    filled with 0.
4421  */
4422 static int
4423 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4424                               const struct rte_flow_item *pattern,
4425                               struct rte_flow_error *error,
4426                               struct i40e_tunnel_filter_conf *filter)
4427 {
4428         const struct rte_flow_item *item = pattern;
4429         const struct rte_flow_item_vlan *vlan_spec = NULL;
4430         const struct rte_flow_item_vlan *vlan_mask = NULL;
4431         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4432         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4433         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4434         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4435
4436         enum rte_flow_item_type item_type;
4437         bool vlan_flag = 0;
4438
4439         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4440                 if (item->last) {
4441                         rte_flow_error_set(error, EINVAL,
4442                                            RTE_FLOW_ERROR_TYPE_ITEM,
4443                                            item,
4444                                            "Not support range");
4445                         return -rte_errno;
4446                 }
4447                 item_type = item->type;
4448                 switch (item_type) {
4449                 case RTE_FLOW_ITEM_TYPE_ETH:
4450                         if (item->spec || item->mask) {
4451                                 rte_flow_error_set(error, EINVAL,
4452                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4453                                                    item,
4454                                                    "Invalid ETH item");
4455                                 return -rte_errno;
4456                         }
4457                         break;
4458                 case RTE_FLOW_ITEM_TYPE_VLAN:
4459                         vlan_spec = item->spec;
4460                         vlan_mask = item->mask;
4461
4462                         if (!(vlan_spec && vlan_mask) ||
4463                             vlan_mask->inner_type) {
4464                                 rte_flow_error_set(error, EINVAL,
4465                                            RTE_FLOW_ERROR_TYPE_ITEM,
4466                                            item,
4467                                            "Invalid vlan item");
4468                                 return -rte_errno;
4469                         }
4470
4471                         if (!vlan_flag) {
4472                                 o_vlan_spec = vlan_spec;
4473                                 o_vlan_mask = vlan_mask;
4474                                 vlan_flag = 1;
4475                         } else {
4476                                 i_vlan_spec = vlan_spec;
4477                                 i_vlan_mask = vlan_mask;
4478                                 vlan_flag = 0;
4479                         }
4480                         break;
4481
4482                 default:
4483                         break;
4484                 }
4485         }
4486
4487         /* Get filter specification */
4488         if (o_vlan_mask != NULL &&  i_vlan_mask != NULL) {
4489                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci);
4490                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci);
4491         } else {
4492                         rte_flow_error_set(error, EINVAL,
4493                                            RTE_FLOW_ERROR_TYPE_ITEM,
4494                                            NULL,
4495                                            "Invalid filter type");
4496                         return -rte_errno;
4497         }
4498
4499         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4500         return 0;
4501 }
4502
4503 static int
4504 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4505                               const struct rte_flow_attr *attr,
4506                               const struct rte_flow_item pattern[],
4507                               const struct rte_flow_action actions[],
4508                               struct rte_flow_error *error,
4509                               union i40e_filter_t *filter)
4510 {
4511         struct i40e_tunnel_filter_conf *tunnel_filter =
4512                 &filter->consistent_tunnel_filter;
4513         int ret;
4514
4515         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4516                                              error, tunnel_filter);
4517         if (ret)
4518                 return ret;
4519
4520         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4521         if (ret)
4522                 return ret;
4523
4524         ret = i40e_flow_parse_attr(attr, error);
4525         if (ret)
4526                 return ret;
4527
4528         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4529
4530         return ret;
4531 }
4532
4533 /**
4534  * This function is used to do configuration i40e existing RSS with rte_flow.
4535  * It also enable queue region configuration using flow API for i40e.
4536  * pattern can be used indicate what parameters will be include in flow,
4537  * like user_priority or flowtype for queue region or HASH function for RSS.
4538  * Action is used to transmit parameter like queue index and HASH
4539  * function for RSS, or flowtype for queue region configuration.
4540  * For example:
4541  * pattern:
4542  * Case 1: try to transform patterns to pctype. valid pctype will be
4543  *         used in parse action.
4544  * Case 2: only ETH, indicate flowtype for queue region will be parsed.
4545  * Case 3: only VLAN, indicate user_priority for queue region will be parsed.
4546  * So, pattern choice is depened on the purpose of configuration of
4547  * that flow.
4548  * action:
4549  * action RSS will be used to transmit valid parameter with
4550  * struct rte_flow_action_rss for all the 3 case.
4551  */
4552 static int
4553 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4554                              const struct rte_flow_item *pattern,
4555                              struct rte_flow_error *error,
4556                              struct i40e_rss_pattern_info *p_info,
4557                              struct i40e_queue_regions *info)
4558 {
4559         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4560         const struct rte_flow_item *item = pattern;
4561         enum rte_flow_item_type item_type;
4562         struct rte_flow_item *items;
4563         uint32_t item_num = 0; /* non-void item number of pattern*/
4564         uint32_t i = 0;
4565         static const struct {
4566                 enum rte_flow_item_type *item_array;
4567                 uint64_t type;
4568         } i40e_rss_pctype_patterns[] = {
4569                 { pattern_fdir_ipv4,
4570                         ETH_RSS_FRAG_IPV4 | ETH_RSS_NONFRAG_IPV4_OTHER },
4571                 { pattern_fdir_ipv4_tcp, ETH_RSS_NONFRAG_IPV4_TCP },
4572                 { pattern_fdir_ipv4_udp, ETH_RSS_NONFRAG_IPV4_UDP },
4573                 { pattern_fdir_ipv4_sctp, ETH_RSS_NONFRAG_IPV4_SCTP },
4574                 { pattern_fdir_ipv4_esp, ETH_RSS_ESP },
4575                 { pattern_fdir_ipv4_udp_esp, ETH_RSS_ESP },
4576                 { pattern_fdir_ipv6,
4577                         ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_OTHER },
4578                 { pattern_fdir_ipv6_tcp, ETH_RSS_NONFRAG_IPV6_TCP },
4579                 { pattern_fdir_ipv6_udp, ETH_RSS_NONFRAG_IPV6_UDP },
4580                 { pattern_fdir_ipv6_sctp, ETH_RSS_NONFRAG_IPV6_SCTP },
4581                 { pattern_ethertype, ETH_RSS_L2_PAYLOAD },
4582                 { pattern_fdir_ipv6_esp, ETH_RSS_ESP },
4583                 { pattern_fdir_ipv6_udp_esp, ETH_RSS_ESP },
4584         };
4585
4586         p_info->types = I40E_RSS_TYPE_INVALID;
4587
4588         if (item->type == RTE_FLOW_ITEM_TYPE_END) {
4589                 p_info->types = I40E_RSS_TYPE_NONE;
4590                 return 0;
4591         }
4592
4593         /* Convert pattern to RSS offload types */
4594         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4595                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4596                         item_num++;
4597                 i++;
4598         }
4599         item_num++;
4600
4601         items = rte_zmalloc("i40e_pattern",
4602                             item_num * sizeof(struct rte_flow_item), 0);
4603         if (!items) {
4604                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4605                                    NULL, "No memory for PMD internal items.");
4606                 return -ENOMEM;
4607         }
4608
4609         i40e_pattern_skip_void_item(items, pattern);
4610
4611         for (i = 0; i < RTE_DIM(i40e_rss_pctype_patterns); i++) {
4612                 if (i40e_match_pattern(i40e_rss_pctype_patterns[i].item_array,
4613                                         items)) {
4614                         p_info->types = i40e_rss_pctype_patterns[i].type;
4615                         break;
4616                 }
4617         }
4618
4619         rte_free(items);
4620
4621         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4622                 if (item->last) {
4623                         rte_flow_error_set(error, EINVAL,
4624                                            RTE_FLOW_ERROR_TYPE_ITEM,
4625                                            item,
4626                                            "Not support range");
4627                         return -rte_errno;
4628                 }
4629                 item_type = item->type;
4630                 switch (item_type) {
4631                 case RTE_FLOW_ITEM_TYPE_ETH:
4632                         p_info->action_flag = 1;
4633                         break;
4634                 case RTE_FLOW_ITEM_TYPE_VLAN:
4635                         vlan_spec = item->spec;
4636                         vlan_mask = item->mask;
4637                         if (vlan_spec && vlan_mask) {
4638                                 if (vlan_mask->tci ==
4639                                         rte_cpu_to_be_16(I40E_VLAN_TCI_MASK)) {
4640                                         info->region[0].user_priority[0] =
4641                                                 (rte_be_to_cpu_16(
4642                                                 vlan_spec->tci) >> 13) & 0x7;
4643                                         info->region[0].user_priority_num = 1;
4644                                         info->queue_region_number = 1;
4645                                         p_info->action_flag = 0;
4646                                 }
4647                         }
4648                         break;
4649                 default:
4650                         p_info->action_flag = 0;
4651                         memset(info, 0, sizeof(struct i40e_queue_regions));
4652                         return 0;
4653                 }
4654         }
4655
4656         return 0;
4657 }
4658
4659 /**
4660  * This function is used to parse RSS queue index, total queue number and
4661  * hash functions, If the purpose of this configuration is for queue region
4662  * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4663  * In queue region configuration, it also need to parse hardware flowtype
4664  * and user_priority from configuration, it will also cheeck the validity
4665  * of these parameters. For example, The queue region sizes should
4666  * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4667  * hw_flowtype or PCTYPE max index should be 63, the user priority
4668  * max index should be 7, and so on. And also, queue index should be
4669  * continuous sequence and queue region index should be part of RSS
4670  * queue index for this port.
4671  * For hash params, the pctype in action and pattern must be same.
4672  * Set queue index must be with non-types.
4673  */
4674 static int
4675 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4676                             const struct rte_flow_action *actions,
4677                             struct rte_flow_error *error,
4678                                 struct i40e_rss_pattern_info p_info,
4679                             struct i40e_queue_regions *conf_info,
4680                             union i40e_filter_t *filter)
4681 {
4682         const struct rte_flow_action *act;
4683         const struct rte_flow_action_rss *rss;
4684         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4686         struct i40e_queue_regions *info = &pf->queue_region;
4687         struct i40e_rte_flow_rss_conf *rss_config =
4688                         &filter->rss_conf;
4689         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4690         uint16_t i, j, n, m, tmp, nb_types;
4691         uint32_t index = 0;
4692         uint64_t hf_bit = 1;
4693
4694         static const struct {
4695                 uint64_t rss_type;
4696                 enum i40e_filter_pctype pctype;
4697         } pctype_match_table[] = {
4698                 {ETH_RSS_FRAG_IPV4,
4699                         I40E_FILTER_PCTYPE_FRAG_IPV4},
4700                 {ETH_RSS_NONFRAG_IPV4_TCP,
4701                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP},
4702                 {ETH_RSS_NONFRAG_IPV4_UDP,
4703                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP},
4704                 {ETH_RSS_NONFRAG_IPV4_SCTP,
4705                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP},
4706                 {ETH_RSS_NONFRAG_IPV4_OTHER,
4707                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER},
4708                 {ETH_RSS_FRAG_IPV6,
4709                         I40E_FILTER_PCTYPE_FRAG_IPV6},
4710                 {ETH_RSS_NONFRAG_IPV6_TCP,
4711                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP},
4712                 {ETH_RSS_NONFRAG_IPV6_UDP,
4713                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP},
4714                 {ETH_RSS_NONFRAG_IPV6_SCTP,
4715                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP},
4716                 {ETH_RSS_NONFRAG_IPV6_OTHER,
4717                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER},
4718                 {ETH_RSS_L2_PAYLOAD,
4719                         I40E_FILTER_PCTYPE_L2_PAYLOAD},
4720         };
4721
4722         static const struct {
4723                 uint64_t rss_type;
4724                 enum i40e_filter_pctype pctype;
4725         } pctype_match_table_x722[] = {
4726                 {ETH_RSS_NONFRAG_IPV4_TCP,
4727                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK},
4728                 {ETH_RSS_NONFRAG_IPV4_UDP,
4729                         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP},
4730                 {ETH_RSS_NONFRAG_IPV4_UDP,
4731                         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP},
4732                 {ETH_RSS_NONFRAG_IPV6_TCP,
4733                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK},
4734                 {ETH_RSS_NONFRAG_IPV6_UDP,
4735                         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP},
4736                 {ETH_RSS_NONFRAG_IPV6_UDP,
4737                         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP},
4738         };
4739
4740         NEXT_ITEM_OF_ACTION(act, actions, index);
4741         rss = act->conf;
4742
4743         /**
4744          * RSS only supports forwarding,
4745          * check if the first not void action is RSS.
4746          */
4747         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4748                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4749                 rte_flow_error_set(error, EINVAL,
4750                         RTE_FLOW_ERROR_TYPE_ACTION,
4751                         act, "Not supported action.");
4752                 return -rte_errno;
4753         }
4754
4755         if (p_info.action_flag && rss->queue_num) {
4756                 for (j = 0; j < RTE_DIM(pctype_match_table); j++) {
4757                         if (rss->types & pctype_match_table[j].rss_type) {
4758                                 conf_info->region[0].hw_flowtype[0] =
4759                                         (uint8_t)pctype_match_table[j].pctype;
4760                                 conf_info->region[0].flowtype_num = 1;
4761                                 conf_info->queue_region_number = 1;
4762                                 break;
4763                         }
4764                 }
4765
4766                 if (hw->mac.type == I40E_MAC_X722)
4767                         for (j = 0; j < RTE_DIM(pctype_match_table_x722); j++) {
4768                                 if (rss->types &
4769                                     pctype_match_table_x722[j].rss_type) {
4770                                         m = conf_info->region[0].flowtype_num;
4771                                         conf_info->region[0].hw_flowtype[m] =
4772                                                 pctype_match_table_x722[j].pctype;
4773                                         conf_info->region[0].flowtype_num++;
4774                                         conf_info->queue_region_number = 1;
4775                                 }
4776                         }
4777         }
4778
4779         /**
4780          * Do some queue region related parameters check
4781          * in order to keep queue index for queue region to be
4782          * continuous sequence and also to be part of RSS
4783          * queue index for this port.
4784          */
4785         if (conf_info->queue_region_number) {
4786                 for (i = 0; i < rss->queue_num; i++) {
4787                         for (j = 0; j < rss_info->conf.queue_num; j++) {
4788                                 if (rss->queue[i] == rss_info->conf.queue[j])
4789                                         break;
4790                         }
4791                         if (j == rss_info->conf.queue_num) {
4792                                 rte_flow_error_set(error, EINVAL,
4793                                         RTE_FLOW_ERROR_TYPE_ACTION,
4794                                         act,
4795                                         "no valid queues");
4796                                 return -rte_errno;
4797                         }
4798                 }
4799
4800                 for (i = 0; i < rss->queue_num - 1; i++) {
4801                         if (rss->queue[i + 1] != rss->queue[i] + 1) {
4802                                 rte_flow_error_set(error, EINVAL,
4803                                         RTE_FLOW_ERROR_TYPE_ACTION,
4804                                         act,
4805                                         "no valid queues");
4806                                 return -rte_errno;
4807                         }
4808                 }
4809         }
4810
4811         /* Parse queue region related parameters from configuration */
4812         for (n = 0; n < conf_info->queue_region_number; n++) {
4813                 if (conf_info->region[n].user_priority_num ||
4814                                 conf_info->region[n].flowtype_num) {
4815                         if (!((rte_is_power_of_2(rss->queue_num)) &&
4816                                         rss->queue_num <= 64)) {
4817                                 rte_flow_error_set(error, EINVAL,
4818                                         RTE_FLOW_ERROR_TYPE_ACTION,
4819                                         act,
4820                                         "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4821                                         "total number of queues do not exceed the VSI allocation");
4822                                 return -rte_errno;
4823                         }
4824
4825                         if (conf_info->region[n].user_priority[n] >=
4826                                         I40E_MAX_USER_PRIORITY) {
4827                                 rte_flow_error_set(error, EINVAL,
4828                                         RTE_FLOW_ERROR_TYPE_ACTION,
4829                                         act,
4830                                         "the user priority max index is 7");
4831                                 return -rte_errno;
4832                         }
4833
4834                         if (conf_info->region[n].hw_flowtype[n] >=
4835                                         I40E_FILTER_PCTYPE_MAX) {
4836                                 rte_flow_error_set(error, EINVAL,
4837                                         RTE_FLOW_ERROR_TYPE_ACTION,
4838                                         act,
4839                                         "the hw_flowtype or PCTYPE max index is 63");
4840                                 return -rte_errno;
4841                         }
4842
4843                         for (i = 0; i < info->queue_region_number; i++) {
4844                                 if (info->region[i].queue_num ==
4845                                     rss->queue_num &&
4846                                         info->region[i].queue_start_index ==
4847                                                 rss->queue[0])
4848                                         break;
4849                         }
4850
4851                         if (i == info->queue_region_number) {
4852                                 if (i > I40E_REGION_MAX_INDEX) {
4853                                         rte_flow_error_set(error, EINVAL,
4854                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4855                                                 act,
4856                                                 "the queue region max index is 7");
4857                                         return -rte_errno;
4858                                 }
4859
4860                                 info->region[i].queue_num =
4861                                         rss->queue_num;
4862                                 info->region[i].queue_start_index =
4863                                         rss->queue[0];
4864                                 info->region[i].region_id =
4865                                         info->queue_region_number;
4866
4867                                 j = info->region[i].user_priority_num;
4868                                 tmp = conf_info->region[n].user_priority[0];
4869                                 if (conf_info->region[n].user_priority_num) {
4870                                         info->region[i].user_priority[j] = tmp;
4871                                         info->region[i].user_priority_num++;
4872                                 }
4873
4874                                 for (m = 0; m < conf_info->region[n].flowtype_num; m++) {
4875                                         j = info->region[i].flowtype_num;
4876                                         tmp = conf_info->region[n].hw_flowtype[m];
4877                                         info->region[i].hw_flowtype[j] = tmp;
4878                                         info->region[i].flowtype_num++;
4879                                 }
4880                                 info->queue_region_number++;
4881                         } else {
4882                                 j = info->region[i].user_priority_num;
4883                                 tmp = conf_info->region[n].user_priority[0];
4884                                 if (conf_info->region[n].user_priority_num) {
4885                                         info->region[i].user_priority[j] = tmp;
4886                                         info->region[i].user_priority_num++;
4887                                 }
4888
4889                                 for (m = 0; m < conf_info->region[n].flowtype_num; m++) {
4890                                         j = info->region[i].flowtype_num;
4891                                         tmp = conf_info->region[n].hw_flowtype[m];
4892                                         info->region[i].hw_flowtype[j] = tmp;
4893                                         info->region[i].flowtype_num++;
4894                                 }
4895                         }
4896                 }
4897
4898                 rss_config->queue_region_conf = TRUE;
4899         }
4900
4901         /**
4902          * Return function if this flow is used for queue region configuration
4903          */
4904         if (rss_config->queue_region_conf)
4905                 return 0;
4906
4907         if (!rss) {
4908                 rte_flow_error_set(error, EINVAL,
4909                                 RTE_FLOW_ERROR_TYPE_ACTION,
4910                                 act,
4911                                 "invalid rule");
4912                 return -rte_errno;
4913         }
4914
4915         for (n = 0; n < rss->queue_num; n++) {
4916                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4917                         rte_flow_error_set(error, EINVAL,
4918                                    RTE_FLOW_ERROR_TYPE_ACTION,
4919                                    act,
4920                                    "queue id > max number of queues");
4921                         return -rte_errno;
4922                 }
4923         }
4924
4925         if (rss->queue_num && (p_info.types || rss->types))
4926                 return rte_flow_error_set
4927                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4928                          "RSS types must be empty while configuring queue region");
4929
4930         /* validate pattern and pctype */
4931         if (!(rss->types & p_info.types) &&
4932             (rss->types || p_info.types) && !rss->queue_num)
4933                 return rte_flow_error_set
4934                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
4935                          act, "invalid pctype");
4936
4937         nb_types = 0;
4938         for (n = 0; n < RTE_ETH_FLOW_MAX; n++) {
4939                 if (rss->types & (hf_bit << n))
4940                         nb_types++;
4941                 if (nb_types > 1)
4942                         return rte_flow_error_set
4943                                 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
4944                                  act, "multi pctype is not supported");
4945         }
4946
4947         if (rss->func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
4948             (p_info.types || rss->types || rss->queue_num))
4949                 return rte_flow_error_set
4950                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4951                          "pattern, type and queues must be empty while"
4952                          " setting hash function as simple_xor");
4953
4954         if (rss->func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ &&
4955             !(p_info.types && rss->types))
4956                 return rte_flow_error_set
4957                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4958                          "pctype and queues can not be empty while"
4959                          " setting hash function as symmetric toeplitz");
4960
4961         /* Parse RSS related parameters from configuration */
4962         if (rss->func >= RTE_ETH_HASH_FUNCTION_MAX ||
4963             rss->func == RTE_ETH_HASH_FUNCTION_TOEPLITZ)
4964                 return rte_flow_error_set
4965                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4966                          "RSS hash functions are not supported");
4967         if (rss->level)
4968                 return rte_flow_error_set
4969                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4970                          "a nonzero RSS encapsulation level is not supported");
4971         if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4972                 return rte_flow_error_set
4973                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4974                          "RSS hash key too large");
4975         if (rss->queue_num > RTE_DIM(rss_config->queue))
4976                 return rte_flow_error_set
4977                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4978                          "too many queues for RSS context");
4979         if (i40e_rss_conf_init(rss_config, rss))
4980                 return rte_flow_error_set
4981                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4982                          "RSS context initialization failure");
4983
4984         index++;
4985
4986         /* check if the next not void action is END */
4987         NEXT_ITEM_OF_ACTION(act, actions, index);
4988         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4989                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4990                 rte_flow_error_set(error, EINVAL,
4991                         RTE_FLOW_ERROR_TYPE_ACTION,
4992                         act, "Not supported action.");
4993                 return -rte_errno;
4994         }
4995         rss_config->queue_region_conf = FALSE;
4996
4997         return 0;
4998 }
4999
5000 static int
5001 i40e_parse_rss_filter(struct rte_eth_dev *dev,
5002                         const struct rte_flow_attr *attr,
5003                         const struct rte_flow_item pattern[],
5004                         const struct rte_flow_action actions[],
5005                         union i40e_filter_t *filter,
5006                         struct rte_flow_error *error)
5007 {
5008         struct i40e_rss_pattern_info p_info;
5009         struct i40e_queue_regions info;
5010         int ret;
5011
5012         memset(&info, 0, sizeof(struct i40e_queue_regions));
5013         memset(&p_info, 0, sizeof(struct i40e_rss_pattern_info));
5014
5015         ret = i40e_flow_parse_rss_pattern(dev, pattern,
5016                                         error, &p_info, &info);
5017         if (ret)
5018                 return ret;
5019
5020         ret = i40e_flow_parse_rss_action(dev, actions, error,
5021                                         p_info, &info, filter);
5022         if (ret)
5023                 return ret;
5024
5025         ret = i40e_flow_parse_attr(attr, error);
5026         if (ret)
5027                 return ret;
5028
5029         cons_filter_type = RTE_ETH_FILTER_HASH;
5030
5031         return 0;
5032 }
5033
5034 static int
5035 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
5036                 struct i40e_rte_flow_rss_conf *conf)
5037 {
5038         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5039         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5040         struct i40e_rss_filter *rss_filter;
5041         int ret;
5042
5043         if (conf->queue_region_conf) {
5044                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
5045         } else {
5046                 ret = i40e_config_rss_filter(pf, conf, 1);
5047         }
5048
5049         if (ret)
5050                 return ret;
5051
5052         rss_filter = rte_zmalloc("i40e_rss_filter",
5053                                 sizeof(*rss_filter), 0);
5054         if (rss_filter == NULL) {
5055                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5056                 return -ENOMEM;
5057         }
5058         rss_filter->rss_filter_info = *conf;
5059         /* the rule new created is always valid
5060          * the existing rule covered by new rule will be set invalid
5061          */
5062         rss_filter->rss_filter_info.valid = true;
5063
5064         TAILQ_INSERT_TAIL(&pf->rss_config_list, rss_filter, next);
5065
5066         return 0;
5067 }
5068
5069 static int
5070 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
5071                 struct i40e_rte_flow_rss_conf *conf)
5072 {
5073         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5074         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         struct i40e_rss_filter *rss_filter;
5076         void *temp;
5077
5078         if (conf->queue_region_conf)
5079                 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5080         else
5081                 i40e_config_rss_filter(pf, conf, 0);
5082
5083         TAILQ_FOREACH_SAFE(rss_filter, &pf->rss_config_list, next, temp) {
5084                 if (!memcmp(&rss_filter->rss_filter_info, conf,
5085                         sizeof(struct rte_flow_action_rss))) {
5086                         TAILQ_REMOVE(&pf->rss_config_list, rss_filter, next);
5087                         rte_free(rss_filter);
5088                 }
5089         }
5090         return 0;
5091 }
5092
5093 static int
5094 i40e_flow_validate(struct rte_eth_dev *dev,
5095                    const struct rte_flow_attr *attr,
5096                    const struct rte_flow_item pattern[],
5097                    const struct rte_flow_action actions[],
5098                    struct rte_flow_error *error)
5099 {
5100         struct rte_flow_item *items; /* internal pattern w/o VOID items */
5101         parse_filter_t parse_filter;
5102         uint32_t item_num = 0; /* non-void item number of pattern*/
5103         uint32_t i = 0;
5104         bool flag = false;
5105         int ret = I40E_NOT_SUPPORTED;
5106
5107         if (!pattern) {
5108                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
5109                                    NULL, "NULL pattern.");
5110                 return -rte_errno;
5111         }
5112
5113         if (!actions) {
5114                 rte_flow_error_set(error, EINVAL,
5115                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
5116                                    NULL, "NULL action.");
5117                 return -rte_errno;
5118         }
5119
5120         if (!attr) {
5121                 rte_flow_error_set(error, EINVAL,
5122                                    RTE_FLOW_ERROR_TYPE_ATTR,
5123                                    NULL, "NULL attribute.");
5124                 return -rte_errno;
5125         }
5126         memset(&cons_filter, 0, sizeof(cons_filter));
5127
5128         /* Get the non-void item of action */
5129         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
5130                 i++;
5131
5132         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
5133                 ret = i40e_parse_rss_filter(dev, attr, pattern,
5134                                         actions, &cons_filter, error);
5135                 return ret;
5136         }
5137
5138         i = 0;
5139         /* Get the non-void item number of pattern */
5140         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
5141                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
5142                         item_num++;
5143                 i++;
5144         }
5145         item_num++;
5146
5147         if (item_num <= ARRAY_SIZE(g_items)) {
5148                 items = g_items;
5149         } else {
5150                 items = rte_zmalloc("i40e_pattern",
5151                                     item_num * sizeof(struct rte_flow_item), 0);
5152                 if (!items) {
5153                         rte_flow_error_set(error, ENOMEM,
5154                                         RTE_FLOW_ERROR_TYPE_ITEM_NUM,
5155                                         NULL,
5156                                         "No memory for PMD internal items.");
5157                         return -ENOMEM;
5158                 }
5159         }
5160
5161         i40e_pattern_skip_void_item(items, pattern);
5162
5163         i = 0;
5164         do {
5165                 parse_filter = i40e_find_parse_filter_func(items, &i);
5166                 if (!parse_filter && !flag) {
5167                         rte_flow_error_set(error, EINVAL,
5168                                            RTE_FLOW_ERROR_TYPE_ITEM,
5169                                            pattern, "Unsupported pattern");
5170
5171                         if (items != g_items)
5172                                 rte_free(items);
5173                         return -rte_errno;
5174                 }
5175
5176                 if (parse_filter)
5177                         ret = parse_filter(dev, attr, items, actions,
5178                                            error, &cons_filter);
5179
5180                 flag = true;
5181         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
5182
5183         if (items != g_items)
5184                 rte_free(items);
5185
5186         return ret;
5187 }
5188
5189 static struct rte_flow *
5190 i40e_flow_create(struct rte_eth_dev *dev,
5191                  const struct rte_flow_attr *attr,
5192                  const struct rte_flow_item pattern[],
5193                  const struct rte_flow_action actions[],
5194                  struct rte_flow_error *error)
5195 {
5196         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5197         struct rte_flow *flow = NULL;
5198         struct i40e_fdir_info *fdir_info = &pf->fdir;
5199         int ret;
5200
5201         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
5202         if (ret < 0)
5203                 return NULL;
5204
5205         if (cons_filter_type == RTE_ETH_FILTER_FDIR) {
5206                 flow = i40e_fdir_entry_pool_get(fdir_info);
5207                 if (flow == NULL) {
5208                         rte_flow_error_set(error, ENOBUFS,
5209                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5210                            "Fdir space full");
5211
5212                         return flow;
5213                 }
5214         } else {
5215                 flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
5216                 if (!flow) {
5217                         rte_flow_error_set(error, ENOMEM,
5218                                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5219                                            "Failed to allocate memory");
5220                         return flow;
5221                 }
5222         }
5223
5224         switch (cons_filter_type) {
5225         case RTE_ETH_FILTER_ETHERTYPE:
5226                 ret = i40e_ethertype_filter_set(pf,
5227                                         &cons_filter.ethertype_filter, 1);
5228                 if (ret)
5229                         goto free_flow;
5230                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
5231                                         i40e_ethertype_filter_list);
5232                 break;
5233         case RTE_ETH_FILTER_FDIR:
5234                 ret = i40e_flow_add_del_fdir_filter(dev,
5235                                &cons_filter.fdir_filter, 1);
5236                 if (ret)
5237                         goto free_flow;
5238                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
5239                                         i40e_fdir_filter_list);
5240                 break;
5241         case RTE_ETH_FILTER_TUNNEL:
5242                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
5243                             &cons_filter.consistent_tunnel_filter, 1);
5244                 if (ret)
5245                         goto free_flow;
5246                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
5247                                         i40e_tunnel_filter_list);
5248                 break;
5249         case RTE_ETH_FILTER_HASH:
5250                 ret = i40e_config_rss_filter_set(dev,
5251                             &cons_filter.rss_conf);
5252                 if (ret)
5253                         goto free_flow;
5254                 flow->rule = TAILQ_LAST(&pf->rss_config_list,
5255                                 i40e_rss_conf_list);
5256                 break;
5257         default:
5258                 goto free_flow;
5259         }
5260
5261         flow->filter_type = cons_filter_type;
5262         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
5263         return flow;
5264
5265 free_flow:
5266         rte_flow_error_set(error, -ret,
5267                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5268                            "Failed to create flow.");
5269
5270         if (cons_filter_type != RTE_ETH_FILTER_FDIR)
5271                 rte_free(flow);
5272         else
5273                 i40e_fdir_entry_pool_put(fdir_info, flow);
5274
5275         return NULL;
5276 }
5277
5278 static int
5279 i40e_flow_destroy(struct rte_eth_dev *dev,
5280                   struct rte_flow *flow,
5281                   struct rte_flow_error *error)
5282 {
5283         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5284         enum rte_filter_type filter_type = flow->filter_type;
5285         struct i40e_fdir_info *fdir_info = &pf->fdir;
5286         int ret = 0;
5287
5288         switch (filter_type) {
5289         case RTE_ETH_FILTER_ETHERTYPE:
5290                 ret = i40e_flow_destroy_ethertype_filter(pf,
5291                          (struct i40e_ethertype_filter *)flow->rule);
5292                 break;
5293         case RTE_ETH_FILTER_TUNNEL:
5294                 ret = i40e_flow_destroy_tunnel_filter(pf,
5295                               (struct i40e_tunnel_filter *)flow->rule);
5296                 break;
5297         case RTE_ETH_FILTER_FDIR:
5298                 ret = i40e_flow_add_del_fdir_filter(dev,
5299                                 &((struct i40e_fdir_filter *)flow->rule)->fdir,
5300                                 0);
5301
5302                 /* If the last flow is destroyed, disable fdir. */
5303                 if (!ret && TAILQ_EMPTY(&pf->fdir.fdir_list)) {
5304                         i40e_fdir_rx_proc_enable(dev, 0);
5305                 }
5306                 break;
5307         case RTE_ETH_FILTER_HASH:
5308                 ret = i40e_config_rss_filter_del(dev,
5309                         &((struct i40e_rss_filter *)flow->rule)->rss_filter_info);
5310                 break;
5311         default:
5312                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5313                             filter_type);
5314                 ret = -EINVAL;
5315                 break;
5316         }
5317
5318         if (!ret) {
5319                 TAILQ_REMOVE(&pf->flow_list, flow, node);
5320                 if (filter_type == RTE_ETH_FILTER_FDIR)
5321                         i40e_fdir_entry_pool_put(fdir_info, flow);
5322                 else
5323                         rte_free(flow);
5324
5325         } else
5326                 rte_flow_error_set(error, -ret,
5327                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5328                                    "Failed to destroy flow.");
5329
5330         return ret;
5331 }
5332
5333 static int
5334 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
5335                                    struct i40e_ethertype_filter *filter)
5336 {
5337         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5338         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
5339         struct i40e_ethertype_filter *node;
5340         struct i40e_control_filter_stats stats;
5341         uint16_t flags = 0;
5342         int ret = 0;
5343
5344         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5345                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5346         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5347                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5348         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5349
5350         memset(&stats, 0, sizeof(stats));
5351         ret = i40e_aq_add_rem_control_packet_filter(hw,
5352                                     filter->input.mac_addr.addr_bytes,
5353                                     filter->input.ether_type,
5354                                     flags, pf->main_vsi->seid,
5355                                     filter->queue, 0, &stats, NULL);
5356         if (ret < 0)
5357                 return ret;
5358
5359         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
5360         if (!node)
5361                 return -EINVAL;
5362
5363         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
5364
5365         return ret;
5366 }
5367
5368 static int
5369 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
5370                                 struct i40e_tunnel_filter *filter)
5371 {
5372         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5373         struct i40e_vsi *vsi;
5374         struct i40e_pf_vf *vf;
5375         struct i40e_aqc_cloud_filters_element_bb cld_filter;
5376         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
5377         struct i40e_tunnel_filter *node;
5378         bool big_buffer = 0;
5379         int ret = 0;
5380
5381         memset(&cld_filter, 0, sizeof(cld_filter));
5382         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.outer_mac,
5383                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
5384         rte_ether_addr_copy((struct rte_ether_addr *)&filter->input.inner_mac,
5385                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
5386         cld_filter.element.inner_vlan = filter->input.inner_vlan;
5387         cld_filter.element.flags = filter->input.flags;
5388         cld_filter.element.tenant_id = filter->input.tenant_id;
5389         cld_filter.element.queue_number = filter->queue;
5390         rte_memcpy(cld_filter.general_fields,
5391                    filter->input.general_fields,
5392                    sizeof(cld_filter.general_fields));
5393
5394         if (!filter->is_to_vf)
5395                 vsi = pf->main_vsi;
5396         else {
5397                 vf = &pf->vfs[filter->vf_id];
5398                 vsi = vf->vsi;
5399         }
5400
5401         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
5402             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
5403             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
5404             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
5405             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
5406             I40E_AQC_ADD_CLOUD_FILTER_0X10))
5407                 big_buffer = 1;
5408
5409         if (big_buffer)
5410                 ret = i40e_aq_rem_cloud_filters_bb(hw, vsi->seid,
5411                                                 &cld_filter, 1);
5412         else
5413                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
5414                                                 &cld_filter.element, 1);
5415         if (ret < 0)
5416                 return -ENOTSUP;
5417
5418         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
5419         if (!node)
5420                 return -EINVAL;
5421
5422         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
5423
5424         return ret;
5425 }
5426
5427 static int
5428 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
5429 {
5430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5431         int ret;
5432
5433         ret = i40e_flow_flush_fdir_filter(pf);
5434         if (ret) {
5435                 rte_flow_error_set(error, -ret,
5436                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5437                                    "Failed to flush FDIR flows.");
5438                 return -rte_errno;
5439         }
5440
5441         ret = i40e_flow_flush_ethertype_filter(pf);
5442         if (ret) {
5443                 rte_flow_error_set(error, -ret,
5444                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5445                                    "Failed to ethertype flush flows.");
5446                 return -rte_errno;
5447         }
5448
5449         ret = i40e_flow_flush_tunnel_filter(pf);
5450         if (ret) {
5451                 rte_flow_error_set(error, -ret,
5452                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5453                                    "Failed to flush tunnel flows.");
5454                 return -rte_errno;
5455         }
5456
5457         ret = i40e_flow_flush_rss_filter(dev);
5458         if (ret) {
5459                 rte_flow_error_set(error, -ret,
5460                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
5461                                    "Failed to flush RSS flows.");
5462                 return -rte_errno;
5463         }
5464
5465         return ret;
5466 }
5467
5468 static int
5469 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
5470 {
5471         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5472         struct i40e_fdir_info *fdir_info = &pf->fdir;
5473         struct i40e_fdir_filter *fdir_filter;
5474         enum i40e_filter_pctype pctype;
5475         struct rte_flow *flow;
5476         void *temp;
5477         int ret;
5478         uint32_t i = 0;
5479
5480         ret = i40e_fdir_flush(dev);
5481         if (!ret) {
5482                 /* Delete FDIR filters in FDIR list. */
5483                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
5484                         ret = i40e_sw_fdir_filter_del(pf,
5485                                                       &fdir_filter->fdir.input);
5486                         if (ret < 0)
5487                                 return ret;
5488                 }
5489
5490                 /* Delete FDIR flows in flow list. */
5491                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5492                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
5493                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
5494                         }
5495                 }
5496
5497                 /* reset bitmap */
5498                 rte_bitmap_reset(fdir_info->fdir_flow_pool.bitmap);
5499                 for (i = 0; i < fdir_info->fdir_space_size; i++) {
5500                         fdir_info->fdir_flow_pool.pool[i].idx = i;
5501                         rte_bitmap_set(fdir_info->fdir_flow_pool.bitmap, i);
5502                 }
5503
5504                 fdir_info->fdir_actual_cnt = 0;
5505                 fdir_info->fdir_guarantee_free_space =
5506                         fdir_info->fdir_guarantee_total_space;
5507                 memset(fdir_info->fdir_filter_array,
5508                         0,
5509                         sizeof(struct i40e_fdir_filter) *
5510                         I40E_MAX_FDIR_FILTER_NUM);
5511
5512                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5513                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
5514                         pf->fdir.inset_flag[pctype] = 0;
5515                         pf->fdir.flex_mask_flag[pctype] = 0;
5516                 }
5517
5518                 /* Disable FDIR processing as all FDIR rules are now flushed */
5519                 i40e_fdir_rx_proc_enable(dev, 0);
5520         }
5521
5522         return ret;
5523 }
5524
5525 /* Flush all ethertype filters */
5526 static int
5527 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
5528 {
5529         struct i40e_ethertype_filter_list
5530                 *ethertype_list = &pf->ethertype.ethertype_list;
5531         struct i40e_ethertype_filter *filter;
5532         struct rte_flow *flow;
5533         void *temp;
5534         int ret = 0;
5535
5536         while ((filter = TAILQ_FIRST(ethertype_list))) {
5537                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
5538                 if (ret)
5539                         return ret;
5540         }
5541
5542         /* Delete ethertype flows in flow list. */
5543         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5544                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
5545                         TAILQ_REMOVE(&pf->flow_list, flow, node);
5546                         rte_free(flow);
5547                 }
5548         }
5549
5550         return ret;
5551 }
5552
5553 /* Flush all tunnel filters */
5554 static int
5555 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
5556 {
5557         struct i40e_tunnel_filter_list
5558                 *tunnel_list = &pf->tunnel.tunnel_list;
5559         struct i40e_tunnel_filter *filter;
5560         struct rte_flow *flow;
5561         void *temp;
5562         int ret = 0;
5563
5564         while ((filter = TAILQ_FIRST(tunnel_list))) {
5565                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
5566                 if (ret)
5567                         return ret;
5568         }
5569
5570         /* Delete tunnel flows in flow list. */
5571         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5572                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
5573                         TAILQ_REMOVE(&pf->flow_list, flow, node);
5574                         rte_free(flow);
5575                 }
5576         }
5577
5578         return ret;
5579 }
5580
5581 /* remove the RSS filter */
5582 static int
5583 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
5584 {
5585         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5586         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5587         struct rte_flow *flow;
5588         void *temp;
5589         int32_t ret = -EINVAL;
5590
5591         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
5592
5593         /* Delete RSS flows in flow list. */
5594         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
5595                 if (flow->filter_type != RTE_ETH_FILTER_HASH)
5596                         continue;
5597
5598                 if (flow->rule) {
5599                         ret = i40e_config_rss_filter_del(dev,
5600                                 &((struct i40e_rss_filter *)flow->rule)->rss_filter_info);
5601                         if (ret)
5602                                 return ret;
5603                 }
5604                 TAILQ_REMOVE(&pf->flow_list, flow, node);
5605                 rte_free(flow);
5606         }
5607
5608         return ret;
5609 }
5610
5611 static int
5612 i40e_flow_query(struct rte_eth_dev *dev __rte_unused,
5613                 struct rte_flow *flow,
5614                 const struct rte_flow_action *actions,
5615                 void *data, struct rte_flow_error *error)
5616 {
5617         struct i40e_rss_filter *rss_rule = (struct i40e_rss_filter *)flow->rule;
5618         enum rte_filter_type filter_type = flow->filter_type;
5619         struct rte_flow_action_rss *rss_conf = data;
5620
5621         if (!rss_rule) {
5622                 rte_flow_error_set(error, EINVAL,
5623                                    RTE_FLOW_ERROR_TYPE_HANDLE,
5624                                    NULL, "Invalid rule");
5625                 return -rte_errno;
5626         }
5627
5628         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5629                 switch (actions->type) {
5630                 case RTE_FLOW_ACTION_TYPE_VOID:
5631                         break;
5632                 case RTE_FLOW_ACTION_TYPE_RSS:
5633                         if (filter_type != RTE_ETH_FILTER_HASH) {
5634                                 rte_flow_error_set(error, ENOTSUP,
5635                                                    RTE_FLOW_ERROR_TYPE_ACTION,
5636                                                    actions,
5637                                                    "action not supported");
5638                                 return -rte_errno;
5639                         }
5640                         rte_memcpy(rss_conf,
5641                                    &rss_rule->rss_filter_info.conf,
5642                                    sizeof(struct rte_flow_action_rss));
5643                         break;
5644                 default:
5645                         return rte_flow_error_set(error, ENOTSUP,
5646                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5647                                                   actions,
5648                                                   "action not supported");
5649                 }
5650         }
5651
5652         return 0;
5653 }