drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "i40e_logs.h"
  28 #include "base/i40e_prototype.h"
  29 #include "base/i40e_type.h"
  30 #include "i40e_ethdev.h"
  31 #include "i40e_rxtx.h"
  32
  33 #define DEFAULT_TX_RS_THRESH   32
  34 #define DEFAULT_TX_FREE_THRESH 32
  35
  36 #define I40E_TX_MAX_BURST  32
  37
  38 #define I40E_DMA_MEM_ALIGN 4096
  39
  40 /* Base address of the HW descriptor ring should be 128B aligned. */
  41 #define I40E_RING_BASE_ALIGN    128
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 #ifdef RTE_LIBRTE_IEEE1588
  46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  47 #else
  48 #define I40E_TX_IEEE1588_TMST 0
  49 #endif
  50
  51 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  52                 PKT_TX_IP_CKSUM |                \
  53                 PKT_TX_L4_MASK |                 \
  54                 PKT_TX_TCP_SEG |                 \
  55                 PKT_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (  \
  58                 PKT_TX_OUTER_IPV4 |     \
  59                 PKT_TX_OUTER_IPV6 |     \
  60                 PKT_TX_IPV4 |           \
  61                 PKT_TX_IPV6 |           \
  62                 PKT_TX_IP_CKSUM |       \
  63                 PKT_TX_L4_MASK |        \
  64                 PKT_TX_OUTER_IP_CKSUM | \
  65                 PKT_TX_TCP_SEG |        \
  66                 PKT_TX_QINQ_PKT |       \
  67                 PKT_TX_VLAN_PKT |       \
  68                 PKT_TX_TUNNEL_MASK |    \
  69                 I40E_TX_IEEE1588_TMST)
  70
  71 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  72                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  73
  74 static inline void
  75 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  76 {
  77         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  78                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  79                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
  80                 mb->vlan_tci =
  81                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  82                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  83                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  84         } else {
  85                 mb->vlan_tci = 0;
  86         }
  87 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  88         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
  89                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
  90                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
  91                         PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
  92                 mb->vlan_tci_outer = mb->vlan_tci;
  93                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
  94                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
  95                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
  96                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
  97         } else {
  98                 mb->vlan_tci_outer = 0;
  99         }
 100 #endif
 101         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 102                    mb->vlan_tci, mb->vlan_tci_outer);
 103 }
 104
 105 /* Translate the rx descriptor status to pkt flags */
 106 static inline uint64_t
 107 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 108 {
 109         uint64_t flags;
 110
 111         /* Check if RSS_HASH */
 112         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 113                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 114                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 115
 116         /* Check if FDIR Match */
 117         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 118                                                         PKT_RX_FDIR : 0);
 119
 120         return flags;
 121 }
 122
 123 static inline uint64_t
 124 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 125 {
 126         uint64_t flags = 0;
 127         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 128
 129 #define I40E_RX_ERR_BITS 0x3f
 130         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 131                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 132                 return flags;
 133         }
 134
 135         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 136                 flags |= PKT_RX_IP_CKSUM_BAD;
 137         else
 138                 flags |= PKT_RX_IP_CKSUM_GOOD;
 139
 140         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 141                 flags |= PKT_RX_L4_CKSUM_BAD;
 142         else
 143                 flags |= PKT_RX_L4_CKSUM_GOOD;
 144
 145         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 146                 flags |= PKT_RX_EIP_CKSUM_BAD;
 147
 148         return flags;
 149 }
 150
 151 /* Function to check and set the ieee1588 timesync index and get the
 152  * appropriate flags.
 153  */
 154 #ifdef RTE_LIBRTE_IEEE1588
 155 static inline uint64_t
 156 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 157 {
 158         uint64_t pkt_flags = 0;
 159         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 160                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 161                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 162
 163         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 164                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 165                 pkt_flags = PKT_RX_IEEE1588_PTP;
 166         if (tsyn & 0x04) {
 167                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 168                 mb->timesync = tsyn & 0x03;
 169         }
 170
 171         return pkt_flags;
 172 }
 173 #endif
 174
 175 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 176 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 177 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 178 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 179 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 180
 181 static inline uint64_t
 182 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 183 {
 184         uint64_t flags = 0;
 185 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 186         uint16_t flexbh, flexbl;
 187
 188         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 189                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 190                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 191         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 192                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 193                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 194
 195
 196         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 197                 mb->hash.fdir.hi =
 198                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 199                 flags |= PKT_RX_FDIR_ID;
 200         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 201                 mb->hash.fdir.hi =
 202                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 203                 flags |= PKT_RX_FDIR_FLX;
 204         }
 205         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 206                 mb->hash.fdir.lo =
 207                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 208                 flags |= PKT_RX_FDIR_FLX;
 209         }
 210 #else
 211         mb->hash.fdir.hi =
 212                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 213         flags |= PKT_RX_FDIR_ID;
 214 #endif
 215         return flags;
 216 }
 217
 218 static inline void
 219 i40e_parse_tunneling_params(uint64_t ol_flags,
 220                             union i40e_tx_offload tx_offload,
 221                             uint32_t *cd_tunneling)
 222 {
 223         /* EIPT: External (outer) IP header type */
 224         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 225                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 226         else if (ol_flags & PKT_TX_OUTER_IPV4)
 227                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 228         else if (ol_flags & PKT_TX_OUTER_IPV6)
 229                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 230
 231         /* EIPLEN: External (outer) IP header length, in DWords */
 232         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 233                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 234
 235         /* L4TUNT: L4 Tunneling Type */
 236         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 237         case PKT_TX_TUNNEL_IPIP:
 238                 /* for non UDP / GRE tunneling, set to 00b */
 239                 break;
 240         case PKT_TX_TUNNEL_VXLAN:
 241         case PKT_TX_TUNNEL_GENEVE:
 242                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 243                 break;
 244         case PKT_TX_TUNNEL_GRE:
 245                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 246                 break;
 247         default:
 248                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 249                 return;
 250         }
 251
 252         /* L4TUNLEN: L4 Tunneling Length, in Words
 253          *
 254          * We depend on app to set rte_mbuf.l2_len correctly.
 255          * For IP in GRE it should be set to the length of the GRE
 256          * header;
 257          * for MAC in GRE or MAC in UDP it should be set to the length
 258          * of the GRE or UDP headers plus the inner MAC up to including
 259          * its last Ethertype.
 260          */
 261         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 262                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 263 }
 264
 265 static inline void
 266 i40e_txd_enable_checksum(uint64_t ol_flags,
 267                         uint32_t *td_cmd,
 268                         uint32_t *td_offset,
 269                         union i40e_tx_offload tx_offload)
 270 {
 271         /* Set MACLEN */
 272         if (ol_flags & PKT_TX_TUNNEL_MASK)
 273                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 274                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 275         else
 276                 *td_offset |= (tx_offload.l2_len >> 1)
 277                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 278
 279         /* Enable L3 checksum offloads */
 280         if (ol_flags & PKT_TX_IP_CKSUM) {
 281                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 282                 *td_offset |= (tx_offload.l3_len >> 2)
 283                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 284         } else if (ol_flags & PKT_TX_IPV4) {
 285                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 286                 *td_offset |= (tx_offload.l3_len >> 2)
 287                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 288         } else if (ol_flags & PKT_TX_IPV6) {
 289                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 290                 *td_offset |= (tx_offload.l3_len >> 2)
 291                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 292         }
 293
 294         if (ol_flags & PKT_TX_TCP_SEG) {
 295                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 296                 *td_offset |= (tx_offload.l4_len >> 2)
 297                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 298                 return;
 299         }
 300
 301         /* Enable L4 checksum offloads */
 302         switch (ol_flags & PKT_TX_L4_MASK) {
 303         case PKT_TX_TCP_CKSUM:
 304                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 305                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
 306                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 307                 break;
 308         case PKT_TX_SCTP_CKSUM:
 309                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 310                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
 311                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 312                 break;
 313         case PKT_TX_UDP_CKSUM:
 314                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 315                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
 316                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 317                 break;
 318         default:
 319                 break;
 320         }
 321 }
 322
 323 /* Construct the tx flags */
 324 static inline uint64_t
 325 i40e_build_ctob(uint32_t td_cmd,
 326                 uint32_t td_offset,
 327                 unsigned int size,
 328                 uint32_t td_tag)
 329 {
 330         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 331                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 332                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 333                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 334                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 335 }
 336
 337 static inline int
 338 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 339 {
 340         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 341         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 342         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 343         uint16_t nb_tx_desc = txq->nb_tx_desc;
 344         uint16_t desc_to_clean_to;
 345         uint16_t nb_tx_to_clean;
 346
 347         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 348         if (desc_to_clean_to >= nb_tx_desc)
 349                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 350
 351         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 352         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 353                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 354                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 355                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 356                         "(port=%d queue=%d)", desc_to_clean_to,
 357                                 txq->port_id, txq->queue_id);
 358                 return -1;
 359         }
 360
 361         if (last_desc_cleaned > desc_to_clean_to)
 362                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 363                                                         desc_to_clean_to);
 364         else
 365                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 366                                         last_desc_cleaned);
 367
 368         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 369
 370         txq->last_desc_cleaned = desc_to_clean_to;
 371         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 372
 373         return 0;
 374 }
 375
 376 static inline int
 377 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 378 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 379 #else
 380 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 381 #endif
 382 {
 383         int ret = 0;
 384
 385 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 386         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 387                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 388                              "rxq->rx_free_thresh=%d, "
 389                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 390                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 391                 ret = -EINVAL;
 392         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 393                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 394                              "rxq->rx_free_thresh=%d, "
 395                              "rxq->nb_rx_desc=%d",
 396                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 397                 ret = -EINVAL;
 398         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 399                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 400                              "rxq->nb_rx_desc=%d, "
 401                              "rxq->rx_free_thresh=%d",
 402                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 403                 ret = -EINVAL;
 404         }
 405 #else
 406         ret = -EINVAL;
 407 #endif
 408
 409         return ret;
 410 }
 411
 412 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 413 #define I40E_LOOK_AHEAD 8
 414 #if (I40E_LOOK_AHEAD != 8)
 415 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 416 #endif
 417 static inline int
 418 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 419 {
 420         volatile union i40e_rx_desc *rxdp;
 421         struct i40e_rx_entry *rxep;
 422         struct rte_mbuf *mb;
 423         uint16_t pkt_len;
 424         uint64_t qword1;
 425         uint32_t rx_status;
 426         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 427         int32_t i, j, nb_rx = 0;
 428         uint64_t pkt_flags;
 429         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 430
 431         rxdp = &rxq->rx_ring[rxq->rx_tail];
 432         rxep = &rxq->sw_ring[rxq->rx_tail];
 433
 434         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 435         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 436                                 I40E_RXD_QW1_STATUS_SHIFT;
 437
 438         /* Make sure there is at least 1 packet to receive */
 439         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 440                 return 0;
 441
 442         /**
 443          * Scan LOOK_AHEAD descriptors at a time to determine which
 444          * descriptors reference packets that are ready to be received.
 445          */
 446         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 447                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 448                 /* Read desc statuses backwards to avoid race condition */
 449                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 450                         qword1 = rte_le_to_cpu_64(\
 451                                 rxdp[j].wb.qword1.status_error_len);
 452                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 453                                         I40E_RXD_QW1_STATUS_SHIFT;
 454                 }
 455
 456                 rte_smp_rmb();
 457
 458                 /* Compute how many status bits were set */
 459                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 460                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 461
 462                 nb_rx += nb_dd;
 463
 464                 /* Translate descriptor info to mbuf parameters */
 465                 for (j = 0; j < nb_dd; j++) {
 466                         mb = rxep[j].mbuf;
 467                         qword1 = rte_le_to_cpu_64(\
 468                                 rxdp[j].wb.qword1.status_error_len);
 469                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 470                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 471                         mb->data_len = pkt_len;
 472                         mb->pkt_len = pkt_len;
 473                         mb->ol_flags = 0;
 474                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 475                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 476                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 477                         mb->packet_type =
 478                                 ptype_tbl[(uint8_t)((qword1 &
 479                                 I40E_RXD_QW1_PTYPE_MASK) >>
 480                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 481                         if (pkt_flags & PKT_RX_RSS_HASH)
 482                                 mb->hash.rss = rte_le_to_cpu_32(\
 483                                         rxdp[j].wb.qword0.hi_dword.rss);
 484                         if (pkt_flags & PKT_RX_FDIR)
 485                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 486
 487 #ifdef RTE_LIBRTE_IEEE1588
 488                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 489 #endif
 490                         mb->ol_flags |= pkt_flags;
 491
 492                 }
 493
 494                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 495                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 496
 497                 if (nb_dd != I40E_LOOK_AHEAD)
 498                         break;
 499         }
 500
 501         /* Clear software ring entries */
 502         for (i = 0; i < nb_rx; i++)
 503                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 504
 505         return nb_rx;
 506 }
 507
 508 static inline uint16_t
 509 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 510                         struct rte_mbuf **rx_pkts,
 511                         uint16_t nb_pkts)
 512 {
 513         uint16_t i;
 514         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 515
 516         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 517
 518         for (i = 0; i < nb_pkts; i++)
 519                 rx_pkts[i] = stage[i];
 520
 521         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 522         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 523
 524         return nb_pkts;
 525 }
 526
 527 static inline int
 528 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 529 {
 530         volatile union i40e_rx_desc *rxdp;
 531         struct i40e_rx_entry *rxep;
 532         struct rte_mbuf *mb;
 533         uint16_t alloc_idx, i;
 534         uint64_t dma_addr;
 535         int diag;
 536
 537         /* Allocate buffers in bulk */
 538         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 539                                 (rxq->rx_free_thresh - 1));
 540         rxep = &(rxq->sw_ring[alloc_idx]);
 541         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 542                                         rxq->rx_free_thresh);
 543         if (unlikely(diag != 0)) {
 544                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 545                 return -ENOMEM;
 546         }
 547
 548         rxdp = &rxq->rx_ring[alloc_idx];
 549         for (i = 0; i < rxq->rx_free_thresh; i++) {
 550                 if (likely(i < (rxq->rx_free_thresh - 1)))
 551                         /* Prefetch next mbuf */
 552                         rte_prefetch0(rxep[i + 1].mbuf);
 553
 554                 mb = rxep[i].mbuf;
 555                 rte_mbuf_refcnt_set(mb, 1);
 556                 mb->next = NULL;
 557                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 558                 mb->nb_segs = 1;
 559                 mb->port = rxq->port_id;
 560                 dma_addr = rte_cpu_to_le_64(\
 561                         rte_mbuf_data_iova_default(mb));
 562                 rxdp[i].read.hdr_addr = 0;
 563                 rxdp[i].read.pkt_addr = dma_addr;
 564         }
 565
 566         /* Update rx tail regsiter */
 567         rte_wmb();
 568         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 569
 570         rxq->rx_free_trigger =
 571                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 572         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 573                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 574
 575         return 0;
 576 }
 577
 578 static inline uint16_t
 579 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 580 {
 581         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 582         struct rte_eth_dev *dev;
 583         uint16_t nb_rx = 0;
 584
 585         if (!nb_pkts)
 586                 return 0;
 587
 588         if (rxq->rx_nb_avail)
 589                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 590
 591         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 592         rxq->rx_next_avail = 0;
 593         rxq->rx_nb_avail = nb_rx;
 594         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 595
 596         if (rxq->rx_tail > rxq->rx_free_trigger) {
 597                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 598                         uint16_t i, j;
 599
 600                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 601                         dev->data->rx_mbuf_alloc_failed +=
 602                                 rxq->rx_free_thresh;
 603
 604                         rxq->rx_nb_avail = 0;
 605                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 606                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 607                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 608
 609                         return 0;
 610                 }
 611         }
 612
 613         if (rxq->rx_tail >= rxq->nb_rx_desc)
 614                 rxq->rx_tail = 0;
 615
 616         if (rxq->rx_nb_avail)
 617                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 618
 619         return 0;
 620 }
 621
 622 static uint16_t
 623 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 624                           struct rte_mbuf **rx_pkts,
 625                           uint16_t nb_pkts)
 626 {
 627         uint16_t nb_rx = 0, n, count;
 628
 629         if (unlikely(nb_pkts == 0))
 630                 return 0;
 631
 632         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 633                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 634
 635         while (nb_pkts) {
 636                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 637                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 638                 nb_rx = (uint16_t)(nb_rx + count);
 639                 nb_pkts = (uint16_t)(nb_pkts - count);
 640                 if (count < n)
 641                         break;
 642         }
 643
 644         return nb_rx;
 645 }
 646 #else
 647 static uint16_t
 648 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 649                           struct rte_mbuf __rte_unused **rx_pkts,
 650                           uint16_t __rte_unused nb_pkts)
 651 {
 652         return 0;
 653 }
 654 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 655
 656 uint16_t
 657 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 658 {
 659         struct i40e_rx_queue *rxq;
 660         volatile union i40e_rx_desc *rx_ring;
 661         volatile union i40e_rx_desc *rxdp;
 662         union i40e_rx_desc rxd;
 663         struct i40e_rx_entry *sw_ring;
 664         struct i40e_rx_entry *rxe;
 665         struct rte_eth_dev *dev;
 666         struct rte_mbuf *rxm;
 667         struct rte_mbuf *nmb;
 668         uint16_t nb_rx;
 669         uint32_t rx_status;
 670         uint64_t qword1;
 671         uint16_t rx_packet_len;
 672         uint16_t rx_id, nb_hold;
 673         uint64_t dma_addr;
 674         uint64_t pkt_flags;
 675         uint32_t *ptype_tbl;
 676
 677         nb_rx = 0;
 678         nb_hold = 0;
 679         rxq = rx_queue;
 680         rx_id = rxq->rx_tail;
 681         rx_ring = rxq->rx_ring;
 682         sw_ring = rxq->sw_ring;
 683         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 684
 685         while (nb_rx < nb_pkts) {
 686                 rxdp = &rx_ring[rx_id];
 687                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 688                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 689                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 690
 691                 /* Check the DD bit first */
 692                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 693                         break;
 694
 695                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 696                 if (unlikely(!nmb)) {
 697                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 698                         dev->data->rx_mbuf_alloc_failed++;
 699                         break;
 700                 }
 701
 702                 rxd = *rxdp;
 703                 nb_hold++;
 704                 rxe = &sw_ring[rx_id];
 705                 rx_id++;
 706                 if (unlikely(rx_id == rxq->nb_rx_desc))
 707                         rx_id = 0;
 708
 709                 /* Prefetch next mbuf */
 710                 rte_prefetch0(sw_ring[rx_id].mbuf);
 711
 712                 /**
 713                  * When next RX descriptor is on a cache line boundary,
 714                  * prefetch the next 4 RX descriptors and next 8 pointers
 715                  * to mbufs.
 716                  */
 717                 if ((rx_id & 0x3) == 0) {
 718                         rte_prefetch0(&rx_ring[rx_id]);
 719                         rte_prefetch0(&sw_ring[rx_id]);
 720                 }
 721                 rxm = rxe->mbuf;
 722                 rxe->mbuf = nmb;
 723                 dma_addr =
 724                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 725                 rxdp->read.hdr_addr = 0;
 726                 rxdp->read.pkt_addr = dma_addr;
 727
 728                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 729                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 730
 731                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 732                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 733                 rxm->nb_segs = 1;
 734                 rxm->next = NULL;
 735                 rxm->pkt_len = rx_packet_len;
 736                 rxm->data_len = rx_packet_len;
 737                 rxm->port = rxq->port_id;
 738                 rxm->ol_flags = 0;
 739                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 740                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 741                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 742                 rxm->packet_type =
 743                         ptype_tbl[(uint8_t)((qword1 &
 744                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 745                 if (pkt_flags & PKT_RX_RSS_HASH)
 746                         rxm->hash.rss =
 747                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 748                 if (pkt_flags & PKT_RX_FDIR)
 749                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 750
 751 #ifdef RTE_LIBRTE_IEEE1588
 752                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 753 #endif
 754                 rxm->ol_flags |= pkt_flags;
 755
 756                 rx_pkts[nb_rx++] = rxm;
 757         }
 758         rxq->rx_tail = rx_id;
 759
 760         /**
 761          * If the number of free RX descriptors is greater than the RX free
 762          * threshold of the queue, advance the receive tail register of queue.
 763          * Update that register with the value of the last processed RX
 764          * descriptor minus 1.
 765          */
 766         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 767         if (nb_hold > rxq->rx_free_thresh) {
 768                 rx_id = (uint16_t) ((rx_id == 0) ?
 769                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 770                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 771                 nb_hold = 0;
 772         }
 773         rxq->nb_rx_hold = nb_hold;
 774
 775         return nb_rx;
 776 }
 777
 778 uint16_t
 779 i40e_recv_scattered_pkts(void *rx_queue,
 780                          struct rte_mbuf **rx_pkts,
 781                          uint16_t nb_pkts)
 782 {
 783         struct i40e_rx_queue *rxq = rx_queue;
 784         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 785         volatile union i40e_rx_desc *rxdp;
 786         union i40e_rx_desc rxd;
 787         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 788         struct i40e_rx_entry *rxe;
 789         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 790         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 791         struct rte_mbuf *nmb, *rxm;
 792         uint16_t rx_id = rxq->rx_tail;
 793         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 794         struct rte_eth_dev *dev;
 795         uint32_t rx_status;
 796         uint64_t qword1;
 797         uint64_t dma_addr;
 798         uint64_t pkt_flags;
 799         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 800
 801         while (nb_rx < nb_pkts) {
 802                 rxdp = &rx_ring[rx_id];
 803                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 804                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 805                                         I40E_RXD_QW1_STATUS_SHIFT;
 806
 807                 /* Check the DD bit */
 808                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 809                         break;
 810
 811                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 812                 if (unlikely(!nmb)) {
 813                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 814                         dev->data->rx_mbuf_alloc_failed++;
 815                         break;
 816                 }
 817
 818                 rxd = *rxdp;
 819                 nb_hold++;
 820                 rxe = &sw_ring[rx_id];
 821                 rx_id++;
 822                 if (rx_id == rxq->nb_rx_desc)
 823                         rx_id = 0;
 824
 825                 /* Prefetch next mbuf */
 826                 rte_prefetch0(sw_ring[rx_id].mbuf);
 827
 828                 /**
 829                  * When next RX descriptor is on a cache line boundary,
 830                  * prefetch the next 4 RX descriptors and next 8 pointers
 831                  * to mbufs.
 832                  */
 833                 if ((rx_id & 0x3) == 0) {
 834                         rte_prefetch0(&rx_ring[rx_id]);
 835                         rte_prefetch0(&sw_ring[rx_id]);
 836                 }
 837
 838                 rxm = rxe->mbuf;
 839                 rxe->mbuf = nmb;
 840                 dma_addr =
 841                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 842
 843                 /* Set data buffer address and data length of the mbuf */
 844                 rxdp->read.hdr_addr = 0;
 845                 rxdp->read.pkt_addr = dma_addr;
 846                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 847                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 848                 rxm->data_len = rx_packet_len;
 849                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 850
 851                 /**
 852                  * If this is the first buffer of the received packet, set the
 853                  * pointer to the first mbuf of the packet and initialize its
 854                  * context. Otherwise, update the total length and the number
 855                  * of segments of the current scattered packet, and update the
 856                  * pointer to the last mbuf of the current packet.
 857                  */
 858                 if (!first_seg) {
 859                         first_seg = rxm;
 860                         first_seg->nb_segs = 1;
 861                         first_seg->pkt_len = rx_packet_len;
 862                 } else {
 863                         first_seg->pkt_len =
 864                                 (uint16_t)(first_seg->pkt_len +
 865                                                 rx_packet_len);
 866                         first_seg->nb_segs++;
 867                         last_seg->next = rxm;
 868                 }
 869
 870                 /**
 871                  * If this is not the last buffer of the received packet,
 872                  * update the pointer to the last mbuf of the current scattered
 873                  * packet and continue to parse the RX ring.
 874                  */
 875                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 876                         last_seg = rxm;
 877                         continue;
 878                 }
 879
 880                 /**
 881                  * This is the last buffer of the received packet. If the CRC
 882                  * is not stripped by the hardware:
 883                  *  - Subtract the CRC length from the total packet length.
 884                  *  - If the last buffer only contains the whole CRC or a part
 885                  *  of it, free the mbuf associated to the last buffer. If part
 886                  *  of the CRC is also contained in the previous mbuf, subtract
 887                  *  the length of that CRC part from the data length of the
 888                  *  previous mbuf.
 889                  */
 890                 rxm->next = NULL;
 891                 if (unlikely(rxq->crc_len > 0)) {
 892                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
 893                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
 894                                 rte_pktmbuf_free_seg(rxm);
 895                                 first_seg->nb_segs--;
 896                                 last_seg->data_len =
 897                                         (uint16_t)(last_seg->data_len -
 898                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
 899                                 last_seg->next = NULL;
 900                         } else
 901                                 rxm->data_len = (uint16_t)(rx_packet_len -
 902                                                         RTE_ETHER_CRC_LEN);
 903                 }
 904
 905                 first_seg->port = rxq->port_id;
 906                 first_seg->ol_flags = 0;
 907                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 908                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 909                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 910                 first_seg->packet_type =
 911                         ptype_tbl[(uint8_t)((qword1 &
 912                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 913                 if (pkt_flags & PKT_RX_RSS_HASH)
 914                         first_seg->hash.rss =
 915                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 916                 if (pkt_flags & PKT_RX_FDIR)
 917                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 918
 919 #ifdef RTE_LIBRTE_IEEE1588
 920                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 921 #endif
 922                 first_seg->ol_flags |= pkt_flags;
 923
 924                 /* Prefetch data of first segment, if configured to do so. */
 925                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 926                         first_seg->data_off));
 927                 rx_pkts[nb_rx++] = first_seg;
 928                 first_seg = NULL;
 929         }
 930
 931         /* Record index of the next RX descriptor to probe. */
 932         rxq->rx_tail = rx_id;
 933         rxq->pkt_first_seg = first_seg;
 934         rxq->pkt_last_seg = last_seg;
 935
 936         /**
 937          * If the number of free RX descriptors is greater than the RX free
 938          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 939          * register. Update the RDT with the value of the last processed RX
 940          * descriptor minus 1, to guarantee that the RDT register is never
 941          * equal to the RDH register, which creates a "full" ring situtation
 942          * from the hardware point of view.
 943          */
 944         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 945         if (nb_hold > rxq->rx_free_thresh) {
 946                 rx_id = (uint16_t)(rx_id == 0 ?
 947                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 948                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 949                 nb_hold = 0;
 950         }
 951         rxq->nb_rx_hold = nb_hold;
 952
 953         return nb_rx;
 954 }
 955
 956 /* Check if the context descriptor is needed for TX offloading */
 957 static inline uint16_t
 958 i40e_calc_context_desc(uint64_t flags)
 959 {
 960         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 961                 PKT_TX_TCP_SEG |
 962                 PKT_TX_QINQ_PKT |
 963                 PKT_TX_TUNNEL_MASK;
 964
 965 #ifdef RTE_LIBRTE_IEEE1588
 966         mask |= PKT_TX_IEEE1588_TMST;
 967 #endif
 968
 969         return (flags & mask) ? 1 : 0;
 970 }
 971
 972 /* set i40e TSO context descriptor */
 973 static inline uint64_t
 974 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 975 {
 976         uint64_t ctx_desc = 0;
 977         uint32_t cd_cmd, hdr_len, cd_tso_len;
 978
 979         if (!tx_offload.l4_len) {
 980                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 981                 return ctx_desc;
 982         }
 983
 984         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
 985         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
 986                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
 987
 988         cd_cmd = I40E_TX_CTX_DESC_TSO;
 989         cd_tso_len = mbuf->pkt_len - hdr_len;
 990         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 991                 ((uint64_t)cd_tso_len <<
 992                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 993                 ((uint64_t)mbuf->tso_segsz <<
 994                  I40E_TXD_CTX_QW1_MSS_SHIFT);
 995
 996         return ctx_desc;
 997 }
 998
 999 uint16_t
1000 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1001 {
1002         struct i40e_tx_queue *txq;
1003         struct i40e_tx_entry *sw_ring;
1004         struct i40e_tx_entry *txe, *txn;
1005         volatile struct i40e_tx_desc *txd;
1006         volatile struct i40e_tx_desc *txr;
1007         struct rte_mbuf *tx_pkt;
1008         struct rte_mbuf *m_seg;
1009         uint32_t cd_tunneling_params;
1010         uint16_t tx_id;
1011         uint16_t nb_tx;
1012         uint32_t td_cmd;
1013         uint32_t td_offset;
1014         uint32_t td_tag;
1015         uint64_t ol_flags;
1016         uint16_t nb_used;
1017         uint16_t nb_ctx;
1018         uint16_t tx_last;
1019         uint16_t slen;
1020         uint64_t buf_dma_addr;
1021         union i40e_tx_offload tx_offload = {0};
1022
1023         txq = tx_queue;
1024         sw_ring = txq->sw_ring;
1025         txr = txq->tx_ring;
1026         tx_id = txq->tx_tail;
1027         txe = &sw_ring[tx_id];
1028
1029         /* Check if the descriptor ring needs to be cleaned. */
1030         if (txq->nb_tx_free < txq->tx_free_thresh)
1031                 i40e_xmit_cleanup(txq);
1032
1033         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1034                 td_cmd = 0;
1035                 td_tag = 0;
1036                 td_offset = 0;
1037
1038                 tx_pkt = *tx_pkts++;
1039                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1040
1041                 ol_flags = tx_pkt->ol_flags;
1042                 tx_offload.l2_len = tx_pkt->l2_len;
1043                 tx_offload.l3_len = tx_pkt->l3_len;
1044                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1045                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1046                 tx_offload.l4_len = tx_pkt->l4_len;
1047                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1048
1049                 /* Calculate the number of context descriptors needed. */
1050                 nb_ctx = i40e_calc_context_desc(ol_flags);
1051
1052                 /**
1053                  * The number of descriptors that must be allocated for
1054                  * a packet equals to the number of the segments of that
1055                  * packet plus 1 context descriptor if needed.
1056                  */
1057                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1058                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1059
1060                 /* Circular ring */
1061                 if (tx_last >= txq->nb_tx_desc)
1062                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1063
1064                 if (nb_used > txq->nb_tx_free) {
1065                         if (i40e_xmit_cleanup(txq) != 0) {
1066                                 if (nb_tx == 0)
1067                                         return 0;
1068                                 goto end_of_tx;
1069                         }
1070                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1071                                 while (nb_used > txq->nb_tx_free) {
1072                                         if (i40e_xmit_cleanup(txq) != 0) {
1073                                                 if (nb_tx == 0)
1074                                                         return 0;
1075                                                 goto end_of_tx;
1076                                         }
1077                                 }
1078                         }
1079                 }
1080
1081                 /* Descriptor based VLAN insertion */
1082                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1083                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1084                         td_tag = tx_pkt->vlan_tci;
1085                 }
1086
1087                 /* Always enable CRC offload insertion */
1088                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1089
1090                 /* Fill in tunneling parameters if necessary */
1091                 cd_tunneling_params = 0;
1092                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1093                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1094                                                     &cd_tunneling_params);
1095                 /* Enable checksum offloading */
1096                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1097                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1098                                                  &td_offset, tx_offload);
1099
1100                 if (nb_ctx) {
1101                         /* Setup TX context descriptor if required */
1102                         volatile struct i40e_tx_context_desc *ctx_txd =
1103                                 (volatile struct i40e_tx_context_desc *)\
1104                                                         &txr[tx_id];
1105                         uint16_t cd_l2tag2 = 0;
1106                         uint64_t cd_type_cmd_tso_mss =
1107                                 I40E_TX_DESC_DTYPE_CONTEXT;
1108
1109                         txn = &sw_ring[txe->next_id];
1110                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1111                         if (txe->mbuf != NULL) {
1112                                 rte_pktmbuf_free_seg(txe->mbuf);
1113                                 txe->mbuf = NULL;
1114                         }
1115
1116                         /* TSO enabled means no timestamp */
1117                         if (ol_flags & PKT_TX_TCP_SEG)
1118                                 cd_type_cmd_tso_mss |=
1119                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1120                         else {
1121 #ifdef RTE_LIBRTE_IEEE1588
1122                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1123                                         cd_type_cmd_tso_mss |=
1124                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1125                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1126 #endif
1127                         }
1128
1129                         ctx_txd->tunneling_params =
1130                                 rte_cpu_to_le_32(cd_tunneling_params);
1131                         if (ol_flags & PKT_TX_QINQ_PKT) {
1132                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1133                                 cd_type_cmd_tso_mss |=
1134                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1135                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1136                         }
1137                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1138                         ctx_txd->type_cmd_tso_mss =
1139                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1140
1141                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1142                                 "tunneling_params: %#x;\n"
1143                                 "l2tag2: %#hx;\n"
1144                                 "rsvd: %#hx;\n"
1145                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1146                                 tx_pkt, tx_id,
1147                                 ctx_txd->tunneling_params,
1148                                 ctx_txd->l2tag2,
1149                                 ctx_txd->rsvd,
1150                                 ctx_txd->type_cmd_tso_mss);
1151
1152                         txe->last_id = tx_last;
1153                         tx_id = txe->next_id;
1154                         txe = txn;
1155                 }
1156
1157                 m_seg = tx_pkt;
1158                 do {
1159                         txd = &txr[tx_id];
1160                         txn = &sw_ring[txe->next_id];
1161
1162                         if (txe->mbuf)
1163                                 rte_pktmbuf_free_seg(txe->mbuf);
1164                         txe->mbuf = m_seg;
1165
1166                         /* Setup TX Descriptor */
1167                         slen = m_seg->data_len;
1168                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1169
1170                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1171                                 "buf_dma_addr: %#"PRIx64";\n"
1172                                 "td_cmd: %#x;\n"
1173                                 "td_offset: %#x;\n"
1174                                 "td_len: %u;\n"
1175                                 "td_tag: %#x;\n",
1176                                 tx_pkt, tx_id, buf_dma_addr,
1177                                 td_cmd, td_offset, slen, td_tag);
1178
1179                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1180                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1181                                                 td_offset, slen, td_tag);
1182                         txe->last_id = tx_last;
1183                         tx_id = txe->next_id;
1184                         txe = txn;
1185                         m_seg = m_seg->next;
1186                 } while (m_seg != NULL);
1187
1188                 /* The last packet data descriptor needs End Of Packet (EOP) */
1189                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1190                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1191                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1192
1193                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1194                         PMD_TX_FREE_LOG(DEBUG,
1195                                         "Setting RS bit on TXD id="
1196                                         "%4u (port=%d queue=%d)",
1197                                         tx_last, txq->port_id, txq->queue_id);
1198
1199                         td_cmd |= I40E_TX_DESC_CMD_RS;
1200
1201                         /* Update txq RS bit counters */
1202                         txq->nb_tx_used = 0;
1203                 }
1204
1205                 txd->cmd_type_offset_bsz |=
1206                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1207                                         I40E_TXD_QW1_CMD_SHIFT);
1208         }
1209
1210 end_of_tx:
1211         rte_wmb();
1212
1213         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1214                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1215                    (unsigned) tx_id, (unsigned) nb_tx);
1216
1217         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1218         txq->tx_tail = tx_id;
1219
1220         return nb_tx;
1221 }
1222
1223 static __rte_always_inline int
1224 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1225 {
1226         struct i40e_tx_entry *txep;
1227         uint16_t i;
1228
1229         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1230                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1231                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1232                 return 0;
1233
1234         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1235
1236         for (i = 0; i < txq->tx_rs_thresh; i++)
1237                 rte_prefetch0((txep + i)->mbuf);
1238
1239         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1240                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1241                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1242                         txep->mbuf = NULL;
1243                 }
1244         } else {
1245                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1246                         rte_pktmbuf_free_seg(txep->mbuf);
1247                         txep->mbuf = NULL;
1248                 }
1249         }
1250
1251         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1252         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1253         if (txq->tx_next_dd >= txq->nb_tx_desc)
1254                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1255
1256         return txq->tx_rs_thresh;
1257 }
1258
1259 /* Populate 4 descriptors with data from 4 mbufs */
1260 static inline void
1261 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1262 {
1263         uint64_t dma_addr;
1264         uint32_t i;
1265
1266         for (i = 0; i < 4; i++, txdp++, pkts++) {
1267                 dma_addr = rte_mbuf_data_iova(*pkts);
1268                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1269                 txdp->cmd_type_offset_bsz =
1270                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1271                                         (*pkts)->data_len, 0);
1272         }
1273 }
1274
1275 /* Populate 1 descriptor with data from 1 mbuf */
1276 static inline void
1277 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1278 {
1279         uint64_t dma_addr;
1280
1281         dma_addr = rte_mbuf_data_iova(*pkts);
1282         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1283         txdp->cmd_type_offset_bsz =
1284                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1285                                 (*pkts)->data_len, 0);
1286 }
1287
1288 /* Fill hardware descriptor ring with mbuf data */
1289 static inline void
1290 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1291                      struct rte_mbuf **pkts,
1292                      uint16_t nb_pkts)
1293 {
1294         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1295         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1296         const int N_PER_LOOP = 4;
1297         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1298         int mainpart, leftover;
1299         int i, j;
1300
1301         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1302         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1303         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1304                 for (j = 0; j < N_PER_LOOP; ++j) {
1305                         (txep + i + j)->mbuf = *(pkts + i + j);
1306                 }
1307                 tx4(txdp + i, pkts + i);
1308         }
1309         if (unlikely(leftover > 0)) {
1310                 for (i = 0; i < leftover; ++i) {
1311                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1312                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1313                 }
1314         }
1315 }
1316
1317 static inline uint16_t
1318 tx_xmit_pkts(struct i40e_tx_queue *txq,
1319              struct rte_mbuf **tx_pkts,
1320              uint16_t nb_pkts)
1321 {
1322         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1323         uint16_t n = 0;
1324
1325         /**
1326          * Begin scanning the H/W ring for done descriptors when the number
1327          * of available descriptors drops below tx_free_thresh. For each done
1328          * descriptor, free the associated buffer.
1329          */
1330         if (txq->nb_tx_free < txq->tx_free_thresh)
1331                 i40e_tx_free_bufs(txq);
1332
1333         /* Use available descriptor only */
1334         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1335         if (unlikely(!nb_pkts))
1336                 return 0;
1337
1338         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1339         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1340                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1341                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1342                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1343                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1344                                                 I40E_TXD_QW1_CMD_SHIFT);
1345                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1346                 txq->tx_tail = 0;
1347         }
1348
1349         /* Fill hardware descriptor ring with mbuf data */
1350         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1351         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1352
1353         /* Determin if RS bit needs to be set */
1354         if (txq->tx_tail > txq->tx_next_rs) {
1355                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1356                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1357                                                 I40E_TXD_QW1_CMD_SHIFT);
1358                 txq->tx_next_rs =
1359                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1360                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1361                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1362         }
1363
1364         if (txq->tx_tail >= txq->nb_tx_desc)
1365                 txq->tx_tail = 0;
1366
1367         /* Update the tx tail register */
1368         rte_wmb();
1369         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1370
1371         return nb_pkts;
1372 }
1373
1374 static uint16_t
1375 i40e_xmit_pkts_simple(void *tx_queue,
1376                       struct rte_mbuf **tx_pkts,
1377                       uint16_t nb_pkts)
1378 {
1379         uint16_t nb_tx = 0;
1380
1381         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1382                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1383                                                 tx_pkts, nb_pkts);
1384
1385         while (nb_pkts) {
1386                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1387                                                 I40E_TX_MAX_BURST);
1388
1389                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1390                                                 &tx_pkts[nb_tx], num);
1391                 nb_tx = (uint16_t)(nb_tx + ret);
1392                 nb_pkts = (uint16_t)(nb_pkts - ret);
1393                 if (ret < num)
1394                         break;
1395         }
1396
1397         return nb_tx;
1398 }
1399
1400 static uint16_t
1401 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1402                    uint16_t nb_pkts)
1403 {
1404         uint16_t nb_tx = 0;
1405         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1406
1407         while (nb_pkts) {
1408                 uint16_t ret, num;
1409
1410                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1411                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1412                                                 num);
1413                 nb_tx += ret;
1414                 nb_pkts -= ret;
1415                 if (ret < num)
1416                         break;
1417         }
1418
1419         return nb_tx;
1420 }
1421
1422 /*********************************************************************
1423  *
1424  *  TX prep functions
1425  *
1426  **********************************************************************/
1427 uint16_t
1428 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1429                 uint16_t nb_pkts)
1430 {
1431         int i, ret;
1432         uint64_t ol_flags;
1433         struct rte_mbuf *m;
1434
1435         for (i = 0; i < nb_pkts; i++) {
1436                 m = tx_pkts[i];
1437                 ol_flags = m->ol_flags;
1438
1439                 /* Check for m->nb_segs to not exceed the limits. */
1440                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1441                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1442                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1443                                 rte_errno = EINVAL;
1444                                 return i;
1445                         }
1446                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1447                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1448                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1449                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1450                         /* MSS outside the range (256B - 9674B) are considered
1451                          * malicious
1452                          */
1453                         rte_errno = EINVAL;
1454                         return i;
1455                 }
1456
1457                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1458                         rte_errno = ENOTSUP;
1459                         return i;
1460                 }
1461
1462                 /* check the size of packet */
1463                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1464                         rte_errno = EINVAL;
1465                         return i;
1466                 }
1467
1468 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1469                 ret = rte_validate_tx_offload(m);
1470                 if (ret != 0) {
1471                         rte_errno = -ret;
1472                         return i;
1473                 }
1474 #endif
1475                 ret = rte_net_intel_cksum_prepare(m);
1476                 if (ret != 0) {
1477                         rte_errno = -ret;
1478                         return i;
1479                 }
1480         }
1481         return i;
1482 }
1483
1484 /*
1485  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1486  * application used, which assume having sequential ones. But from driver's
1487  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1488  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1489  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1490  * use queue_idx from 0 to 95 to access queues, while real queue would be
1491  * different. This function will do a queue mapping to find VSI the queue
1492  * belongs to.
1493  */
1494 static struct i40e_vsi*
1495 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1496 {
1497         /* the queue in MAIN VSI range */
1498         if (queue_idx < pf->main_vsi->nb_qps)
1499                 return pf->main_vsi;
1500
1501         queue_idx -= pf->main_vsi->nb_qps;
1502
1503         /* queue_idx is greater than VMDQ VSIs range */
1504         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1505                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1506                 return NULL;
1507         }
1508
1509         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1510 }
1511
1512 static uint16_t
1513 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1514 {
1515         /* the queue in MAIN VSI range */
1516         if (queue_idx < pf->main_vsi->nb_qps)
1517                 return queue_idx;
1518
1519         /* It's VMDQ queues */
1520         queue_idx -= pf->main_vsi->nb_qps;
1521
1522         if (pf->nb_cfg_vmdq_vsi)
1523                 return queue_idx % pf->vmdq_nb_qps;
1524         else {
1525                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1526                 return (uint16_t)(-1);
1527         }
1528 }
1529
1530 int
1531 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1532 {
1533         struct i40e_rx_queue *rxq;
1534         int err;
1535         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536
1537         PMD_INIT_FUNC_TRACE();
1538
1539         rxq = dev->data->rx_queues[rx_queue_id];
1540
1541         err = i40e_alloc_rx_queue_mbufs(rxq);
1542         if (err) {
1543                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1544                 return err;
1545         }
1546
1547         rte_wmb();
1548
1549         /* Init the RX tail regieter. */
1550         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1551
1552         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1553         if (err) {
1554                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1555                             rx_queue_id);
1556
1557                 i40e_rx_queue_release_mbufs(rxq);
1558                 i40e_reset_rx_queue(rxq);
1559                 return err;
1560         }
1561         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1562
1563         return 0;
1564 }
1565
1566 int
1567 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1568 {
1569         struct i40e_rx_queue *rxq;
1570         int err;
1571         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1572
1573         rxq = dev->data->rx_queues[rx_queue_id];
1574
1575         /*
1576          * rx_queue_id is queue id application refers to, while
1577          * rxq->reg_idx is the real queue index.
1578          */
1579         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1580         if (err) {
1581                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1582                             rx_queue_id);
1583                 return err;
1584         }
1585         i40e_rx_queue_release_mbufs(rxq);
1586         i40e_reset_rx_queue(rxq);
1587         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1588
1589         return 0;
1590 }
1591
1592 int
1593 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1594 {
1595         int err;
1596         struct i40e_tx_queue *txq;
1597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598
1599         PMD_INIT_FUNC_TRACE();
1600
1601         txq = dev->data->tx_queues[tx_queue_id];
1602
1603         /*
1604          * tx_queue_id is queue id application refers to, while
1605          * rxq->reg_idx is the real queue index.
1606          */
1607         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1608         if (err) {
1609                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1610                             tx_queue_id);
1611                 return err;
1612         }
1613         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1614
1615         return 0;
1616 }
1617
1618 int
1619 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1620 {
1621         struct i40e_tx_queue *txq;
1622         int err;
1623         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624
1625         txq = dev->data->tx_queues[tx_queue_id];
1626
1627         /*
1628          * tx_queue_id is queue id application refers to, while
1629          * txq->reg_idx is the real queue index.
1630          */
1631         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1632         if (err) {
1633                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1634                             tx_queue_id);
1635                 return err;
1636         }
1637
1638         i40e_tx_queue_release_mbufs(txq);
1639         i40e_reset_tx_queue(txq);
1640         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1641
1642         return 0;
1643 }
1644
1645 const uint32_t *
1646 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1647 {
1648         static const uint32_t ptypes[] = {
1649                 /* refers to i40e_rxd_pkt_type_mapping() */
1650                 RTE_PTYPE_L2_ETHER,
1651                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1652                 RTE_PTYPE_L2_ETHER_LLDP,
1653                 RTE_PTYPE_L2_ETHER_ARP,
1654                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1655                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1656                 RTE_PTYPE_L4_FRAG,
1657                 RTE_PTYPE_L4_ICMP,
1658                 RTE_PTYPE_L4_NONFRAG,
1659                 RTE_PTYPE_L4_SCTP,
1660                 RTE_PTYPE_L4_TCP,
1661                 RTE_PTYPE_L4_UDP,
1662                 RTE_PTYPE_TUNNEL_GRENAT,
1663                 RTE_PTYPE_TUNNEL_IP,
1664                 RTE_PTYPE_INNER_L2_ETHER,
1665                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1666                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1667                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1668                 RTE_PTYPE_INNER_L4_FRAG,
1669                 RTE_PTYPE_INNER_L4_ICMP,
1670                 RTE_PTYPE_INNER_L4_NONFRAG,
1671                 RTE_PTYPE_INNER_L4_SCTP,
1672                 RTE_PTYPE_INNER_L4_TCP,
1673                 RTE_PTYPE_INNER_L4_UDP,
1674                 RTE_PTYPE_UNKNOWN
1675         };
1676
1677         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1678 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1679             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1680 #endif
1681             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1682             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1683             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1684             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1685             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1686                 return ptypes;
1687         return NULL;
1688 }
1689
1690 static int
1691 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1692 {
1693         uint16_t i;
1694
1695         for (i = 0; i < num; i++) {
1696                 if (i != idx && queues[i])
1697                         return 0;
1698         }
1699
1700         return 1;
1701 }
1702
1703 static int
1704 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1705                                 struct i40e_rx_queue *rxq)
1706 {
1707         struct i40e_adapter *ad =
1708                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1709         int use_def_burst_func =
1710                 check_rx_burst_bulk_alloc_preconditions(rxq);
1711         uint16_t buf_size =
1712                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1713                            RTE_PKTMBUF_HEADROOM);
1714         int use_scattered_rx =
1715                 (rxq->max_pkt_len > buf_size);
1716
1717         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1718                 PMD_DRV_LOG(ERR,
1719                             "Failed to do RX queue initialization");
1720                 return -EINVAL;
1721         }
1722
1723         if (i40e_dev_first_queue(rxq->queue_id,
1724                                  dev->data->rx_queues,
1725                                  dev->data->nb_rx_queues)) {
1726                 /**
1727                  * If it is the first queue to setup,
1728                  * set all flags to default and call
1729                  * i40e_set_rx_function.
1730                  */
1731                 ad->rx_bulk_alloc_allowed = true;
1732                 ad->rx_vec_allowed = true;
1733                 dev->data->scattered_rx = use_scattered_rx;
1734                 if (use_def_burst_func)
1735                         ad->rx_bulk_alloc_allowed = false;
1736                 i40e_set_rx_function(dev);
1737                 return 0;
1738         } else if (ad->rx_vec_allowed && !rte_is_power_of_2(rxq->nb_rx_desc)) {
1739                 PMD_DRV_LOG(ERR, "Vector mode is allowed, but descriptor"
1740                             " number %d of queue %d isn't power of 2",
1741                             rxq->nb_rx_desc, rxq->queue_id);
1742                 return -EINVAL;
1743         }
1744
1745         /* check bulk alloc conflict */
1746         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1747                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1748                 return -EINVAL;
1749         }
1750         /* check scatterred conflict */
1751         if (!dev->data->scattered_rx && use_scattered_rx) {
1752                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1753                 return -EINVAL;
1754         }
1755         /* check vector conflict */
1756         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1757                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1758                 return -EINVAL;
1759         }
1760
1761         return 0;
1762 }
1763
1764 int
1765 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1766                         uint16_t queue_idx,
1767                         uint16_t nb_desc,
1768                         unsigned int socket_id,
1769                         const struct rte_eth_rxconf *rx_conf,
1770                         struct rte_mempool *mp)
1771 {
1772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773         struct i40e_adapter *ad =
1774                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1775         struct i40e_vsi *vsi;
1776         struct i40e_pf *pf = NULL;
1777         struct i40e_vf *vf = NULL;
1778         struct i40e_rx_queue *rxq;
1779         const struct rte_memzone *rz;
1780         uint32_t ring_size;
1781         uint16_t len, i;
1782         uint16_t reg_idx, base, bsf, tc_mapping;
1783         int q_offset, use_def_burst_func = 1;
1784         uint64_t offloads;
1785
1786         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1787
1788         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1789                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1790                 vsi = &vf->vsi;
1791                 if (!vsi)
1792                         return -EINVAL;
1793                 reg_idx = queue_idx;
1794         } else {
1795                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1796                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1797                 if (!vsi)
1798                         return -EINVAL;
1799                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1800                 if (q_offset < 0)
1801                         return -EINVAL;
1802                 reg_idx = vsi->base_queue + q_offset;
1803         }
1804
1805         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1806             (nb_desc > I40E_MAX_RING_DESC) ||
1807             (nb_desc < I40E_MIN_RING_DESC)) {
1808                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1809                             "invalid", nb_desc);
1810                 return -EINVAL;
1811         }
1812
1813         /* Free memory if needed */
1814         if (dev->data->rx_queues[queue_idx]) {
1815                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1816                 dev->data->rx_queues[queue_idx] = NULL;
1817         }
1818
1819         /* Allocate the rx queue data structure */
1820         rxq = rte_zmalloc_socket("i40e rx queue",
1821                                  sizeof(struct i40e_rx_queue),
1822                                  RTE_CACHE_LINE_SIZE,
1823                                  socket_id);
1824         if (!rxq) {
1825                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1826                             "rx queue data structure");
1827                 return -ENOMEM;
1828         }
1829         rxq->mp = mp;
1830         rxq->nb_rx_desc = nb_desc;
1831         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1832         rxq->queue_id = queue_idx;
1833         rxq->reg_idx = reg_idx;
1834         rxq->port_id = dev->data->port_id;
1835         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1836                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1837         else
1838                 rxq->crc_len = 0;
1839         rxq->drop_en = rx_conf->rx_drop_en;
1840         rxq->vsi = vsi;
1841         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1842         rxq->offloads = offloads;
1843
1844         /* Allocate the maximun number of RX ring hardware descriptor. */
1845         len = I40E_MAX_RING_DESC;
1846
1847         /**
1848          * Allocating a little more memory because vectorized/bulk_alloc Rx
1849          * functions doesn't check boundaries each time.
1850          */
1851         len += RTE_PMD_I40E_RX_MAX_BURST;
1852
1853         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1854                               I40E_DMA_MEM_ALIGN);
1855
1856         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1857                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1858         if (!rz) {
1859                 i40e_dev_rx_queue_release(rxq);
1860                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1861                 return -ENOMEM;
1862         }
1863
1864         /* Zero all the descriptors in the ring. */
1865         memset(rz->addr, 0, ring_size);
1866
1867         rxq->rx_ring_phys_addr = rz->iova;
1868         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1869
1870         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1871
1872         /* Allocate the software ring. */
1873         rxq->sw_ring =
1874                 rte_zmalloc_socket("i40e rx sw ring",
1875                                    sizeof(struct i40e_rx_entry) * len,
1876                                    RTE_CACHE_LINE_SIZE,
1877                                    socket_id);
1878         if (!rxq->sw_ring) {
1879                 i40e_dev_rx_queue_release(rxq);
1880                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1881                 return -ENOMEM;
1882         }
1883
1884         i40e_reset_rx_queue(rxq);
1885         rxq->q_set = TRUE;
1886
1887         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1888                 if (!(vsi->enabled_tc & (1 << i)))
1889                         continue;
1890                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1891                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1892                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1893                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1894                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1895
1896                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1897                         rxq->dcb_tc = i;
1898         }
1899
1900         if (dev->data->dev_started) {
1901                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1902                         i40e_dev_rx_queue_release(rxq);
1903                         return -EINVAL;
1904                 }
1905         } else {
1906                 use_def_burst_func =
1907                         check_rx_burst_bulk_alloc_preconditions(rxq);
1908                 if (!use_def_burst_func) {
1909 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1910                         PMD_INIT_LOG(DEBUG,
1911                           "Rx Burst Bulk Alloc Preconditions are "
1912                           "satisfied. Rx Burst Bulk Alloc function will be "
1913                           "used on port=%d, queue=%d.",
1914                           rxq->port_id, rxq->queue_id);
1915 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1916                 } else {
1917                         PMD_INIT_LOG(DEBUG,
1918                           "Rx Burst Bulk Alloc Preconditions are "
1919                           "not satisfied, Scattered Rx is requested, "
1920                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1921                           "not enabled on port=%d, queue=%d.",
1922                           rxq->port_id, rxq->queue_id);
1923                         ad->rx_bulk_alloc_allowed = false;
1924                 }
1925         }
1926
1927         dev->data->rx_queues[queue_idx] = rxq;
1928         return 0;
1929 }
1930
1931 void
1932 i40e_dev_rx_queue_release(void *rxq)
1933 {
1934         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1935
1936         if (!q) {
1937                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1938                 return;
1939         }
1940
1941         i40e_rx_queue_release_mbufs(q);
1942         rte_free(q->sw_ring);
1943         rte_free(q);
1944 }
1945
1946 uint32_t
1947 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1948 {
1949 #define I40E_RXQ_SCAN_INTERVAL 4
1950         volatile union i40e_rx_desc *rxdp;
1951         struct i40e_rx_queue *rxq;
1952         uint16_t desc = 0;
1953
1954         rxq = dev->data->rx_queues[rx_queue_id];
1955         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1956         while ((desc < rxq->nb_rx_desc) &&
1957                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1958                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1959                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1960                 /**
1961                  * Check the DD bit of a rx descriptor of each 4 in a group,
1962                  * to avoid checking too frequently and downgrading performance
1963                  * too much.
1964                  */
1965                 desc += I40E_RXQ_SCAN_INTERVAL;
1966                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1967                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1968                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1969                                         desc - rxq->nb_rx_desc]);
1970         }
1971
1972         return desc;
1973 }
1974
1975 int
1976 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1977 {
1978         volatile union i40e_rx_desc *rxdp;
1979         struct i40e_rx_queue *rxq = rx_queue;
1980         uint16_t desc;
1981         int ret;
1982
1983         if (unlikely(offset >= rxq->nb_rx_desc)) {
1984                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1985                 return 0;
1986         }
1987
1988         desc = rxq->rx_tail + offset;
1989         if (desc >= rxq->nb_rx_desc)
1990                 desc -= rxq->nb_rx_desc;
1991
1992         rxdp = &(rxq->rx_ring[desc]);
1993
1994         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1995                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1996                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1997
1998         return ret;
1999 }
2000
2001 int
2002 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2003 {
2004         struct i40e_rx_queue *rxq = rx_queue;
2005         volatile uint64_t *status;
2006         uint64_t mask;
2007         uint32_t desc;
2008
2009         if (unlikely(offset >= rxq->nb_rx_desc))
2010                 return -EINVAL;
2011
2012         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2013                 return RTE_ETH_RX_DESC_UNAVAIL;
2014
2015         desc = rxq->rx_tail + offset;
2016         if (desc >= rxq->nb_rx_desc)
2017                 desc -= rxq->nb_rx_desc;
2018
2019         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2020         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2021                 << I40E_RXD_QW1_STATUS_SHIFT);
2022         if (*status & mask)
2023                 return RTE_ETH_RX_DESC_DONE;
2024
2025         return RTE_ETH_RX_DESC_AVAIL;
2026 }
2027
2028 int
2029 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2030 {
2031         struct i40e_tx_queue *txq = tx_queue;
2032         volatile uint64_t *status;
2033         uint64_t mask, expect;
2034         uint32_t desc;
2035
2036         if (unlikely(offset >= txq->nb_tx_desc))
2037                 return -EINVAL;
2038
2039         desc = txq->tx_tail + offset;
2040         /* go to next desc that has the RS bit */
2041         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2042                 txq->tx_rs_thresh;
2043         if (desc >= txq->nb_tx_desc) {
2044                 desc -= txq->nb_tx_desc;
2045                 if (desc >= txq->nb_tx_desc)
2046                         desc -= txq->nb_tx_desc;
2047         }
2048
2049         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2050         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2051         expect = rte_cpu_to_le_64(
2052                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2053         if ((*status & mask) == expect)
2054                 return RTE_ETH_TX_DESC_DONE;
2055
2056         return RTE_ETH_TX_DESC_FULL;
2057 }
2058
2059 static int
2060 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2061                                 struct i40e_tx_queue *txq)
2062 {
2063         struct i40e_adapter *ad =
2064                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2065
2066         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2067                 PMD_DRV_LOG(ERR,
2068                             "Failed to do TX queue initialization");
2069                 return -EINVAL;
2070         }
2071
2072         if (i40e_dev_first_queue(txq->queue_id,
2073                                  dev->data->tx_queues,
2074                                  dev->data->nb_tx_queues)) {
2075                 /**
2076                  * If it is the first queue to setup,
2077                  * set all flags and call
2078                  * i40e_set_tx_function.
2079                  */
2080                 i40e_set_tx_function_flag(dev, txq);
2081                 i40e_set_tx_function(dev);
2082                 return 0;
2083         }
2084
2085         /* check vector conflict */
2086         if (ad->tx_vec_allowed) {
2087                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2088                     i40e_txq_vec_setup(txq)) {
2089                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2090                         return -EINVAL;
2091                 }
2092         }
2093         /* check simple tx conflict */
2094         if (ad->tx_simple_allowed) {
2095                 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2096                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2097                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2098                         return -EINVAL;
2099                 }
2100         }
2101
2102         return 0;
2103 }
2104
2105 int
2106 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2107                         uint16_t queue_idx,
2108                         uint16_t nb_desc,
2109                         unsigned int socket_id,
2110                         const struct rte_eth_txconf *tx_conf)
2111 {
2112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113         struct i40e_vsi *vsi;
2114         struct i40e_pf *pf = NULL;
2115         struct i40e_vf *vf = NULL;
2116         struct i40e_tx_queue *txq;
2117         const struct rte_memzone *tz;
2118         uint32_t ring_size;
2119         uint16_t tx_rs_thresh, tx_free_thresh;
2120         uint16_t reg_idx, i, base, bsf, tc_mapping;
2121         int q_offset;
2122         uint64_t offloads;
2123
2124         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2125
2126         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2127                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2128                 vsi = &vf->vsi;
2129                 if (!vsi)
2130                         return -EINVAL;
2131                 reg_idx = queue_idx;
2132         } else {
2133                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2134                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2135                 if (!vsi)
2136                         return -EINVAL;
2137                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2138                 if (q_offset < 0)
2139                         return -EINVAL;
2140                 reg_idx = vsi->base_queue + q_offset;
2141         }
2142
2143         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2144             (nb_desc > I40E_MAX_RING_DESC) ||
2145             (nb_desc < I40E_MIN_RING_DESC)) {
2146                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2147                             "invalid", nb_desc);
2148                 return -EINVAL;
2149         }
2150
2151         /**
2152          * The following two parameters control the setting of the RS bit on
2153          * transmit descriptors. TX descriptors will have their RS bit set
2154          * after txq->tx_rs_thresh descriptors have been used. The TX
2155          * descriptor ring will be cleaned after txq->tx_free_thresh
2156          * descriptors are used or if the number of descriptors required to
2157          * transmit a packet is greater than the number of free TX descriptors.
2158          *
2159          * The following constraints must be satisfied:
2160          *  - tx_rs_thresh must be greater than 0.
2161          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2162          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2163          *  - tx_rs_thresh must be a divisor of the ring size.
2164          *  - tx_free_thresh must be greater than 0.
2165          *  - tx_free_thresh must be less than the size of the ring minus 3.
2166          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
2167          *
2168          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2169          * race condition, hence the maximum threshold constraints. When set
2170          * to zero use default values.
2171          */
2172         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2173                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2174         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
2175         tx_rs_thresh = (DEFAULT_TX_RS_THRESH + tx_free_thresh > nb_desc) ?
2176                 nb_desc - tx_free_thresh : DEFAULT_TX_RS_THRESH;
2177         if (tx_conf->tx_rs_thresh > 0)
2178                 tx_rs_thresh = tx_conf->tx_rs_thresh;
2179         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
2180                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
2181                                 "exceed nb_desc. (tx_rs_thresh=%u "
2182                                 "tx_free_thresh=%u nb_desc=%u port=%d queue=%d)",
2183                                 (unsigned int)tx_rs_thresh,
2184                                 (unsigned int)tx_free_thresh,
2185                                 (unsigned int)nb_desc,
2186                                 (int)dev->data->port_id,
2187                                 (int)queue_idx);
2188                 return I40E_ERR_PARAM;
2189         }
2190         if (tx_rs_thresh >= (nb_desc - 2)) {
2191                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2192                              "number of TX descriptors minus 2. "
2193                              "(tx_rs_thresh=%u port=%d queue=%d)",
2194                              (unsigned int)tx_rs_thresh,
2195                              (int)dev->data->port_id,
2196                              (int)queue_idx);
2197                 return I40E_ERR_PARAM;
2198         }
2199         if (tx_free_thresh >= (nb_desc - 3)) {
2200                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2201                              "number of TX descriptors minus 3. "
2202                              "(tx_free_thresh=%u port=%d queue=%d)",
2203                              (unsigned int)tx_free_thresh,
2204                              (int)dev->data->port_id,
2205                              (int)queue_idx);
2206                 return I40E_ERR_PARAM;
2207         }
2208         if (tx_rs_thresh > tx_free_thresh) {
2209                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2210                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2211                              " tx_rs_thresh=%u port=%d queue=%d)",
2212                              (unsigned int)tx_free_thresh,
2213                              (unsigned int)tx_rs_thresh,
2214                              (int)dev->data->port_id,
2215                              (int)queue_idx);
2216                 return I40E_ERR_PARAM;
2217         }
2218         if ((nb_desc % tx_rs_thresh) != 0) {
2219                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2220                              "number of TX descriptors. (tx_rs_thresh=%u"
2221                              " port=%d queue=%d)",
2222                              (unsigned int)tx_rs_thresh,
2223                              (int)dev->data->port_id,
2224                              (int)queue_idx);
2225                 return I40E_ERR_PARAM;
2226         }
2227         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2228                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2229                              "tx_rs_thresh is greater than 1. "
2230                              "(tx_rs_thresh=%u port=%d queue=%d)",
2231                              (unsigned int)tx_rs_thresh,
2232                              (int)dev->data->port_id,
2233                              (int)queue_idx);
2234                 return I40E_ERR_PARAM;
2235         }
2236
2237         /* Free memory if needed. */
2238         if (dev->data->tx_queues[queue_idx]) {
2239                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2240                 dev->data->tx_queues[queue_idx] = NULL;
2241         }
2242
2243         /* Allocate the TX queue data structure. */
2244         txq = rte_zmalloc_socket("i40e tx queue",
2245                                   sizeof(struct i40e_tx_queue),
2246                                   RTE_CACHE_LINE_SIZE,
2247                                   socket_id);
2248         if (!txq) {
2249                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2250                             "tx queue structure");
2251                 return -ENOMEM;
2252         }
2253
2254         /* Allocate TX hardware ring descriptors. */
2255         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2256         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2257         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2258                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2259         if (!tz) {
2260                 i40e_dev_tx_queue_release(txq);
2261                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2262                 return -ENOMEM;
2263         }
2264
2265         txq->nb_tx_desc = nb_desc;
2266         txq->tx_rs_thresh = tx_rs_thresh;
2267         txq->tx_free_thresh = tx_free_thresh;
2268         txq->pthresh = tx_conf->tx_thresh.pthresh;
2269         txq->hthresh = tx_conf->tx_thresh.hthresh;
2270         txq->wthresh = tx_conf->tx_thresh.wthresh;
2271         txq->queue_id = queue_idx;
2272         txq->reg_idx = reg_idx;
2273         txq->port_id = dev->data->port_id;
2274         txq->offloads = offloads;
2275         txq->vsi = vsi;
2276         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2277
2278         txq->tx_ring_phys_addr = tz->iova;
2279         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2280
2281         /* Allocate software ring */
2282         txq->sw_ring =
2283                 rte_zmalloc_socket("i40e tx sw ring",
2284                                    sizeof(struct i40e_tx_entry) * nb_desc,
2285                                    RTE_CACHE_LINE_SIZE,
2286                                    socket_id);
2287         if (!txq->sw_ring) {
2288                 i40e_dev_tx_queue_release(txq);
2289                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2290                 return -ENOMEM;
2291         }
2292
2293         i40e_reset_tx_queue(txq);
2294         txq->q_set = TRUE;
2295
2296         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2297                 if (!(vsi->enabled_tc & (1 << i)))
2298                         continue;
2299                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2300                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2301                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2302                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2303                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2304
2305                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2306                         txq->dcb_tc = i;
2307         }
2308
2309         if (dev->data->dev_started) {
2310                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2311                         i40e_dev_tx_queue_release(txq);
2312                         return -EINVAL;
2313                 }
2314         } else {
2315                 /**
2316                  * Use a simple TX queue without offloads or
2317                  * multi segs if possible
2318                  */
2319                 i40e_set_tx_function_flag(dev, txq);
2320         }
2321         dev->data->tx_queues[queue_idx] = txq;
2322
2323         return 0;
2324 }
2325
2326 void
2327 i40e_dev_tx_queue_release(void *txq)
2328 {
2329         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2330
2331         if (!q) {
2332                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2333                 return;
2334         }
2335
2336         i40e_tx_queue_release_mbufs(q);
2337         rte_free(q->sw_ring);
2338         rte_free(q);
2339 }
2340
2341 const struct rte_memzone *
2342 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2343 {
2344         const struct rte_memzone *mz;
2345
2346         mz = rte_memzone_lookup(name);
2347         if (mz)
2348                 return mz;
2349
2350         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2351                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2352         return mz;
2353 }
2354
2355 void
2356 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2357 {
2358         uint16_t i;
2359
2360         /* SSE Vector driver has a different way of releasing mbufs. */
2361         if (rxq->rx_using_sse) {
2362                 i40e_rx_queue_release_mbufs_vec(rxq);
2363                 return;
2364         }
2365
2366         if (!rxq->sw_ring) {
2367                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2368                 return;
2369         }
2370
2371         for (i = 0; i < rxq->nb_rx_desc; i++) {
2372                 if (rxq->sw_ring[i].mbuf) {
2373                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2374                         rxq->sw_ring[i].mbuf = NULL;
2375                 }
2376         }
2377 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2378         if (rxq->rx_nb_avail == 0)
2379                 return;
2380         for (i = 0; i < rxq->rx_nb_avail; i++) {
2381                 struct rte_mbuf *mbuf;
2382
2383                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2384                 rte_pktmbuf_free_seg(mbuf);
2385         }
2386         rxq->rx_nb_avail = 0;
2387 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2388 }
2389
2390 void
2391 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2392 {
2393         unsigned i;
2394         uint16_t len;
2395
2396         if (!rxq) {
2397                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2398                 return;
2399         }
2400
2401 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2402         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2403                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2404         else
2405 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2406                 len = rxq->nb_rx_desc;
2407
2408         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2409                 ((volatile char *)rxq->rx_ring)[i] = 0;
2410
2411         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2412         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2413                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2414
2415 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2416         rxq->rx_nb_avail = 0;
2417         rxq->rx_next_avail = 0;
2418         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2419 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2420         rxq->rx_tail = 0;
2421         rxq->nb_rx_hold = 0;
2422         rxq->pkt_first_seg = NULL;
2423         rxq->pkt_last_seg = NULL;
2424
2425         rxq->rxrearm_start = 0;
2426         rxq->rxrearm_nb = 0;
2427 }
2428
2429 void
2430 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2431 {
2432         struct rte_eth_dev *dev;
2433         uint16_t i;
2434
2435         if (!txq || !txq->sw_ring) {
2436                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
2437                 return;
2438         }
2439
2440         dev = &rte_eth_devices[txq->port_id];
2441
2442         /**
2443          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2444          *  so need to free remains more carefully.
2445          */
2446         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2447                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2448                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2449                 if (txq->tx_tail < i) {
2450                         for (; i < txq->nb_tx_desc; i++) {
2451                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2452                                 txq->sw_ring[i].mbuf = NULL;
2453                         }
2454                         i = 0;
2455                 }
2456                 for (; i < txq->tx_tail; i++) {
2457                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2458                         txq->sw_ring[i].mbuf = NULL;
2459                 }
2460         } else {
2461                 for (i = 0; i < txq->nb_tx_desc; i++) {
2462                         if (txq->sw_ring[i].mbuf) {
2463                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2464                                 txq->sw_ring[i].mbuf = NULL;
2465                         }
2466                 }
2467         }
2468 }
2469
2470 void
2471 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2472 {
2473         struct i40e_tx_entry *txe;
2474         uint16_t i, prev, size;
2475
2476         if (!txq) {
2477                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2478                 return;
2479         }
2480
2481         txe = txq->sw_ring;
2482         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2483         for (i = 0; i < size; i++)
2484                 ((volatile char *)txq->tx_ring)[i] = 0;
2485
2486         prev = (uint16_t)(txq->nb_tx_desc - 1);
2487         for (i = 0; i < txq->nb_tx_desc; i++) {
2488                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2489
2490                 txd->cmd_type_offset_bsz =
2491                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2492                 txe[i].mbuf =  NULL;
2493                 txe[i].last_id = i;
2494                 txe[prev].next_id = i;
2495                 prev = i;
2496         }
2497
2498         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2499         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2500
2501         txq->tx_tail = 0;
2502         txq->nb_tx_used = 0;
2503
2504         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2505         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2506 }
2507
2508 /* Init the TX queue in hardware */
2509 int
2510 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2511 {
2512         enum i40e_status_code err = I40E_SUCCESS;
2513         struct i40e_vsi *vsi = txq->vsi;
2514         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2515         uint16_t pf_q = txq->reg_idx;
2516         struct i40e_hmc_obj_txq tx_ctx;
2517         uint32_t qtx_ctl;
2518
2519         /* clear the context structure first */
2520         memset(&tx_ctx, 0, sizeof(tx_ctx));
2521         tx_ctx.new_context = 1;
2522         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2523         tx_ctx.qlen = txq->nb_tx_desc;
2524
2525 #ifdef RTE_LIBRTE_IEEE1588
2526         tx_ctx.timesync_ena = 1;
2527 #endif
2528         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2529         if (vsi->type == I40E_VSI_FDIR)
2530                 tx_ctx.fd_ena = TRUE;
2531
2532         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2533         if (err != I40E_SUCCESS) {
2534                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2535                 return err;
2536         }
2537
2538         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2539         if (err != I40E_SUCCESS) {
2540                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2541                 return err;
2542         }
2543
2544         /* Now associate this queue with this PCI function */
2545         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2546         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2547                                         I40E_QTX_CTL_PF_INDX_MASK);
2548         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2549         I40E_WRITE_FLUSH(hw);
2550
2551         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2552
2553         return err;
2554 }
2555
2556 int
2557 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2558 {
2559         struct i40e_rx_entry *rxe = rxq->sw_ring;
2560         uint64_t dma_addr;
2561         uint16_t i;
2562
2563         for (i = 0; i < rxq->nb_rx_desc; i++) {
2564                 volatile union i40e_rx_desc *rxd;
2565                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2566
2567                 if (unlikely(!mbuf)) {
2568                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2569                         return -ENOMEM;
2570                 }
2571
2572                 rte_mbuf_refcnt_set(mbuf, 1);
2573                 mbuf->next = NULL;
2574                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2575                 mbuf->nb_segs = 1;
2576                 mbuf->port = rxq->port_id;
2577
2578                 dma_addr =
2579                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2580
2581                 rxd = &rxq->rx_ring[i];
2582                 rxd->read.pkt_addr = dma_addr;
2583                 rxd->read.hdr_addr = 0;
2584 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2585                 rxd->read.rsvd1 = 0;
2586                 rxd->read.rsvd2 = 0;
2587 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2588
2589                 rxe[i].mbuf = mbuf;
2590         }
2591
2592         return 0;
2593 }
2594
2595 /*
2596  * Calculate the buffer length, and check the jumbo frame
2597  * and maximum packet length.
2598  */
2599 static int
2600 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2601 {
2602         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2603         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2604         struct rte_eth_dev_data *data = pf->dev_data;
2605         uint16_t buf_size, len;
2606
2607         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2608                 RTE_PKTMBUF_HEADROOM);
2609
2610         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2611                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2612         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2613                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2614                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2615                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2616                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2617                 rxq->hs_mode = i40e_header_split_enabled;
2618                 break;
2619         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2620         default:
2621                 rxq->rx_hdr_len = 0;
2622                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2623                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2624                 rxq->hs_mode = i40e_header_split_none;
2625                 break;
2626         }
2627
2628         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2629         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2630         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2631                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
2632                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2633                         PMD_DRV_LOG(ERR, "maximum packet length must "
2634                                     "be larger than %u and smaller than %u,"
2635                                     "as jumbo frame is enabled",
2636                                     (uint32_t)RTE_ETHER_MAX_LEN,
2637                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2638                         return I40E_ERR_CONFIG;
2639                 }
2640         } else {
2641                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
2642                         rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
2643                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2644                                     "larger than %u and smaller than %u, "
2645                                     "as jumbo frame is disabled",
2646                                     (uint32_t)RTE_ETHER_MIN_LEN,
2647                                     (uint32_t)RTE_ETHER_MAX_LEN);
2648                         return I40E_ERR_CONFIG;
2649                 }
2650         }
2651
2652         return 0;
2653 }
2654
2655 /* Init the RX queue in hardware */
2656 int
2657 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2658 {
2659         int err = I40E_SUCCESS;
2660         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2661         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2662         uint16_t pf_q = rxq->reg_idx;
2663         uint16_t buf_size;
2664         struct i40e_hmc_obj_rxq rx_ctx;
2665
2666         err = i40e_rx_queue_config(rxq);
2667         if (err < 0) {
2668                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2669                 return err;
2670         }
2671
2672         /* Clear the context structure first */
2673         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2674         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2675         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2676
2677         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2678         rx_ctx.qlen = rxq->nb_rx_desc;
2679 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2680         rx_ctx.dsize = 1;
2681 #endif
2682         rx_ctx.dtype = rxq->hs_mode;
2683         if (rxq->hs_mode)
2684                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2685         else
2686                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2687         rx_ctx.rxmax = rxq->max_pkt_len;
2688         rx_ctx.tphrdesc_ena = 1;
2689         rx_ctx.tphwdesc_ena = 1;
2690         rx_ctx.tphdata_ena = 1;
2691         rx_ctx.tphhead_ena = 1;
2692         rx_ctx.lrxqthresh = 2;
2693         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2694         rx_ctx.l2tsel = 1;
2695         /* showiv indicates if inner VLAN is stripped inside of tunnel
2696          * packet. When set it to 1, vlan information is stripped from
2697          * the inner header, but the hardware does not put it in the
2698          * descriptor. So set it zero by default.
2699          */
2700         rx_ctx.showiv = 0;
2701         rx_ctx.prefena = 1;
2702
2703         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2704         if (err != I40E_SUCCESS) {
2705                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2706                 return err;
2707         }
2708         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2709         if (err != I40E_SUCCESS) {
2710                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2711                 return err;
2712         }
2713
2714         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2715
2716         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2717                 RTE_PKTMBUF_HEADROOM);
2718
2719         /* Check if scattered RX needs to be used. */
2720         if (rxq->max_pkt_len > buf_size)
2721                 dev_data->scattered_rx = 1;
2722
2723         /* Init the RX tail regieter. */
2724         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2725
2726         return 0;
2727 }
2728
2729 void
2730 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2731 {
2732         uint16_t i;
2733
2734         PMD_INIT_FUNC_TRACE();
2735
2736         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2737                 if (!dev->data->tx_queues[i])
2738                         continue;
2739                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2740                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2741         }
2742
2743         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2744                 if (!dev->data->rx_queues[i])
2745                         continue;
2746                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2747                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2748         }
2749 }
2750
2751 void
2752 i40e_dev_free_queues(struct rte_eth_dev *dev)
2753 {
2754         uint16_t i;
2755
2756         PMD_INIT_FUNC_TRACE();
2757
2758         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2759                 if (!dev->data->rx_queues[i])
2760                         continue;
2761                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2762                 dev->data->rx_queues[i] = NULL;
2763         }
2764
2765         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2766                 if (!dev->data->tx_queues[i])
2767                         continue;
2768                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2769                 dev->data->tx_queues[i] = NULL;
2770         }
2771 }
2772
2773 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2774 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2775
2776 enum i40e_status_code
2777 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2778 {
2779         struct i40e_tx_queue *txq;
2780         const struct rte_memzone *tz = NULL;
2781         uint32_t ring_size;
2782         struct rte_eth_dev *dev;
2783
2784         if (!pf) {
2785                 PMD_DRV_LOG(ERR, "PF is not available");
2786                 return I40E_ERR_BAD_PTR;
2787         }
2788
2789         dev = pf->adapter->eth_dev;
2790
2791         /* Allocate the TX queue data structure. */
2792         txq = rte_zmalloc_socket("i40e fdir tx queue",
2793                                   sizeof(struct i40e_tx_queue),
2794                                   RTE_CACHE_LINE_SIZE,
2795                                   SOCKET_ID_ANY);
2796         if (!txq) {
2797                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2798                                         "tx queue structure.");
2799                 return I40E_ERR_NO_MEMORY;
2800         }
2801
2802         /* Allocate TX hardware ring descriptors. */
2803         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2804         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2805
2806         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2807                                       I40E_FDIR_QUEUE_ID, ring_size,
2808                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2809         if (!tz) {
2810                 i40e_dev_tx_queue_release(txq);
2811                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2812                 return I40E_ERR_NO_MEMORY;
2813         }
2814
2815         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2816         txq->queue_id = I40E_FDIR_QUEUE_ID;
2817         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2818         txq->vsi = pf->fdir.fdir_vsi;
2819
2820         txq->tx_ring_phys_addr = tz->iova;
2821         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2822         /*
2823          * don't need to allocate software ring and reset for the fdir
2824          * program queue just set the queue has been configured.
2825          */
2826         txq->q_set = TRUE;
2827         pf->fdir.txq = txq;
2828
2829         return I40E_SUCCESS;
2830 }
2831
2832 enum i40e_status_code
2833 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2834 {
2835         struct i40e_rx_queue *rxq;
2836         const struct rte_memzone *rz = NULL;
2837         uint32_t ring_size;
2838         struct rte_eth_dev *dev;
2839
2840         if (!pf) {
2841                 PMD_DRV_LOG(ERR, "PF is not available");
2842                 return I40E_ERR_BAD_PTR;
2843         }
2844
2845         dev = pf->adapter->eth_dev;
2846
2847         /* Allocate the RX queue data structure. */
2848         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2849                                   sizeof(struct i40e_rx_queue),
2850                                   RTE_CACHE_LINE_SIZE,
2851                                   SOCKET_ID_ANY);
2852         if (!rxq) {
2853                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2854                                         "rx queue structure.");
2855                 return I40E_ERR_NO_MEMORY;
2856         }
2857
2858         /* Allocate RX hardware ring descriptors. */
2859         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2860         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2861
2862         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2863                                       I40E_FDIR_QUEUE_ID, ring_size,
2864                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2865         if (!rz) {
2866                 i40e_dev_rx_queue_release(rxq);
2867                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2868                 return I40E_ERR_NO_MEMORY;
2869         }
2870
2871         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2872         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2873         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2874         rxq->vsi = pf->fdir.fdir_vsi;
2875
2876         rxq->rx_ring_phys_addr = rz->iova;
2877         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2878         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2879
2880         /*
2881          * Don't need to allocate software ring and reset for the fdir
2882          * rx queue, just set the queue has been configured.
2883          */
2884         rxq->q_set = TRUE;
2885         pf->fdir.rxq = rxq;
2886
2887         return I40E_SUCCESS;
2888 }
2889
2890 void
2891 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2892         struct rte_eth_rxq_info *qinfo)
2893 {
2894         struct i40e_rx_queue *rxq;
2895
2896         rxq = dev->data->rx_queues[queue_id];
2897
2898         qinfo->mp = rxq->mp;
2899         qinfo->scattered_rx = dev->data->scattered_rx;
2900         qinfo->nb_desc = rxq->nb_rx_desc;
2901
2902         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2903         qinfo->conf.rx_drop_en = rxq->drop_en;
2904         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2905         qinfo->conf.offloads = rxq->offloads;
2906 }
2907
2908 void
2909 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2910         struct rte_eth_txq_info *qinfo)
2911 {
2912         struct i40e_tx_queue *txq;
2913
2914         txq = dev->data->tx_queues[queue_id];
2915
2916         qinfo->nb_desc = txq->nb_tx_desc;
2917
2918         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2919         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2920         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2921
2922         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2923         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2924         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2925         qinfo->conf.offloads = txq->offloads;
2926 }
2927
2928 static eth_rx_burst_t
2929 i40e_get_latest_rx_vec(bool scatter)
2930 {
2931 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2932         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
2933                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2934                                  i40e_recv_pkts_vec_avx2;
2935 #endif
2936         return scatter ? i40e_recv_scattered_pkts_vec :
2937                          i40e_recv_pkts_vec;
2938 }
2939
2940 static eth_rx_burst_t
2941 i40e_get_recommend_rx_vec(bool scatter)
2942 {
2943 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2944         /*
2945          * since AVX frequency can be different to base frequency, limit
2946          * use of AVX2 version to later plaforms, not all those that could
2947          * theoretically run it.
2948          */
2949         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2950                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2951                                  i40e_recv_pkts_vec_avx2;
2952 #endif
2953         return scatter ? i40e_recv_scattered_pkts_vec :
2954                          i40e_recv_pkts_vec;
2955 }
2956
2957 void __attribute__((cold))
2958 i40e_set_rx_function(struct rte_eth_dev *dev)
2959 {
2960         struct i40e_adapter *ad =
2961                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2962         uint16_t rx_using_sse, i;
2963         /* In order to allow Vector Rx there are a few configuration
2964          * conditions to be met and Rx Bulk Allocation should be allowed.
2965          */
2966         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2967                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2968                     !ad->rx_bulk_alloc_allowed) {
2969                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2970                                      " Vector Rx preconditions",
2971                                      dev->data->port_id);
2972
2973                         ad->rx_vec_allowed = false;
2974                 }
2975                 if (ad->rx_vec_allowed) {
2976                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2977                                 struct i40e_rx_queue *rxq =
2978                                         dev->data->rx_queues[i];
2979
2980                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2981                                         ad->rx_vec_allowed = false;
2982                                         break;
2983                                 }
2984                         }
2985                 }
2986         }
2987
2988         if (ad->rx_vec_allowed) {
2989                 /* Vec Rx path */
2990                 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
2991                                 dev->data->port_id);
2992                 if (ad->use_latest_vec)
2993                         dev->rx_pkt_burst =
2994                         i40e_get_latest_rx_vec(dev->data->scattered_rx);
2995                 else
2996                         dev->rx_pkt_burst =
2997                         i40e_get_recommend_rx_vec(dev->data->scattered_rx);
2998         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
2999                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3000                                     "satisfied. Rx Burst Bulk Alloc function "
3001                                     "will be used on port=%d.",
3002                              dev->data->port_id);
3003
3004                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3005         } else {
3006                 /* Simple Rx Path. */
3007                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
3008                              dev->data->port_id);
3009                 dev->rx_pkt_burst = dev->data->scattered_rx ?
3010                                         i40e_recv_scattered_pkts :
3011                                         i40e_recv_pkts;
3012         }
3013
3014         /* Propagate information about RX function choice through all queues. */
3015         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3016                 rx_using_sse =
3017                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3018                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3019                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3020                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3021
3022                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3023                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3024
3025                         if (rxq)
3026                                 rxq->rx_using_sse = rx_using_sse;
3027                 }
3028         }
3029 }
3030
3031 void __attribute__((cold))
3032 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3033 {
3034         struct i40e_adapter *ad =
3035                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3036
3037         /* Use a simple Tx queue if possible (only fast free is allowed) */
3038         ad->tx_simple_allowed =
3039                 (txq->offloads ==
3040                  (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3041                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3042         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3043                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3044
3045         if (ad->tx_vec_allowed)
3046                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3047                                 txq->queue_id);
3048         else if (ad->tx_simple_allowed)
3049                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3050                                 txq->queue_id);
3051         else
3052                 PMD_INIT_LOG(DEBUG,
3053                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3054                                 txq->queue_id);
3055 }
3056
3057 static eth_tx_burst_t
3058 i40e_get_latest_tx_vec(void)
3059 {
3060 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3061         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3062                 return i40e_xmit_pkts_vec_avx2;
3063 #endif
3064         return i40e_xmit_pkts_vec;
3065 }
3066
3067 static eth_tx_burst_t
3068 i40e_get_recommend_tx_vec(void)
3069 {
3070 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3071         /*
3072          * since AVX frequency can be different to base frequency, limit
3073          * use of AVX2 version to later plaforms, not all those that could
3074          * theoretically run it.
3075          */
3076         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3077                 return i40e_xmit_pkts_vec_avx2;
3078 #endif
3079         return i40e_xmit_pkts_vec;
3080 }
3081
3082 void __attribute__((cold))
3083 i40e_set_tx_function(struct rte_eth_dev *dev)
3084 {
3085         struct i40e_adapter *ad =
3086                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3087         int i;
3088
3089         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3090                 if (ad->tx_vec_allowed) {
3091                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3092                                 struct i40e_tx_queue *txq =
3093                                         dev->data->tx_queues[i];
3094
3095                                 if (txq && i40e_txq_vec_setup(txq)) {
3096                                         ad->tx_vec_allowed = false;
3097                                         break;
3098                                 }
3099                         }
3100                 }
3101         }
3102
3103         if (ad->tx_simple_allowed) {
3104                 if (ad->tx_vec_allowed) {
3105                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3106                         if (ad->use_latest_vec)
3107                                 dev->tx_pkt_burst =
3108                                         i40e_get_latest_tx_vec();
3109                         else
3110                                 dev->tx_pkt_burst =
3111                                         i40e_get_recommend_tx_vec();
3112                 } else {
3113                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3114                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3115                 }
3116                 dev->tx_pkt_prepare = NULL;
3117         } else {
3118                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3119                 dev->tx_pkt_burst = i40e_xmit_pkts;
3120                 dev->tx_pkt_prepare = i40e_prep_pkts;
3121         }
3122 }
3123
3124 void __attribute__((cold))
3125 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3126 {
3127         struct i40e_adapter *ad =
3128                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3129         int i;
3130
3131         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3132                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3133 }
3134
3135 void __attribute__((cold))
3136 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3137 {
3138         struct i40e_adapter *ad =
3139                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3140         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3141         int i;
3142
3143         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3144                 ad->pctypes_tbl[i] = 0ULL;
3145         ad->flow_types_mask = 0ULL;
3146         ad->pctypes_mask = 0ULL;
3147
3148         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3149                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3150         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3151                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3152         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3153                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3154         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3155                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3156         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3157                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3158         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3159                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3160         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3161                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3162         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3163                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3164         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3165                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3166         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3167                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3168         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3169                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3170
3171         if (hw->mac.type == I40E_MAC_X722 ||
3172                 hw->mac.type == I40E_MAC_X722_VF) {
3173                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3174                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3175                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3176                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3177                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3178                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3179                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3180                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3181                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3182                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3183                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3184                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3185         }
3186
3187         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3188                 if (ad->pctypes_tbl[i])
3189                         ad->flow_types_mask |= (1ULL << i);
3190                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3191         }
3192 }
3193
3194 #ifndef RTE_LIBRTE_I40E_INC_VECTOR
3195 /* Stubs needed for linkage when CONFIG_RTE_LIBRTE_I40E_INC_VECTOR is set to 'n' */
3196 int
3197 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3198 {
3199         return -1;
3200 }
3201
3202 uint16_t
3203 i40e_recv_pkts_vec(
3204         void __rte_unused *rx_queue,
3205         struct rte_mbuf __rte_unused **rx_pkts,
3206         uint16_t __rte_unused nb_pkts)
3207 {
3208         return 0;
3209 }
3210
3211 uint16_t
3212 i40e_recv_scattered_pkts_vec(
3213         void __rte_unused *rx_queue,
3214         struct rte_mbuf __rte_unused **rx_pkts,
3215         uint16_t __rte_unused nb_pkts)
3216 {
3217         return 0;
3218 }
3219
3220 int
3221 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3222 {
3223         return -1;
3224 }
3225
3226 int
3227 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3228 {
3229         return -1;
3230 }
3231
3232 void
3233 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3234 {
3235         return;
3236 }
3237
3238 uint16_t
3239 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3240                           struct rte_mbuf __rte_unused **tx_pkts,
3241                           uint16_t __rte_unused nb_pkts)
3242 {
3243         return 0;
3244 }
3245 #endif /* ifndef RTE_LIBRTE_I40E_INC_VECTOR */
3246
3247 #ifndef CC_AVX2_SUPPORT
3248 uint16_t
3249 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3250                         struct rte_mbuf __rte_unused **rx_pkts,
3251                         uint16_t __rte_unused nb_pkts)
3252 {
3253         return 0;
3254 }
3255
3256 uint16_t
3257 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3258                         struct rte_mbuf __rte_unused **rx_pkts,
3259                         uint16_t __rte_unused nb_pkts)
3260 {
3261         return 0;
3262 }
3263
3264 uint16_t
3265 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3266                           struct rte_mbuf __rte_unused **tx_pkts,
3267                           uint16_t __rte_unused nb_pkts)
3268 {
3269         return 0;
3270 }
3271 #endif /* ifndef CC_AVX2_SUPPORT */